Changeset 70 for GPL/trunk/alsa-kernel/pci/intel8x0.c
- Timestamp:
- Jan 14, 2006, 6:38:48 PM (20 years ago)
- File:
-
- 1 edited
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GPL/trunk/alsa-kernel/pci/intel8x0.c
r64 r70 260 260 #define ICH_SAMPLE_16_20 0x00400000 /* ICH4: 16- and 20-bit samples */ 261 261 #define ICH_MULTICHAN_CAP 0x00300000 /* ICH4: multi-channel capability bits (RO) */ 262 #define ICH_SIS_TRI 0x00080000 /* SIS: tertiary resume irq */ 263 #define ICH_SIS_TCR 0x00040000 /* SIS: tertiary codec ready */ 262 264 #define ICH_MD3 0x00020000 /* modem power down semaphore */ 263 265 #define ICH_AD3 0x00010000 /* audio power down semaphore */ … … 457 459 ac97_t *ac97[3]; 458 460 unsigned int ac97_sdin[3]; 461 unsigned int max_codecs, ncodecs; 462 unsigned int *codec_bit; 463 unsigned int codec_isr_bits; 464 unsigned int codec_ready_bits; 459 465 460 466 snd_rawmidi_t *rmidi; … … 577 583 */ 578 584 579 /* return the GLOB_STA bit for the corresponding codec */580 static unsigned int get_ich_codec_bit(struct intel8x0 *chip, unsigned int codec)581 {582 static unsigned int codec_bit[3] = {583 ICH_PCR, ICH_SCR, ICH_TCR584 };585 snd_assert(codec < 3, return ICH_PCR);586 if (chip->device_type == DEVICE_INTEL_ICH4 ||587 chip->device_type == DEVICE_INTEL_ICH5)588 codec = chip->ac97_sdin[codec];589 return codec_bit[codec];590 }591 592 585 static int snd_intel8x0_codec_semaphore(struct intel8x0 *chip, unsigned int codec) 593 586 { … … 599 592 /* we don't know the ready bit assignment at the moment */ 600 593 /* so we check any */ 601 codec = ICH_PCR | ICH_SCR | ICH_TCR;594 codec = chip->codec_isr_bits; 602 595 } else { 603 codec = get_ich_codec_bit(chip, codec);596 codec = chip->codec_bit[chip->ac97_sdin[codec]]; 604 597 } 605 598 … … 654 647 if ((tmp = igetdword(chip, ICHREG(GLOB_STA))) & ICH_RCS) { 655 648 /* reset RCS and preserve other R/WC bits */ 656 iputdword(chip, ICHREG(GLOB_STA), tmp & ~( ICH_SRI|ICH_PRI|ICH_TRI|ICH_GSCI));649 iputdword(chip, ICHREG(GLOB_STA), tmp & ~(chip->codec_ready_bits | ICH_GSCI)); 657 650 if (! chip->in_ac97_init) 658 651 snd_printk("codec_read %d: read timeout for register 0x%x\n", ac97->num, reg); … … 663 656 } 664 657 665 static void snd_intel8x0_codec_read_test(struct intel8x0 *chip, unsigned int codec) 658 static void __devinit snd_intel8x0_codec_read_test(struct intel8x0 *chip, 659 unsigned int codec) 666 660 { 667 661 unsigned int tmp; … … 671 665 if ((tmp = igetdword(chip, ICHREG(GLOB_STA))) & ICH_RCS) { 672 666 /* reset RCS and preserve other R/WC bits */ 673 iputdword(chip, ICHREG(GLOB_STA), tmp & ~( ICH_SRI|ICH_PRI|ICH_TRI|ICH_GSCI));667 iputdword(chip, ICHREG(GLOB_STA), tmp & ~(chip->codec_ready_bits | ICH_GSCI)); 674 668 } 675 669 } … … 1822 1816 }, 1823 1817 { 1824 .subvendor = 0x1028, 1818 .subvendor = 0x1028, 1819 .subdevice = 0x0151, 1820 .name = "Dell Optiplex GX270", /* AD1981B */ 1821 .type = AC97_TUNE_HP_ONLY 1822 }, 1823 { 1824 .subvendor = 0x1028, 1825 1825 .subdevice = 0x0163, 1826 1826 .name = "Dell Unknown", /* STAC9750/51 */ … … 1862 1862 .name = "HP nx8220", 1863 1863 .type = AC97_TUNE_MUTE_LED 1864 },1865 {1866 .subvendor = 0x103c,1867 .subdevice = 0x099c,1868 .name = "HP nx6110", /* AD1981B */1869 .type = AC97_TUNE_HP_ONLY1870 1864 }, 1871 1865 { … … 1890 1884 .subvendor = 0x103c, 1891 1885 .subdevice = 0x0944, 1892 .name = "HP n c6220",1886 .name = "HP nx6110/nc6120", 1893 1887 .type = AC97_TUNE_HP_MUTE_LED 1894 1888 }, … … 2092 2086 glob_sta = igetdword(chip, ICHREG(GLOB_STA)); 2093 2087 ops = &standard_bus_ops; 2094 if (chip->device_type == DEVICE_INTEL_ICH4 || 2095 chip->device_type == DEVICE_INTEL_ICH5) { 2096 codecs = 0; 2097 if (glob_sta & ICH_PCR) 2098 codecs++; 2099 if (glob_sta & ICH_SCR) 2100 codecs++; 2101 if (glob_sta & ICH_TCR) 2102 codecs++; 2088 chip->in_sdin_init = 1; 2089 codecs = 0; 2090 for (i = 0; i < chip->max_codecs; i++) { 2091 if (! (glob_sta & chip->codec_bit[i])) 2092 continue; 2093 if (chip->device_type == DEVICE_INTEL_ICH4 || 2094 chip->device_type == DEVICE_INTEL_ICH5) { 2095 snd_intel8x0_codec_read_test(chip, codecs); 2096 chip->ac97_sdin[codecs] = 2097 igetbyte(chip, ICHREG(SDM)) & ICH_LDI_MASK; 2098 snd_assert(chip->ac97_sdin[codecs] < 3, 2099 chip->ac97_sdin[codecs] = 0); 2100 } else 2101 chip->ac97_sdin[codecs] = i; 2102 codecs++; 2103 2103 chip->in_sdin_init = 1; 2104 #if 1 //vladest 06.10.2003 15:55 - bull shit!!! it doesnt works here 2105 for (i = 0; i < codecs; i++) { 2106 printk("codec %i read test begins...", i); 2107 snd_intel8x0_codec_read_test(chip, i); 2108 chip->ac97_sdin[i] = igetbyte(chip, ICHREG(SDM)) & ICH_LDI_MASK; 2109 printk("finished\n"); 2110 } 2111 #endif 2112 chip->in_sdin_init = 0; 2113 } else { 2114 codecs = glob_sta & ICH_SCR ? 2 : 1; 2115 } 2104 } 2105 chip->in_sdin_init = 0; 2106 if (! codecs) 2107 codecs = 1; 2116 2108 } else { 2117 2109 ops = &ali_bus_ops; … … 2131 2123 goto __err; 2132 2124 pbus->private_free = snd_intel8x0_mixer_free_ac97_bus; 2133 pbus->shared_type = AC97_SHARED_TYPE_ICH; /* shared with modem driver */2134 2125 if (ac97_clock >= 8000 && ac97_clock <= 48000) 2135 2126 pbus->clock = ac97_clock; … … 2140 2131 pbus->dra = 1; 2141 2132 chip->ac97_bus = pbus; 2133 chip->ncodecs = codecs; 2142 2134 2143 2135 ac97.pci = chip->pci; … … 2320 2312 i = 0; 2321 2313 do { 2322 status = igetdword(chip, ICHREG(GLOB_STA)) & (ICH_PCR | ICH_SCR | ICH_TCR);2314 status = igetdword(chip, ICHREG(GLOB_STA)) & chip->codec_isr_bits;; 2323 2315 if (status) 2324 2316 break; … … 2338 2330 // mdelay(50); 2339 2331 2340 if (chip->device_type == DEVICE_INTEL_ICH4 ||2341 chip->device_type == DEVICE_INTEL_ICH5)2342 /* ICH4 can have three codecs */2343 nstatus = ICH_PCR | ICH_SCR | ICH_TCR;2344 else2345 /* others up to two codecs */2346 nstatus = ICH_PCR | ICH_SCR;2347 2332 /* wait for other codecs ready status. */ 2348 2333 end_time = jiffies + HZ / 4; 2349 while (status != nstatus && time_after_eq(end_time, jiffies)) { 2334 while (status != chip->codec_isr_bits && 2335 time_after_eq(end_time, jiffies)) { 2350 2336 do_delay(chip); 2351 status |= igetdword(chip, ICHREG(GLOB_STA)) & nstatus; 2337 status |= igetdword(chip, ICHREG(GLOB_STA)) & 2338 chip->codec_isr_bits; 2352 2339 } 2353 2340 } else { … … 2355 2342 int i; 2356 2343 status = 0; 2357 for (i = 0; i < 3; i++)2344 for (i = 0; i < chip->ncodecs; i++) 2358 2345 if (chip->ac97[i]) 2359 status |= get_ich_codec_bit(chip, i);2346 status |= chip->codec_bit[chip->ac97_sdin[i]]; 2360 2347 /* wait until all the probed codecs are ready */ 2361 2348 end_time = jiffies + HZ; 2362 2349 do { 2363 nstatus = igetdword(chip, ICHREG(GLOB_STA)) & (ICH_PCR | ICH_SCR | ICH_TCR);2350 nstatus = igetdword(chip, ICHREG(GLOB_STA)) & chip->codec_isr_bits;; 2364 2351 if (status == nstatus) 2365 2352 break; … … 2497 2484 snd_pcm_suspend_all(chip->pcm[i]); 2498 2485 2499 for (i = 0; i < 3; i++)2486 for (i = 0; i < chip->ncodecs; i++) 2500 2487 if (chip->ac97[i]) //Rudi: check, if codec present !!! 2501 2488 snd_ac97_suspend(chip->ac97[i]); … … 2536 2523 } 2537 2524 2538 for (i = 0; i < 3; i++)2525 for (i = 0; i < chip->ncodecs; i++) 2539 2526 if (chip->ac97[i]) //Rudi: check, if codec present !!! 2540 2527 snd_ac97_resume(chip->ac97[i]); … … 2655 2642 chip->device_type == DEVICE_INTEL_ICH5) 2656 2643 snd_iprintf(buffer, "SDM : 0x%08x\n", igetdword(chip, ICHREG(SDM))); 2657 snd_iprintf(buffer, "AC'97 codecs ready :%s%s%s%s\n", 2658 tmp & ICH_PCR ? " primary" : "", 2659 tmp & ICH_SCR ? " secondary" : "", 2660 tmp & ICH_TCR ? " tertiary" : "", 2661 (tmp & (ICH_PCR | ICH_SCR | ICH_TCR)) == 0 ? " none" : ""); 2644 snd_iprintf(buffer, "AC'97 codecs ready :"); 2645 if (tmp & chip->codec_isr_bits) { 2646 int i; 2647 static const char *codecs[3] = { 2648 "primary", "secondary", "tertiary" 2649 }; 2650 for (i = 0; i < chip->max_codecs; i++) 2651 if (tmp & chip->codec_bit[i]) 2652 snd_iprintf(buffer, " %s", codecs[i]); 2653 } else 2654 snd_iprintf(buffer, " none"); 2655 snd_iprintf(buffer, "\n"); 2662 2656 if (chip->device_type == DEVICE_INTEL_ICH4 || 2663 chip->device_type == DEVICE_INTEL_ICH5)2657 chip->device_type == DEVICE_SIS) 2664 2658 snd_iprintf(buffer, "AC'97 codecs SDIN : %i %i %i\n", 2665 2659 chip->ac97_sdin[0], … … 2690 2684 }; 2691 2685 2686 static unsigned int ich_codec_bits[3] = { 2687 ICH_PCR, ICH_SCR, ICH_TCR 2688 }; 2689 static unsigned int sis_codec_bits[3] = { 2690 ICH_PCR, ICH_SCR, ICH_SIS_TCR 2691 }; 2692 2692 2693 2693 static int __devinit snd_intel8x0_create(snd_card_t * card, … … 2929 2929 synchronize_irq(chip->irq); 2930 2930 2931 switch(chip->device_type) { 2932 case DEVICE_INTEL_ICH4: 2933 case DEVICE_INTEL_ICH5: 2934 /* ICH4/5 can have three codecs */ 2935 chip->max_codecs = 3; 2936 chip->codec_bit = ich_codec_bits; 2937 chip->codec_ready_bits = ICH_PRI | ICH_SRI | ICH_TRI; 2938 break; 2939 case DEVICE_SIS: 2940 /* recent SIS7012 can have three codecs */ 2941 chip->max_codecs = 3; 2942 chip->codec_bit = sis_codec_bits; 2943 chip->codec_ready_bits = ICH_PRI | ICH_SRI | ICH_SIS_TRI; 2944 break; 2945 default: 2946 /* others up to two codecs */ 2947 chip->max_codecs = 2; 2948 chip->codec_bit = ich_codec_bits; 2949 chip->codec_ready_bits = ICH_PRI | ICH_SRI; 2950 break; 2951 } 2952 for (i = 0; i < chip->max_codecs; i++) 2953 chip->codec_isr_bits |= chip->codec_bit[i]; 2954 2931 2955 if ((err = snd_intel8x0_chip_init(chip, 1)) < 0) { 2932 2956 snd_intel8x0_free(chip);
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