Changeset 76 for GPL/trunk/alsa-kernel/pci/intel8x0.c

Timestamp:

Apr 9, 2006, 12:09:39 PM (19 years ago)

Author:

vladest

Message:

Latest ALSA patches
HDA patches
Patch for Intel from Rudy's
Fixes locks on NM256 chipsets
Fixes PM on Maestro3 chipsets

File:

• GPL/trunk/alsa-kernel/pci/intel8x0.c (modified) (11 diffs)

GPL/trunk/alsa-kernel/pci/intel8x0.c

@@ -494 +494 @@
     { 0x10de, 0x00da, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE },    /* NFORCE3 */
     { 0x10de, 0x00ea, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE },        /* CK8S */
+    { 0x10de, 0x026b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE },        /* MCP51 */
     { 0x1022, 0x746d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL },     /* AMD8111 */
     { 0x1022, 0x7445, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL },     /* AMD768 */
@@ -834 +835 @@
     unsigned int status;
     unsigned int i;
+#ifdef TARGET_OS2
+    int fOurIrq = FALSE;
+#endif
 
     status = igetdword(chip, chip->int_sta_reg);
@@ -854 +858 @@
 #endif
         }
-        return IRQ_RETVAL(status);
-    }
+        return IRQ_NONE/*RETVAL(status)*/;
+    }
+#ifdef TARGET_OS2
+    fOurIrq = TRUE;
+#endif
 
     for (i = 0; i < chip->bdbars_count; i++) {
@@ -865 +872 @@
     /* ack them */
     iputdword(chip, chip->int_sta_reg, status & chip->int_sta_mask);
+#ifdef TARGET_OS2
+    if (fOurIrq) {
+        //eoi_irq(irq);
+    }
+#endif //TARGET_OS2
 
     return IRQ_HANDLED;
@@ -1161 +1173 @@
         runtime->hw.period_bytes_max = 64*1024;
     }
+#if 1 /* vladest */
     if ((err = snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS)) < 0)
         return err;
+#endif
     runtime->private_data = ichdev;
     return 0;
@@ -1175 +1189 @@
     err = snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_PCMOUT]);
     if (err < 0)
+    {
+        printk("snd_intel8x0_pcm_open open error: %i\n", err);
         return err;
+    }
     if (chip->multi6) {
         runtime->hw.channels_max = 6;
@@ -1988 +2005 @@
                 .name = "Fujitsu-Siemens D1522",        /* AD1981 */
                 .type = AC97_TUNE_HP_ONLY
-        },
+        },
+        {
+            .subvendor = 0x8086,
+            .subdevice = 0x0104,
+            .name = "Intel D845GEBV2",              /* AD1981B */
+            .type = AC97_TUNE_HP_ONLY
+        },
         {
                 .subvendor = 0x8086,
@@ -2310 +2333 @@
          */
         end_time = jiffies + HZ;
-        i = 0;
         do {
-            status = igetdword(chip, ICHREG(GLOB_STA)) & chip->codec_isr_bits;;
+            status = igetdword(chip, ICHREG(GLOB_STA)) &
+                chip->codec_isr_bits;
             if (status)
                 break;
             mdelay(1);
             //do_delay(chip);
-            i++;
-        } while (i<100);/*(time_after_eq(end_time, jiffies));*/
+        } while (time_after_eq(end_time, jiffies));
 
         if (! status) {
@@ -2410 +2432 @@
 static int snd_intel8x0_chip_init(struct intel8x0 *chip, int probing)
 {
-    unsigned int i;
+    unsigned int i, timeout;
     int err;
 
@@ -2428 +2450 @@
     for (i = 0; i < chip->bdbars_count; i++)
         iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, ICH_RESETREGS);
+    for (i = 0; i < chip->bdbars_count; i++) {
+        timeout = 100000;
+        while (--timeout != 0) {
+            if ((igetbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset) & ICH_RESETREGS) == 0)
+                break;
+        }
+        if (timeout == 0)
+            printk(KERN_ERR "intel8x0: reset of registers failed?\n");
+    }
     /* initialize Buffer Descriptor Lists */
     for (i = 0; i < chip->bdbars_count; i++)
@@ -2606 +2637 @@
     iputbyte(chip, port + ICH_REG_OFF_CR, ICH_RESETREGS);
     spin_unlock_irq(&chip->reg_lock);
-
+#if 0
     t = stop_time.tv_sec - start_time.tv_sec;
     t *= 1000000;
     t += stop_time.tv_usec - start_time.tv_usec;
+#else
+    t = 50000; /* patch, suggested by r.ihle */
+#endif
     printk(KERN_INFO "%s: measured %lu usecs\n", __FUNCTION__, t);
     if (t == 0) {