source: GPL/trunk/alsa-kernel/pci/intel8x0.c@ 70

Last change on this file since 70 was 70, checked in by vladest, 20 years ago

Ensonic/Maestro3/VIA/ATI power management fixes
Intel ICH SI7012 fixes
File size: 105.0 KB
Line 
1/*
2 * ALSA driver for Intel ICH (i8x0) chipsets
3 *
4 * Copyright (c) 2000 Jaroslav Kysela <perex@suse.cz>
5 *
6 *
7 * This code also contains alpha support for SiS 735 chipsets provided
8 * by Mike Pieper <mptei@users.sourceforge.net>. We have no datasheet
9 * for SiS735, so the code is not fully functional.
10 *
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
25
26 *
27 */
28
29#include <sound/driver.h>
30#include <asm/io.h>
31#include <linux/delay.h>
32#include <linux/interrupt.h>
33#include <linux/init.h>
34#include <linux/pci.h>
35#include <linux/slab.h>
36#include <sound/core.h>
37#include <sound/pcm.h>
38#include <sound/ac97_codec.h>
39#include <sound/info.h>
40#include <sound/mpu401.h>
41#define SNDRV_GET_ID
42#include <sound/initval.h>
43
44#define I810_DEBUG
45
46MODULE_AUTHOR("Jaroslav Kysela <perex@suse.cz>");
47MODULE_DESCRIPTION("Intel 82801AA,82901AB,i810,i820,i830,i840,i845,MX440; SiS 7012; Ali 5455");
48MODULE_LICENSE("GPL");
49MODULE_CLASSES("{sound}");
50MODULE_DEVICES("{{Intel,82801AA-ICH},"
51 "{Intel,82901AB-ICH0},"
52 "{Intel,82801BA-ICH2},"
53 "{Intel,82801CA-ICH3},"
54 "{Intel,82801DB-ICH4},"
55 "{Intel,ICH5},"
56 "{Intel,ICH6},"
57 "{Intel,ICH7},"
58 "{Intel,6300ESB},"
59 "{Intel,ESB2},"
60 "{Intel,MX440},"
61 "{SiS,SI7012},"
62 "{NVidia,nForce Audio},"
63 "{NVidia,nForce2 Audio},"
64 "{AMD,AMD768},"
65 "{AMD,AMD8111},"
66 "{ALI,M5455}}");
67
68#if defined(CONFIG_GAMEPORT) || (defined(MODULE) && defined(CONFIG_GAMEPORT_MODULE))
69//#define SUPPORT_JOYSTICK 1
70#endif
71#define SUPPORT_MIDI 1
72
73extern int midi_port;
74
75static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
76static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
77static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable this card */
78#ifdef TARGET_OS2
79static int ac97_clock[SNDRV_CARDS] = {REPEAT_SNDRV(0)};
80static char *ac97_quirk[SNDRV_CARDS];
81#else
82static int ac97_clock[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = 0};
83#endif
84#ifdef SUPPORT_JOYSTICK
85static int joystick[SNDRV_CARDS];
86#endif
87#ifdef SUPPORT_MIDI
88static int mpu_port[SNDRV_CARDS];// = {REPEAT_SNDRV(0x330)};;
89/* disabled */
90#endif
91
92static int buggy_semaphore;
93static int buggy_irq = -1; /* auto-check */
94
95MODULE_PARM(index, "1-" __MODULE_STRING(SNDRV_CARDS) "i");
96MODULE_PARM_DESC(index, "Index value for Intel i8x0 soundcard.");
97MODULE_PARM_SYNTAX(index, SNDRV_INDEX_DESC);
98MODULE_PARM(id, "1-" __MODULE_STRING(SNDRV_CARDS) "s");
99MODULE_PARM_DESC(id, "ID string for Intel i8x0 soundcard.");
100MODULE_PARM_SYNTAX(id, SNDRV_ID_DESC);
101MODULE_PARM(enable, "1-" __MODULE_STRING(SNDRV_CARDS) "i");
102MODULE_PARM_DESC(enable, "Enable Intel i8x0 soundcard.");
103MODULE_PARM_SYNTAX(enable, SNDRV_ENABLE_DESC);
104MODULE_PARM(ac97_clock, "1-" __MODULE_STRING(SNDRV_CARDS) "i");
105MODULE_PARM_DESC(ac97_clock, "AC'97 codec clock (0 = auto-detect).");
106MODULE_PARM_SYNTAX(ac97_clock, SNDRV_ENABLED ",default:0");
107MODULE_PARM(ac97_quirk, "1-" __MODULE_STRING(SNDRV_CARDS) "i");
108MODULE_PARM_DESC(ac97_quirk, "AC'97 workaround for strange hardware.");
109MODULE_PARM_SYNTAX(ac97_quirk, SNDRV_ENABLED ",allows:{{-1,3}},dialog:list,default:-1");
110#ifdef SUPPORT_JOYSTICK
111MODULE_PARM(joystick, "1-" __MODULE_STRING(SNDRV_CARDS) "i");
112MODULE_PARM_DESC(joystick, "Enable joystick for Intel i8x0 soundcard.");
113MODULE_PARM_SYNTAX(joystick, SNDRV_ENABLED "," SNDRV_BOOLEAN_FALSE_DESC);
114#endif
115#ifdef SUPPORT_MIDI
116MODULE_PARM(mpu_port, "1-" __MODULE_STRING(SNDRV_CARDS) "i");
117MODULE_PARM_DESC(mpu_port, "MPU401 port # for Intel i8x0 driver.");
118MODULE_PARM_SYNTAX(mpu_port, SNDRV_ENABLED ",allows:{{0},{0x330},{0x300}},dialog:list");
119#endif
120
121/*
122 * Direct registers
123 */
124
125#ifndef PCI_DEVICE_ID_INTEL_82801
126#define PCI_DEVICE_ID_INTEL_82801 0x2415
127#endif
128#ifndef PCI_DEVICE_ID_INTEL_82901
129#define PCI_DEVICE_ID_INTEL_82901 0x2425
130#endif
131#ifndef PCI_DEVICE_ID_INTEL_82801BA
132#define PCI_DEVICE_ID_INTEL_82801BA 0x2445
133#endif
134#ifndef PCI_DEVICE_ID_INTEL_440MX
135#define PCI_DEVICE_ID_INTEL_440MX 0x7195
136#endif
137#ifndef PCI_DEVICE_ID_INTEL_ICH3
138#define PCI_DEVICE_ID_INTEL_ICH3 0x2485
139#endif
140#ifndef PCI_DEVICE_ID_INTEL_ICH4
141#define PCI_DEVICE_ID_INTEL_ICH4 0x24c5
142#endif
143#ifndef PCI_DEVICE_ID_INTEL_ICH5
144#define PCI_DEVICE_ID_INTEL_ICH5 0x24d5
145#endif
146#ifndef PCI_DEVICE_ID_INTEL_ESB_5
147#define PCI_DEVICE_ID_INTEL_ESB_5 0x25a6
148#endif
149#ifndef PCI_DEVICE_ID_INTEL_ICH6_18
150#define PCI_DEVICE_ID_INTEL_ICH6_18 0x266e
151#endif
152#ifndef PCI_DEVICE_ID_INTEL_ICH7_20
153#define PCI_DEVICE_ID_INTEL_ICH7_20 0x27de
154#endif
155#ifndef PCI_DEVICE_ID_INTEL_ESB2_14
156#define PCI_DEVICE_ID_INTEL_ESB2_14 0x2698
157#endif
158#ifndef PCI_DEVICE_ID_SI_7012
159#define PCI_DEVICE_ID_SI_7012 0x7012
160#endif
161#ifndef PCI_DEVICE_ID_NVIDIA_CK804_AUDIO
162#define PCI_DEVICE_ID_NVIDIA_CK804_AUDIO 0x0059
163#endif
164#ifndef PCI_DEVICE_ID_NVIDIA_MCP_AUDIO
165#define PCI_DEVICE_ID_NVIDIA_MCP_AUDIO 0x01b1
166#endif
167#ifndef PCI_DEVICE_ID_NVIDIA_MCP2_AUDIO
168#define PCI_DEVICE_ID_NVIDIA_MCP2_AUDIO 0x006a
169#endif
170#ifndef PCI_DEVICE_ID_NVIDIA_MCP3_AUDIO
171#define PCI_DEVICE_ID_NVIDIA_MCP3_AUDIO 0x00da
172#endif
173#ifndef PCI_DEVICE_ID_NVIDIA_CK8S_AUDIO
174#define PCI_DEVICE_ID_NVIDIA_CK8S_AUDIO 0x00ea
175#endif
176#ifndef PCI_DEVICE_ID_NVIDIA_CK8_AUDIO
177#define PCI_DEVICE_ID_NVIDIA_CK8_AUDIO 0x008a
178#endif
179
180enum { DEVICE_INTEL, DEVICE_INTEL_ICH4, DEVICE_INTEL_ICH5, DEVICE_SIS, DEVICE_ALI, DEVICE_NFORCE };
181
182#define ICHREG(x) ICH_REG_##x
183
184#define DEFINE_REGSET(name,base) \
185 enum { \
186 ICH_REG_##name##_BDBAR = base + 0x0, /* dword - buffer descriptor list base address */ \
187 ICH_REG_##name##_CIV = base + 0x04, /* byte - current index value */ \
188 ICH_REG_##name##_LVI = base + 0x05, /* byte - last valid index */ \
189 ICH_REG_##name##_SR = base + 0x06, /* byte - status register */ \
190 ICH_REG_##name##_PICB = base + 0x08, /* word - position in current buffer */ \
191 ICH_REG_##name##_PIV = base + 0x0a, /* byte - prefetched index value */ \
192 ICH_REG_##name##_CR = base + 0x0b, /* byte - control register */ \
193 };
194
195/* busmaster blocks */
196DEFINE_REGSET(OFF, 0); /* offset */
197DEFINE_REGSET(PI, 0x00); /* PCM in */
198DEFINE_REGSET(PO, 0x10); /* PCM out */
199DEFINE_REGSET(MC, 0x20); /* Mic in */
200
201/* ICH4 busmaster blocks */
202DEFINE_REGSET(MC2, 0x40); /* Mic in 2 */
203DEFINE_REGSET(PI2, 0x50); /* PCM in 2 */
204DEFINE_REGSET(SP, 0x60); /* SPDIF out */
205
206/* values for each busmaster block */
207
208/* LVI */
209#define ICH_REG_LVI_MASK 0x1f
210
211/* SR */
212#define ICH_FIFOE 0x10 /* FIFO error */
213#define ICH_BCIS 0x08 /* buffer completion interrupt status */
214#define ICH_LVBCI 0x04 /* last valid buffer completion interrupt */
215#define ICH_CELV 0x02 /* current equals last valid */
216#define ICH_DCH 0x01 /* DMA controller halted */
217
218/* PIV */
219#define ICH_REG_PIV_MASK 0x1f /* mask */
220
221/* CR */
222#define ICH_IOCE 0x10 /* interrupt on completion enable */
223#define ICH_FEIE 0x08 /* fifo error interrupt enable */
224#define ICH_LVBIE 0x04 /* last valid buffer interrupt enable */
225#define ICH_RESETREGS 0x02 /* reset busmaster registers */
226#define ICH_STARTBM 0x01 /* start busmaster operation */
227
228
229/* global block */
230#define ICH_REG_GLOB_CNT 0x2c /* dword - global control */
231#define ICH_PCM_SPDIF_MASK 0xc0000000 /* s/pdif pcm slot mask (ICH4) */
232#define ICH_PCM_SPDIF_NONE 0x00000000 /* reserved - undefined */
233#define ICH_PCM_SPDIF_78 0x40000000 /* s/pdif pcm on slots 7&8 */
234#define ICH_PCM_SPDIF_69 0x80000000 /* s/pdif pcm on slots 6&9 */
235#define ICH_PCM_SPDIF_1011 0xc0000000 /* s/pdif pcm on slots 10&11 */
236#define ICH_PCM_20BIT 0x00400000 /* 20-bit samples (ICH4) */
237#define ICH_PCM_246_MASK 0x00300000 /* 6 channels (not all chips) */
238#define ICH_PCM_6 0x00200000 /* 6 channels (not all chips) */
239#define ICH_PCM_4 0x00100000 /* 4 channels (not all chips) */
240#define ICH_PCM_2 0x00000000 /* 2 channels (stereo) */
241#define ICH_SIS_PCM_246_MASK 0x000000c0 /* 6 channels (SIS7012) */
242#define ICH_SIS_PCM_6 0x00000080 /* 6 channels (SIS7012) */
243#define ICH_SIS_PCM_4 0x00000040 /* 4 channels (SIS7012) */
244#define ICH_SIS_PCM_2 0x00000000 /* 2 channels (SIS7012) */
245#define ICH_TRIE 0x00000040 /* tertiary resume interrupt enable */
246#define ICH_SRIE 0x00000020 /* secondary resume interrupt enable */
247#define ICH_PRIE 0x00000010 /* primary resume interrupt enable */
248#define ICH_ACLINK 0x00000008 /* AClink shut off */
249#define ICH_AC97WARM 0x00000004 /* AC'97 warm reset */
250#define ICH_AC97COLD 0x00000002 /* AC'97 cold reset */
251#define ICH_GIE 0x00000001 /* GPI interrupt enable */
252#define ICH_REG_GLOB_STA 0x30 /* dword - global status */
253#define ICH_TRI 0x20000000 /* ICH4: tertiary (AC_SDIN2) resume interrupt */
254#define ICH_TCR 0x10000000 /* ICH4: tertiary (AC_SDIN2) codec ready */
255#define ICH_BCS 0x08000000 /* ICH4: bit clock stopped */
256#define ICH_SPINT 0x04000000 /* ICH4: S/PDIF interrupt */
257#define ICH_P2INT 0x02000000 /* ICH4: PCM2-In interrupt */
258#define ICH_M2INT 0x01000000 /* ICH4: Mic2-In interrupt */
259#define ICH_SAMPLE_CAP 0x00c00000 /* ICH4: sample capability bits (RO) */
260#define ICH_SAMPLE_16_20 0x00400000 /* ICH4: 16- and 20-bit samples */
261#define ICH_MULTICHAN_CAP 0x00300000 /* ICH4: multi-channel capability bits (RO) */
262#define ICH_SIS_TRI 0x00080000 /* SIS: tertiary resume irq */
263#define ICH_SIS_TCR 0x00040000 /* SIS: tertiary codec ready */
264#define ICH_MD3 0x00020000 /* modem power down semaphore */
265#define ICH_AD3 0x00010000 /* audio power down semaphore */
266#define ICH_RCS 0x00008000 /* read completion status */
267#define ICH_BIT3 0x00004000 /* bit 3 slot 12 */
268#define ICH_BIT2 0x00002000 /* bit 2 slot 12 */
269#define ICH_BIT1 0x00001000 /* bit 1 slot 12 */
270#define ICH_SRI 0x00000800 /* secondary (AC_SDIN1) resume interrupt */
271#define ICH_PRI 0x00000400 /* primary (AC_SDIN0) resume interrupt */
272#define ICH_SCR 0x00000200 /* secondary (AC_SDIN1) codec ready */
273#define ICH_PCR 0x00000100 /* primary (AC_SDIN0) codec ready */
274#define ICH_MCINT 0x00000080 /* MIC capture interrupt */
275#define ICH_POINT 0x00000040 /* playback interrupt */
276#define ICH_PIINT 0x00000020 /* capture interrupt */
277#define ICH_NVSPINT 0x00000010 /* nforce spdif interrupt */
278#define ICH_MOINT 0x00000004 /* modem playback interrupt */
279#define ICH_MIINT 0x00000002 /* modem capture interrupt */
280#define ICH_GSCI 0x00000001 /* GPI status change interrupt */
281#define ICH_REG_ACC_SEMA 0x34 /* byte - codec write semaphore */
282#define ICH_CAS 0x01 /* codec access semaphore */
283#define ICH_REG_SDM 0x80
284#define ICH_DI2L_MASK 0x000000c0 /* PCM In 2, Mic In 2 data in line */
285#define ICH_DI2L_SHIFT 6
286#define ICH_DI1L_MASK 0x00000030 /* PCM In 1, Mic In 1 data in line */
287#define ICH_DI1L_SHIFT 4
288#define ICH_SE 0x00000008 /* steer enable */
289#define ICH_LDI_MASK 0x00000003 /* last codec read data input */
290
291#define ICH_MAX_FRAGS 32 /* max hw frags */
292
293
294/*
295 * registers for Ali5455
296 */
297
298/* ALi 5455 busmaster blocks */
299DEFINE_REGSET(AL_PI, 0x40); /* ALi PCM in */
300DEFINE_REGSET(AL_PO, 0x50); /* Ali PCM out */
301DEFINE_REGSET(AL_MC, 0x60); /* Ali Mic in */
302DEFINE_REGSET(AL_CDC_SPO, 0x70); /* Ali Codec SPDIF out */
303DEFINE_REGSET(AL_CENTER, 0x80); /* Ali center out */
304DEFINE_REGSET(AL_LFE, 0x90); /* Ali center out */
305DEFINE_REGSET(AL_CLR_SPI, 0xa0); /* Ali Controller SPDIF in */
306DEFINE_REGSET(AL_CLR_SPO, 0xb0); /* Ali Controller SPDIF out */
307DEFINE_REGSET(AL_I2S, 0xc0); /* Ali I2S in */
308DEFINE_REGSET(AL_PI2, 0xd0); /* Ali PCM2 in */
309DEFINE_REGSET(AL_MC2, 0xe0); /* Ali Mic2 in */
310
311enum {
312 ICH_REG_ALI_SCR = 0x00, /* System Control Register */
313 ICH_REG_ALI_SSR = 0x04, /* System Status Register */
314 ICH_REG_ALI_DMACR = 0x08, /* DMA Control Register */
315 ICH_REG_ALI_FIFOCR1 = 0x0c, /* FIFO Control Register 1 */
316 ICH_REG_ALI_INTERFACECR = 0x10, /* Interface Control Register */
317 ICH_REG_ALI_INTERRUPTCR = 0x14, /* Interrupt control Register */
318 ICH_REG_ALI_INTERRUPTSR = 0x18, /* Interrupt Status Register */
319 ICH_REG_ALI_FIFOCR2 = 0x1c, /* FIFO Control Register 2 */
320 ICH_REG_ALI_CPR = 0x20, /* Command Port Register */
321 ICH_REG_ALI_CPR_ADDR = 0x22, /* ac97 addr write */
322 ICH_REG_ALI_SPR = 0x24, /* Status Port Register */
323 ICH_REG_ALI_SPR_ADDR = 0x26, /* ac97 addr read */
324 ICH_REG_ALI_FIFOCR3 = 0x2c, /* FIFO Control Register 3 */
325 ICH_REG_ALI_TTSR = 0x30, /* Transmit Tag Slot Register */
326 ICH_REG_ALI_RTSR = 0x34, /* Receive Tag Slot Register */
327 ICH_REG_ALI_CSPSR = 0x38, /* Command/Status Port Status Register */
328 ICH_REG_ALI_CAS = 0x3c, /* Codec Write Semaphore Register */
329 ICH_REG_ALI_HWVOL = 0xf0, /* hardware volume control/status */
330 ICH_REG_ALI_I2SCR = 0xf4, /* I2S control/status */
331 ICH_REG_ALI_SPDIFCSR = 0xf8, /* spdif channel status register */
332 ICH_REG_ALI_SPDIFICS = 0xfc, /* spdif interface control/status */
333};
334
335#define ALI_CAS_SEM_BUSY 0x80000000
336#define ALI_CPR_ADDR_SECONDARY 0x100
337#define ALI_CPR_ADDR_READ 0x80
338#define ALI_CSPSR_CODEC_READY 0x08
339#define ALI_CSPSR_READ_OK 0x02
340#define ALI_CSPSR_WRITE_OK 0x01
341
342/* interrupts for the whole chip by interrupt status register finish */
343
344#define ALI_INT_MICIN2 (1<<26)
345#define ALI_INT_PCMIN2 (1<<25)
346#define ALI_INT_I2SIN (1<<24)
347#define ALI_INT_SPDIFOUT (1<<23) /* controller spdif out INTERRUPT */
348#define ALI_INT_SPDIFIN (1<<22)
349#define ALI_INT_LFEOUT (1<<21)
350#define ALI_INT_CENTEROUT (1<<20)
351#define ALI_INT_CODECSPDIFOUT (1<<19)
352#define ALI_INT_MICIN (1<<18)
353#define ALI_INT_PCMOUT (1<<17)
354#define ALI_INT_PCMIN (1<<16)
355#define ALI_INT_CPRAIS (1<<7) /* command port available */
356#define ALI_INT_SPRAIS (1<<5) /* status port available */
357#define ALI_INT_GPIO (1<<1)
358#define ALI_INT_MASK (ALI_INT_SPDIFOUT|ALI_INT_CODECSPDIFOUT|ALI_INT_MICIN|ALI_INT_PCMOUT|ALI_INT_PCMIN)
359
360#define ICH_ALI_SC_RESET (1<<31) /* master reset */
361#define ICH_ALI_SC_AC97_DBL (1<<30)
362#define ICH_ALI_SC_CODEC_SPDF (3<<20) /* 1=7/8, 2=6/9, 3=10/11 */
363#define ICH_ALI_SC_IN_BITS (3<<18)
364#define ICH_ALI_SC_OUT_BITS (3<<16)
365#define ICH_ALI_SC_6CH_CFG (3<<14)
366#define ICH_ALI_SC_PCM_4 (1<<8)
367#define ICH_ALI_SC_PCM_6 (2<<8)
368#define ICH_ALI_SC_PCM_246_MASK (3<<8)
369
370#define ICH_ALI_SS_SEC_ID (3<<5)
371#define ICH_ALI_SS_PRI_ID (3<<3)
372
373#define ICH_ALI_IF_AC97SP (1<<21)
374#define ICH_ALI_IF_MC (1<<20)
375#define ICH_ALI_IF_PI (1<<19)
376#define ICH_ALI_IF_MC2 (1<<18)
377#define ICH_ALI_IF_PI2 (1<<17)
378#define ICH_ALI_IF_LINE_SRC (1<<15) /* 0/1 = slot 3/6 */
379#define ICH_ALI_IF_MIC_SRC (1<<14) /* 0/1 = slot 3/6 */
380#define ICH_ALI_IF_SPDF_SRC (3<<12) /* 00 = PCM, 01 = AC97-in, 10 = spdif-in, 11 = i2s */
381#define ICH_ALI_IF_AC97_OUT (3<<8) /* 00 = PCM, 10 = spdif-in, 11 = i2s */
382#define ICH_ALI_IF_PO_SPDF (1<<3)
383#define ICH_ALI_IF_PO (1<<1)
384
385/*
386 *
387 */
388
389enum { ICHD_PCMIN, ICHD_PCMOUT, ICHD_MIC, ICHD_MIC2, ICHD_PCM2IN, ICHD_SPBAR, ICHD_LAST = ICHD_SPBAR };
390enum { NVD_PCMIN, NVD_PCMOUT, NVD_MIC, NVD_SPBAR, NVD_LAST = NVD_SPBAR };
391enum { ALID_PCMIN, ALID_PCMOUT, ALID_MIC, ALID_AC97SPDIFOUT, ALID_SPDIFIN, ALID_SPDIFOUT, ALID_LAST = ALID_SPDIFOUT };
392
393#define get_ichdev(substream) (struct ichdev *)(substream->runtime->private_data)
394
395typedef struct ichdev {
396 unsigned int ichd; /* ich device number */
397 unsigned long reg_offset; /* offset to bmaddr */
398 u32 *bdbar; /* CPU address (32bit) */
399 unsigned int bdbar_addr; /* PCI bus address (32bit) */
400 snd_pcm_substream_t *substream;
401 unsigned int physbuf; /* physical address (32bit) */
402 unsigned int size;
403 unsigned int fragsize;
404 unsigned int fragsize1;
405 unsigned int position;
406 unsigned int pos_shift;
407 int frags;
408 int lvi;
409 int lvi_frag;
410 int civ;
411 int ack;
412 int ack_reload;
413 unsigned int ack_bit;
414 unsigned int roff_sr;
415 unsigned int roff_picb;
416 unsigned int int_sta_mask; /* interrupt status mask */
417 unsigned int ali_slot; /* ALI DMA slot */
418 struct ac97_pcm *pcm;
419 int pcm_open_flag;
420 unsigned int page_attr_changed: 1;
421 unsigned int suspended: 1;
422};
423
424struct intel8x0 {
425 unsigned int device_type;
426
427 int irq;
428
429 unsigned int mmio;
430 unsigned long addr;
431 unsigned long remap_addr;
432 unsigned int bm_mmio;
433 unsigned long bmaddr;
434 unsigned long remap_bmaddr;
435
436 struct pci_dev *pci;
437 snd_card_t *card;
438
439 int pcm_devs;
440 snd_pcm_t *pcm[6];
441 struct ichdev ichd[6];
442
443 int multi4: 1,
444 multi6: 1,
445 dra: 1,
446 smp20bit: 1;
447 int in_ac97_init: 1,
448 in_sdin_init: 1;
449 unsigned in_measurement: 1; /* during ac97 clock measurement */
450 unsigned fix_nocache: 1; /* workaround for 440MX */
451 unsigned buggy_irq: 1; /* workaround for buggy mobos */
452 unsigned xbox: 1; /* workaround for Xbox AC'97 detection */
453 unsigned buggy_semaphore: 1; /* workaround for buggy codec semaphore */
454
455 int spdif_idx; /* SPDIF BAR index; *_SPBAR or -1 if use PCMOUT */
456 unsigned int sdm_saved; /* SDM reg value */
457
458 ac97_bus_t *ac97_bus;
459 ac97_t *ac97[3];
460 unsigned int ac97_sdin[3];
461 unsigned int max_codecs, ncodecs;
462 unsigned int *codec_bit;
463 unsigned int codec_isr_bits;
464 unsigned int codec_ready_bits;
465
466 snd_rawmidi_t *rmidi;
467
468 spinlock_t reg_lock;
469
470 u32 bdbars_count;
471 struct snd_dma_buffer bdbars;
472 u32 int_sta_reg; /* interrupt status register */
473 u32 int_sta_mask; /* interrupt status mask */
474};
475
476static struct pci_device_id snd_intel8x0_ids[] = {
477 { 0x8086, 0x2415, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* 82801AA */
478 { 0x8086, 0x2425, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* 82901AB */
479 { 0x8086, 0x2445, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* 82801BA */
480 { 0x8086, 0x2485, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* ICH3 */
481 { 0x8086, 0x24c5, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL_ICH4 }, /* ICH4 */
482 { 0x8086, 0x24d5, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL_ICH5 }, /* ICH5 */
483 { 0x8086, 0x25a6, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL_ICH5 }, /* ESB */
484 { 0x8086, 0x266e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL_ICH5 }, /* ICH6 */
485 { 0x8086, 0x27de, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL_ICH5 }, /* ICH7 */
486 { 0x8086, 0x2698, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL_ICH4 }, /* ESB2 */
487 { 0x8086, 0x7195, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* 440MX */
488 { 0x1039, 0x7012, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_SIS }, /* SI7012 */
489 { 0x10de, 0x01b1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE }, /* NFORCE */
490 { 0x10de, 0x003a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE }, /* MCP04 */
491 { 0x10de, 0x006a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE }, /* NFORCE2 */
492 { 0x10de, 0x0059, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE }, /* CK804 */
493 { 0x10de, 0x008a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE }, /* CK8 */
494 { 0x10de, 0x00da, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE }, /* NFORCE3 */
495 { 0x10de, 0x00ea, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE }, /* CK8S */
496 { 0x1022, 0x746d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* AMD8111 */
497 { 0x1022, 0x7445, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* AMD768 */
498 { 0x10b9, 0x5455, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_ALI }, /* Ali5455 */
499 { 0 }
500};
501
502MODULE_DEVICE_TABLE(pci, snd_intel8x0_ids);
503
504
505/*
506 * Lowlevel I/O - busmaster
507 */
508
509static u8 igetbyte(struct intel8x0 *chip, u32 offset)
510{
511 if (chip->bm_mmio)
512 return readb(chip->remap_bmaddr + offset);
513 else
514 return inb(chip->bmaddr + offset);
515}
516
517static u16 igetword(struct intel8x0 *chip, u32 offset)
518{
519 if (chip->bm_mmio)
520 return readw(chip->remap_bmaddr + offset);
521 else
522 return inw(chip->bmaddr + offset);
523}
524
525static u32 igetdword(struct intel8x0 *chip, u32 offset)
526{
527 if (chip->bm_mmio)
528 return readl(chip->remap_bmaddr + offset);
529 else
530 return inl(chip->bmaddr + offset);
531}
532
533static void iputbyte(struct intel8x0 *chip, u32 offset, u8 val)
534{
535 if (chip->bm_mmio)
536 writeb(val, chip->remap_bmaddr + offset);
537 else
538 outb(val, chip->bmaddr + offset);
539}
540
541static void iputword(struct intel8x0 *chip, u32 offset, u16 val)
542{
543 if (chip->bm_mmio)
544 writew(val, chip->remap_bmaddr + offset);
545 else
546 outw(val, chip->bmaddr + offset);
547}
548
549static void iputdword(struct intel8x0 *chip, u32 offset, u32 val)
550{
551 if (chip->bm_mmio)
552 writel(val, chip->remap_bmaddr + offset);
553 else
554 outl(val, chip->bmaddr + offset);
555}
556
557/*
558 * Lowlevel I/O - AC'97 registers
559 */
560
561static u16 iagetword(struct intel8x0 *chip, u32 offset)
562{
563 if (chip->mmio)
564 return readw(chip->remap_addr + offset);
565 else
566 return inw(chip->addr + offset);
567}
568
569static void iaputword(struct intel8x0 *chip, u32 offset, u16 val)
570{
571 if (chip->mmio)
572 writew(val, chip->remap_addr + offset);
573 else
574 outw(val, chip->addr + offset);
575}
576
577/*
578 * Basic I/O
579 */
580
581/*
582 * access to AC97 codec via normal i/o (for ICH and SIS7012)
583 */
584
585static int snd_intel8x0_codec_semaphore(struct intel8x0 *chip, unsigned int codec)
586{
587 int time;
588
589 if (codec > 2)
590 return -EIO;
591 if (chip->in_sdin_init) {
592 /* we don't know the ready bit assignment at the moment */
593 /* so we check any */
594 codec = chip->codec_isr_bits;
595 } else {
596 codec = chip->codec_bit[chip->ac97_sdin[codec]];
597 }
598
599 /* codec ready ? */
600 if ((igetdword(chip, ICHREG(GLOB_STA)) & codec) == 0)
601 return -EIO;
602
603 /* Anyone holding a semaphore for 1 msec should be shot... */
604 time = 100;
605 do {
606 if (!(igetbyte(chip, ICHREG(ACC_SEMA)) & ICH_CAS))
607 return 0;
608 udelay(10);
609 } while (time--);
610
611 /* access to some forbidden (non existant) ac97 registers will not
612 * reset the semaphore. So even if you don't get the semaphore, still
613 * continue the access. We don't need the semaphore anyway. */
614 snd_printk("codec_semaphore: semaphore is not ready [0x%x][0x%x]\n",
615 igetbyte(chip, ICHREG(ACC_SEMA)), igetdword(chip, ICHREG(GLOB_STA)));
616 iagetword(chip, 0); /* clear semaphore flag */
617 /* I don't care about the semaphore */
618 return -EBUSY;
619}
620
621static void snd_intel8x0_codec_write(ac97_t *ac97,
622 unsigned short reg,
623 unsigned short val)
624{
625 struct intel8x0 *chip = ac97->private_data;
626
627 if (snd_intel8x0_codec_semaphore(chip, ac97->num) < 0) {
628 if (! chip->in_ac97_init)
629 snd_printk("codec_write %d: semaphore is not ready for register 0x%x\n", ac97->num, reg);
630 }
631 iaputword(chip, reg + ac97->num * 0x80, val);
632}
633
634static unsigned short snd_intel8x0_codec_read(ac97_t *ac97,
635 unsigned short reg)
636{
637 struct intel8x0 *chip = ac97->private_data;
638 unsigned short res;
639 unsigned int tmp;
640
641 if (snd_intel8x0_codec_semaphore(chip, ac97->num) < 0) {
642 if (! chip->in_ac97_init)
643 snd_printk("codec_read %d: semaphore is not ready for register 0x%x\n", ac97->num, reg);
644 res = 0xffff;
645 } else {
646 res = iagetword(chip, reg + ac97->num * 0x80);
647 if ((tmp = igetdword(chip, ICHREG(GLOB_STA))) & ICH_RCS) {
648 /* reset RCS and preserve other R/WC bits */
649 iputdword(chip, ICHREG(GLOB_STA), tmp & ~(chip->codec_ready_bits | ICH_GSCI));
650 if (! chip->in_ac97_init)
651 snd_printk("codec_read %d: read timeout for register 0x%x\n", ac97->num, reg);
652 res = 0xffff;
653 }
654 }
655 return res;
656}
657
658static void __devinit snd_intel8x0_codec_read_test(struct intel8x0 *chip,
659 unsigned int codec)
660{
661 unsigned int tmp;
662
663 if (snd_intel8x0_codec_semaphore(chip, codec) >= 0) {
664 iagetword(chip, codec * 0x80);
665 if ((tmp = igetdword(chip, ICHREG(GLOB_STA))) & ICH_RCS) {
666 /* reset RCS and preserve other R/WC bits */
667 iputdword(chip, ICHREG(GLOB_STA), tmp & ~(chip->codec_ready_bits | ICH_GSCI));
668 }
669 }
670}
671
672/*
673 * access to AC97 for Ali5455
674 */
675static int snd_intel8x0_ali_codec_ready(struct intel8x0 *chip, int mask)
676{
677 int count = 0;
678 for (count = 0; count < 0x7f; count++) {
679 int val = igetbyte(chip, ICHREG(ALI_CSPSR));
680 if (val & mask)
681 return 0;
682 }
683 if (! chip->in_ac97_init)
684 snd_printd(KERN_WARNING "intel8x0: AC97 codec ready timeout.\n");
685 return -EBUSY;
686}
687
688static int snd_intel8x0_ali_codec_semaphore(struct intel8x0 *chip)
689{
690 int time = 100;
691 if (chip->buggy_semaphore)
692 return 0; /* just ignore ... */
693 while (time-- && (igetdword(chip, ICHREG(ALI_CAS)) & ALI_CAS_SEM_BUSY))
694 udelay(1);
695 if (! time && ! chip->in_ac97_init)
696 snd_printk(KERN_WARNING "ali_codec_semaphore timeout\n");
697 return snd_intel8x0_ali_codec_ready(chip, ALI_CSPSR_CODEC_READY);
698}
699
700static unsigned short snd_intel8x0_ali_codec_read(ac97_t *ac97, unsigned short reg)
701{
702 struct intel8x0 *chip = ac97->private_data;
703 unsigned short data = 0xffff;
704
705 if (snd_intel8x0_ali_codec_semaphore(chip))
706 goto __err;
707 reg |= ALI_CPR_ADDR_READ;
708 if (ac97->num)
709 reg |= ALI_CPR_ADDR_SECONDARY;
710 iputword(chip, ICHREG(ALI_CPR_ADDR), reg);
711 if (snd_intel8x0_ali_codec_ready(chip, ALI_CSPSR_READ_OK))
712 goto __err;
713 data = igetword(chip, ICHREG(ALI_SPR));
714__err:
715 return data;
716}
717
718static void snd_intel8x0_ali_codec_write(ac97_t *ac97, unsigned short reg, unsigned short val)
719{
720 struct intel8x0 *chip = ac97->private_data;
721
722 if (snd_intel8x0_ali_codec_semaphore(chip))
723 return;
724 iputword(chip, ICHREG(ALI_CPR), val);
725 if (ac97->num)
726 reg |= ALI_CPR_ADDR_SECONDARY;
727 iputword(chip, ICHREG(ALI_CPR_ADDR), reg);
728 snd_intel8x0_ali_codec_ready(chip, ALI_CSPSR_WRITE_OK);
729}
730
731
732/*
733 * DMA I/O
734 */
735static void snd_intel8x0_setup_periods(struct intel8x0 *chip, struct ichdev *ichdev)
736{
737 int idx;
738 u32 *bdbar = ichdev->bdbar;
739 unsigned long port = ichdev->reg_offset;
740
741 iputdword(chip, port + ICH_REG_OFF_BDBAR, ichdev->bdbar_addr);
742 if (ichdev->size == ichdev->fragsize) {
743 ichdev->ack_reload = ichdev->ack = 2;
744 ichdev->fragsize1 = ichdev->fragsize >> 1;
745 for (idx = 0; idx < (ICH_REG_LVI_MASK + 1) * 2; idx += 4) {
746 bdbar[idx + 0] = cpu_to_le32(ichdev->physbuf);
747 bdbar[idx + 1] = cpu_to_le32(0x80000000 | /* interrupt on completion */
748 ichdev->fragsize1 >> ichdev->pos_shift);
749 bdbar[idx + 2] = cpu_to_le32(ichdev->physbuf + (ichdev->size >> 1));
750 bdbar[idx + 3] = cpu_to_le32(0x80000000 | /* interrupt on completion */
751 ichdev->fragsize1 >> ichdev->pos_shift);
752 }
753 ichdev->frags = 2;
754 } else {
755 ichdev->ack_reload = ichdev->ack = 1;
756 ichdev->fragsize1 = ichdev->fragsize;
757 for (idx = 0; idx < (ICH_REG_LVI_MASK + 1) * 2; idx += 2) {
758 bdbar[idx + 0] = cpu_to_le32(ichdev->physbuf + (((idx >> 1) * ichdev->fragsize) % ichdev->size));
759 bdbar[idx + 1] = cpu_to_le32(0x80000000 | /* interrupt on completion */
760 ichdev->fragsize >> ichdev->pos_shift);
761 // printk("bdbar[%i] = 0x%x [0x%x]\n", idx + 0, bdbar[idx + 0], bdbar[idx + 1]);
762 }
763 ichdev->frags = ichdev->size / ichdev->fragsize;
764 }
765 iputbyte(chip, port + ICH_REG_OFF_LVI, ichdev->lvi = ICH_REG_LVI_MASK);
766 ichdev->civ = 0;
767 iputbyte(chip, port + ICH_REG_OFF_CIV, 0);
768 ichdev->lvi_frag = ICH_REG_LVI_MASK % ichdev->frags;
769 ichdev->position = 0;
770#if 0
771 printk("lvi_frag = %i, frags = %i, period_size = 0x%x, period_size1 = 0x%x\n",
772 ichdev->lvi_frag, ichdev->frags, ichdev->fragsize, ichdev->fragsize1);
773#endif
774 /* clear interrupts */
775 iputbyte(chip, port + ichdev->roff_sr, ICH_FIFOE | ICH_BCIS | ICH_LVBCI);
776}
777
778/*
779 * Interrupt handler
780 */
781
782static inline void snd_intel8x0_update(struct intel8x0 *chip, struct ichdev *ichdev)
783{
784 unsigned long port = ichdev->reg_offset;
785 int status, civ, i, step;
786 int ack = 0;
787
788 spin_lock(&chip->reg_lock);
789 status = igetbyte(chip, port + ichdev->roff_sr);
790 civ = igetbyte(chip, port + ICH_REG_OFF_CIV);
791 if (!(status & ICH_BCIS)) {
792 step = 0;
793 } else if (civ == ichdev->civ) {
794 // snd_printd("civ same %d\n", civ);
795 step = 1;
796 ichdev->civ++;
797 ichdev->civ &= ICH_REG_LVI_MASK;
798 } else {
799 step = civ - ichdev->civ;
800 if (step < 0)
801 step += ICH_REG_LVI_MASK + 1;
802 // if (step != 1)
803 // snd_printd("step = %d, %d -> %d\n", step, ichdev->civ, civ);
804 ichdev->civ = civ;
805 }
806
807 ichdev->position += step * ichdev->fragsize1;
808 ichdev->position %= ichdev->size;
809 ichdev->lvi += step;
810 ichdev->lvi &= ICH_REG_LVI_MASK;
811 iputbyte(chip, port + ICH_REG_OFF_LVI, ichdev->lvi);
812 for (i = 0; i < step; i++) {
813 ichdev->lvi_frag++;
814 ichdev->lvi_frag %= ichdev->frags;
815 ichdev->bdbar[ichdev->lvi * 2] = cpu_to_le32(ichdev->physbuf + ichdev->lvi_frag * ichdev->fragsize1);
816 // printk("new: bdbar[%i] = 0x%x [0x%x], prefetch = %i, all = 0x%x, 0x%x\n", ichdev->lvi * 2, ichdev->bdbar[ichdev->lvi * 2], ichdev->bdbar[ichdev->lvi * 2 + 1], inb(ICH_REG_OFF_PIV + port), inl(port + 4), inb(port + ICH_REG_OFF_CR));
817 if (--ichdev->ack == 0) {
818 ichdev->ack = ichdev->ack_reload;
819 ack = 1;
820 }
821 }
822 spin_unlock(&chip->reg_lock);
823 if (ack && ichdev->substream) {
824 snd_pcm_period_elapsed(ichdev->substream);
825 }
826 iputbyte(chip, port + ichdev->roff_sr,
827 status & (ICH_FIFOE | ICH_BCIS | ICH_LVBCI));
828}
829
830static irqreturn_t snd_intel8x0_interrupt(int irq, void *dev_id, struct pt_regs *regs)
831{
832 struct intel8x0 *chip = dev_id;
833 struct ichdev *ichdev;
834 unsigned int status;
835 unsigned int i;
836
837 status = igetdword(chip, chip->int_sta_reg);
838 if (status == 0xffffffff) /* we are not yet resumed */
839 return IRQ_NONE;
840
841 if ((status & chip->int_sta_mask) == 0) {
842 static int err_count = 10;
843 if (status) {
844 /* ack */
845 iputdword(chip, chip->int_sta_reg, status);
846 /* FIXME: on some ICH5 board shows the same
847 * problem. So we return IRQ_HANDLED
848 * in any cases.
849 * (or, maybe add a new module param to control this?)
850 */
851#if 0
852 if (chip->device_type != DEVICE_NFORCE)
853 status ^= igetdword(chip, chip->int_sta_reg);
854#endif
855 }
856 return IRQ_RETVAL(status);
857 }
858
859 for (i = 0; i < chip->bdbars_count; i++) {
860 ichdev = &chip->ichd[i];
861 if (status & ichdev->int_sta_mask)
862 snd_intel8x0_update(chip, ichdev);
863 }
864
865 /* ack them */
866 iputdword(chip, chip->int_sta_reg, status & chip->int_sta_mask);
867
868 return IRQ_HANDLED;
869}
870
871/*
872 * PCM part
873 */
874
875static int snd_intel8x0_pcm_trigger(snd_pcm_substream_t *substream, int cmd)
876{
877 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
878 struct ichdev *ichdev = get_ichdev(substream);
879 unsigned char val = 0;
880 unsigned long port = ichdev->reg_offset;
881
882 switch (cmd) {
883 case SNDRV_PCM_TRIGGER_RESUME:
884 ichdev->suspended = 0;
885 /* fallthru */
886 case SNDRV_PCM_TRIGGER_START:
887 val = ICH_IOCE | ICH_STARTBM;
888 break;
889 case SNDRV_PCM_TRIGGER_SUSPEND:
890 ichdev->suspended = 1;
891 /* fallthru */
892 case SNDRV_PCM_TRIGGER_STOP:
893 val = 0;
894 break;
895 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
896 val = ICH_IOCE;
897 break;
898 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
899 val = ICH_IOCE | ICH_STARTBM;
900 break;
901 default:
902 return -EINVAL;
903 }
904 iputbyte(chip, port + ICH_REG_OFF_CR, val);
905 if (cmd == SNDRV_PCM_TRIGGER_STOP) {
906 /* wait until DMA stopped */
907 while (!(igetbyte(chip, port + ichdev->roff_sr) & ICH_DCH)) ;
908 /* reset whole DMA things */
909 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_RESETREGS);
910 }
911 return 0;
912}
913
914static int snd_intel8x0_ali_trigger(snd_pcm_substream_t *substream, int cmd)
915{
916 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
917 struct ichdev *ichdev = get_ichdev(substream);
918 unsigned long port = ichdev->reg_offset;
919 static int fiforeg[] = { ICHREG(ALI_FIFOCR1), ICHREG(ALI_FIFOCR2), ICHREG(ALI_FIFOCR3) };
920 unsigned int val, fifo;
921
922 val = igetdword(chip, ICHREG(ALI_DMACR));
923 switch (cmd) {
924 case SNDRV_PCM_TRIGGER_RESUME:
925 ichdev->suspended = 0;
926 /* fallthru */
927 case SNDRV_PCM_TRIGGER_START:
928 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
929 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
930 /* clear FIFO for synchronization of channels */
931 fifo = igetdword(chip, fiforeg[ichdev->ali_slot / 4]);
932 fifo &= ~(0xff << (ichdev->ali_slot % 4));
933 fifo |= 0x83 << (ichdev->ali_slot % 4);
934 iputdword(chip, fiforeg[ichdev->ali_slot / 4], fifo);
935 }
936 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_IOCE);
937 val &= ~(1 << (ichdev->ali_slot + 16)); /* clear PAUSE flag */
938 iputdword(chip, ICHREG(ALI_DMACR), val | (1 << ichdev->ali_slot)); /* start DMA */
939 break;
940 case SNDRV_PCM_TRIGGER_SUSPEND:
941 ichdev->suspended = 1;
942 /* fallthru */
943 case SNDRV_PCM_TRIGGER_STOP:
944 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
945 iputdword(chip, ICHREG(ALI_DMACR), val | (1 << (ichdev->ali_slot + 16))); /* pause */
946 iputbyte(chip, port + ICH_REG_OFF_CR, 0);
947 while (igetbyte(chip, port + ICH_REG_OFF_CR))
948 ;
949 if (cmd == SNDRV_PCM_TRIGGER_PAUSE_PUSH)
950 break;
951 /* reset whole DMA things */
952 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_RESETREGS);
953 /* clear interrupts */
954 iputbyte(chip, port + ICH_REG_OFF_SR, igetbyte(chip, port + ICH_REG_OFF_SR) | 0x1e);
955 iputdword(chip, ICHREG(ALI_INTERRUPTSR),
956 igetdword(chip, ICHREG(ALI_INTERRUPTSR)) & ichdev->int_sta_mask);
957 break;
958 default:
959 return -EINVAL;
960 }
961 return 0;
962}
963
964static int snd_intel8x0_hw_params(snd_pcm_substream_t * substream,
965 snd_pcm_hw_params_t * hw_params)
966{
967 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
968 struct ichdev *ichdev = get_ichdev(substream);
969 int dbl = params_rate(hw_params) > 48000;
970 int err;
971
972 err = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params));
973 if (err < 0)
974 return err;
975 if (ichdev->pcm_open_flag) {
976 snd_ac97_pcm_close(ichdev->pcm);
977 ichdev->pcm_open_flag = 0;
978 }
979 err = snd_ac97_pcm_open(ichdev->pcm, params_rate(hw_params),
980 params_channels(hw_params),
981 ichdev->pcm->r[dbl].slots);
982 if (err >= 0) {
983 ichdev->pcm_open_flag = 1;
984 /* Force SPDIF setting */
985 if (ichdev->ichd == ICHD_PCMOUT && chip->spdif_idx < 0)
986 snd_ac97_set_rate(ichdev->pcm->r[0].codec[0], AC97_SPDIF, params_rate(hw_params));
987 }
988 return err;
989}
990
991static int snd_intel8x0_hw_free(snd_pcm_substream_t * substream)
992{
993 struct ichdev *ichdev = get_ichdev(substream);
994
995 if (ichdev->pcm_open_flag) {
996 snd_ac97_pcm_close(ichdev->pcm);
997 ichdev->pcm_open_flag = 0;
998 }
999 return snd_pcm_lib_free_pages(substream);
1000}
1001
1002static void snd_intel8x0_setup_pcm_out(struct intel8x0 *chip,
1003 snd_pcm_runtime_t *runtime)
1004{
1005 unsigned int cnt;
1006 int dbl = runtime->rate > 48000;
1007
1008 spin_lock_irq(&chip->reg_lock);
1009 switch (chip->device_type) {
1010 case DEVICE_ALI:
1011 cnt = igetdword(chip, ICHREG(ALI_SCR));
1012 cnt &= ~ICH_ALI_SC_PCM_246_MASK;
1013 if (runtime->channels == 4 || dbl)
1014 cnt |= ICH_ALI_SC_PCM_4;
1015 else if (runtime->channels == 6)
1016 cnt |= ICH_ALI_SC_PCM_6;
1017 iputdword(chip, ICHREG(ALI_SCR), cnt);
1018 break;
1019 case DEVICE_SIS:
1020 cnt = igetdword(chip, ICHREG(GLOB_CNT));
1021 cnt &= ~ICH_SIS_PCM_246_MASK;
1022 if (runtime->channels == 4 || dbl)
1023 cnt |= ICH_SIS_PCM_4;
1024 else if (runtime->channels == 6)
1025 cnt |= ICH_SIS_PCM_6;
1026 iputdword(chip, ICHREG(GLOB_CNT), cnt);
1027 break;
1028 default:
1029 cnt = igetdword(chip, ICHREG(GLOB_CNT));
1030 cnt &= ~(ICH_PCM_246_MASK | ICH_PCM_20BIT);
1031 if (runtime->channels == 4 || dbl)
1032 cnt |= ICH_PCM_4;
1033 else if (runtime->channels == 6)
1034 cnt |= ICH_PCM_6;
1035 if (chip->device_type == DEVICE_NFORCE) {
1036 /* reset to 2ch once to keep the 6 channel data in alignment,
1037 * to start from Front Left always
1038 */
1039 if (cnt & ICH_PCM_246_MASK) {
1040 iputdword(chip, ICHREG(GLOB_CNT), cnt & ~ICH_PCM_246_MASK);
1041 spin_unlock_irq(&chip->reg_lock);
1042 msleep(50); /* grrr... */
1043 spin_lock_irq(&chip->reg_lock);
1044 }
1045 } else if (chip->device_type == DEVICE_INTEL_ICH4 ||
1046 chip->device_type == DEVICE_INTEL_ICH5) {
1047 if (runtime->sample_bits > 16)
1048 cnt |= ICH_PCM_20BIT;
1049 }
1050 iputdword(chip, ICHREG(GLOB_CNT), cnt);
1051 break;
1052 }
1053 spin_unlock_irq(&chip->reg_lock);
1054}
1055
1056static int snd_intel8x0_pcm_prepare(snd_pcm_substream_t * substream)
1057{
1058 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1059 snd_pcm_runtime_t *runtime = substream->runtime;
1060 struct ichdev *ichdev = get_ichdev(substream);
1061
1062 ichdev->physbuf = runtime->dma_addr;
1063 ichdev->size = snd_pcm_lib_buffer_bytes(substream);
1064 ichdev->fragsize = snd_pcm_lib_period_bytes(substream);
1065 if (ichdev->ichd == ICHD_PCMOUT) {
1066 snd_intel8x0_setup_pcm_out(chip, runtime);
1067 if (chip->device_type == DEVICE_INTEL_ICH4 ||
1068 chip->device_type == DEVICE_INTEL_ICH5)
1069 ichdev->pos_shift = (runtime->sample_bits > 16) ? 2 : 1;
1070 }
1071 snd_intel8x0_setup_periods(chip, ichdev);
1072 return 0;
1073}
1074
1075static snd_pcm_uframes_t snd_intel8x0_pcm_pointer(snd_pcm_substream_t * substream)
1076{
1077 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1078 struct ichdev *ichdev = get_ichdev(substream);
1079 size_t ptr1, ptr;
1080 int civ, timeout = 100;
1081 unsigned int position;
1082
1083 spin_lock(&chip->reg_lock);
1084 do {
1085 civ = igetbyte(chip, ichdev->reg_offset + ICH_REG_OFF_CIV);
1086 ptr1 = igetword(chip, ichdev->reg_offset + ichdev->roff_picb);
1087 position = ichdev->position;
1088 if (ptr1 == 0) {
1089 udelay(10);
1090 continue;
1091 }
1092 if (civ == igetbyte(chip, ichdev->reg_offset + ICH_REG_OFF_CIV) &&
1093 ptr1 == igetword(chip, ichdev->reg_offset + ichdev->roff_picb))
1094 break;
1095 } while (timeout--);
1096 ptr1 <<= ichdev->pos_shift;
1097 ptr = ichdev->fragsize1 - ptr1;
1098 ptr += position;
1099 spin_unlock(&chip->reg_lock);
1100 if (ptr >= ichdev->size)
1101 return 0;
1102 return bytes_to_frames(substream->runtime, ptr);
1103}
1104
1105static snd_pcm_hardware_t snd_intel8x0_stream =
1106{
1107 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1108 SNDRV_PCM_INFO_BLOCK_TRANSFER |
1109 SNDRV_PCM_INFO_MMAP_VALID |
1110 SNDRV_PCM_INFO_PAUSE |
1111 SNDRV_PCM_INFO_RESUME),
1112 .formats = SNDRV_PCM_FMTBIT_S16_LE,
1113 .rates = SNDRV_PCM_RATE_48000,
1114 .rate_min = 48000,
1115 .rate_max = 48000,
1116 .channels_min = 2,
1117 .channels_max = 2,
1118 .buffer_bytes_max = 128 * 1024,
1119 .period_bytes_min = 32,
1120 .period_bytes_max = 128 * 1024,
1121 .periods_min = 1,
1122 .periods_max = 1024,
1123 .fifo_size = 0,
1124};
1125
1126static unsigned int channels4[] = {
1127 2, 4,
1128};
1129
1130static snd_pcm_hw_constraint_list_t hw_constraints_channels4 = {
1131 .count = ARRAY_SIZE(channels4),
1132 .list = channels4,
1133 .mask = 0,
1134};
1135
1136static unsigned int channels6[] = {
1137 2, 4, 6,
1138};
1139
1140static snd_pcm_hw_constraint_list_t hw_constraints_channels6 = {
1141 .count = ARRAY_SIZE(channels6),
1142 .list = channels6,
1143 .mask = 0,
1144};
1145
1146static int snd_intel8x0_pcm_open(snd_pcm_substream_t * substream, struct ichdev *ichdev)
1147{
1148 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1149 snd_pcm_runtime_t *runtime = substream->runtime;
1150 int err;
1151
1152 ichdev->substream = substream;
1153 runtime->hw = snd_intel8x0_stream;
1154 runtime->hw.rates = ichdev->pcm->rates;
1155 snd_pcm_limit_hw_rates(runtime);
1156 if (chip->device_type == DEVICE_SIS) {
1157 // vladest workaround
1158 if (!runtime->hw.rates)
1159 runtime->hw.rates = SNDRV_PCM_RATE_48000;
1160 runtime->hw.buffer_bytes_max = 64*1024;
1161 runtime->hw.period_bytes_max = 64*1024;
1162 }
1163 if ((err = snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS)) < 0)
1164 return err;
1165 runtime->private_data = ichdev;
1166 return 0;
1167}
1168
1169static int snd_intel8x0_playback_open(snd_pcm_substream_t * substream)
1170{
1171 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1172 snd_pcm_runtime_t *runtime = substream->runtime;
1173 int err;
1174
1175 err = snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_PCMOUT]);
1176 if (err < 0)
1177 return err;
1178 if (chip->multi6) {
1179 runtime->hw.channels_max = 6;
1180 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, &hw_constraints_channels6);
1181 } else if (chip->multi4) {
1182 runtime->hw.channels_max = 4;
1183 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, &hw_constraints_channels4);
1184 }
1185 if (chip->dra) {
1186 snd_ac97_pcm_double_rate_rules(runtime);
1187 }
1188 if (chip->smp20bit)
1189 runtime->hw.formats |= SNDRV_PCM_FMTBIT_S32_LE;
1190 return 0;
1191}
1192
1193static int snd_intel8x0_playback_close(snd_pcm_substream_t * substream)
1194{
1195 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1196
1197 chip->ichd[ICHD_PCMOUT].substream = NULL;
1198 return 0;
1199}
1200
1201static int snd_intel8x0_capture_open(snd_pcm_substream_t * substream)
1202{
1203 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1204
1205 return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_PCMIN]);
1206}
1207
1208static int snd_intel8x0_capture_close(snd_pcm_substream_t * substream)
1209{
1210 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1211
1212 chip->ichd[ICHD_PCMIN].substream = NULL;
1213 return 0;
1214}
1215
1216static int snd_intel8x0_mic_open(snd_pcm_substream_t * substream)
1217{
1218 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1219
1220 return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_MIC]);
1221}
1222
1223static int snd_intel8x0_mic_close(snd_pcm_substream_t * substream)
1224{
1225 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1226
1227 chip->ichd[ICHD_MIC].substream = NULL;
1228 return 0;
1229}
1230
1231static int snd_intel8x0_mic2_open(snd_pcm_substream_t * substream)
1232{
1233 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1234
1235 return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_MIC2]);
1236}
1237
1238static int snd_intel8x0_mic2_close(snd_pcm_substream_t * substream)
1239{
1240 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1241
1242 chip->ichd[ICHD_MIC2].substream = NULL;
1243 return 0;
1244}
1245
1246static int snd_intel8x0_capture2_open(snd_pcm_substream_t * substream)
1247{
1248 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1249
1250 return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_PCM2IN]);
1251}
1252
1253static int snd_intel8x0_capture2_close(snd_pcm_substream_t * substream)
1254{
1255 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1256
1257 chip->ichd[ICHD_PCM2IN].substream = NULL;
1258 return 0;
1259}
1260
1261static int snd_intel8x0_spdif_open(snd_pcm_substream_t * substream)
1262{
1263 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1264 int idx = chip->device_type == DEVICE_NFORCE ? NVD_SPBAR : ICHD_SPBAR;
1265
1266 return snd_intel8x0_pcm_open(substream, &chip->ichd[idx]);
1267}
1268
1269static int snd_intel8x0_spdif_close(snd_pcm_substream_t * substream)
1270{
1271 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1272 int idx = chip->device_type == DEVICE_NFORCE ? NVD_SPBAR : ICHD_SPBAR;
1273
1274 chip->ichd[idx].substream = NULL;
1275 return 0;
1276}
1277
1278static int snd_intel8x0_ali_ac97spdifout_open(snd_pcm_substream_t * substream)
1279{
1280 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1281 unsigned int val;
1282
1283 spin_lock_irq(&chip->reg_lock);
1284 val = igetdword(chip, ICHREG(ALI_INTERFACECR));
1285 val |= ICH_ALI_IF_AC97SP;
1286 iputdword(chip, ICHREG(ALI_INTERFACECR), val);
1287 /* also needs to set ALI_SC_CODEC_SPDF correctly */
1288 spin_unlock_irq(&chip->reg_lock);
1289
1290 return snd_intel8x0_pcm_open(substream, &chip->ichd[ALID_AC97SPDIFOUT]);
1291}
1292
1293static int snd_intel8x0_ali_ac97spdifout_close(snd_pcm_substream_t * substream)
1294{
1295 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1296 unsigned int val;
1297
1298 chip->ichd[ALID_AC97SPDIFOUT].substream = NULL;
1299 spin_lock_irq(&chip->reg_lock);
1300 val = igetdword(chip, ICHREG(ALI_INTERFACECR));
1301 val &= ~ICH_ALI_IF_AC97SP;
1302 iputdword(chip, ICHREG(ALI_INTERFACECR), val);
1303 spin_unlock_irq(&chip->reg_lock);
1304
1305 return 0;
1306}
1307
1308static int snd_intel8x0_ali_spdifin_open(snd_pcm_substream_t * substream)
1309{
1310 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1311
1312 return snd_intel8x0_pcm_open(substream, &chip->ichd[ALID_SPDIFIN]);
1313}
1314
1315static int snd_intel8x0_ali_spdifin_close(snd_pcm_substream_t * substream)
1316{
1317 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1318
1319 chip->ichd[ALID_SPDIFIN].substream = NULL;
1320 return 0;
1321}
1322
1323#if 0 // NYI
1324static int snd_intel8x0_ali_spdifout_open(snd_pcm_substream_t * substream)
1325{
1326 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1327
1328 return snd_intel8x0_pcm_open(substream, &chip->ichd[ALID_SPDIFOUT]);
1329}
1330
1331static int snd_intel8x0_ali_spdifout_close(snd_pcm_substream_t * substream)
1332{
1333 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1334
1335 chip->ichd[ALID_SPDIFOUT].substream = NULL;
1336 return 0;
1337}
1338#endif
1339
1340static snd_pcm_ops_t snd_intel8x0_playback_ops = {
1341 .open = snd_intel8x0_playback_open,
1342 .close = snd_intel8x0_playback_close,
1343 .ioctl = snd_pcm_lib_ioctl,
1344 .hw_params = snd_intel8x0_hw_params,
1345 .hw_free = snd_intel8x0_hw_free,
1346 .prepare = snd_intel8x0_pcm_prepare,
1347 .trigger = snd_intel8x0_pcm_trigger,
1348 .pointer = snd_intel8x0_pcm_pointer,
1349};
1350
1351static snd_pcm_ops_t snd_intel8x0_capture_ops = {
1352 .open = snd_intel8x0_capture_open,
1353 .close = snd_intel8x0_capture_close,
1354 .ioctl = snd_pcm_lib_ioctl,
1355 .hw_params = snd_intel8x0_hw_params,
1356 .hw_free = snd_intel8x0_hw_free,
1357 .prepare = snd_intel8x0_pcm_prepare,
1358 .trigger = snd_intel8x0_pcm_trigger,
1359 .pointer = snd_intel8x0_pcm_pointer,
1360};
1361
1362static snd_pcm_ops_t snd_intel8x0_capture_mic_ops = {
1363 .open = snd_intel8x0_mic_open,
1364 .close = snd_intel8x0_mic_close,
1365 .ioctl = snd_pcm_lib_ioctl,
1366 .hw_params = snd_intel8x0_hw_params,
1367 .hw_free = snd_intel8x0_hw_free,
1368 .prepare = snd_intel8x0_pcm_prepare,
1369 .trigger = snd_intel8x0_pcm_trigger,
1370 .pointer = snd_intel8x0_pcm_pointer,
1371};
1372
1373static snd_pcm_ops_t snd_intel8x0_capture_mic2_ops = {
1374 .open = snd_intel8x0_mic2_open,
1375 .close = snd_intel8x0_mic2_close,
1376 .ioctl = snd_pcm_lib_ioctl,
1377 .hw_params = snd_intel8x0_hw_params,
1378 .hw_free = snd_intel8x0_hw_free,
1379 .prepare = snd_intel8x0_pcm_prepare,
1380 .trigger = snd_intel8x0_pcm_trigger,
1381 .pointer = snd_intel8x0_pcm_pointer,
1382};
1383
1384static snd_pcm_ops_t snd_intel8x0_capture2_ops = {
1385 .open = snd_intel8x0_capture2_open,
1386 .close = snd_intel8x0_capture2_close,
1387 .ioctl = snd_pcm_lib_ioctl,
1388 .hw_params = snd_intel8x0_hw_params,
1389 .hw_free = snd_intel8x0_hw_free,
1390 .prepare = snd_intel8x0_pcm_prepare,
1391 .trigger = snd_intel8x0_pcm_trigger,
1392 .pointer = snd_intel8x0_pcm_pointer,
1393};
1394
1395static snd_pcm_ops_t snd_intel8x0_spdif_ops = {
1396 .open = snd_intel8x0_spdif_open,
1397 .close = snd_intel8x0_spdif_close,
1398 .ioctl = snd_pcm_lib_ioctl,
1399 .hw_params = snd_intel8x0_hw_params,
1400 .hw_free = snd_intel8x0_hw_free,
1401 .prepare = snd_intel8x0_pcm_prepare,
1402 .trigger = snd_intel8x0_pcm_trigger,
1403 .pointer = snd_intel8x0_pcm_pointer,
1404};
1405
1406static snd_pcm_ops_t snd_intel8x0_ali_playback_ops = {
1407 .open = snd_intel8x0_playback_open,
1408 .close = snd_intel8x0_playback_close,
1409 .ioctl = snd_pcm_lib_ioctl,
1410 .hw_params = snd_intel8x0_hw_params,
1411 .hw_free = snd_intel8x0_hw_free,
1412 .prepare = snd_intel8x0_pcm_prepare,
1413 .trigger = snd_intel8x0_ali_trigger,
1414 .pointer = snd_intel8x0_pcm_pointer,
1415};
1416
1417static snd_pcm_ops_t snd_intel8x0_ali_capture_ops = {
1418 .open = snd_intel8x0_capture_open,
1419 .close = snd_intel8x0_capture_close,
1420 .ioctl = snd_pcm_lib_ioctl,
1421 .hw_params = snd_intel8x0_hw_params,
1422 .hw_free = snd_intel8x0_hw_free,
1423 .prepare = snd_intel8x0_pcm_prepare,
1424 .trigger = snd_intel8x0_ali_trigger,
1425 .pointer = snd_intel8x0_pcm_pointer,
1426};
1427
1428static snd_pcm_ops_t snd_intel8x0_ali_capture_mic_ops = {
1429 .open = snd_intel8x0_mic_open,
1430 .close = snd_intel8x0_mic_close,
1431 .ioctl = snd_pcm_lib_ioctl,
1432 .hw_params = snd_intel8x0_hw_params,
1433 .hw_free = snd_intel8x0_hw_free,
1434 .prepare = snd_intel8x0_pcm_prepare,
1435 .trigger = snd_intel8x0_ali_trigger,
1436 .pointer = snd_intel8x0_pcm_pointer,
1437};
1438
1439static snd_pcm_ops_t snd_intel8x0_ali_ac97spdifout_ops = {
1440 .open = snd_intel8x0_ali_ac97spdifout_open,
1441 .close = snd_intel8x0_ali_ac97spdifout_close,
1442 .ioctl = snd_pcm_lib_ioctl,
1443 .hw_params = snd_intel8x0_hw_params,
1444 .hw_free = snd_intel8x0_hw_free,
1445 .prepare = snd_intel8x0_pcm_prepare,
1446 .trigger = snd_intel8x0_ali_trigger,
1447 .pointer = snd_intel8x0_pcm_pointer,
1448};
1449
1450static snd_pcm_ops_t snd_intel8x0_ali_spdifin_ops = {
1451 .open = snd_intel8x0_ali_spdifin_open,
1452 .close = snd_intel8x0_ali_spdifin_close,
1453 .ioctl = snd_pcm_lib_ioctl,
1454 .hw_params = snd_intel8x0_hw_params,
1455 .hw_free = snd_intel8x0_hw_free,
1456 .prepare = snd_intel8x0_pcm_prepare,
1457 .trigger = snd_intel8x0_pcm_trigger,
1458 .pointer = snd_intel8x0_pcm_pointer,
1459};
1460
1461#if 0 // NYI
1462static snd_pcm_ops_t snd_intel8x0_ali_spdifout_ops = {
1463 .open = snd_intel8x0_ali_spdifout_open,
1464 .close = snd_intel8x0_ali_spdifout_close,
1465 .ioctl = snd_pcm_lib_ioctl,
1466 .hw_params = snd_intel8x0_hw_params,
1467 .hw_free = snd_intel8x0_hw_free,
1468 .prepare = snd_intel8x0_pcm_prepare,
1469 .trigger = snd_intel8x0_pcm_trigger,
1470 .pointer = snd_intel8x0_pcm_pointer,
1471};
1472#endif // NYI
1473
1474
1475struct ich_pcm_table {
1476 char *suffix;
1477 snd_pcm_ops_t *playback_ops;
1478 snd_pcm_ops_t *capture_ops;
1479 size_t prealloc_size;
1480 size_t prealloc_max_size;
1481 int ac97_idx;
1482};
1483
1484static int __devinit snd_intel8x0_pcm1(struct intel8x0 *chip, int device, struct ich_pcm_table *rec)
1485{
1486 snd_pcm_t *pcm;
1487 int err;
1488 char name[32];
1489
1490 if (rec->suffix)
1491 sprintf(name, "Intel ICH - %s", rec->suffix);
1492 else
1493 strcpy(name, "Intel ICH");
1494 err = snd_pcm_new(chip->card, name, device,
1495 rec->playback_ops ? 1 : 0,
1496 rec->capture_ops ? 1 : 0, &pcm);
1497 if (err < 0)
1498 return err;
1499
1500 if (rec->playback_ops)
1501 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, rec->playback_ops);
1502 if (rec->capture_ops)
1503 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, rec->capture_ops);
1504
1505 pcm->private_data = chip;
1506 pcm->info_flags = 0;
1507 if (rec->suffix)
1508 sprintf(pcm->name, "%s - %s", chip->card->shortname, rec->suffix);
1509 else
1510 strcpy(pcm->name, chip->card->shortname);
1511 chip->pcm[device] = pcm;
1512
1513 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(chip->pci),
1514 rec->prealloc_size, rec->prealloc_max_size);
1515
1516 return 0;
1517}
1518
1519static struct ich_pcm_table intel_pcms[] __devinitdata = {
1520 {
1521 .playback_ops = &snd_intel8x0_playback_ops,
1522 .capture_ops = &snd_intel8x0_capture_ops,
1523 .prealloc_size = 64 * 1024,
1524 .prealloc_max_size = 128 * 1024,
1525 },
1526 {
1527 .suffix = "MIC ADC",
1528 .capture_ops = &snd_intel8x0_capture_mic_ops,
1529 .prealloc_size = 0,
1530 .prealloc_max_size = 128 * 1024,
1531 .ac97_idx = ICHD_MIC,
1532 },
1533 {
1534 .suffix = "MIC2 ADC",
1535 .capture_ops = &snd_intel8x0_capture_mic2_ops,
1536 .prealloc_size = 0,
1537 .prealloc_max_size = 128 * 1024,
1538 .ac97_idx = ICHD_MIC2,
1539 },
1540 {
1541 .suffix = "ADC2",
1542 .capture_ops = &snd_intel8x0_capture2_ops,
1543 .prealloc_size = 0,
1544 .prealloc_max_size = 128 * 1024,
1545 .ac97_idx = ICHD_PCM2IN,
1546 },
1547 {
1548 .suffix = "IEC958",
1549 .playback_ops = &snd_intel8x0_spdif_ops,
1550 .prealloc_size = 64 * 1024,
1551 .prealloc_max_size = 128 * 1024,
1552 .ac97_idx = ICHD_SPBAR,
1553 },
1554};
1555
1556static struct ich_pcm_table nforce_pcms[] __devinitdata = {
1557 {
1558 .playback_ops = &snd_intel8x0_playback_ops,
1559 .capture_ops = &snd_intel8x0_capture_ops,
1560 .prealloc_size = 64 * 1024,
1561 .prealloc_max_size = 128 * 1024,
1562 },
1563 {
1564 .suffix = "MIC ADC",
1565 .capture_ops = &snd_intel8x0_capture_mic_ops,
1566 .prealloc_size = 0,
1567 .prealloc_max_size = 128 * 1024,
1568 .ac97_idx = NVD_MIC,
1569 },
1570 {
1571 .suffix = "IEC958",
1572 .playback_ops = &snd_intel8x0_spdif_ops,
1573 .prealloc_size = 64 * 1024,
1574 .prealloc_max_size = 128 * 1024,
1575 .ac97_idx = NVD_SPBAR,
1576 },
1577};
1578
1579static struct ich_pcm_table ali_pcms[] __devinitdata = {
1580 {
1581 .playback_ops = &snd_intel8x0_ali_playback_ops,
1582 .capture_ops = &snd_intel8x0_ali_capture_ops,
1583 .prealloc_size = 64 * 1024,
1584 .prealloc_max_size = 128 * 1024,
1585 },
1586 {
1587 .suffix = "MIC ADC",
1588 .capture_ops = &snd_intel8x0_ali_capture_mic_ops,
1589 .prealloc_size = 0,
1590 .prealloc_max_size = 128 * 1024,
1591 .ac97_idx = ALID_MIC,
1592 },
1593 {
1594 .suffix = "IEC958",
1595 .playback_ops = &snd_intel8x0_ali_ac97spdifout_ops,
1596 .capture_ops = &snd_intel8x0_ali_spdifin_ops,
1597 .prealloc_size = 64 * 1024,
1598 .prealloc_max_size = 128 * 1024,
1599 .ac97_idx = ALID_AC97SPDIFOUT,
1600 },
1601#if 0 // NYI
1602 {
1603 .suffix = "HW IEC958",
1604 .playback_ops = &snd_intel8x0_ali_spdifout_ops,
1605 .prealloc_size = 64 * 1024,
1606 .prealloc_max_size = 128 * 1024,
1607 },
1608#endif
1609};
1610
1611
1612static int __devinit snd_intel8x0_pcm(struct intel8x0 *chip)
1613{
1614 int i, tblsize, device, err;
1615 struct ich_pcm_table *tbl, *rec;
1616
1617 switch (chip->device_type) {
1618 case DEVICE_INTEL_ICH4:
1619 case DEVICE_INTEL_ICH5:
1620 tbl = intel_pcms;
1621 tblsize = ARRAY_SIZE(intel_pcms);
1622 break;
1623 case DEVICE_NFORCE:
1624 tbl = nforce_pcms;
1625 tblsize = ARRAY_SIZE(nforce_pcms);
1626 break;
1627 case DEVICE_ALI:
1628 tbl = ali_pcms;
1629 tblsize = ARRAY_SIZE(ali_pcms);
1630 break;
1631 default:
1632 tbl = intel_pcms;
1633 tblsize = 2;
1634 break;
1635 }
1636
1637 device = 0;
1638 for (i = 0; i < tblsize; i++) {
1639 rec = tbl + i;
1640 if (i > 0 && rec->ac97_idx) {
1641 /* activate PCM only when associated AC'97 codec */
1642 if (! chip->ichd[rec->ac97_idx].pcm)
1643 continue;
1644 }
1645 err = snd_intel8x0_pcm1(chip, device, rec);
1646 if (err < 0)
1647 return err;
1648 device++;
1649 }
1650
1651 chip->pcm_devs = device;
1652 return 0;
1653}
1654
1655
1656/*
1657 * Mixer part
1658 */
1659
1660static void snd_intel8x0_mixer_free_ac97_bus(ac97_bus_t *bus)
1661{
1662 struct intel8x0 *chip = bus->private_data;
1663 chip->ac97_bus = NULL;
1664}
1665
1666static void snd_intel8x0_mixer_free_ac97(ac97_t *ac97)
1667{
1668 struct intel8x0 *chip = ac97->private_data;
1669 chip->ac97[ac97->num] = NULL;
1670}
1671
1672static struct ac97_pcm ac97_pcm_defs[] __devinitdata = {
1673 /* front PCM */
1674 {
1675 .exclusive = 1,
1676 .r =
1677 {
1678 {
1679 .slots = (1 << AC97_SLOT_PCM_LEFT) |
1680 (1 << AC97_SLOT_PCM_RIGHT) |
1681 (1 << AC97_SLOT_PCM_CENTER) |
1682 (1 << AC97_SLOT_PCM_SLEFT) |
1683 (1 << AC97_SLOT_PCM_SRIGHT) |
1684 (1 << AC97_SLOT_LFE)
1685 },
1686 {
1687 .slots = (1 << AC97_SLOT_PCM_LEFT) |
1688 (1 << AC97_SLOT_PCM_RIGHT) |
1689 (1 << AC97_SLOT_PCM_LEFT_0) |
1690 (1 << AC97_SLOT_PCM_RIGHT_0)
1691 }
1692 }
1693 },
1694 /* PCM IN #1 */
1695 {
1696 .stream = 1,
1697 .exclusive = 1,
1698 .r = { {
1699 .slots = (1 << AC97_SLOT_PCM_LEFT) |
1700 (1 << AC97_SLOT_PCM_RIGHT)
1701 }
1702 }
1703 },
1704 /* MIC IN #1 */
1705 {
1706 .stream = 1,
1707 .exclusive = 1,
1708 .r = { {
1709 .slots = (1 << AC97_SLOT_MIC)
1710 }
1711 }
1712 },
1713 /* S/PDIF PCM */
1714 {
1715 .exclusive = 1,
1716 .spdif = 1,
1717 .r = { {
1718 .slots = (1 << AC97_SLOT_SPDIF_LEFT2) |
1719 (1 << AC97_SLOT_SPDIF_RIGHT2)
1720 }
1721 }
1722 },
1723 /* PCM IN #2 */
1724 {
1725 .stream = 1,
1726 .exclusive = 1,
1727 .r = { {
1728 .slots = (1 << AC97_SLOT_PCM_LEFT) |
1729 (1 << AC97_SLOT_PCM_RIGHT)
1730 }
1731 }
1732 },
1733 /* MIC IN #2 */
1734 {
1735 .stream = 1,
1736 .exclusive = 1,
1737 .r = { {
1738 .slots = (1 << AC97_SLOT_MIC)
1739 }
1740 }
1741 },
1742};
1743
1744static struct ac97_quirk ac97_quirks[] __devinitdata = {
1745 {
1746 .subvendor = 0x0e11,
1747 .subdevice = 0x008a,
1748 .name = "Compaq Evo W4000", /* AD1885 */
1749 .type = AC97_TUNE_HP_ONLY
1750 },
1751 {
1752 .subvendor = 0x0e11,
1753 .subdevice = 0x00b8,
1754 .name = "Compaq Evo D510C",
1755 .type = AC97_TUNE_HP_ONLY
1756 },
1757 {
1758 .subvendor = 0x0e11,
1759 .subdevice = 0x0860,
1760 .name = "HP/Compaq nx7010",
1761 .type = AC97_TUNE_MUTE_LED
1762 },
1763 {
1764 .subvendor = 0x1014,
1765 .subdevice = 0x1f00,
1766 .name = "MS-9128",
1767 .type = AC97_TUNE_ALC_JACK
1768 },
1769 {
1770 .subvendor = 0x1014,
1771 .subdevice = 0x0267,
1772 .name = "IBM NetVista A30p", /* AD1981B */
1773 .type = AC97_TUNE_HP_ONLY
1774 },
1775 {
1776 .subvendor = 0x1025,
1777 .subdevice = 0x0083,
1778 .name = "Acer Aspire 3003LCi",
1779 .type = AC97_TUNE_HP_ONLY
1780 },
1781 {
1782 .subvendor = 0x1028,
1783 .subdevice = 0x00d8,
1784 .name = "Dell Precision 530", /* AD1885 */
1785 .type = AC97_TUNE_HP_ONLY
1786 },
1787 {
1788 .subvendor = 0x1028,
1789 .subdevice = 0x010d,
1790 .name = "Dell", /* which model? AD1885 */
1791 .type = AC97_TUNE_HP_ONLY
1792 },
1793 {
1794 .subvendor = 0x1028,
1795 .subdevice = 0x0126,
1796 .name = "Dell Optiplex GX260", /* AD1981A */
1797 .type = AC97_TUNE_HP_ONLY
1798 },
1799 {
1800 .subvendor = 0x1028,
1801 .subdevice = 0x012c,
1802 .name = "Dell Precision 650", /* AD1981A */
1803 .type = AC97_TUNE_HP_ONLY
1804 },
1805 {
1806 .subvendor = 0x1028,
1807 .subdevice = 0x012d,
1808 .name = "Dell Precision 450", /* AD1981B*/
1809 .type = AC97_TUNE_HP_ONLY
1810 },
1811 {
1812 .subvendor = 0x1028,
1813 .subdevice = 0x0147,
1814 .name = "Dell", /* which model? AD1981B*/
1815 .type = AC97_TUNE_HP_ONLY
1816 },
1817 {
1818 .subvendor = 0x1028,
1819 .subdevice = 0x0151,
1820 .name = "Dell Optiplex GX270", /* AD1981B */
1821 .type = AC97_TUNE_HP_ONLY
1822 },
1823 {
1824 .subvendor = 0x1028,
1825 .subdevice = 0x0163,
1826 .name = "Dell Unknown", /* STAC9750/51 */
1827 .type = AC97_TUNE_HP_ONLY
1828 },
1829 {
1830 .subvendor = 0x1028,
1831 .subdevice = 0x0191,
1832 .name = "Dell Inspiron 8600",
1833 .type = AC97_TUNE_HP_ONLY
1834 },
1835 {
1836 .subvendor = 0x103c,
1837 .subdevice = 0x006d,
1838 .name = "HP zv5000",
1839 .type = AC97_TUNE_MUTE_LED /*AD1981B*/
1840 },
1841 { /* FIXME: which codec? */
1842 .subvendor = 0x103c,
1843 .subdevice = 0x00c3,
1844 .name = "HP xw6000",
1845 .type = AC97_TUNE_HP_ONLY
1846 },
1847 {
1848 .subvendor = 0x103c,
1849 .subdevice = 0x088c,
1850 .name = "HP nc8000",
1851 .type = AC97_TUNE_MUTE_LED
1852 },
1853 {
1854 .subvendor = 0x103c,
1855 .subdevice = 0x0890,
1856 .name = "HP nc6000",
1857 .type = AC97_TUNE_MUTE_LED
1858 },
1859 {
1860 .subvendor = 0x103c,
1861 .subdevice = 0x0934,
1862 .name = "HP nx8220",
1863 .type = AC97_TUNE_MUTE_LED
1864 },
1865 {
1866 .subvendor = 0x103c,
1867 .subdevice = 0x129d,
1868 .name = "HP xw8000",
1869 .type = AC97_TUNE_HP_ONLY
1870 },
1871 {
1872 .subvendor = 0x103c,
1873 .subdevice = 0x0938,
1874 .name = "HP nc4200",
1875 .type = AC97_TUNE_HP_MUTE_LED
1876 },
1877 {
1878 .subvendor = 0x103c,
1879 .subdevice = 0x099c,
1880 .name = "HP nc6120",
1881 .type = AC97_TUNE_HP_MUTE_LED
1882 },
1883 {
1884 .subvendor = 0x103c,
1885 .subdevice = 0x0944,
1886 .name = "HP nx6110/nc6120",
1887 .type = AC97_TUNE_HP_MUTE_LED
1888 },
1889 {
1890 .subvendor = 0x103c,
1891 .subdevice = 0x0934,
1892 .name = "HP nc8220",
1893 .type = AC97_TUNE_HP_MUTE_LED
1894 },
1895 {
1896 .subvendor = 0x103c,
1897 .subdevice = 0x12f1,
1898 .name = "HP xw8200", /* AD1981B*/
1899 .type = AC97_TUNE_HP_ONLY
1900 },
1901 {
1902 .subvendor = 0x103c,
1903 .subdevice = 0x12f2,
1904 .name = "HP xw6200",
1905 .type = AC97_TUNE_HP_ONLY
1906 },
1907 {
1908 .subvendor = 0x103c,
1909 .subdevice = 0x3008,
1910 .name = "HP xw4200", /* AD1981B*/
1911 .type = AC97_TUNE_HP_ONLY
1912 },
1913 {
1914 .subvendor = 0x104d,
1915 .subdevice = 0x8197,
1916 .name = "Sony S1XP",
1917 .type = AC97_TUNE_INV_EAPD
1918 },
1919 {
1920 .subvendor = 0x1043,
1921 .subdevice = 0x80f3,
1922 .name = "ASUS ICH5/AD1985",
1923 .type = AC97_TUNE_AD_SHARING
1924 },
1925 {
1926 .subvendor = 0x10cf,
1927 .subdevice = 0x11c3,
1928 .name = "Fujitsu-Siemens E4010",
1929 .type = AC97_TUNE_HP_ONLY
1930 },
1931 {
1932 .subvendor = 0x10cf,
1933 .subdevice = 0x1225,
1934 .name = "Fujitsu-Siemens T3010",
1935 .type = AC97_TUNE_HP_ONLY
1936 },
1937 {
1938 .subvendor = 0x10cf,
1939 .subdevice = 0x1253,
1940 .name = "Fujitsu S6210", /* STAC9750/51 */
1941 .type = AC97_TUNE_HP_ONLY
1942 },
1943 {
1944 .subvendor = 0x10cf,
1945 .subdevice = 0x12ec,
1946 .name = "Fujitsu-Siemens 4010",
1947 .type = AC97_TUNE_HP_ONLY
1948 },
1949 {
1950 .subvendor = 0x10cf,
1951 .subdevice = 0x12f2,
1952 .name = "Fujitsu-Siemens Celsius H320",
1953 .type = AC97_TUNE_SWAP_HP
1954 },
1955 {
1956 .subvendor = 0x10f1,
1957 .subdevice = 0x2665,
1958 .name = "Fujitsu-Siemens Celsius", /* AD1981? */
1959 .type = AC97_TUNE_HP_ONLY
1960 },
1961 {
1962 .subvendor = 0x10f1,
1963 .subdevice = 0x2885,
1964 .name = "AMD64 Mobo", /* ALC650 */
1965 .type = AC97_TUNE_HP_ONLY
1966 },
1967 {
1968 .subvendor = 0x110a,
1969 .subdevice = 0x0056,
1970 .name = "Fujitsu-Siemens Scenic", /* AD1981? */
1971 .type = AC97_TUNE_HP_ONLY
1972 },
1973 {
1974 .subvendor = 0x11d4,
1975 .subdevice = 0x5375,
1976 .name = "ADI AD1985 (discrete)",
1977 .type = AC97_TUNE_HP_ONLY
1978 },
1979 {
1980 .subvendor = 0x1462,
1981 .subdevice = 0x5470,
1982 .name = "MSI P4 ATX 645 Ultra",
1983 .type = AC97_TUNE_HP_ONLY
1984 },
1985 {
1986 .subvendor = 0x1734,
1987 .subdevice = 0x0088,
1988 .name = "Fujitsu-Siemens D1522", /* AD1981 */
1989 .type = AC97_TUNE_HP_ONLY
1990 },
1991 {
1992 .subvendor = 0x8086,
1993 .subdevice = 0x2000,
1994 .mask = 0xfff0,
1995 .name = "Intel ICH5/AD1985",
1996 .type = AC97_TUNE_AD_SHARING
1997 },
1998 {
1999 .subvendor = 0x8086,
2000 .subdevice = 0x4000,
2001 .mask = 0xfff0,
2002 .name = "Intel ICH5/AD1985",
2003 .type = AC97_TUNE_AD_SHARING
2004 },
2005 {
2006 .subvendor = 0x8086,
2007 .subdevice = 0x4856,
2008 .name = "Intel D845WN (82801BA)",
2009 .type = AC97_TUNE_SWAP_HP
2010 },
2011 {
2012 .subvendor = 0x8086,
2013 .subdevice = 0x4d44,
2014 .name = "Intel D850EMV2", /* AD1885 */
2015 .type = AC97_TUNE_HP_ONLY
2016 },
2017 {
2018 .subvendor = 0x8086,
2019 .subdevice = 0x4d56,
2020 .name = "Intel ICH/AD1885",
2021 .type = AC97_TUNE_HP_ONLY
2022 },
2023 {
2024 .subvendor = 0x8086,
2025 .subdevice = 0x6000,
2026 .mask = 0xfff0,
2027 .name = "Intel ICH5/AD1985",
2028 .type = AC97_TUNE_AD_SHARING
2029 },
2030 {
2031 .subvendor = 0x8086,
2032 .subdevice = 0xe000,
2033 .mask = 0xfff0,
2034 .name = "Intel ICH5/AD1985",
2035 .type = AC97_TUNE_AD_SHARING
2036 },
2037#if 0 /* FIXME: this seems wrong on most boards */
2038 {
2039 .subvendor = 0x8086,
2040 .subdevice = 0xa000,
2041 .mask = 0xfff0,
2042 .name = "Intel ICH5/AD1985",
2043 .type = AC97_TUNE_HP_ONLY
2044 },
2045#endif
2046 {0} /* terminator */
2047};
2048
2049static int __devinit snd_intel8x0_mixer(struct intel8x0 *chip, int ac97_clock, char *quirk_override)
2050{
2051 ac97_bus_t *pbus;
2052 ac97_template_t ac97;
2053 int err;
2054 unsigned int i, codecs;
2055 unsigned int glob_sta = 0;
2056 ac97_bus_ops_t *ops;
2057 static ac97_bus_ops_t standard_bus_ops = {
2058 0,snd_intel8x0_codec_write,
2059 snd_intel8x0_codec_read,0,0
2060 };
2061 static ac97_bus_ops_t ali_bus_ops = {
2062 0,snd_intel8x0_ali_codec_write,
2063 snd_intel8x0_ali_codec_read,0,0
2064 };
2065 chip->spdif_idx = -1; /* use PCMOUT (or disabled) */
2066 switch (chip->device_type) {
2067 case DEVICE_NFORCE:
2068 chip->spdif_idx = NVD_SPBAR;
2069 break;
2070 case DEVICE_ALI:
2071 chip->spdif_idx = ALID_AC97SPDIFOUT;
2072 break;
2073 case DEVICE_INTEL_ICH4:
2074 case DEVICE_INTEL_ICH5:
2075 chip->spdif_idx = ICHD_SPBAR;
2076 break;
2077 };
2078
2079 chip->in_ac97_init = 1;
2080
2081 memset(&ac97, 0, sizeof(ac97));
2082 ac97.private_data = chip;
2083 ac97.private_free = snd_intel8x0_mixer_free_ac97;
2084 ac97.scaps = AC97_SCAP_SKIP_MODEM;
2085 if (chip->device_type != DEVICE_ALI) {
2086 glob_sta = igetdword(chip, ICHREG(GLOB_STA));
2087 ops = &standard_bus_ops;
2088 chip->in_sdin_init = 1;
2089 codecs = 0;
2090 for (i = 0; i < chip->max_codecs; i++) {
2091 if (! (glob_sta & chip->codec_bit[i]))
2092 continue;
2093 if (chip->device_type == DEVICE_INTEL_ICH4 ||
2094 chip->device_type == DEVICE_INTEL_ICH5) {
2095 snd_intel8x0_codec_read_test(chip, codecs);
2096 chip->ac97_sdin[codecs] =
2097 igetbyte(chip, ICHREG(SDM)) & ICH_LDI_MASK;
2098 snd_assert(chip->ac97_sdin[codecs] < 3,
2099 chip->ac97_sdin[codecs] = 0);
2100 } else
2101 chip->ac97_sdin[codecs] = i;
2102 codecs++;
2103 chip->in_sdin_init = 1;
2104 }
2105 chip->in_sdin_init = 0;
2106 if (! codecs)
2107 codecs = 1;
2108 } else {
2109 ops = &ali_bus_ops;
2110 codecs = 1;
2111 /* detect the secondary codec */
2112 for (i = 0; i < 100; i++) {
2113 unsigned int reg = igetdword(chip, ICHREG(ALI_RTSR));
2114 if (reg & 0x40) {
2115 codecs = 2;
2116 break;
2117 }
2118 iputdword(chip, ICHREG(ALI_RTSR), reg | 0x40);
2119 udelay(1);
2120 }
2121 }
2122 if ((err = snd_ac97_bus(chip->card, 0, ops, chip, &pbus)) < 0)
2123 goto __err;
2124 pbus->private_free = snd_intel8x0_mixer_free_ac97_bus;
2125 if (ac97_clock >= 8000 && ac97_clock <= 48000)
2126 pbus->clock = ac97_clock;
2127 /* FIXME: my test board doesn't work well with VRA... */
2128 if (chip->device_type == DEVICE_ALI)
2129 pbus->no_vra = 1;
2130 else
2131 pbus->dra = 1;
2132 chip->ac97_bus = pbus;
2133 chip->ncodecs = codecs;
2134
2135 ac97.pci = chip->pci;
2136 for (i = 0; i < codecs; i++) {
2137 ac97.num = i;
2138 if ((err = snd_ac97_mixer(pbus, &ac97, &chip->ac97[i])) < 0) {
2139 if (err != -EACCES)
2140 snd_printk(KERN_ERR "Unable to initialize codec #%d\n", i);
2141 if (i == 0)
2142 goto __err;
2143 continue;
2144 }
2145 }
2146 /* tune up the primary codec */
2147 snd_ac97_tune_hardware(chip->ac97[0], ac97_quirks, quirk_override);
2148 /* enable separate SDINs for ICH4 */
2149 if (chip->device_type == DEVICE_INTEL_ICH4 ||
2150 chip->device_type == DEVICE_INTEL_ICH5)
2151 pbus->isdin = 1;
2152 /* find the available PCM streams */
2153 i = ARRAY_SIZE(ac97_pcm_defs);
2154 if (chip->device_type != DEVICE_INTEL_ICH4 &&
2155 chip->device_type != DEVICE_INTEL_ICH5)
2156 i -= 2; /* do not allocate PCM2IN and MIC2 */
2157 if (chip->spdif_idx < 0)
2158 i--; /* do not allocate S/PDIF */
2159 err = snd_ac97_pcm_assign(pbus, i, ac97_pcm_defs);
2160 if (err < 0)
2161 goto __err;
2162 chip->ichd[ICHD_PCMOUT].pcm = &pbus->pcms[0];
2163 chip->ichd[ICHD_PCMIN].pcm = &pbus->pcms[1];
2164 chip->ichd[ICHD_MIC].pcm = &pbus->pcms[2];
2165 if (chip->spdif_idx >= 0)
2166 chip->ichd[chip->spdif_idx].pcm = &pbus->pcms[3];
2167 if (chip->device_type == DEVICE_INTEL_ICH4 ||
2168 chip->device_type == DEVICE_INTEL_ICH5) {
2169 chip->ichd[ICHD_PCM2IN].pcm = &pbus->pcms[4];
2170 chip->ichd[ICHD_MIC2].pcm = &pbus->pcms[5];
2171 }
2172 /* enable separate SDINs for ICH4 */
2173 if (chip->device_type == DEVICE_INTEL_ICH4 ||
2174 chip->device_type == DEVICE_INTEL_ICH5) {
2175 struct ac97_pcm *pcm = chip->ichd[ICHD_PCM2IN].pcm;
2176 u8 tmp = igetbyte(chip, ICHREG(SDM));
2177 tmp &= ~(ICH_DI2L_MASK|ICH_DI1L_MASK);
2178 if (pcm) {
2179 tmp |= ICH_SE; /* steer enable for multiple SDINs */
2180 tmp |= chip->ac97_sdin[0] << ICH_DI1L_SHIFT;
2181 for (i = 1; i < 4; i++) {
2182 if (pcm->r[0].codec[i]) {
2183 tmp |= chip->ac97_sdin[pcm->r[0].codec[1]->num] << ICH_DI2L_SHIFT;
2184 break;
2185 }
2186 }
2187 } else {
2188 tmp &= ~ICH_SE; /* steer disable */
2189 }
2190 iputbyte(chip, ICHREG(SDM), tmp);
2191 }
2192 if (pbus->pcms[0].r[0].slots & (1 << AC97_SLOT_PCM_SLEFT)) {
2193 chip->multi4 = 1;
2194 if (pbus->pcms[0].r[0].slots & (1 << AC97_SLOT_LFE))
2195 chip->multi6 = 1;
2196 }
2197 if (pbus->pcms[0].r[1].rslots[0]) {
2198 chip->dra = 1;
2199 }
2200 if (chip->device_type == DEVICE_INTEL_ICH4 ||
2201 chip->device_type == DEVICE_INTEL_ICH5) {
2202 if ((igetdword(chip, ICHREG(GLOB_STA)) & ICH_SAMPLE_CAP) == ICH_SAMPLE_16_20)
2203 chip->smp20bit = 1;
2204 }
2205 if (chip->device_type == DEVICE_NFORCE) {
2206 /* 48kHz only */
2207 chip->ichd[chip->spdif_idx].pcm->rates = SNDRV_PCM_RATE_48000;
2208 }
2209
2210 if (chip->device_type == DEVICE_INTEL_ICH4 ||
2211 chip->device_type == DEVICE_INTEL_ICH5) {
2212 /* use slot 10/11 for SPDIF */
2213 u32 val;
2214 val = igetdword(chip, ICHREG(GLOB_CNT)) & ~ICH_PCM_SPDIF_MASK;
2215 val |= ICH_PCM_SPDIF_1011;
2216 iputdword(chip, ICHREG(GLOB_CNT), val);
2217 snd_ac97_update_bits(chip->ac97[0], AC97_EXTENDED_STATUS, 0x03 << 4, 0x03 << 4);
2218 }
2219 chip->in_ac97_init = 0;
2220 return 0;
2221
2222 __err:
2223 /* clear the cold-reset bit for the next chance */
2224 if (chip->device_type != DEVICE_ALI)
2225 iputdword(chip, ICHREG(GLOB_CNT), igetdword(chip, ICHREG(GLOB_CNT)) & ~ICH_AC97COLD);
2226 return err;
2227}
2228
2229
2230/*
2231 *
2232 */
2233
2234static void do_ali_reset(struct intel8x0 *chip)
2235{
2236 iputdword(chip, ICHREG(ALI_SCR), ICH_ALI_SC_RESET);
2237 iputdword(chip, ICHREG(ALI_FIFOCR1), 0x83838383);
2238 iputdword(chip, ICHREG(ALI_FIFOCR2), 0x83838383);
2239 iputdword(chip, ICHREG(ALI_FIFOCR3), 0x83838383);
2240 iputdword(chip, ICHREG(ALI_INTERFACECR),
2241 ICH_ALI_IF_PI|ICH_ALI_IF_PO);
2242 iputdword(chip, ICHREG(ALI_INTERRUPTCR), 0x00000000);
2243 iputdword(chip, ICHREG(ALI_INTERRUPTSR), 0x00000000);
2244}
2245
2246#define do_delay(chip) do {\
2247 set_current_state(TASK_UNINTERRUPTIBLE);\
2248 schedule_timeout(1);\
2249 } while (0)
2250
2251static int snd_intel8x0_ich_chip_init(struct intel8x0 *chip, int probing)
2252{
2253 unsigned long end_time;
2254 unsigned int cnt, status, nstatus,i;
2255
2256#ifdef DEBUG
2257 dprintf(("ICH chip init begins"));
2258#endif
2259 /* put logic to right state */
2260 /* first clear status bits */
2261#if 1 // noone do it. wtf? //vladest 06.10.2003 13:51
2262 status = ICH_RCS | ICH_MCINT | ICH_POINT | ICH_PIINT;
2263 if (chip->device_type == DEVICE_NFORCE)
2264 status |= ICH_NVSPINT;
2265 cnt = igetdword(chip, ICHREG(GLOB_STA));
2266 iputdword(chip, ICHREG(GLOB_STA), cnt & status);
2267#endif
2268 // hmm. at least we should try
2269 //iputdword(chip, ICHREG(GLOB_CNT), igetdword(chip, ICHREG(GLOB_CNT)) & ~ICH_AC97COLD);
2270 /* ACLink on, 2 channels */
2271 cnt = igetdword(chip, ICHREG(GLOB_CNT));
2272 // added by vladest
2273 // cnt &= ~ICH_ACLINK;
2274 cnt &= ~(ICH_ACLINK | ICH_PCM_246_MASK);
2275 cnt |= (cnt & ICH_AC97COLD) == 0 ? ICH_AC97COLD : ICH_AC97WARM;
2276
2277 // ??? 25.03.2004 by vladest cnt &= ~(ICH_ACLINK | ICH_PCM_246_MASK);
2278 // FIXME!!! cmi drivers didnt uses ICH_PCM_246_MASK
2279 /* finish cold or do warm reset */
2280#ifdef DEBUG
2281 dprintf(("ICH chip init try to wake up ACLink with %x",cnt));
2282#endif
2283 iputdword(chip, ICHREG(GLOB_CNT), cnt);
2284// mdelay(500); //vladest 06.10.2003 15:08
2285 end_time = (jiffies + (HZ / 4)) + 1;
2286 i = 0;
2287 do {
2288 cnt=igetdword(chip, ICHREG(GLOB_CNT));
2289 if ((cnt & ICH_AC97WARM) == 0)
2290 goto __ok;
2291#ifdef DEBUG
2292 dprintf(("ICH chip init ACLink ON. try no %d got %x",i,cnt));
2293#endif
2294 do_delay(chip);
2295 i++;
2296 } while (i<100); //(time_after_eq(end_time, jiffies));
2297 snd_printk("AC'97 warm reset still in progress? [0x%x]\n", igetdword(chip, ICHREG(GLOB_CNT)));
2298 return -EIO;
2299__ok:
2300#ifdef DEBUG
2301 dprintf(("ICH chip init ACLink ON"));
2302#endif
2303
2304// mdelay(50);
2305
2306 if (probing) {
2307 /* wait for any codec ready status.
2308 * Once it becomes ready it should remain ready
2309 * as long as we do not disable the ac97 link.
2310 */
2311 end_time = jiffies + HZ;
2312 i = 0;
2313 do {
2314 status = igetdword(chip, ICHREG(GLOB_STA)) & chip->codec_isr_bits;;
2315 if (status)
2316 break;
2317 mdelay(1);
2318 //do_delay(chip);
2319 i++;
2320 } while (i<100);/*(time_after_eq(end_time, jiffies));*/
2321
2322 if (! status) {
2323 /* no codec is found */
2324 snd_printk(KERN_ERR "codec_ready: codec is not ready [0x%x]\n", igetdword(chip, ICHREG(GLOB_STA)));
2325 return -EIO;
2326 }
2327#ifdef DEBUG
2328 dprintf(("ICH chip init codec ready"));
2329#endif
2330// mdelay(50);
2331
2332 /* wait for other codecs ready status. */
2333 end_time = jiffies + HZ / 4;
2334 while (status != chip->codec_isr_bits &&
2335 time_after_eq(end_time, jiffies)) {
2336 do_delay(chip);
2337 status |= igetdword(chip, ICHREG(GLOB_STA)) &
2338 chip->codec_isr_bits;
2339 }
2340 } else {
2341 /* resume phase */
2342 int i;
2343 status = 0;
2344 for (i = 0; i < chip->ncodecs; i++)
2345 if (chip->ac97[i])
2346 status |= chip->codec_bit[chip->ac97_sdin[i]];
2347 /* wait until all the probed codecs are ready */
2348 end_time = jiffies + HZ;
2349 do {
2350 nstatus = igetdword(chip, ICHREG(GLOB_STA)) & chip->codec_isr_bits;;
2351 if (status == nstatus)
2352 break;
2353 do_delay(chip);
2354 } while (time_after_eq(end_time, jiffies));
2355 }
2356
2357 if (chip->device_type == DEVICE_SIS) {
2358 /* unmute the output on SIS7012 */
2359 iputword(chip, 0x4c, igetword(chip, 0x4c) | 1);
2360 }
2361 if (chip->device_type == DEVICE_NFORCE) {
2362 /* enable SPDIF interrupt */
2363 unsigned int val;
2364 pci_read_config_dword(chip->pci, 0x4c, &val);
2365 val |= 0x1000000;
2366 pci_write_config_dword(chip->pci, 0x4c, val);
2367 }
2368#ifdef DEBUG
2369 dprintf(("ICH chip init finished"));
2370#endif
2371
2372 return 0;
2373}
2374
2375static int snd_intel8x0_ali_chip_init(struct intel8x0 *chip, int probing)
2376{
2377 u32 reg;
2378 int i = 0;
2379
2380 reg = igetdword(chip, ICHREG(ALI_SCR));
2381 if ((reg & 2) == 0) /* Cold required */
2382 reg |= 2;
2383 else
2384 reg |= 1; /* Warm */
2385 reg &= ~0x80000000; /* ACLink on */
2386 iputdword(chip, ICHREG(ALI_SCR), reg);
2387
2388 for (i = 0; i < HZ / 2; i++) {
2389 if (! (igetdword(chip, ICHREG(ALI_INTERRUPTSR)) & ALI_INT_GPIO))
2390 goto __ok;
2391 do_delay(chip);
2392 }
2393 snd_printk(KERN_ERR "AC'97 reset failed.\n");
2394 if (probing)
2395 return -EIO;
2396
2397 __ok:
2398 for (i = 0; i < HZ / 2; i++) {
2399 reg = igetdword(chip, ICHREG(ALI_RTSR));
2400 if (reg & 0x80) /* primary codec */
2401 break;
2402 iputdword(chip, ICHREG(ALI_RTSR), reg | 0x80);
2403 do_delay(chip);
2404 }
2405
2406 do_ali_reset(chip);
2407 return 0;
2408}
2409
2410static int snd_intel8x0_chip_init(struct intel8x0 *chip, int probing)
2411{
2412 unsigned int i;
2413 int err;
2414
2415 if (chip->device_type != DEVICE_ALI) {
2416 if ((err = snd_intel8x0_ich_chip_init(chip, probing)) < 0)
2417 return err;
2418 iagetword(chip, 0); /* clear semaphore flag */
2419 } else {
2420 if ((err = snd_intel8x0_ali_chip_init(chip, probing)) < 0)
2421 return err;
2422 }
2423
2424 /* disable interrupts */
2425 for (i = 0; i < chip->bdbars_count; i++)
2426 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, 0x00);
2427 /* reset channels */
2428 for (i = 0; i < chip->bdbars_count; i++)
2429 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, ICH_RESETREGS);
2430 /* initialize Buffer Descriptor Lists */
2431 for (i = 0; i < chip->bdbars_count; i++)
2432 iputdword(chip, ICH_REG_OFF_BDBAR + chip->ichd[i].reg_offset, chip->ichd[i].bdbar_addr);
2433 return 0;
2434}
2435
2436static int snd_intel8x0_free(struct intel8x0 *chip)
2437{
2438 unsigned int i;
2439
2440 if (chip->irq < 0)
2441 goto __hw_end;
2442 /* disable interrupts */
2443 for (i = 0; i < chip->bdbars_count; i++)
2444 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, 0x00);
2445 /* reset channels */
2446 for (i = 0; i < chip->bdbars_count; i++)
2447 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, ICH_RESETREGS);
2448 if (chip->device_type == DEVICE_NFORCE) {
2449 /* stop the spdif interrupt */
2450 unsigned int val;
2451 pci_read_config_dword(chip->pci, 0x4c, &val);
2452 val &= ~0x1000000;
2453 pci_write_config_dword(chip->pci, 0x4c, val);
2454 }
2455 /* --- */
2456 synchronize_irq(chip->irq);
2457__hw_end:
2458 if (chip->irq >= 0)
2459 free_irq(chip->irq, (void *)chip);
2460 if (chip->bdbars.area)
2461 snd_dma_free_pages(&chip->bdbars);
2462 if (chip->remap_addr)
2463 iounmap((void *) chip->remap_addr);
2464 if (chip->remap_bmaddr)
2465 iounmap((void *) chip->remap_bmaddr);
2466 pci_release_regions(chip->pci);
2467 kfree(chip);
2468 return 0;
2469}
2470
2471#ifdef CONFIG_PM
2472/*
2473 * power management
2474 */
2475static int intel8x0_suspend(struct pci_dev *pci, pm_message_t state)
2476{
2477 struct snd_card *card = pci_get_drvdata(pci);
2478 struct intel8x0 *chip = card->private_data;
2479 int i;
2480
2481 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
2482
2483 for (i = 0; i < chip->pcm_devs; i++)
2484 snd_pcm_suspend_all(chip->pcm[i]);
2485
2486 for (i = 0; i < chip->ncodecs; i++)
2487 if (chip->ac97[i]) //Rudi: check, if codec present !!!
2488 snd_ac97_suspend(chip->ac97[i]);
2489 if (chip->device_type == DEVICE_INTEL_ICH4 ||
2490 chip->device_type == DEVICE_INTEL_ICH5)
2491 chip->sdm_saved = igetbyte(chip, ICHREG(SDM));
2492
2493 if (chip->irq >= 0)
2494 free_irq(chip->irq, (void *)chip);
2495 pci_disable_device(pci);
2496 pci_save_state(pci);
2497 return 0;
2498}
2499
2500static int intel8x0_resume(struct pci_dev *pci)
2501{
2502 struct snd_card *card = pci_get_drvdata(pci);
2503 struct intel8x0 *chip = card->private_data;
2504 int i;
2505
2506 pci_restore_state(pci);
2507 pci_enable_device(pci);
2508 pci_set_master(pci);
2509 request_irq(pci->irq, snd_intel8x0_interrupt, SA_INTERRUPT|SA_SHIRQ,
2510 card->shortname, (void *)chip);
2511 chip->irq = pci->irq;
2512 synchronize_irq(chip->irq);
2513 snd_intel8x0_chip_init(chip, 1);
2514 /* re-initialize mixer stuff */
2515 if (chip->device_type == DEVICE_INTEL_ICH4 ||
2516 chip->device_type == DEVICE_INTEL_ICH5) {
2517 /* enable separate SDINs for ICH4 */
2518 iputbyte(chip, ICHREG(SDM), chip->sdm_saved);
2519 /* use slot 10/11 for SPDIF */
2520 iputdword(chip, ICHREG(GLOB_CNT),
2521 (igetdword(chip, ICHREG(GLOB_CNT)) & ~ICH_PCM_SPDIF_MASK) |
2522 ICH_PCM_SPDIF_1011);
2523 }
2524
2525 for (i = 0; i < chip->ncodecs; i++)
2526 if (chip->ac97[i]) //Rudi: check, if codec present !!!
2527 snd_ac97_resume(chip->ac97[i]);
2528 /* resume status */
2529 for (i = 0; i < chip->bdbars_count; i++) {
2530 struct ichdev *ichdev = &chip->ichd[i];
2531 unsigned long port = ichdev->reg_offset;
2532 if (! ichdev->substream || ! ichdev->suspended)
2533 continue;
2534 if (ichdev->ichd == ICHD_PCMOUT)
2535 snd_intel8x0_setup_pcm_out(chip, ichdev->substream->runtime);
2536 iputdword(chip, port + ICH_REG_OFF_BDBAR, ichdev->bdbar_addr);
2537 iputbyte(chip, port + ICH_REG_OFF_LVI, ichdev->lvi);
2538 iputbyte(chip, port + ICH_REG_OFF_CIV, ichdev->civ);
2539 iputbyte(chip, port + ichdev->roff_sr, ICH_FIFOE | ICH_BCIS | ICH_LVBCI);
2540 }
2541 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
2542 return 0;
2543}
2544
2545#endif /* CONFIG_PM */
2546
2547#define INTEL8X0_TESTBUF_SIZE 32768 /* enough large for one shot */
2548
2549static void __devinit intel8x0_measure_ac97_clock(struct intel8x0 *chip)
2550{
2551 snd_pcm_substream_t *subs;
2552 struct ichdev *ichdev;
2553 unsigned long port;
2554 unsigned long pos, t;
2555 struct timeval start_time, stop_time;
2556
2557 if (chip->ac97_bus->clock != 48000)
2558 return; /* specified in module option */
2559
2560 subs = chip->pcm[0]->streams[0].substream;
2561 if (! subs || subs->dma_buffer.bytes < INTEL8X0_TESTBUF_SIZE) {
2562 snd_printk("no playback buffer allocated - aborting measure ac97 clock\n");
2563 return;
2564 }
2565 ichdev = &chip->ichd[ICHD_PCMOUT];
2566 ichdev->physbuf = subs->dma_buffer.addr;
2567 ichdev->size = chip->ichd[ICHD_PCMOUT].fragsize = INTEL8X0_TESTBUF_SIZE;
2568 ichdev->substream = NULL; /* don't process interrupts */
2569
2570 /* set rate */
2571 if (snd_ac97_set_rate(chip->ac97[0], AC97_PCM_FRONT_DAC_RATE, 48000) < 0) {
2572 snd_printk(KERN_ERR "cannot set ac97 rate: clock = %d\n", chip->ac97_bus->clock);
2573 return;
2574 }
2575 snd_intel8x0_setup_periods(chip, ichdev);
2576 port = ichdev->reg_offset;
2577 spin_lock_irq(&chip->reg_lock);
2578 /* trigger */
2579 if (chip->device_type != DEVICE_ALI)
2580 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_IOCE | ICH_STARTBM);
2581 else {
2582 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_IOCE);
2583 iputdword(chip, ICHREG(ALI_DMACR), 1 << ichdev->ali_slot);
2584 }
2585 do_gettimeofday(&start_time);
2586 spin_unlock_irq(&chip->reg_lock);
2587 mdelay(50);
2588
2589 spin_lock_irq(&chip->reg_lock);
2590 /* check the position */
2591 pos = ichdev->fragsize1;
2592 pos -= igetword(chip, ichdev->reg_offset + ichdev->roff_picb) << ichdev->pos_shift;
2593 pos += ichdev->position;
2594 do_gettimeofday(&stop_time);
2595 /* stop */
2596 if (chip->device_type == DEVICE_ALI) {
2597 iputdword(chip, ICHREG(ALI_DMACR), 1 << (ichdev->ali_slot + 16));
2598 iputbyte(chip, port + ICH_REG_OFF_CR, 0);
2599 while (igetbyte(chip, port + ICH_REG_OFF_CR))
2600 ;
2601 } else {
2602 iputbyte(chip, port + ICH_REG_OFF_CR, 0);
2603 while (!(igetbyte(chip, port + ichdev->roff_sr) & ICH_DCH))
2604 ;
2605 }
2606 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_RESETREGS);
2607 spin_unlock_irq(&chip->reg_lock);
2608
2609 t = stop_time.tv_sec - start_time.tv_sec;
2610 t *= 1000000;
2611 t += stop_time.tv_usec - start_time.tv_usec;
2612 printk(KERN_INFO "%s: measured %lu usecs\n", __FUNCTION__, t);
2613 if (t == 0) {
2614 snd_printk(KERN_ERR "?? calculation error..\n");
2615 return;
2616 }
2617 pos = (pos / 4) * 1000;
2618 pos = (pos / t) * 1000 + ((pos % t) * 1000) / t;
2619 if (pos < 40000 || pos >= 60000)
2620 /* abnormal value. hw problem? */
2621 printk(KERN_INFO "intel8x0: measured clock %ld rejected\n", pos);
2622 else if (pos < 47500 || pos > 48500)
2623 /* not 48000Hz, tuning the clock.. */
2624 chip->ac97_bus->clock = (chip->ac97_bus->clock * 48000) / pos;
2625 printk(KERN_INFO "intel8x0: clocking to %d\n", chip->ac97_bus->clock);
2626}
2627
2628#ifdef CONFIG_PROC_FS
2629static void snd_intel8x0_proc_read(snd_info_entry_t * entry,
2630 snd_info_buffer_t * buffer)
2631{
2632 struct intel8x0 *chip = entry->private_data;
2633 unsigned int tmp;
2634
2635 snd_iprintf(buffer, "Intel8x0\n\n");
2636 if (chip->device_type == DEVICE_ALI)
2637 return;
2638 tmp = igetdword(chip, ICHREG(GLOB_STA));
2639 snd_iprintf(buffer, "Global control : 0x%08x\n", igetdword(chip, ICHREG(GLOB_CNT)));
2640 snd_iprintf(buffer, "Global status : 0x%08x\n", tmp);
2641 if (chip->device_type == DEVICE_INTEL_ICH4 ||
2642 chip->device_type == DEVICE_INTEL_ICH5)
2643 snd_iprintf(buffer, "SDM : 0x%08x\n", igetdword(chip, ICHREG(SDM)));
2644 snd_iprintf(buffer, "AC'97 codecs ready :");
2645 if (tmp & chip->codec_isr_bits) {
2646 int i;
2647 static const char *codecs[3] = {
2648 "primary", "secondary", "tertiary"
2649 };
2650 for (i = 0; i < chip->max_codecs; i++)
2651 if (tmp & chip->codec_bit[i])
2652 snd_iprintf(buffer, " %s", codecs[i]);
2653 } else
2654 snd_iprintf(buffer, " none");
2655 snd_iprintf(buffer, "\n");
2656 if (chip->device_type == DEVICE_INTEL_ICH4 ||
2657 chip->device_type == DEVICE_SIS)
2658 snd_iprintf(buffer, "AC'97 codecs SDIN : %i %i %i\n",
2659 chip->ac97_sdin[0],
2660 chip->ac97_sdin[1],
2661 chip->ac97_sdin[2]);
2662}
2663
2664static void __devinit snd_intel8x0_proc_init(struct intel8x0 * chip)
2665{
2666 snd_info_entry_t *entry;
2667
2668 if (! snd_card_proc_new(chip->card, "intel8x0", &entry))
2669 snd_info_set_text_ops(entry, chip, 1024, snd_intel8x0_proc_read);
2670}
2671#else
2672#define snd_intel8x0_proc_init(x)
2673#endif
2674
2675static int snd_intel8x0_dev_free(snd_device_t *device)
2676{
2677 struct intel8x0 *chip = device->device_data;
2678 return snd_intel8x0_free(chip);
2679}
2680
2681struct ich_reg_info {
2682 unsigned int int_sta_mask;
2683 unsigned int offset;
2684};
2685
2686static unsigned int ich_codec_bits[3] = {
2687 ICH_PCR, ICH_SCR, ICH_TCR
2688};
2689static unsigned int sis_codec_bits[3] = {
2690 ICH_PCR, ICH_SCR, ICH_SIS_TCR
2691};
2692
2693static int __devinit snd_intel8x0_create(snd_card_t * card,
2694 struct pci_dev *pci,
2695 unsigned long device_type,
2696 struct intel8x0 ** r_intel8x0)
2697{
2698 struct intel8x0 *chip;
2699 int err;
2700 unsigned int i,pci_dword;
2701 unsigned int int_sta_masks;
2702 unsigned short pci_word;
2703 unsigned char pci_byte;
2704
2705 struct ichdev *ichdev;
2706#ifdef TARGET_OS2
2707 static snd_device_ops_t ops = {
2708 snd_intel8x0_dev_free,0,0,0
2709 };
2710#else
2711 static snd_device_ops_t ops = {
2712 .dev_free = snd_intel8x0_dev_free,
2713 };
2714#endif
2715 static unsigned int bdbars[] = {
2716 3, /* DEVICE_INTEL */
2717 6, /* DEVICE_INTEL_ICH4 */
2718 6, /* DEVICE_INTEL_ICH5 */
2719 3, /* DEVICE_SIS */
2720 6, /* DEVICE_ALI */
2721 4, /* DEVICE_NFORCE */
2722 };
2723 static struct ich_reg_info intel_regs[6] = {
2724 { ICH_PIINT, 0 },
2725 { ICH_POINT, 0x10 },
2726 { ICH_MCINT, 0x20 },
2727 { ICH_M2INT, 0x40 },
2728 { ICH_P2INT, 0x50 },
2729 { ICH_SPINT, 0x60 },
2730 };
2731 static struct ich_reg_info nforce_regs[4] = {
2732 { ICH_PIINT, 0 },
2733 { ICH_POINT, 0x10 },
2734 { ICH_MCINT, 0x20 },
2735 { ICH_NVSPINT, 0x70 },
2736 };
2737 static struct ich_reg_info ali_regs[6] = {
2738 { ALI_INT_PCMIN, 0x40 },
2739 { ALI_INT_PCMOUT, 0x50 },
2740 { ALI_INT_MICIN, 0x60 },
2741 { ALI_INT_CODECSPDIFOUT, 0x70 },
2742 { ALI_INT_SPDIFIN, 0xa0 },
2743 { ALI_INT_SPDIFOUT, 0xb0 },
2744 };
2745 struct ich_reg_info *tbl;
2746
2747 *r_intel8x0 = NULL;
2748
2749 if ((err = pci_enable_device(pci)) < 0)
2750 return err;
2751 pci_set_master(pci);
2752
2753// pci_write_config_byte(pci, 0x40, 0xff); // added by vladest
2754
2755 chip = kcalloc(1, sizeof(*chip), GFP_KERNEL);
2756 if (chip == NULL)
2757 return -ENOMEM;
2758 spin_lock_init(&chip->reg_lock);
2759 chip->device_type = device_type;
2760 chip->card = card;
2761 chip->pci = pci;
2762 chip->irq = -1;
2763 if ((err = pci_request_regions(pci, card->shortname)) < 0) {
2764 kfree(chip);
2765 return err;
2766 }
2767 if (device_type == DEVICE_ALI) {
2768 /* ALI5455 has no ac97 region */
2769 chip->bmaddr = pci_resource_start(pci, 0);
2770 goto port_inited;
2771 }
2772 /*
2773 ¥áâì €¢  ­î ­á .  €® ᬮâà¥âì. ¥à¢®¥: pci_cfg_space 54h,
2774 €¢  ¬« €èšå ¡šâ  㪠§ë¢ îâ á®áâ®ï­š¥ 皯 . ¥á«š â ¬ 11, â®
2775 ªà®¬¥ ª®­äš£á¯¥©á  ¡®«ìè¥ ­š å७  ­¥ à ¡®â ¥â.
2776 ’〠 ­ €® § ¯šá âì 00.
2777 ‚â®à®¥: ॣšáâà PCICMD, íâ® 16-¡šâ­ë© ॣšáâà ¯® ᬥ饭šî 04h
2778 ¢ cfg_space. šâ 1 ¢ëáâ ¢šâì ¢ 1
2779 */
2780#if 1
2781 if (chip->device_type == DEVICE_INTEL_ICH5 ||
2782 chip->device_type == DEVICE_INTEL_ICH4)
2783 {
2784 pci_read_config_dword(pci, 0x40, &pci_dword);
2785 printk("acpi_base %x\n", pci_dword);
2786 pci_read_config_byte(pci, 0x44, &pci_byte);
2787 printk("acpi_cntl %i\n", pci_byte);
2788// pci_write_config_byte(pci, 0x44, pci_byte & ~(0x10));
2789 pci_read_config_word(pci, 0x54, &pci_word);
2790// pci_write_config_word(pci, 0x54, pci_word & ~(0x3));
2791
2792 pci_read_config_word(pci, PCI_COMMAND, &pci_word);
2793// pci_write_config_word(pci, PCI_COMMAND, pci_word | (PCI_COMMAND_IO | PCI_COMMAND_MEMORY));
2794
2795 pci_read_config_byte(pci, 0x55, &pci_byte);
2796 printk("pci config at 0x55 %i\n", pci_byte);
2797
2798 pci_write_config_byte(pci, 0x55, 0x01);
2799 }
2800#endif
2801 // make sure that pci allow mmio operations
2802
2803 if (pci_resource_flags(pci, /*2*/0) & IORESOURCE_MEM) { /* ICH4 and Nforce */
2804 chip->mmio = 1;
2805 chip->addr = pci_resource_start(pci, /*2*/0);
2806 chip->remap_addr = (unsigned long)
2807 ioremap_nocache(chip->addr, pci_resource_len(pci, /*2*/0));
2808 if (chip->remap_addr == 0) {
2809 snd_printk("AC'97 space ioremap problem\n");
2810 snd_intel8x0_free(chip);
2811 return -EIO;
2812 }
2813 printk("ioremap %x len %i remap addr: %x\n",
2814 chip->addr, pci_resource_len(pci, /*2*/0), chip->remap_addr);
2815 }
2816 else if (pci_resource_flags(pci, 2) & IORESOURCE_MEM) { /* ICH4 and Nforce */
2817 chip->mmio = 1;
2818 chip->addr = pci_resource_start(pci, 2);
2819 chip->remap_addr = (unsigned long)
2820 ioremap_nocache(chip->addr, pci_resource_len(pci, 2));
2821 if (chip->remap_addr == 0) {
2822 snd_printk("AC'97 space ioremap problem\n");
2823 snd_intel8x0_free(chip);
2824 return -EIO;
2825 }
2826 printk("ioremap %x len %i remap addr: %x\n",
2827 chip->addr, pci_resource_len(pci, 2), chip->remap_addr);
2828 } else {
2829 chip->addr = pci_resource_start(pci, 0);
2830 }
2831
2832 if (pci_resource_flags(pci, /*3*/1) & IORESOURCE_MEM) { /* ICH4 */
2833 chip->bm_mmio = 1;
2834 chip->bmaddr = pci_resource_start(pci, /*3*/1);
2835 chip->remap_bmaddr = (unsigned long)
2836 ioremap_nocache(chip->bmaddr, pci_resource_len(pci, /*3*/1));
2837 if (chip->remap_bmaddr == 0) {
2838 snd_printk("Controller space ioremap problem\n");
2839 snd_intel8x0_free(chip);
2840 return -EIO;
2841 }
2842 printk("ioremap bm %x len %i remap addr: %x\n",
2843 chip->bmaddr, pci_resource_len(pci, /*3*/1), chip->remap_bmaddr);
2844 }
2845 else if (pci_resource_flags(pci, 3) & IORESOURCE_MEM) { /* ICH4 */
2846 chip->bm_mmio = 1;
2847 chip->bmaddr = pci_resource_start(pci, 3);
2848 chip->remap_bmaddr = (unsigned long)
2849 ioremap_nocache(chip->bmaddr, pci_resource_len(pci, 3));
2850 if (chip->remap_bmaddr == 0) {
2851 snd_printk("Controller space ioremap problem\n");
2852 snd_intel8x0_free(chip);
2853 return -EIO;
2854 }
2855 printk("ioremap bm %x len %i remap addr: %x\n",
2856 chip->bmaddr, pci_resource_len(pci, 3), chip->remap_bmaddr);
2857 } else {
2858 chip->bmaddr = pci_resource_start(pci, 1);
2859 }
2860
2861port_inited:
2862 chip->bdbars_count = bdbars[device_type];
2863
2864 /* initialize offsets */
2865 switch (device_type) {
2866 case DEVICE_NFORCE:
2867 tbl = nforce_regs;
2868 break;
2869 case DEVICE_ALI:
2870 tbl = ali_regs;
2871 break;
2872 default:
2873 tbl = intel_regs;
2874 break;
2875 }
2876 for (i = 0; i < chip->bdbars_count; i++) {
2877 ichdev = &chip->ichd[i];
2878 ichdev->ichd = i;
2879 ichdev->reg_offset = tbl[i].offset;
2880 ichdev->int_sta_mask = tbl[i].int_sta_mask;
2881 if (device_type == DEVICE_SIS) {
2882 /* SiS 7012 swaps the registers */
2883 ichdev->roff_sr = ICH_REG_OFF_PICB;
2884 ichdev->roff_picb = ICH_REG_OFF_SR;
2885 } else {
2886 ichdev->roff_sr = ICH_REG_OFF_SR;
2887 ichdev->roff_picb = ICH_REG_OFF_PICB;
2888 }
2889 if (device_type == DEVICE_ALI)
2890 ichdev->ali_slot = (ichdev->reg_offset - 0x40) / 0x10;
2891 /* SIS7012 handles the pcm data in bytes, others are in samples */
2892 ichdev->pos_shift = (device_type == DEVICE_SIS) ? 0 : 1;
2893 }
2894
2895 /* allocate buffer descriptor lists */
2896 /* the start of each lists must be aligned to 8 bytes */
2897 if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(pci),
2898 chip->bdbars_count * sizeof(u32) * ICH_MAX_FRAGS * 2,
2899 &chip->bdbars) < 0) {
2900 snd_intel8x0_free(chip);
2901 snd_printk(KERN_ERR "intel8x0: cannot allocate buffer descriptors\n");
2902 return -ENOMEM;
2903 }
2904 /* tables must be aligned to 8 bytes here, but the kernel pages
2905 are much bigger, so we don't care (on i386) */
2906
2907 int_sta_masks = 0;
2908 for (i = 0; i < chip->bdbars_count; i++) {
2909 ichdev = &chip->ichd[i];
2910 ichdev->bdbar = ((u32 *)chip->bdbars.area) +
2911 (i * ICH_MAX_FRAGS * 2);
2912 ichdev->bdbar_addr = chip->bdbars.addr +
2913 (i * sizeof(u32) * ICH_MAX_FRAGS * 2);
2914 int_sta_masks |= ichdev->int_sta_mask;
2915 }
2916 chip->int_sta_reg = device_type == DEVICE_ALI ?
2917 ICH_REG_ALI_INTERRUPTSR : ICH_REG_GLOB_STA;
2918 chip->int_sta_mask = int_sta_masks;
2919
2920 /* request irq after initializaing int_sta_mask, etc */
2921 if (request_irq(pci->irq, snd_intel8x0_interrupt,
2922 SA_INTERRUPT|SA_SHIRQ, card->shortname, (void *)chip)) {
2923 snd_printk(KERN_ERR "unable to grab IRQ %d\n", pci->irq);
2924 snd_intel8x0_free(chip);
2925 return -EBUSY;
2926 }
2927 chip->irq = pci->irq;
2928 pci_set_master(pci);
2929 synchronize_irq(chip->irq);
2930
2931 switch(chip->device_type) {
2932 case DEVICE_INTEL_ICH4:
2933 case DEVICE_INTEL_ICH5:
2934 /* ICH4/5 can have three codecs */
2935 chip->max_codecs = 3;
2936 chip->codec_bit = ich_codec_bits;
2937 chip->codec_ready_bits = ICH_PRI | ICH_SRI | ICH_TRI;
2938 break;
2939 case DEVICE_SIS:
2940 /* recent SIS7012 can have three codecs */
2941 chip->max_codecs = 3;
2942 chip->codec_bit = sis_codec_bits;
2943 chip->codec_ready_bits = ICH_PRI | ICH_SRI | ICH_SIS_TRI;
2944 break;
2945 default:
2946 /* others up to two codecs */
2947 chip->max_codecs = 2;
2948 chip->codec_bit = ich_codec_bits;
2949 chip->codec_ready_bits = ICH_PRI | ICH_SRI;
2950 break;
2951 }
2952 for (i = 0; i < chip->max_codecs; i++)
2953 chip->codec_isr_bits |= chip->codec_bit[i];
2954
2955 if ((err = snd_intel8x0_chip_init(chip, 1)) < 0) {
2956 snd_intel8x0_free(chip);
2957 return err;
2958 }
2959
2960 if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) < 0) {
2961 snd_intel8x0_free(chip);
2962 return err;
2963 }
2964
2965 *r_intel8x0 = chip;
2966 return 0;
2967}
2968
2969static struct shortname_table {
2970 unsigned int id;
2971 const char *s;
2972} shortnames[] __devinitdata = {
2973 { PCI_DEVICE_ID_INTEL_82801, "Intel 82801AA-ICH" },
2974 { PCI_DEVICE_ID_INTEL_82901, "Intel 82901AB-ICH0" },
2975 { PCI_DEVICE_ID_INTEL_82801BA, "Intel 82801BA-ICH2" },
2976 { PCI_DEVICE_ID_INTEL_440MX, "Intel 440MX" },
2977 { PCI_DEVICE_ID_INTEL_ICH3, "Intel 82801CA-ICH3" },
2978 { PCI_DEVICE_ID_INTEL_ICH4, "Intel 82801DB-ICH4" },
2979 { PCI_DEVICE_ID_INTEL_ICH5, "Intel ICH5" },
2980 { PCI_DEVICE_ID_INTEL_ESB_5, "Intel ICH 6300ESB" },
2981 { PCI_DEVICE_ID_INTEL_ICH6_18, "Intel ICH6" },
2982 { PCI_DEVICE_ID_INTEL_ICH7_20, "Intel ICH7" },
2983 { PCI_DEVICE_ID_INTEL_ESB2_14, "Intel ESB2" },
2984 { PCI_DEVICE_ID_SI_7012, "SiS SI7012" },
2985 { PCI_DEVICE_ID_NVIDIA_MCP_AUDIO, "NVidia nForce" },
2986 { PCI_DEVICE_ID_NVIDIA_MCP2_AUDIO, "NVidia nForce2" },
2987 { PCI_DEVICE_ID_NVIDIA_MCP3_AUDIO, "NVidia nForce3" },
2988 { PCI_DEVICE_ID_NVIDIA_CK8S_AUDIO, "NVidia CK8S" },
2989 { PCI_DEVICE_ID_NVIDIA_CK804_AUDIO, "NVidia CK804" },
2990 { PCI_DEVICE_ID_NVIDIA_CK8_AUDIO, "NVidia CK8" },
2991 { 0x003a, "NVidia MCP04" },
2992 { 0x746d, "AMD AMD8111" },
2993 { 0x7445, "AMD AMD768" },
2994 { 0x5455, "ALi M5455" },
2995 { 0, 0 },
2996};
2997
2998static int __devinit snd_intel8x0_probe(struct pci_dev *pci,
2999 const struct pci_device_id *pci_id)
3000{
3001 static int dev;
3002 snd_card_t *card;
3003 struct intel8x0 *chip;
3004 int err;
3005 struct shortname_table *name;
3006
3007 if (dev >= SNDRV_CARDS)
3008 return -ENODEV;
3009 if (!enable[dev]) {
3010 dev++;
3011 return -ENOENT;
3012 }
3013
3014 card = snd_card_new(index[dev], id[dev], THIS_MODULE, 0);
3015 if (card == NULL)
3016 return -ENOMEM;
3017 switch (pci_id->driver_data) {
3018 case DEVICE_NFORCE:
3019 strcpy(card->driver, "NFORCE");
3020 break;
3021 case DEVICE_INTEL_ICH4:
3022 strcpy(card->driver, "ICH4");
3023 break;
3024 case DEVICE_INTEL_ICH5:
3025 strcpy(card->driver, "ICH5");
3026 break;
3027 default:
3028 strcpy(card->driver, "ICH");
3029 break;
3030 }
3031
3032 strcpy(card->shortname, "Intel ICH");
3033 for (name = shortnames; name->id; name++) {
3034 if (pci->device == name->id) {
3035 strcpy(card->shortname, name->s);
3036 break;
3037 }
3038 }
3039 // card->dev = &pci->dev;
3040 if (buggy_irq < 0) {
3041 /* some Nforce[2] and ICH boards have problems with IRQ handling.
3042 * Needs to return IRQ_HANDLED for unknown irqs.
3043 */
3044 if (pci_id->driver_data == DEVICE_NFORCE)
3045 buggy_irq = 1;
3046 else
3047 buggy_irq = 0;
3048 }
3049
3050 if ((err = snd_intel8x0_create(card, pci, pci_id->driver_data, &chip)) < 0) {
3051 snd_card_free(card);
3052 printk(KERN_ERR "ICH: create error. err = %x\n",err);
3053 return err;
3054 }
3055
3056 card->private_data = chip;
3057
3058 if ((err = snd_intel8x0_mixer(chip, ac97_clock[dev], ac97_quirk[dev])) < 0){
3059 snd_card_free(card);
3060 // printk(KERN_ERR "ICH: mixer error. err = %x\n",err);
3061 return err;
3062 }
3063 if ((err = snd_intel8x0_pcm(chip)) < 0) {
3064 snd_card_free(card);
3065 printk(KERN_ERR "ICH: pcm error. err = %x\n",err);
3066 return err;
3067 }
3068
3069 if (mpu_port[dev] == 0x300 || mpu_port[dev] == 0x330) {
3070 if ((err = snd_mpu401_uart_new(card, 0, MPU401_HW_INTEL8X0,
3071 mpu_port[dev], 0,
3072 -1, 0, &chip->rmidi)) < 0) {
3073 printk(KERN_ERR "intel8x0: no UART401 device at 0x%x, skipping.\n", mpu_port[dev]);
3074 mpu_port[dev] = 0;
3075 }
3076 } else
3077 mpu_port[dev] = 0;
3078
3079 snd_intel8x0_proc_init(chip);
3080
3081 sprintf(card->longname, "%s at 0x%lx, irq %i",
3082 card->shortname, chip->addr, chip->irq);
3083
3084 if (! ac97_clock[dev])
3085 intel8x0_measure_ac97_clock(chip);
3086
3087 if ((err = snd_card_register(card)) < 0) {
3088 snd_card_free(card);
3089 printk(KERN_ERR "ICH: card register error. err = %x\n",err);
3090 return err;
3091 }
3092 pci_set_drvdata(pci, card);
3093 dev++;
3094 return 0;
3095}
3096
3097static void __devexit snd_intel8x0_remove(struct pci_dev *pci)
3098{
3099 snd_card_free(pci_get_drvdata(pci));
3100 pci_set_drvdata(pci, NULL);
3101}
3102
3103static struct pci_driver driver = {
3104 .name = "Intel ICH",
3105 .id_table = snd_intel8x0_ids,
3106 .probe = snd_intel8x0_probe,
3107 .remove = snd_intel8x0_remove,
3108#ifdef CONFIG_PM
3109 .suspend = intel8x0_suspend,
3110 .resume = intel8x0_resume,
3111#endif
3112};
3113
3114#if defined(SUPPORT_JOYSTICK) || defined(SUPPORT_MIDI)
3115/*
3116 * initialize joystick/midi addresses
3117 */
3118#ifdef SUPPORT_JOYSTICK
3119/* there is only one available device, so we keep it here */
3120static struct pci_dev *ich_gameport_pci;
3121static struct gameport ich_gameport = { .io = 0x200 };
3122#endif
3123
3124
3125static int __devinit snd_intel8x0_joystick_probe(struct pci_dev *pci,
3126 const struct pci_device_id *id)
3127{
3128 u16 val;
3129 static int dev;
3130 if (dev >= SNDRV_CARDS)
3131 return -ENODEV;
3132 if (!enable[dev]) {
3133 dev++;
3134 return -ENOENT;
3135 }
3136
3137 pci_read_config_word(pci, 0xe6, &val);
3138#ifdef SUPPORT_JOYSTICK
3139 if (joystick[dev]) {
3140 if (! request_region(ich_gameport.io, 8, "ICH gameport")) {
3141 printk(KERN_WARNING "intel8x0: cannot grab gameport 0x%x\n", ich_gameport.io);
3142 joystick[dev] = 0;
3143 } else {
3144 ich_gameport_pci = pci;
3145 gameport_register_port(&ich_gameport);
3146 val |= 0x100;
3147 }
3148 }
3149#endif
3150#ifdef SUPPORT_MIDI
3151 if (mpu_port[dev] > 0) {
3152 if (mpu_port[dev] == 0x300 || mpu_port[dev] == 0x330) {
3153 u8 b;
3154 val |= 0x20;
3155 pci_read_config_byte(pci, 0xe2, &b);
3156 if (mpu_port[dev] == 0x300)
3157 b |= 0x08;
3158 else
3159 b &= ~0x08;
3160 pci_write_config_byte(pci, 0xe2, b);
3161 }
3162 }
3163#endif
3164 pci_write_config_word(pci, 0xe6, val);
3165 return 0;
3166}
3167
3168static void __devexit snd_intel8x0_joystick_remove(struct pci_dev *pci)
3169{
3170 u16 val;
3171#ifdef SUPPORT_JOYSTICK
3172 if (ich_gameport_pci == pci) {
3173 gameport_unregister_port(&ich_gameport);
3174 release_region(ich_gameport.io, 8);
3175 ich_gameport_pci = NULL;
3176 }
3177#endif
3178 /* disable joystick and MIDI */
3179 pci_read_config_word(pci, 0xe6, &val);
3180 val &= ~0x120;
3181 pci_write_config_word(pci, 0xe6, val);
3182}
3183
3184static struct pci_device_id snd_intel8x0_joystick_ids[] = {
3185 { 0x8086, 0x2410, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, /* 82801AA */
3186 { 0x8086, 0x2420, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, /* 82901AB */
3187 { 0x8086, 0x2440, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, /* ICH2 */
3188 { 0x8086, 0x244c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, /* ICH2M */
3189 { 0x8086, 0x248c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, /* ICH3 */
3190 // { 0x8086, 0x7195, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, /* 440MX */
3191 // { 0x1039, 0x7012, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, /* SI7012 */
3192 //Rudi: this is not a joystick !!!!
3193 // { 0x10de, 0x01b2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, /* NFORCE */
3194 // { 0x10de, 0x006b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, /* NFORCE2 */
3195 { 0x10de, 0x00db, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, /* NFORCE3 */
3196 { 0, }
3197};
3198
3199static struct pci_driver joystick_driver = {
3200 0, 0, 0,
3201 /* name: */ "Intel ICH Joystick",
3202 /* id_table: */ snd_intel8x0_joystick_ids,
3203 /* probe: */ snd_intel8x0_joystick_probe,
3204 0,0,0
3205};
3206static int have_joystick;
3207#endif
3208
3209static int __init alsa_card_intel8x0_init(void)
3210{
3211 int err = 0;
3212
3213 // printk(KERN_ERR "alsa_card_intel8x0_init\n");
3214#ifdef TARGET_OS2
3215 if (midi_port > 0) mpu_port[0] = midi_port;
3216#endif
3217
3218 if ((err = pci_module_init(&driver)) < 0) {
3219#ifdef MODULE
3220 // printk(KERN_ERR "Intel ICH soundcard not found or device busy. err = %x\n",err);
3221#endif
3222 return err;
3223 }
3224#if defined(SUPPORT_JOYSTICK) || defined(SUPPORT_MIDI)
3225 if (pci_module_init(&joystick_driver) < 0) {
3226 snd_printdd(KERN_INFO "no joystick found\n");
3227 have_joystick = 0;
3228 } else {
3229 snd_printdd(KERN_INFO "joystick(s) found\n");
3230 have_joystick = 1;
3231 }
3232#endif
3233 return 0;
3234}
3235
3236static void __exit alsa_card_intel8x0_exit(void)
3237{
3238 pci_unregister_driver(&driver);
3239#if defined(SUPPORT_JOYSTICK) || defined(SUPPORT_MIDI)
3240 if (have_joystick)
3241 pci_unregister_driver(&joystick_driver);
3242#endif
3243}
3244
3245module_init(alsa_card_intel8x0_init)
3246module_exit(alsa_card_intel8x0_exit)
3247
3248#ifndef MODULE
3249
3250/* format is: snd-intel8x0=enable,index,id,ac97_clock,mpu_port,joystick */
3251
3252static int __init alsa_card_intel8x0_setup(char *str)
3253{
3254 static unsigned __initdata nr_dev = 0;
3255
3256 if (nr_dev >= SNDRV_CARDS)
3257 return 0;
3258 (void)(get_option(&str,&enable[nr_dev]) == 2 &&
3259 get_option(&str,&index[nr_dev]) == 2 &&
3260 get_id(&str,&id[nr_dev]) == 2 &&
3261 get_option(&str,&ac97_clock[nr_dev]) == 2 &&
3262 get_option(&str,&ac97_quirk[nr_dev]) == 2
3263#ifdef SUPPORT_MIDI
3264 && get_option(&str,&mpu_port[nr_dev]) == 2
3265#endif
3266#ifdef SUPPORT_JOYSTICK
3267 && get_option(&str,&joystick[nr_dev]) == 2
3268#endif
3269 );
3270 nr_dev++;
3271 return 1;
3272}
3273
3274__setup("snd-intel8x0=", alsa_card_intel8x0_setup);
3275
3276#endif /* ifndef MODULE */
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