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intel8x0.c

Last change on this file was 777, checked in by David Azarewicz, 4 months ago
Merge from uniaud32-exp branch
File size: 91.0 KB

Rev	Line
[679]	1	// SPDX-License-Identifier: GPL-2.0-or-later
[32]	2	/*
	3	* ALSA driver for Intel ICH (i8x0) chipsets
	4	*
[305]	5	* Copyright (c) 2000 Jaroslav Kysela <perex@perex.cz>
[32]	6	*
	7	* This code also contains alpha support for SiS 735 chipsets provided
	8	* by Mike Pieper <mptei@users.sourceforge.net>. We have no datasheet
	9	* for SiS735, so the code is not fully functional.
	10	*
[679]	11	*/
[32]	12
[679]	13	#ifdef TARGET_OS2
	14	#define KBUILD_MODNAME "intel8x0"
	15	#endif
[32]	16
[679]	17	#include <linux/io.h>
[32]	18	#include <linux/delay.h>
	19	#include <linux/interrupt.h>
	20	#include <linux/init.h>
	21	#include <linux/pci.h>
	22	#include <linux/slab.h>
[679]	23	#include <linux/module.h>
[32]	24	#include <sound/core.h>
	25	#include <sound/pcm.h>
	26	#include <sound/ac97_codec.h>
	27	#include <sound/info.h>
	28	#include <sound/initval.h>
	29
[305]	30	MODULE_AUTHOR("Jaroslav Kysela <perex@perex.cz>");
[32]	31	MODULE_DESCRIPTION("Intel 82801AA,82901AB,i810,i820,i830,i840,i845,MX440; SiS 7012; Ali 5455");
	32	MODULE_LICENSE("GPL");
	33
[305]	34	static int index = SNDRV_DEFAULT_IDX1; /* Index 0-MAX */
	35	static char id = SNDRV_DEFAULT_STR1; / ID for this card */
	36	static int ac97_clock;
	37	static char *ac97_quirk;
[679]	38	static bool buggy_semaphore;
[32]	39	static int buggy_irq = -1; /* auto-check */
[679]	40	static bool xbox;
[305]	41	static int spdif_aclink = -1;
[679]	42	static int inside_vm = -1;
[32]	43
[305]	44	module_param(index, int, 0444);
[32]	45	MODULE_PARM_DESC(index, "Index value for Intel i8x0 soundcard.");
[305]	46	module_param(id, charp, 0444);
[32]	47	MODULE_PARM_DESC(id, "ID string for Intel i8x0 soundcard.");
[305]	48	module_param(ac97_clock, int, 0444);
[679]	49	MODULE_PARM_DESC(ac97_clock, "AC'97 codec clock (0 = allowlist + auto-detect, 1 = force autodetect).");
[305]	50	module_param(ac97_quirk, charp, 0444);
[32]	51	MODULE_PARM_DESC(ac97_quirk, "AC'97 workaround for strange hardware.");
[305]	52	module_param(buggy_semaphore, bool, 0444);
	53	MODULE_PARM_DESC(buggy_semaphore, "Enable workaround for hardwares with problematic codec semaphores.");
[679]	54	module_param(buggy_irq, bint, 0444);
[305]	55	MODULE_PARM_DESC(buggy_irq, "Enable workaround for buggy interrupts on some motherboards.");
	56	module_param(xbox, bool, 0444);
	57	MODULE_PARM_DESC(xbox, "Set to 1 for Xbox, if you have problems with the AC'97 codec detection.");
	58	module_param(spdif_aclink, int, 0444);
	59	MODULE_PARM_DESC(spdif_aclink, "S/PDIF over AC-link.");
[679]	60	module_param(inside_vm, bint, 0444);
	61	MODULE_PARM_DESC(inside_vm, "KVM/Parallels optimization.");
[32]	62
[305]	63	/* just for backward compatibility */
[679]	64	//static bool enable;
[305]	65	module_param(enable, bool, 0444);
[598]	66	//static int joystick;
[305]	67	module_param(joystick, int, 0444);
	68
[32]	69	/*
	70	* Direct registers
	71	*/
[305]	72	enum { DEVICE_INTEL, DEVICE_INTEL_ICH4, DEVICE_SIS, DEVICE_ALI, DEVICE_NFORCE };
[32]	73
	74	#define ICHREG(x) ICH_REG_##x
	75
	76	#define DEFINE_REGSET(name,base) \
[305]	77	enum { \
	78	ICH_REG_##name##_BDBAR = base + 0x0, /* dword - buffer descriptor list base address */ \
	79	ICH_REG_##name##_CIV = base + 0x04, /* byte - current index value */ \
	80	ICH_REG_##name##_LVI = base + 0x05, /* byte - last valid index */ \
	81	ICH_REG_##name##_SR = base + 0x06, /* byte - status register */ \
	82	ICH_REG_##name##_PICB = base + 0x08, /* word - position in current buffer */ \
	83	ICH_REG_##name##_PIV = base + 0x0a, /* byte - prefetched index value */ \
	84	ICH_REG_##name##_CR = base + 0x0b, /* byte - control register */ \
[703]	85	}
[32]	86
	87	/* busmaster blocks */
	88	DEFINE_REGSET(OFF, 0); /* offset */
	89	DEFINE_REGSET(PI, 0x00); /* PCM in */
	90	DEFINE_REGSET(PO, 0x10); /* PCM out */
	91	DEFINE_REGSET(MC, 0x20); /* Mic in */
	92
	93	/* ICH4 busmaster blocks */
	94	DEFINE_REGSET(MC2, 0x40); /* Mic in 2 */
	95	DEFINE_REGSET(PI2, 0x50); /* PCM in 2 */
	96	DEFINE_REGSET(SP, 0x60); /* SPDIF out */
	97
	98	/* values for each busmaster block */
	99
	100	/* LVI */
	101	#define ICH_REG_LVI_MASK 0x1f
	102
	103	/* SR */
	104	#define ICH_FIFOE 0x10 /* FIFO error */
	105	#define ICH_BCIS 0x08 /* buffer completion interrupt status */
	106	#define ICH_LVBCI 0x04 /* last valid buffer completion interrupt */
	107	#define ICH_CELV 0x02 /* current equals last valid */
	108	#define ICH_DCH 0x01 /* DMA controller halted */
	109
	110	/* PIV */
	111	#define ICH_REG_PIV_MASK 0x1f /* mask */
	112
	113	/* CR */
	114	#define ICH_IOCE 0x10 /* interrupt on completion enable */
	115	#define ICH_FEIE 0x08 /* fifo error interrupt enable */
	116	#define ICH_LVBIE 0x04 /* last valid buffer interrupt enable */
	117	#define ICH_RESETREGS 0x02 /* reset busmaster registers */
	118	#define ICH_STARTBM 0x01 /* start busmaster operation */
	119
	120
	121	/* global block */
	122	#define ICH_REG_GLOB_CNT 0x2c /* dword - global control */
[305]	123	#define ICH_PCM_SPDIF_MASK 0xc0000000 /* s/pdif pcm slot mask (ICH4) */
	124	#define ICH_PCM_SPDIF_NONE 0x00000000 /* reserved - undefined */
	125	#define ICH_PCM_SPDIF_78 0x40000000 /* s/pdif pcm on slots 7&8 */
	126	#define ICH_PCM_SPDIF_69 0x80000000 /* s/pdif pcm on slots 6&9 */
	127	#define ICH_PCM_SPDIF_1011 0xc0000000 /* s/pdif pcm on slots 10&11 */
[32]	128	#define ICH_PCM_20BIT 0x00400000 /* 20-bit samples (ICH4) */
[358]	129	#define ICH_PCM_246_MASK 0x00300000 /* chan mask (not all chips) */
	130	#define ICH_PCM_8 0x00300000 /* 8 channels (not all chips) */
[32]	131	#define ICH_PCM_6 0x00200000 /* 6 channels (not all chips) */
	132	#define ICH_PCM_4 0x00100000 /* 4 channels (not all chips) */
	133	#define ICH_PCM_2 0x00000000 /* 2 channels (stereo) */
	134	#define ICH_SIS_PCM_246_MASK 0x000000c0 /* 6 channels (SIS7012) */
	135	#define ICH_SIS_PCM_6 0x00000080 /* 6 channels (SIS7012) */
	136	#define ICH_SIS_PCM_4 0x00000040 /* 4 channels (SIS7012) */
	137	#define ICH_SIS_PCM_2 0x00000000 /* 2 channels (SIS7012) */
	138	#define ICH_TRIE 0x00000040 /* tertiary resume interrupt enable */
	139	#define ICH_SRIE 0x00000020 /* secondary resume interrupt enable */
	140	#define ICH_PRIE 0x00000010 /* primary resume interrupt enable */
	141	#define ICH_ACLINK 0x00000008 /* AClink shut off */
	142	#define ICH_AC97WARM 0x00000004 /* AC'97 warm reset */
	143	#define ICH_AC97COLD 0x00000002 /* AC'97 cold reset */
	144	#define ICH_GIE 0x00000001 /* GPI interrupt enable */
[305]	145	#define ICH_REG_GLOB_STA 0x30 /* dword - global status */
[32]	146	#define ICH_TRI 0x20000000 /* ICH4: tertiary (AC_SDIN2) resume interrupt */
	147	#define ICH_TCR 0x10000000 /* ICH4: tertiary (AC_SDIN2) codec ready */
	148	#define ICH_BCS 0x08000000 /* ICH4: bit clock stopped */
	149	#define ICH_SPINT 0x04000000 /* ICH4: S/PDIF interrupt */
	150	#define ICH_P2INT 0x02000000 /* ICH4: PCM2-In interrupt */
	151	#define ICH_M2INT 0x01000000 /* ICH4: Mic2-In interrupt */
	152	#define ICH_SAMPLE_CAP 0x00c00000 /* ICH4: sample capability bits (RO) */
[305]	153	#define ICH_SAMPLE_16_20 0x00400000 /* ICH4: 16- and 20-bit samples */
[32]	154	#define ICH_MULTICHAN_CAP 0x00300000 /* ICH4: multi-channel capability bits (RO) */
[305]	155	#define ICH_SIS_TRI 0x00080000 /* SIS: tertiary resume irq */
	156	#define ICH_SIS_TCR 0x00040000 /* SIS: tertiary codec ready */
[32]	157	#define ICH_MD3 0x00020000 /* modem power down semaphore */
	158	#define ICH_AD3 0x00010000 /* audio power down semaphore */
	159	#define ICH_RCS 0x00008000 /* read completion status */
	160	#define ICH_BIT3 0x00004000 /* bit 3 slot 12 */
	161	#define ICH_BIT2 0x00002000 /* bit 2 slot 12 */
	162	#define ICH_BIT1 0x00001000 /* bit 1 slot 12 */
	163	#define ICH_SRI 0x00000800 /* secondary (AC_SDIN1) resume interrupt */
	164	#define ICH_PRI 0x00000400 /* primary (AC_SDIN0) resume interrupt */
	165	#define ICH_SCR 0x00000200 /* secondary (AC_SDIN1) codec ready */
	166	#define ICH_PCR 0x00000100 /* primary (AC_SDIN0) codec ready */
	167	#define ICH_MCINT 0x00000080 /* MIC capture interrupt */
	168	#define ICH_POINT 0x00000040 /* playback interrupt */
	169	#define ICH_PIINT 0x00000020 /* capture interrupt */
	170	#define ICH_NVSPINT 0x00000010 /* nforce spdif interrupt */
	171	#define ICH_MOINT 0x00000004 /* modem playback interrupt */
	172	#define ICH_MIINT 0x00000002 /* modem capture interrupt */
	173	#define ICH_GSCI 0x00000001 /* GPI status change interrupt */
[305]	174	#define ICH_REG_ACC_SEMA 0x34 /* byte - codec write semaphore */
[32]	175	#define ICH_CAS 0x01 /* codec access semaphore */
	176	#define ICH_REG_SDM 0x80
	177	#define ICH_DI2L_MASK 0x000000c0 /* PCM In 2, Mic In 2 data in line */
	178	#define ICH_DI2L_SHIFT 6
	179	#define ICH_DI1L_MASK 0x00000030 /* PCM In 1, Mic In 1 data in line */
	180	#define ICH_DI1L_SHIFT 4
	181	#define ICH_SE 0x00000008 /* steer enable */
	182	#define ICH_LDI_MASK 0x00000003 /* last codec read data input */
	183
[305]	184	#define ICH_MAX_FRAGS 32 /* max hw frags */
[32]	185
	186
	187	/*
	188	* registers for Ali5455
	189	*/
	190
	191	/* ALi 5455 busmaster blocks */
	192	DEFINE_REGSET(AL_PI, 0x40); /* ALi PCM in */
	193	DEFINE_REGSET(AL_PO, 0x50); /* Ali PCM out */
	194	DEFINE_REGSET(AL_MC, 0x60); /* Ali Mic in */
	195	DEFINE_REGSET(AL_CDC_SPO, 0x70); /* Ali Codec SPDIF out */
	196	DEFINE_REGSET(AL_CENTER, 0x80); /* Ali center out */
	197	DEFINE_REGSET(AL_LFE, 0x90); /* Ali center out */
	198	DEFINE_REGSET(AL_CLR_SPI, 0xa0); /* Ali Controller SPDIF in */
	199	DEFINE_REGSET(AL_CLR_SPO, 0xb0); /* Ali Controller SPDIF out */
	200	DEFINE_REGSET(AL_I2S, 0xc0); /* Ali I2S in */
	201	DEFINE_REGSET(AL_PI2, 0xd0); /* Ali PCM2 in */
	202	DEFINE_REGSET(AL_MC2, 0xe0); /* Ali Mic2 in */
	203
	204	enum {
[305]	205	ICH_REG_ALI_SCR = 0x00, /* System Control Register */
	206	ICH_REG_ALI_SSR = 0x04, /* System Status Register */
	207	ICH_REG_ALI_DMACR = 0x08, /* DMA Control Register */
	208	ICH_REG_ALI_FIFOCR1 = 0x0c, /* FIFO Control Register 1 */
	209	ICH_REG_ALI_INTERFACECR = 0x10, /* Interface Control Register */
	210	ICH_REG_ALI_INTERRUPTCR = 0x14, /* Interrupt control Register */
	211	ICH_REG_ALI_INTERRUPTSR = 0x18, /* Interrupt Status Register */
	212	ICH_REG_ALI_FIFOCR2 = 0x1c, /* FIFO Control Register 2 */
	213	ICH_REG_ALI_CPR = 0x20, /* Command Port Register */
	214	ICH_REG_ALI_CPR_ADDR = 0x22, /* ac97 addr write */
	215	ICH_REG_ALI_SPR = 0x24, /* Status Port Register */
	216	ICH_REG_ALI_SPR_ADDR = 0x26, /* ac97 addr read */
	217	ICH_REG_ALI_FIFOCR3 = 0x2c, /* FIFO Control Register 3 */
	218	ICH_REG_ALI_TTSR = 0x30, /* Transmit Tag Slot Register */
	219	ICH_REG_ALI_RTSR = 0x34, /* Receive Tag Slot Register */
	220	ICH_REG_ALI_CSPSR = 0x38, /* Command/Status Port Status Register */
	221	ICH_REG_ALI_CAS = 0x3c, /* Codec Write Semaphore Register */
	222	ICH_REG_ALI_HWVOL = 0xf0, /* hardware volume control/status */
	223	ICH_REG_ALI_I2SCR = 0xf4, /* I2S control/status */
	224	ICH_REG_ALI_SPDIFCSR = 0xf8, /* spdif channel status register */
	225	ICH_REG_ALI_SPDIFICS = 0xfc, /* spdif interface control/status */
[32]	226	};
	227
	228	#define ALI_CAS_SEM_BUSY 0x80000000
	229	#define ALI_CPR_ADDR_SECONDARY 0x100
	230	#define ALI_CPR_ADDR_READ 0x80
	231	#define ALI_CSPSR_CODEC_READY 0x08
	232	#define ALI_CSPSR_READ_OK 0x02
	233	#define ALI_CSPSR_WRITE_OK 0x01
	234
	235	/* interrupts for the whole chip by interrupt status register finish */
[679]	236
[32]	237	#define ALI_INT_MICIN2 (1<<26)
	238	#define ALI_INT_PCMIN2 (1<<25)
	239	#define ALI_INT_I2SIN (1<<24)
	240	#define ALI_INT_SPDIFOUT (1<<23) /* controller spdif out INTERRUPT */
	241	#define ALI_INT_SPDIFIN (1<<22)
	242	#define ALI_INT_LFEOUT (1<<21)
	243	#define ALI_INT_CENTEROUT (1<<20)
	244	#define ALI_INT_CODECSPDIFOUT (1<<19)
	245	#define ALI_INT_MICIN (1<<18)
	246	#define ALI_INT_PCMOUT (1<<17)
	247	#define ALI_INT_PCMIN (1<<16)
	248	#define ALI_INT_CPRAIS (1<<7) /* command port available */
	249	#define ALI_INT_SPRAIS (1<<5) /* status port available */
	250	#define ALI_INT_GPIO (1<<1)
[305]	251	#define ALI_INT_MASK (ALI_INT_SPDIFOUT\|ALI_INT_CODECSPDIFOUT\|\
	252	ALI_INT_MICIN\|ALI_INT_PCMOUT\|ALI_INT_PCMIN)
[32]	253
	254	#define ICH_ALI_SC_RESET (1<<31) /* master reset */
	255	#define ICH_ALI_SC_AC97_DBL (1<<30)
	256	#define ICH_ALI_SC_CODEC_SPDF (3<<20) /* 1=7/8, 2=6/9, 3=10/11 */
	257	#define ICH_ALI_SC_IN_BITS (3<<18)
	258	#define ICH_ALI_SC_OUT_BITS (3<<16)
	259	#define ICH_ALI_SC_6CH_CFG (3<<14)
	260	#define ICH_ALI_SC_PCM_4 (1<<8)
	261	#define ICH_ALI_SC_PCM_6 (2<<8)
	262	#define ICH_ALI_SC_PCM_246_MASK (3<<8)
	263
	264	#define ICH_ALI_SS_SEC_ID (3<<5)
	265	#define ICH_ALI_SS_PRI_ID (3<<3)
	266
	267	#define ICH_ALI_IF_AC97SP (1<<21)
	268	#define ICH_ALI_IF_MC (1<<20)
	269	#define ICH_ALI_IF_PI (1<<19)
	270	#define ICH_ALI_IF_MC2 (1<<18)
	271	#define ICH_ALI_IF_PI2 (1<<17)
	272	#define ICH_ALI_IF_LINE_SRC (1<<15) /* 0/1 = slot 3/6 */
	273	#define ICH_ALI_IF_MIC_SRC (1<<14) /* 0/1 = slot 3/6 */
	274	#define ICH_ALI_IF_SPDF_SRC (3<<12) /* 00 = PCM, 01 = AC97-in, 10 = spdif-in, 11 = i2s */
	275	#define ICH_ALI_IF_AC97_OUT (3<<8) /* 00 = PCM, 10 = spdif-in, 11 = i2s */
	276	#define ICH_ALI_IF_PO_SPDF (1<<3)
	277	#define ICH_ALI_IF_PO (1<<1)
	278
	279	/*
[679]	280	*
[32]	281	*/
	282
[305]	283	enum {
	284	ICHD_PCMIN,
	285	ICHD_PCMOUT,
	286	ICHD_MIC,
	287	ICHD_MIC2,
	288	ICHD_PCM2IN,
	289	ICHD_SPBAR,
	290	ICHD_LAST = ICHD_SPBAR
	291	};
	292	enum {
	293	NVD_PCMIN,
	294	NVD_PCMOUT,
	295	NVD_MIC,
	296	NVD_SPBAR,
	297	NVD_LAST = NVD_SPBAR
	298	};
	299	enum {
	300	ALID_PCMIN,
	301	ALID_PCMOUT,
	302	ALID_MIC,
	303	ALID_AC97SPDIFOUT,
	304	ALID_SPDIFIN,
	305	ALID_SPDIFOUT,
	306	ALID_LAST = ALID_SPDIFOUT
	307	};
[32]	308
[305]	309	#define get_ichdev(substream) (substream->runtime->private_data)
[32]	310
[305]	311	struct ichdev {
	312	unsigned int ichd; /* ich device number */
	313	unsigned long reg_offset; /* offset to bmaddr */
[679]	314	__le32 bdbar; / CPU address (32bit) */
[305]	315	unsigned int bdbar_addr; /* PCI bus address (32bit) */
	316	struct snd_pcm_substream *substream;
	317	unsigned int physbuf; /* physical address (32bit) */
	318	unsigned int size;
	319	unsigned int fragsize;
	320	unsigned int fragsize1;
	321	unsigned int position;
	322	unsigned int pos_shift;
[426]	323	unsigned int last_pos;
[305]	324	int frags;
	325	int lvi;
	326	int lvi_frag;
	327	int civ;
	328	int ack;
	329	int ack_reload;
	330	unsigned int ack_bit;
	331	unsigned int roff_sr;
	332	unsigned int roff_picb;
	333	unsigned int int_sta_mask; /* interrupt status mask */
	334	unsigned int ali_slot; /* ALI DMA slot */
	335	struct ac97_pcm *pcm;
	336	int pcm_open_flag;
[689]	337	unsigned int prepared:1;
[305]	338	unsigned int suspended: 1;
[35]	339	};
[32]	340
[35]	341	struct intel8x0 {
[305]	342	unsigned int device_type;
[32]	343
[305]	344	int irq;
[32]	345
[305]	346	void __iomem *addr;
	347	void __iomem *bmaddr;
[32]	348
[305]	349	struct pci_dev *pci;
	350	struct snd_card *card;
[32]	351
[305]	352	int pcm_devs;
	353	struct snd_pcm *pcm[6];
	354	struct ichdev ichd[6];
[32]	355
[305]	356	unsigned multi4: 1,
	357	multi6: 1,
[358]	358	multi8 :1,
[305]	359	dra: 1,
	360	smp20bit: 1;
	361	unsigned in_ac97_init: 1,
	362	in_sdin_init: 1;
	363	unsigned in_measurement: 1; /* during ac97 clock measurement */
	364	unsigned fix_nocache: 1; /* workaround for 440MX */
	365	unsigned buggy_irq: 1; /* workaround for buggy mobos */
	366	unsigned xbox: 1; /* workaround for Xbox AC'97 detection */
	367	unsigned buggy_semaphore: 1; /* workaround for buggy codec semaphore */
[679]	368	unsigned inside_vm: 1; /* enable VM optimization */
[32]	369
[305]	370	int spdif_idx; /* SPDIF BAR index; _SPBAR or -1 if use PCMOUT /
	371	unsigned int sdm_saved; /* SDM reg value */
[32]	372
[305]	373	struct snd_ac97_bus *ac97_bus;
	374	struct snd_ac97 *ac97[3];
	375	unsigned int ac97_sdin[3];
	376	unsigned int max_codecs, ncodecs;
[679]	377	const unsigned int *codec_bit;
[305]	378	unsigned int codec_isr_bits;
	379	unsigned int codec_ready_bits;
[32]	380
[305]	381	spinlock_t reg_lock;
	382
	383	u32 bdbars_count;
[717]	384	struct snd_dma_buffer *bdbars;
[305]	385	u32 int_sta_reg; /* interrupt status register */
	386	u32 int_sta_mask; /* interrupt status mask */
[32]	387	};
	388
[679]	389	static const struct pci_device_id snd_intel8x0_ids[] = {
[464]	390	{ PCI_VDEVICE(INTEL, 0x2415), DEVICE_INTEL }, /* 82801AA */
	391	{ PCI_VDEVICE(INTEL, 0x2425), DEVICE_INTEL }, /* 82901AB */
	392	{ PCI_VDEVICE(INTEL, 0x2445), DEVICE_INTEL }, /* 82801BA */
	393	{ PCI_VDEVICE(INTEL, 0x2485), DEVICE_INTEL }, /* ICH3 */
	394	{ PCI_VDEVICE(INTEL, 0x24c5), DEVICE_INTEL_ICH4 }, /* ICH4 */
	395	{ PCI_VDEVICE(INTEL, 0x24d5), DEVICE_INTEL_ICH4 }, /* ICH5 */
	396	{ PCI_VDEVICE(INTEL, 0x25a6), DEVICE_INTEL_ICH4 }, /* ESB */
	397	{ PCI_VDEVICE(INTEL, 0x266e), DEVICE_INTEL_ICH4 }, /* ICH6 */
	398	{ PCI_VDEVICE(INTEL, 0x27de), DEVICE_INTEL_ICH4 }, /* ICH7 */
	399	{ PCI_VDEVICE(INTEL, 0x2698), DEVICE_INTEL_ICH4 }, /* ESB2 */
	400	{ PCI_VDEVICE(INTEL, 0x7195), DEVICE_INTEL }, /* 440MX */
	401	{ PCI_VDEVICE(SI, 0x7012), DEVICE_SIS }, /* SI7012 */
	402	{ PCI_VDEVICE(NVIDIA, 0x01b1), DEVICE_NFORCE }, /* NFORCE */
	403	{ PCI_VDEVICE(NVIDIA, 0x003a), DEVICE_NFORCE }, /* MCP04 */
	404	{ PCI_VDEVICE(NVIDIA, 0x006a), DEVICE_NFORCE }, /* NFORCE2 */
	405	{ PCI_VDEVICE(NVIDIA, 0x0059), DEVICE_NFORCE }, /* CK804 */
	406	{ PCI_VDEVICE(NVIDIA, 0x008a), DEVICE_NFORCE }, /* CK8 */
	407	{ PCI_VDEVICE(NVIDIA, 0x00da), DEVICE_NFORCE }, /* NFORCE3 */
	408	{ PCI_VDEVICE(NVIDIA, 0x00ea), DEVICE_NFORCE }, /* CK8S */
	409	{ PCI_VDEVICE(NVIDIA, 0x026b), DEVICE_NFORCE }, /* MCP51 */
	410	{ PCI_VDEVICE(AMD, 0x746d), DEVICE_INTEL }, /* AMD8111 */
	411	{ PCI_VDEVICE(AMD, 0x7445), DEVICE_INTEL }, /* AMD768 */
	412	{ PCI_VDEVICE(AL, 0x5455), DEVICE_ALI }, /* Ali5455 */
[305]	413	{ 0, }
[32]	414	};
	415
	416	MODULE_DEVICE_TABLE(pci, snd_intel8x0_ids);
	417
	418	/*
	419	* Lowlevel I/O - busmaster
	420	*/
	421
[305]	422	static inline u8 igetbyte(struct intel8x0 *chip, u32 offset)
[32]	423	{
[305]	424	return ioread8(chip->bmaddr + offset);
[32]	425	}
	426
[305]	427	static inline u16 igetword(struct intel8x0 *chip, u32 offset)
[32]	428	{
[305]	429	return ioread16(chip->bmaddr + offset);
[32]	430	}
	431
[305]	432	static inline u32 igetdword(struct intel8x0 *chip, u32 offset)
[32]	433	{
[305]	434	return ioread32(chip->bmaddr + offset);
[32]	435	}
	436
[305]	437	static inline void iputbyte(struct intel8x0 *chip, u32 offset, u8 val)
[32]	438	{
[305]	439	iowrite8(val, chip->bmaddr + offset);
[32]	440	}
	441
[305]	442	static inline void iputword(struct intel8x0 *chip, u32 offset, u16 val)
[32]	443	{
[305]	444	iowrite16(val, chip->bmaddr + offset);
[32]	445	}
	446
[305]	447	static inline void iputdword(struct intel8x0 *chip, u32 offset, u32 val)
[32]	448	{
[305]	449	iowrite32(val, chip->bmaddr + offset);
[32]	450	}
	451
	452	/*
	453	* Lowlevel I/O - AC'97 registers
	454	*/
	455
[305]	456	static inline u16 iagetword(struct intel8x0 *chip, u32 offset)
[32]	457	{
[305]	458	return ioread16(chip->addr + offset);
[32]	459	}
	460
[305]	461	static inline void iaputword(struct intel8x0 *chip, u32 offset, u16 val)
[32]	462	{
[305]	463	iowrite16(val, chip->addr + offset);
[32]	464	}
	465
	466	/*
	467	* Basic I/O
	468	*/
	469
	470	/*
	471	* access to AC97 codec via normal i/o (for ICH and SIS7012)
	472	*/
	473
[35]	474	static int snd_intel8x0_codec_semaphore(struct intel8x0 *chip, unsigned int codec)
[32]	475	{
[305]	476	int time;
	477
	478	if (codec > 2)
	479	return -EIO;
	480	if (chip->in_sdin_init) {
	481	/* we don't know the ready bit assignment at the moment */
	482	/* so we check any */
	483	codec = chip->codec_isr_bits;
	484	} else {
	485	codec = chip->codec_bit[chip->ac97_sdin[codec]];
	486	}
[32]	487
[305]	488	/* codec ready ? */
	489	if ((igetdword(chip, ICHREG(GLOB_STA)) & codec) == 0)
	490	return -EIO;
[32]	491
[305]	492	if (chip->buggy_semaphore)
	493	return 0; /* just ignore ... */
[32]	494
[305]	495	/* Anyone holding a semaphore for 1 msec should be shot... */
	496	time = 100;
	497	do {
	498	if (!(igetbyte(chip, ICHREG(ACC_SEMA)) & ICH_CAS))
	499	return 0;
	500	udelay(10);
	501	} while (time--);
[32]	502
[679]	503	/* access to some forbidden (non existent) ac97 registers will not
[305]	504	* reset the semaphore. So even if you don't get the semaphore, still
	505	* continue the access. We don't need the semaphore anyway. */
[679]	506	dev_err(chip->card->dev,
	507	"codec_semaphore: semaphore is not ready [0x%x][0x%x]\n",
[305]	508	igetbyte(chip, ICHREG(ACC_SEMA)), igetdword(chip, ICHREG(GLOB_STA)));
	509	iagetword(chip, 0); /* clear semaphore flag */
	510	/* I don't care about the semaphore */
	511	return -EBUSY;
[32]	512	}
[485]	513
[305]	514	static void snd_intel8x0_codec_write(struct snd_ac97 *ac97,
	515	unsigned short reg,
	516	unsigned short val)
[32]	517	{
[305]	518	struct intel8x0 *chip = ac97->private_data;
	519
	520	if (snd_intel8x0_codec_semaphore(chip, ac97->num) < 0) {
	521	if (! chip->in_ac97_init)
[679]	522	dev_err(chip->card->dev,
	523	"codec_write %d: semaphore is not ready for register 0x%x\n",
	524	ac97->num, reg);
[305]	525	}
	526	iaputword(chip, reg + ac97->num * 0x80, val);
[32]	527	}
	528
[305]	529	static unsigned short snd_intel8x0_codec_read(struct snd_ac97 *ac97,
	530	unsigned short reg)
[32]	531	{
[305]	532	struct intel8x0 *chip = ac97->private_data;
	533	unsigned short res;
	534	unsigned int tmp;
[32]	535
[305]	536	if (snd_intel8x0_codec_semaphore(chip, ac97->num) < 0) {
	537	if (! chip->in_ac97_init)
[679]	538	dev_err(chip->card->dev,
	539	"codec_read %d: semaphore is not ready for register 0x%x\n",
	540	ac97->num, reg);
[305]	541	res = 0xffff;
	542	} else {
	543	res = iagetword(chip, reg + ac97->num * 0x80);
[703]	544	tmp = igetdword(chip, ICHREG(GLOB_STA));
	545	if (tmp & ICH_RCS) {
[305]	546	/* reset RCS and preserve other R/WC bits */
	547	iputdword(chip, ICHREG(GLOB_STA), tmp &
	548	~(chip->codec_ready_bits \| ICH_GSCI));
	549	if (! chip->in_ac97_init)
[679]	550	dev_err(chip->card->dev,
	551	"codec_read %d: read timeout for register 0x%x\n",
	552	ac97->num, reg);
[305]	553	res = 0xffff;
	554	}
	555	}
	556	return res;
[32]	557	}
	558
[679]	559	static void snd_intel8x0_codec_read_test(struct intel8x0 *chip,
	560	unsigned int codec)
[32]	561	{
[305]	562	unsigned int tmp;
[32]	563
[305]	564	if (snd_intel8x0_codec_semaphore(chip, codec) >= 0) {
	565	iagetword(chip, codec * 0x80);
[703]	566	tmp = igetdword(chip, ICHREG(GLOB_STA));
	567	if (tmp & ICH_RCS) {
[305]	568	/* reset RCS and preserve other R/WC bits */
	569	iputdword(chip, ICHREG(GLOB_STA), tmp &
	570	~(chip->codec_ready_bits \| ICH_GSCI));
	571	}
	572	}
[32]	573	}
	574
	575	/*
	576	* access to AC97 for Ali5455
	577	*/
[35]	578	static int snd_intel8x0_ali_codec_ready(struct intel8x0 *chip, int mask)
[32]	579	{
[305]	580	int count = 0;
	581	for (count = 0; count < 0x7f; count++) {
	582	int val = igetbyte(chip, ICHREG(ALI_CSPSR));
	583	if (val & mask)
	584	return 0;
	585	}
	586	if (! chip->in_ac97_init)
[679]	587	dev_warn(chip->card->dev, "AC97 codec ready timeout.\n");
[305]	588	return -EBUSY;
[32]	589	}
	590
[35]	591	static int snd_intel8x0_ali_codec_semaphore(struct intel8x0 *chip)
[32]	592	{
[305]	593	int time = 100;
	594	if (chip->buggy_semaphore)
	595	return 0; /* just ignore ... */
[426]	596	while (--time && (igetdword(chip, ICHREG(ALI_CAS)) & ALI_CAS_SEM_BUSY))
[305]	597	udelay(1);
	598	if (! time && ! chip->in_ac97_init)
[679]	599	dev_warn(chip->card->dev, "ali_codec_semaphore timeout\n");
[305]	600	return snd_intel8x0_ali_codec_ready(chip, ALI_CSPSR_CODEC_READY);
[32]	601	}
	602
[305]	603	static unsigned short snd_intel8x0_ali_codec_read(struct snd_ac97 *ac97, unsigned short reg)
[32]	604	{
[305]	605	struct intel8x0 *chip = ac97->private_data;
	606	unsigned short data = 0xffff;
[32]	607
[305]	608	if (snd_intel8x0_ali_codec_semaphore(chip))
	609	goto __err;
	610	reg \|= ALI_CPR_ADDR_READ;
	611	if (ac97->num)
	612	reg \|= ALI_CPR_ADDR_SECONDARY;
	613	iputword(chip, ICHREG(ALI_CPR_ADDR), reg);
	614	if (snd_intel8x0_ali_codec_ready(chip, ALI_CSPSR_READ_OK))
	615	goto __err;
	616	data = igetword(chip, ICHREG(ALI_SPR));
	617	__err:
	618	return data;
[32]	619	}
	620
[305]	621	static void snd_intel8x0_ali_codec_write(struct snd_ac97 *ac97, unsigned short reg,
	622	unsigned short val)
[32]	623	{
[305]	624	struct intel8x0 *chip = ac97->private_data;
[32]	625
[305]	626	if (snd_intel8x0_ali_codec_semaphore(chip))
	627	return;
	628	iputword(chip, ICHREG(ALI_CPR), val);
	629	if (ac97->num)
	630	reg \|= ALI_CPR_ADDR_SECONDARY;
	631	iputword(chip, ICHREG(ALI_CPR_ADDR), reg);
	632	snd_intel8x0_ali_codec_ready(chip, ALI_CSPSR_WRITE_OK);
[32]	633	}
	634
	635
	636	/*
	637	* DMA I/O
	638	*/
[679]	639	static void snd_intel8x0_setup_periods(struct intel8x0 chip, struct ichdev ichdev)
[32]	640	{
[305]	641	int idx;
[679]	642	__le32 *bdbar = ichdev->bdbar;
[305]	643	unsigned long port = ichdev->reg_offset;
[32]	644
[305]	645	iputdword(chip, port + ICH_REG_OFF_BDBAR, ichdev->bdbar_addr);
	646	if (ichdev->size == ichdev->fragsize) {
	647	ichdev->ack_reload = ichdev->ack = 2;
	648	ichdev->fragsize1 = ichdev->fragsize >> 1;
	649	for (idx = 0; idx < (ICH_REG_LVI_MASK + 1) * 2; idx += 4) {
	650	bdbar[idx + 0] = cpu_to_le32(ichdev->physbuf);
	651	bdbar[idx + 1] = cpu_to_le32(0x80000000 \| /* interrupt on completion */
	652	ichdev->fragsize1 >> ichdev->pos_shift);
	653	bdbar[idx + 2] = cpu_to_le32(ichdev->physbuf + (ichdev->size >> 1));
	654	bdbar[idx + 3] = cpu_to_le32(0x80000000 \| /* interrupt on completion */
	655	ichdev->fragsize1 >> ichdev->pos_shift);
	656	}
	657	ichdev->frags = 2;
	658	} else {
	659	ichdev->ack_reload = ichdev->ack = 1;
	660	ichdev->fragsize1 = ichdev->fragsize;
	661	for (idx = 0; idx < (ICH_REG_LVI_MASK + 1) * 2; idx += 2) {
	662	bdbar[idx + 0] = cpu_to_le32(ichdev->physbuf +
	663	(((idx >> 1) * ichdev->fragsize) %
	664	ichdev->size));
	665	bdbar[idx + 1] = cpu_to_le32(0x80000000 \| /* interrupt on completion */
	666	ichdev->fragsize >> ichdev->pos_shift);
[32]	667	#if 0
[679]	668	dev_dbg(chip->card->dev, "bdbar[%i] = 0x%x [0x%x]\n",
[305]	669	idx + 0, bdbar[idx + 0], bdbar[idx + 1]);
[32]	670	#endif
[305]	671	}
	672	ichdev->frags = ichdev->size / ichdev->fragsize;
	673	}
	674	iputbyte(chip, port + ICH_REG_OFF_LVI, ichdev->lvi = ICH_REG_LVI_MASK);
	675	ichdev->civ = 0;
	676	iputbyte(chip, port + ICH_REG_OFF_CIV, 0);
	677	ichdev->lvi_frag = ICH_REG_LVI_MASK % ichdev->frags;
	678	ichdev->position = 0;
	679	#if 0
[679]	680	dev_dbg(chip->card->dev,
	681	"lvi_frag = %i, frags = %i, period_size = 0x%x, period_size1 = 0x%x\n",
[426]	682	ichdev->lvi_frag, ichdev->frags, ichdev->fragsize,
	683	ichdev->fragsize1);
[305]	684	#endif
	685	/* clear interrupts */
	686	iputbyte(chip, port + ichdev->roff_sr, ICH_FIFOE \| ICH_BCIS \| ICH_LVBCI);
[32]	687	}
	688
	689	/*
	690	* Interrupt handler
	691	*/
	692
[35]	693	static inline void snd_intel8x0_update(struct intel8x0 chip, struct ichdev ichdev)
[32]	694	{
[305]	695	unsigned long port = ichdev->reg_offset;
	696	unsigned long flags;
	697	int status, civ, i, step;
	698	int ack = 0;
[32]	699
[689]	700	if (!(ichdev->prepared \|\| chip->in_measurement) \|\| ichdev->suspended)
	701	return;
	702
[305]	703	spin_lock_irqsave(&chip->reg_lock, flags);
	704	status = igetbyte(chip, port + ichdev->roff_sr);
	705	civ = igetbyte(chip, port + ICH_REG_OFF_CIV);
	706	if (!(status & ICH_BCIS)) {
	707	step = 0;
	708	} else if (civ == ichdev->civ) {
	709	step = 1;
	710	ichdev->civ++;
	711	ichdev->civ &= ICH_REG_LVI_MASK;
	712	} else {
	713	step = civ - ichdev->civ;
	714	if (step < 0)
	715	step += ICH_REG_LVI_MASK + 1;
	716	ichdev->civ = civ;
	717	}
[32]	718
[305]	719	ichdev->position += step * ichdev->fragsize1;
	720	if (! chip->in_measurement)
	721	ichdev->position %= ichdev->size;
	722	ichdev->lvi += step;
	723	ichdev->lvi &= ICH_REG_LVI_MASK;
	724	iputbyte(chip, port + ICH_REG_OFF_LVI, ichdev->lvi);
	725	for (i = 0; i < step; i++) {
	726	ichdev->lvi_frag++;
	727	ichdev->lvi_frag %= ichdev->frags;
	728	ichdev->bdbar[ichdev->lvi * 2] = cpu_to_le32(ichdev->physbuf + ichdev->lvi_frag * ichdev->fragsize1);
	729	#if 0
[679]	730	dev_dbg(chip->card->dev,
	731	"new: bdbar[%i] = 0x%x [0x%x], prefetch = %i, all = 0x%x, 0x%x\n",
[305]	732	ichdev->lvi * 2, ichdev->bdbar[ichdev->lvi * 2],
	733	ichdev->bdbar[ichdev->lvi * 2 + 1], inb(ICH_REG_OFF_PIV + port),
	734	inl(port + 4), inb(port + ICH_REG_OFF_CR));
	735	#endif
	736	if (--ichdev->ack == 0) {
	737	ichdev->ack = ichdev->ack_reload;
	738	ack = 1;
	739	}
	740	}
	741	spin_unlock_irqrestore(&chip->reg_lock, flags);
	742	if (ack && ichdev->substream) {
	743	snd_pcm_period_elapsed(ichdev->substream);
	744	}
	745	iputbyte(chip, port + ichdev->roff_sr,
	746	status & (ICH_FIFOE \| ICH_BCIS \| ICH_LVBCI));
[32]	747	}
	748
[305]	749	static irqreturn_t snd_intel8x0_interrupt(int irq, void *dev_id)
[32]	750	{
[305]	751	struct intel8x0 *chip = dev_id;
	752	struct ichdev *ichdev;
	753	unsigned int status;
	754	unsigned int i;
[32]	755
[305]	756	status = igetdword(chip, chip->int_sta_reg);
	757	if (status == 0xffffffff) /* we are not yet resumed */
	758	return IRQ_NONE;
[32]	759
[305]	760	if ((status & chip->int_sta_mask) == 0) {
	761	if (status) {
	762	/* ack */
	763	iputdword(chip, chip->int_sta_reg, status);
	764	if (! chip->buggy_irq)
	765	status = 0;
	766	}
	767	return IRQ_RETVAL(status);
	768	}
[32]	769
[305]	770	for (i = 0; i < chip->bdbars_count; i++) {
	771	ichdev = &chip->ichd[i];
	772	if (status & ichdev->int_sta_mask)
	773	snd_intel8x0_update(chip, ichdev);
	774	}
[32]	775
[305]	776	/* ack them */
	777	iputdword(chip, chip->int_sta_reg, status & chip->int_sta_mask);
	778
	779	return IRQ_HANDLED;
[32]	780	}
	781
	782	/*
	783	* PCM part
	784	*/
	785
[305]	786	static int snd_intel8x0_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
[32]	787	{
[305]	788	struct intel8x0 *chip = snd_pcm_substream_chip(substream);
	789	struct ichdev *ichdev = get_ichdev(substream);
	790	unsigned char val = 0;
	791	unsigned long port = ichdev->reg_offset;
[32]	792
[305]	793	switch (cmd) {
	794	case SNDRV_PCM_TRIGGER_RESUME:
	795	ichdev->suspended = 0;
[679]	796	fallthrough;
[305]	797	case SNDRV_PCM_TRIGGER_START:
[426]	798	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
[305]	799	val = ICH_IOCE \| ICH_STARTBM;
[426]	800	ichdev->last_pos = ichdev->position;
[305]	801	break;
	802	case SNDRV_PCM_TRIGGER_SUSPEND:
	803	ichdev->suspended = 1;
[679]	804	fallthrough;
[305]	805	case SNDRV_PCM_TRIGGER_STOP:
	806	val = 0;
	807	break;
	808	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
	809	val = ICH_IOCE;
	810	break;
	811	default:
	812	return -EINVAL;
	813	}
	814	iputbyte(chip, port + ICH_REG_OFF_CR, val);
	815	if (cmd == SNDRV_PCM_TRIGGER_STOP) {
	816	/* wait until DMA stopped */
	817	while (!(igetbyte(chip, port + ichdev->roff_sr) & ICH_DCH)) ;
	818	/* reset whole DMA things */
	819	iputbyte(chip, port + ICH_REG_OFF_CR, ICH_RESETREGS);
	820	}
	821	return 0;
[32]	822	}
	823
[305]	824	static int snd_intel8x0_ali_trigger(struct snd_pcm_substream *substream, int cmd)
[32]	825	{
[305]	826	struct intel8x0 *chip = snd_pcm_substream_chip(substream);
	827	struct ichdev *ichdev = get_ichdev(substream);
	828	unsigned long port = ichdev->reg_offset;
[679]	829	static const int fiforeg[] = {
[305]	830	ICHREG(ALI_FIFOCR1), ICHREG(ALI_FIFOCR2), ICHREG(ALI_FIFOCR3)
	831	};
	832	unsigned int val, fifo;
[32]	833
[305]	834	val = igetdword(chip, ICHREG(ALI_DMACR));
	835	switch (cmd) {
	836	case SNDRV_PCM_TRIGGER_RESUME:
	837	ichdev->suspended = 0;
[679]	838	fallthrough;
[305]	839	case SNDRV_PCM_TRIGGER_START:
	840	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
	841	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
	842	/* clear FIFO for synchronization of channels */
	843	fifo = igetdword(chip, fiforeg[ichdev->ali_slot / 4]);
[679]	844	fifo &= ~(0xff << (ichdev->ali_slot % 4));
	845	fifo \|= 0x83 << (ichdev->ali_slot % 4);
[305]	846	iputdword(chip, fiforeg[ichdev->ali_slot / 4], fifo);
	847	}
	848	iputbyte(chip, port + ICH_REG_OFF_CR, ICH_IOCE);
	849	val &= ~(1 << (ichdev->ali_slot + 16)); /* clear PAUSE flag */
	850	/* start DMA */
	851	iputdword(chip, ICHREG(ALI_DMACR), val \| (1 << ichdev->ali_slot));
	852	break;
	853	case SNDRV_PCM_TRIGGER_SUSPEND:
	854	ichdev->suspended = 1;
[679]	855	fallthrough;
[305]	856	case SNDRV_PCM_TRIGGER_STOP:
	857	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
	858	/* pause */
	859	iputdword(chip, ICHREG(ALI_DMACR), val \| (1 << (ichdev->ali_slot + 16)));
	860	iputbyte(chip, port + ICH_REG_OFF_CR, 0);
	861	while (igetbyte(chip, port + ICH_REG_OFF_CR))
	862	;
	863	if (cmd == SNDRV_PCM_TRIGGER_PAUSE_PUSH)
	864	break;
	865	/* reset whole DMA things */
	866	iputbyte(chip, port + ICH_REG_OFF_CR, ICH_RESETREGS);
	867	/* clear interrupts */
	868	iputbyte(chip, port + ICH_REG_OFF_SR,
	869	igetbyte(chip, port + ICH_REG_OFF_SR) \| 0x1e);
	870	iputdword(chip, ICHREG(ALI_INTERRUPTSR),
	871	igetdword(chip, ICHREG(ALI_INTERRUPTSR)) & ichdev->int_sta_mask);
	872	break;
	873	default:
	874	return -EINVAL;
	875	}
	876	return 0;
[32]	877	}
	878
[305]	879	static int snd_intel8x0_hw_params(struct snd_pcm_substream *substream,
	880	struct snd_pcm_hw_params *hw_params)
[32]	881	{
[305]	882	struct intel8x0 *chip = snd_pcm_substream_chip(substream);
	883	struct ichdev *ichdev = get_ichdev(substream);
	884	int dbl = params_rate(hw_params) > 48000;
	885	int err;
[32]	886
[305]	887	if (ichdev->pcm_open_flag) {
	888	snd_ac97_pcm_close(ichdev->pcm);
	889	ichdev->pcm_open_flag = 0;
[689]	890	ichdev->prepared = 0;
[305]	891	}
	892	err = snd_ac97_pcm_open(ichdev->pcm, params_rate(hw_params),
	893	params_channels(hw_params),
	894	ichdev->pcm->r[dbl].slots);
	895	if (err >= 0) {
	896	ichdev->pcm_open_flag = 1;
	897	/* Force SPDIF setting */
	898	if (ichdev->ichd == ICHD_PCMOUT && chip->spdif_idx < 0)
	899	snd_ac97_set_rate(ichdev->pcm->r[0].codec[0], AC97_SPDIF,
	900	params_rate(hw_params));
	901	}
	902	return err;
[32]	903	}
	904
[305]	905	static int snd_intel8x0_hw_free(struct snd_pcm_substream *substream)
[32]	906	{
[305]	907	struct ichdev *ichdev = get_ichdev(substream);
[32]	908
[305]	909	if (ichdev->pcm_open_flag) {
	910	snd_ac97_pcm_close(ichdev->pcm);
	911	ichdev->pcm_open_flag = 0;
[689]	912	ichdev->prepared = 0;
[305]	913	}
[679]	914	return 0;
[32]	915	}
	916
[35]	917	static void snd_intel8x0_setup_pcm_out(struct intel8x0 *chip,
[305]	918	struct snd_pcm_runtime *runtime)
[32]	919	{
[305]	920	unsigned int cnt;
	921	int dbl = runtime->rate > 48000;
[32]	922
[305]	923	spin_lock_irq(&chip->reg_lock);
	924	switch (chip->device_type) {
	925	case DEVICE_ALI:
	926	cnt = igetdword(chip, ICHREG(ALI_SCR));
	927	cnt &= ~ICH_ALI_SC_PCM_246_MASK;
	928	if (runtime->channels == 4 \|\| dbl)
	929	cnt \|= ICH_ALI_SC_PCM_4;
	930	else if (runtime->channels == 6)
	931	cnt \|= ICH_ALI_SC_PCM_6;
	932	iputdword(chip, ICHREG(ALI_SCR), cnt);
	933	break;
	934	case DEVICE_SIS:
	935	cnt = igetdword(chip, ICHREG(GLOB_CNT));
	936	cnt &= ~ICH_SIS_PCM_246_MASK;
	937	if (runtime->channels == 4 \|\| dbl)
	938	cnt \|= ICH_SIS_PCM_4;
	939	else if (runtime->channels == 6)
	940	cnt \|= ICH_SIS_PCM_6;
	941	iputdword(chip, ICHREG(GLOB_CNT), cnt);
	942	break;
	943	default:
	944	cnt = igetdword(chip, ICHREG(GLOB_CNT));
	945	cnt &= ~(ICH_PCM_246_MASK \| ICH_PCM_20BIT);
	946	if (runtime->channels == 4 \|\| dbl)
	947	cnt \|= ICH_PCM_4;
	948	else if (runtime->channels == 6)
	949	cnt \|= ICH_PCM_6;
[358]	950	else if (runtime->channels == 8)
	951	cnt \|= ICH_PCM_8;
[305]	952	if (chip->device_type == DEVICE_NFORCE) {
	953	/* reset to 2ch once to keep the 6 channel data in alignment,
	954	* to start from Front Left always
	955	*/
	956	if (cnt & ICH_PCM_246_MASK) {
	957	iputdword(chip, ICHREG(GLOB_CNT), cnt & ~ICH_PCM_246_MASK);
	958	spin_unlock_irq(&chip->reg_lock);
	959	msleep(50); /* grrr... */
	960	spin_lock_irq(&chip->reg_lock);
	961	}
	962	} else if (chip->device_type == DEVICE_INTEL_ICH4) {
	963	if (runtime->sample_bits > 16)
	964	cnt \|= ICH_PCM_20BIT;
	965	}
	966	iputdword(chip, ICHREG(GLOB_CNT), cnt);
	967	break;
	968	}
	969	spin_unlock_irq(&chip->reg_lock);
[32]	970	}
	971
[305]	972	static int snd_intel8x0_pcm_prepare(struct snd_pcm_substream *substream)
[32]	973	{
[305]	974	struct intel8x0 *chip = snd_pcm_substream_chip(substream);
	975	struct snd_pcm_runtime *runtime = substream->runtime;
	976	struct ichdev *ichdev = get_ichdev(substream);
[32]	977
[305]	978	ichdev->physbuf = runtime->dma_addr;
	979	ichdev->size = snd_pcm_lib_buffer_bytes(substream);
	980	ichdev->fragsize = snd_pcm_lib_period_bytes(substream);
	981	if (ichdev->ichd == ICHD_PCMOUT) {
	982	snd_intel8x0_setup_pcm_out(chip, runtime);
	983	if (chip->device_type == DEVICE_INTEL_ICH4)
	984	ichdev->pos_shift = (runtime->sample_bits > 16) ? 2 : 1;
	985	}
	986	snd_intel8x0_setup_periods(chip, ichdev);
[689]	987	ichdev->prepared = 1;
[305]	988	return 0;
[32]	989	}
	990
[305]	991	static snd_pcm_uframes_t snd_intel8x0_pcm_pointer(struct snd_pcm_substream *substream)
[32]	992	{
[305]	993	struct intel8x0 *chip = snd_pcm_substream_chip(substream);
	994	struct ichdev *ichdev = get_ichdev(substream);
	995	size_t ptr1, ptr;
[426]	996	int civ, timeout = 10;
[305]	997	unsigned int position;
[32]	998
[305]	999	spin_lock(&chip->reg_lock);
	1000	do {
	1001	civ = igetbyte(chip, ichdev->reg_offset + ICH_REG_OFF_CIV);
	1002	ptr1 = igetword(chip, ichdev->reg_offset + ichdev->roff_picb);
	1003	position = ichdev->position;
	1004	if (ptr1 == 0) {
	1005	udelay(10);
	1006	continue;
	1007	}
[679]	1008	if (civ != igetbyte(chip, ichdev->reg_offset + ICH_REG_OFF_CIV))
	1009	continue;
	1010
	1011	/* IO read operation is very expensive inside virtual machine
	1012	* as it is emulated. The probability that subsequent PICB read
	1013	* will return different result is high enough to loop till
	1014	* timeout here.
	1015	* Same CIV is strict enough condition to be sure that PICB
	1016	* is valid inside VM on emulated card. */
	1017	if (chip->inside_vm)
[305]	1018	break;
[679]	1019	if (ptr1 == igetword(chip, ichdev->reg_offset + ichdev->roff_picb))
	1020	break;
[305]	1021	} while (timeout--);
[464]	1022	ptr = ichdev->last_pos;
[426]	1023	if (ptr1 != 0) {
	1024	ptr1 <<= ichdev->pos_shift;
	1025	ptr = ichdev->fragsize1 - ptr1;
	1026	ptr += position;
[464]	1027	if (ptr < ichdev->last_pos) {
	1028	unsigned int pos_base, last_base;
	1029	pos_base = position / ichdev->fragsize1;
	1030	last_base = ichdev->last_pos / ichdev->fragsize1;
	1031	/* another sanity check; ptr1 can go back to full
	1032	* before the base position is updated
	1033	*/
	1034	if (pos_base == last_base)
	1035	ptr = ichdev->last_pos;
	1036	}
[426]	1037	}
[464]	1038	ichdev->last_pos = ptr;
[305]	1039	spin_unlock(&chip->reg_lock);
	1040	if (ptr >= ichdev->size)
	1041	return 0;
	1042	return bytes_to_frames(substream->runtime, ptr);
[32]	1043	}
	1044
[679]	1045	static const struct snd_pcm_hardware snd_intel8x0_stream =
[32]	1046	{
	1047	.info = (SNDRV_PCM_INFO_MMAP \| SNDRV_PCM_INFO_INTERLEAVED \|
	1048	SNDRV_PCM_INFO_BLOCK_TRANSFER \|
	1049	SNDRV_PCM_INFO_MMAP_VALID \|
	1050	SNDRV_PCM_INFO_PAUSE \|
	1051	SNDRV_PCM_INFO_RESUME),
	1052	.formats = SNDRV_PCM_FMTBIT_S16_LE,
	1053	.rates = SNDRV_PCM_RATE_48000,
	1054	.rate_min = 48000,
	1055	.rate_max = 48000,
	1056	.channels_min = 2,
	1057	.channels_max = 2,
	1058	.buffer_bytes_max = 128 * 1024,
	1059	.period_bytes_min = 32,
	1060	.period_bytes_max = 128 * 1024,
	1061	.periods_min = 1,
	1062	.periods_max = 1024,
	1063	.fifo_size = 0,
	1064	};
	1065
[679]	1066	static const unsigned int channels4[] = {
[305]	1067	2, 4,
[32]	1068	};
	1069
[679]	1070	static const struct snd_pcm_hw_constraint_list hw_constraints_channels4 = {
[32]	1071	.count = ARRAY_SIZE(channels4),
	1072	.list = channels4,
	1073	.mask = 0,
	1074	};
	1075
[679]	1076	static const unsigned int channels6[] = {
[305]	1077	2, 4, 6,
[32]	1078	};
	1079
[679]	1080	static const struct snd_pcm_hw_constraint_list hw_constraints_channels6 = {
[32]	1081	.count = ARRAY_SIZE(channels6),
	1082	.list = channels6,
	1083	.mask = 0,
	1084	};
	1085
[679]	1086	static const unsigned int channels8[] = {
[358]	1087	2, 4, 6, 8,
	1088	};
	1089
[679]	1090	static const struct snd_pcm_hw_constraint_list hw_constraints_channels8 = {
[358]	1091	.count = ARRAY_SIZE(channels8),
	1092	.list = channels8,
	1093	.mask = 0,
	1094	};
	1095
[305]	1096	static int snd_intel8x0_pcm_open(struct snd_pcm_substream substream, struct ichdev ichdev)
[32]	1097	{
[305]	1098	struct intel8x0 *chip = snd_pcm_substream_chip(substream);
	1099	struct snd_pcm_runtime *runtime = substream->runtime;
	1100	int err;
[32]	1101
[305]	1102	ichdev->substream = substream;
	1103	runtime->hw = snd_intel8x0_stream;
	1104	runtime->hw.rates = ichdev->pcm->rates;
	1105	snd_pcm_limit_hw_rates(runtime);
	1106	if (chip->device_type == DEVICE_SIS) {
	1107	runtime->hw.buffer_bytes_max = 64*1024;
	1108	runtime->hw.period_bytes_max = 64*1024;
	1109	}
[703]	1110	err = snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS);
	1111	if (err < 0)
[305]	1112	return err;
	1113	runtime->private_data = ichdev;
	1114	return 0;
[32]	1115	}
	1116
[305]	1117	static int snd_intel8x0_playback_open(struct snd_pcm_substream *substream)
[32]	1118	{
[305]	1119	struct intel8x0 *chip = snd_pcm_substream_chip(substream);
	1120	struct snd_pcm_runtime *runtime = substream->runtime;
	1121	int err;
[32]	1122
[305]	1123	err = snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_PCMOUT]);
	1124	if (err < 0)
	1125	return err;
	1126
[358]	1127	if (chip->multi8) {
	1128	runtime->hw.channels_max = 8;
	1129	snd_pcm_hw_constraint_list(runtime, 0,
	1130	SNDRV_PCM_HW_PARAM_CHANNELS,
	1131	&hw_constraints_channels8);
	1132	} else if (chip->multi6) {
[305]	1133	runtime->hw.channels_max = 6;
	1134	snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
	1135	&hw_constraints_channels6);
	1136	} else if (chip->multi4) {
	1137	runtime->hw.channels_max = 4;
	1138	snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
	1139	&hw_constraints_channels4);
	1140	}
	1141	if (chip->dra) {
	1142	snd_ac97_pcm_double_rate_rules(runtime);
	1143	}
	1144	if (chip->smp20bit) {
	1145	runtime->hw.formats \|= SNDRV_PCM_FMTBIT_S32_LE;
	1146	snd_pcm_hw_constraint_msbits(runtime, 0, 32, 20);
	1147	}
	1148	return 0;
[32]	1149	}
	1150
[305]	1151	static int snd_intel8x0_playback_close(struct snd_pcm_substream *substream)
[32]	1152	{
[305]	1153	struct intel8x0 *chip = snd_pcm_substream_chip(substream);
[32]	1154
[305]	1155	chip->ichd[ICHD_PCMOUT].substream = NULL;
	1156	return 0;
[32]	1157	}
	1158
[305]	1159	static int snd_intel8x0_capture_open(struct snd_pcm_substream *substream)
[32]	1160	{
[305]	1161	struct intel8x0 *chip = snd_pcm_substream_chip(substream);
[32]	1162
[305]	1163	return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_PCMIN]);
[32]	1164	}
	1165
[305]	1166	static int snd_intel8x0_capture_close(struct snd_pcm_substream *substream)
[32]	1167	{
[305]	1168	struct intel8x0 *chip = snd_pcm_substream_chip(substream);
[32]	1169
[305]	1170	chip->ichd[ICHD_PCMIN].substream = NULL;
	1171	return 0;
[32]	1172	}
	1173
[305]	1174	static int snd_intel8x0_mic_open(struct snd_pcm_substream *substream)
[32]	1175	{
[305]	1176	struct intel8x0 *chip = snd_pcm_substream_chip(substream);
[32]	1177
[305]	1178	return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_MIC]);
[32]	1179	}
	1180
[305]	1181	static int snd_intel8x0_mic_close(struct snd_pcm_substream *substream)
[32]	1182	{
[305]	1183	struct intel8x0 *chip = snd_pcm_substream_chip(substream);
[32]	1184
[305]	1185	chip->ichd[ICHD_MIC].substream = NULL;
	1186	return 0;
[32]	1187	}
	1188
[305]	1189	static int snd_intel8x0_mic2_open(struct snd_pcm_substream *substream)
[32]	1190	{
[305]	1191	struct intel8x0 *chip = snd_pcm_substream_chip(substream);
[32]	1192
[305]	1193	return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_MIC2]);
[32]	1194	}
	1195
[305]	1196	static int snd_intel8x0_mic2_close(struct snd_pcm_substream *substream)
[32]	1197	{
[305]	1198	struct intel8x0 *chip = snd_pcm_substream_chip(substream);
[32]	1199
[305]	1200	chip->ichd[ICHD_MIC2].substream = NULL;
	1201	return 0;
[32]	1202	}
	1203
[305]	1204	static int snd_intel8x0_capture2_open(struct snd_pcm_substream *substream)
[32]	1205	{
[305]	1206	struct intel8x0 *chip = snd_pcm_substream_chip(substream);
[32]	1207
[305]	1208	return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_PCM2IN]);
[32]	1209	}
	1210
[305]	1211	static int snd_intel8x0_capture2_close(struct snd_pcm_substream *substream)
[32]	1212	{
[305]	1213	struct intel8x0 *chip = snd_pcm_substream_chip(substream);
[32]	1214
[305]	1215	chip->ichd[ICHD_PCM2IN].substream = NULL;
	1216	return 0;
[32]	1217	}
	1218
[305]	1219	static int snd_intel8x0_spdif_open(struct snd_pcm_substream *substream)
[32]	1220	{
[305]	1221	struct intel8x0 *chip = snd_pcm_substream_chip(substream);
	1222	int idx = chip->device_type == DEVICE_NFORCE ? NVD_SPBAR : ICHD_SPBAR;
[32]	1223
[305]	1224	return snd_intel8x0_pcm_open(substream, &chip->ichd[idx]);
[32]	1225	}
	1226
[305]	1227	static int snd_intel8x0_spdif_close(struct snd_pcm_substream *substream)
[32]	1228	{
[305]	1229	struct intel8x0 *chip = snd_pcm_substream_chip(substream);
	1230	int idx = chip->device_type == DEVICE_NFORCE ? NVD_SPBAR : ICHD_SPBAR;
[32]	1231
[305]	1232	chip->ichd[idx].substream = NULL;
	1233	return 0;
[32]	1234	}
	1235
[305]	1236	static int snd_intel8x0_ali_ac97spdifout_open(struct snd_pcm_substream *substream)
[32]	1237	{
[305]	1238	struct intel8x0 *chip = snd_pcm_substream_chip(substream);
	1239	unsigned int val;
[32]	1240
[305]	1241	spin_lock_irq(&chip->reg_lock);
	1242	val = igetdword(chip, ICHREG(ALI_INTERFACECR));
	1243	val \|= ICH_ALI_IF_AC97SP;
	1244	iputdword(chip, ICHREG(ALI_INTERFACECR), val);
	1245	/* also needs to set ALI_SC_CODEC_SPDF correctly */
	1246	spin_unlock_irq(&chip->reg_lock);
[32]	1247
[305]	1248	return snd_intel8x0_pcm_open(substream, &chip->ichd[ALID_AC97SPDIFOUT]);
[32]	1249	}
	1250
[305]	1251	static int snd_intel8x0_ali_ac97spdifout_close(struct snd_pcm_substream *substream)
[32]	1252	{
[305]	1253	struct intel8x0 *chip = snd_pcm_substream_chip(substream);
	1254	unsigned int val;
[32]	1255
[305]	1256	chip->ichd[ALID_AC97SPDIFOUT].substream = NULL;
	1257	spin_lock_irq(&chip->reg_lock);
	1258	val = igetdword(chip, ICHREG(ALI_INTERFACECR));
	1259	val &= ~ICH_ALI_IF_AC97SP;
	1260	iputdword(chip, ICHREG(ALI_INTERFACECR), val);
	1261	spin_unlock_irq(&chip->reg_lock);
[32]	1262
[305]	1263	return 0;
[32]	1264	}
	1265
[305]	1266	#if 0 // NYI
	1267	static int snd_intel8x0_ali_spdifin_open(struct snd_pcm_substream *substream)
[32]	1268	{
[305]	1269	struct intel8x0 *chip = snd_pcm_substream_chip(substream);
[32]	1270
[305]	1271	return snd_intel8x0_pcm_open(substream, &chip->ichd[ALID_SPDIFIN]);
[32]	1272	}
	1273
[305]	1274	static int snd_intel8x0_ali_spdifin_close(struct snd_pcm_substream *substream)
[32]	1275	{
[305]	1276	struct intel8x0 *chip = snd_pcm_substream_chip(substream);
[32]	1277
[305]	1278	chip->ichd[ALID_SPDIFIN].substream = NULL;
	1279	return 0;
[32]	1280	}
	1281
[305]	1282	static int snd_intel8x0_ali_spdifout_open(struct snd_pcm_substream *substream)
[32]	1283	{
[305]	1284	struct intel8x0 *chip = snd_pcm_substream_chip(substream);
[32]	1285
[305]	1286	return snd_intel8x0_pcm_open(substream, &chip->ichd[ALID_SPDIFOUT]);
[32]	1287	}
	1288
[305]	1289	static int snd_intel8x0_ali_spdifout_close(struct snd_pcm_substream *substream)
[32]	1290	{
[305]	1291	struct intel8x0 *chip = snd_pcm_substream_chip(substream);
[32]	1292
[305]	1293	chip->ichd[ALID_SPDIFOUT].substream = NULL;
	1294	return 0;
[32]	1295	}
	1296	#endif
	1297
[679]	1298	static const struct snd_pcm_ops snd_intel8x0_playback_ops = {
[32]	1299	.open = snd_intel8x0_playback_open,
	1300	.close = snd_intel8x0_playback_close,
	1301	.hw_params = snd_intel8x0_hw_params,
	1302	.hw_free = snd_intel8x0_hw_free,
	1303	.prepare = snd_intel8x0_pcm_prepare,
	1304	.trigger = snd_intel8x0_pcm_trigger,
	1305	.pointer = snd_intel8x0_pcm_pointer,
	1306	};
	1307
[679]	1308	static const struct snd_pcm_ops snd_intel8x0_capture_ops = {
[32]	1309	.open = snd_intel8x0_capture_open,
	1310	.close = snd_intel8x0_capture_close,
	1311	.hw_params = snd_intel8x0_hw_params,
	1312	.hw_free = snd_intel8x0_hw_free,
	1313	.prepare = snd_intel8x0_pcm_prepare,
	1314	.trigger = snd_intel8x0_pcm_trigger,
	1315	.pointer = snd_intel8x0_pcm_pointer,
	1316	};
	1317
[679]	1318	static const struct snd_pcm_ops snd_intel8x0_capture_mic_ops = {
[32]	1319	.open = snd_intel8x0_mic_open,
	1320	.close = snd_intel8x0_mic_close,
	1321	.hw_params = snd_intel8x0_hw_params,
	1322	.hw_free = snd_intel8x0_hw_free,
	1323	.prepare = snd_intel8x0_pcm_prepare,
	1324	.trigger = snd_intel8x0_pcm_trigger,
	1325	.pointer = snd_intel8x0_pcm_pointer,
	1326	};
	1327
[679]	1328	static const struct snd_pcm_ops snd_intel8x0_capture_mic2_ops = {
[32]	1329	.open = snd_intel8x0_mic2_open,
	1330	.close = snd_intel8x0_mic2_close,
	1331	.hw_params = snd_intel8x0_hw_params,
	1332	.hw_free = snd_intel8x0_hw_free,
	1333	.prepare = snd_intel8x0_pcm_prepare,
	1334	.trigger = snd_intel8x0_pcm_trigger,
	1335	.pointer = snd_intel8x0_pcm_pointer,
	1336	};
	1337
[679]	1338	static const struct snd_pcm_ops snd_intel8x0_capture2_ops = {
[32]	1339	.open = snd_intel8x0_capture2_open,
	1340	.close = snd_intel8x0_capture2_close,
	1341	.hw_params = snd_intel8x0_hw_params,
	1342	.hw_free = snd_intel8x0_hw_free,
	1343	.prepare = snd_intel8x0_pcm_prepare,
	1344	.trigger = snd_intel8x0_pcm_trigger,
	1345	.pointer = snd_intel8x0_pcm_pointer,
	1346	};
	1347
[679]	1348	static const struct snd_pcm_ops snd_intel8x0_spdif_ops = {
[32]	1349	.open = snd_intel8x0_spdif_open,
	1350	.close = snd_intel8x0_spdif_close,
	1351	.hw_params = snd_intel8x0_hw_params,
	1352	.hw_free = snd_intel8x0_hw_free,
	1353	.prepare = snd_intel8x0_pcm_prepare,
	1354	.trigger = snd_intel8x0_pcm_trigger,
	1355	.pointer = snd_intel8x0_pcm_pointer,
	1356	};
	1357
[679]	1358	static const struct snd_pcm_ops snd_intel8x0_ali_playback_ops = {
[32]	1359	.open = snd_intel8x0_playback_open,
	1360	.close = snd_intel8x0_playback_close,
	1361	.hw_params = snd_intel8x0_hw_params,
	1362	.hw_free = snd_intel8x0_hw_free,
	1363	.prepare = snd_intel8x0_pcm_prepare,
	1364	.trigger = snd_intel8x0_ali_trigger,
	1365	.pointer = snd_intel8x0_pcm_pointer,
	1366	};
	1367
[679]	1368	static const struct snd_pcm_ops snd_intel8x0_ali_capture_ops = {
[32]	1369	.open = snd_intel8x0_capture_open,
	1370	.close = snd_intel8x0_capture_close,
	1371	.hw_params = snd_intel8x0_hw_params,
	1372	.hw_free = snd_intel8x0_hw_free,
	1373	.prepare = snd_intel8x0_pcm_prepare,
	1374	.trigger = snd_intel8x0_ali_trigger,
	1375	.pointer = snd_intel8x0_pcm_pointer,
	1376	};
	1377
[679]	1378	static const struct snd_pcm_ops snd_intel8x0_ali_capture_mic_ops = {
[32]	1379	.open = snd_intel8x0_mic_open,
	1380	.close = snd_intel8x0_mic_close,
	1381	.hw_params = snd_intel8x0_hw_params,
	1382	.hw_free = snd_intel8x0_hw_free,
	1383	.prepare = snd_intel8x0_pcm_prepare,
	1384	.trigger = snd_intel8x0_ali_trigger,
	1385	.pointer = snd_intel8x0_pcm_pointer,
	1386	};
	1387
[679]	1388	static const struct snd_pcm_ops snd_intel8x0_ali_ac97spdifout_ops = {
[32]	1389	.open = snd_intel8x0_ali_ac97spdifout_open,
	1390	.close = snd_intel8x0_ali_ac97spdifout_close,
	1391	.hw_params = snd_intel8x0_hw_params,
	1392	.hw_free = snd_intel8x0_hw_free,
	1393	.prepare = snd_intel8x0_pcm_prepare,
	1394	.trigger = snd_intel8x0_ali_trigger,
	1395	.pointer = snd_intel8x0_pcm_pointer,
	1396	};
	1397
[305]	1398	#if 0 // NYI
	1399	static struct snd_pcm_ops snd_intel8x0_ali_spdifin_ops = {
[32]	1400	.open = snd_intel8x0_ali_spdifin_open,
	1401	.close = snd_intel8x0_ali_spdifin_close,
	1402	.hw_params = snd_intel8x0_hw_params,
	1403	.hw_free = snd_intel8x0_hw_free,
	1404	.prepare = snd_intel8x0_pcm_prepare,
	1405	.trigger = snd_intel8x0_pcm_trigger,
	1406	.pointer = snd_intel8x0_pcm_pointer,
	1407	};
	1408
[305]	1409	static struct snd_pcm_ops snd_intel8x0_ali_spdifout_ops = {
[32]	1410	.open = snd_intel8x0_ali_spdifout_open,
	1411	.close = snd_intel8x0_ali_spdifout_close,
	1412	.hw_params = snd_intel8x0_hw_params,
	1413	.hw_free = snd_intel8x0_hw_free,
	1414	.prepare = snd_intel8x0_pcm_prepare,
	1415	.trigger = snd_intel8x0_pcm_trigger,
	1416	.pointer = snd_intel8x0_pcm_pointer,
	1417	};
	1418	#endif // NYI
	1419
	1420	struct ich_pcm_table {
[305]	1421	char *suffix;
[679]	1422	const struct snd_pcm_ops *playback_ops;
	1423	const struct snd_pcm_ops *capture_ops;
[305]	1424	size_t prealloc_size;
	1425	size_t prealloc_max_size;
	1426	int ac97_idx;
[32]	1427	};
	1428
[679]	1429	#define intel8x0_dma_type(chip) \
[717]	1430	((chip)->fix_nocache ? SNDRV_DMA_TYPE_DEV_WC : SNDRV_DMA_TYPE_DEV)
[679]	1431
	1432	static int snd_intel8x0_pcm1(struct intel8x0 *chip, int device,
	1433	const struct ich_pcm_table *rec)
[32]	1434	{
[305]	1435	struct snd_pcm *pcm;
[32]	1436	int err;
	1437	char name[32];
	1438
	1439	if (rec->suffix)
	1440	sprintf(name, "Intel ICH - %s", rec->suffix);
	1441	else
	1442	strcpy(name, "Intel ICH");
	1443	err = snd_pcm_new(chip->card, name, device,
	1444	rec->playback_ops ? 1 : 0,
	1445	rec->capture_ops ? 1 : 0, &pcm);
	1446	if (err < 0)
	1447	return err;
	1448
	1449	if (rec->playback_ops)
	1450	snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, rec->playback_ops);
	1451	if (rec->capture_ops)
	1452	snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, rec->capture_ops);
	1453
	1454	pcm->private_data = chip;
	1455	pcm->info_flags = 0;
	1456	if (rec->suffix)
	1457	sprintf(pcm->name, "%s - %s", chip->card->shortname, rec->suffix);
	1458	else
	1459	strcpy(pcm->name, chip->card->shortname);
	1460	chip->pcm[device] = pcm;
	1461
[679]	1462	snd_pcm_set_managed_buffer_all(pcm, intel8x0_dma_type(chip),
	1463	&chip->pci->dev,
	1464	rec->prealloc_size, rec->prealloc_max_size);
[32]	1465
[679]	1466	if (rec->playback_ops &&
	1467	rec->playback_ops->open == snd_intel8x0_playback_open) {
	1468	struct snd_pcm_chmap *chmap;
	1469	int chs = 2;
	1470	if (chip->multi8)
	1471	chs = 8;
	1472	else if (chip->multi6)
	1473	chs = 6;
	1474	else if (chip->multi4)
	1475	chs = 4;
	1476	err = snd_pcm_add_chmap_ctls(pcm, SNDRV_PCM_STREAM_PLAYBACK,
	1477	snd_pcm_alt_chmaps, chs, 0,
	1478	&chmap);
	1479	if (err < 0)
	1480	return err;
	1481	chmap->channel_mask = SND_PCM_CHMAP_MASK_2468;
	1482	chip->ac97[0]->chmaps[SNDRV_PCM_STREAM_PLAYBACK] = chmap;
	1483	}
	1484
[32]	1485	return 0;
	1486	}
	1487
[679]	1488	static const struct ich_pcm_table intel_pcms[] = {
[32]	1489	{
	1490	.playback_ops = &snd_intel8x0_playback_ops,
	1491	.capture_ops = &snd_intel8x0_capture_ops,
	1492	.prealloc_size = 64 * 1024,
	1493	.prealloc_max_size = 128 * 1024,
	1494	},
	1495	{
	1496	.suffix = "MIC ADC",
	1497	.capture_ops = &snd_intel8x0_capture_mic_ops,
	1498	.prealloc_size = 0,
	1499	.prealloc_max_size = 128 * 1024,
	1500	.ac97_idx = ICHD_MIC,
	1501	},
	1502	{
	1503	.suffix = "MIC2 ADC",
	1504	.capture_ops = &snd_intel8x0_capture_mic2_ops,
	1505	.prealloc_size = 0,
	1506	.prealloc_max_size = 128 * 1024,
	1507	.ac97_idx = ICHD_MIC2,
	1508	},
	1509	{
	1510	.suffix = "ADC2",
	1511	.capture_ops = &snd_intel8x0_capture2_ops,
	1512	.prealloc_size = 0,
	1513	.prealloc_max_size = 128 * 1024,
	1514	.ac97_idx = ICHD_PCM2IN,
	1515	},
	1516	{
	1517	.suffix = "IEC958",
	1518	.playback_ops = &snd_intel8x0_spdif_ops,
	1519	.prealloc_size = 64 * 1024,
	1520	.prealloc_max_size = 128 * 1024,
	1521	.ac97_idx = ICHD_SPBAR,
	1522	},
	1523	};
	1524
[679]	1525	static const struct ich_pcm_table nforce_pcms[] = {
[32]	1526	{
	1527	.playback_ops = &snd_intel8x0_playback_ops,
	1528	.capture_ops = &snd_intel8x0_capture_ops,
	1529	.prealloc_size = 64 * 1024,
	1530	.prealloc_max_size = 128 * 1024,
	1531	},
	1532	{
	1533	.suffix = "MIC ADC",
	1534	.capture_ops = &snd_intel8x0_capture_mic_ops,
	1535	.prealloc_size = 0,
	1536	.prealloc_max_size = 128 * 1024,
	1537	.ac97_idx = NVD_MIC,
	1538	},
	1539	{
	1540	.suffix = "IEC958",
	1541	.playback_ops = &snd_intel8x0_spdif_ops,
	1542	.prealloc_size = 64 * 1024,
	1543	.prealloc_max_size = 128 * 1024,
	1544	.ac97_idx = NVD_SPBAR,
	1545	},
	1546	};
	1547
[679]	1548	static const struct ich_pcm_table ali_pcms[] = {
[32]	1549	{
	1550	.playback_ops = &snd_intel8x0_ali_playback_ops,
	1551	.capture_ops = &snd_intel8x0_ali_capture_ops,
	1552	.prealloc_size = 64 * 1024,
	1553	.prealloc_max_size = 128 * 1024,
	1554	},
	1555	{
	1556	.suffix = "MIC ADC",
	1557	.capture_ops = &snd_intel8x0_ali_capture_mic_ops,
	1558	.prealloc_size = 0,
	1559	.prealloc_max_size = 128 * 1024,
	1560	.ac97_idx = ALID_MIC,
	1561	},
	1562	{
	1563	.suffix = "IEC958",
	1564	.playback_ops = &snd_intel8x0_ali_ac97spdifout_ops,
[305]	1565	/* .capture_ops = &snd_intel8x0_ali_spdifin_ops, */
[32]	1566	.prealloc_size = 64 * 1024,
	1567	.prealloc_max_size = 128 * 1024,
	1568	.ac97_idx = ALID_AC97SPDIFOUT,
	1569	},
	1570	#if 0 // NYI
	1571	{
	1572	.suffix = "HW IEC958",
	1573	.playback_ops = &snd_intel8x0_ali_spdifout_ops,
	1574	.prealloc_size = 64 * 1024,
	1575	.prealloc_max_size = 128 * 1024,
	1576	},
	1577	#endif
	1578	};
	1579
[679]	1580	static int snd_intel8x0_pcm(struct intel8x0 *chip)
[32]	1581	{
[305]	1582	int i, tblsize, device, err;
[679]	1583	const struct ich_pcm_table tbl, rec;
[32]	1584
[305]	1585	switch (chip->device_type) {
	1586	case DEVICE_INTEL_ICH4:
	1587	tbl = intel_pcms;
	1588	tblsize = ARRAY_SIZE(intel_pcms);
	1589	if (spdif_aclink)
	1590	tblsize--;
	1591	break;
	1592	case DEVICE_NFORCE:
	1593	tbl = nforce_pcms;
	1594	tblsize = ARRAY_SIZE(nforce_pcms);
	1595	if (spdif_aclink)
	1596	tblsize--;
	1597	break;
	1598	case DEVICE_ALI:
	1599	tbl = ali_pcms;
	1600	tblsize = ARRAY_SIZE(ali_pcms);
	1601	break;
	1602	default:
	1603	tbl = intel_pcms;
	1604	tblsize = 2;
	1605	break;
	1606	}
[32]	1607
[305]	1608	device = 0;
	1609	for (i = 0; i < tblsize; i++) {
	1610	rec = tbl + i;
	1611	if (i > 0 && rec->ac97_idx) {
	1612	/* activate PCM only when associated AC'97 codec */
	1613	if (! chip->ichd[rec->ac97_idx].pcm)
	1614	continue;
	1615	}
	1616	err = snd_intel8x0_pcm1(chip, device, rec);
	1617	if (err < 0)
	1618	return err;
	1619	device++;
	1620	}
[32]	1621
[305]	1622	chip->pcm_devs = device;
	1623	return 0;
[32]	1624	}
[305]	1625
[32]	1626
	1627	/*
	1628	* Mixer part
	1629	*/
	1630
[305]	1631	static void snd_intel8x0_mixer_free_ac97_bus(struct snd_ac97_bus *bus)
[32]	1632	{
[305]	1633	struct intel8x0 *chip = bus->private_data;
	1634	chip->ac97_bus = NULL;
[32]	1635	}
	1636
[305]	1637	static void snd_intel8x0_mixer_free_ac97(struct snd_ac97 *ac97)
[32]	1638	{
[305]	1639	struct intel8x0 *chip = ac97->private_data;
	1640	chip->ac97[ac97->num] = NULL;
[32]	1641	}
	1642
[679]	1643	static const struct ac97_pcm ac97_pcm_defs[] = {
[305]	1644	/* front PCM */
	1645	{
	1646	.exclusive = 1,
[679]	1647	.r = { {
[305]	1648	.slots = (1 << AC97_SLOT_PCM_LEFT) \|
	1649	(1 << AC97_SLOT_PCM_RIGHT) \|
	1650	(1 << AC97_SLOT_PCM_CENTER) \|
	1651	(1 << AC97_SLOT_PCM_SLEFT) \|
	1652	(1 << AC97_SLOT_PCM_SRIGHT) \|
	1653	(1 << AC97_SLOT_LFE)
	1654	},
	1655	{
	1656	.slots = (1 << AC97_SLOT_PCM_LEFT) \|
	1657	(1 << AC97_SLOT_PCM_RIGHT) \|
	1658	(1 << AC97_SLOT_PCM_LEFT_0) \|
	1659	(1 << AC97_SLOT_PCM_RIGHT_0)
	1660	}
	1661	}
	1662	},
	1663	/* PCM IN #1 */
	1664	{
	1665	.stream = 1,
	1666	.exclusive = 1,
	1667	.r = { {
	1668	.slots = (1 << AC97_SLOT_PCM_LEFT) \|
	1669	(1 << AC97_SLOT_PCM_RIGHT)
	1670	}
	1671	}
	1672	},
	1673	/* MIC IN #1 */
	1674	{
	1675	.stream = 1,
	1676	.exclusive = 1,
	1677	.r = { {
	1678	.slots = (1 << AC97_SLOT_MIC)
	1679	}
	1680	}
	1681	},
	1682	/* S/PDIF PCM */
	1683	{
	1684	.exclusive = 1,
	1685	.spdif = 1,
	1686	.r = { {
	1687	.slots = (1 << AC97_SLOT_SPDIF_LEFT2) \|
	1688	(1 << AC97_SLOT_SPDIF_RIGHT2)
	1689	}
	1690	}
	1691	},
	1692	/* PCM IN #2 */
	1693	{
	1694	.stream = 1,
	1695	.exclusive = 1,
	1696	.r = { {
	1697	.slots = (1 << AC97_SLOT_PCM_LEFT) \|
	1698	(1 << AC97_SLOT_PCM_RIGHT)
	1699	}
	1700	}
	1701	},
	1702	/* MIC IN #2 */
	1703	{
	1704	.stream = 1,
	1705	.exclusive = 1,
	1706	.r = { {
	1707	.slots = (1 << AC97_SLOT_MIC)
	1708	}
	1709	}
	1710	},
[32]	1711	};
	1712
[679]	1713	static const struct ac97_quirk ac97_quirks[] = {
	1714	{
[358]	1715	.subvendor = 0x0e11,
	1716	.subdevice = 0x000e,
	1717	.name = "Compaq Deskpro EN", /* AD1885 */
	1718	.type = AC97_TUNE_HP_ONLY
[679]	1719	},
[32]	1720	{
	1721	.subvendor = 0x0e11,
	1722	.subdevice = 0x008a,
	1723	.name = "Compaq Evo W4000", /* AD1885 */
	1724	.type = AC97_TUNE_HP_ONLY
	1725	},
	1726	{
	1727	.subvendor = 0x0e11,
	1728	.subdevice = 0x00b8,
	1729	.name = "Compaq Evo D510C",
	1730	.type = AC97_TUNE_HP_ONLY
	1731	},
[679]	1732	{
[32]	1733	.subvendor = 0x0e11,
	1734	.subdevice = 0x0860,
	1735	.name = "HP/Compaq nx7010",
	1736	.type = AC97_TUNE_MUTE_LED
[679]	1737	},
[32]	1738	{
	1739	.subvendor = 0x1014,
[598]	1740	.subdevice = 0x0534,
	1741	.name = "ThinkPad X31",
	1742	.type = AC97_TUNE_INV_EAPD
	1743	},
	1744	{
	1745	.subvendor = 0x1014,
[32]	1746	.subdevice = 0x1f00,
	1747	.name = "MS-9128",
	1748	.type = AC97_TUNE_ALC_JACK
	1749	},
[305]	1750	{
	1751	.subvendor = 0x1014,
	1752	.subdevice = 0x0267,
	1753	.name = "IBM NetVista A30p", /* AD1981B */
	1754	.type = AC97_TUNE_HP_ONLY
	1755	},
	1756	{
	1757	.subvendor = 0x1025,
	1758	.subdevice = 0x0082,
	1759	.name = "Acer Travelmate 2310",
	1760	.type = AC97_TUNE_HP_ONLY
	1761	},
	1762	{
	1763	.subvendor = 0x1025,
	1764	.subdevice = 0x0083,
	1765	.name = "Acer Aspire 3003LCi",
	1766	.type = AC97_TUNE_HP_ONLY
	1767	},
	1768	{
[32]	1769	.subvendor = 0x1028,
	1770	.subdevice = 0x00d8,
	1771	.name = "Dell Precision 530", /* AD1885 */
	1772	.type = AC97_TUNE_HP_ONLY
	1773	},
	1774	{
	1775	.subvendor = 0x1028,
	1776	.subdevice = 0x010d,
	1777	.name = "Dell", /* which model? AD1885 */
	1778	.type = AC97_TUNE_HP_ONLY
	1779	},
	1780	{
	1781	.subvendor = 0x1028,
	1782	.subdevice = 0x0126,
	1783	.name = "Dell Optiplex GX260", /* AD1981A */
	1784	.type = AC97_TUNE_HP_ONLY
	1785	},
	1786	{
	1787	.subvendor = 0x1028,
	1788	.subdevice = 0x012c,
	1789	.name = "Dell Precision 650", /* AD1981A */
	1790	.type = AC97_TUNE_HP_ONLY
	1791	},
	1792	{
	1793	.subvendor = 0x1028,
	1794	.subdevice = 0x012d,
	1795	.name = "Dell Precision 450", /* AD1981B*/
	1796	.type = AC97_TUNE_HP_ONLY
	1797	},
	1798	{
	1799	.subvendor = 0x1028,
	1800	.subdevice = 0x0147,
	1801	.name = "Dell", /* which model? AD1981B*/
	1802	.type = AC97_TUNE_HP_ONLY
	1803	},
	1804	{
[305]	1805	.subvendor = 0x1028,
[598]	1806	.subdevice = 0x0151,
	1807	.name = "Dell Optiplex GX270", /* AD1981B */
[305]	1808	.type = AC97_TUNE_HP_ONLY
[77]	1809	},
	1810	{
	1811	.subvendor = 0x1028,
[598]	1812	.subdevice = 0x014e,
	1813	.name = "Dell D800", /* STAC9750/51 */
[305]	1814	.type = AC97_TUNE_HP_ONLY
	1815	},
	1816	{
	1817	.subvendor = 0x1028,
[32]	1818	.subdevice = 0x0163,
	1819	.name = "Dell Unknown", /* STAC9750/51 */
	1820	.type = AC97_TUNE_HP_ONLY
[305]	1821	},
[32]	1822	{
[305]	1823	.subvendor = 0x1028,
[426]	1824	.subdevice = 0x016a,
	1825	.name = "Dell Inspiron 8600", /* STAC9750/51 */
	1826	.type = AC97_TUNE_HP_ONLY
	1827	},
	1828	{
	1829	.subvendor = 0x1028,
[598]	1830	.subdevice = 0x0182,
	1831	.name = "Dell Latitude D610", /* STAC9750/51 */
	1832	.type = AC97_TUNE_HP_ONLY
	1833	},
	1834	{
	1835	.subvendor = 0x1028,
[305]	1836	.subdevice = 0x0186,
	1837	.name = "Dell Latitude D810", /* cf. Malone #41015 */
	1838	.type = AC97_TUNE_HP_MUTE_LED
	1839	},
	1840	{
	1841	.subvendor = 0x1028,
	1842	.subdevice = 0x0188,
	1843	.name = "Dell Inspiron 6000",
	1844	.type = AC97_TUNE_HP_MUTE_LED /* cf. Malone #41015 */
	1845	},
	1846	{
	1847	.subvendor = 0x1028,
[679]	1848	.subdevice = 0x0189,
	1849	.name = "Dell Inspiron 9300",
	1850	.type = AC97_TUNE_HP_MUTE_LED
	1851	},
	1852	{
	1853	.subvendor = 0x1028,
[305]	1854	.subdevice = 0x0191,
	1855	.name = "Dell Inspiron 8600",
	1856	.type = AC97_TUNE_HP_ONLY
	1857	},
	1858	{
[32]	1859	.subvendor = 0x103c,
	1860	.subdevice = 0x006d,
	1861	.name = "HP zv5000",
	1862	.type = AC97_TUNE_MUTE_LED /AD1981B/
	1863	},
	1864	{ /* FIXME: which codec? */
	1865	.subvendor = 0x103c,
	1866	.subdevice = 0x00c3,
	1867	.name = "HP xw6000",
	1868	.type = AC97_TUNE_HP_ONLY
	1869	},
	1870	{
	1871	.subvendor = 0x103c,
	1872	.subdevice = 0x088c,
	1873	.name = "HP nc8000",
[305]	1874	.type = AC97_TUNE_HP_MUTE_LED
[32]	1875	},
	1876	{
	1877	.subvendor = 0x103c,
	1878	.subdevice = 0x0890,
	1879	.name = "HP nc6000",
	1880	.type = AC97_TUNE_MUTE_LED
	1881	},
	1882	{
[305]	1883	.subvendor = 0x103c,
[598]	1884	.subdevice = 0x129d,
	1885	.name = "HP xw8000",
	1886	.type = AC97_TUNE_HP_ONLY
[32]	1887	},
	1888	{
[305]	1889	.subvendor = 0x103c,
	1890	.subdevice = 0x0938,
	1891	.name = "HP nc4200",
	1892	.type = AC97_TUNE_HP_MUTE_LED
	1893	},
	1894	{
	1895	.subvendor = 0x103c,
[598]	1896	.subdevice = 0x099c,
	1897	.name = "HP nx6110/nc6120",
[305]	1898	.type = AC97_TUNE_HP_MUTE_LED
	1899	},
	1900	{
	1901	.subvendor = 0x103c,
[598]	1902	.subdevice = 0x0944,
	1903	.name = "HP nc6220",
[305]	1904	.type = AC97_TUNE_HP_MUTE_LED
	1905	},
	1906	{
	1907	.subvendor = 0x103c,
[598]	1908	.subdevice = 0x0934,
	1909	.name = "HP nc8220",
	1910	.type = AC97_TUNE_HP_MUTE_LED
[305]	1911	},
	1912	{
	1913	.subvendor = 0x103c,
[32]	1914	.subdevice = 0x12f1,
	1915	.name = "HP xw8200", /* AD1981B*/
	1916	.type = AC97_TUNE_HP_ONLY
	1917	},
	1918	{
	1919	.subvendor = 0x103c,
	1920	.subdevice = 0x12f2,
	1921	.name = "HP xw6200",
	1922	.type = AC97_TUNE_HP_ONLY
	1923	},
	1924	{
	1925	.subvendor = 0x103c,
	1926	.subdevice = 0x3008,
	1927	.name = "HP xw4200", /* AD1981B*/
	1928	.type = AC97_TUNE_HP_ONLY
	1929	},
	1930	{
	1931	.subvendor = 0x104d,
[598]	1932	.subdevice = 0x8144,
	1933	.name = "Sony",
	1934	.type = AC97_TUNE_INV_EAPD
	1935	},
	1936	{
	1937	.subvendor = 0x104d,
[32]	1938	.subdevice = 0x8197,
	1939	.name = "Sony S1XP",
	1940	.type = AC97_TUNE_INV_EAPD
	1941	},
[598]	1942	{
	1943	.subvendor = 0x104d,
	1944	.subdevice = 0x81c0,
	1945	.name = "Sony VAIO VGN-T350P", /AD1981B/
	1946	.type = AC97_TUNE_INV_EAPD
	1947	},
	1948	{
	1949	.subvendor = 0x104d,
	1950	.subdevice = 0x81c5,
	1951	.name = "Sony VAIO VGN-B1VP", /AD1981B/
	1952	.type = AC97_TUNE_INV_EAPD
	1953	},
[32]	1954	{
	1955	.subvendor = 0x1043,
	1956	.subdevice = 0x80f3,
	1957	.name = "ASUS ICH5/AD1985",
	1958	.type = AC97_TUNE_AD_SHARING
	1959	},
	1960	{
	1961	.subvendor = 0x10cf,
	1962	.subdevice = 0x11c3,
	1963	.name = "Fujitsu-Siemens E4010",
	1964	.type = AC97_TUNE_HP_ONLY
	1965	},
	1966	{
	1967	.subvendor = 0x10cf,
	1968	.subdevice = 0x1225,
	1969	.name = "Fujitsu-Siemens T3010",
	1970	.type = AC97_TUNE_HP_ONLY
	1971	},
	1972	{
	1973	.subvendor = 0x10cf,
	1974	.subdevice = 0x1253,
	1975	.name = "Fujitsu S6210", /* STAC9750/51 */
	1976	.type = AC97_TUNE_HP_ONLY
	1977	},
[305]	1978	{
	1979	.subvendor = 0x10cf,
[399]	1980	.subdevice = 0x127d,
	1981	.name = "Fujitsu Lifebook P7010",
	1982	.type = AC97_TUNE_HP_ONLY
	1983	},
	1984	{
	1985	.subvendor = 0x10cf,
[305]	1986	.subdevice = 0x127e,
	1987	.name = "Fujitsu Lifebook C1211D",
	1988	.type = AC97_TUNE_HP_ONLY
	1989	},
	1990	{
	1991	.subvendor = 0x10cf,
	1992	.subdevice = 0x12ec,
	1993	.name = "Fujitsu-Siemens 4010",
	1994	.type = AC97_TUNE_HP_ONLY
	1995	},
	1996	{
	1997	.subvendor = 0x10cf,
	1998	.subdevice = 0x12f2,
	1999	.name = "Fujitsu-Siemens Celsius H320",
	2000	.type = AC97_TUNE_SWAP_HP
	2001	},
	2002	{
[32]	2003	.subvendor = 0x10f1,
	2004	.subdevice = 0x2665,
	2005	.name = "Fujitsu-Siemens Celsius", /* AD1981? */
	2006	.type = AC97_TUNE_HP_ONLY
	2007	},
	2008	{
	2009	.subvendor = 0x10f1,
	2010	.subdevice = 0x2885,
	2011	.name = "AMD64 Mobo", /* ALC650 */
	2012	.type = AC97_TUNE_HP_ONLY
	2013	},
[305]	2014	{
	2015	.subvendor = 0x10f1,
	2016	.subdevice = 0x2895,
	2017	.name = "Tyan Thunder K8WE",
	2018	.type = AC97_TUNE_HP_ONLY
[77]	2019	},
[32]	2020	{
[305]	2021	.subvendor = 0x10f7,
	2022	.subdevice = 0x834c,
	2023	.name = "Panasonic CF-R4",
	2024	.type = AC97_TUNE_HP_ONLY,
	2025	},
	2026	{
[32]	2027	.subvendor = 0x110a,
	2028	.subdevice = 0x0056,
	2029	.name = "Fujitsu-Siemens Scenic", /* AD1981? */
	2030	.type = AC97_TUNE_HP_ONLY
	2031	},
	2032	{
	2033	.subvendor = 0x11d4,
	2034	.subdevice = 0x5375,
	2035	.name = "ADI AD1985 (discrete)",
	2036	.type = AC97_TUNE_HP_ONLY
	2037	},
	2038	{
	2039	.subvendor = 0x1462,
	2040	.subdevice = 0x5470,
	2041	.name = "MSI P4 ATX 645 Ultra",
	2042	.type = AC97_TUNE_HP_ONLY
	2043	},
	2044	{
[598]	2045	.subvendor = 0x161f,
[679]	2046	.subdevice = 0x202f,
	2047	.name = "Gateway M520",
	2048	.type = AC97_TUNE_INV_EAPD
	2049	},
	2050	{
	2051	.subvendor = 0x161f,
[598]	2052	.subdevice = 0x203a,
	2053	.name = "Gateway 4525GZ", /* AD1981B */
	2054	.type = AC97_TUNE_INV_EAPD
	2055	},
	2056	{
[32]	2057	.subvendor = 0x1734,
	2058	.subdevice = 0x0088,
	2059	.name = "Fujitsu-Siemens D1522", /* AD1981 */
	2060	.type = AC97_TUNE_HP_ONLY
[305]	2061	},
[32]	2062	{
	2063	.subvendor = 0x8086,
	2064	.subdevice = 0x2000,
	2065	.mask = 0xfff0,
	2066	.name = "Intel ICH5/AD1985",
	2067	.type = AC97_TUNE_AD_SHARING
	2068	},
	2069	{
	2070	.subvendor = 0x8086,
	2071	.subdevice = 0x4000,
	2072	.mask = 0xfff0,
	2073	.name = "Intel ICH5/AD1985",
	2074	.type = AC97_TUNE_AD_SHARING
	2075	},
	2076	{
	2077	.subvendor = 0x8086,
	2078	.subdevice = 0x4856,
	2079	.name = "Intel D845WN (82801BA)",
	2080	.type = AC97_TUNE_SWAP_HP
	2081	},
	2082	{
	2083	.subvendor = 0x8086,
	2084	.subdevice = 0x4d44,
	2085	.name = "Intel D850EMV2", /* AD1885 */
	2086	.type = AC97_TUNE_HP_ONLY
	2087	},
	2088	{
	2089	.subvendor = 0x8086,
	2090	.subdevice = 0x4d56,
	2091	.name = "Intel ICH/AD1885",
	2092	.type = AC97_TUNE_HP_ONLY
	2093	},
	2094	{
	2095	.subvendor = 0x8086,
	2096	.subdevice = 0x6000,
	2097	.mask = 0xfff0,
	2098	.name = "Intel ICH5/AD1985",
	2099	.type = AC97_TUNE_AD_SHARING
	2100	},
	2101	{
	2102	.subvendor = 0x8086,
	2103	.subdevice = 0xe000,
	2104	.mask = 0xfff0,
	2105	.name = "Intel ICH5/AD1985",
	2106	.type = AC97_TUNE_AD_SHARING
	2107	},
	2108	#if 0 /* FIXME: this seems wrong on most boards */
	2109	{
	2110	.subvendor = 0x8086,
	2111	.subdevice = 0xa000,
	2112	.mask = 0xfff0,
	2113	.name = "Intel ICH5/AD1985",
	2114	.type = AC97_TUNE_HP_ONLY
	2115	},
	2116	#endif
	2117	{0} /* terminator */
	2118	};
	2119
[679]	2120	static int snd_intel8x0_mixer(struct intel8x0 *chip, int ac97_clock,
	2121	const char *quirk_override)
[32]	2122	{
[305]	2123	struct snd_ac97_bus *pbus;
	2124	struct snd_ac97_template ac97;
	2125	int err;
	2126	unsigned int i, codecs;
	2127	unsigned int glob_sta = 0;
[679]	2128	const struct snd_ac97_bus_ops *ops;
	2129	static const struct snd_ac97_bus_ops standard_bus_ops = {
[305]	2130	.write = snd_intel8x0_codec_write,
	2131	.read = snd_intel8x0_codec_read,
	2132	};
[679]	2133	static const struct snd_ac97_bus_ops ali_bus_ops = {
[305]	2134	.write = snd_intel8x0_ali_codec_write,
	2135	.read = snd_intel8x0_ali_codec_read,
	2136	};
[88]	2137
[305]	2138	chip->spdif_idx = -1; /* use PCMOUT (or disabled) */
	2139	if (!spdif_aclink) {
	2140	switch (chip->device_type) {
	2141	case DEVICE_NFORCE:
	2142	chip->spdif_idx = NVD_SPBAR;
	2143	break;
	2144	case DEVICE_ALI:
	2145	chip->spdif_idx = ALID_AC97SPDIFOUT;
	2146	break;
	2147	case DEVICE_INTEL_ICH4:
	2148	chip->spdif_idx = ICHD_SPBAR;
	2149	break;
[679]	2150	}
[305]	2151	}
[32]	2152
[305]	2153	chip->in_ac97_init = 1;
	2154
	2155	memset(&ac97, 0, sizeof(ac97));
	2156	ac97.private_data = chip;
	2157	ac97.private_free = snd_intel8x0_mixer_free_ac97;
	2158	ac97.scaps = AC97_SCAP_SKIP_MODEM \| AC97_SCAP_POWER_SAVE;
	2159	if (chip->xbox)
	2160	ac97.scaps \|= AC97_SCAP_DETECT_BY_VENDOR;
	2161	if (chip->device_type != DEVICE_ALI) {
	2162	glob_sta = igetdword(chip, ICHREG(GLOB_STA));
	2163	ops = &standard_bus_ops;
	2164	chip->in_sdin_init = 1;
	2165	codecs = 0;
	2166	for (i = 0; i < chip->max_codecs; i++) {
	2167	if (! (glob_sta & chip->codec_bit[i]))
	2168	continue;
	2169	if (chip->device_type == DEVICE_INTEL_ICH4) {
	2170	snd_intel8x0_codec_read_test(chip, codecs);
	2171	chip->ac97_sdin[codecs] =
	2172	igetbyte(chip, ICHREG(SDM)) & ICH_LDI_MASK;
[399]	2173	if (snd_BUG_ON(chip->ac97_sdin[codecs] >= 3))
	2174	chip->ac97_sdin[codecs] = 0;
[305]	2175	} else
	2176	chip->ac97_sdin[codecs] = i;
	2177	codecs++;
	2178	}
	2179	chip->in_sdin_init = 0;
	2180	if (! codecs)
	2181	codecs = 1;
	2182	} else {
	2183	ops = &ali_bus_ops;
	2184	codecs = 1;
	2185	/* detect the secondary codec */
	2186	for (i = 0; i < 100; i++) {
	2187	unsigned int reg = igetdword(chip, ICHREG(ALI_RTSR));
	2188	if (reg & 0x40) {
	2189	codecs = 2;
	2190	break;
	2191	}
	2192	iputdword(chip, ICHREG(ALI_RTSR), reg \| 0x40);
	2193	udelay(1);
	2194	}
	2195	}
[703]	2196	err = snd_ac97_bus(chip->card, 0, ops, chip, &pbus);
	2197	if (err < 0)
[305]	2198	goto __err;
	2199	pbus->private_free = snd_intel8x0_mixer_free_ac97_bus;
	2200	if (ac97_clock >= 8000 && ac97_clock <= 48000)
	2201	pbus->clock = ac97_clock;
	2202	/* FIXME: my test board doesn't work well with VRA... */
	2203	if (chip->device_type == DEVICE_ALI)
	2204	pbus->no_vra = 1;
	2205	else
	2206	pbus->dra = 1;
	2207	chip->ac97_bus = pbus;
	2208	chip->ncodecs = codecs;
[32]	2209
[305]	2210	ac97.pci = chip->pci;
	2211	for (i = 0; i < codecs; i++) {
	2212	ac97.num = i;
[703]	2213	err = snd_ac97_mixer(pbus, &ac97, &chip->ac97[i]);
	2214	if (err < 0) {
[305]	2215	if (err != -EACCES)
[679]	2216	dev_err(chip->card->dev,
	2217	"Unable to initialize codec #%d\n", i);
[305]	2218	if (i == 0)
	2219	goto __err;
	2220	}
	2221	}
	2222	/* tune up the primary codec */
	2223	snd_ac97_tune_hardware(chip->ac97[0], ac97_quirks, quirk_override);
	2224	/* enable separate SDINs for ICH4 */
	2225	if (chip->device_type == DEVICE_INTEL_ICH4)
	2226	pbus->isdin = 1;
	2227	/* find the available PCM streams */
	2228	i = ARRAY_SIZE(ac97_pcm_defs);
	2229	if (chip->device_type != DEVICE_INTEL_ICH4)
	2230	i -= 2; /* do not allocate PCM2IN and MIC2 */
	2231	if (chip->spdif_idx < 0)
	2232	i--; /* do not allocate S/PDIF */
	2233	err = snd_ac97_pcm_assign(pbus, i, ac97_pcm_defs);
	2234	if (err < 0)
	2235	goto __err;
	2236	chip->ichd[ICHD_PCMOUT].pcm = &pbus->pcms[0];
	2237	chip->ichd[ICHD_PCMIN].pcm = &pbus->pcms[1];
	2238	chip->ichd[ICHD_MIC].pcm = &pbus->pcms[2];
	2239	if (chip->spdif_idx >= 0)
	2240	chip->ichd[chip->spdif_idx].pcm = &pbus->pcms[3];
	2241	if (chip->device_type == DEVICE_INTEL_ICH4) {
	2242	chip->ichd[ICHD_PCM2IN].pcm = &pbus->pcms[4];
	2243	chip->ichd[ICHD_MIC2].pcm = &pbus->pcms[5];
	2244	}
	2245	/* enable separate SDINs for ICH4 */
	2246	if (chip->device_type == DEVICE_INTEL_ICH4) {
	2247	struct ac97_pcm *pcm = chip->ichd[ICHD_PCM2IN].pcm;
	2248	u8 tmp = igetbyte(chip, ICHREG(SDM));
	2249	tmp &= ~(ICH_DI2L_MASK\|ICH_DI1L_MASK);
	2250	if (pcm) {
	2251	tmp \|= ICH_SE; /* steer enable for multiple SDINs */
	2252	tmp \|= chip->ac97_sdin[0] << ICH_DI1L_SHIFT;
	2253	for (i = 1; i < 4; i++) {
	2254	if (pcm->r[0].codec[i]) {
	2255	tmp \|= chip->ac97_sdin[pcm->r[0].codec[1]->num] << ICH_DI2L_SHIFT;
	2256	break;
	2257	}
	2258	}
	2259	} else {
	2260	tmp &= ~ICH_SE; /* steer disable */
	2261	}
	2262	iputbyte(chip, ICHREG(SDM), tmp);
	2263	}
	2264	if (pbus->pcms[0].r[0].slots & (1 << AC97_SLOT_PCM_SLEFT)) {
	2265	chip->multi4 = 1;
[358]	2266	if (pbus->pcms[0].r[0].slots & (1 << AC97_SLOT_LFE)) {
[305]	2267	chip->multi6 = 1;
[358]	2268	if (chip->ac97[0]->flags & AC97_HAS_8CH)
	2269	chip->multi8 = 1;
	2270	}
[305]	2271	}
	2272	if (pbus->pcms[0].r[1].rslots[0]) {
	2273	chip->dra = 1;
	2274	}
	2275	if (chip->device_type == DEVICE_INTEL_ICH4) {
	2276	if ((igetdword(chip, ICHREG(GLOB_STA)) & ICH_SAMPLE_CAP) == ICH_SAMPLE_16_20)
	2277	chip->smp20bit = 1;
	2278	}
	2279	if (chip->device_type == DEVICE_NFORCE && !spdif_aclink) {
	2280	/* 48kHz only */
	2281	chip->ichd[chip->spdif_idx].pcm->rates = SNDRV_PCM_RATE_48000;
	2282	}
	2283	if (chip->device_type == DEVICE_INTEL_ICH4 && !spdif_aclink) {
	2284	/* use slot 10/11 for SPDIF */
	2285	u32 val;
	2286	val = igetdword(chip, ICHREG(GLOB_CNT)) & ~ICH_PCM_SPDIF_MASK;
	2287	val \|= ICH_PCM_SPDIF_1011;
	2288	iputdword(chip, ICHREG(GLOB_CNT), val);
	2289	snd_ac97_update_bits(chip->ac97[0], AC97_EXTENDED_STATUS, 0x03 << 4, 0x03 << 4);
	2290	}
	2291	chip->in_ac97_init = 0;
	2292	return 0;
[32]	2293
[305]	2294	__err:
	2295	/* clear the cold-reset bit for the next chance */
	2296	if (chip->device_type != DEVICE_ALI)
	2297	iputdword(chip, ICHREG(GLOB_CNT),
	2298	igetdword(chip, ICHREG(GLOB_CNT)) & ~ICH_AC97COLD);
	2299	return err;
[32]	2300	}
	2301
	2302
	2303	/*
	2304	*
	2305	*/
	2306
[35]	2307	static void do_ali_reset(struct intel8x0 *chip)
[32]	2308	{
[305]	2309	iputdword(chip, ICHREG(ALI_SCR), ICH_ALI_SC_RESET);
	2310	iputdword(chip, ICHREG(ALI_FIFOCR1), 0x83838383);
	2311	iputdword(chip, ICHREG(ALI_FIFOCR2), 0x83838383);
	2312	iputdword(chip, ICHREG(ALI_FIFOCR3), 0x83838383);
	2313	iputdword(chip, ICHREG(ALI_INTERFACECR),
	2314	ICH_ALI_IF_PI\|ICH_ALI_IF_PO);
	2315	iputdword(chip, ICHREG(ALI_INTERRUPTCR), 0x00000000);
	2316	iputdword(chip, ICHREG(ALI_INTERRUPTSR), 0x00000000);
[32]	2317	}
	2318
[426]	2319	#ifdef CONFIG_SND_AC97_POWER_SAVE
[679]	2320	static const struct snd_pci_quirk ich_chip_reset_mode[] = {
[426]	2321	SND_PCI_QUIRK(0x1014, 0x051f, "Thinkpad R32", 1),
[679]	2322	{0} /* end */
[426]	2323	};
	2324
	2325	static int snd_intel8x0_ich_chip_cold_reset(struct intel8x0 *chip)
[32]	2326	{
[426]	2327	unsigned int cnt;
	2328	/* ACLink on, 2 channels */
[32]	2329
[426]	2330	if (snd_pci_quirk_lookup(chip->pci, ich_chip_reset_mode))
	2331	return -EIO;
	2332
[305]	2333	cnt = igetdword(chip, ICHREG(GLOB_CNT));
	2334	cnt &= ~(ICH_ACLINK \| ICH_PCM_246_MASK);
[426]	2335
[305]	2336	/* do cold reset - the full ac97 powerdown may leave the controller
	2337	* in a warm state but actually it cannot communicate with the codec.
	2338	*/
	2339	iputdword(chip, ICHREG(GLOB_CNT), cnt & ~ICH_AC97COLD);
	2340	cnt = igetdword(chip, ICHREG(GLOB_CNT));
	2341	udelay(10);
	2342	iputdword(chip, ICHREG(GLOB_CNT), cnt \| ICH_AC97COLD);
	2343	msleep(1);
[426]	2344	return 0;
	2345	}
	2346	#define snd_intel8x0_ich_chip_can_cold_reset(chip) \
	2347	(!snd_pci_quirk_lookup(chip->pci, ich_chip_reset_mode))
[77]	2348	#else
[426]	2349	#define snd_intel8x0_ich_chip_cold_reset(chip) 0
	2350	#define snd_intel8x0_ich_chip_can_cold_reset(chip) (0)
	2351	#endif
	2352
	2353	static int snd_intel8x0_ich_chip_reset(struct intel8x0 *chip)
	2354	{
	2355	unsigned long end_time;
	2356	unsigned int cnt;
	2357	/* ACLink on, 2 channels */
	2358	cnt = igetdword(chip, ICHREG(GLOB_CNT));
	2359	cnt &= ~(ICH_ACLINK \| ICH_PCM_246_MASK);
[305]	2360	/* finish cold or do warm reset */
	2361	cnt \|= (cnt & ICH_AC97COLD) == 0 ? ICH_AC97COLD : ICH_AC97WARM;
	2362	iputdword(chip, ICHREG(GLOB_CNT), cnt);
	2363	end_time = (jiffies + (HZ / 4)) + 1;
	2364	do {
	2365	if ((igetdword(chip, ICHREG(GLOB_CNT)) & ICH_AC97WARM) == 0)
[426]	2366	return 0;
[305]	2367	schedule_timeout_uninterruptible(1);
	2368	} while (time_after_eq(end_time, jiffies));
[679]	2369	dev_err(chip->card->dev, "AC'97 warm reset still in progress? [0x%x]\n",
[305]	2370	igetdword(chip, ICHREG(GLOB_CNT)));
	2371	return -EIO;
[426]	2372	}
[32]	2373
[426]	2374	static int snd_intel8x0_ich_chip_init(struct intel8x0 *chip, int probing)
	2375	{
	2376	unsigned long end_time;
	2377	unsigned int status, nstatus;
	2378	unsigned int cnt;
	2379	int err;
	2380
	2381	/* put logic to right state */
	2382	/* first clear status bits */
	2383	status = ICH_RCS \| ICH_MCINT \| ICH_POINT \| ICH_PIINT;
	2384	if (chip->device_type == DEVICE_NFORCE)
	2385	status \|= ICH_NVSPINT;
	2386	cnt = igetdword(chip, ICHREG(GLOB_STA));
	2387	iputdword(chip, ICHREG(GLOB_STA), cnt & status);
	2388
[522]	2389	#ifdef CONFIG_SND_AC97_POWER_SAVE
[426]	2390	if (snd_intel8x0_ich_chip_can_cold_reset(chip))
	2391	err = snd_intel8x0_ich_chip_cold_reset(chip);
	2392	else
[522]	2393	#endif
[426]	2394	err = snd_intel8x0_ich_chip_reset(chip);
	2395	if (err < 0)
	2396	return err;
	2397
[305]	2398	if (probing) {
	2399	/* wait for any codec ready status.
	2400	* Once it becomes ready it should remain ready
	2401	* as long as we do not disable the ac97 link.
	2402	*/
	2403	end_time = jiffies + HZ;
	2404	do {
	2405	status = igetdword(chip, ICHREG(GLOB_STA)) &
	2406	chip->codec_isr_bits;
	2407	if (status)
	2408	break;
	2409	schedule_timeout_uninterruptible(1);
	2410	} while (time_after_eq(end_time, jiffies));
	2411	if (! status) {
	2412	/* no codec is found */
[679]	2413	dev_err(chip->card->dev,
	2414	"codec_ready: codec is not ready [0x%x]\n",
[305]	2415	igetdword(chip, ICHREG(GLOB_STA)));
	2416	return -EIO;
	2417	}
[32]	2418
[305]	2419	/* wait for other codecs ready status. */
	2420	end_time = jiffies + HZ / 4;
	2421	while (status != chip->codec_isr_bits &&
	2422	time_after_eq(end_time, jiffies)) {
	2423	schedule_timeout_uninterruptible(1);
	2424	status \|= igetdword(chip, ICHREG(GLOB_STA)) &
	2425	chip->codec_isr_bits;
	2426	}
[32]	2427
[305]	2428	} else {
	2429	/* resume phase */
	2430	int i;
	2431	status = 0;
	2432	for (i = 0; i < chip->ncodecs; i++)
	2433	if (chip->ac97[i])
	2434	status \|= chip->codec_bit[chip->ac97_sdin[i]];
	2435	/* wait until all the probed codecs are ready */
	2436	end_time = jiffies + HZ;
	2437	do {
	2438	nstatus = igetdword(chip, ICHREG(GLOB_STA)) &
	2439	chip->codec_isr_bits;
	2440	if (status == nstatus)
	2441	break;
	2442	schedule_timeout_uninterruptible(1);
	2443	} while (time_after_eq(end_time, jiffies));
	2444	}
[32]	2445
[305]	2446	if (chip->device_type == DEVICE_SIS) {
	2447	/* unmute the output on SIS7012 */
	2448	iputword(chip, 0x4c, igetword(chip, 0x4c) \| 1);
	2449	}
	2450	if (chip->device_type == DEVICE_NFORCE && !spdif_aclink) {
	2451	/* enable SPDIF interrupt */
	2452	unsigned int val;
	2453	pci_read_config_dword(chip->pci, 0x4c, &val);
	2454	val \|= 0x1000000;
	2455	pci_write_config_dword(chip->pci, 0x4c, val);
	2456	}
	2457	return 0;
[32]	2458	}
	2459
[35]	2460	static int snd_intel8x0_ali_chip_init(struct intel8x0 *chip, int probing)
[32]	2461	{
[305]	2462	u32 reg;
	2463	int i = 0;
[32]	2464
[305]	2465	reg = igetdword(chip, ICHREG(ALI_SCR));
	2466	if ((reg & 2) == 0) /* Cold required */
	2467	reg \|= 2;
	2468	else
	2469	reg \|= 1; /* Warm */
	2470	reg &= ~0x80000000; /* ACLink on */
	2471	iputdword(chip, ICHREG(ALI_SCR), reg);
[32]	2472
[305]	2473	for (i = 0; i < HZ / 2; i++) {
	2474	if (! (igetdword(chip, ICHREG(ALI_INTERRUPTSR)) & ALI_INT_GPIO))
	2475	goto __ok;
	2476	schedule_timeout_uninterruptible(1);
	2477	}
[679]	2478	dev_err(chip->card->dev, "AC'97 reset failed.\n");
[305]	2479	if (probing)
	2480	return -EIO;
[32]	2481
[305]	2482	__ok:
	2483	for (i = 0; i < HZ / 2; i++) {
	2484	reg = igetdword(chip, ICHREG(ALI_RTSR));
	2485	if (reg & 0x80) /* primary codec */
	2486	break;
	2487	iputdword(chip, ICHREG(ALI_RTSR), reg \| 0x80);
	2488	schedule_timeout_uninterruptible(1);
	2489	}
[32]	2490
[305]	2491	do_ali_reset(chip);
	2492	return 0;
[32]	2493	}
	2494
[35]	2495	static int snd_intel8x0_chip_init(struct intel8x0 *chip, int probing)
[32]	2496	{
[305]	2497	unsigned int i, timeout;
	2498	int err;
	2499
	2500	if (chip->device_type != DEVICE_ALI) {
[703]	2501	err = snd_intel8x0_ich_chip_init(chip, probing);
	2502	if (err < 0)
[305]	2503	return err;
	2504	iagetword(chip, 0); /* clear semaphore flag */
	2505	} else {
[703]	2506	err = snd_intel8x0_ali_chip_init(chip, probing);
	2507	if (err < 0)
[305]	2508	return err;
	2509	}
[32]	2510
[305]	2511	/* disable interrupts */
	2512	for (i = 0; i < chip->bdbars_count; i++)
	2513	iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, 0x00);
	2514	/* reset channels */
	2515	for (i = 0; i < chip->bdbars_count; i++)
	2516	iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, ICH_RESETREGS);
	2517	for (i = 0; i < chip->bdbars_count; i++) {
	2518	timeout = 100000;
	2519	while (--timeout != 0) {
	2520	if ((igetbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset) & ICH_RESETREGS) == 0)
	2521	break;
	2522	}
	2523	if (timeout == 0)
[679]	2524	dev_err(chip->card->dev, "reset of registers failed?\n");
[76]	2525	}
[305]	2526	/* initialize Buffer Descriptor Lists */
	2527	for (i = 0; i < chip->bdbars_count; i++)
	2528	iputdword(chip, ICH_REG_OFF_BDBAR + chip->ichd[i].reg_offset,
	2529	chip->ichd[i].bdbar_addr);
	2530	return 0;
[32]	2531	}
	2532
[717]	2533	static void snd_intel8x0_free(struct snd_card *card)
[32]	2534	{
[717]	2535	struct intel8x0 *chip = card->private_data;
[305]	2536	unsigned int i;
[32]	2537
[305]	2538	if (chip->irq < 0)
	2539	goto __hw_end;
	2540	/* disable interrupts */
	2541	for (i = 0; i < chip->bdbars_count; i++)
	2542	iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, 0x00);
	2543	/* reset channels */
	2544	for (i = 0; i < chip->bdbars_count; i++)
	2545	iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, ICH_RESETREGS);
	2546	if (chip->device_type == DEVICE_NFORCE && !spdif_aclink) {
	2547	/* stop the spdif interrupt */
	2548	unsigned int val;
	2549	pci_read_config_dword(chip->pci, 0x4c, &val);
	2550	val &= ~0x1000000;
	2551	pci_write_config_dword(chip->pci, 0x4c, val);
	2552	}
	2553	/* --- */
[358]	2554
[305]	2555	__hw_end:
	2556	if (chip->irq >= 0)
	2557	free_irq(chip->irq, chip);
[32]	2558	}
	2559
	2560	/*
	2561	* power management
	2562	*/
[679]	2563	static int intel8x0_suspend(struct device *dev)
[32]	2564	{
[679]	2565	struct snd_card *card = dev_get_drvdata(dev);
[305]	2566	struct intel8x0 *chip = card->private_data;
	2567	int i;
[32]	2568
[305]	2569	snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
	2570	for (i = 0; i < chip->ncodecs; i++)
	2571	snd_ac97_suspend(chip->ac97[i]);
	2572	if (chip->device_type == DEVICE_INTEL_ICH4)
	2573	chip->sdm_saved = igetbyte(chip, ICHREG(SDM));
[35]	2574
[305]	2575	if (chip->irq >= 0) {
	2576	free_irq(chip->irq, chip);
	2577	chip->irq = -1;
[679]	2578	card->sync_irq = -1;
[305]	2579	}
	2580	return 0;
[32]	2581	}
	2582
[679]	2583	static int intel8x0_resume(struct device *dev)
[32]	2584	{
[679]	2585	struct pci_dev *pci = to_pci_dev(dev);
	2586	struct snd_card *card = dev_get_drvdata(dev);
[305]	2587	struct intel8x0 *chip = card->private_data;
	2588	int i;
[32]	2589
[305]	2590	snd_intel8x0_chip_init(chip, 0);
	2591	if (request_irq(pci->irq, snd_intel8x0_interrupt,
[679]	2592	IRQF_SHARED, KBUILD_MODNAME, chip)) {
	2593	dev_err(dev, "unable to grab IRQ %d, disabling device\n",
	2594	pci->irq);
[305]	2595	snd_card_disconnect(card);
	2596	return -EIO;
	2597	}
	2598	chip->irq = pci->irq;
[679]	2599	card->sync_irq = chip->irq;
[32]	2600
[305]	2601	/* re-initialize mixer stuff */
	2602	if (chip->device_type == DEVICE_INTEL_ICH4 && !spdif_aclink) {
	2603	/* enable separate SDINs for ICH4 */
	2604	iputbyte(chip, ICHREG(SDM), chip->sdm_saved);
	2605	/* use slot 10/11 for SPDIF */
	2606	iputdword(chip, ICHREG(GLOB_CNT),
	2607	(igetdword(chip, ICHREG(GLOB_CNT)) & ~ICH_PCM_SPDIF_MASK) \|
	2608	ICH_PCM_SPDIF_1011);
	2609	}
	2610
	2611	for (i = 0; i < chip->ncodecs; i++)
	2612	snd_ac97_resume(chip->ac97[i]);
	2613
	2614	/* resume status */
	2615	for (i = 0; i < chip->bdbars_count; i++) {
	2616	struct ichdev *ichdev = &chip->ichd[i];
	2617	unsigned long port = ichdev->reg_offset;
	2618	if (! ichdev->substream \|\| ! ichdev->suspended)
	2619	continue;
	2620	if (ichdev->ichd == ICHD_PCMOUT)
	2621	snd_intel8x0_setup_pcm_out(chip, ichdev->substream->runtime);
	2622	iputdword(chip, port + ICH_REG_OFF_BDBAR, ichdev->bdbar_addr);
	2623	iputbyte(chip, port + ICH_REG_OFF_LVI, ichdev->lvi);
	2624	iputbyte(chip, port + ICH_REG_OFF_CIV, ichdev->civ);
	2625	iputbyte(chip, port + ichdev->roff_sr, ICH_FIFOE \| ICH_BCIS \| ICH_LVBCI);
	2626	}
	2627
	2628	snd_power_change_state(card, SNDRV_CTL_POWER_D0);
	2629	return 0;
[32]	2630	}
	2631
[777]	2632	static DEFINE_SIMPLE_DEV_PM_OPS(intel8x0_pm, intel8x0_suspend, intel8x0_resume);
[679]	2633
[32]	2634	#define INTEL8X0_TESTBUF_SIZE 32768 /* enough large for one shot */
	2635
[679]	2636	static void intel8x0_measure_ac97_clock(struct intel8x0 *chip)
[32]	2637	{
[305]	2638	struct snd_pcm_substream *subs;
	2639	struct ichdev *ichdev;
	2640	unsigned long port;
[426]	2641	unsigned long pos, pos1, t;
	2642	int civ, timeout = 1000, attempt = 1;
[679]	2643	#ifndef TARGET_OS2
	2644	ktime_t start_time, stop_time;
	2645	#else
[426]	2646	struct timespec start_time, stop_time;
[679]	2647	#endif
[32]	2648
[305]	2649	if (chip->ac97_bus->clock != 48000)
	2650	return; /* specified in module option */
[717]	2651	if (chip->inside_vm && !ac97_clock)
	2652	return; /* no measurement on VM */
[32]	2653
[426]	2654	__again:
[305]	2655	subs = chip->pcm[0]->streams[0].substream;
	2656	if (! subs \|\| subs->dma_buffer.bytes < INTEL8X0_TESTBUF_SIZE) {
[679]	2657	dev_warn(chip->card->dev,
	2658	"no playback buffer allocated - aborting measure ac97 clock\n");
[305]	2659	return;
	2660	}
	2661	ichdev = &chip->ichd[ICHD_PCMOUT];
	2662	ichdev->physbuf = subs->dma_buffer.addr;
[426]	2663	ichdev->size = ichdev->fragsize = INTEL8X0_TESTBUF_SIZE;
[305]	2664	ichdev->substream = NULL; /* don't process interrupts */
[32]	2665
[305]	2666	/* set rate */
	2667	if (snd_ac97_set_rate(chip->ac97[0], AC97_PCM_FRONT_DAC_RATE, 48000) < 0) {
[679]	2668	dev_err(chip->card->dev, "cannot set ac97 rate: clock = %d\n",
	2669	chip->ac97_bus->clock);
[305]	2670	return;
	2671	}
	2672	snd_intel8x0_setup_periods(chip, ichdev);
	2673	port = ichdev->reg_offset;
	2674	spin_lock_irq(&chip->reg_lock);
	2675	chip->in_measurement = 1;
	2676	/* trigger */
	2677	if (chip->device_type != DEVICE_ALI)
	2678	iputbyte(chip, port + ICH_REG_OFF_CR, ICH_IOCE \| ICH_STARTBM);
	2679	else {
	2680	iputbyte(chip, port + ICH_REG_OFF_CR, ICH_IOCE);
	2681	iputdword(chip, ICHREG(ALI_DMACR), 1 << ichdev->ali_slot);
	2682	}
[679]	2683	#ifndef TARGET_OS2
	2684	start_time = ktime_get();
	2685	#else
[426]	2686	do_posix_clock_monotonic_gettime(&start_time);
[679]	2687	#endif
[305]	2688	spin_unlock_irq(&chip->reg_lock);
	2689	msleep(50);
	2690	spin_lock_irq(&chip->reg_lock);
	2691	/* check the position */
[426]	2692	do {
	2693	civ = igetbyte(chip, ichdev->reg_offset + ICH_REG_OFF_CIV);
	2694	pos1 = igetword(chip, ichdev->reg_offset + ichdev->roff_picb);
	2695	if (pos1 == 0) {
	2696	udelay(10);
	2697	continue;
	2698	}
	2699	if (civ == igetbyte(chip, ichdev->reg_offset + ICH_REG_OFF_CIV) &&
	2700	pos1 == igetword(chip, ichdev->reg_offset + ichdev->roff_picb))
	2701	break;
	2702	} while (timeout--);
	2703	if (pos1 == 0) { /* oops, this value is not reliable */
	2704	pos = 0;
	2705	} else {
	2706	pos = ichdev->fragsize1;
	2707	pos -= pos1 << ichdev->pos_shift;
	2708	pos += ichdev->position;
	2709	}
[305]	2710	chip->in_measurement = 0;
[679]	2711	#ifndef TARGET_OS2
	2712	stop_time = ktime_get();
	2713	#else
[426]	2714	do_posix_clock_monotonic_gettime(&stop_time);
[679]	2715	#endif
[305]	2716	/* stop */
	2717	if (chip->device_type == DEVICE_ALI) {
	2718	iputdword(chip, ICHREG(ALI_DMACR), 1 << (ichdev->ali_slot + 16));
	2719	iputbyte(chip, port + ICH_REG_OFF_CR, 0);
	2720	while (igetbyte(chip, port + ICH_REG_OFF_CR))
	2721	;
	2722	} else {
	2723	iputbyte(chip, port + ICH_REG_OFF_CR, 0);
	2724	while (!(igetbyte(chip, port + ichdev->roff_sr) & ICH_DCH))
	2725	;
	2726	}
	2727	iputbyte(chip, port + ICH_REG_OFF_CR, ICH_RESETREGS);
	2728	spin_unlock_irq(&chip->reg_lock);
[32]	2729
[426]	2730	if (pos == 0) {
[679]	2731	dev_err(chip->card->dev,
	2732	"measure - unreliable DMA position..\n");
[426]	2733	__retry:
	2734	if (attempt < 3) {
	2735	msleep(300);
	2736	attempt++;
	2737	goto __again;
	2738	}
	2739	goto __end;
	2740	}
	2741
	2742	pos /= 4;
[679]	2743	#ifndef TARGET_OS2
	2744	t = ktime_us_delta(stop_time, start_time);
	2745	#else
[305]	2746	t = stop_time.tv_sec - start_time.tv_sec;
	2747	t *= 1000000;
[426]	2748	t += (stop_time.tv_nsec - start_time.tv_nsec) / 1000;
[598]	2749	dprintf(("%s: measured %lu usecs (%lu samples)\n", __func__, t, pos));
[679]	2750	#endif
	2751	dev_info(chip->card->dev,
	2752	"%s: measured %lu usecs (%lu samples)\n", __func__, t, pos);
[305]	2753	if (t == 0) {
[679]	2754	dev_err(chip->card->dev, "?? calculation error..\n");
[426]	2755	goto __retry;
[305]	2756	}
[426]	2757	pos *= 1000;
[305]	2758	pos = (pos / t) * 1000 + ((pos % t) * 1000) / t;
[426]	2759	if (pos < 40000 \|\| pos >= 60000) {
[305]	2760	/* abnormal value. hw problem? */
[679]	2761	dev_info(chip->card->dev, "measured clock %ld rejected\n", pos);
[426]	2762	goto __retry;
	2763	} else if (pos > 40500 && pos < 41500)
	2764	/* first exception - 41000Hz reference clock */
	2765	chip->ac97_bus->clock = 41000;
	2766	else if (pos > 43600 && pos < 44600)
	2767	/* second exception - 44100HZ reference clock */
	2768	chip->ac97_bus->clock = 44100;
[305]	2769	else if (pos < 47500 \|\| pos > 48500)
	2770	/* not 48000Hz, tuning the clock.. */
	2771	chip->ac97_bus->clock = (chip->ac97_bus->clock * 48000) / pos;
[426]	2772	__end:
[679]	2773	dev_info(chip->card->dev, "clocking to %d\n", chip->ac97_bus->clock);
[305]	2774	snd_ac97_update_power(chip->ac97[0], AC97_PCM_FRONT_DAC_RATE, 0);
[32]	2775	}
	2776
[679]	2777	static const struct snd_pci_quirk intel8x0_clock_list[] = {
[399]	2778	SND_PCI_QUIRK(0x0e11, 0x008a, "AD1885", 41000),
[679]	2779	SND_PCI_QUIRK(0x1014, 0x0581, "AD1981B", 48000),
[399]	2780	SND_PCI_QUIRK(0x1028, 0x00be, "AD1885", 44100),
	2781	SND_PCI_QUIRK(0x1028, 0x0177, "AD1980", 48000),
[402]	2782	SND_PCI_QUIRK(0x1028, 0x01ad, "AD1981B", 48000),
[399]	2783	SND_PCI_QUIRK(0x1043, 0x80f3, "AD1985", 48000),
	2784	{0} /* terminator */
	2785	};
	2786
[679]	2787	static int intel8x0_in_clock_list(struct intel8x0 *chip)
[399]	2788	{
	2789	struct pci_dev *pci = chip->pci;
	2790	const struct snd_pci_quirk *wl;
	2791
	2792	wl = snd_pci_quirk_lookup(pci, intel8x0_clock_list);
	2793	if (!wl)
	2794	return 0;
[679]	2795	dev_info(chip->card->dev, "allow list rate for %04x:%04x is %i\n",
[399]	2796	pci->subsystem_vendor, pci->subsystem_device, wl->value);
	2797	chip->ac97_bus->clock = wl->value;
	2798	return 1;
	2799	}
	2800
[305]	2801	static void snd_intel8x0_proc_read(struct snd_info_entry * entry,
	2802	struct snd_info_buffer *buffer)
[32]	2803	{
[305]	2804	struct intel8x0 *chip = entry->private_data;
	2805	unsigned int tmp;
[32]	2806
[305]	2807	snd_iprintf(buffer, "Intel8x0\n\n");
	2808	if (chip->device_type == DEVICE_ALI)
	2809	return;
	2810	tmp = igetdword(chip, ICHREG(GLOB_STA));
	2811	snd_iprintf(buffer, "Global control : 0x%08x\n", igetdword(chip, ICHREG(GLOB_CNT)));
	2812	snd_iprintf(buffer, "Global status : 0x%08x\n", tmp);
	2813	if (chip->device_type == DEVICE_INTEL_ICH4)
	2814	snd_iprintf(buffer, "SDM : 0x%08x\n", igetdword(chip, ICHREG(SDM)));
	2815	snd_iprintf(buffer, "AC'97 codecs ready :");
	2816	if (tmp & chip->codec_isr_bits) {
	2817	int i;
	2818	static const char *codecs[3] = {
	2819	"primary", "secondary", "tertiary"
	2820	};
	2821	for (i = 0; i < chip->max_codecs; i++)
	2822	if (tmp & chip->codec_bit[i])
	2823	snd_iprintf(buffer, " %s", codecs[i]);
	2824	} else
	2825	snd_iprintf(buffer, " none");
	2826	snd_iprintf(buffer, "\n");
	2827	if (chip->device_type == DEVICE_INTEL_ICH4 \|\|
	2828	chip->device_type == DEVICE_SIS)
	2829	snd_iprintf(buffer, "AC'97 codecs SDIN : %i %i %i\n",
	2830	chip->ac97_sdin[0],
	2831	chip->ac97_sdin[1],
	2832	chip->ac97_sdin[2]);
[32]	2833	}
	2834
[679]	2835	static void snd_intel8x0_proc_init(struct intel8x0 *chip)
[32]	2836	{
[679]	2837	snd_card_ro_proc_new(chip->card, "intel8x0", chip,
	2838	snd_intel8x0_proc_read);
[32]	2839	}
	2840
	2841	struct ich_reg_info {
[305]	2842	unsigned int int_sta_mask;
	2843	unsigned int offset;
[32]	2844	};
	2845
[679]	2846	static const unsigned int ich_codec_bits[3] = {
[305]	2847	ICH_PCR, ICH_SCR, ICH_TCR
[70]	2848	};
[679]	2849	static const unsigned int sis_codec_bits[3] = {
[305]	2850	ICH_PCR, ICH_SCR, ICH_SIS_TCR
[70]	2851	};
[32]	2852
[679]	2853	static int snd_intel8x0_inside_vm(struct pci_dev *pci)
[32]	2854	{
[679]	2855	int result = inside_vm;
	2856	char *msg = NULL;
	2857
	2858	/* check module parameter first (override detection) */
	2859	if (result >= 0) {
	2860	msg = result ? "enable (forced) VM" : "disable (forced) VM";
	2861	goto fini;
	2862	}
	2863
	2864	/* check for known (emulated) devices */
	2865	result = 0;
	2866	if (pci->subsystem_vendor == PCI_SUBVENDOR_ID_REDHAT_QUMRANET &&
	2867	pci->subsystem_device == PCI_SUBDEVICE_ID_QEMU) {
	2868	/* KVM emulated sound, PCI SSID: 1af4:1100 */
	2869	msg = "enable KVM";
	2870	result = 1;
	2871	} else if (pci->subsystem_vendor == 0x1ab8) {
	2872	/* Parallels VM emulated sound, PCI SSID: 1ab8:xxxx */
	2873	msg = "enable Parallels VM";
	2874	result = 1;
	2875	}
	2876
	2877	fini:
	2878	if (msg != NULL)
	2879	dev_info(&pci->dev, "%s optimization\n", msg);
	2880
	2881	return result;
	2882	}
	2883
[717]	2884	static int snd_intel8x0_init(struct snd_card *card,
	2885	struct pci_dev *pci,
	2886	unsigned long device_type)
[679]	2887	{
[717]	2888	struct intel8x0 *chip = card->private_data;
[305]	2889	int err;
	2890	unsigned int i;
	2891	unsigned int int_sta_masks;
	2892	struct ichdev *ichdev;
[32]	2893
[679]	2894	static const unsigned int bdbars[] = {
[305]	2895	3, /* DEVICE_INTEL */
	2896	6, /* DEVICE_INTEL_ICH4 */
	2897	3, /* DEVICE_SIS */
	2898	6, /* DEVICE_ALI */
	2899	4, /* DEVICE_NFORCE */
	2900	};
[679]	2901	static const struct ich_reg_info intel_regs[6] = {
[305]	2902	{ ICH_PIINT, 0 },
	2903	{ ICH_POINT, 0x10 },
	2904	{ ICH_MCINT, 0x20 },
	2905	{ ICH_M2INT, 0x40 },
	2906	{ ICH_P2INT, 0x50 },
	2907	{ ICH_SPINT, 0x60 },
	2908	};
[679]	2909	static const struct ich_reg_info nforce_regs[4] = {
[305]	2910	{ ICH_PIINT, 0 },
	2911	{ ICH_POINT, 0x10 },
	2912	{ ICH_MCINT, 0x20 },
	2913	{ ICH_NVSPINT, 0x70 },
	2914	};
[679]	2915	static const struct ich_reg_info ali_regs[6] = {
[305]	2916	{ ALI_INT_PCMIN, 0x40 },
	2917	{ ALI_INT_PCMOUT, 0x50 },
	2918	{ ALI_INT_MICIN, 0x60 },
	2919	{ ALI_INT_CODECSPDIFOUT, 0x70 },
	2920	{ ALI_INT_SPDIFIN, 0xa0 },
	2921	{ ALI_INT_SPDIFOUT, 0xb0 },
	2922	};
[679]	2923	const struct ich_reg_info *tbl;
[32]	2924
[717]	2925	err = pcim_enable_device(pci);
[703]	2926	if (err < 0)
[305]	2927	return err;
[32]	2928
[305]	2929	spin_lock_init(&chip->reg_lock);
	2930	chip->device_type = device_type;
	2931	chip->card = card;
	2932	chip->pci = pci;
	2933	chip->irq = -1;
[32]	2934
[305]	2935	/* module parameters */
	2936	chip->buggy_irq = buggy_irq;
	2937	chip->buggy_semaphore = buggy_semaphore;
	2938	if (xbox)
	2939	chip->xbox = 1;
[32]	2940
[679]	2941	chip->inside_vm = snd_intel8x0_inside_vm(pci);
	2942
	2943	/*
	2944	* Intel 82443MX running a 100MHz processor system bus has a hardware
	2945	* bug, which aborts PCI busmaster for audio transfer. A workaround
	2946	* is to set the pages as non-cached. For details, see the errata in
	2947	* http://download.intel.com/design/chipsets/specupdt/24505108.pdf
	2948	*/
[305]	2949	if (pci->vendor == PCI_VENDOR_ID_INTEL &&
	2950	pci->device == PCI_DEVICE_ID_INTEL_440MX)
	2951	chip->fix_nocache = 1; /* enable workaround */
[32]	2952
[703]	2953	err = pci_request_regions(pci, card->shortname);
[717]	2954	if (err < 0)
[305]	2955	return err;
[32]	2956
[305]	2957	if (device_type == DEVICE_ALI) {
	2958	/* ALI5455 has no ac97 region */
[717]	2959	chip->bmaddr = pcim_iomap(pci, 0, 0);
	2960	} else {
	2961	if (pci_resource_flags(pci, 2) & IORESOURCE_MEM) /* ICH4 and Nforce */
	2962	chip->addr = pcim_iomap(pci, 2, 0);
	2963	else
	2964	chip->addr = pcim_iomap(pci, 0, 0);
	2965	if (pci_resource_flags(pci, 3) & IORESOURCE_MEM) /* ICH4 */
	2966	chip->bmaddr = pcim_iomap(pci, 3, 0);
	2967	else
	2968	chip->bmaddr = pcim_iomap(pci, 1, 0);
[305]	2969	}
[32]	2970
[305]	2971	chip->bdbars_count = bdbars[device_type];
[32]	2972
[305]	2973	/* initialize offsets */
	2974	switch (device_type) {
	2975	case DEVICE_NFORCE:
	2976	tbl = nforce_regs;
	2977	break;
	2978	case DEVICE_ALI:
	2979	tbl = ali_regs;
	2980	break;
	2981	default:
	2982	tbl = intel_regs;
	2983	break;
	2984	}
	2985	for (i = 0; i < chip->bdbars_count; i++) {
	2986	ichdev = &chip->ichd[i];
	2987	ichdev->ichd = i;
	2988	ichdev->reg_offset = tbl[i].offset;
	2989	ichdev->int_sta_mask = tbl[i].int_sta_mask;
	2990	if (device_type == DEVICE_SIS) {
	2991	/* SiS 7012 swaps the registers */
	2992	ichdev->roff_sr = ICH_REG_OFF_PICB;
	2993	ichdev->roff_picb = ICH_REG_OFF_SR;
	2994	} else {
	2995	ichdev->roff_sr = ICH_REG_OFF_SR;
	2996	ichdev->roff_picb = ICH_REG_OFF_PICB;
	2997	}
	2998	if (device_type == DEVICE_ALI)
	2999	ichdev->ali_slot = (ichdev->reg_offset - 0x40) / 0x10;
	3000	/* SIS7012 handles the pcm data in bytes, others are in samples */
	3001	ichdev->pos_shift = (device_type == DEVICE_SIS) ? 0 : 1;
	3002	}
[32]	3003
[305]	3004	/* allocate buffer descriptor lists */
	3005	/* the start of each lists must be aligned to 8 bytes */
[717]	3006	chip->bdbars = snd_devm_alloc_pages(&pci->dev, intel8x0_dma_type(chip),
	3007	chip->bdbars_count * sizeof(u32) *
	3008	ICH_MAX_FRAGS * 2);
	3009	if (!chip->bdbars)
[305]	3010	return -ENOMEM;
	3011	/* tables must be aligned to 8 bytes here, but the kernel pages
	3012	are much bigger, so we don't care (on i386) */
	3013	int_sta_masks = 0;
	3014	for (i = 0; i < chip->bdbars_count; i++) {
	3015	ichdev = &chip->ichd[i];
[717]	3016	ichdev->bdbar = ((__le32 *)chip->bdbars->area) +
[305]	3017	(i * ICH_MAX_FRAGS * 2);
[717]	3018	ichdev->bdbar_addr = chip->bdbars->addr +
[305]	3019	(i * sizeof(u32) * ICH_MAX_FRAGS * 2);
	3020	int_sta_masks \|= ichdev->int_sta_mask;
	3021	}
	3022	chip->int_sta_reg = device_type == DEVICE_ALI ?
	3023	ICH_REG_ALI_INTERRUPTSR : ICH_REG_GLOB_STA;
	3024	chip->int_sta_mask = int_sta_masks;
[32]	3025
[305]	3026	pci_set_master(pci);
[32]	3027
[305]	3028	switch(chip->device_type) {
	3029	case DEVICE_INTEL_ICH4:
	3030	/* ICH4 can have three codecs */
	3031	chip->max_codecs = 3;
	3032	chip->codec_bit = ich_codec_bits;
	3033	chip->codec_ready_bits = ICH_PRI \| ICH_SRI \| ICH_TRI;
	3034	break;
	3035	case DEVICE_SIS:
	3036	/* recent SIS7012 can have three codecs */
	3037	chip->max_codecs = 3;
	3038	chip->codec_bit = sis_codec_bits;
	3039	chip->codec_ready_bits = ICH_PRI \| ICH_SRI \| ICH_SIS_TRI;
	3040	break;
	3041	default:
	3042	/* others up to two codecs */
	3043	chip->max_codecs = 2;
	3044	chip->codec_bit = ich_codec_bits;
	3045	chip->codec_ready_bits = ICH_PRI \| ICH_SRI;
	3046	break;
	3047	}
	3048	for (i = 0; i < chip->max_codecs; i++)
	3049	chip->codec_isr_bits \|= chip->codec_bit[i];
[32]	3050
[703]	3051	err = snd_intel8x0_chip_init(chip, 1);
[717]	3052	if (err < 0)
[305]	3053	return err;
[32]	3054
[305]	3055	/* request irq after initializaing int_sta_mask, etc */
[717]	3056	/* NOTE: we don't use devm version here since it's released /
	3057	* re-acquired in PM callbacks.
	3058	* It's released explicitly in snd_intel8x0_free(), too.
	3059	*/
[305]	3060	if (request_irq(pci->irq, snd_intel8x0_interrupt,
[679]	3061	IRQF_SHARED, KBUILD_MODNAME, chip)) {
	3062	dev_err(card->dev, "unable to grab IRQ %d\n", pci->irq);
[305]	3063	return -EBUSY;
	3064	}
	3065	chip->irq = pci->irq;
[679]	3066	card->sync_irq = chip->irq;
[70]	3067
[717]	3068	card->private_free = snd_intel8x0_free;
[32]	3069
[305]	3070	return 0;
[32]	3071	}
	3072
	3073	static struct shortname_table {
[305]	3074	unsigned int id;
	3075	const char *s;
[679]	3076	} shortnames[] = {
[305]	3077	{ PCI_DEVICE_ID_INTEL_82801AA_5, "Intel 82801AA-ICH" },
	3078	{ PCI_DEVICE_ID_INTEL_82801AB_5, "Intel 82901AB-ICH0" },
	3079	{ PCI_DEVICE_ID_INTEL_82801BA_4, "Intel 82801BA-ICH2" },
	3080	{ PCI_DEVICE_ID_INTEL_440MX, "Intel 440MX" },
	3081	{ PCI_DEVICE_ID_INTEL_82801CA_5, "Intel 82801CA-ICH3" },
	3082	{ PCI_DEVICE_ID_INTEL_82801DB_5, "Intel 82801DB-ICH4" },
	3083	{ PCI_DEVICE_ID_INTEL_82801EB_5, "Intel ICH5" },
	3084	{ PCI_DEVICE_ID_INTEL_ESB_5, "Intel 6300ESB" },
	3085	{ PCI_DEVICE_ID_INTEL_ICH6_18, "Intel ICH6" },
	3086	{ PCI_DEVICE_ID_INTEL_ICH7_20, "Intel ICH7" },
	3087	{ PCI_DEVICE_ID_INTEL_ESB2_14, "Intel ESB2" },
	3088	{ PCI_DEVICE_ID_SI_7012, "SiS SI7012" },
	3089	{ PCI_DEVICE_ID_NVIDIA_MCP1_AUDIO, "NVidia nForce" },
	3090	{ PCI_DEVICE_ID_NVIDIA_MCP2_AUDIO, "NVidia nForce2" },
	3091	{ PCI_DEVICE_ID_NVIDIA_MCP3_AUDIO, "NVidia nForce3" },
	3092	{ PCI_DEVICE_ID_NVIDIA_CK8S_AUDIO, "NVidia CK8S" },
	3093	{ PCI_DEVICE_ID_NVIDIA_CK804_AUDIO, "NVidia CK804" },
	3094	{ PCI_DEVICE_ID_NVIDIA_CK8_AUDIO, "NVidia CK8" },
	3095	{ 0x003a, "NVidia MCP04" },
	3096	{ 0x746d, "AMD AMD8111" },
	3097	{ 0x7445, "AMD AMD768" },
	3098	{ 0x5455, "ALi M5455" },
	3099	{ 0, NULL },
[32]	3100	};
	3101
[679]	3102	static const struct snd_pci_quirk spdif_aclink_defaults[] = {
[305]	3103	SND_PCI_QUIRK(0x147b, 0x1c1a, "ASUS KN8", 1),
	3104	{0} /* end */
	3105	};
	3106
[679]	3107	/* look up allow/deny list for SPDIF over ac-link */
	3108	static int check_default_spdif_aclink(struct pci_dev *pci)
[305]	3109	{
	3110	const struct snd_pci_quirk *w;
	3111
	3112	w = snd_pci_quirk_lookup(pci, spdif_aclink_defaults);
	3113	if (w) {
	3114	if (w->value)
[679]	3115	dev_dbg(&pci->dev,
	3116	"Using SPDIF over AC-Link for %s\n",
	3117	snd_pci_quirk_name(w));
[305]	3118	else
[679]	3119	dev_dbg(&pci->dev,
	3120	"Using integrated SPDIF DMA for %s\n",
	3121	snd_pci_quirk_name(w));
[305]	3122	return w->value;
	3123	}
	3124	return 0;
	3125	}
	3126
[717]	3127	static int __snd_intel8x0_probe(struct pci_dev *pci,
	3128	const struct pci_device_id *pci_id)
[32]	3129	{
[305]	3130	struct snd_card *card;
	3131	struct intel8x0 *chip;
	3132	int err;
	3133	struct shortname_table *name;
[32]	3134
[717]	3135	err = snd_devm_card_new(&pci->dev, index, id, THIS_MODULE,
	3136	sizeof(*chip), &card);
[410]	3137	if (err < 0)
	3138	return err;
[717]	3139	chip = card->private_data;
[32]	3140
[305]	3141	if (spdif_aclink < 0)
	3142	spdif_aclink = check_default_spdif_aclink(pci);
[32]	3143
[305]	3144	strcpy(card->driver, "ICH");
	3145	if (!spdif_aclink) {
	3146	switch (pci_id->driver_data) {
	3147	case DEVICE_NFORCE:
	3148	strcpy(card->driver, "NFORCE");
	3149	break;
	3150	case DEVICE_INTEL_ICH4:
	3151	strcpy(card->driver, "ICH4");
	3152	}
	3153	}
[32]	3154
[305]	3155	strcpy(card->shortname, "Intel ICH");
	3156	for (name = shortnames; name->id; name++) {
	3157	if (pci->device == name->id) {
	3158	strcpy(card->shortname, name->s);
	3159	break;
	3160	}
	3161	}
[35]	3162
[305]	3163	if (buggy_irq < 0) {
	3164	/* some Nforce[2] and ICH boards have problems with IRQ handling.
	3165	* Needs to return IRQ_HANDLED for unknown irqs.
	3166	*/
	3167	if (pci_id->driver_data == DEVICE_NFORCE)
	3168	buggy_irq = 1;
	3169	else
	3170	buggy_irq = 0;
	3171	}
[35]	3172
[717]	3173	err = snd_intel8x0_init(card, pci, pci_id->driver_data);
	3174	if (err < 0)
[305]	3175	return err;
[32]	3176
[703]	3177	err = snd_intel8x0_mixer(chip, ac97_clock, ac97_quirk);
[717]	3178	if (err < 0)
[305]	3179	return err;
[703]	3180	err = snd_intel8x0_pcm(chip);
[717]	3181	if (err < 0)
[305]	3182	return err;
	3183
	3184	snd_intel8x0_proc_init(chip);
[32]	3185
[305]	3186	snprintf(card->longname, sizeof(card->longname),
	3187	"%s with %s at irq %i", card->shortname,
	3188	snd_ac97_get_short_name(chip->ac97[0]), chip->irq);
[32]	3189
[399]	3190	if (ac97_clock == 0 \|\| ac97_clock == 1) {
	3191	if (ac97_clock == 0) {
	3192	if (intel8x0_in_clock_list(chip) == 0)
	3193	intel8x0_measure_ac97_clock(chip);
	3194	} else {
	3195	intel8x0_measure_ac97_clock(chip);
	3196	}
	3197	}
[32]	3198
[703]	3199	err = snd_card_register(card);
[717]	3200	if (err < 0)
[305]	3201	return err;
[717]	3202
[305]	3203	pci_set_drvdata(pci, card);
	3204	return 0;
[32]	3205	}
	3206
[717]	3207	static int snd_intel8x0_probe(struct pci_dev *pci,
	3208	const struct pci_device_id *pci_id)
[32]	3209	{
[717]	3210	return snd_card_free_on_error(&pci->dev, __snd_intel8x0_probe(pci, pci_id));
[32]	3211	}
	3212
[679]	3213	static struct pci_driver intel8x0_driver = {
	3214	.name = KBUILD_MODNAME,
[32]	3215	.id_table = snd_intel8x0_ids,
	3216	.probe = snd_intel8x0_probe,
[679]	3217	.driver = {
[777]	3218	.pm = &intel8x0_pm,
[679]	3219	},
[32]	3220	};
	3221
[679]	3222	module_pci_driver(intel8x0_driver);

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source: GPL/trunk/alsa-kernel/pci/intel8x0.c

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