source: GPL/trunk/alsa-kernel/pci/intel8x0.c@ 717

Last change on this file since 717 was 717, checked in by David Azarewicz, 3 years ago

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1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * ALSA driver for Intel ICH (i8x0) chipsets
4 *
5 * Copyright (c) 2000 Jaroslav Kysela <perex@perex.cz>
6 *
7 * This code also contains alpha support for SiS 735 chipsets provided
8 * by Mike Pieper <mptei@users.sourceforge.net>. We have no datasheet
9 * for SiS735, so the code is not fully functional.
10 *
11 */
12
13#ifdef TARGET_OS2
14#define KBUILD_MODNAME "intel8x0"
15#endif
16
17#include <linux/io.h>
18#include <linux/delay.h>
19#include <linux/interrupt.h>
20#include <linux/init.h>
21#include <linux/pci.h>
22#include <linux/slab.h>
23#include <linux/module.h>
24#include <sound/core.h>
25#include <sound/pcm.h>
26#include <sound/ac97_codec.h>
27#include <sound/info.h>
28#include <sound/initval.h>
29
30MODULE_AUTHOR("Jaroslav Kysela <perex@perex.cz>");
31MODULE_DESCRIPTION("Intel 82801AA,82901AB,i810,i820,i830,i840,i845,MX440; SiS 7012; Ali 5455");
32MODULE_LICENSE("GPL");
33
34static int index = SNDRV_DEFAULT_IDX1; /* Index 0-MAX */
35static char *id = SNDRV_DEFAULT_STR1; /* ID for this card */
36static int ac97_clock;
37static char *ac97_quirk;
38static bool buggy_semaphore;
39static int buggy_irq = -1; /* auto-check */
40static bool xbox;
41static int spdif_aclink = -1;
42static int inside_vm = -1;
43
44module_param(index, int, 0444);
45MODULE_PARM_DESC(index, "Index value for Intel i8x0 soundcard.");
46module_param(id, charp, 0444);
47MODULE_PARM_DESC(id, "ID string for Intel i8x0 soundcard.");
48module_param(ac97_clock, int, 0444);
49MODULE_PARM_DESC(ac97_clock, "AC'97 codec clock (0 = allowlist + auto-detect, 1 = force autodetect).");
50module_param(ac97_quirk, charp, 0444);
51MODULE_PARM_DESC(ac97_quirk, "AC'97 workaround for strange hardware.");
52module_param(buggy_semaphore, bool, 0444);
53MODULE_PARM_DESC(buggy_semaphore, "Enable workaround for hardwares with problematic codec semaphores.");
54module_param(buggy_irq, bint, 0444);
55MODULE_PARM_DESC(buggy_irq, "Enable workaround for buggy interrupts on some motherboards.");
56module_param(xbox, bool, 0444);
57MODULE_PARM_DESC(xbox, "Set to 1 for Xbox, if you have problems with the AC'97 codec detection.");
58module_param(spdif_aclink, int, 0444);
59MODULE_PARM_DESC(spdif_aclink, "S/PDIF over AC-link.");
60module_param(inside_vm, bint, 0444);
61MODULE_PARM_DESC(inside_vm, "KVM/Parallels optimization.");
62
63/* just for backward compatibility */
64//static bool enable;
65module_param(enable, bool, 0444);
66//static int joystick;
67module_param(joystick, int, 0444);
68
69/*
70 * Direct registers
71 */
72enum { DEVICE_INTEL, DEVICE_INTEL_ICH4, DEVICE_SIS, DEVICE_ALI, DEVICE_NFORCE };
73
74#define ICHREG(x) ICH_REG_##x
75
76#define DEFINE_REGSET(name,base) \
77enum { \
78 ICH_REG_##name##_BDBAR = base + 0x0, /* dword - buffer descriptor list base address */ \
79 ICH_REG_##name##_CIV = base + 0x04, /* byte - current index value */ \
80 ICH_REG_##name##_LVI = base + 0x05, /* byte - last valid index */ \
81 ICH_REG_##name##_SR = base + 0x06, /* byte - status register */ \
82 ICH_REG_##name##_PICB = base + 0x08, /* word - position in current buffer */ \
83 ICH_REG_##name##_PIV = base + 0x0a, /* byte - prefetched index value */ \
84 ICH_REG_##name##_CR = base + 0x0b, /* byte - control register */ \
85}
86
87/* busmaster blocks */
88DEFINE_REGSET(OFF, 0); /* offset */
89DEFINE_REGSET(PI, 0x00); /* PCM in */
90DEFINE_REGSET(PO, 0x10); /* PCM out */
91DEFINE_REGSET(MC, 0x20); /* Mic in */
92
93/* ICH4 busmaster blocks */
94DEFINE_REGSET(MC2, 0x40); /* Mic in 2 */
95DEFINE_REGSET(PI2, 0x50); /* PCM in 2 */
96DEFINE_REGSET(SP, 0x60); /* SPDIF out */
97
98/* values for each busmaster block */
99
100/* LVI */
101#define ICH_REG_LVI_MASK 0x1f
102
103/* SR */
104#define ICH_FIFOE 0x10 /* FIFO error */
105#define ICH_BCIS 0x08 /* buffer completion interrupt status */
106#define ICH_LVBCI 0x04 /* last valid buffer completion interrupt */
107#define ICH_CELV 0x02 /* current equals last valid */
108#define ICH_DCH 0x01 /* DMA controller halted */
109
110/* PIV */
111#define ICH_REG_PIV_MASK 0x1f /* mask */
112
113/* CR */
114#define ICH_IOCE 0x10 /* interrupt on completion enable */
115#define ICH_FEIE 0x08 /* fifo error interrupt enable */
116#define ICH_LVBIE 0x04 /* last valid buffer interrupt enable */
117#define ICH_RESETREGS 0x02 /* reset busmaster registers */
118#define ICH_STARTBM 0x01 /* start busmaster operation */
119
120
121/* global block */
122#define ICH_REG_GLOB_CNT 0x2c /* dword - global control */
123#define ICH_PCM_SPDIF_MASK 0xc0000000 /* s/pdif pcm slot mask (ICH4) */
124#define ICH_PCM_SPDIF_NONE 0x00000000 /* reserved - undefined */
125#define ICH_PCM_SPDIF_78 0x40000000 /* s/pdif pcm on slots 7&8 */
126#define ICH_PCM_SPDIF_69 0x80000000 /* s/pdif pcm on slots 6&9 */
127#define ICH_PCM_SPDIF_1011 0xc0000000 /* s/pdif pcm on slots 10&11 */
128#define ICH_PCM_20BIT 0x00400000 /* 20-bit samples (ICH4) */
129#define ICH_PCM_246_MASK 0x00300000 /* chan mask (not all chips) */
130#define ICH_PCM_8 0x00300000 /* 8 channels (not all chips) */
131#define ICH_PCM_6 0x00200000 /* 6 channels (not all chips) */
132#define ICH_PCM_4 0x00100000 /* 4 channels (not all chips) */
133#define ICH_PCM_2 0x00000000 /* 2 channels (stereo) */
134#define ICH_SIS_PCM_246_MASK 0x000000c0 /* 6 channels (SIS7012) */
135#define ICH_SIS_PCM_6 0x00000080 /* 6 channels (SIS7012) */
136#define ICH_SIS_PCM_4 0x00000040 /* 4 channels (SIS7012) */
137#define ICH_SIS_PCM_2 0x00000000 /* 2 channels (SIS7012) */
138#define ICH_TRIE 0x00000040 /* tertiary resume interrupt enable */
139#define ICH_SRIE 0x00000020 /* secondary resume interrupt enable */
140#define ICH_PRIE 0x00000010 /* primary resume interrupt enable */
141#define ICH_ACLINK 0x00000008 /* AClink shut off */
142#define ICH_AC97WARM 0x00000004 /* AC'97 warm reset */
143#define ICH_AC97COLD 0x00000002 /* AC'97 cold reset */
144#define ICH_GIE 0x00000001 /* GPI interrupt enable */
145#define ICH_REG_GLOB_STA 0x30 /* dword - global status */
146#define ICH_TRI 0x20000000 /* ICH4: tertiary (AC_SDIN2) resume interrupt */
147#define ICH_TCR 0x10000000 /* ICH4: tertiary (AC_SDIN2) codec ready */
148#define ICH_BCS 0x08000000 /* ICH4: bit clock stopped */
149#define ICH_SPINT 0x04000000 /* ICH4: S/PDIF interrupt */
150#define ICH_P2INT 0x02000000 /* ICH4: PCM2-In interrupt */
151#define ICH_M2INT 0x01000000 /* ICH4: Mic2-In interrupt */
152#define ICH_SAMPLE_CAP 0x00c00000 /* ICH4: sample capability bits (RO) */
153#define ICH_SAMPLE_16_20 0x00400000 /* ICH4: 16- and 20-bit samples */
154#define ICH_MULTICHAN_CAP 0x00300000 /* ICH4: multi-channel capability bits (RO) */
155#define ICH_SIS_TRI 0x00080000 /* SIS: tertiary resume irq */
156#define ICH_SIS_TCR 0x00040000 /* SIS: tertiary codec ready */
157#define ICH_MD3 0x00020000 /* modem power down semaphore */
158#define ICH_AD3 0x00010000 /* audio power down semaphore */
159#define ICH_RCS 0x00008000 /* read completion status */
160#define ICH_BIT3 0x00004000 /* bit 3 slot 12 */
161#define ICH_BIT2 0x00002000 /* bit 2 slot 12 */
162#define ICH_BIT1 0x00001000 /* bit 1 slot 12 */
163#define ICH_SRI 0x00000800 /* secondary (AC_SDIN1) resume interrupt */
164#define ICH_PRI 0x00000400 /* primary (AC_SDIN0) resume interrupt */
165#define ICH_SCR 0x00000200 /* secondary (AC_SDIN1) codec ready */
166#define ICH_PCR 0x00000100 /* primary (AC_SDIN0) codec ready */
167#define ICH_MCINT 0x00000080 /* MIC capture interrupt */
168#define ICH_POINT 0x00000040 /* playback interrupt */
169#define ICH_PIINT 0x00000020 /* capture interrupt */
170#define ICH_NVSPINT 0x00000010 /* nforce spdif interrupt */
171#define ICH_MOINT 0x00000004 /* modem playback interrupt */
172#define ICH_MIINT 0x00000002 /* modem capture interrupt */
173#define ICH_GSCI 0x00000001 /* GPI status change interrupt */
174#define ICH_REG_ACC_SEMA 0x34 /* byte - codec write semaphore */
175#define ICH_CAS 0x01 /* codec access semaphore */
176#define ICH_REG_SDM 0x80
177#define ICH_DI2L_MASK 0x000000c0 /* PCM In 2, Mic In 2 data in line */
178#define ICH_DI2L_SHIFT 6
179#define ICH_DI1L_MASK 0x00000030 /* PCM In 1, Mic In 1 data in line */
180#define ICH_DI1L_SHIFT 4
181#define ICH_SE 0x00000008 /* steer enable */
182#define ICH_LDI_MASK 0x00000003 /* last codec read data input */
183
184#define ICH_MAX_FRAGS 32 /* max hw frags */
185
186
187/*
188 * registers for Ali5455
189 */
190
191/* ALi 5455 busmaster blocks */
192DEFINE_REGSET(AL_PI, 0x40); /* ALi PCM in */
193DEFINE_REGSET(AL_PO, 0x50); /* Ali PCM out */
194DEFINE_REGSET(AL_MC, 0x60); /* Ali Mic in */
195DEFINE_REGSET(AL_CDC_SPO, 0x70); /* Ali Codec SPDIF out */
196DEFINE_REGSET(AL_CENTER, 0x80); /* Ali center out */
197DEFINE_REGSET(AL_LFE, 0x90); /* Ali center out */
198DEFINE_REGSET(AL_CLR_SPI, 0xa0); /* Ali Controller SPDIF in */
199DEFINE_REGSET(AL_CLR_SPO, 0xb0); /* Ali Controller SPDIF out */
200DEFINE_REGSET(AL_I2S, 0xc0); /* Ali I2S in */
201DEFINE_REGSET(AL_PI2, 0xd0); /* Ali PCM2 in */
202DEFINE_REGSET(AL_MC2, 0xe0); /* Ali Mic2 in */
203
204enum {
205 ICH_REG_ALI_SCR = 0x00, /* System Control Register */
206 ICH_REG_ALI_SSR = 0x04, /* System Status Register */
207 ICH_REG_ALI_DMACR = 0x08, /* DMA Control Register */
208 ICH_REG_ALI_FIFOCR1 = 0x0c, /* FIFO Control Register 1 */
209 ICH_REG_ALI_INTERFACECR = 0x10, /* Interface Control Register */
210 ICH_REG_ALI_INTERRUPTCR = 0x14, /* Interrupt control Register */
211 ICH_REG_ALI_INTERRUPTSR = 0x18, /* Interrupt Status Register */
212 ICH_REG_ALI_FIFOCR2 = 0x1c, /* FIFO Control Register 2 */
213 ICH_REG_ALI_CPR = 0x20, /* Command Port Register */
214 ICH_REG_ALI_CPR_ADDR = 0x22, /* ac97 addr write */
215 ICH_REG_ALI_SPR = 0x24, /* Status Port Register */
216 ICH_REG_ALI_SPR_ADDR = 0x26, /* ac97 addr read */
217 ICH_REG_ALI_FIFOCR3 = 0x2c, /* FIFO Control Register 3 */
218 ICH_REG_ALI_TTSR = 0x30, /* Transmit Tag Slot Register */
219 ICH_REG_ALI_RTSR = 0x34, /* Receive Tag Slot Register */
220 ICH_REG_ALI_CSPSR = 0x38, /* Command/Status Port Status Register */
221 ICH_REG_ALI_CAS = 0x3c, /* Codec Write Semaphore Register */
222 ICH_REG_ALI_HWVOL = 0xf0, /* hardware volume control/status */
223 ICH_REG_ALI_I2SCR = 0xf4, /* I2S control/status */
224 ICH_REG_ALI_SPDIFCSR = 0xf8, /* spdif channel status register */
225 ICH_REG_ALI_SPDIFICS = 0xfc, /* spdif interface control/status */
226};
227
228#define ALI_CAS_SEM_BUSY 0x80000000
229#define ALI_CPR_ADDR_SECONDARY 0x100
230#define ALI_CPR_ADDR_READ 0x80
231#define ALI_CSPSR_CODEC_READY 0x08
232#define ALI_CSPSR_READ_OK 0x02
233#define ALI_CSPSR_WRITE_OK 0x01
234
235/* interrupts for the whole chip by interrupt status register finish */
236
237#define ALI_INT_MICIN2 (1<<26)
238#define ALI_INT_PCMIN2 (1<<25)
239#define ALI_INT_I2SIN (1<<24)
240#define ALI_INT_SPDIFOUT (1<<23) /* controller spdif out INTERRUPT */
241#define ALI_INT_SPDIFIN (1<<22)
242#define ALI_INT_LFEOUT (1<<21)
243#define ALI_INT_CENTEROUT (1<<20)
244#define ALI_INT_CODECSPDIFOUT (1<<19)
245#define ALI_INT_MICIN (1<<18)
246#define ALI_INT_PCMOUT (1<<17)
247#define ALI_INT_PCMIN (1<<16)
248#define ALI_INT_CPRAIS (1<<7) /* command port available */
249#define ALI_INT_SPRAIS (1<<5) /* status port available */
250#define ALI_INT_GPIO (1<<1)
251#define ALI_INT_MASK (ALI_INT_SPDIFOUT|ALI_INT_CODECSPDIFOUT|\
252 ALI_INT_MICIN|ALI_INT_PCMOUT|ALI_INT_PCMIN)
253
254#define ICH_ALI_SC_RESET (1<<31) /* master reset */
255#define ICH_ALI_SC_AC97_DBL (1<<30)
256#define ICH_ALI_SC_CODEC_SPDF (3<<20) /* 1=7/8, 2=6/9, 3=10/11 */
257#define ICH_ALI_SC_IN_BITS (3<<18)
258#define ICH_ALI_SC_OUT_BITS (3<<16)
259#define ICH_ALI_SC_6CH_CFG (3<<14)
260#define ICH_ALI_SC_PCM_4 (1<<8)
261#define ICH_ALI_SC_PCM_6 (2<<8)
262#define ICH_ALI_SC_PCM_246_MASK (3<<8)
263
264#define ICH_ALI_SS_SEC_ID (3<<5)
265#define ICH_ALI_SS_PRI_ID (3<<3)
266
267#define ICH_ALI_IF_AC97SP (1<<21)
268#define ICH_ALI_IF_MC (1<<20)
269#define ICH_ALI_IF_PI (1<<19)
270#define ICH_ALI_IF_MC2 (1<<18)
271#define ICH_ALI_IF_PI2 (1<<17)
272#define ICH_ALI_IF_LINE_SRC (1<<15) /* 0/1 = slot 3/6 */
273#define ICH_ALI_IF_MIC_SRC (1<<14) /* 0/1 = slot 3/6 */
274#define ICH_ALI_IF_SPDF_SRC (3<<12) /* 00 = PCM, 01 = AC97-in, 10 = spdif-in, 11 = i2s */
275#define ICH_ALI_IF_AC97_OUT (3<<8) /* 00 = PCM, 10 = spdif-in, 11 = i2s */
276#define ICH_ALI_IF_PO_SPDF (1<<3)
277#define ICH_ALI_IF_PO (1<<1)
278
279/*
280 *
281 */
282
283enum {
284 ICHD_PCMIN,
285 ICHD_PCMOUT,
286 ICHD_MIC,
287 ICHD_MIC2,
288 ICHD_PCM2IN,
289 ICHD_SPBAR,
290 ICHD_LAST = ICHD_SPBAR
291};
292enum {
293 NVD_PCMIN,
294 NVD_PCMOUT,
295 NVD_MIC,
296 NVD_SPBAR,
297 NVD_LAST = NVD_SPBAR
298};
299enum {
300 ALID_PCMIN,
301 ALID_PCMOUT,
302 ALID_MIC,
303 ALID_AC97SPDIFOUT,
304 ALID_SPDIFIN,
305 ALID_SPDIFOUT,
306 ALID_LAST = ALID_SPDIFOUT
307};
308
309#define get_ichdev(substream) (substream->runtime->private_data)
310
311struct ichdev {
312 unsigned int ichd; /* ich device number */
313 unsigned long reg_offset; /* offset to bmaddr */
314 __le32 *bdbar; /* CPU address (32bit) */
315 unsigned int bdbar_addr; /* PCI bus address (32bit) */
316 struct snd_pcm_substream *substream;
317 unsigned int physbuf; /* physical address (32bit) */
318 unsigned int size;
319 unsigned int fragsize;
320 unsigned int fragsize1;
321 unsigned int position;
322 unsigned int pos_shift;
323 unsigned int last_pos;
324 int frags;
325 int lvi;
326 int lvi_frag;
327 int civ;
328 int ack;
329 int ack_reload;
330 unsigned int ack_bit;
331 unsigned int roff_sr;
332 unsigned int roff_picb;
333 unsigned int int_sta_mask; /* interrupt status mask */
334 unsigned int ali_slot; /* ALI DMA slot */
335 struct ac97_pcm *pcm;
336 int pcm_open_flag;
337 unsigned int prepared:1;
338 unsigned int suspended: 1;
339};
340
341struct intel8x0 {
342 unsigned int device_type;
343
344 int irq;
345
346 void __iomem *addr;
347 void __iomem *bmaddr;
348
349 struct pci_dev *pci;
350 struct snd_card *card;
351
352 int pcm_devs;
353 struct snd_pcm *pcm[6];
354 struct ichdev ichd[6];
355
356 unsigned multi4: 1,
357 multi6: 1,
358 multi8 :1,
359 dra: 1,
360 smp20bit: 1;
361 unsigned in_ac97_init: 1,
362 in_sdin_init: 1;
363 unsigned in_measurement: 1; /* during ac97 clock measurement */
364 unsigned fix_nocache: 1; /* workaround for 440MX */
365 unsigned buggy_irq: 1; /* workaround for buggy mobos */
366 unsigned xbox: 1; /* workaround for Xbox AC'97 detection */
367 unsigned buggy_semaphore: 1; /* workaround for buggy codec semaphore */
368 unsigned inside_vm: 1; /* enable VM optimization */
369
370 int spdif_idx; /* SPDIF BAR index; *_SPBAR or -1 if use PCMOUT */
371 unsigned int sdm_saved; /* SDM reg value */
372
373 struct snd_ac97_bus *ac97_bus;
374 struct snd_ac97 *ac97[3];
375 unsigned int ac97_sdin[3];
376 unsigned int max_codecs, ncodecs;
377 const unsigned int *codec_bit;
378 unsigned int codec_isr_bits;
379 unsigned int codec_ready_bits;
380
381 spinlock_t reg_lock;
382
383 u32 bdbars_count;
384 struct snd_dma_buffer *bdbars;
385 u32 int_sta_reg; /* interrupt status register */
386 u32 int_sta_mask; /* interrupt status mask */
387};
388
389static const struct pci_device_id snd_intel8x0_ids[] = {
390 { PCI_VDEVICE(INTEL, 0x2415), DEVICE_INTEL }, /* 82801AA */
391 { PCI_VDEVICE(INTEL, 0x2425), DEVICE_INTEL }, /* 82901AB */
392 { PCI_VDEVICE(INTEL, 0x2445), DEVICE_INTEL }, /* 82801BA */
393 { PCI_VDEVICE(INTEL, 0x2485), DEVICE_INTEL }, /* ICH3 */
394 { PCI_VDEVICE(INTEL, 0x24c5), DEVICE_INTEL_ICH4 }, /* ICH4 */
395 { PCI_VDEVICE(INTEL, 0x24d5), DEVICE_INTEL_ICH4 }, /* ICH5 */
396 { PCI_VDEVICE(INTEL, 0x25a6), DEVICE_INTEL_ICH4 }, /* ESB */
397 { PCI_VDEVICE(INTEL, 0x266e), DEVICE_INTEL_ICH4 }, /* ICH6 */
398 { PCI_VDEVICE(INTEL, 0x27de), DEVICE_INTEL_ICH4 }, /* ICH7 */
399 { PCI_VDEVICE(INTEL, 0x2698), DEVICE_INTEL_ICH4 }, /* ESB2 */
400 { PCI_VDEVICE(INTEL, 0x7195), DEVICE_INTEL }, /* 440MX */
401 { PCI_VDEVICE(SI, 0x7012), DEVICE_SIS }, /* SI7012 */
402 { PCI_VDEVICE(NVIDIA, 0x01b1), DEVICE_NFORCE }, /* NFORCE */
403 { PCI_VDEVICE(NVIDIA, 0x003a), DEVICE_NFORCE }, /* MCP04 */
404 { PCI_VDEVICE(NVIDIA, 0x006a), DEVICE_NFORCE }, /* NFORCE2 */
405 { PCI_VDEVICE(NVIDIA, 0x0059), DEVICE_NFORCE }, /* CK804 */
406 { PCI_VDEVICE(NVIDIA, 0x008a), DEVICE_NFORCE }, /* CK8 */
407 { PCI_VDEVICE(NVIDIA, 0x00da), DEVICE_NFORCE }, /* NFORCE3 */
408 { PCI_VDEVICE(NVIDIA, 0x00ea), DEVICE_NFORCE }, /* CK8S */
409 { PCI_VDEVICE(NVIDIA, 0x026b), DEVICE_NFORCE }, /* MCP51 */
410 { PCI_VDEVICE(AMD, 0x746d), DEVICE_INTEL }, /* AMD8111 */
411 { PCI_VDEVICE(AMD, 0x7445), DEVICE_INTEL }, /* AMD768 */
412 { PCI_VDEVICE(AL, 0x5455), DEVICE_ALI }, /* Ali5455 */
413 { 0, }
414};
415
416MODULE_DEVICE_TABLE(pci, snd_intel8x0_ids);
417
418/*
419 * Lowlevel I/O - busmaster
420 */
421
422static inline u8 igetbyte(struct intel8x0 *chip, u32 offset)
423{
424 return ioread8(chip->bmaddr + offset);
425}
426
427static inline u16 igetword(struct intel8x0 *chip, u32 offset)
428{
429 return ioread16(chip->bmaddr + offset);
430}
431
432static inline u32 igetdword(struct intel8x0 *chip, u32 offset)
433{
434 return ioread32(chip->bmaddr + offset);
435}
436
437static inline void iputbyte(struct intel8x0 *chip, u32 offset, u8 val)
438{
439 iowrite8(val, chip->bmaddr + offset);
440}
441
442static inline void iputword(struct intel8x0 *chip, u32 offset, u16 val)
443{
444 iowrite16(val, chip->bmaddr + offset);
445}
446
447static inline void iputdword(struct intel8x0 *chip, u32 offset, u32 val)
448{
449 iowrite32(val, chip->bmaddr + offset);
450}
451
452/*
453 * Lowlevel I/O - AC'97 registers
454 */
455
456static inline u16 iagetword(struct intel8x0 *chip, u32 offset)
457{
458 return ioread16(chip->addr + offset);
459}
460
461static inline void iaputword(struct intel8x0 *chip, u32 offset, u16 val)
462{
463 iowrite16(val, chip->addr + offset);
464}
465
466/*
467 * Basic I/O
468 */
469
470/*
471 * access to AC97 codec via normal i/o (for ICH and SIS7012)
472 */
473
474static int snd_intel8x0_codec_semaphore(struct intel8x0 *chip, unsigned int codec)
475{
476 int time;
477
478 if (codec > 2)
479 return -EIO;
480 if (chip->in_sdin_init) {
481 /* we don't know the ready bit assignment at the moment */
482 /* so we check any */
483 codec = chip->codec_isr_bits;
484 } else {
485 codec = chip->codec_bit[chip->ac97_sdin[codec]];
486 }
487
488 /* codec ready ? */
489 if ((igetdword(chip, ICHREG(GLOB_STA)) & codec) == 0)
490 return -EIO;
491
492 if (chip->buggy_semaphore)
493 return 0; /* just ignore ... */
494
495 /* Anyone holding a semaphore for 1 msec should be shot... */
496 time = 100;
497 do {
498 if (!(igetbyte(chip, ICHREG(ACC_SEMA)) & ICH_CAS))
499 return 0;
500 udelay(10);
501 } while (time--);
502
503 /* access to some forbidden (non existent) ac97 registers will not
504 * reset the semaphore. So even if you don't get the semaphore, still
505 * continue the access. We don't need the semaphore anyway. */
506 dev_err(chip->card->dev,
507 "codec_semaphore: semaphore is not ready [0x%x][0x%x]\n",
508 igetbyte(chip, ICHREG(ACC_SEMA)), igetdword(chip, ICHREG(GLOB_STA)));
509 iagetword(chip, 0); /* clear semaphore flag */
510 /* I don't care about the semaphore */
511 return -EBUSY;
512}
513
514static void snd_intel8x0_codec_write(struct snd_ac97 *ac97,
515 unsigned short reg,
516 unsigned short val)
517{
518 struct intel8x0 *chip = ac97->private_data;
519
520 if (snd_intel8x0_codec_semaphore(chip, ac97->num) < 0) {
521 if (! chip->in_ac97_init)
522 dev_err(chip->card->dev,
523 "codec_write %d: semaphore is not ready for register 0x%x\n",
524 ac97->num, reg);
525 }
526 iaputword(chip, reg + ac97->num * 0x80, val);
527}
528
529static unsigned short snd_intel8x0_codec_read(struct snd_ac97 *ac97,
530 unsigned short reg)
531{
532 struct intel8x0 *chip = ac97->private_data;
533 unsigned short res;
534 unsigned int tmp;
535
536 if (snd_intel8x0_codec_semaphore(chip, ac97->num) < 0) {
537 if (! chip->in_ac97_init)
538 dev_err(chip->card->dev,
539 "codec_read %d: semaphore is not ready for register 0x%x\n",
540 ac97->num, reg);
541 res = 0xffff;
542 } else {
543 res = iagetword(chip, reg + ac97->num * 0x80);
544 tmp = igetdword(chip, ICHREG(GLOB_STA));
545 if (tmp & ICH_RCS) {
546 /* reset RCS and preserve other R/WC bits */
547 iputdword(chip, ICHREG(GLOB_STA), tmp &
548 ~(chip->codec_ready_bits | ICH_GSCI));
549 if (! chip->in_ac97_init)
550 dev_err(chip->card->dev,
551 "codec_read %d: read timeout for register 0x%x\n",
552 ac97->num, reg);
553 res = 0xffff;
554 }
555 }
556 return res;
557}
558
559static void snd_intel8x0_codec_read_test(struct intel8x0 *chip,
560 unsigned int codec)
561{
562 unsigned int tmp;
563
564 if (snd_intel8x0_codec_semaphore(chip, codec) >= 0) {
565 iagetword(chip, codec * 0x80);
566 tmp = igetdword(chip, ICHREG(GLOB_STA));
567 if (tmp & ICH_RCS) {
568 /* reset RCS and preserve other R/WC bits */
569 iputdword(chip, ICHREG(GLOB_STA), tmp &
570 ~(chip->codec_ready_bits | ICH_GSCI));
571 }
572 }
573}
574
575/*
576 * access to AC97 for Ali5455
577 */
578static int snd_intel8x0_ali_codec_ready(struct intel8x0 *chip, int mask)
579{
580 int count = 0;
581 for (count = 0; count < 0x7f; count++) {
582 int val = igetbyte(chip, ICHREG(ALI_CSPSR));
583 if (val & mask)
584 return 0;
585 }
586 if (! chip->in_ac97_init)
587 dev_warn(chip->card->dev, "AC97 codec ready timeout.\n");
588 return -EBUSY;
589}
590
591static int snd_intel8x0_ali_codec_semaphore(struct intel8x0 *chip)
592{
593 int time = 100;
594 if (chip->buggy_semaphore)
595 return 0; /* just ignore ... */
596 while (--time && (igetdword(chip, ICHREG(ALI_CAS)) & ALI_CAS_SEM_BUSY))
597 udelay(1);
598 if (! time && ! chip->in_ac97_init)
599 dev_warn(chip->card->dev, "ali_codec_semaphore timeout\n");
600 return snd_intel8x0_ali_codec_ready(chip, ALI_CSPSR_CODEC_READY);
601}
602
603static unsigned short snd_intel8x0_ali_codec_read(struct snd_ac97 *ac97, unsigned short reg)
604{
605 struct intel8x0 *chip = ac97->private_data;
606 unsigned short data = 0xffff;
607
608 if (snd_intel8x0_ali_codec_semaphore(chip))
609 goto __err;
610 reg |= ALI_CPR_ADDR_READ;
611 if (ac97->num)
612 reg |= ALI_CPR_ADDR_SECONDARY;
613 iputword(chip, ICHREG(ALI_CPR_ADDR), reg);
614 if (snd_intel8x0_ali_codec_ready(chip, ALI_CSPSR_READ_OK))
615 goto __err;
616 data = igetword(chip, ICHREG(ALI_SPR));
617 __err:
618 return data;
619}
620
621static void snd_intel8x0_ali_codec_write(struct snd_ac97 *ac97, unsigned short reg,
622 unsigned short val)
623{
624 struct intel8x0 *chip = ac97->private_data;
625
626 if (snd_intel8x0_ali_codec_semaphore(chip))
627 return;
628 iputword(chip, ICHREG(ALI_CPR), val);
629 if (ac97->num)
630 reg |= ALI_CPR_ADDR_SECONDARY;
631 iputword(chip, ICHREG(ALI_CPR_ADDR), reg);
632 snd_intel8x0_ali_codec_ready(chip, ALI_CSPSR_WRITE_OK);
633}
634
635
636/*
637 * DMA I/O
638 */
639static void snd_intel8x0_setup_periods(struct intel8x0 *chip, struct ichdev *ichdev)
640{
641 int idx;
642 __le32 *bdbar = ichdev->bdbar;
643 unsigned long port = ichdev->reg_offset;
644
645 iputdword(chip, port + ICH_REG_OFF_BDBAR, ichdev->bdbar_addr);
646 if (ichdev->size == ichdev->fragsize) {
647 ichdev->ack_reload = ichdev->ack = 2;
648 ichdev->fragsize1 = ichdev->fragsize >> 1;
649 for (idx = 0; idx < (ICH_REG_LVI_MASK + 1) * 2; idx += 4) {
650 bdbar[idx + 0] = cpu_to_le32(ichdev->physbuf);
651 bdbar[idx + 1] = cpu_to_le32(0x80000000 | /* interrupt on completion */
652 ichdev->fragsize1 >> ichdev->pos_shift);
653 bdbar[idx + 2] = cpu_to_le32(ichdev->physbuf + (ichdev->size >> 1));
654 bdbar[idx + 3] = cpu_to_le32(0x80000000 | /* interrupt on completion */
655 ichdev->fragsize1 >> ichdev->pos_shift);
656 }
657 ichdev->frags = 2;
658 } else {
659 ichdev->ack_reload = ichdev->ack = 1;
660 ichdev->fragsize1 = ichdev->fragsize;
661 for (idx = 0; idx < (ICH_REG_LVI_MASK + 1) * 2; idx += 2) {
662 bdbar[idx + 0] = cpu_to_le32(ichdev->physbuf +
663 (((idx >> 1) * ichdev->fragsize) %
664 ichdev->size));
665 bdbar[idx + 1] = cpu_to_le32(0x80000000 | /* interrupt on completion */
666 ichdev->fragsize >> ichdev->pos_shift);
667#if 0
668 dev_dbg(chip->card->dev, "bdbar[%i] = 0x%x [0x%x]\n",
669 idx + 0, bdbar[idx + 0], bdbar[idx + 1]);
670#endif
671 }
672 ichdev->frags = ichdev->size / ichdev->fragsize;
673 }
674 iputbyte(chip, port + ICH_REG_OFF_LVI, ichdev->lvi = ICH_REG_LVI_MASK);
675 ichdev->civ = 0;
676 iputbyte(chip, port + ICH_REG_OFF_CIV, 0);
677 ichdev->lvi_frag = ICH_REG_LVI_MASK % ichdev->frags;
678 ichdev->position = 0;
679#if 0
680 dev_dbg(chip->card->dev,
681 "lvi_frag = %i, frags = %i, period_size = 0x%x, period_size1 = 0x%x\n",
682 ichdev->lvi_frag, ichdev->frags, ichdev->fragsize,
683 ichdev->fragsize1);
684#endif
685 /* clear interrupts */
686 iputbyte(chip, port + ichdev->roff_sr, ICH_FIFOE | ICH_BCIS | ICH_LVBCI);
687}
688
689/*
690 * Interrupt handler
691 */
692
693static inline void snd_intel8x0_update(struct intel8x0 *chip, struct ichdev *ichdev)
694{
695 unsigned long port = ichdev->reg_offset;
696 unsigned long flags;
697 int status, civ, i, step;
698 int ack = 0;
699
700 if (!(ichdev->prepared || chip->in_measurement) || ichdev->suspended)
701 return;
702
703 spin_lock_irqsave(&chip->reg_lock, flags);
704 status = igetbyte(chip, port + ichdev->roff_sr);
705 civ = igetbyte(chip, port + ICH_REG_OFF_CIV);
706 if (!(status & ICH_BCIS)) {
707 step = 0;
708 } else if (civ == ichdev->civ) {
709 // snd_printd("civ same %d\n", civ);
710 step = 1;
711 ichdev->civ++;
712 ichdev->civ &= ICH_REG_LVI_MASK;
713 } else {
714 step = civ - ichdev->civ;
715 if (step < 0)
716 step += ICH_REG_LVI_MASK + 1;
717 // if (step != 1)
718 // snd_printd("step = %d, %d -> %d\n", step, ichdev->civ, civ);
719 ichdev->civ = civ;
720 }
721
722 ichdev->position += step * ichdev->fragsize1;
723 if (! chip->in_measurement)
724 ichdev->position %= ichdev->size;
725 ichdev->lvi += step;
726 ichdev->lvi &= ICH_REG_LVI_MASK;
727 iputbyte(chip, port + ICH_REG_OFF_LVI, ichdev->lvi);
728 for (i = 0; i < step; i++) {
729 ichdev->lvi_frag++;
730 ichdev->lvi_frag %= ichdev->frags;
731 ichdev->bdbar[ichdev->lvi * 2] = cpu_to_le32(ichdev->physbuf + ichdev->lvi_frag * ichdev->fragsize1);
732#if 0
733 dev_dbg(chip->card->dev,
734 "new: bdbar[%i] = 0x%x [0x%x], prefetch = %i, all = 0x%x, 0x%x\n",
735 ichdev->lvi * 2, ichdev->bdbar[ichdev->lvi * 2],
736 ichdev->bdbar[ichdev->lvi * 2 + 1], inb(ICH_REG_OFF_PIV + port),
737 inl(port + 4), inb(port + ICH_REG_OFF_CR));
738#endif
739 if (--ichdev->ack == 0) {
740 ichdev->ack = ichdev->ack_reload;
741 ack = 1;
742 }
743 }
744 spin_unlock_irqrestore(&chip->reg_lock, flags);
745 if (ack && ichdev->substream) {
746 snd_pcm_period_elapsed(ichdev->substream);
747 }
748 iputbyte(chip, port + ichdev->roff_sr,
749 status & (ICH_FIFOE | ICH_BCIS | ICH_LVBCI));
750}
751
752static irqreturn_t snd_intel8x0_interrupt(int irq, void *dev_id)
753{
754 struct intel8x0 *chip = dev_id;
755 struct ichdev *ichdev;
756 unsigned int status;
757 unsigned int i;
758
759 status = igetdword(chip, chip->int_sta_reg);
760 if (status == 0xffffffff) /* we are not yet resumed */
761 return IRQ_NONE;
762
763 if ((status & chip->int_sta_mask) == 0) {
764 if (status) {
765 /* ack */
766 iputdword(chip, chip->int_sta_reg, status);
767 if (! chip->buggy_irq)
768 status = 0;
769 }
770 return IRQ_RETVAL(status);
771 }
772
773 for (i = 0; i < chip->bdbars_count; i++) {
774 ichdev = &chip->ichd[i];
775 if (status & ichdev->int_sta_mask)
776 snd_intel8x0_update(chip, ichdev);
777 }
778
779 /* ack them */
780 iputdword(chip, chip->int_sta_reg, status & chip->int_sta_mask);
781
782 return IRQ_HANDLED;
783}
784
785/*
786 * PCM part
787 */
788
789static int snd_intel8x0_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
790{
791 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
792 struct ichdev *ichdev = get_ichdev(substream);
793 unsigned char val = 0;
794 unsigned long port = ichdev->reg_offset;
795
796 switch (cmd) {
797 case SNDRV_PCM_TRIGGER_RESUME:
798 ichdev->suspended = 0;
799 fallthrough;
800 case SNDRV_PCM_TRIGGER_START:
801 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
802 val = ICH_IOCE | ICH_STARTBM;
803 ichdev->last_pos = ichdev->position;
804 break;
805 case SNDRV_PCM_TRIGGER_SUSPEND:
806 ichdev->suspended = 1;
807 fallthrough;
808 case SNDRV_PCM_TRIGGER_STOP:
809 val = 0;
810 break;
811 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
812 val = ICH_IOCE;
813 break;
814 default:
815 return -EINVAL;
816 }
817 iputbyte(chip, port + ICH_REG_OFF_CR, val);
818 if (cmd == SNDRV_PCM_TRIGGER_STOP) {
819 /* wait until DMA stopped */
820 while (!(igetbyte(chip, port + ichdev->roff_sr) & ICH_DCH)) ;
821 /* reset whole DMA things */
822 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_RESETREGS);
823 }
824 return 0;
825}
826
827static int snd_intel8x0_ali_trigger(struct snd_pcm_substream *substream, int cmd)
828{
829 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
830 struct ichdev *ichdev = get_ichdev(substream);
831 unsigned long port = ichdev->reg_offset;
832 static const int fiforeg[] = {
833 ICHREG(ALI_FIFOCR1), ICHREG(ALI_FIFOCR2), ICHREG(ALI_FIFOCR3)
834 };
835 unsigned int val, fifo;
836
837 val = igetdword(chip, ICHREG(ALI_DMACR));
838 switch (cmd) {
839 case SNDRV_PCM_TRIGGER_RESUME:
840 ichdev->suspended = 0;
841 fallthrough;
842 case SNDRV_PCM_TRIGGER_START:
843 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
844 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
845 /* clear FIFO for synchronization of channels */
846 fifo = igetdword(chip, fiforeg[ichdev->ali_slot / 4]);
847 fifo &= ~(0xff << (ichdev->ali_slot % 4));
848 fifo |= 0x83 << (ichdev->ali_slot % 4);
849 iputdword(chip, fiforeg[ichdev->ali_slot / 4], fifo);
850 }
851 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_IOCE);
852 val &= ~(1 << (ichdev->ali_slot + 16)); /* clear PAUSE flag */
853 /* start DMA */
854 iputdword(chip, ICHREG(ALI_DMACR), val | (1 << ichdev->ali_slot));
855 break;
856 case SNDRV_PCM_TRIGGER_SUSPEND:
857 ichdev->suspended = 1;
858 fallthrough;
859 case SNDRV_PCM_TRIGGER_STOP:
860 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
861 /* pause */
862 iputdword(chip, ICHREG(ALI_DMACR), val | (1 << (ichdev->ali_slot + 16)));
863 iputbyte(chip, port + ICH_REG_OFF_CR, 0);
864 while (igetbyte(chip, port + ICH_REG_OFF_CR))
865 ;
866 if (cmd == SNDRV_PCM_TRIGGER_PAUSE_PUSH)
867 break;
868 /* reset whole DMA things */
869 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_RESETREGS);
870 /* clear interrupts */
871 iputbyte(chip, port + ICH_REG_OFF_SR,
872 igetbyte(chip, port + ICH_REG_OFF_SR) | 0x1e);
873 iputdword(chip, ICHREG(ALI_INTERRUPTSR),
874 igetdword(chip, ICHREG(ALI_INTERRUPTSR)) & ichdev->int_sta_mask);
875 break;
876 default:
877 return -EINVAL;
878 }
879 return 0;
880}
881
882static int snd_intel8x0_hw_params(struct snd_pcm_substream *substream,
883 struct snd_pcm_hw_params *hw_params)
884{
885 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
886 struct ichdev *ichdev = get_ichdev(substream);
887 int dbl = params_rate(hw_params) > 48000;
888 int err;
889
890 if (ichdev->pcm_open_flag) {
891 snd_ac97_pcm_close(ichdev->pcm);
892 ichdev->pcm_open_flag = 0;
893 ichdev->prepared = 0;
894 }
895 err = snd_ac97_pcm_open(ichdev->pcm, params_rate(hw_params),
896 params_channels(hw_params),
897 ichdev->pcm->r[dbl].slots);
898 if (err >= 0) {
899 ichdev->pcm_open_flag = 1;
900 /* Force SPDIF setting */
901 if (ichdev->ichd == ICHD_PCMOUT && chip->spdif_idx < 0)
902 snd_ac97_set_rate(ichdev->pcm->r[0].codec[0], AC97_SPDIF,
903 params_rate(hw_params));
904 }
905 return err;
906}
907
908static int snd_intel8x0_hw_free(struct snd_pcm_substream *substream)
909{
910 struct ichdev *ichdev = get_ichdev(substream);
911
912 if (ichdev->pcm_open_flag) {
913 snd_ac97_pcm_close(ichdev->pcm);
914 ichdev->pcm_open_flag = 0;
915 ichdev->prepared = 0;
916 }
917 return 0;
918}
919
920static void snd_intel8x0_setup_pcm_out(struct intel8x0 *chip,
921 struct snd_pcm_runtime *runtime)
922{
923 unsigned int cnt;
924 int dbl = runtime->rate > 48000;
925
926 spin_lock_irq(&chip->reg_lock);
927 switch (chip->device_type) {
928 case DEVICE_ALI:
929 cnt = igetdword(chip, ICHREG(ALI_SCR));
930 cnt &= ~ICH_ALI_SC_PCM_246_MASK;
931 if (runtime->channels == 4 || dbl)
932 cnt |= ICH_ALI_SC_PCM_4;
933 else if (runtime->channels == 6)
934 cnt |= ICH_ALI_SC_PCM_6;
935 iputdword(chip, ICHREG(ALI_SCR), cnt);
936 break;
937 case DEVICE_SIS:
938 cnt = igetdword(chip, ICHREG(GLOB_CNT));
939 cnt &= ~ICH_SIS_PCM_246_MASK;
940 if (runtime->channels == 4 || dbl)
941 cnt |= ICH_SIS_PCM_4;
942 else if (runtime->channels == 6)
943 cnt |= ICH_SIS_PCM_6;
944 iputdword(chip, ICHREG(GLOB_CNT), cnt);
945 break;
946 default:
947 cnt = igetdword(chip, ICHREG(GLOB_CNT));
948 cnt &= ~(ICH_PCM_246_MASK | ICH_PCM_20BIT);
949 if (runtime->channels == 4 || dbl)
950 cnt |= ICH_PCM_4;
951 else if (runtime->channels == 6)
952 cnt |= ICH_PCM_6;
953 else if (runtime->channels == 8)
954 cnt |= ICH_PCM_8;
955 if (chip->device_type == DEVICE_NFORCE) {
956 /* reset to 2ch once to keep the 6 channel data in alignment,
957 * to start from Front Left always
958 */
959 if (cnt & ICH_PCM_246_MASK) {
960 iputdword(chip, ICHREG(GLOB_CNT), cnt & ~ICH_PCM_246_MASK);
961 spin_unlock_irq(&chip->reg_lock);
962 msleep(50); /* grrr... */
963 spin_lock_irq(&chip->reg_lock);
964 }
965 } else if (chip->device_type == DEVICE_INTEL_ICH4) {
966 if (runtime->sample_bits > 16)
967 cnt |= ICH_PCM_20BIT;
968 }
969 iputdword(chip, ICHREG(GLOB_CNT), cnt);
970 break;
971 }
972 spin_unlock_irq(&chip->reg_lock);
973}
974
975static int snd_intel8x0_pcm_prepare(struct snd_pcm_substream *substream)
976{
977 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
978 struct snd_pcm_runtime *runtime = substream->runtime;
979 struct ichdev *ichdev = get_ichdev(substream);
980
981 ichdev->physbuf = runtime->dma_addr;
982 ichdev->size = snd_pcm_lib_buffer_bytes(substream);
983 ichdev->fragsize = snd_pcm_lib_period_bytes(substream);
984 if (ichdev->ichd == ICHD_PCMOUT) {
985 snd_intel8x0_setup_pcm_out(chip, runtime);
986 if (chip->device_type == DEVICE_INTEL_ICH4)
987 ichdev->pos_shift = (runtime->sample_bits > 16) ? 2 : 1;
988 }
989 snd_intel8x0_setup_periods(chip, ichdev);
990 ichdev->prepared = 1;
991 return 0;
992}
993
994static snd_pcm_uframes_t snd_intel8x0_pcm_pointer(struct snd_pcm_substream *substream)
995{
996 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
997 struct ichdev *ichdev = get_ichdev(substream);
998 size_t ptr1, ptr;
999 int civ, timeout = 10;
1000 unsigned int position;
1001
1002 spin_lock(&chip->reg_lock);
1003 do {
1004 civ = igetbyte(chip, ichdev->reg_offset + ICH_REG_OFF_CIV);
1005 ptr1 = igetword(chip, ichdev->reg_offset + ichdev->roff_picb);
1006 position = ichdev->position;
1007 if (ptr1 == 0) {
1008 udelay(10);
1009 continue;
1010 }
1011 if (civ != igetbyte(chip, ichdev->reg_offset + ICH_REG_OFF_CIV))
1012 continue;
1013
1014 /* IO read operation is very expensive inside virtual machine
1015 * as it is emulated. The probability that subsequent PICB read
1016 * will return different result is high enough to loop till
1017 * timeout here.
1018 * Same CIV is strict enough condition to be sure that PICB
1019 * is valid inside VM on emulated card. */
1020 if (chip->inside_vm)
1021 break;
1022 if (ptr1 == igetword(chip, ichdev->reg_offset + ichdev->roff_picb))
1023 break;
1024 } while (timeout--);
1025 ptr = ichdev->last_pos;
1026 if (ptr1 != 0) {
1027 ptr1 <<= ichdev->pos_shift;
1028 ptr = ichdev->fragsize1 - ptr1;
1029 ptr += position;
1030 if (ptr < ichdev->last_pos) {
1031 unsigned int pos_base, last_base;
1032 pos_base = position / ichdev->fragsize1;
1033 last_base = ichdev->last_pos / ichdev->fragsize1;
1034 /* another sanity check; ptr1 can go back to full
1035 * before the base position is updated
1036 */
1037 if (pos_base == last_base)
1038 ptr = ichdev->last_pos;
1039 }
1040 }
1041 ichdev->last_pos = ptr;
1042 spin_unlock(&chip->reg_lock);
1043 if (ptr >= ichdev->size)
1044 return 0;
1045 return bytes_to_frames(substream->runtime, ptr);
1046}
1047
1048static const struct snd_pcm_hardware snd_intel8x0_stream =
1049{
1050 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1051 SNDRV_PCM_INFO_BLOCK_TRANSFER |
1052 SNDRV_PCM_INFO_MMAP_VALID |
1053 SNDRV_PCM_INFO_PAUSE |
1054 SNDRV_PCM_INFO_RESUME),
1055 .formats = SNDRV_PCM_FMTBIT_S16_LE,
1056 .rates = SNDRV_PCM_RATE_48000,
1057 .rate_min = 48000,
1058 .rate_max = 48000,
1059 .channels_min = 2,
1060 .channels_max = 2,
1061 .buffer_bytes_max = 128 * 1024,
1062 .period_bytes_min = 32,
1063 .period_bytes_max = 128 * 1024,
1064 .periods_min = 1,
1065 .periods_max = 1024,
1066 .fifo_size = 0,
1067};
1068
1069static const unsigned int channels4[] = {
1070 2, 4,
1071};
1072
1073static const struct snd_pcm_hw_constraint_list hw_constraints_channels4 = {
1074 .count = ARRAY_SIZE(channels4),
1075 .list = channels4,
1076 .mask = 0,
1077};
1078
1079static const unsigned int channels6[] = {
1080 2, 4, 6,
1081};
1082
1083static const struct snd_pcm_hw_constraint_list hw_constraints_channels6 = {
1084 .count = ARRAY_SIZE(channels6),
1085 .list = channels6,
1086 .mask = 0,
1087};
1088
1089static const unsigned int channels8[] = {
1090 2, 4, 6, 8,
1091};
1092
1093static const struct snd_pcm_hw_constraint_list hw_constraints_channels8 = {
1094 .count = ARRAY_SIZE(channels8),
1095 .list = channels8,
1096 .mask = 0,
1097};
1098
1099static int snd_intel8x0_pcm_open(struct snd_pcm_substream *substream, struct ichdev *ichdev)
1100{
1101 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1102 struct snd_pcm_runtime *runtime = substream->runtime;
1103 int err;
1104
1105 ichdev->substream = substream;
1106 runtime->hw = snd_intel8x0_stream;
1107 runtime->hw.rates = ichdev->pcm->rates;
1108 snd_pcm_limit_hw_rates(runtime);
1109 if (chip->device_type == DEVICE_SIS) {
1110 runtime->hw.buffer_bytes_max = 64*1024;
1111 runtime->hw.period_bytes_max = 64*1024;
1112 }
1113 err = snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS);
1114 if (err < 0)
1115 return err;
1116 runtime->private_data = ichdev;
1117 return 0;
1118}
1119
1120static int snd_intel8x0_playback_open(struct snd_pcm_substream *substream)
1121{
1122 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1123 struct snd_pcm_runtime *runtime = substream->runtime;
1124 int err;
1125
1126 err = snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_PCMOUT]);
1127 if (err < 0)
1128 return err;
1129
1130 if (chip->multi8) {
1131 runtime->hw.channels_max = 8;
1132 snd_pcm_hw_constraint_list(runtime, 0,
1133 SNDRV_PCM_HW_PARAM_CHANNELS,
1134 &hw_constraints_channels8);
1135 } else if (chip->multi6) {
1136 runtime->hw.channels_max = 6;
1137 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
1138 &hw_constraints_channels6);
1139 } else if (chip->multi4) {
1140 runtime->hw.channels_max = 4;
1141 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
1142 &hw_constraints_channels4);
1143 }
1144 if (chip->dra) {
1145 snd_ac97_pcm_double_rate_rules(runtime);
1146 }
1147 if (chip->smp20bit) {
1148 runtime->hw.formats |= SNDRV_PCM_FMTBIT_S32_LE;
1149 snd_pcm_hw_constraint_msbits(runtime, 0, 32, 20);
1150 }
1151 return 0;
1152}
1153
1154static int snd_intel8x0_playback_close(struct snd_pcm_substream *substream)
1155{
1156 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1157
1158 chip->ichd[ICHD_PCMOUT].substream = NULL;
1159 return 0;
1160}
1161
1162static int snd_intel8x0_capture_open(struct snd_pcm_substream *substream)
1163{
1164 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1165
1166 return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_PCMIN]);
1167}
1168
1169static int snd_intel8x0_capture_close(struct snd_pcm_substream *substream)
1170{
1171 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1172
1173 chip->ichd[ICHD_PCMIN].substream = NULL;
1174 return 0;
1175}
1176
1177static int snd_intel8x0_mic_open(struct snd_pcm_substream *substream)
1178{
1179 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1180
1181 return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_MIC]);
1182}
1183
1184static int snd_intel8x0_mic_close(struct snd_pcm_substream *substream)
1185{
1186 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1187
1188 chip->ichd[ICHD_MIC].substream = NULL;
1189 return 0;
1190}
1191
1192static int snd_intel8x0_mic2_open(struct snd_pcm_substream *substream)
1193{
1194 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1195
1196 return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_MIC2]);
1197}
1198
1199static int snd_intel8x0_mic2_close(struct snd_pcm_substream *substream)
1200{
1201 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1202
1203 chip->ichd[ICHD_MIC2].substream = NULL;
1204 return 0;
1205}
1206
1207static int snd_intel8x0_capture2_open(struct snd_pcm_substream *substream)
1208{
1209 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1210
1211 return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_PCM2IN]);
1212}
1213
1214static int snd_intel8x0_capture2_close(struct snd_pcm_substream *substream)
1215{
1216 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1217
1218 chip->ichd[ICHD_PCM2IN].substream = NULL;
1219 return 0;
1220}
1221
1222static int snd_intel8x0_spdif_open(struct snd_pcm_substream *substream)
1223{
1224 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1225 int idx = chip->device_type == DEVICE_NFORCE ? NVD_SPBAR : ICHD_SPBAR;
1226
1227 return snd_intel8x0_pcm_open(substream, &chip->ichd[idx]);
1228}
1229
1230static int snd_intel8x0_spdif_close(struct snd_pcm_substream *substream)
1231{
1232 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1233 int idx = chip->device_type == DEVICE_NFORCE ? NVD_SPBAR : ICHD_SPBAR;
1234
1235 chip->ichd[idx].substream = NULL;
1236 return 0;
1237}
1238
1239static int snd_intel8x0_ali_ac97spdifout_open(struct snd_pcm_substream *substream)
1240{
1241 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1242 unsigned int val;
1243
1244 spin_lock_irq(&chip->reg_lock);
1245 val = igetdword(chip, ICHREG(ALI_INTERFACECR));
1246 val |= ICH_ALI_IF_AC97SP;
1247 iputdword(chip, ICHREG(ALI_INTERFACECR), val);
1248 /* also needs to set ALI_SC_CODEC_SPDF correctly */
1249 spin_unlock_irq(&chip->reg_lock);
1250
1251 return snd_intel8x0_pcm_open(substream, &chip->ichd[ALID_AC97SPDIFOUT]);
1252}
1253
1254static int snd_intel8x0_ali_ac97spdifout_close(struct snd_pcm_substream *substream)
1255{
1256 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1257 unsigned int val;
1258
1259 chip->ichd[ALID_AC97SPDIFOUT].substream = NULL;
1260 spin_lock_irq(&chip->reg_lock);
1261 val = igetdword(chip, ICHREG(ALI_INTERFACECR));
1262 val &= ~ICH_ALI_IF_AC97SP;
1263 iputdword(chip, ICHREG(ALI_INTERFACECR), val);
1264 spin_unlock_irq(&chip->reg_lock);
1265
1266 return 0;
1267}
1268
1269#if 0 // NYI
1270static int snd_intel8x0_ali_spdifin_open(struct snd_pcm_substream *substream)
1271{
1272 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1273
1274 return snd_intel8x0_pcm_open(substream, &chip->ichd[ALID_SPDIFIN]);
1275}
1276
1277static int snd_intel8x0_ali_spdifin_close(struct snd_pcm_substream *substream)
1278{
1279 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1280
1281 chip->ichd[ALID_SPDIFIN].substream = NULL;
1282 return 0;
1283}
1284
1285static int snd_intel8x0_ali_spdifout_open(struct snd_pcm_substream *substream)
1286{
1287 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1288
1289 return snd_intel8x0_pcm_open(substream, &chip->ichd[ALID_SPDIFOUT]);
1290}
1291
1292static int snd_intel8x0_ali_spdifout_close(struct snd_pcm_substream *substream)
1293{
1294 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1295
1296 chip->ichd[ALID_SPDIFOUT].substream = NULL;
1297 return 0;
1298}
1299#endif
1300
1301static const struct snd_pcm_ops snd_intel8x0_playback_ops = {
1302 .open = snd_intel8x0_playback_open,
1303 .close = snd_intel8x0_playback_close,
1304 .hw_params = snd_intel8x0_hw_params,
1305 .hw_free = snd_intel8x0_hw_free,
1306 .prepare = snd_intel8x0_pcm_prepare,
1307 .trigger = snd_intel8x0_pcm_trigger,
1308 .pointer = snd_intel8x0_pcm_pointer,
1309};
1310
1311static const struct snd_pcm_ops snd_intel8x0_capture_ops = {
1312 .open = snd_intel8x0_capture_open,
1313 .close = snd_intel8x0_capture_close,
1314 .hw_params = snd_intel8x0_hw_params,
1315 .hw_free = snd_intel8x0_hw_free,
1316 .prepare = snd_intel8x0_pcm_prepare,
1317 .trigger = snd_intel8x0_pcm_trigger,
1318 .pointer = snd_intel8x0_pcm_pointer,
1319};
1320
1321static const struct snd_pcm_ops snd_intel8x0_capture_mic_ops = {
1322 .open = snd_intel8x0_mic_open,
1323 .close = snd_intel8x0_mic_close,
1324 .hw_params = snd_intel8x0_hw_params,
1325 .hw_free = snd_intel8x0_hw_free,
1326 .prepare = snd_intel8x0_pcm_prepare,
1327 .trigger = snd_intel8x0_pcm_trigger,
1328 .pointer = snd_intel8x0_pcm_pointer,
1329};
1330
1331static const struct snd_pcm_ops snd_intel8x0_capture_mic2_ops = {
1332 .open = snd_intel8x0_mic2_open,
1333 .close = snd_intel8x0_mic2_close,
1334 .hw_params = snd_intel8x0_hw_params,
1335 .hw_free = snd_intel8x0_hw_free,
1336 .prepare = snd_intel8x0_pcm_prepare,
1337 .trigger = snd_intel8x0_pcm_trigger,
1338 .pointer = snd_intel8x0_pcm_pointer,
1339};
1340
1341static const struct snd_pcm_ops snd_intel8x0_capture2_ops = {
1342 .open = snd_intel8x0_capture2_open,
1343 .close = snd_intel8x0_capture2_close,
1344 .hw_params = snd_intel8x0_hw_params,
1345 .hw_free = snd_intel8x0_hw_free,
1346 .prepare = snd_intel8x0_pcm_prepare,
1347 .trigger = snd_intel8x0_pcm_trigger,
1348 .pointer = snd_intel8x0_pcm_pointer,
1349};
1350
1351static const struct snd_pcm_ops snd_intel8x0_spdif_ops = {
1352 .open = snd_intel8x0_spdif_open,
1353 .close = snd_intel8x0_spdif_close,
1354 .hw_params = snd_intel8x0_hw_params,
1355 .hw_free = snd_intel8x0_hw_free,
1356 .prepare = snd_intel8x0_pcm_prepare,
1357 .trigger = snd_intel8x0_pcm_trigger,
1358 .pointer = snd_intel8x0_pcm_pointer,
1359};
1360
1361static const struct snd_pcm_ops snd_intel8x0_ali_playback_ops = {
1362 .open = snd_intel8x0_playback_open,
1363 .close = snd_intel8x0_playback_close,
1364 .hw_params = snd_intel8x0_hw_params,
1365 .hw_free = snd_intel8x0_hw_free,
1366 .prepare = snd_intel8x0_pcm_prepare,
1367 .trigger = snd_intel8x0_ali_trigger,
1368 .pointer = snd_intel8x0_pcm_pointer,
1369};
1370
1371static const struct snd_pcm_ops snd_intel8x0_ali_capture_ops = {
1372 .open = snd_intel8x0_capture_open,
1373 .close = snd_intel8x0_capture_close,
1374 .hw_params = snd_intel8x0_hw_params,
1375 .hw_free = snd_intel8x0_hw_free,
1376 .prepare = snd_intel8x0_pcm_prepare,
1377 .trigger = snd_intel8x0_ali_trigger,
1378 .pointer = snd_intel8x0_pcm_pointer,
1379};
1380
1381static const struct snd_pcm_ops snd_intel8x0_ali_capture_mic_ops = {
1382 .open = snd_intel8x0_mic_open,
1383 .close = snd_intel8x0_mic_close,
1384 .hw_params = snd_intel8x0_hw_params,
1385 .hw_free = snd_intel8x0_hw_free,
1386 .prepare = snd_intel8x0_pcm_prepare,
1387 .trigger = snd_intel8x0_ali_trigger,
1388 .pointer = snd_intel8x0_pcm_pointer,
1389};
1390
1391static const struct snd_pcm_ops snd_intel8x0_ali_ac97spdifout_ops = {
1392 .open = snd_intel8x0_ali_ac97spdifout_open,
1393 .close = snd_intel8x0_ali_ac97spdifout_close,
1394 .hw_params = snd_intel8x0_hw_params,
1395 .hw_free = snd_intel8x0_hw_free,
1396 .prepare = snd_intel8x0_pcm_prepare,
1397 .trigger = snd_intel8x0_ali_trigger,
1398 .pointer = snd_intel8x0_pcm_pointer,
1399};
1400
1401#if 0 // NYI
1402static struct snd_pcm_ops snd_intel8x0_ali_spdifin_ops = {
1403 .open = snd_intel8x0_ali_spdifin_open,
1404 .close = snd_intel8x0_ali_spdifin_close,
1405 .hw_params = snd_intel8x0_hw_params,
1406 .hw_free = snd_intel8x0_hw_free,
1407 .prepare = snd_intel8x0_pcm_prepare,
1408 .trigger = snd_intel8x0_pcm_trigger,
1409 .pointer = snd_intel8x0_pcm_pointer,
1410};
1411
1412static struct snd_pcm_ops snd_intel8x0_ali_spdifout_ops = {
1413 .open = snd_intel8x0_ali_spdifout_open,
1414 .close = snd_intel8x0_ali_spdifout_close,
1415 .hw_params = snd_intel8x0_hw_params,
1416 .hw_free = snd_intel8x0_hw_free,
1417 .prepare = snd_intel8x0_pcm_prepare,
1418 .trigger = snd_intel8x0_pcm_trigger,
1419 .pointer = snd_intel8x0_pcm_pointer,
1420};
1421#endif // NYI
1422
1423struct ich_pcm_table {
1424 char *suffix;
1425 const struct snd_pcm_ops *playback_ops;
1426 const struct snd_pcm_ops *capture_ops;
1427 size_t prealloc_size;
1428 size_t prealloc_max_size;
1429 int ac97_idx;
1430};
1431
1432#define intel8x0_dma_type(chip) \
1433 ((chip)->fix_nocache ? SNDRV_DMA_TYPE_DEV_WC : SNDRV_DMA_TYPE_DEV)
1434
1435static int snd_intel8x0_pcm1(struct intel8x0 *chip, int device,
1436 const struct ich_pcm_table *rec)
1437{
1438 struct snd_pcm *pcm;
1439 int err;
1440 char name[32];
1441
1442 if (rec->suffix)
1443 sprintf(name, "Intel ICH - %s", rec->suffix);
1444 else
1445 strcpy(name, "Intel ICH");
1446 err = snd_pcm_new(chip->card, name, device,
1447 rec->playback_ops ? 1 : 0,
1448 rec->capture_ops ? 1 : 0, &pcm);
1449 if (err < 0)
1450 return err;
1451
1452 if (rec->playback_ops)
1453 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, rec->playback_ops);
1454 if (rec->capture_ops)
1455 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, rec->capture_ops);
1456
1457 pcm->private_data = chip;
1458 pcm->info_flags = 0;
1459 if (rec->suffix)
1460 sprintf(pcm->name, "%s - %s", chip->card->shortname, rec->suffix);
1461 else
1462 strcpy(pcm->name, chip->card->shortname);
1463 chip->pcm[device] = pcm;
1464
1465 snd_pcm_set_managed_buffer_all(pcm, intel8x0_dma_type(chip),
1466 &chip->pci->dev,
1467 rec->prealloc_size, rec->prealloc_max_size);
1468
1469 if (rec->playback_ops &&
1470 rec->playback_ops->open == snd_intel8x0_playback_open) {
1471 struct snd_pcm_chmap *chmap;
1472 int chs = 2;
1473 if (chip->multi8)
1474 chs = 8;
1475 else if (chip->multi6)
1476 chs = 6;
1477 else if (chip->multi4)
1478 chs = 4;
1479 err = snd_pcm_add_chmap_ctls(pcm, SNDRV_PCM_STREAM_PLAYBACK,
1480 snd_pcm_alt_chmaps, chs, 0,
1481 &chmap);
1482 if (err < 0)
1483 return err;
1484 chmap->channel_mask = SND_PCM_CHMAP_MASK_2468;
1485 chip->ac97[0]->chmaps[SNDRV_PCM_STREAM_PLAYBACK] = chmap;
1486 }
1487
1488 return 0;
1489}
1490
1491static const struct ich_pcm_table intel_pcms[] = {
1492 {
1493 .playback_ops = &snd_intel8x0_playback_ops,
1494 .capture_ops = &snd_intel8x0_capture_ops,
1495 .prealloc_size = 64 * 1024,
1496 .prealloc_max_size = 128 * 1024,
1497 },
1498 {
1499 .suffix = "MIC ADC",
1500 .capture_ops = &snd_intel8x0_capture_mic_ops,
1501 .prealloc_size = 0,
1502 .prealloc_max_size = 128 * 1024,
1503 .ac97_idx = ICHD_MIC,
1504 },
1505 {
1506 .suffix = "MIC2 ADC",
1507 .capture_ops = &snd_intel8x0_capture_mic2_ops,
1508 .prealloc_size = 0,
1509 .prealloc_max_size = 128 * 1024,
1510 .ac97_idx = ICHD_MIC2,
1511 },
1512 {
1513 .suffix = "ADC2",
1514 .capture_ops = &snd_intel8x0_capture2_ops,
1515 .prealloc_size = 0,
1516 .prealloc_max_size = 128 * 1024,
1517 .ac97_idx = ICHD_PCM2IN,
1518 },
1519 {
1520 .suffix = "IEC958",
1521 .playback_ops = &snd_intel8x0_spdif_ops,
1522 .prealloc_size = 64 * 1024,
1523 .prealloc_max_size = 128 * 1024,
1524 .ac97_idx = ICHD_SPBAR,
1525 },
1526};
1527
1528static const struct ich_pcm_table nforce_pcms[] = {
1529 {
1530 .playback_ops = &snd_intel8x0_playback_ops,
1531 .capture_ops = &snd_intel8x0_capture_ops,
1532 .prealloc_size = 64 * 1024,
1533 .prealloc_max_size = 128 * 1024,
1534 },
1535 {
1536 .suffix = "MIC ADC",
1537 .capture_ops = &snd_intel8x0_capture_mic_ops,
1538 .prealloc_size = 0,
1539 .prealloc_max_size = 128 * 1024,
1540 .ac97_idx = NVD_MIC,
1541 },
1542 {
1543 .suffix = "IEC958",
1544 .playback_ops = &snd_intel8x0_spdif_ops,
1545 .prealloc_size = 64 * 1024,
1546 .prealloc_max_size = 128 * 1024,
1547 .ac97_idx = NVD_SPBAR,
1548 },
1549};
1550
1551static const struct ich_pcm_table ali_pcms[] = {
1552 {
1553 .playback_ops = &snd_intel8x0_ali_playback_ops,
1554 .capture_ops = &snd_intel8x0_ali_capture_ops,
1555 .prealloc_size = 64 * 1024,
1556 .prealloc_max_size = 128 * 1024,
1557 },
1558 {
1559 .suffix = "MIC ADC",
1560 .capture_ops = &snd_intel8x0_ali_capture_mic_ops,
1561 .prealloc_size = 0,
1562 .prealloc_max_size = 128 * 1024,
1563 .ac97_idx = ALID_MIC,
1564 },
1565 {
1566 .suffix = "IEC958",
1567 .playback_ops = &snd_intel8x0_ali_ac97spdifout_ops,
1568 /* .capture_ops = &snd_intel8x0_ali_spdifin_ops, */
1569 .prealloc_size = 64 * 1024,
1570 .prealloc_max_size = 128 * 1024,
1571 .ac97_idx = ALID_AC97SPDIFOUT,
1572 },
1573#if 0 // NYI
1574 {
1575 .suffix = "HW IEC958",
1576 .playback_ops = &snd_intel8x0_ali_spdifout_ops,
1577 .prealloc_size = 64 * 1024,
1578 .prealloc_max_size = 128 * 1024,
1579 },
1580#endif
1581};
1582
1583static int snd_intel8x0_pcm(struct intel8x0 *chip)
1584{
1585 int i, tblsize, device, err;
1586 const struct ich_pcm_table *tbl, *rec;
1587
1588 switch (chip->device_type) {
1589 case DEVICE_INTEL_ICH4:
1590 tbl = intel_pcms;
1591 tblsize = ARRAY_SIZE(intel_pcms);
1592 if (spdif_aclink)
1593 tblsize--;
1594 break;
1595 case DEVICE_NFORCE:
1596 tbl = nforce_pcms;
1597 tblsize = ARRAY_SIZE(nforce_pcms);
1598 if (spdif_aclink)
1599 tblsize--;
1600 break;
1601 case DEVICE_ALI:
1602 tbl = ali_pcms;
1603 tblsize = ARRAY_SIZE(ali_pcms);
1604 break;
1605 default:
1606 tbl = intel_pcms;
1607 tblsize = 2;
1608 break;
1609 }
1610
1611 device = 0;
1612 for (i = 0; i < tblsize; i++) {
1613 rec = tbl + i;
1614 if (i > 0 && rec->ac97_idx) {
1615 /* activate PCM only when associated AC'97 codec */
1616 if (! chip->ichd[rec->ac97_idx].pcm)
1617 continue;
1618 }
1619 err = snd_intel8x0_pcm1(chip, device, rec);
1620 if (err < 0)
1621 return err;
1622 device++;
1623 }
1624
1625 chip->pcm_devs = device;
1626 return 0;
1627}
1628
1629
1630/*
1631 * Mixer part
1632 */
1633
1634static void snd_intel8x0_mixer_free_ac97_bus(struct snd_ac97_bus *bus)
1635{
1636 struct intel8x0 *chip = bus->private_data;
1637 chip->ac97_bus = NULL;
1638}
1639
1640static void snd_intel8x0_mixer_free_ac97(struct snd_ac97 *ac97)
1641{
1642 struct intel8x0 *chip = ac97->private_data;
1643 chip->ac97[ac97->num] = NULL;
1644}
1645
1646static const struct ac97_pcm ac97_pcm_defs[] = {
1647 /* front PCM */
1648 {
1649 .exclusive = 1,
1650 .r = { {
1651 .slots = (1 << AC97_SLOT_PCM_LEFT) |
1652 (1 << AC97_SLOT_PCM_RIGHT) |
1653 (1 << AC97_SLOT_PCM_CENTER) |
1654 (1 << AC97_SLOT_PCM_SLEFT) |
1655 (1 << AC97_SLOT_PCM_SRIGHT) |
1656 (1 << AC97_SLOT_LFE)
1657 },
1658 {
1659 .slots = (1 << AC97_SLOT_PCM_LEFT) |
1660 (1 << AC97_SLOT_PCM_RIGHT) |
1661 (1 << AC97_SLOT_PCM_LEFT_0) |
1662 (1 << AC97_SLOT_PCM_RIGHT_0)
1663 }
1664 }
1665 },
1666 /* PCM IN #1 */
1667 {
1668 .stream = 1,
1669 .exclusive = 1,
1670 .r = { {
1671 .slots = (1 << AC97_SLOT_PCM_LEFT) |
1672 (1 << AC97_SLOT_PCM_RIGHT)
1673 }
1674 }
1675 },
1676 /* MIC IN #1 */
1677 {
1678 .stream = 1,
1679 .exclusive = 1,
1680 .r = { {
1681 .slots = (1 << AC97_SLOT_MIC)
1682 }
1683 }
1684 },
1685 /* S/PDIF PCM */
1686 {
1687 .exclusive = 1,
1688 .spdif = 1,
1689 .r = { {
1690 .slots = (1 << AC97_SLOT_SPDIF_LEFT2) |
1691 (1 << AC97_SLOT_SPDIF_RIGHT2)
1692 }
1693 }
1694 },
1695 /* PCM IN #2 */
1696 {
1697 .stream = 1,
1698 .exclusive = 1,
1699 .r = { {
1700 .slots = (1 << AC97_SLOT_PCM_LEFT) |
1701 (1 << AC97_SLOT_PCM_RIGHT)
1702 }
1703 }
1704 },
1705 /* MIC IN #2 */
1706 {
1707 .stream = 1,
1708 .exclusive = 1,
1709 .r = { {
1710 .slots = (1 << AC97_SLOT_MIC)
1711 }
1712 }
1713 },
1714};
1715
1716static const struct ac97_quirk ac97_quirks[] = {
1717 {
1718 .subvendor = 0x0e11,
1719 .subdevice = 0x000e,
1720 .name = "Compaq Deskpro EN", /* AD1885 */
1721 .type = AC97_TUNE_HP_ONLY
1722 },
1723 {
1724 .subvendor = 0x0e11,
1725 .subdevice = 0x008a,
1726 .name = "Compaq Evo W4000", /* AD1885 */
1727 .type = AC97_TUNE_HP_ONLY
1728 },
1729 {
1730 .subvendor = 0x0e11,
1731 .subdevice = 0x00b8,
1732 .name = "Compaq Evo D510C",
1733 .type = AC97_TUNE_HP_ONLY
1734 },
1735 {
1736 .subvendor = 0x0e11,
1737 .subdevice = 0x0860,
1738 .name = "HP/Compaq nx7010",
1739 .type = AC97_TUNE_MUTE_LED
1740 },
1741 {
1742 .subvendor = 0x1014,
1743 .subdevice = 0x0534,
1744 .name = "ThinkPad X31",
1745 .type = AC97_TUNE_INV_EAPD
1746 },
1747 {
1748 .subvendor = 0x1014,
1749 .subdevice = 0x1f00,
1750 .name = "MS-9128",
1751 .type = AC97_TUNE_ALC_JACK
1752 },
1753 {
1754 .subvendor = 0x1014,
1755 .subdevice = 0x0267,
1756 .name = "IBM NetVista A30p", /* AD1981B */
1757 .type = AC97_TUNE_HP_ONLY
1758 },
1759 {
1760 .subvendor = 0x1025,
1761 .subdevice = 0x0082,
1762 .name = "Acer Travelmate 2310",
1763 .type = AC97_TUNE_HP_ONLY
1764 },
1765 {
1766 .subvendor = 0x1025,
1767 .subdevice = 0x0083,
1768 .name = "Acer Aspire 3003LCi",
1769 .type = AC97_TUNE_HP_ONLY
1770 },
1771 {
1772 .subvendor = 0x1028,
1773 .subdevice = 0x00d8,
1774 .name = "Dell Precision 530", /* AD1885 */
1775 .type = AC97_TUNE_HP_ONLY
1776 },
1777 {
1778 .subvendor = 0x1028,
1779 .subdevice = 0x010d,
1780 .name = "Dell", /* which model? AD1885 */
1781 .type = AC97_TUNE_HP_ONLY
1782 },
1783 {
1784 .subvendor = 0x1028,
1785 .subdevice = 0x0126,
1786 .name = "Dell Optiplex GX260", /* AD1981A */
1787 .type = AC97_TUNE_HP_ONLY
1788 },
1789 {
1790 .subvendor = 0x1028,
1791 .subdevice = 0x012c,
1792 .name = "Dell Precision 650", /* AD1981A */
1793 .type = AC97_TUNE_HP_ONLY
1794 },
1795 {
1796 .subvendor = 0x1028,
1797 .subdevice = 0x012d,
1798 .name = "Dell Precision 450", /* AD1981B*/
1799 .type = AC97_TUNE_HP_ONLY
1800 },
1801 {
1802 .subvendor = 0x1028,
1803 .subdevice = 0x0147,
1804 .name = "Dell", /* which model? AD1981B*/
1805 .type = AC97_TUNE_HP_ONLY
1806 },
1807 {
1808 .subvendor = 0x1028,
1809 .subdevice = 0x0151,
1810 .name = "Dell Optiplex GX270", /* AD1981B */
1811 .type = AC97_TUNE_HP_ONLY
1812 },
1813 {
1814 .subvendor = 0x1028,
1815 .subdevice = 0x014e,
1816 .name = "Dell D800", /* STAC9750/51 */
1817 .type = AC97_TUNE_HP_ONLY
1818 },
1819 {
1820 .subvendor = 0x1028,
1821 .subdevice = 0x0163,
1822 .name = "Dell Unknown", /* STAC9750/51 */
1823 .type = AC97_TUNE_HP_ONLY
1824 },
1825 {
1826 .subvendor = 0x1028,
1827 .subdevice = 0x016a,
1828 .name = "Dell Inspiron 8600", /* STAC9750/51 */
1829 .type = AC97_TUNE_HP_ONLY
1830 },
1831 {
1832 .subvendor = 0x1028,
1833 .subdevice = 0x0182,
1834 .name = "Dell Latitude D610", /* STAC9750/51 */
1835 .type = AC97_TUNE_HP_ONLY
1836 },
1837 {
1838 .subvendor = 0x1028,
1839 .subdevice = 0x0186,
1840 .name = "Dell Latitude D810", /* cf. Malone #41015 */
1841 .type = AC97_TUNE_HP_MUTE_LED
1842 },
1843 {
1844 .subvendor = 0x1028,
1845 .subdevice = 0x0188,
1846 .name = "Dell Inspiron 6000",
1847 .type = AC97_TUNE_HP_MUTE_LED /* cf. Malone #41015 */
1848 },
1849 {
1850 .subvendor = 0x1028,
1851 .subdevice = 0x0189,
1852 .name = "Dell Inspiron 9300",
1853 .type = AC97_TUNE_HP_MUTE_LED
1854 },
1855 {
1856 .subvendor = 0x1028,
1857 .subdevice = 0x0191,
1858 .name = "Dell Inspiron 8600",
1859 .type = AC97_TUNE_HP_ONLY
1860 },
1861 {
1862 .subvendor = 0x103c,
1863 .subdevice = 0x006d,
1864 .name = "HP zv5000",
1865 .type = AC97_TUNE_MUTE_LED /*AD1981B*/
1866 },
1867 { /* FIXME: which codec? */
1868 .subvendor = 0x103c,
1869 .subdevice = 0x00c3,
1870 .name = "HP xw6000",
1871 .type = AC97_TUNE_HP_ONLY
1872 },
1873 {
1874 .subvendor = 0x103c,
1875 .subdevice = 0x088c,
1876 .name = "HP nc8000",
1877 .type = AC97_TUNE_HP_MUTE_LED
1878 },
1879 {
1880 .subvendor = 0x103c,
1881 .subdevice = 0x0890,
1882 .name = "HP nc6000",
1883 .type = AC97_TUNE_MUTE_LED
1884 },
1885 {
1886 .subvendor = 0x103c,
1887 .subdevice = 0x129d,
1888 .name = "HP xw8000",
1889 .type = AC97_TUNE_HP_ONLY
1890 },
1891 {
1892 .subvendor = 0x103c,
1893 .subdevice = 0x0938,
1894 .name = "HP nc4200",
1895 .type = AC97_TUNE_HP_MUTE_LED
1896 },
1897 {
1898 .subvendor = 0x103c,
1899 .subdevice = 0x099c,
1900 .name = "HP nx6110/nc6120",
1901 .type = AC97_TUNE_HP_MUTE_LED
1902 },
1903 {
1904 .subvendor = 0x103c,
1905 .subdevice = 0x0944,
1906 .name = "HP nc6220",
1907 .type = AC97_TUNE_HP_MUTE_LED
1908 },
1909 {
1910 .subvendor = 0x103c,
1911 .subdevice = 0x0934,
1912 .name = "HP nc8220",
1913 .type = AC97_TUNE_HP_MUTE_LED
1914 },
1915 {
1916 .subvendor = 0x103c,
1917 .subdevice = 0x12f1,
1918 .name = "HP xw8200", /* AD1981B*/
1919 .type = AC97_TUNE_HP_ONLY
1920 },
1921 {
1922 .subvendor = 0x103c,
1923 .subdevice = 0x12f2,
1924 .name = "HP xw6200",
1925 .type = AC97_TUNE_HP_ONLY
1926 },
1927 {
1928 .subvendor = 0x103c,
1929 .subdevice = 0x3008,
1930 .name = "HP xw4200", /* AD1981B*/
1931 .type = AC97_TUNE_HP_ONLY
1932 },
1933 {
1934 .subvendor = 0x104d,
1935 .subdevice = 0x8144,
1936 .name = "Sony",
1937 .type = AC97_TUNE_INV_EAPD
1938 },
1939 {
1940 .subvendor = 0x104d,
1941 .subdevice = 0x8197,
1942 .name = "Sony S1XP",
1943 .type = AC97_TUNE_INV_EAPD
1944 },
1945 {
1946 .subvendor = 0x104d,
1947 .subdevice = 0x81c0,
1948 .name = "Sony VAIO VGN-T350P", /*AD1981B*/
1949 .type = AC97_TUNE_INV_EAPD
1950 },
1951 {
1952 .subvendor = 0x104d,
1953 .subdevice = 0x81c5,
1954 .name = "Sony VAIO VGN-B1VP", /*AD1981B*/
1955 .type = AC97_TUNE_INV_EAPD
1956 },
1957 {
1958 .subvendor = 0x1043,
1959 .subdevice = 0x80f3,
1960 .name = "ASUS ICH5/AD1985",
1961 .type = AC97_TUNE_AD_SHARING
1962 },
1963 {
1964 .subvendor = 0x10cf,
1965 .subdevice = 0x11c3,
1966 .name = "Fujitsu-Siemens E4010",
1967 .type = AC97_TUNE_HP_ONLY
1968 },
1969 {
1970 .subvendor = 0x10cf,
1971 .subdevice = 0x1225,
1972 .name = "Fujitsu-Siemens T3010",
1973 .type = AC97_TUNE_HP_ONLY
1974 },
1975 {
1976 .subvendor = 0x10cf,
1977 .subdevice = 0x1253,
1978 .name = "Fujitsu S6210", /* STAC9750/51 */
1979 .type = AC97_TUNE_HP_ONLY
1980 },
1981 {
1982 .subvendor = 0x10cf,
1983 .subdevice = 0x127d,
1984 .name = "Fujitsu Lifebook P7010",
1985 .type = AC97_TUNE_HP_ONLY
1986 },
1987 {
1988 .subvendor = 0x10cf,
1989 .subdevice = 0x127e,
1990 .name = "Fujitsu Lifebook C1211D",
1991 .type = AC97_TUNE_HP_ONLY
1992 },
1993 {
1994 .subvendor = 0x10cf,
1995 .subdevice = 0x12ec,
1996 .name = "Fujitsu-Siemens 4010",
1997 .type = AC97_TUNE_HP_ONLY
1998 },
1999 {
2000 .subvendor = 0x10cf,
2001 .subdevice = 0x12f2,
2002 .name = "Fujitsu-Siemens Celsius H320",
2003 .type = AC97_TUNE_SWAP_HP
2004 },
2005 {
2006 .subvendor = 0x10f1,
2007 .subdevice = 0x2665,
2008 .name = "Fujitsu-Siemens Celsius", /* AD1981? */
2009 .type = AC97_TUNE_HP_ONLY
2010 },
2011 {
2012 .subvendor = 0x10f1,
2013 .subdevice = 0x2885,
2014 .name = "AMD64 Mobo", /* ALC650 */
2015 .type = AC97_TUNE_HP_ONLY
2016 },
2017 {
2018 .subvendor = 0x10f1,
2019 .subdevice = 0x2895,
2020 .name = "Tyan Thunder K8WE",
2021 .type = AC97_TUNE_HP_ONLY
2022 },
2023 {
2024 .subvendor = 0x10f7,
2025 .subdevice = 0x834c,
2026 .name = "Panasonic CF-R4",
2027 .type = AC97_TUNE_HP_ONLY,
2028 },
2029 {
2030 .subvendor = 0x110a,
2031 .subdevice = 0x0056,
2032 .name = "Fujitsu-Siemens Scenic", /* AD1981? */
2033 .type = AC97_TUNE_HP_ONLY
2034 },
2035 {
2036 .subvendor = 0x11d4,
2037 .subdevice = 0x5375,
2038 .name = "ADI AD1985 (discrete)",
2039 .type = AC97_TUNE_HP_ONLY
2040 },
2041 {
2042 .subvendor = 0x1462,
2043 .subdevice = 0x5470,
2044 .name = "MSI P4 ATX 645 Ultra",
2045 .type = AC97_TUNE_HP_ONLY
2046 },
2047 {
2048 .subvendor = 0x161f,
2049 .subdevice = 0x202f,
2050 .name = "Gateway M520",
2051 .type = AC97_TUNE_INV_EAPD
2052 },
2053 {
2054 .subvendor = 0x161f,
2055 .subdevice = 0x203a,
2056 .name = "Gateway 4525GZ", /* AD1981B */
2057 .type = AC97_TUNE_INV_EAPD
2058 },
2059 {
2060 .subvendor = 0x1734,
2061 .subdevice = 0x0088,
2062 .name = "Fujitsu-Siemens D1522", /* AD1981 */
2063 .type = AC97_TUNE_HP_ONLY
2064 },
2065 {
2066 .subvendor = 0x8086,
2067 .subdevice = 0x2000,
2068 .mask = 0xfff0,
2069 .name = "Intel ICH5/AD1985",
2070 .type = AC97_TUNE_AD_SHARING
2071 },
2072 {
2073 .subvendor = 0x8086,
2074 .subdevice = 0x4000,
2075 .mask = 0xfff0,
2076 .name = "Intel ICH5/AD1985",
2077 .type = AC97_TUNE_AD_SHARING
2078 },
2079 {
2080 .subvendor = 0x8086,
2081 .subdevice = 0x4856,
2082 .name = "Intel D845WN (82801BA)",
2083 .type = AC97_TUNE_SWAP_HP
2084 },
2085 {
2086 .subvendor = 0x8086,
2087 .subdevice = 0x4d44,
2088 .name = "Intel D850EMV2", /* AD1885 */
2089 .type = AC97_TUNE_HP_ONLY
2090 },
2091 {
2092 .subvendor = 0x8086,
2093 .subdevice = 0x4d56,
2094 .name = "Intel ICH/AD1885",
2095 .type = AC97_TUNE_HP_ONLY
2096 },
2097 {
2098 .subvendor = 0x8086,
2099 .subdevice = 0x6000,
2100 .mask = 0xfff0,
2101 .name = "Intel ICH5/AD1985",
2102 .type = AC97_TUNE_AD_SHARING
2103 },
2104 {
2105 .subvendor = 0x8086,
2106 .subdevice = 0xe000,
2107 .mask = 0xfff0,
2108 .name = "Intel ICH5/AD1985",
2109 .type = AC97_TUNE_AD_SHARING
2110 },
2111#if 0 /* FIXME: this seems wrong on most boards */
2112 {
2113 .subvendor = 0x8086,
2114 .subdevice = 0xa000,
2115 .mask = 0xfff0,
2116 .name = "Intel ICH5/AD1985",
2117 .type = AC97_TUNE_HP_ONLY
2118 },
2119#endif
2120 {0} /* terminator */
2121};
2122
2123static int snd_intel8x0_mixer(struct intel8x0 *chip, int ac97_clock,
2124 const char *quirk_override)
2125{
2126 struct snd_ac97_bus *pbus;
2127 struct snd_ac97_template ac97;
2128 int err;
2129 unsigned int i, codecs;
2130 unsigned int glob_sta = 0;
2131 const struct snd_ac97_bus_ops *ops;
2132 static const struct snd_ac97_bus_ops standard_bus_ops = {
2133 .write = snd_intel8x0_codec_write,
2134 .read = snd_intel8x0_codec_read,
2135 };
2136 static const struct snd_ac97_bus_ops ali_bus_ops = {
2137 .write = snd_intel8x0_ali_codec_write,
2138 .read = snd_intel8x0_ali_codec_read,
2139 };
2140
2141 chip->spdif_idx = -1; /* use PCMOUT (or disabled) */
2142 if (!spdif_aclink) {
2143 switch (chip->device_type) {
2144 case DEVICE_NFORCE:
2145 chip->spdif_idx = NVD_SPBAR;
2146 break;
2147 case DEVICE_ALI:
2148 chip->spdif_idx = ALID_AC97SPDIFOUT;
2149 break;
2150 case DEVICE_INTEL_ICH4:
2151 chip->spdif_idx = ICHD_SPBAR;
2152 break;
2153 }
2154 }
2155
2156 chip->in_ac97_init = 1;
2157
2158 memset(&ac97, 0, sizeof(ac97));
2159 ac97.private_data = chip;
2160 ac97.private_free = snd_intel8x0_mixer_free_ac97;
2161 ac97.scaps = AC97_SCAP_SKIP_MODEM | AC97_SCAP_POWER_SAVE;
2162 if (chip->xbox)
2163 ac97.scaps |= AC97_SCAP_DETECT_BY_VENDOR;
2164 if (chip->device_type != DEVICE_ALI) {
2165 glob_sta = igetdword(chip, ICHREG(GLOB_STA));
2166 ops = &standard_bus_ops;
2167 chip->in_sdin_init = 1;
2168 codecs = 0;
2169 for (i = 0; i < chip->max_codecs; i++) {
2170 if (! (glob_sta & chip->codec_bit[i]))
2171 continue;
2172 if (chip->device_type == DEVICE_INTEL_ICH4) {
2173 snd_intel8x0_codec_read_test(chip, codecs);
2174 chip->ac97_sdin[codecs] =
2175 igetbyte(chip, ICHREG(SDM)) & ICH_LDI_MASK;
2176 if (snd_BUG_ON(chip->ac97_sdin[codecs] >= 3))
2177 chip->ac97_sdin[codecs] = 0;
2178 } else
2179 chip->ac97_sdin[codecs] = i;
2180 codecs++;
2181 }
2182 chip->in_sdin_init = 0;
2183 if (! codecs)
2184 codecs = 1;
2185 } else {
2186 ops = &ali_bus_ops;
2187 codecs = 1;
2188 /* detect the secondary codec */
2189 for (i = 0; i < 100; i++) {
2190 unsigned int reg = igetdword(chip, ICHREG(ALI_RTSR));
2191 if (reg & 0x40) {
2192 codecs = 2;
2193 break;
2194 }
2195 iputdword(chip, ICHREG(ALI_RTSR), reg | 0x40);
2196 udelay(1);
2197 }
2198 }
2199 err = snd_ac97_bus(chip->card, 0, ops, chip, &pbus);
2200 if (err < 0)
2201 goto __err;
2202 pbus->private_free = snd_intel8x0_mixer_free_ac97_bus;
2203 if (ac97_clock >= 8000 && ac97_clock <= 48000)
2204 pbus->clock = ac97_clock;
2205 /* FIXME: my test board doesn't work well with VRA... */
2206 if (chip->device_type == DEVICE_ALI)
2207 pbus->no_vra = 1;
2208 else
2209 pbus->dra = 1;
2210 chip->ac97_bus = pbus;
2211 chip->ncodecs = codecs;
2212
2213 ac97.pci = chip->pci;
2214 for (i = 0; i < codecs; i++) {
2215 ac97.num = i;
2216 err = snd_ac97_mixer(pbus, &ac97, &chip->ac97[i]);
2217 if (err < 0) {
2218 if (err != -EACCES)
2219 dev_err(chip->card->dev,
2220 "Unable to initialize codec #%d\n", i);
2221 if (i == 0)
2222 goto __err;
2223 }
2224 }
2225 /* tune up the primary codec */
2226 snd_ac97_tune_hardware(chip->ac97[0], ac97_quirks, quirk_override);
2227 /* enable separate SDINs for ICH4 */
2228 if (chip->device_type == DEVICE_INTEL_ICH4)
2229 pbus->isdin = 1;
2230 /* find the available PCM streams */
2231 i = ARRAY_SIZE(ac97_pcm_defs);
2232 if (chip->device_type != DEVICE_INTEL_ICH4)
2233 i -= 2; /* do not allocate PCM2IN and MIC2 */
2234 if (chip->spdif_idx < 0)
2235 i--; /* do not allocate S/PDIF */
2236 err = snd_ac97_pcm_assign(pbus, i, ac97_pcm_defs);
2237 if (err < 0)
2238 goto __err;
2239 chip->ichd[ICHD_PCMOUT].pcm = &pbus->pcms[0];
2240 chip->ichd[ICHD_PCMIN].pcm = &pbus->pcms[1];
2241 chip->ichd[ICHD_MIC].pcm = &pbus->pcms[2];
2242 if (chip->spdif_idx >= 0)
2243 chip->ichd[chip->spdif_idx].pcm = &pbus->pcms[3];
2244 if (chip->device_type == DEVICE_INTEL_ICH4) {
2245 chip->ichd[ICHD_PCM2IN].pcm = &pbus->pcms[4];
2246 chip->ichd[ICHD_MIC2].pcm = &pbus->pcms[5];
2247 }
2248 /* enable separate SDINs for ICH4 */
2249 if (chip->device_type == DEVICE_INTEL_ICH4) {
2250 struct ac97_pcm *pcm = chip->ichd[ICHD_PCM2IN].pcm;
2251 u8 tmp = igetbyte(chip, ICHREG(SDM));
2252 tmp &= ~(ICH_DI2L_MASK|ICH_DI1L_MASK);
2253 if (pcm) {
2254 tmp |= ICH_SE; /* steer enable for multiple SDINs */
2255 tmp |= chip->ac97_sdin[0] << ICH_DI1L_SHIFT;
2256 for (i = 1; i < 4; i++) {
2257 if (pcm->r[0].codec[i]) {
2258 tmp |= chip->ac97_sdin[pcm->r[0].codec[1]->num] << ICH_DI2L_SHIFT;
2259 break;
2260 }
2261 }
2262 } else {
2263 tmp &= ~ICH_SE; /* steer disable */
2264 }
2265 iputbyte(chip, ICHREG(SDM), tmp);
2266 }
2267 if (pbus->pcms[0].r[0].slots & (1 << AC97_SLOT_PCM_SLEFT)) {
2268 chip->multi4 = 1;
2269 if (pbus->pcms[0].r[0].slots & (1 << AC97_SLOT_LFE)) {
2270 chip->multi6 = 1;
2271 if (chip->ac97[0]->flags & AC97_HAS_8CH)
2272 chip->multi8 = 1;
2273 }
2274 }
2275 if (pbus->pcms[0].r[1].rslots[0]) {
2276 chip->dra = 1;
2277 }
2278 if (chip->device_type == DEVICE_INTEL_ICH4) {
2279 if ((igetdword(chip, ICHREG(GLOB_STA)) & ICH_SAMPLE_CAP) == ICH_SAMPLE_16_20)
2280 chip->smp20bit = 1;
2281 }
2282 if (chip->device_type == DEVICE_NFORCE && !spdif_aclink) {
2283 /* 48kHz only */
2284 chip->ichd[chip->spdif_idx].pcm->rates = SNDRV_PCM_RATE_48000;
2285 }
2286 if (chip->device_type == DEVICE_INTEL_ICH4 && !spdif_aclink) {
2287 /* use slot 10/11 for SPDIF */
2288 u32 val;
2289 val = igetdword(chip, ICHREG(GLOB_CNT)) & ~ICH_PCM_SPDIF_MASK;
2290 val |= ICH_PCM_SPDIF_1011;
2291 iputdword(chip, ICHREG(GLOB_CNT), val);
2292 snd_ac97_update_bits(chip->ac97[0], AC97_EXTENDED_STATUS, 0x03 << 4, 0x03 << 4);
2293 }
2294 chip->in_ac97_init = 0;
2295 return 0;
2296
2297 __err:
2298 /* clear the cold-reset bit for the next chance */
2299 if (chip->device_type != DEVICE_ALI)
2300 iputdword(chip, ICHREG(GLOB_CNT),
2301 igetdword(chip, ICHREG(GLOB_CNT)) & ~ICH_AC97COLD);
2302 return err;
2303}
2304
2305
2306/*
2307 *
2308 */
2309
2310static void do_ali_reset(struct intel8x0 *chip)
2311{
2312 iputdword(chip, ICHREG(ALI_SCR), ICH_ALI_SC_RESET);
2313 iputdword(chip, ICHREG(ALI_FIFOCR1), 0x83838383);
2314 iputdword(chip, ICHREG(ALI_FIFOCR2), 0x83838383);
2315 iputdword(chip, ICHREG(ALI_FIFOCR3), 0x83838383);
2316 iputdword(chip, ICHREG(ALI_INTERFACECR),
2317 ICH_ALI_IF_PI|ICH_ALI_IF_PO);
2318 iputdword(chip, ICHREG(ALI_INTERRUPTCR), 0x00000000);
2319 iputdword(chip, ICHREG(ALI_INTERRUPTSR), 0x00000000);
2320}
2321
2322#ifdef CONFIG_SND_AC97_POWER_SAVE
2323static const struct snd_pci_quirk ich_chip_reset_mode[] = {
2324 SND_PCI_QUIRK(0x1014, 0x051f, "Thinkpad R32", 1),
2325 {0} /* end */
2326};
2327
2328static int snd_intel8x0_ich_chip_cold_reset(struct intel8x0 *chip)
2329{
2330 unsigned int cnt;
2331 /* ACLink on, 2 channels */
2332
2333 if (snd_pci_quirk_lookup(chip->pci, ich_chip_reset_mode))
2334 return -EIO;
2335
2336 cnt = igetdword(chip, ICHREG(GLOB_CNT));
2337 cnt &= ~(ICH_ACLINK | ICH_PCM_246_MASK);
2338
2339 /* do cold reset - the full ac97 powerdown may leave the controller
2340 * in a warm state but actually it cannot communicate with the codec.
2341 */
2342 iputdword(chip, ICHREG(GLOB_CNT), cnt & ~ICH_AC97COLD);
2343 cnt = igetdword(chip, ICHREG(GLOB_CNT));
2344 udelay(10);
2345 iputdword(chip, ICHREG(GLOB_CNT), cnt | ICH_AC97COLD);
2346 msleep(1);
2347 return 0;
2348}
2349#define snd_intel8x0_ich_chip_can_cold_reset(chip) \
2350 (!snd_pci_quirk_lookup(chip->pci, ich_chip_reset_mode))
2351#else
2352#define snd_intel8x0_ich_chip_cold_reset(chip) 0
2353#define snd_intel8x0_ich_chip_can_cold_reset(chip) (0)
2354#endif
2355
2356static int snd_intel8x0_ich_chip_reset(struct intel8x0 *chip)
2357{
2358 unsigned long end_time;
2359 unsigned int cnt;
2360 /* ACLink on, 2 channels */
2361 cnt = igetdword(chip, ICHREG(GLOB_CNT));
2362 cnt &= ~(ICH_ACLINK | ICH_PCM_246_MASK);
2363 /* finish cold or do warm reset */
2364 cnt |= (cnt & ICH_AC97COLD) == 0 ? ICH_AC97COLD : ICH_AC97WARM;
2365 iputdword(chip, ICHREG(GLOB_CNT), cnt);
2366 end_time = (jiffies + (HZ / 4)) + 1;
2367 do {
2368 if ((igetdword(chip, ICHREG(GLOB_CNT)) & ICH_AC97WARM) == 0)
2369 return 0;
2370 schedule_timeout_uninterruptible(1);
2371 } while (time_after_eq(end_time, jiffies));
2372 dev_err(chip->card->dev, "AC'97 warm reset still in progress? [0x%x]\n",
2373 igetdword(chip, ICHREG(GLOB_CNT)));
2374 return -EIO;
2375}
2376
2377static int snd_intel8x0_ich_chip_init(struct intel8x0 *chip, int probing)
2378{
2379 unsigned long end_time;
2380 unsigned int status, nstatus;
2381 unsigned int cnt;
2382 int err;
2383
2384 /* put logic to right state */
2385 /* first clear status bits */
2386 status = ICH_RCS | ICH_MCINT | ICH_POINT | ICH_PIINT;
2387 if (chip->device_type == DEVICE_NFORCE)
2388 status |= ICH_NVSPINT;
2389 cnt = igetdword(chip, ICHREG(GLOB_STA));
2390 iputdword(chip, ICHREG(GLOB_STA), cnt & status);
2391
2392#ifdef CONFIG_SND_AC97_POWER_SAVE
2393 if (snd_intel8x0_ich_chip_can_cold_reset(chip))
2394 err = snd_intel8x0_ich_chip_cold_reset(chip);
2395 else
2396#endif
2397 err = snd_intel8x0_ich_chip_reset(chip);
2398 if (err < 0)
2399 return err;
2400
2401 if (probing) {
2402 /* wait for any codec ready status.
2403 * Once it becomes ready it should remain ready
2404 * as long as we do not disable the ac97 link.
2405 */
2406 end_time = jiffies + HZ;
2407 do {
2408 status = igetdword(chip, ICHREG(GLOB_STA)) &
2409 chip->codec_isr_bits;
2410 if (status)
2411 break;
2412 schedule_timeout_uninterruptible(1);
2413 } while (time_after_eq(end_time, jiffies));
2414 if (! status) {
2415 /* no codec is found */
2416 dev_err(chip->card->dev,
2417 "codec_ready: codec is not ready [0x%x]\n",
2418 igetdword(chip, ICHREG(GLOB_STA)));
2419 return -EIO;
2420 }
2421
2422 /* wait for other codecs ready status. */
2423 end_time = jiffies + HZ / 4;
2424 while (status != chip->codec_isr_bits &&
2425 time_after_eq(end_time, jiffies)) {
2426 schedule_timeout_uninterruptible(1);
2427 status |= igetdword(chip, ICHREG(GLOB_STA)) &
2428 chip->codec_isr_bits;
2429 }
2430
2431 } else {
2432 /* resume phase */
2433 int i;
2434 status = 0;
2435 for (i = 0; i < chip->ncodecs; i++)
2436 if (chip->ac97[i])
2437 status |= chip->codec_bit[chip->ac97_sdin[i]];
2438 /* wait until all the probed codecs are ready */
2439 end_time = jiffies + HZ;
2440 do {
2441 nstatus = igetdword(chip, ICHREG(GLOB_STA)) &
2442 chip->codec_isr_bits;
2443 if (status == nstatus)
2444 break;
2445 schedule_timeout_uninterruptible(1);
2446 } while (time_after_eq(end_time, jiffies));
2447 }
2448
2449 if (chip->device_type == DEVICE_SIS) {
2450 /* unmute the output on SIS7012 */
2451 iputword(chip, 0x4c, igetword(chip, 0x4c) | 1);
2452 }
2453 if (chip->device_type == DEVICE_NFORCE && !spdif_aclink) {
2454 /* enable SPDIF interrupt */
2455 unsigned int val;
2456 pci_read_config_dword(chip->pci, 0x4c, &val);
2457 val |= 0x1000000;
2458 pci_write_config_dword(chip->pci, 0x4c, val);
2459 }
2460 return 0;
2461}
2462
2463static int snd_intel8x0_ali_chip_init(struct intel8x0 *chip, int probing)
2464{
2465 u32 reg;
2466 int i = 0;
2467
2468 reg = igetdword(chip, ICHREG(ALI_SCR));
2469 if ((reg & 2) == 0) /* Cold required */
2470 reg |= 2;
2471 else
2472 reg |= 1; /* Warm */
2473 reg &= ~0x80000000; /* ACLink on */
2474 iputdword(chip, ICHREG(ALI_SCR), reg);
2475
2476 for (i = 0; i < HZ / 2; i++) {
2477 if (! (igetdword(chip, ICHREG(ALI_INTERRUPTSR)) & ALI_INT_GPIO))
2478 goto __ok;
2479 schedule_timeout_uninterruptible(1);
2480 }
2481 dev_err(chip->card->dev, "AC'97 reset failed.\n");
2482 if (probing)
2483 return -EIO;
2484
2485 __ok:
2486 for (i = 0; i < HZ / 2; i++) {
2487 reg = igetdword(chip, ICHREG(ALI_RTSR));
2488 if (reg & 0x80) /* primary codec */
2489 break;
2490 iputdword(chip, ICHREG(ALI_RTSR), reg | 0x80);
2491 schedule_timeout_uninterruptible(1);
2492 }
2493
2494 do_ali_reset(chip);
2495 return 0;
2496}
2497
2498static int snd_intel8x0_chip_init(struct intel8x0 *chip, int probing)
2499{
2500 unsigned int i, timeout;
2501 int err;
2502
2503 if (chip->device_type != DEVICE_ALI) {
2504 err = snd_intel8x0_ich_chip_init(chip, probing);
2505 if (err < 0)
2506 return err;
2507 iagetword(chip, 0); /* clear semaphore flag */
2508 } else {
2509 err = snd_intel8x0_ali_chip_init(chip, probing);
2510 if (err < 0)
2511 return err;
2512 }
2513
2514 /* disable interrupts */
2515 for (i = 0; i < chip->bdbars_count; i++)
2516 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, 0x00);
2517 /* reset channels */
2518 for (i = 0; i < chip->bdbars_count; i++)
2519 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, ICH_RESETREGS);
2520 for (i = 0; i < chip->bdbars_count; i++) {
2521 timeout = 100000;
2522 while (--timeout != 0) {
2523 if ((igetbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset) & ICH_RESETREGS) == 0)
2524 break;
2525 }
2526 if (timeout == 0)
2527 dev_err(chip->card->dev, "reset of registers failed?\n");
2528 }
2529 /* initialize Buffer Descriptor Lists */
2530 for (i = 0; i < chip->bdbars_count; i++)
2531 iputdword(chip, ICH_REG_OFF_BDBAR + chip->ichd[i].reg_offset,
2532 chip->ichd[i].bdbar_addr);
2533 return 0;
2534}
2535
2536static void snd_intel8x0_free(struct snd_card *card)
2537{
2538 struct intel8x0 *chip = card->private_data;
2539 unsigned int i;
2540
2541 if (chip->irq < 0)
2542 goto __hw_end;
2543 /* disable interrupts */
2544 for (i = 0; i < chip->bdbars_count; i++)
2545 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, 0x00);
2546 /* reset channels */
2547 for (i = 0; i < chip->bdbars_count; i++)
2548 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, ICH_RESETREGS);
2549 if (chip->device_type == DEVICE_NFORCE && !spdif_aclink) {
2550 /* stop the spdif interrupt */
2551 unsigned int val;
2552 pci_read_config_dword(chip->pci, 0x4c, &val);
2553 val &= ~0x1000000;
2554 pci_write_config_dword(chip->pci, 0x4c, val);
2555 }
2556 /* --- */
2557
2558 __hw_end:
2559 if (chip->irq >= 0)
2560 free_irq(chip->irq, chip);
2561}
2562
2563#ifdef CONFIG_PM_SLEEP
2564/*
2565 * power management
2566 */
2567static int intel8x0_suspend(struct device *dev)
2568{
2569 struct snd_card *card = dev_get_drvdata(dev);
2570 struct intel8x0 *chip = card->private_data;
2571 int i;
2572
2573 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
2574 for (i = 0; i < chip->ncodecs; i++)
2575 snd_ac97_suspend(chip->ac97[i]);
2576 if (chip->device_type == DEVICE_INTEL_ICH4)
2577 chip->sdm_saved = igetbyte(chip, ICHREG(SDM));
2578
2579 if (chip->irq >= 0) {
2580 free_irq(chip->irq, chip);
2581 chip->irq = -1;
2582 card->sync_irq = -1;
2583 }
2584 return 0;
2585}
2586
2587static int intel8x0_resume(struct device *dev)
2588{
2589 struct pci_dev *pci = to_pci_dev(dev);
2590 struct snd_card *card = dev_get_drvdata(dev);
2591 struct intel8x0 *chip = card->private_data;
2592 int i;
2593
2594 snd_intel8x0_chip_init(chip, 0);
2595 if (request_irq(pci->irq, snd_intel8x0_interrupt,
2596 IRQF_SHARED, KBUILD_MODNAME, chip)) {
2597 dev_err(dev, "unable to grab IRQ %d, disabling device\n",
2598 pci->irq);
2599 snd_card_disconnect(card);
2600 return -EIO;
2601 }
2602 chip->irq = pci->irq;
2603 card->sync_irq = chip->irq;
2604
2605 /* re-initialize mixer stuff */
2606 if (chip->device_type == DEVICE_INTEL_ICH4 && !spdif_aclink) {
2607 /* enable separate SDINs for ICH4 */
2608 iputbyte(chip, ICHREG(SDM), chip->sdm_saved);
2609 /* use slot 10/11 for SPDIF */
2610 iputdword(chip, ICHREG(GLOB_CNT),
2611 (igetdword(chip, ICHREG(GLOB_CNT)) & ~ICH_PCM_SPDIF_MASK) |
2612 ICH_PCM_SPDIF_1011);
2613 }
2614
2615 for (i = 0; i < chip->ncodecs; i++)
2616 snd_ac97_resume(chip->ac97[i]);
2617
2618 /* resume status */
2619 for (i = 0; i < chip->bdbars_count; i++) {
2620 struct ichdev *ichdev = &chip->ichd[i];
2621 unsigned long port = ichdev->reg_offset;
2622 if (! ichdev->substream || ! ichdev->suspended)
2623 continue;
2624 if (ichdev->ichd == ICHD_PCMOUT)
2625 snd_intel8x0_setup_pcm_out(chip, ichdev->substream->runtime);
2626 iputdword(chip, port + ICH_REG_OFF_BDBAR, ichdev->bdbar_addr);
2627 iputbyte(chip, port + ICH_REG_OFF_LVI, ichdev->lvi);
2628 iputbyte(chip, port + ICH_REG_OFF_CIV, ichdev->civ);
2629 iputbyte(chip, port + ichdev->roff_sr, ICH_FIFOE | ICH_BCIS | ICH_LVBCI);
2630 }
2631
2632 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
2633 return 0;
2634}
2635
2636static SIMPLE_DEV_PM_OPS(intel8x0_pm, intel8x0_suspend, intel8x0_resume);
2637#define INTEL8X0_PM_OPS &intel8x0_pm
2638#else
2639#define INTEL8X0_PM_OPS NULL
2640#endif /* CONFIG_PM_SLEEP */
2641
2642#define INTEL8X0_TESTBUF_SIZE 32768 /* enough large for one shot */
2643
2644static void intel8x0_measure_ac97_clock(struct intel8x0 *chip)
2645{
2646 struct snd_pcm_substream *subs;
2647 struct ichdev *ichdev;
2648 unsigned long port;
2649 unsigned long pos, pos1, t;
2650 int civ, timeout = 1000, attempt = 1;
2651#ifndef TARGET_OS2
2652 ktime_t start_time, stop_time;
2653#else
2654 struct timespec start_time, stop_time;
2655#endif
2656
2657 if (chip->ac97_bus->clock != 48000)
2658 return; /* specified in module option */
2659 if (chip->inside_vm && !ac97_clock)
2660 return; /* no measurement on VM */
2661
2662 __again:
2663 subs = chip->pcm[0]->streams[0].substream;
2664 if (! subs || subs->dma_buffer.bytes < INTEL8X0_TESTBUF_SIZE) {
2665 dev_warn(chip->card->dev,
2666 "no playback buffer allocated - aborting measure ac97 clock\n");
2667 return;
2668 }
2669 ichdev = &chip->ichd[ICHD_PCMOUT];
2670 ichdev->physbuf = subs->dma_buffer.addr;
2671 ichdev->size = ichdev->fragsize = INTEL8X0_TESTBUF_SIZE;
2672 ichdev->substream = NULL; /* don't process interrupts */
2673
2674 /* set rate */
2675 if (snd_ac97_set_rate(chip->ac97[0], AC97_PCM_FRONT_DAC_RATE, 48000) < 0) {
2676 dev_err(chip->card->dev, "cannot set ac97 rate: clock = %d\n",
2677 chip->ac97_bus->clock);
2678 return;
2679 }
2680 snd_intel8x0_setup_periods(chip, ichdev);
2681 port = ichdev->reg_offset;
2682 spin_lock_irq(&chip->reg_lock);
2683 chip->in_measurement = 1;
2684 /* trigger */
2685 if (chip->device_type != DEVICE_ALI)
2686 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_IOCE | ICH_STARTBM);
2687 else {
2688 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_IOCE);
2689 iputdword(chip, ICHREG(ALI_DMACR), 1 << ichdev->ali_slot);
2690 }
2691#ifndef TARGET_OS2
2692 start_time = ktime_get();
2693#else
2694 do_posix_clock_monotonic_gettime(&start_time);
2695#endif
2696 spin_unlock_irq(&chip->reg_lock);
2697 msleep(50);
2698 spin_lock_irq(&chip->reg_lock);
2699 /* check the position */
2700 do {
2701 civ = igetbyte(chip, ichdev->reg_offset + ICH_REG_OFF_CIV);
2702 pos1 = igetword(chip, ichdev->reg_offset + ichdev->roff_picb);
2703 if (pos1 == 0) {
2704 udelay(10);
2705 continue;
2706 }
2707 if (civ == igetbyte(chip, ichdev->reg_offset + ICH_REG_OFF_CIV) &&
2708 pos1 == igetword(chip, ichdev->reg_offset + ichdev->roff_picb))
2709 break;
2710 } while (timeout--);
2711 if (pos1 == 0) { /* oops, this value is not reliable */
2712 pos = 0;
2713 } else {
2714 pos = ichdev->fragsize1;
2715 pos -= pos1 << ichdev->pos_shift;
2716 pos += ichdev->position;
2717 }
2718 chip->in_measurement = 0;
2719#ifndef TARGET_OS2
2720 stop_time = ktime_get();
2721#else
2722 do_posix_clock_monotonic_gettime(&stop_time);
2723#endif
2724 /* stop */
2725 if (chip->device_type == DEVICE_ALI) {
2726 iputdword(chip, ICHREG(ALI_DMACR), 1 << (ichdev->ali_slot + 16));
2727 iputbyte(chip, port + ICH_REG_OFF_CR, 0);
2728 while (igetbyte(chip, port + ICH_REG_OFF_CR))
2729 ;
2730 } else {
2731 iputbyte(chip, port + ICH_REG_OFF_CR, 0);
2732 while (!(igetbyte(chip, port + ichdev->roff_sr) & ICH_DCH))
2733 ;
2734 }
2735 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_RESETREGS);
2736 spin_unlock_irq(&chip->reg_lock);
2737
2738 if (pos == 0) {
2739 dev_err(chip->card->dev,
2740 "measure - unreliable DMA position..\n");
2741 __retry:
2742 if (attempt < 3) {
2743 msleep(300);
2744 attempt++;
2745 goto __again;
2746 }
2747 goto __end;
2748 }
2749
2750 pos /= 4;
2751#ifndef TARGET_OS2
2752 t = ktime_us_delta(stop_time, start_time);
2753#else
2754 t = stop_time.tv_sec - start_time.tv_sec;
2755 t *= 1000000;
2756 t += (stop_time.tv_nsec - start_time.tv_nsec) / 1000;
2757 dprintf(("%s: measured %lu usecs (%lu samples)\n", __func__, t, pos));
2758#endif
2759 dev_info(chip->card->dev,
2760 "%s: measured %lu usecs (%lu samples)\n", __func__, t, pos);
2761 if (t == 0) {
2762 dev_err(chip->card->dev, "?? calculation error..\n");
2763 goto __retry;
2764 }
2765 pos *= 1000;
2766 pos = (pos / t) * 1000 + ((pos % t) * 1000) / t;
2767 if (pos < 40000 || pos >= 60000) {
2768 /* abnormal value. hw problem? */
2769 dev_info(chip->card->dev, "measured clock %ld rejected\n", pos);
2770 goto __retry;
2771 } else if (pos > 40500 && pos < 41500)
2772 /* first exception - 41000Hz reference clock */
2773 chip->ac97_bus->clock = 41000;
2774 else if (pos > 43600 && pos < 44600)
2775 /* second exception - 44100HZ reference clock */
2776 chip->ac97_bus->clock = 44100;
2777 else if (pos < 47500 || pos > 48500)
2778 /* not 48000Hz, tuning the clock.. */
2779 chip->ac97_bus->clock = (chip->ac97_bus->clock * 48000) / pos;
2780 __end:
2781 dev_info(chip->card->dev, "clocking to %d\n", chip->ac97_bus->clock);
2782 snd_ac97_update_power(chip->ac97[0], AC97_PCM_FRONT_DAC_RATE, 0);
2783}
2784
2785static const struct snd_pci_quirk intel8x0_clock_list[] = {
2786 SND_PCI_QUIRK(0x0e11, 0x008a, "AD1885", 41000),
2787 SND_PCI_QUIRK(0x1014, 0x0581, "AD1981B", 48000),
2788 SND_PCI_QUIRK(0x1028, 0x00be, "AD1885", 44100),
2789 SND_PCI_QUIRK(0x1028, 0x0177, "AD1980", 48000),
2790 SND_PCI_QUIRK(0x1028, 0x01ad, "AD1981B", 48000),
2791 SND_PCI_QUIRK(0x1043, 0x80f3, "AD1985", 48000),
2792 {0} /* terminator */
2793};
2794
2795static int intel8x0_in_clock_list(struct intel8x0 *chip)
2796{
2797 struct pci_dev *pci = chip->pci;
2798 const struct snd_pci_quirk *wl;
2799
2800 wl = snd_pci_quirk_lookup(pci, intel8x0_clock_list);
2801 if (!wl)
2802 return 0;
2803 dev_info(chip->card->dev, "allow list rate for %04x:%04x is %i\n",
2804 pci->subsystem_vendor, pci->subsystem_device, wl->value);
2805 chip->ac97_bus->clock = wl->value;
2806 return 1;
2807}
2808
2809static void snd_intel8x0_proc_read(struct snd_info_entry * entry,
2810 struct snd_info_buffer *buffer)
2811{
2812 struct intel8x0 *chip = entry->private_data;
2813 unsigned int tmp;
2814
2815 snd_iprintf(buffer, "Intel8x0\n\n");
2816 if (chip->device_type == DEVICE_ALI)
2817 return;
2818 tmp = igetdword(chip, ICHREG(GLOB_STA));
2819 snd_iprintf(buffer, "Global control : 0x%08x\n", igetdword(chip, ICHREG(GLOB_CNT)));
2820 snd_iprintf(buffer, "Global status : 0x%08x\n", tmp);
2821 if (chip->device_type == DEVICE_INTEL_ICH4)
2822 snd_iprintf(buffer, "SDM : 0x%08x\n", igetdword(chip, ICHREG(SDM)));
2823 snd_iprintf(buffer, "AC'97 codecs ready :");
2824 if (tmp & chip->codec_isr_bits) {
2825 int i;
2826 static const char *codecs[3] = {
2827 "primary", "secondary", "tertiary"
2828 };
2829 for (i = 0; i < chip->max_codecs; i++)
2830 if (tmp & chip->codec_bit[i])
2831 snd_iprintf(buffer, " %s", codecs[i]);
2832 } else
2833 snd_iprintf(buffer, " none");
2834 snd_iprintf(buffer, "\n");
2835 if (chip->device_type == DEVICE_INTEL_ICH4 ||
2836 chip->device_type == DEVICE_SIS)
2837 snd_iprintf(buffer, "AC'97 codecs SDIN : %i %i %i\n",
2838 chip->ac97_sdin[0],
2839 chip->ac97_sdin[1],
2840 chip->ac97_sdin[2]);
2841}
2842
2843static void snd_intel8x0_proc_init(struct intel8x0 *chip)
2844{
2845 snd_card_ro_proc_new(chip->card, "intel8x0", chip,
2846 snd_intel8x0_proc_read);
2847}
2848
2849struct ich_reg_info {
2850 unsigned int int_sta_mask;
2851 unsigned int offset;
2852};
2853
2854static const unsigned int ich_codec_bits[3] = {
2855 ICH_PCR, ICH_SCR, ICH_TCR
2856};
2857static const unsigned int sis_codec_bits[3] = {
2858 ICH_PCR, ICH_SCR, ICH_SIS_TCR
2859};
2860
2861static int snd_intel8x0_inside_vm(struct pci_dev *pci)
2862{
2863 int result = inside_vm;
2864 char *msg = NULL;
2865
2866 /* check module parameter first (override detection) */
2867 if (result >= 0) {
2868 msg = result ? "enable (forced) VM" : "disable (forced) VM";
2869 goto fini;
2870 }
2871
2872 /* check for known (emulated) devices */
2873 result = 0;
2874 if (pci->subsystem_vendor == PCI_SUBVENDOR_ID_REDHAT_QUMRANET &&
2875 pci->subsystem_device == PCI_SUBDEVICE_ID_QEMU) {
2876 /* KVM emulated sound, PCI SSID: 1af4:1100 */
2877 msg = "enable KVM";
2878 result = 1;
2879 } else if (pci->subsystem_vendor == 0x1ab8) {
2880 /* Parallels VM emulated sound, PCI SSID: 1ab8:xxxx */
2881 msg = "enable Parallels VM";
2882 result = 1;
2883 }
2884
2885fini:
2886 if (msg != NULL)
2887 dev_info(&pci->dev, "%s optimization\n", msg);
2888
2889 return result;
2890}
2891
2892static int snd_intel8x0_init(struct snd_card *card,
2893 struct pci_dev *pci,
2894 unsigned long device_type)
2895{
2896 struct intel8x0 *chip = card->private_data;
2897 int err;
2898 unsigned int i;
2899 unsigned int int_sta_masks;
2900 struct ichdev *ichdev;
2901
2902 static const unsigned int bdbars[] = {
2903 3, /* DEVICE_INTEL */
2904 6, /* DEVICE_INTEL_ICH4 */
2905 3, /* DEVICE_SIS */
2906 6, /* DEVICE_ALI */
2907 4, /* DEVICE_NFORCE */
2908 };
2909 static const struct ich_reg_info intel_regs[6] = {
2910 { ICH_PIINT, 0 },
2911 { ICH_POINT, 0x10 },
2912 { ICH_MCINT, 0x20 },
2913 { ICH_M2INT, 0x40 },
2914 { ICH_P2INT, 0x50 },
2915 { ICH_SPINT, 0x60 },
2916 };
2917 static const struct ich_reg_info nforce_regs[4] = {
2918 { ICH_PIINT, 0 },
2919 { ICH_POINT, 0x10 },
2920 { ICH_MCINT, 0x20 },
2921 { ICH_NVSPINT, 0x70 },
2922 };
2923 static const struct ich_reg_info ali_regs[6] = {
2924 { ALI_INT_PCMIN, 0x40 },
2925 { ALI_INT_PCMOUT, 0x50 },
2926 { ALI_INT_MICIN, 0x60 },
2927 { ALI_INT_CODECSPDIFOUT, 0x70 },
2928 { ALI_INT_SPDIFIN, 0xa0 },
2929 { ALI_INT_SPDIFOUT, 0xb0 },
2930 };
2931 const struct ich_reg_info *tbl;
2932
2933 err = pcim_enable_device(pci);
2934 if (err < 0)
2935 return err;
2936
2937 spin_lock_init(&chip->reg_lock);
2938 chip->device_type = device_type;
2939 chip->card = card;
2940 chip->pci = pci;
2941 chip->irq = -1;
2942
2943 /* module parameters */
2944 chip->buggy_irq = buggy_irq;
2945 chip->buggy_semaphore = buggy_semaphore;
2946 if (xbox)
2947 chip->xbox = 1;
2948
2949 chip->inside_vm = snd_intel8x0_inside_vm(pci);
2950
2951 /*
2952 * Intel 82443MX running a 100MHz processor system bus has a hardware
2953 * bug, which aborts PCI busmaster for audio transfer. A workaround
2954 * is to set the pages as non-cached. For details, see the errata in
2955 * http://download.intel.com/design/chipsets/specupdt/24505108.pdf
2956 */
2957 if (pci->vendor == PCI_VENDOR_ID_INTEL &&
2958 pci->device == PCI_DEVICE_ID_INTEL_440MX)
2959 chip->fix_nocache = 1; /* enable workaround */
2960
2961 err = pci_request_regions(pci, card->shortname);
2962 if (err < 0)
2963 return err;
2964
2965 if (device_type == DEVICE_ALI) {
2966 /* ALI5455 has no ac97 region */
2967 chip->bmaddr = pcim_iomap(pci, 0, 0);
2968 } else {
2969 if (pci_resource_flags(pci, 2) & IORESOURCE_MEM) /* ICH4 and Nforce */
2970 chip->addr = pcim_iomap(pci, 2, 0);
2971 else
2972 chip->addr = pcim_iomap(pci, 0, 0);
2973 if (pci_resource_flags(pci, 3) & IORESOURCE_MEM) /* ICH4 */
2974 chip->bmaddr = pcim_iomap(pci, 3, 0);
2975 else
2976 chip->bmaddr = pcim_iomap(pci, 1, 0);
2977 }
2978
2979 chip->bdbars_count = bdbars[device_type];
2980
2981 /* initialize offsets */
2982 switch (device_type) {
2983 case DEVICE_NFORCE:
2984 tbl = nforce_regs;
2985 break;
2986 case DEVICE_ALI:
2987 tbl = ali_regs;
2988 break;
2989 default:
2990 tbl = intel_regs;
2991 break;
2992 }
2993 for (i = 0; i < chip->bdbars_count; i++) {
2994 ichdev = &chip->ichd[i];
2995 ichdev->ichd = i;
2996 ichdev->reg_offset = tbl[i].offset;
2997 ichdev->int_sta_mask = tbl[i].int_sta_mask;
2998 if (device_type == DEVICE_SIS) {
2999 /* SiS 7012 swaps the registers */
3000 ichdev->roff_sr = ICH_REG_OFF_PICB;
3001 ichdev->roff_picb = ICH_REG_OFF_SR;
3002 } else {
3003 ichdev->roff_sr = ICH_REG_OFF_SR;
3004 ichdev->roff_picb = ICH_REG_OFF_PICB;
3005 }
3006 if (device_type == DEVICE_ALI)
3007 ichdev->ali_slot = (ichdev->reg_offset - 0x40) / 0x10;
3008 /* SIS7012 handles the pcm data in bytes, others are in samples */
3009 ichdev->pos_shift = (device_type == DEVICE_SIS) ? 0 : 1;
3010 }
3011
3012 /* allocate buffer descriptor lists */
3013 /* the start of each lists must be aligned to 8 bytes */
3014 chip->bdbars = snd_devm_alloc_pages(&pci->dev, intel8x0_dma_type(chip),
3015 chip->bdbars_count * sizeof(u32) *
3016 ICH_MAX_FRAGS * 2);
3017 if (!chip->bdbars)
3018 return -ENOMEM;
3019 /* tables must be aligned to 8 bytes here, but the kernel pages
3020 are much bigger, so we don't care (on i386) */
3021 int_sta_masks = 0;
3022 for (i = 0; i < chip->bdbars_count; i++) {
3023 ichdev = &chip->ichd[i];
3024 ichdev->bdbar = ((__le32 *)chip->bdbars->area) +
3025 (i * ICH_MAX_FRAGS * 2);
3026 ichdev->bdbar_addr = chip->bdbars->addr +
3027 (i * sizeof(u32) * ICH_MAX_FRAGS * 2);
3028 int_sta_masks |= ichdev->int_sta_mask;
3029 }
3030 chip->int_sta_reg = device_type == DEVICE_ALI ?
3031 ICH_REG_ALI_INTERRUPTSR : ICH_REG_GLOB_STA;
3032 chip->int_sta_mask = int_sta_masks;
3033
3034 pci_set_master(pci);
3035
3036 switch(chip->device_type) {
3037 case DEVICE_INTEL_ICH4:
3038 /* ICH4 can have three codecs */
3039 chip->max_codecs = 3;
3040 chip->codec_bit = ich_codec_bits;
3041 chip->codec_ready_bits = ICH_PRI | ICH_SRI | ICH_TRI;
3042 break;
3043 case DEVICE_SIS:
3044 /* recent SIS7012 can have three codecs */
3045 chip->max_codecs = 3;
3046 chip->codec_bit = sis_codec_bits;
3047 chip->codec_ready_bits = ICH_PRI | ICH_SRI | ICH_SIS_TRI;
3048 break;
3049 default:
3050 /* others up to two codecs */
3051 chip->max_codecs = 2;
3052 chip->codec_bit = ich_codec_bits;
3053 chip->codec_ready_bits = ICH_PRI | ICH_SRI;
3054 break;
3055 }
3056 for (i = 0; i < chip->max_codecs; i++)
3057 chip->codec_isr_bits |= chip->codec_bit[i];
3058
3059 err = snd_intel8x0_chip_init(chip, 1);
3060 if (err < 0)
3061 return err;
3062
3063 /* request irq after initializaing int_sta_mask, etc */
3064 /* NOTE: we don't use devm version here since it's released /
3065 * re-acquired in PM callbacks.
3066 * It's released explicitly in snd_intel8x0_free(), too.
3067 */
3068 if (request_irq(pci->irq, snd_intel8x0_interrupt,
3069 IRQF_SHARED, KBUILD_MODNAME, chip)) {
3070 dev_err(card->dev, "unable to grab IRQ %d\n", pci->irq);
3071 return -EBUSY;
3072 }
3073 chip->irq = pci->irq;
3074 card->sync_irq = chip->irq;
3075
3076 card->private_free = snd_intel8x0_free;
3077
3078 return 0;
3079}
3080
3081static struct shortname_table {
3082 unsigned int id;
3083 const char *s;
3084} shortnames[] = {
3085 { PCI_DEVICE_ID_INTEL_82801AA_5, "Intel 82801AA-ICH" },
3086 { PCI_DEVICE_ID_INTEL_82801AB_5, "Intel 82901AB-ICH0" },
3087 { PCI_DEVICE_ID_INTEL_82801BA_4, "Intel 82801BA-ICH2" },
3088 { PCI_DEVICE_ID_INTEL_440MX, "Intel 440MX" },
3089 { PCI_DEVICE_ID_INTEL_82801CA_5, "Intel 82801CA-ICH3" },
3090 { PCI_DEVICE_ID_INTEL_82801DB_5, "Intel 82801DB-ICH4" },
3091 { PCI_DEVICE_ID_INTEL_82801EB_5, "Intel ICH5" },
3092 { PCI_DEVICE_ID_INTEL_ESB_5, "Intel 6300ESB" },
3093 { PCI_DEVICE_ID_INTEL_ICH6_18, "Intel ICH6" },
3094 { PCI_DEVICE_ID_INTEL_ICH7_20, "Intel ICH7" },
3095 { PCI_DEVICE_ID_INTEL_ESB2_14, "Intel ESB2" },
3096 { PCI_DEVICE_ID_SI_7012, "SiS SI7012" },
3097 { PCI_DEVICE_ID_NVIDIA_MCP1_AUDIO, "NVidia nForce" },
3098 { PCI_DEVICE_ID_NVIDIA_MCP2_AUDIO, "NVidia nForce2" },
3099 { PCI_DEVICE_ID_NVIDIA_MCP3_AUDIO, "NVidia nForce3" },
3100 { PCI_DEVICE_ID_NVIDIA_CK8S_AUDIO, "NVidia CK8S" },
3101 { PCI_DEVICE_ID_NVIDIA_CK804_AUDIO, "NVidia CK804" },
3102 { PCI_DEVICE_ID_NVIDIA_CK8_AUDIO, "NVidia CK8" },
3103 { 0x003a, "NVidia MCP04" },
3104 { 0x746d, "AMD AMD8111" },
3105 { 0x7445, "AMD AMD768" },
3106 { 0x5455, "ALi M5455" },
3107 { 0, NULL },
3108};
3109
3110static const struct snd_pci_quirk spdif_aclink_defaults[] = {
3111 SND_PCI_QUIRK(0x147b, 0x1c1a, "ASUS KN8", 1),
3112 {0} /* end */
3113};
3114
3115/* look up allow/deny list for SPDIF over ac-link */
3116static int check_default_spdif_aclink(struct pci_dev *pci)
3117{
3118 const struct snd_pci_quirk *w;
3119
3120 w = snd_pci_quirk_lookup(pci, spdif_aclink_defaults);
3121 if (w) {
3122 if (w->value)
3123 dev_dbg(&pci->dev,
3124 "Using SPDIF over AC-Link for %s\n",
3125 snd_pci_quirk_name(w));
3126 else
3127 dev_dbg(&pci->dev,
3128 "Using integrated SPDIF DMA for %s\n",
3129 snd_pci_quirk_name(w));
3130 return w->value;
3131 }
3132 return 0;
3133}
3134
3135static int __snd_intel8x0_probe(struct pci_dev *pci,
3136 const struct pci_device_id *pci_id)
3137{
3138 struct snd_card *card;
3139 struct intel8x0 *chip;
3140 int err;
3141 struct shortname_table *name;
3142
3143 err = snd_devm_card_new(&pci->dev, index, id, THIS_MODULE,
3144 sizeof(*chip), &card);
3145 if (err < 0)
3146 return err;
3147 chip = card->private_data;
3148
3149 if (spdif_aclink < 0)
3150 spdif_aclink = check_default_spdif_aclink(pci);
3151
3152 strcpy(card->driver, "ICH");
3153 if (!spdif_aclink) {
3154 switch (pci_id->driver_data) {
3155 case DEVICE_NFORCE:
3156 strcpy(card->driver, "NFORCE");
3157 break;
3158 case DEVICE_INTEL_ICH4:
3159 strcpy(card->driver, "ICH4");
3160 }
3161 }
3162
3163 strcpy(card->shortname, "Intel ICH");
3164 for (name = shortnames; name->id; name++) {
3165 if (pci->device == name->id) {
3166 strcpy(card->shortname, name->s);
3167 break;
3168 }
3169 }
3170
3171 if (buggy_irq < 0) {
3172 /* some Nforce[2] and ICH boards have problems with IRQ handling.
3173 * Needs to return IRQ_HANDLED for unknown irqs.
3174 */
3175 if (pci_id->driver_data == DEVICE_NFORCE)
3176 buggy_irq = 1;
3177 else
3178 buggy_irq = 0;
3179 }
3180
3181 err = snd_intel8x0_init(card, pci, pci_id->driver_data);
3182 if (err < 0)
3183 return err;
3184
3185 err = snd_intel8x0_mixer(chip, ac97_clock, ac97_quirk);
3186 if (err < 0)
3187 return err;
3188 err = snd_intel8x0_pcm(chip);
3189 if (err < 0)
3190 return err;
3191
3192 snd_intel8x0_proc_init(chip);
3193
3194 snprintf(card->longname, sizeof(card->longname),
3195 "%s with %s at irq %i", card->shortname,
3196 snd_ac97_get_short_name(chip->ac97[0]), chip->irq);
3197
3198 if (ac97_clock == 0 || ac97_clock == 1) {
3199 if (ac97_clock == 0) {
3200 if (intel8x0_in_clock_list(chip) == 0)
3201 intel8x0_measure_ac97_clock(chip);
3202 } else {
3203 intel8x0_measure_ac97_clock(chip);
3204 }
3205 }
3206
3207 err = snd_card_register(card);
3208 if (err < 0)
3209 return err;
3210
3211 pci_set_drvdata(pci, card);
3212 return 0;
3213}
3214
3215static int snd_intel8x0_probe(struct pci_dev *pci,
3216 const struct pci_device_id *pci_id)
3217{
3218 return snd_card_free_on_error(&pci->dev, __snd_intel8x0_probe(pci, pci_id));
3219}
3220
3221static struct pci_driver intel8x0_driver = {
3222 .name = KBUILD_MODNAME,
3223 .id_table = snd_intel8x0_ids,
3224 .probe = snd_intel8x0_probe,
3225 .driver = {
3226 .pm = INTEL8X0_PM_OPS,
3227 },
3228};
3229
3230module_pci_driver(intel8x0_driver);
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