Ignore:
Timestamp:
Apr 19, 2025, 8:08:37 PM (4 months ago)
Author:
David Azarewicz
Message:

Merge in changes from 6.6-LTS branch.
Fixed additional 25+ problems.

Location:
GPL/trunk
Files:
1 added
29 edited
8 copied

Legend:

Unmodified
Added
Removed

  • GPL/trunk

  • GPL/trunk/include/linux/device.h

    r717 r772  
    4242
    4343        const struct dev_pm_ops *pm;
     44};
     45
     46struct device_dma_parameters {
     47        /*
     48         * a low level driver may set these to teach IOMMU code about
     49         * sg limitations.
     50         */
     51        unsigned int max_segment_size;
     52        unsigned int min_align_mask;
     53        unsigned long segment_boundary_mask;
    4454};
    4555
    … …  
    6777  void *platform_data;
    6878  struct dev_pm_info    power;
     79        struct device_dma_parameters *dma_parms;
    6980  struct list_head      dma_pools;      /* dma pools (if dma'ble) */
    7081  struct device_driver *driver;
     82  void          *driver_data;   /* Driver data, set and get with
     83                                           dev_set_drvdata/dev_get_drvdata */
    7184  struct pm_dev *pm_dev;
    7285  char  bus_id[20];
    73   struct class          *class;
     86  const struct class            *class;
    7487  spinlock_t            devres_lock;
    7588  struct list_head      devres_head;
    … …  
    92105static inline const char *dev_name(const struct device *dev)
    93106{
     107#if 0
    94108        /* Use the init name until the kobject becomes available */
    95109        if (dev->init_name)
    … …  
    97111
    98112        return kobject_name(&dev->kobj);
     113#else
     114        return "uniaud32";
     115#endif
    99116}
    100117
    … …  
    146163                                         struct bus_type *bus);
    147164
    148 #define dev_set_drvdata(dev,ptr)        ((dev)->private_data = (ptr))
    149 #define dev_get_drvdata(dev)    (dev)->private_data
    150 
    151165#define MODULE_ALIAS_CHARDEV_MAJOR(x)
    152166
    … …  
    218232typedef int (*dr_match_t)(struct device *dev, void *res, void *match_data);
    219233
    220 extern void *devres_alloc_node(dr_release_t release, size_t size, gfp_t gfp,
    221                                int nid);
    222234#define NUMA_NO_NODE    (-1)
    223 static inline void *devres_alloc(dr_release_t release, size_t size, gfp_t gfp)
    224 {
    225         return devres_alloc_node(release, size, gfp, NUMA_NO_NODE);
    226 }
     235void *__devres_alloc_node(dr_release_t release, size_t size, gfp_t gfp,
     236                          int nid, const char *name);
     237#define devres_alloc(release, size, gfp) \
     238        __devres_alloc_node(release, size, gfp, NUMA_NO_NODE, #release)
    227239
    228240/**
    … …  
    288300                         dr_match_t match, void *match_data);
    289301
     302/* devres group */
     303void * __must_check devres_open_group(struct device *dev, void *id, gfp_t gfp);
     304void devres_close_group(struct device *dev, void *id);
     305void devres_remove_group(struct device *dev, void *id);
     306int devres_release_group(struct device *dev, void *id);
     307
    290308/* debugging and troubleshooting/diagnostic helpers. */
    291309extern const char *dev_driver_string(const struct device *dev);
    292 #define devm_kzalloc(A, B, C) kzalloc(B, C)
    293 #define devm_kmalloc(A, B, C) kmalloc(B, C)
    294 #define devm_kcalloc(A, B, C, D) kmalloc(B, C)
    295 #define devm_kmalloc_array(A, B, C, D) kmalloc_array(B, C, D)
    296 
     310void *devm_kmalloc(struct device *dev, size_t size, gfp_t gfp);
     311
     312static inline void *devm_kzalloc(struct device *dev, size_t size, gfp_t gfp)
     313{
     314        return devm_kmalloc(dev, size, gfp | __GFP_ZERO);
     315}
     316
     317static inline void *devm_kmalloc_array(struct device *dev,
     318                                       size_t n, size_t size, gfp_t flags)
     319{
     320//      size_t bytes;
     321
     322//      if (unlikely(check_mul_overflow(n, size, &bytes)))
     323//              return NULL;
     324
     325        return devm_kmalloc(dev, n * size, flags);
     326}
     327static inline void *devm_kcalloc(struct device *dev,
     328                                 size_t n, size_t size, gfp_t flags)
     329{
     330        return devm_kmalloc_array(dev, n, size, flags | __GFP_ZERO);
     331}
    297332
    298333/* allows to add/remove a custom action to devres stack */
    299334int devm_add_action(struct device *dev, void (*action)(void *), void *data);
    300335void devm_remove_action(struct device *dev, void (*action)(void *), void *data);
     336
     337static inline int dev_to_node(struct device *dev)
     338{
     339        return NUMA_NO_NODE;
     340}
     341
     342static inline void *dev_get_drvdata(const struct device *dev)
     343{
     344        return dev->driver_data;
     345}
     346
     347static inline void dev_set_drvdata(struct device *dev, void *data)
     348{
     349        dev->driver_data = data;
     350}
     351
     352/* Generic device matching functions that all busses can use to match with */
     353int device_match_name(struct device *dev, const void *name);
     354int device_match_of_node(struct device *dev, const void *np);
     355
     356char *devm_kasprintf(struct device *dev, gfp_t gfp,
     357                                    const char *fmt, ...);
     358
    301359#endif /* _LINUX_DEVICE_H */
    302360

  • GPL/trunk/include/linux/dma-mapping.h

    r703 r772  
    55#include <linux/string.h>
    66#include <linux/err.h>
    7 
    8 /* These definitions mirror those in pci.h, so they can be used
    9  * interchangeably with their PCI_ counterparts */
    10 enum dma_data_direction {
    11         DMA_BIDIRECTIONAL = 0,
    12         DMA_TO_DEVICE = 1,
    13         DMA_FROM_DEVICE = 2,
    14         DMA_NONE = 3,
    15 };
    167
    178/*
    … …  
    144135}
    145136#define pci_set_consistent_dma_mask(p,x) pci_set_dma_mask(p,x)
     137
     138static inline int dma_set_max_seg_size(struct device *dev, unsigned int size)
     139{
     140        if (dev->dma_parms) {
     141                dev->dma_parms->max_segment_size = size;
     142                return 0;
     143        }
     144        return -EIO;
     145}
    146146#endif

  • GPL/trunk/include/linux/errno.h

    r679 r772  
    1313#define ERESTARTNOHAND  514     /* restart if no handler.. */
    1414#define ENOIOCTLCMD     515     /* No ioctl command */
     15#define EPROBE_DEFER    517     /* Driver requests probe retry */
    1516#define ENOTSUPP        524     /* Operation is not supported */
    1617

  • GPL/trunk/include/linux/fs.h

    r679 r772  
    336336}
    337337
     338#define MAX_RW_COUNT (INT_MAX & PAGE_MASK)
     339
    338340#endif /* _LINUX_FS_H */

  • GPL/trunk/include/linux/gfp.h

    r679 r772  
    22#define __LINUX_GFP_H
    33
    4 #include <asm/page.h>
    5 #include <linux/export.h>
    6 #include <linux/mm.h>
    74#include <linux/types.h>
     5
     6/*
     7 * GFP bitmasks..
     8 */
     9#define __GFP_WAIT      0x01
     10#define __GFP_LOW       0x02
     11#define __GFP_MED       0x04
     12#define __GFP_HIGH      0x08
     13#define __GFP_IO        0x10
     14#define __GFP_SWAP      0x20
    815
    916/* Plain integer GFP bitmasks. Do not use this directly. */
    … …  
    4451#define __GFP_RETRY_MAYFAIL     ((__force gfp_t)___GFP_RETRY_MAYFAIL)
    4552#define GFP_DMA32 0             /* driver must check for 32-bit address */
     53#define GFP_BUFFER      (__GFP_LOW | __GFP_WAIT)
     54#define GFP_ATOMIC      (__GFP_HIGH)
     55#define GFP_USER        (__GFP_LOW | __GFP_WAIT | __GFP_IO)
     56#define GFP_HIGHUSER    (GFP_USER | __GFP_HIGHMEM)
     57#define GFP_KERNEL      (__GFP_MED | __GFP_WAIT | __GFP_IO)
     58#define GFP_NFS         (__GFP_HIGH | __GFP_WAIT | __GFP_IO)
     59#define GFP_KSWAPD      (__GFP_IO | __GFP_SWAP)
     60
    4661
    4762/*
    … …  
    5772#define __GFP_MOVABLE   ((__force gfp_t)___GFP_MOVABLE)  /* ZONE_MOVABLE allowed */
    5873#define GFP_ZONEMASK    (__GFP_DMA|__GFP_HIGHMEM|__GFP_DMA32|__GFP_MOVABLE)
     74/* Flag - indicates that the buffer will be suitable for DMA.  Ignored on some
     75   platforms, used as appropriate on others */
     76
     77#define GFP_DMA         __GFP_DMA
     78
     79/* Flag - indicates that the buffer can be taken from high memory which is not
     80   directly addressable by the kernel */
     81
     82#define GFP_HIGHMEM     __GFP_HIGHMEM
     83#define __GFP_DMAHIGHMEM  0x100
     84#define GFP_DMAHIGHMEM    __GFP_DMAHIGHMEM
     85
    5986void *alloc_pages_exact(size_t size, gfp_t gfp_mask);
    6087void free_pages_exact(void *virt, size_t size);

  • GPL/trunk/include/linux/interrupt.h

    r717 r772  
    154154
    155155static inline void devm_free_irq(struct device *dev, unsigned int irq, void *dev_id) {}
    156 #define devm_request_irq(A, B, C, D, E, F) request_irq(B, C, D, E, F)
    157156
     157extern int __must_check
     158devm_request_threaded_irq(struct device *dev, unsigned int irq,
     159                          irq_handler_t handler, irq_handler_t thread_fn,
     160                          unsigned long irqflags, const char *devname,
     161                          void *dev_id);
     162
     163static inline int __must_check
     164devm_request_irq(struct device *dev, unsigned int irq, irq_handler_t handler,
     165                 unsigned long irqflags, const char *devname, void *dev_id)
     166{
     167        return devm_request_threaded_irq(dev, irq, handler, NULL, irqflags,
     168                                         devname, dev_id);
     169}
    158170#endif

  • GPL/trunk/include/linux/io.h

    r717 r772  
    77#include <linux/err.h>
    88
    9 #define devm_ioremap(A, B, C) ioremap(B, C)
     9void __iomem *devm_ioremap(struct device *dev, resource_size_t offset,
     10                           resource_size_t size);
     11
    1012#endif /* _LINUX_IO_H */

  • GPL/trunk/include/linux/ioport.h

    r717 r772  
    1212
    1313#include <linux/types.h>
     14#include <linux/minmax.h>
     15
    1416/*
    1517 * Resources are tree-like, allowing
    … …  
    111113extern int autoirq_report(int waittime);
    112114
    113 #define devm_request_region(A, B, C, D) request_region(B, C, D)
     115extern struct resource * __devm_request_region(struct device *dev,
     116                                struct resource *parent, resource_size_t start,
     117                                resource_size_t n, const char *name);
     118
     119#define devm_request_region(dev,start,n,name) \
     120        __devm_request_region(dev, &ioport_resource, (start), (n), (name))
    114121#endif  /* _LINUX_IOPORT_H */

  • GPL/trunk/include/linux/kernel.h

    r679 r772  
    1515#include <linux/types.h>
    1616#include <linux/log2.h>
     17#include <linux/string.h>
     18#include <linux/math.h>
     19#include <linux/minmax.h>
     20#include <linux/export.h>
    1721
    1822/* Optimization barrier */

  • GPL/trunk/include/linux/lockdep.h

    r679 r772  
    1919                do { (void)(key); (void)(name); } while (0)
    2020struct lock_class_key {int not_used; };
     21
     22#define lockdep_assert_held(l)
     23#define lockdep_assert_not_held(l)
     24#define lockdep_assert_held_write(l)
     25#define lockdep_assert_held_read(l)
     26#define lockdep_assert_held_once(l)
     27#define lockdep_assert_none_held_once()
     28
    2129#endif /* __LINUX_LOCKDEP_H */

  • GPL/trunk/include/linux/math64.h

    r679 r772  
    140140#endif
    141141
     142u64 div64_u64_rem(u64 dividend, u64 divisor, u64 *remainder);
     143
    142144#endif /* MATH64_COMPAT_H */

  • GPL/trunk/include/linux/mm.h

    r679 r772  
    1111
    1212#define NUMA_NO_NODE    (-1)
    13 /*
    14  * GFP bitmasks..
    15  */
    16 #define __GFP_WAIT      0x01
    17 #define __GFP_LOW       0x02
    18 #define __GFP_MED       0x04
    19 #define __GFP_HIGH      0x08
    20 #define __GFP_IO        0x10
    21 #define __GFP_SWAP      0x20
    22 #define ___GFP_ZERO             0x100u
    23 #define __GFP_ZERO      ((__force gfp_t)___GFP_ZERO)
    24 
    25 #ifdef TARGET_OS2
    26 #define __GFP_DMAHIGHMEM  0x100
    27 #define GFP_DMAHIGHMEM    __GFP_DMAHIGHMEM
    28 #endif
    29 
    30 #define GFP_BUFFER      (__GFP_LOW | __GFP_WAIT)
    31 #define GFP_ATOMIC      (__GFP_HIGH)
    32 #define GFP_USER        (__GFP_LOW | __GFP_WAIT | __GFP_IO)
    33 #define GFP_HIGHUSER    (GFP_USER | __GFP_HIGHMEM)
    34 #define GFP_KERNEL      (__GFP_MED | __GFP_WAIT | __GFP_IO)
    35 #define GFP_NFS         (__GFP_HIGH | __GFP_WAIT | __GFP_IO)
    36 #define GFP_KSWAPD      (__GFP_IO | __GFP_SWAP)
    37 
    38 /* Flag - indicates that the buffer will be suitable for DMA.  Ignored on some
    39    platforms, used as appropriate on others */
    40 
    41 #define GFP_DMA         __GFP_DMA
    42 
    43 /* Flag - indicates that the buffer can be taken from high memory which is not
    44    directly addressable by the kernel */
    45 
    46 #define GFP_HIGHMEM     __GFP_HIGHMEM
    4713
    4814/*

  • GPL/trunk/include/linux/of.h

    r679 r772  
    2828
    2929
     30struct device_node {
     31        const char *name;
     32//      phandle phandle;
     33        const char *full_name;
     34//      struct fwnode_handle fwnode;
     35
     36        struct  property *properties;
     37        struct  property *deadprops;    /* removed properties */
     38        struct  device_node *parent;
     39        struct  device_node *child;
     40        struct  device_node *sibling;
     41        struct  kobject kobj;
     42        unsigned long _flags;
     43        void    *data;
     44};
    3045struct property {
    3146        char    *name;
    … …  
    6075        return prop ? true : false;
    6176}
     77extern void of_node_put(struct device_node *node);
    6278
    6379#endif /* _LINUX_OF_H */

  • GPL/trunk/include/linux/pci.h

    r717 r772  
    4343#define  PCI_COMMAND_SERR 0x100 /* Enable SERR */
    4444#define  PCI_COMMAND_FAST_BACK  0x200 /* Enable back-to-back writes */
     45#define  PCI_COMMAND_INTX_DISABLE 0x400 /* INTx Emulation Disable */
    4546
    4647#define PCI_STATUS    0x06  /* 16 bits */
    … …  
    363364  struct resource dma_resource[DEVICE_COUNT_DMA];
    364365  struct resource irq_resource[DEVICE_COUNT_IRQ];
     366        unsigned int    is_managed:1;
    365367
    366368  char    name[48]; /* Device name */
    … …  
    672674void pci_set_driver_data (struct pci_dev *dev, void *driver_data);
    673675
    674 #define pci_get_drvdata(a)   pci_get_driver_data(a)
    675 #define pci_set_drvdata(a,b) pci_set_driver_data(a, b)
    676 
    677676#define PCI_DEVICE(vend,dev) \
    678677        .vendor = (vend), .device = (dev), \
    … …  
    694693  return rev;
    695694}
    696 
    697 /* pci_intx() wrapper */
    698 #define pci_intx(pci,x)
    699695
    700696/* MSI */
    … …  
    739735static inline bool pci_dev_run_wake(struct pci_dev *dev) { return 0; }
    740736
     737/*
     738 * Similar to the helpers above, these manipulate per-pci_dev
     739 * driver-specific data.  They are really just a wrapper around
     740 * the generic device structure functions of these calls.
     741 */
     742static inline void *pci_get_drvdata(struct pci_dev *pdev)
     743{
     744        return dev_get_drvdata(&pdev->dev);
     745}
     746
     747static inline void pci_set_drvdata(struct pci_dev *pdev, void *data)
     748{
     749        dev_set_drvdata(&pdev->dev, data);
     750}
    741751/* If you want to know what to call your pci_dev, ask this function.
    742752 * Again, it's a wrapper around the generic device.
    … …  
    771781#define dev_is_pci(d) (true)
    772782int pcim_enable_device(struct pci_dev *pdev);
    773 #define pcim_iomap pci_iomap
    774783int pcim_iomap_regions(struct pci_dev *pdev, int mask, const char *name);
     784void __iomem *pcim_iomap(struct pci_dev *pdev, int bar, unsigned long maxlen);
     785
     786static inline int pci_is_managed(struct pci_dev *pdev)
     787{
     788        return pdev->is_managed;
     789}
     790void pci_intx(struct pci_dev *pdev, int enable);
     791#define PCI_STD_NUM_BARS        6       /* Number of standard BARs */
     792int __must_check pci_request_region(struct pci_dev *, int, char *);
     793void pci_release_region(struct pci_dev *, int);
     794void __iomem * const *pcim_iomap_table(struct pci_dev *pdev);
     795#define for_each_pci_dev(d) while ((d = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, d)) != NULL)
     796
     797/**
     798 * PCI_DEVICE_DATA - macro used to describe a specific PCI device in very short form
     799 * @vend: the vendor name (without PCI_VENDOR_ID_ prefix)
     800 * @dev: the device name (without PCI_DEVICE_ID_<vend>_ prefix)
     801 * @data: the driver data to be filled
     802 *
     803 * This macro is used to create a struct pci_device_id that matches a
     804 * specific PCI device.  The subvendor, and subdevice fields will be set
     805 * to PCI_ANY_ID.
     806 */
     807#define PCI_DEVICE_DATA(vend, dev, data) \
     808        .vendor = PCI_VENDOR_ID_##vend, .device = PCI_DEVICE_ID_##vend##_##dev, \
     809        .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, 0, 0, \
     810        .driver_data = (unsigned long)(data)
     811
    775812#endif /* LINUX_PCI_H */

  • GPL/trunk/include/linux/pci_ids.h

    r679 r772  
    33 *      PCI Class, Vendor and Device IDs
    44 *
    5  *      Please keep sorted.
     5 *      Please keep sorted by numeric Vendor ID and Device ID.
    66 *
    77 *      Do not add new entries to this file unless the definitions
    … …  
    5252#define PCI_CLASS_MEMORY_RAM            0x0500
    5353#define PCI_CLASS_MEMORY_FLASH          0x0501
     54#define PCI_CLASS_MEMORY_CXL            0x0502
    5455#define PCI_CLASS_MEMORY_OTHER          0x0580
    5556
    … …  
    6061#define PCI_CLASS_BRIDGE_MC             0x0603
    6162#define PCI_CLASS_BRIDGE_PCI            0x0604
     63#define PCI_CLASS_BRIDGE_PCI_NORMAL             0x060400
     64#define PCI_CLASS_BRIDGE_PCI_SUBTRACTIVE        0x060401
    6265#define PCI_CLASS_BRIDGE_PCMCIA         0x0605
    6366#define PCI_CLASS_BRIDGE_NUBUS          0x0606
    … …  
    7275#define PCI_CLASS_COMMUNICATION_MODEM   0x0703
    7376#define PCI_CLASS_COMMUNICATION_OTHER   0x0780
     77
     78/* Interface for SERIAL/MODEM */
     79#define PCI_SERIAL_16550_COMPATIBLE     0x02
    7480
    7581#define PCI_BASE_CLASS_SYSTEM           0x08
    … …  
    8288#define PCI_CLASS_SYSTEM_PCI_HOTPLUG    0x0804
    8389#define PCI_CLASS_SYSTEM_SDHCI          0x0805
     90#define PCI_CLASS_SYSTEM_RCEC           0x0807
    8491#define PCI_CLASS_SYSTEM_OTHER          0x0880
    8592
    … …  
    118125#define PCI_CLASS_SERIAL_FIBER          0x0c04
    119126#define PCI_CLASS_SERIAL_SMBUS          0x0c05
     127#define PCI_CLASS_SERIAL_IPMI           0x0c07
     128#define PCI_CLASS_SERIAL_IPMI_SMIC      0x0c0700
     129#define PCI_CLASS_SERIAL_IPMI_KCS       0x0c0701
     130#define PCI_CLASS_SERIAL_IPMI_BT        0x0c0702
    120131
    121132#define PCI_BASE_CLASS_WIRELESS                 0x0d
    … …  
    141152#define PCI_CLASS_SP_OTHER              0x1180
    142153
     154#define PCI_BASE_CLASS_ACCELERATOR      0x12
     155#define PCI_CLASS_ACCELERATOR_PROCESSING        0x1200
     156
    143157#define PCI_CLASS_OTHERS                0xff
    144158
    145159/* Vendors and devices.  Sort key: vendor first, device next. */
     160#define PCI_VENDOR_ID_PCI_SIG           0x0001
     161
     162#define PCI_VENDOR_ID_LOONGSON          0x0014
     163
     164#define PCI_DEVICE_ID_LOONGSON_HDA      0x7a07
     165#define PCI_DEVICE_ID_LOONGSON_HDMI     0x7a37
     166
     167#define PCI_VENDOR_ID_SOLIDIGM          0x025e
    146168
    147169#define PCI_VENDOR_ID_TTTECH            0x0357
    … …  
    150172#define PCI_VENDOR_ID_DYNALINK          0x0675
    151173#define PCI_DEVICE_ID_DYNALINK_IS64PH   0x1702
     174
     175#define PCI_VENDOR_ID_UBIQUITI          0x0777
    152176
    153177#define PCI_VENDOR_ID_BERKOM                    0x0871
    … …  
    156180#define PCI_DEVICE_ID_BERKOM_A4T                0xffa4
    157181#define PCI_DEVICE_ID_BERKOM_SCITEL_QUADRO      0xffa8
     182
     183#define PCI_VENDOR_ID_ITTIM             0x0b48
    158184
    159185#define PCI_VENDOR_ID_COMPAQ            0x0e11
    … …  
    540566#define PCI_DEVICE_ID_AMD_16H_M30H_NB_F3 0x1583
    541567#define PCI_DEVICE_ID_AMD_16H_M30H_NB_F4 0x1584
     568#define PCI_DEVICE_ID_AMD_17H_DF_F3     0x1463
     569#define PCI_DEVICE_ID_AMD_17H_M10H_DF_F3 0x15eb
     570#define PCI_DEVICE_ID_AMD_17H_M30H_DF_F3 0x1493
     571#define PCI_DEVICE_ID_AMD_17H_M60H_DF_F3 0x144b
     572#define PCI_DEVICE_ID_AMD_17H_M70H_DF_F3 0x1443
     573#define PCI_DEVICE_ID_AMD_17H_MA0H_DF_F3 0x1727
     574#define PCI_DEVICE_ID_AMD_19H_DF_F3     0x1653
     575#define PCI_DEVICE_ID_AMD_19H_M10H_DF_F3 0x14b0
     576#define PCI_DEVICE_ID_AMD_19H_M40H_DF_F3 0x167c
     577#define PCI_DEVICE_ID_AMD_19H_M50H_DF_F3 0x166d
     578#define PCI_DEVICE_ID_AMD_19H_M60H_DF_F3 0x14e3
     579#define PCI_DEVICE_ID_AMD_19H_M70H_DF_F3 0x14f3
     580#define PCI_DEVICE_ID_AMD_19H_M78H_DF_F3 0x12fb
     581#define PCI_DEVICE_ID_AMD_1AH_M00H_DF_F3 0x12c3
     582#define PCI_DEVICE_ID_AMD_1AH_M20H_DF_F3 0x16fb
     583#define PCI_DEVICE_ID_AMD_1AH_M60H_DF_F3 0x124b
     584#define PCI_DEVICE_ID_AMD_1AH_M70H_DF_F3 0x12bb
     585#define PCI_DEVICE_ID_AMD_MI200_DF_F3   0x14d3
     586#define PCI_DEVICE_ID_AMD_VANGOGH_USB   0x163a
    542587#define PCI_DEVICE_ID_AMD_CNB17H_F3     0x1703
    543588#define PCI_DEVICE_ID_AMD_LANCE         0x2000
    … …  
    560605#define PCI_DEVICE_ID_AMD_VIPER_7443    0x7443
    561606#define PCI_DEVICE_ID_AMD_OPUS_7445     0x7445
     607#define PCI_DEVICE_ID_AMD_GOLAM_7450    0x7450
    562608#define PCI_DEVICE_ID_AMD_8111_PCI      0x7460
    563609#define PCI_DEVICE_ID_AMD_8111_LPC      0x7468
    … …  
    614660#define PCI_DEVICE_ID_DELL_RAC4         0x0012
    615661#define PCI_DEVICE_ID_DELL_PERC5        0x0015
     662
     663#define PCI_SUBVENDOR_ID_DELL           0x1028
    616664
    617665#define PCI_VENDOR_ID_MATROX            0x102B
    … …  
    866914#define PCI_DEVICE_ID_TI_X420           0xac8e
    867915#define PCI_DEVICE_ID_TI_XX20_FM        0xac8f
     916#define PCI_DEVICE_ID_TI_J721E          0xb00d
    868917#define PCI_DEVICE_ID_TI_DRA74x         0xb500
    869918#define PCI_DEVICE_ID_TI_DRA72x         0xb501
    … …  
    10611110#define PCI_DEVICE_ID_SGI_IOC3          0x0003
    10621111#define PCI_DEVICE_ID_SGI_LITHIUM       0x1002
    1063 #define PCI_DEVICE_ID_SGI_IOC4          0x100a
    10641112
    10651113#define PCI_VENDOR_ID_WINBOND           0x10ad
    … …  
    11021150
    11031151#define PCI_VENDOR_ID_AL                0x10b9
     1152#define PCI_DEVICE_ID_AL_M1489          0x1489
    11041153#define PCI_DEVICE_ID_AL_M1533          0x1533
    1105 #define PCI_DEVICE_ID_AL_M1535          0x1535
     1154#define PCI_DEVICE_ID_AL_M1535          0x1535
    11061155#define PCI_DEVICE_ID_AL_M1541          0x1541
    11071156#define PCI_DEVICE_ID_AL_M1563          0x1563
    … …  
    11301179#define PCI_VENDOR_ID_TCONRAD           0x10da
    11311180#define PCI_DEVICE_ID_TCONRAD_TOKENRING 0x0508
     1181
     1182#define PCI_VENDOR_ID_ROHM              0x10db
    11321183
    11331184#define PCI_VENDOR_ID_NVIDIA                    0x10de
    … …  
    13251376#define PCI_DEVICE_ID_NVIDIA_NFORCE_MCP77_IDE       0x0759
    13261377#define PCI_DEVICE_ID_NVIDIA_NFORCE_MCP73_SMBUS     0x07D8
     1378#define PCI_DEVICE_ID_NVIDIA_GEFORCE_320M           0x08A0
    13271379#define PCI_DEVICE_ID_NVIDIA_NFORCE_MCP79_SMBUS     0x0AA2
    13281380#define PCI_DEVICE_ID_NVIDIA_NFORCE_MCP89_SATA      0x0D85
    … …  
    15621614#define PCI_DEVICE_ID_SERVERWORKS_HT1100LD 0x0408
    15631615
     1616#define PCI_VENDOR_ID_ALTERA            0x1172
     1617
    15641618#define PCI_VENDOR_ID_SBE               0x1176
    15651619#define PCI_DEVICE_ID_SBE_WANXL100      0x0301
    … …  
    16641718
    16651719#define PCI_VENDOR_ID_PMC_Sierra        0x11f8
     1720#define PCI_VENDOR_ID_MICROSEMI         0x11f8
    16661721
    16671722#define PCI_VENDOR_ID_RP                0x11fe
    1668 #define PCI_DEVICE_ID_RP32INTF          0x0001
    1669 #define PCI_DEVICE_ID_RP8INTF           0x0002
    1670 #define PCI_DEVICE_ID_RP16INTF          0x0003
    1671 #define PCI_DEVICE_ID_RP4QUAD           0x0004
    1672 #define PCI_DEVICE_ID_RP8OCTA           0x0005
    1673 #define PCI_DEVICE_ID_RP8J              0x0006
    1674 #define PCI_DEVICE_ID_RP4J              0x0007
    1675 #define PCI_DEVICE_ID_RP8SNI            0x0008
    1676 #define PCI_DEVICE_ID_RP16SNI           0x0009
    1677 #define PCI_DEVICE_ID_RPP4              0x000A
    1678 #define PCI_DEVICE_ID_RPP8              0x000B
    1679 #define PCI_DEVICE_ID_RP4M              0x000D
    1680 #define PCI_DEVICE_ID_RP2_232           0x000E
    1681 #define PCI_DEVICE_ID_RP2_422           0x000F
    1682 #define PCI_DEVICE_ID_URP32INTF         0x0801
    1683 #define PCI_DEVICE_ID_URP8INTF          0x0802
    1684 #define PCI_DEVICE_ID_URP16INTF         0x0803
    1685 #define PCI_DEVICE_ID_URP8OCTA          0x0805
    1686 #define PCI_DEVICE_ID_UPCI_RM3_8PORT    0x080C
    1687 #define PCI_DEVICE_ID_UPCI_RM3_4PORT    0x080D
    1688 #define PCI_DEVICE_ID_CRP16INTF         0x0903
    16891723
    16901724#define PCI_VENDOR_ID_CYCLADES          0x120e
    1691 #define PCI_DEVICE_ID_CYCLOM_Y_Lo       0x0100
    1692 #define PCI_DEVICE_ID_CYCLOM_Y_Hi       0x0101
    1693 #define PCI_DEVICE_ID_CYCLOM_4Y_Lo      0x0102
    1694 #define PCI_DEVICE_ID_CYCLOM_4Y_Hi      0x0103
    1695 #define PCI_DEVICE_ID_CYCLOM_8Y_Lo      0x0104
    1696 #define PCI_DEVICE_ID_CYCLOM_8Y_Hi      0x0105
    1697 #define PCI_DEVICE_ID_CYCLOM_Z_Lo       0x0200
    1698 #define PCI_DEVICE_ID_CYCLOM_Z_Hi       0x0201
    16991725#define PCI_DEVICE_ID_PC300_RX_2        0x0300
    17001726#define PCI_DEVICE_ID_PC300_RX_1        0x0301
    … …  
    17381764
    17391765/* Allied Telesyn */
    1740 #define PCI_VENDOR_ID_AT                0x1259
     1766#define PCI_VENDOR_ID_AT                0x1259
    17411767#define PCI_SUBDEVICE_ID_AT_2700FX      0x2701
    17421768#define PCI_SUBDEVICE_ID_AT_2701FX      0x2703
     1769
     1770#define PCI_VENDOR_ID_ASIX              0x125b
     1771#define PCI_DEVICE_ID_ASIX_AX99100      0x9100
     1772#define PCI_DEVICE_ID_ASIX_AX99100_LB   0x9110
    17431773
    17441774#define PCI_VENDOR_ID_ESS               0x125d
    … …  
    18131843#define PCI_VENDOR_ID_NVIDIA_SGS        0x12d2
    18141844#define PCI_DEVICE_ID_NVIDIA_SGS_RIVA128 0x0018
     1845
     1846#define PCI_VENDOR_ID_PERICOM                   0x12D8
     1847#define PCI_DEVICE_ID_PERICOM_PI7C9X7951        0x7951
     1848#define PCI_DEVICE_ID_PERICOM_PI7C9X7952        0x7952
     1849#define PCI_DEVICE_ID_PERICOM_PI7C9X7954        0x7954
     1850#define PCI_DEVICE_ID_PERICOM_PI7C9X7958        0x7958
    18151851
    18161852#define PCI_SUBVENDOR_ID_CHASE_PCIFAST          0x12E0
    … …  
    19361972#define PCI_SUBDEVICE_ID_DIGIGRAM_LX6464ES_SERIAL_SUBSYSTEM     0xc001
    19371973#define PCI_SUBDEVICE_ID_DIGIGRAM_LX6464ES_CAE_SERIAL_SUBSYSTEM 0xc002
     1974#define PCI_SUBDEVICE_ID_DIGIGRAM_LX6464ESE_SERIAL_SUBSYSTEM            0xc021
     1975#define PCI_SUBDEVICE_ID_DIGIGRAM_LX6464ESE_CAE_SERIAL_SUBSYSTEM        0xc022
    19381976
    19391977#define PCI_VENDOR_ID_KAWASAKI          0x136b
    … …  
    19581996
    19591997#define PCI_VENDOR_ID_MOXA              0x1393
    1960 #define PCI_DEVICE_ID_MOXA_RC7000       0x0001
    1961 #define PCI_DEVICE_ID_MOXA_CP102        0x1020
    1962 #define PCI_DEVICE_ID_MOXA_CP102UL      0x1021
    1963 #define PCI_DEVICE_ID_MOXA_CP102U       0x1022
    1964 #define PCI_DEVICE_ID_MOXA_C104         0x1040
    1965 #define PCI_DEVICE_ID_MOXA_CP104U       0x1041
    1966 #define PCI_DEVICE_ID_MOXA_CP104JU      0x1042
    1967 #define PCI_DEVICE_ID_MOXA_CP104EL      0x1043
    1968 #define PCI_DEVICE_ID_MOXA_CT114        0x1140
    1969 #define PCI_DEVICE_ID_MOXA_CP114        0x1141
    1970 #define PCI_DEVICE_ID_MOXA_CP118U       0x1180
    1971 #define PCI_DEVICE_ID_MOXA_CP118EL      0x1181
    1972 #define PCI_DEVICE_ID_MOXA_CP132        0x1320
    1973 #define PCI_DEVICE_ID_MOXA_CP132U       0x1321
    1974 #define PCI_DEVICE_ID_MOXA_CP134U       0x1340
    1975 #define PCI_DEVICE_ID_MOXA_C168         0x1680
    1976 #define PCI_DEVICE_ID_MOXA_CP168U       0x1681
    1977 #define PCI_DEVICE_ID_MOXA_CP168EL      0x1682
    19781998#define PCI_DEVICE_ID_MOXA_CP204J       0x2040
    19791999#define PCI_DEVICE_ID_MOXA_C218         0x2180
    … …  
    20352055
    20362056#define PCI_VENDOR_ID_MICROGATE         0x13c0
    2037 #define PCI_DEVICE_ID_MICROGATE_USC     0x0010
    2038 #define PCI_DEVICE_ID_MICROGATE_SCA     0x0030
    20392057
    20402058#define PCI_VENDOR_ID_3WARE             0x13C1
    … …  
    20862104#define PCI_DEVICE_ID_VT1724            0x1724
    20872105
     2106#define PCI_VENDOR_ID_MICROSOFT         0x1414
     2107#define PCI_DEVICE_ID_HYPERV_VIDEO      0x5353
     2108
    20882109#define PCI_VENDOR_ID_OXSEMI            0x1415
    20892110#define PCI_DEVICE_ID_OXSEMI_12PCI840   0x8403
    … …  
    21062127#define PCI_VENDOR_ID_CHELSIO           0x1425
    21072128
     2129#define PCI_VENDOR_ID_EDIMAX            0x1432
     2130
    21082131#define PCI_VENDOR_ID_ADLINK            0x144a
    21092132
    … …  
    21152138
    21162139#define PCI_VENDOR_ID_MYRICOM           0x14c1
     2140
     2141#define PCI_VENDOR_ID_MEDIATEK          0x14c3
     2142#define PCI_DEVICE_ID_MEDIATEK_7629     0x7629
    21172143
    21182144#define PCI_VENDOR_ID_TITAN             0x14D2
    … …  
    23472373
    23482374#define PCI_VENDOR_ID_SYNOPSYS          0x16c3
     2375#define PCI_DEVICE_ID_SYNOPSYS_HAPSUSB3         0xabcd
     2376#define PCI_DEVICE_ID_SYNOPSYS_HAPSUSB3_AXI     0xabce
     2377#define PCI_DEVICE_ID_SYNOPSYS_HAPSUSB31        0xabcf
     2378#define PCI_DEVICE_ID_SYNOPSYS_EDDA     0xedda
     2379
     2380#define PCI_VENDOR_ID_USR               0x16ec
    23492381
    23502382#define PCI_VENDOR_ID_VITESSE           0x1725
    … …  
    23822414#define PCI_DEVICE_ID_RDC_D1010         0x1010
    23832415
     2416#define PCI_VENDOR_ID_GLI               0x17a0
     2417
    23842418#define PCI_VENDOR_ID_LENOVO            0x17aa
     2419
     2420#define PCI_VENDOR_ID_QCOM              0x17cb
     2421
     2422#define PCI_VENDOR_ID_CDNS              0x17cd
    23852423
    23862424#define PCI_VENDOR_ID_ARECA             0x17d3
    … …  
    24342472#define PCI_DEVICE_ID_TDI_EHCI          0x0101
    24352473
    2436 #define PCI_VENDOR_ID_FREESCALE         0x1957
     2474#define PCI_VENDOR_ID_FREESCALE         0x1957  /* duplicate: NXP */
     2475#define PCI_VENDOR_ID_NXP               0x1957  /* duplicate: FREESCALE */
    24372476#define PCI_DEVICE_ID_MPC8308           0xc006
    24382477#define PCI_DEVICE_ID_MPC8315E          0x00b4
    … …  
    25252564#define PCI_DEVICE_ID_KORENIX_JETCARDF3 0x17ff
    25262565
    2527 #define PCI_VENDOR_ID_HUAWEI            0x19e5
     2566#define PCI_VENDOR_ID_HUAWEI            0x19e5
     2567#define PCI_DEVICE_ID_HUAWEI_ZIP_VF     0xa251
     2568#define PCI_DEVICE_ID_HUAWEI_SEC_VF     0xa256
     2569#define PCI_DEVICE_ID_HUAWEI_HPRE_VF    0xa259
    25282570
    25292571#define PCI_VENDOR_ID_NETRONOME         0x19ee
    2530 #define PCI_DEVICE_ID_NETRONOME_NFP3200 0x3200
    2531 #define PCI_DEVICE_ID_NETRONOME_NFP3240 0x3240
     2572#define PCI_DEVICE_ID_NETRONOME_NFP3800 0x3800
    25322573#define PCI_DEVICE_ID_NETRONOME_NFP4000 0x4000
     2574#define PCI_DEVICE_ID_NETRONOME_NFP5000 0x5000
    25332575#define PCI_DEVICE_ID_NETRONOME_NFP6000 0x6000
     2576#define PCI_DEVICE_ID_NETRONOME_NFP3800_VF      0x3803
    25342577#define PCI_DEVICE_ID_NETRONOME_NFP6000_VF      0x6003
    25352578
    … …  
    25442587#define PCI_VENDOR_ID_ASMEDIA           0x1b21
    25452588
     2589#define PCI_VENDOR_ID_REDHAT            0x1b36
     2590
     2591#define PCI_VENDOR_ID_SILICOM_DENMARK   0x1c2c
     2592
     2593#define PCI_VENDOR_ID_AMAZON_ANNAPURNA_LABS     0x1c36
     2594
    25462595#define PCI_VENDOR_ID_CIRCUITCO         0x1cc8
    25472596#define PCI_SUBSYSTEM_ID_CIRCUITCO_MINNOWBOARD  0x0001
     2597
     2598#define PCI_VENDOR_ID_AMAZON            0x1d0f
     2599
     2600#define PCI_VENDOR_ID_ZHAOXIN           0x1d17
     2601
     2602#define PCI_VENDOR_ID_HYGON             0x1d94
     2603
     2604#define PCI_VENDOR_ID_FUNGIBLE          0x1dad
     2605
     2606#define PCI_VENDOR_ID_HXT               0x1dbf
    25482607
    25492608#define PCI_VENDOR_ID_TEKRAM            0x1de1
    … …  
    25542613#define PCI_DEVICE_ID_TEHUTI_3010       0x3010
    25552614#define PCI_DEVICE_ID_TEHUTI_3014       0x3014
     2615
     2616#define PCI_VENDOR_ID_SUNIX             0x1fd4
     2617#define PCI_DEVICE_ID_SUNIX_1999        0x1999
    25562618
    25572619#define PCI_VENDOR_ID_HINT             0x3388
    … …  
    25942656#define PCI_DEVICE_ID_DCI_PCCOM2        0x0004
    25952657
     2658#define PCI_VENDOR_ID_GLENFLY           0x6766
     2659
    25962660#define PCI_VENDOR_ID_INTEL             0x8086
    25972661#define PCI_DEVICE_ID_INTEL_EESSC       0x0008
     2662#define PCI_DEVICE_ID_INTEL_HDA_CML_LP  0x02c8
    25982663#define PCI_DEVICE_ID_INTEL_PXHD_0      0x0320
    25992664#define PCI_DEVICE_ID_INTEL_PXHD_1      0x0321
    26002665#define PCI_DEVICE_ID_INTEL_PXH_0       0x0329
    2601 #define PCI_DEVICE_ID_INTEL_PXH_1       0x032A
    2602 #define PCI_DEVICE_ID_INTEL_PXHV        0x032C
     2666#define PCI_DEVICE_ID_INTEL_PXH_1       0x032a
     2667#define PCI_DEVICE_ID_INTEL_PXHV        0x032c
    26032668#define PCI_DEVICE_ID_INTEL_80332_0     0x0330
    26042669#define PCI_DEVICE_ID_INTEL_80332_1     0x0332
    26052670#define PCI_DEVICE_ID_INTEL_80333_0     0x0370
    26062671#define PCI_DEVICE_ID_INTEL_80333_1     0x0372
     2672#define PCI_DEVICE_ID_INTEL_QAT_DH895XCC        0x0435
     2673#define PCI_DEVICE_ID_INTEL_QAT_DH895XCC_VF     0x0443
    26072674#define PCI_DEVICE_ID_INTEL_82375       0x0482
    26082675#define PCI_DEVICE_ID_INTEL_82424       0x0483
    26092676#define PCI_DEVICE_ID_INTEL_82378       0x0484
     2677#define PCI_DEVICE_ID_INTEL_82425       0x0486
     2678#define PCI_DEVICE_ID_INTEL_HDA_CML_H   0x06c8
    26102679#define PCI_DEVICE_ID_INTEL_MRST_SD0    0x0807
    26112680#define PCI_DEVICE_ID_INTEL_MRST_SD1    0x0808
     2681#define PCI_DEVICE_ID_INTEL_HDA_OAKTRAIL        0x080a
    26122682#define PCI_DEVICE_ID_INTEL_MFD_SD      0x0820
    26132683#define PCI_DEVICE_ID_INTEL_MFD_SDIO1   0x0821
    … …  
    26152685#define PCI_DEVICE_ID_INTEL_MFD_EMMC0   0x0823
    26162686#define PCI_DEVICE_ID_INTEL_MFD_EMMC1   0x0824
    2617 #define PCI_DEVICE_ID_INTEL_MRST_SD2    0x084F
    2618 #define PCI_DEVICE_ID_INTEL_QUARK_X1000_ILB     0x095E
     2687#define PCI_DEVICE_ID_INTEL_MRST_SD2    0x084f
     2688#define PCI_DEVICE_ID_INTEL_QUARK_X1000_ILB     0x095e
    26192689#define PCI_DEVICE_ID_INTEL_I960        0x0960
    26202690#define PCI_DEVICE_ID_INTEL_I960RM      0x0962
     2691#define PCI_DEVICE_ID_INTEL_HDA_HSW_0   0x0a0c
     2692#define PCI_DEVICE_ID_INTEL_DSA_SPR0    0x0b25
     2693#define PCI_DEVICE_ID_INTEL_HDA_HSW_2   0x0c0c
    26212694#define PCI_DEVICE_ID_INTEL_CENTERTON_ILB       0x0c60
     2695#define PCI_DEVICE_ID_INTEL_IAX_SPR0    0x0cfe
     2696#define PCI_DEVICE_ID_INTEL_HDA_HSW_3   0x0d0c
     2697#define PCI_DEVICE_ID_INTEL_HDA_BYT     0x0f04
     2698#define PCI_DEVICE_ID_INTEL_SST_BYT     0x0f28
    26222699#define PCI_DEVICE_ID_INTEL_8257X_SOL   0x1062
    26232700#define PCI_DEVICE_ID_INTEL_82573E_SOL  0x1085
    2624 #define PCI_DEVICE_ID_INTEL_82573L_SOL  0x108F
     2701#define PCI_DEVICE_ID_INTEL_82573L_SOL  0x108f
    26252702#define PCI_DEVICE_ID_INTEL_82815_MC    0x1130
    26262703#define PCI_DEVICE_ID_INTEL_82815_CGC   0x1132
     2704#define PCI_DEVICE_ID_INTEL_SST_TNG     0x119a
    26272705#define PCI_DEVICE_ID_INTEL_82092AA_0   0x1221
    2628 #define PCI_DEVICE_ID_INTEL_7505_0      0x2550
    2629 #define PCI_DEVICE_ID_INTEL_7205_0      0x255d
    26302706#define PCI_DEVICE_ID_INTEL_82437       0x122d
    26312707#define PCI_DEVICE_ID_INTEL_82371FB_0   0x122e
    … …  
    26532729#define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_4C_NHI     0x1577
    26542730#define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_4C_BRIDGE  0x1578
     2731#define PCI_DEVICE_ID_INTEL_HDA_BDW     0x160c
    26552732#define PCI_DEVICE_ID_INTEL_80960_RP    0x1960
     2733#define PCI_DEVICE_ID_INTEL_QAT_C3XXX   0x19e2
     2734#define PCI_DEVICE_ID_INTEL_QAT_C3XXX_VF        0x19e3
    26562735#define PCI_DEVICE_ID_INTEL_82840_HB    0x1a21
    26572736#define PCI_DEVICE_ID_INTEL_82845_HB    0x1a30
    26582737#define PCI_DEVICE_ID_INTEL_IOAT        0x1a38
     2738#define PCI_DEVICE_ID_INTEL_HDA_CPT     0x1c20
    26592739#define PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_MIN 0x1c41
    26602740#define PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_MAX 0x1c5f
     2741#define PCI_DEVICE_ID_INTEL_HDA_PBG     0x1d20
    26612742#define PCI_DEVICE_ID_INTEL_PATSBURG_LPC_0      0x1d40
    26622743#define PCI_DEVICE_ID_INTEL_PATSBURG_LPC_1      0x1d41
     2744#define PCI_DEVICE_ID_INTEL_HDA_PPT     0x1e20
    26632745#define PCI_DEVICE_ID_INTEL_PANTHERPOINT_XHCI   0x1e31
    26642746#define PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_MIN        0x1e40
    26652747#define PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_MAX        0x1e5f
     2748#define PCI_DEVICE_ID_INTEL_VMD_201D    0x201d
     2749#define PCI_DEVICE_ID_INTEL_HDA_BSW     0x2284
     2750#define PCI_DEVICE_ID_INTEL_SST_BSW     0x22a8
    26662751#define PCI_DEVICE_ID_INTEL_DH89XXCC_LPC_MIN    0x2310
    26672752#define PCI_DEVICE_ID_INTEL_DH89XXCC_LPC_MAX    0x231f
    … …  
    27132798#define PCI_DEVICE_ID_INTEL_82801EB_12  0x24dc
    27142799#define PCI_DEVICE_ID_INTEL_82801EB_13  0x24dd
    2715 #define PCI_DEVICE_ID_INTEL_ESB_1       0x25a1
    2716 #define PCI_DEVICE_ID_INTEL_ESB_2       0x25a2
    2717 #define PCI_DEVICE_ID_INTEL_ESB_4       0x25a4
    2718 #define PCI_DEVICE_ID_INTEL_ESB_5       0x25a6
    2719 #define PCI_DEVICE_ID_INTEL_ESB_9       0x25ab
    2720 #define PCI_DEVICE_ID_INTEL_ESB_10      0x25ac
    27212800#define PCI_DEVICE_ID_INTEL_82820_HB    0x2500
    27222801#define PCI_DEVICE_ID_INTEL_82820_UP_HB 0x2501
    … …  
    27242803#define PCI_DEVICE_ID_INTEL_82860_HB    0x2531
    27252804#define PCI_DEVICE_ID_INTEL_E7501_MCH   0x254c
     2805#define PCI_DEVICE_ID_INTEL_7505_0      0x2550
     2806#define PCI_DEVICE_ID_INTEL_7205_0      0x255d
    27262807#define PCI_DEVICE_ID_INTEL_82845G_HB   0x2560
    27272808#define PCI_DEVICE_ID_INTEL_82845G_IG   0x2562
    … …  
    27332814#define PCI_DEVICE_ID_INTEL_82915GM_HB  0x2590
    27342815#define PCI_DEVICE_ID_INTEL_82915GM_IG  0x2592
    2735 #define PCI_DEVICE_ID_INTEL_5000_ERR    0x25F0
    2736 #define PCI_DEVICE_ID_INTEL_5000_FBD0   0x25F5
    2737 #define PCI_DEVICE_ID_INTEL_5000_FBD1   0x25F6
    2738 #define PCI_DEVICE_ID_INTEL_82945G_HB   0x2770
    2739 #define PCI_DEVICE_ID_INTEL_82945G_IG   0x2772
    2740 #define PCI_DEVICE_ID_INTEL_3000_HB     0x2778
    2741 #define PCI_DEVICE_ID_INTEL_82945GM_HB  0x27A0
    2742 #define PCI_DEVICE_ID_INTEL_82945GM_IG  0x27A2
     2816#define PCI_DEVICE_ID_INTEL_ESB_1       0x25a1
     2817#define PCI_DEVICE_ID_INTEL_ESB_2       0x25a2
     2818#define PCI_DEVICE_ID_INTEL_ESB_4       0x25a4
     2819#define PCI_DEVICE_ID_INTEL_ESB_5       0x25a6
     2820#define PCI_DEVICE_ID_INTEL_ESB_9       0x25ab
     2821#define PCI_DEVICE_ID_INTEL_ESB_10      0x25ac
     2822#define PCI_DEVICE_ID_INTEL_5000_ERR    0x25f0
     2823#define PCI_DEVICE_ID_INTEL_5000_FBD0   0x25f5
     2824#define PCI_DEVICE_ID_INTEL_5000_FBD1   0x25f6
    27432825#define PCI_DEVICE_ID_INTEL_ICH6_0      0x2640
    27442826#define PCI_DEVICE_ID_INTEL_ICH6_1      0x2641
    27452827#define PCI_DEVICE_ID_INTEL_ICH6_2      0x2642
     2828#define PCI_DEVICE_ID_INTEL_HDA_ICH6    0x2668
    27462829#define PCI_DEVICE_ID_INTEL_ICH6_16     0x266a
    27472830#define PCI_DEVICE_ID_INTEL_ICH6_17     0x266d
    … …  
    27502833#define PCI_DEVICE_ID_INTEL_ESB2_0      0x2670
    27512834#define PCI_DEVICE_ID_INTEL_ESB2_14     0x2698
     2835#define PCI_DEVICE_ID_INTEL_HDA_ESB2    0x269a
    27522836#define PCI_DEVICE_ID_INTEL_ESB2_17     0x269b
    27532837#define PCI_DEVICE_ID_INTEL_ESB2_18     0x269e
     2838#define PCI_DEVICE_ID_INTEL_82945G_HB   0x2770
     2839#define PCI_DEVICE_ID_INTEL_82945G_IG   0x2772
     2840#define PCI_DEVICE_ID_INTEL_3000_HB     0x2778
     2841#define PCI_DEVICE_ID_INTEL_82945GM_HB  0x27a0
     2842#define PCI_DEVICE_ID_INTEL_82945GM_IG  0x27a2
     2843#define PCI_DEVICE_ID_INTEL_ICH7_30     0x27b0
    27542844#define PCI_DEVICE_ID_INTEL_ICH7_0      0x27b8
    27552845#define PCI_DEVICE_ID_INTEL_ICH7_1      0x27b9
    2756 #define PCI_DEVICE_ID_INTEL_ICH7_30     0x27b0
    27572846#define PCI_DEVICE_ID_INTEL_TGP_LPC     0x27bc
    27582847#define PCI_DEVICE_ID_INTEL_ICH7_31     0x27bd
     2848#define PCI_DEVICE_ID_INTEL_HDA_ICH7    0x27d8
    27592849#define PCI_DEVICE_ID_INTEL_ICH7_17     0x27da
    27602850#define PCI_DEVICE_ID_INTEL_ICH7_19     0x27dd
    … …  
    27672857#define PCI_DEVICE_ID_INTEL_ICH8_4      0x2815
    27682858#define PCI_DEVICE_ID_INTEL_ICH8_5      0x283e
     2859#define PCI_DEVICE_ID_INTEL_HDA_ICH8    0x284b
    27692860#define PCI_DEVICE_ID_INTEL_ICH8_6      0x2850
     2861#define PCI_DEVICE_ID_INTEL_VMD_28C0    0x28c0
    27702862#define PCI_DEVICE_ID_INTEL_ICH9_0      0x2910
    2771 #define PCI_DEVICE_ID_INTEL_ICH9_1      0x2917
    27722863#define PCI_DEVICE_ID_INTEL_ICH9_2      0x2912
    27732864#define PCI_DEVICE_ID_INTEL_ICH9_3      0x2913
    27742865#define PCI_DEVICE_ID_INTEL_ICH9_4      0x2914
     2866#define PCI_DEVICE_ID_INTEL_ICH9_7      0x2916
     2867#define PCI_DEVICE_ID_INTEL_ICH9_1      0x2917
     2868#define PCI_DEVICE_ID_INTEL_ICH9_8      0x2918
    27752869#define PCI_DEVICE_ID_INTEL_ICH9_5      0x2919
    27762870#define PCI_DEVICE_ID_INTEL_ICH9_6      0x2930
    2777 #define PCI_DEVICE_ID_INTEL_ICH9_7      0x2916
    2778 #define PCI_DEVICE_ID_INTEL_ICH9_8      0x2918
     2871#define PCI_DEVICE_ID_INTEL_HDA_ICH9_0  0x293e
     2872#define PCI_DEVICE_ID_INTEL_HDA_ICH9_1  0x293f
    27792873#define PCI_DEVICE_ID_INTEL_I7_MCR      0x2c18
    27802874#define PCI_DEVICE_ID_INTEL_I7_MC_TAD   0x2c19
    … …  
    27932887#define PCI_DEVICE_ID_INTEL_I7_MC_CH2_RANK  0x2c32
    27942888#define PCI_DEVICE_ID_INTEL_I7_MC_CH2_TC    0x2c33
     2889#define PCI_DEVICE_ID_INTEL_I7_NONCORE_ALT 0x2c40
    27952890#define PCI_DEVICE_ID_INTEL_I7_NONCORE  0x2c41
    2796 #define PCI_DEVICE_ID_INTEL_I7_NONCORE_ALT 0x2c40
    27972891#define PCI_DEVICE_ID_INTEL_LYNNFIELD_NONCORE     0x2c50
    27982892#define PCI_DEVICE_ID_INTEL_LYNNFIELD_NONCORE_ALT 0x2c51
    … …  
    28032897#define PCI_DEVICE_ID_INTEL_LYNNFIELD_MCR         0x2c98
    28042898#define PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_TAD      0x2c99
    2805 #define PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_TEST     0x2c9C
     2899#define PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_TEST     0x2c9c
    28062900#define PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH0_CTRL 0x2ca0
    28072901#define PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH0_ADDR 0x2ca1
    … …  
    28282922#define PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH2_RANK_REV2  0x2db2
    28292923#define PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH2_TC_REV2    0x2db3
     2924#define PCI_DEVICE_ID_INTEL_HDA_GML     0x3198
    28302925#define PCI_DEVICE_ID_INTEL_82855PM_HB  0x3340
    28312926#define PCI_DEVICE_ID_INTEL_IOAT_TBG4   0x3429
    … …  
    28382933#define PCI_DEVICE_ID_INTEL_IOAT_TBG2   0x3432
    28392934#define PCI_DEVICE_ID_INTEL_IOAT_TBG3   0x3433
     2935#define PCI_DEVICE_ID_INTEL_HDA_ICL_LP  0x34c8
    28402936#define PCI_DEVICE_ID_INTEL_82830_HB    0x3575
    28412937#define PCI_DEVICE_ID_INTEL_82830_CGC   0x3577
     2938#define PCI_DEVICE_ID_INTEL_82855GM_HB  0x3580
     2939#define PCI_DEVICE_ID_INTEL_82855GM_IG  0x3582
    28422940#define PCI_DEVICE_ID_INTEL_82854_HB    0x358c
    28432941#define PCI_DEVICE_ID_INTEL_82854_IG    0x358e
    2844 #define PCI_DEVICE_ID_INTEL_82855GM_HB  0x3580
    2845 #define PCI_DEVICE_ID_INTEL_82855GM_IG  0x3582
    28462942#define PCI_DEVICE_ID_INTEL_E7520_MCH   0x3590
    28472943#define PCI_DEVICE_ID_INTEL_E7320_MCH   0x3592
    … …  
    28532949#define PCI_DEVICE_ID_INTEL_MCH_PC1     0x359a
    28542950#define PCI_DEVICE_ID_INTEL_E7525_MCH   0x359e
     2951#define PCI_DEVICE_ID_INTEL_IOAT_CNB    0x360b
     2952#define PCI_DEVICE_ID_INTEL_FBD_CNB     0x360c
    28552953#define PCI_DEVICE_ID_INTEL_I7300_MCH_ERR 0x360c
    28562954#define PCI_DEVICE_ID_INTEL_I7300_MCH_FB0 0x360f
    28572955#define PCI_DEVICE_ID_INTEL_I7300_MCH_FB1 0x3610
    2858 #define PCI_DEVICE_ID_INTEL_IOAT_CNB    0x360b
    2859 #define PCI_DEVICE_ID_INTEL_FBD_CNB     0x360c
    28602956#define PCI_DEVICE_ID_INTEL_IOAT_JSF0   0x3710
    28612957#define PCI_DEVICE_ID_INTEL_IOAT_JSF1   0x3711
    … …  
    28682964#define PCI_DEVICE_ID_INTEL_IOAT_JSF8   0x3718
    28692965#define PCI_DEVICE_ID_INTEL_IOAT_JSF9   0x3719
     2966#define PCI_DEVICE_ID_INTEL_QAT_C62X    0x37c8
     2967#define PCI_DEVICE_ID_INTEL_QAT_C62X_VF 0x37c9
     2968#define PCI_DEVICE_ID_INTEL_HDA_ICL_N   0x38c8
    28702969#define PCI_DEVICE_ID_INTEL_ICH10_0     0x3a14
    28712970#define PCI_DEVICE_ID_INTEL_ICH10_1     0x3a16
    … …  
    28732972#define PCI_DEVICE_ID_INTEL_ICH10_3     0x3a1a
    28742973#define PCI_DEVICE_ID_INTEL_ICH10_4     0x3a30
     2974#define PCI_DEVICE_ID_INTEL_HDA_ICH10_0 0x3a3e
    28752975#define PCI_DEVICE_ID_INTEL_ICH10_5     0x3a60
     2976#define PCI_DEVICE_ID_INTEL_HDA_ICH10_1 0x3a6e
    28762977#define PCI_DEVICE_ID_INTEL_5_3400_SERIES_LPC_MIN       0x3b00
    28772978#define PCI_DEVICE_ID_INTEL_5_3400_SERIES_LPC_MAX       0x3b1f
     2979#define PCI_DEVICE_ID_INTEL_HDA_5_3400_SERIES_0 0x3b56
     2980#define PCI_DEVICE_ID_INTEL_HDA_5_3400_SERIES_1 0x3b57
    28782981#define PCI_DEVICE_ID_INTEL_IOAT_SNB0   0x3c20
    28792982#define PCI_DEVICE_ID_INTEL_IOAT_SNB1   0x3c21
    … …  
    28862989#define PCI_DEVICE_ID_INTEL_IOAT_SNB8   0x3c2e
    28872990#define PCI_DEVICE_ID_INTEL_IOAT_SNB9   0x3c2f
    2888 #define PCI_DEVICE_ID_INTEL_UNC_HA      0x3c46
    2889 #define PCI_DEVICE_ID_INTEL_UNC_IMC0    0x3cb0
    2890 #define PCI_DEVICE_ID_INTEL_UNC_IMC1    0x3cb1
    2891 #define PCI_DEVICE_ID_INTEL_UNC_IMC2    0x3cb4
    2892 #define PCI_DEVICE_ID_INTEL_UNC_IMC3    0x3cb5
    28932991#define PCI_DEVICE_ID_INTEL_UNC_QPI0    0x3c41
    28942992#define PCI_DEVICE_ID_INTEL_UNC_QPI1    0x3c42
    … …  
    28962994#define PCI_DEVICE_ID_INTEL_UNC_R3QPI0  0x3c44
    28972995#define PCI_DEVICE_ID_INTEL_UNC_R3QPI1  0x3c45
     2996#define PCI_DEVICE_ID_INTEL_UNC_HA      0x3c46
    28982997#define PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_RAS     0x3c71  /* 15.1 */
    28992998#define PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_ERR0    0x3c72  /* 16.2 */
    … …  
    29073006#define PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD2    0x3cac  /* 15.4 */
    29083007#define PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD3    0x3cad  /* 15.5 */
     3008#define PCI_DEVICE_ID_INTEL_UNC_IMC0    0x3cb0
     3009#define PCI_DEVICE_ID_INTEL_UNC_IMC1    0x3cb1
     3010#define PCI_DEVICE_ID_INTEL_UNC_IMC2    0x3cb4
     3011#define PCI_DEVICE_ID_INTEL_UNC_IMC3    0x3cb5
    29093012#define PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_DDRIO   0x3cb8  /* 17.0 */
    29103013#define PCI_DEVICE_ID_INTEL_JAKETOWN_UBOX       0x3ce0
    … …  
    29123015#define PCI_DEVICE_ID_INTEL_SBRIDGE_BR          0x3cf5  /* 13.6 */
    29133016#define PCI_DEVICE_ID_INTEL_SBRIDGE_SAD1        0x3cf6  /* 12.7 */
     3017#define PCI_DEVICE_ID_INTEL_HDA_ICL_H   0x3dc8
    29143018#define PCI_DEVICE_ID_INTEL_IOAT_SNB    0x402f
     3019#define PCI_DEVICE_ID_INTEL_5400_ERR    0x4030
     3020#define PCI_DEVICE_ID_INTEL_5400_FBD0   0x4035
     3021#define PCI_DEVICE_ID_INTEL_5400_FBD1   0x4036
     3022#define PCI_DEVICE_ID_INTEL_HDA_TGL_H   0x43c8
     3023#define PCI_DEVICE_ID_INTEL_HDA_DG1     0x490d
     3024#define PCI_DEVICE_ID_INTEL_HDA_EHL_0   0x4b55
     3025#define PCI_DEVICE_ID_INTEL_HDA_EHL_3   0x4b58
     3026#define PCI_DEVICE_ID_INTEL_HDA_JSL_N   0x4dc8
     3027#define PCI_DEVICE_ID_INTEL_HDA_DG2_0   0x4f90
     3028#define PCI_DEVICE_ID_INTEL_HDA_DG2_1   0x4f91
     3029#define PCI_DEVICE_ID_INTEL_HDA_DG2_2   0x4f92
     3030#define PCI_DEVICE_ID_INTEL_EP80579_0   0x5031
     3031#define PCI_DEVICE_ID_INTEL_EP80579_1   0x5032
     3032#define PCI_DEVICE_ID_INTEL_HDA_ADL_P   0x51c8
     3033#define PCI_DEVICE_ID_INTEL_HDA_ADL_PS  0x51c9
     3034#define PCI_DEVICE_ID_INTEL_HDA_RPL_P_0 0x51ca
     3035#define PCI_DEVICE_ID_INTEL_HDA_RPL_P_1 0x51cb
     3036#define PCI_DEVICE_ID_INTEL_HDA_ADL_M   0x51cc
     3037#define PCI_DEVICE_ID_INTEL_HDA_ADL_PX  0x51cd
     3038#define PCI_DEVICE_ID_INTEL_HDA_RPL_M   0x51ce
     3039#define PCI_DEVICE_ID_INTEL_HDA_RPL_PX  0x51cf
     3040#define PCI_DEVICE_ID_INTEL_HDA_ADL_N   0x54c8
     3041#define PCI_DEVICE_ID_INTEL_HDA_APL     0x5a98
    29153042#define PCI_DEVICE_ID_INTEL_5100_16     0x65f0
    29163043#define PCI_DEVICE_ID_INTEL_5100_19     0x65f3
    29173044#define PCI_DEVICE_ID_INTEL_5100_21     0x65f5
    29183045#define PCI_DEVICE_ID_INTEL_5100_22     0x65f6
    2919 #define PCI_DEVICE_ID_INTEL_5400_ERR    0x4030
    2920 #define PCI_DEVICE_ID_INTEL_5400_FBD0   0x4035
    2921 #define PCI_DEVICE_ID_INTEL_5400_FBD1   0x4036
    29223046#define PCI_DEVICE_ID_INTEL_IOAT_SCNB   0x65ff
    2923 #define PCI_DEVICE_ID_INTEL_EP80579_0   0x5031
    2924 #define PCI_DEVICE_ID_INTEL_EP80579_1   0x5032
    29253047#define PCI_DEVICE_ID_INTEL_82371SB_0   0x7000
    29263048#define PCI_DEVICE_ID_INTEL_82371SB_1   0x7010
    … …  
    29513073#define PCI_DEVICE_ID_INTEL_82443GX_2   0x71a2
    29523074#define PCI_DEVICE_ID_INTEL_82372FB_1   0x7601
     3075#define PCI_DEVICE_ID_INTEL_HDA_ARL     0x7728
     3076#define PCI_DEVICE_ID_INTEL_HDA_RPL_S   0x7a50
     3077#define PCI_DEVICE_ID_INTEL_HDA_ADL_S   0x7ad0
     3078#define PCI_DEVICE_ID_INTEL_HDA_MTL     0x7e28
     3079#define PCI_DEVICE_ID_INTEL_HDA_ARL_S   0x7f50
    29533080#define PCI_DEVICE_ID_INTEL_SCH_LPC     0x8119
    29543081#define PCI_DEVICE_ID_INTEL_SCH_IDE     0x811a
     3082#define PCI_DEVICE_ID_INTEL_HDA_POULSBO 0x811b
    29553083#define PCI_DEVICE_ID_INTEL_E6XX_CU     0x8183
    29563084#define PCI_DEVICE_ID_INTEL_ITC_LPC     0x8186
    … …  
    29613089#define PCI_DEVICE_ID_INTEL_84460GX     0x84ea
    29623090#define PCI_DEVICE_ID_INTEL_IXP4XX      0x8500
     3091#define PCI_DEVICE_ID_INTEL_HDA_LPT     0x8c20
     3092#define PCI_DEVICE_ID_INTEL_HDA_9_SERIES        0x8ca0
     3093#define PCI_DEVICE_ID_INTEL_HDA_WBG_0   0x8d20
     3094#define PCI_DEVICE_ID_INTEL_HDA_WBG_1   0x8d21
    29633095#define PCI_DEVICE_ID_INTEL_IXP2800     0x9004
     3096#define PCI_DEVICE_ID_INTEL_HDA_LKF     0x98c8
     3097#define PCI_DEVICE_ID_INTEL_VMD_9A0B    0x9a0b
     3098#define PCI_DEVICE_ID_INTEL_HDA_LPT_LP_0        0x9c20
     3099#define PCI_DEVICE_ID_INTEL_HDA_LPT_LP_1        0x9c21
     3100#define PCI_DEVICE_ID_INTEL_HDA_WPT_LP  0x9ca0
     3101#define PCI_DEVICE_ID_INTEL_HDA_SKL_LP  0x9d70
     3102#define PCI_DEVICE_ID_INTEL_HDA_KBL_LP  0x9d71
     3103#define PCI_DEVICE_ID_INTEL_HDA_CNL_LP  0x9dc8
     3104#define PCI_DEVICE_ID_INTEL_HDA_TGL_LP  0xa0c8
     3105#define PCI_DEVICE_ID_INTEL_HDA_SKL     0xa170
     3106#define PCI_DEVICE_ID_INTEL_HDA_KBL     0xa171
     3107#define PCI_DEVICE_ID_INTEL_HDA_LBG_0   0xa1f0
     3108#define PCI_DEVICE_ID_INTEL_HDA_LBG_1   0xa270
     3109#define PCI_DEVICE_ID_INTEL_HDA_KBL_H   0xa2f0
     3110#define PCI_DEVICE_ID_INTEL_HDA_CNL_H   0xa348
     3111#define PCI_DEVICE_ID_INTEL_HDA_CML_S   0xa3f0
     3112#define PCI_DEVICE_ID_INTEL_HDA_LNL_P   0xa828
    29643113#define PCI_DEVICE_ID_INTEL_S21152BB    0xb152
     3114#define PCI_DEVICE_ID_INTEL_HDA_CML_R   0xf0c8
     3115#define PCI_DEVICE_ID_INTEL_HDA_RKL_S   0xf1c8
     3116
     3117#define PCI_VENDOR_ID_WANGXUN           0x8088
    29653118
    29663119#define PCI_VENDOR_ID_SCALEMP           0x8686
    … …  
    30443197#define PCI_VENDOR_ID_3COM_2            0xa727
    30453198
     3199#define PCI_VENDOR_ID_SOLIDRUN          0xd063
     3200
    30463201#define PCI_VENDOR_ID_DIGIUM            0xd161
    30473202#define PCI_DEVICE_ID_DIGIUM_HFC4S      0xb410

  • GPL/trunk/include/linux/pgtable.h

    r679 r772  
    22#define _LINUX_PGTABLE_H
    33
     4
    45#endif /* _LINUX_PGTABLE_H */

  • GPL/trunk/include/linux/pm.h

    r717 r772  
    247247        struct list_head        entry;
    248248        enum rpm_status         runtime_status;
     249        unsigned int            runtime_auto:1;
    249250};
    250251
    … …  
    294295 * to RAM and hibernation.
    295296 */
     297#define DEFINE_SIMPLE_DEV_PM_OPS(name, suspend_fn, resume_fn) \
     298const struct dev_pm_ops name = { \
     299        SET_SYSTEM_SLEEP_PM_OPS(suspend_fn, resume_fn) \
     300}
     301
     302
    296303#define SIMPLE_DEV_PM_OPS(name, suspend_fn, resume_fn) \
    297304const struct dev_pm_ops name = { \
    … …  
    341348#define PMSG_THAW       0
    342349#define PMSG_RESTORE    0
    343 
     350#define pm_sleep_ptr(_ptr) _ptr
    344351#endif /* _LINUX_PM_H */

  • GPL/trunk/include/linux/regmap.h

    r679 r772  
    4343        REGCACHE_NONE,
    4444        REGCACHE_RBTREE,
    45         REGCACHE_COMPRESSED,
    4645        REGCACHE_FLAT,
     46        REGCACHE_MAPLE,
    4747};
    4848
    … …  
    11201120void regcache_cache_bypass(struct regmap *map, bool enable);
    11211121void regcache_mark_dirty(struct regmap *map);
     1122bool regcache_reg_cached(struct regmap *map, unsigned int reg);
    11221123
    11231124bool regmap_check_range_table(struct regmap *map, unsigned int reg,

  • GPL/trunk/include/linux/rwsem.h

    r695 r772  
    1414#define up_read(x) up(x)
    1515#define up_write(x) up(x)
    16 #define downgrade_write(a)
     16static inline void downgrade_write(struct rw_semaphore *sem) {}
    1717
    1818static inline int down_write_trylock(struct rw_semaphore *sem) {return 0;}

  • GPL/trunk/include/linux/slab.h

    r695 r772  
    8787#endif
    8888
    89 void *kzalloc(size_t n, gfp_t gfp_flags);
     89/**
     90 * kzalloc - allocate memory. The memory is set to zero.
     91 * @size: how many bytes of memory are required.
     92 * @flags: the type of memory to allocate (see kmalloc).
     93 */
     94static inline void *kzalloc(size_t size, gfp_t flags)
     95{
     96        return kmalloc(size, flags | __GFP_ZERO);
     97}
     98
    9099void *kcalloc(size_t n, size_t size, unsigned int __nocast gfp_flags);
    91100void *krealloc(const void *, size_t, gfp_t);
    … …  
    140149};
    141150
    142 #define kvzalloc kzalloc
    143151size_t ksize(const void *);
    144152

  • GPL/trunk/include/linux/stddef.h

    r305 r772  
    1010
    1111#undef offsetof
    12 #define offsetof(TYPE, MEMBER) ((size_t) &((TYPE *)0)->MEMBER)
     12#define offsetof(__typ,__id) ((size_t)&(((__typ*)0)->__id))
    1313
    1414#endif

  • GPL/trunk/include/linux/string.h

    r717 r772  
    1414#endif
    1515
     16extern void *memset32(uint32_t *, uint32_t, __kernel_size_t);
    1617char *kstrdup(const char *s, unsigned int gfp_flags);
    1718_WCRTLINK extern size_t  strnlen_s( const char *__s, size_t __maxsize );
    … …  
    2728        return dst;
    2829}
    29 ssize_t strscpy(char *, const char *, size_t);
     30
    3031#define vmemdup_user memdup_user
    3132#define scnprintf snprintf
    3233ssize_t strscpy(char *dest, const char *src, size_t count);
     34extern bool sysfs_streq(const char *s1, const char *s2);
    3335
    3436#endif

  • GPL/trunk/include/linux/types.h

    r679 r772  
    135135        unsigned long name[((bits)+BITS_PER_LONG-1)/BITS_PER_LONG]
    136136
     137typedef u32 phys_addr_t;
     138typedef phys_addr_t resource_size_t;
     139
     140#define ATOMIC_INIT(i) { (i) }
     141#define ATOMIC_LONG_INIT(i)             ATOMIC_INIT(i)
    137142#endif /* _LINUX_TYPES_H */

  • GPL/trunk/include/linux/uaccess.h

    r679 r772  
    22#define _LINUX_UACCESS_H
    33#include <asm/uaccess.h>
     4#include <linux/minmax.h>
    45
    56#endif /* _LINUX_UACCESS_H */

  • GPL/trunk/include/linux/uio.h

    r679 r772  
    44#define _LINUX_UIO_H
    55
    6 enum {
    7         ITER_IOVEC = 0,
    8         ITER_KVEC = 2,
    9         ITER_BVEC = 4,
     6#include <linux/types.h>
     7
     8enum iter_type {
     9        /* iter types */
     10        ITER_IOVEC,
     11        ITER_KVEC,
     12        ITER_BVEC,
     13        ITER_XARRAY,
     14        ITER_DISCARD,
     15        ITER_UBUF,
     16};
     17
     18#define ITER_SOURCE     1       // == WRITE
     19#define ITER_DEST       0       // == READ
     20
     21struct kvec {
     22        void *iov_base; /* and that should *never* hold a userland pointer */
     23        size_t iov_len;
    1024};
    1125
    … …  
    2034
    2135struct iov_iter {
    22         int type;
    23         size_t iov_offset;
    24         size_t count;
     36        u8 iter_type;
     37        bool copy_mc;
     38        bool nofault;
     39        bool data_source;
     40        bool user_backed;
     41        union {
     42                /*
     43                 * This really should be a const, but we cannot do that without
     44                 * also modifying any of the zero-filling iter init functions.
     45                 * Leave it non-const for now, but it should be treated as such.
     46                 */
     47                struct iovec __ubuf_iovec;
     48                struct {
     49                        union {
     50                                /* use iter_iov() to get the current vec */
     51                                const struct iovec *__iov;
     52                                void __user *ubuf;
     53                        };
     54                        size_t count;
     55                };
     56        };
    2557        union {
    2658                const struct iovec *iov;
    … …  
    3365static inline bool iter_is_iovec(const struct iov_iter *i)
    3466{
    35         return !(i->type & (ITER_BVEC | ITER_KVEC));
     67        return !(i->iter_type & (ITER_BVEC | ITER_KVEC));
    3668}
    3769
     70static inline const struct iovec *iter_iov(const struct iov_iter *iter)
     71{
     72        if (iter->iter_type == ITER_UBUF)
     73                return (const struct iovec *) &iter->__ubuf_iovec;
     74        return iter->__iov;
     75}
     76int import_ubuf(int type, void __user *buf, size_t len, struct iov_iter *i);
     77
    3878#endif /* _LINUX_UIO_H */

  • GPL/trunk/include/linux/vmalloc.h

    r679 r772  
    88#include <asm/page.h>
    99
     10#define VM_MAP                  0x00000004      /* vmap()ed pages */
    1011
    1112struct vm_struct {

  • GPL/trunk/include/linux/wait.h

    r703 r772  
    133133#define wait_event(wq_head, condition)
    134134#define wake_up_all(x)                 
     135
     136#define wait_event_cmd(wq_head, condition, cmd1, cmd2)
     137
    135138#endif

  • GPL/trunk/include/linux/workqueue.h

    r689 r772  
    1818        struct timer_list timer;
    1919};
     20
     21#define WORK_DATA_STATIC_INIT() \
     22        ATOMIC_LONG_INIT((unsigned long)(WORK_STRUCT_NO_POOL | WORK_STRUCT_STATIC))
    2023
    2124struct workqueue_struct {
    … …  
    5255                init_timer(&(_work)->timer);            \
    5356        } while (0)
    54 #define __WORK_INITIALIZER(n, f, d) {                   \
    55                 .func = (f),                            \
    56                 .data = (d),                            \
     57#define __WORK_INITIALIZER(n, f) {                      \
     58        .data = 0,                              \
     59        .func = (void(*)(void *))(f),                           \
    5760        }
    58 #define DECLARE_WORK(n, f, d)                           \
    59         struct work_struct n = __WORK_INITIALIZER(n, f, d)
     61
     62#define DECLARE_WORK(n, f)                                              \
     63        struct work_struct n = __WORK_INITIALIZER(n, f)
    6064
    6165/* redefine INIT_WORK() */
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