source: GPL/trunk/include/linux/pci.h@ 772

Last change on this file since 772 was 772, checked in by David Azarewicz, 4 months ago

Merge in changes from 6.6-LTS branch.
Fixed additional 25+ problems.
File size: 31.8 KB
Line 
1/*
2 * PCI defines and function prototypes
3 * Copyright 1994, Drew Eckhardt
4 * Copyright 1997--1999 Martin Mares <mj@atrey.karlin.mff.cuni.cz>
5 *
6 * For more information, please consult the following manuals (look at
7 * http://www.pcisig.com/ for how to get them):
8 *
9 * PCI BIOS Specification
10 * PCI Local Bus Specification
11 * PCI to PCI Bridge Specification
12 * PCI System Design Guide
13 */
14
15#ifndef LINUX_PCI_H
16#define LINUX_PCI_H
17
18#include <linux/mod_devicetable.h>
19
20#include <linux/types.h>
21#include <linux/list.h>
22#include <linux/kobject.h>
23#include <linux/device.h>
24#include <linux/pm.h>
25#include <linux/io.h>
26
27#pragma pack(1) //!!! by vladest
28/*
29 * Under PCI, each device has 256 bytes of configuration address space,
30 * of which the first 64 bytes are standardized as follows:
31 */
32#define PCI_VENDOR_ID 0x00 /* 16 bits */
33#define PCI_DEVICE_ID 0x02 /* 16 bits */
34#define PCI_COMMAND 0x04 /* 16 bits */
35#define PCI_COMMAND_IO 0x1 /* Enable response in I/O space */
36#define PCI_COMMAND_MEMORY 0x2 /* Enable response in Memory space */
37#define PCI_COMMAND_MASTER 0x4 /* Enable bus mastering */
38#define PCI_COMMAND_SPECIAL 0x8 /* Enable response to special cycles */
39#define PCI_COMMAND_INVALIDATE 0x10 /* Use memory write and invalidate */
40#define PCI_COMMAND_VGA_PALETTE 0x20 /* Enable palette snooping */
41#define PCI_COMMAND_PARITY 0x40 /* Enable parity checking */
42#define PCI_COMMAND_WAIT 0x80 /* Enable address/data stepping */
43#define PCI_COMMAND_SERR 0x100 /* Enable SERR */
44#define PCI_COMMAND_FAST_BACK 0x200 /* Enable back-to-back writes */
45#define PCI_COMMAND_INTX_DISABLE 0x400 /* INTx Emulation Disable */
46
47#define PCI_STATUS 0x06 /* 16 bits */
48#define PCI_STATUS_CAP_LIST 0x10 /* Support Capability List */
49#define PCI_STATUS_66MHZ 0x20 /* Support 66 Mhz PCI 2.1 bus */
50#define PCI_STATUS_UDF 0x40 /* Support User Definable Features [obsolete] */
51#define PCI_STATUS_FAST_BACK 0x80 /* Accept fast-back to back */
52#define PCI_STATUS_PARITY 0x100 /* Detected parity error */
53#define PCI_STATUS_DEVSEL_MASK 0x600 /* DEVSEL timing */
54#define PCI_STATUS_DEVSEL_FAST 0x000
55#define PCI_STATUS_DEVSEL_MEDIUM 0x200
56#define PCI_STATUS_DEVSEL_SLOW 0x400
57#define PCI_STATUS_SIG_TARGET_ABORT 0x800 /* Set on target abort */
58#define PCI_STATUS_REC_TARGET_ABORT 0x1000 /* Master ack of " */
59#define PCI_STATUS_REC_MASTER_ABORT 0x2000 /* Set on master abort */
60#define PCI_STATUS_SIG_SYSTEM_ERROR 0x4000 /* Set when we drive SERR */
61#define PCI_STATUS_DETECTED_PARITY 0x8000 /* Set on parity error */
62
63#define PCI_CLASS_REVISION 0x08 /* High 24 bits are class, low 8
64 revision */
65#define PCI_REVISION_ID 0x08 /* Revision ID */
66#define PCI_CLASS_PROG 0x09 /* Reg. Level Programming Interface */
67#define PCI_CLASS_DEVICE 0x0a /* Device class */
68
69#define PCI_CACHE_LINE_SIZE 0x0c /* 8 bits */
70#define PCI_LATENCY_TIMER 0x0d /* 8 bits */
71#define PCI_HEADER_TYPE 0x0e /* 8 bits */
72#define PCI_HEADER_TYPE_NORMAL 0
73#define PCI_HEADER_TYPE_BRIDGE 1
74#define PCI_HEADER_TYPE_CARDBUS 2
75
76#define PCI_BIST 0x0f /* 8 bits */
77#define PCI_BIST_CODE_MASK 0x0f /* Return result */
78#define PCI_BIST_START 0x40 /* 1 to start BIST, 2 secs or less */
79#define PCI_BIST_CAPABLE 0x80 /* 1 if BIST capable */
80
81/*
82 * Base addresses specify locations in memory or I/O space.
83 * Decoded size can be determined by writing a value of
84 * 0xffffffff to the register, and reading it back. Only
85 * 1 bits are decoded.
86 */
87#define PCI_BASE_ADDRESS_0 0x10 /* 32 bits */
88#define PCI_BASE_ADDRESS_1 0x14 /* 32 bits [htype 0,1 only] */
89#define PCI_BASE_ADDRESS_2 0x18 /* 32 bits [htype 0 only] */
90#define PCI_BASE_ADDRESS_3 0x1c /* 32 bits */
91#define PCI_BASE_ADDRESS_4 0x20 /* 32 bits */
92#define PCI_BASE_ADDRESS_5 0x24 /* 32 bits */
93#define PCI_BASE_ADDRESS_SPACE 0x01 /* 0 = memory, 1 = I/O */
94#define PCI_BASE_ADDRESS_SPACE_IO 0x01
95#define PCI_BASE_ADDRESS_SPACE_MEMORY 0x00
96#define PCI_BASE_ADDRESS_MEM_TYPE_MASK 0x06
97#define PCI_BASE_ADDRESS_MEM_TYPE_32 0x00 /* 32 bit address */
98#define PCI_BASE_ADDRESS_MEM_TYPE_1M 0x02 /* Below 1M [obsolete] */
99#define PCI_BASE_ADDRESS_MEM_TYPE_64 0x04 /* 64 bit address */
100#define PCI_BASE_ADDRESS_MEM_PREFETCH 0x08 /* prefetchable? */
101#define PCI_BASE_ADDRESS_MEM_MASK (~0x0fUL)
102#define PCI_BASE_ADDRESS_IO_MASK (~0x03UL)
103/* bit 1 is reserved if address_space = 1 */
104
105/* Header type 0 (normal devices) */
106#define PCI_CARDBUS_CIS 0x28
107#define PCI_SUBSYSTEM_VENDOR_ID 0x2c
108#define PCI_SUBSYSTEM_ID 0x2e
109#define PCI_ROM_ADDRESS 0x30 /* Bits 31..11 are address, 10..1 reserved */
110#define PCI_ROM_ADDRESS_ENABLE 0x01
111#define PCI_ROM_ADDRESS_MASK (~0x7ffUL)
112
113#define PCI_CAPABILITY_LIST 0x34 /* Offset of first capability list entry */
114
115/* 0x35-0x3b are reserved */
116#define PCI_INTERRUPT_LINE 0x3c /* 8 bits */
117#define PCI_INTERRUPT_PIN 0x3d /* 8 bits */
118#define PCI_MIN_GNT 0x3e /* 8 bits */
119#define PCI_MAX_LAT 0x3f /* 8 bits */
120
121/* Header type 1 (PCI-to-PCI bridges) */
122#define PCI_PRIMARY_BUS 0x18 /* Primary bus number */
123#define PCI_SECONDARY_BUS 0x19 /* Secondary bus number */
124#define PCI_SUBORDINATE_BUS 0x1a /* Highest bus number behind the bridge */
125#define PCI_SEC_LATENCY_TIMER 0x1b /* Latency timer for secondary interface */
126#define PCI_IO_BASE 0x1c /* I/O range behind the bridge */
127#define PCI_IO_LIMIT 0x1d
128#define PCI_IO_RANGE_TYPE_MASK 0x0f /* I/O bridging type */
129#define PCI_IO_RANGE_TYPE_16 0x00
130#define PCI_IO_RANGE_TYPE_32 0x01
131#define PCI_IO_RANGE_MASK ~0x0f
132#define PCI_SEC_STATUS 0x1e /* Secondary status register, only bit 14 used */
133#define PCI_MEMORY_BASE 0x20 /* Memory range behind */
134#define PCI_MEMORY_LIMIT 0x22
135#define PCI_MEMORY_RANGE_TYPE_MASK 0x0f
136#define PCI_MEMORY_RANGE_MASK ~0x0f
137#define PCI_PREF_MEMORY_BASE 0x24 /* Prefetchable memory range behind */
138#define PCI_PREF_MEMORY_LIMIT 0x26
139#define PCI_PREF_RANGE_TYPE_MASK 0x0f
140#define PCI_PREF_RANGE_TYPE_32 0x00
141#define PCI_PREF_RANGE_TYPE_64 0x01
142#define PCI_PREF_RANGE_MASK ~0x0f
143#define PCI_PREF_BASE_UPPER32 0x28 /* Upper half of prefetchable memory range */
144#define PCI_PREF_LIMIT_UPPER32 0x2c
145#define PCI_IO_BASE_UPPER16 0x30 /* Upper half of I/O addresses */
146#define PCI_IO_LIMIT_UPPER16 0x32
147/* 0x34 same as for htype 0 */
148/* 0x35-0x3b is reserved */
149#define PCI_ROM_ADDRESS1 0x38 /* Same as PCI_ROM_ADDRESS, but for htype 1 */
150/* 0x3c-0x3d are same as for htype 0 */
151#define PCI_BRIDGE_CONTROL 0x3e
152#define PCI_BRIDGE_CTL_PARITY 0x01 /* Enable parity detection on secondary interface */
153#define PCI_BRIDGE_CTL_SERR 0x02 /* The same for SERR forwarding */
154#define PCI_BRIDGE_CTL_NO_ISA 0x04 /* Disable bridging of ISA ports */
155#define PCI_BRIDGE_CTL_VGA 0x08 /* Forward VGA addresses */
156#define PCI_BRIDGE_CTL_MASTER_ABORT 0x20 /* Report master aborts */
157#define PCI_BRIDGE_CTL_BUS_RESET 0x40 /* Secondary bus reset */
158#define PCI_BRIDGE_CTL_FAST_BACK 0x80 /* Fast Back2Back enabled on secondary interface */
159
160/* Header type 2 (CardBus bridges) */
161/* 0x14-0x15 reserved */
162#define PCI_CB_CAPABILITY_LIST 0x14
163#define PCI_CB_SEC_STATUS 0x16 /* Secondary status */
164#define PCI_CB_PRIMARY_BUS 0x18 /* PCI bus number */
165#define PCI_CB_CARD_BUS 0x19 /* CardBus bus number */
166#define PCI_CB_SUBORDINATE_BUS 0x1a /* Subordinate bus number */
167#define PCI_CB_LATENCY_TIMER 0x1b /* CardBus latency timer */
168#define PCI_CB_MEMORY_BASE_0 0x1c
169#define PCI_CB_MEMORY_LIMIT_0 0x20
170#define PCI_CB_MEMORY_BASE_1 0x24
171#define PCI_CB_MEMORY_LIMIT_1 0x28
172#define PCI_CB_IO_BASE_0 0x2c
173#define PCI_CB_IO_BASE_0_HI 0x2e
174#define PCI_CB_IO_LIMIT_0 0x30
175#define PCI_CB_IO_LIMIT_0_HI 0x32
176#define PCI_CB_IO_BASE_1 0x34
177#define PCI_CB_IO_BASE_1_HI 0x36
178#define PCI_CB_IO_LIMIT_1 0x38
179#define PCI_CB_IO_LIMIT_1_HI 0x3a
180#define PCI_CB_IO_RANGE_MASK ~0x03
181/* 0x3c-0x3d are same as for htype 0 */
182#define PCI_CB_BRIDGE_CONTROL 0x3e
183#define PCI_CB_BRIDGE_CTL_PARITY 0x01 /* Similar to standard bridge control register */
184#define PCI_CB_BRIDGE_CTL_SERR 0x02
185#define PCI_CB_BRIDGE_CTL_ISA 0x04
186#define PCI_CB_BRIDGE_CTL_VGA 0x08
187#define PCI_CB_BRIDGE_CTL_MASTER_ABORT 0x20
188#define PCI_CB_BRIDGE_CTL_CB_RESET 0x40 /* CardBus reset */
189#define PCI_CB_BRIDGE_CTL_16BIT_INT 0x80 /* Enable interrupt for 16-bit cards */
190#define PCI_CB_BRIDGE_CTL_PREFETCH_MEM0 0x100 /* Prefetch enable for both memory regions */
191#define PCI_CB_BRIDGE_CTL_PREFETCH_MEM1 0x200
192#define PCI_CB_BRIDGE_CTL_POST_WRITES 0x400
193#define PCI_CB_SUBSYSTEM_VENDOR_ID 0x40
194#define PCI_CB_SUBSYSTEM_ID 0x42
195#define PCI_CB_LEGACY_MODE_BASE 0x44 /* 16-bit PC Card legacy mode base address (ExCa) */
196/* 0x48-0x7f reserved */
197
198/* Capability lists */
199
200#define PCI_CAP_LIST_ID 0 /* Capability ID */
201#define PCI_CAP_ID_PM 0x01 /* Power Management */
202#define PCI_CAP_ID_AGP 0x02 /* Accelerated Graphics Port */
203#define PCI_CAP_ID_VPD 0x03 /* Vital Product Data */
204#define PCI_CAP_ID_SLOTID 0x04 /* Slot Identification */
205#define PCI_CAP_ID_MSI 0x05 /* Message Signalled Interrupts */
206#define PCI_CAP_ID_CHSWP 0x06 /* CompactPCI HotSwap */
207#define PCI_CAP_LIST_NEXT 1 /* Next capability in the list */
208#define PCI_CAP_FLAGS 2 /* Capability defined flags (16 bits) */
209#define PCI_CAP_SIZEOF 4
210
211/* Power Management Registers */
212#define PCI_PM_PMC 2 /* PM Capabilities Register */
213#define PCI_PM_CAP_VER_MASK 0x0007 /* Version */
214#define PCI_PM_CAP_PME_CLOCK 0x0008 /* PME clock required */
215#define PCI_PM_CAP_AUX_POWER 0x0010 /* Auxilliary power support */
216#define PCI_PM_CAP_DSI 0x0020 /* Device specific initialization */
217#define PCI_PM_CAP_D1 0x0200 /* D1 power state support */
218#define PCI_PM_CAP_D2 0x0400 /* D2 power state support */
219#define PCI_PM_CAP_PME 0x0800 /* PME pin supported */
220#define PCI_PM_CTRL 4 /* PM control and status register */
221#define PCI_PM_CTRL_STATE_MASK 0x0003 /* Current power state (D0 to D3) */
222#define PCI_PM_CTRL_PME_ENABLE 0x0100 /* PME pin enable */
223#define PCI_PM_CTRL_DATA_SEL_MASK 0x1e00 /* Data select (??) */
224#define PCI_PM_CTRL_DATA_SCALE_MASK 0x6000 /* Data scale (??) */
225#define PCI_PM_CTRL_PME_STATUS 0x8000 /* PME pin status */
226#define PCI_PM_PPB_EXTENSIONS 6 /* PPB support extensions (??) */
227#define PCI_PM_PPB_B2_B3 0x40 /* Stop clock when in D3hot (??) */
228#define PCI_PM_BPCC_ENABLE 0x80 /* Bus power/clock control enable (??) */
229#define PCI_PM_DATA_REGISTER 7 /* (??) */
230#define PCI_PM_SIZEOF 8
231
232/* AGP registers */
233
234#define PCI_AGP_VERSION 2 /* BCD version number */
235#define PCI_AGP_RFU 3 /* Rest of capability flags */
236#define PCI_AGP_STATUS 4 /* Status register */
237#define PCI_AGP_STATUS_RQ_MASK 0xff000000 /* Maximum number of requests - 1 */
238#define PCI_AGP_STATUS_SBA 0x0200 /* Sideband addressing supported */
239#define PCI_AGP_STATUS_64BIT 0x0020 /* 64-bit addressing supported */
240#define PCI_AGP_STATUS_FW 0x0010 /* FW transfers supported */
241#define PCI_AGP_STATUS_RATE4 0x0004 /* 4x transfer rate supported */
242#define PCI_AGP_STATUS_RATE2 0x0002 /* 2x transfer rate supported */
243#define PCI_AGP_STATUS_RATE1 0x0001 /* 1x transfer rate supported */
244#define PCI_AGP_COMMAND 8 /* Control register */
245#define PCI_AGP_COMMAND_RQ_MASK 0xff000000 /* Master: Maximum number of requests */
246#define PCI_AGP_COMMAND_SBA 0x0200 /* Sideband addressing enabled */
247#define PCI_AGP_COMMAND_AGP 0x0100 /* Allow processing of AGP transactions */
248#define PCI_AGP_COMMAND_64BIT 0x0020 /* Allow processing of 64-bit addresses */
249#define PCI_AGP_COMMAND_FW 0x0010 /* Force FW transfers */
250#define PCI_AGP_COMMAND_RATE4 0x0004 /* Use 4x rate */
251#define PCI_AGP_COMMAND_RATE2 0x0002 /* Use 4x rate */
252#define PCI_AGP_COMMAND_RATE1 0x0001 /* Use 4x rate */
253#define PCI_AGP_SIZEOF 12
254
255/* Slot Identification */
256
257#define PCI_SID_ESR 2 /* Expansion Slot Register */
258#define PCI_SID_ESR_NSLOTS 0x1f /* Number of expansion slots available */
259#define PCI_SID_ESR_FIC 0x20 /* First In Chassis Flag */
260#define PCI_SID_CHASSIS_NR 3 /* Chassis Number */
261
262/* Message Signalled Interrupts registers */
263
264#define PCI_MSI_FLAGS 2 /* Various flags */
265#define PCI_MSI_FLAGS_64BIT 0x80 /* 64-bit addresses allowed */
266#define PCI_MSI_FLAGS_QSIZE 0x70 /* Message queue size configured */
267#define PCI_MSI_FLAGS_QMASK 0x0e /* Maximum queue size available */
268#define PCI_MSI_FLAGS_ENABLE 0x01 /* MSI feature enabled */
269#define PCI_MSI_RFU 3 /* Rest of capability flags */
270#define PCI_MSI_ADDRESS_LO 4 /* Lower 32 bits */
271#define PCI_MSI_ADDRESS_HI 8 /* Upper 32 bits (if PCI_MSI_FLAGS_64BIT set) */
272#define PCI_MSI_DATA_32 8 /* 16 bits of data for 32-bit devices */
273#define PCI_MSI_DATA_64 12 /* 16 bits of data for 64-bit devices */
274
275/* Include the ID list */
276
277#include <linux/pci_ids.h>
278
279/*
280 * The PCI interface treats multi-function devices as independent
281 * devices. The slot/function address of each device is encoded
282 * in a single byte as follows:
283 *
284 * 7:3 = slot
285 * 2:0 = function
286 */
287#define PCI_DEVFN(slot,func) ((((slot) & 0x1f) << 3) | ((func) & 0x07))
288#define PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f)
289#define PCI_FUNC(devfn) ((devfn) & 0x07)
290
291#ifdef __KERNEL__
292
293#include <linux/types.h>
294#include <linux/ioport.h>
295
296#include <asm/pci.h>
297#define BUS_ID_SIZE 20
298#define DEVICE_COUNT_COMPATIBLE 4
299#define DEVICE_COUNT_IRQ 2
300#define DEVICE_COUNT_DMA 2
301#define DEVICE_COUNT_RESOURCE 12
302
303typedef struct pci_dev;
304
305#define PCI_D0 0
306#define PCI_D1 1
307#define PCI_D2 2
308#define PCI_D3hot 3
309#define PCI_D3cold 4
310#define pci_choose_state(pci,state) ((state) ? PCI_D3hot : PCI_D0)
311
312struct dev_pm_info2 {
313 unsigned int async_suspend:1;
314 bool is_prepared:1; /* Owned by the PM core */
315 u32 power_state;
316 u8 * saved_state;
317 atomic_t pm_users;
318 struct device * pm_parent;
319 struct list_head entry;
320};
321
322/*
323 * The pci_dev structure is used to describe both PCI and ISAPnP devices.
324 */
325struct pci_dev {
326 int active; /* device is active */
327 int ro; /* Read/Only */
328
329 struct pci_bus *bus; /* bus this device is on */
330 struct pci_dev *sibling; /* next device on this bus */
331 struct pci_dev *next; /* chain of all devices */
332
333 void *sysdata; /* hook for sys-specific extension */
334 struct proc_dir_entry *procent; /* device entry in /proc/bus/pci */
335
336 struct device dev;
337 unsigned int class; /* 3 bytes: (base,sub,prog-if) */
338 u8 revision; /* PCI revision, low byte of class word */
339 unsigned int devfn; /* encoded device & function index */
340 unsigned short vendor;
341 unsigned short device;
342 unsigned short subsystem_vendor;
343 unsigned short subsystem_device;
344 u8 hdr_type; /* PCI header type (`multi' flag masked out) */
345 u8 rom_base_reg; /* Which config register controls the ROM */
346
347 unsigned short regs;
348
349 u32 current_state; /* Current operating state. In ACPI-speak,
350 this is D0-D3, D0 being fully functional,
351 and D3 being off. */
352
353 /* device is compatible with these IDs */
354 unsigned short vendor_compatible[DEVICE_COUNT_COMPATIBLE];
355 unsigned short device_compatible[DEVICE_COUNT_COMPATIBLE];
356
357 /*
358 * Instead of touching interrupt line and base address registers
359 * directly, use the values stored here. They might be different!
360 */
361 unsigned int irq;
362 unsigned char irq_pin;
363 struct resource resource[DEVICE_COUNT_RESOURCE]; /* I/O and memory regions + expansion ROMs */
364 struct resource dma_resource[DEVICE_COUNT_DMA];
365 struct resource irq_resource[DEVICE_COUNT_IRQ];
366 unsigned int is_managed:1;
367
368 char name[48]; /* Device name */
369 char slot_name[8]; /* Slot name */
370
371 void *driver_data;
372 u64 dma_mask; /* Mask of the bits of bus address this
373 device implements. Normally this is
374 0xffffffff. You only need to change
375 this if your device has broken DMA
376 or supports 64-bit transfers. */
377 unsigned int no_64bit_msi:1; /* device may only use 32-bit MSIs */
378
379 int (*prepare)(struct pci_dev *dev);
380 int (*activate)(struct pci_dev *dev);
381 int (*deactivate)(struct pci_dev *dev);
382#ifdef TARGET_OS2
383//DAZ unsigned int picirq;
384//DAZ unsigned int apicirq;
385 unsigned long hAdapter;
386//AT unsigned long hDevice;
387 void *pcidriver;
388#endif
389};
390
391/*
392 * For PCI devices, the region numbers are assigned this way:
393 *
394 * 0-5 standard PCI regions
395 * 6 expansion ROM
396 * 7-10 bridges: address space assigned to buses behind the bridge
397 */
398
399#define PCI_ROM_RESOURCE 6
400#define PCI_BRIDGE_RESOURCES 7
401#define PCI_NUM_RESOURCES 11
402
403#define PCI_REGION_FLAG_MASK 0x0f /* These bits of resource flags tell us the PCI region flags */
404
405struct pci_bus {
406 struct pci_bus *parent; /* parent bus this bridge is on */
407 struct pci_bus *children; /* chain of P2P bridges on this bus */
408 struct pci_bus *next; /* chain of all PCI buses */
409 struct pci_ops *ops; /* configuration access functions */
410
411 struct pci_dev *self; /* bridge device as seen by parent */
412 struct pci_dev *devices; /* devices behind this bridge */
413 struct resource *resource[4]; /* address space routed to this bus */
414
415 void *sysdata; /* hook for sys-specific extension */
416 struct proc_dir_entry *procdir; /* directory entry in /proc/bus/pci */
417
418 unsigned char number; /* bus number */
419 unsigned char primary; /* number of primary bridge */
420 unsigned char secondary; /* number of secondary bridge */
421 unsigned char subordinate; /* max number of subordinate buses */
422
423 char name[48];
424 unsigned short vendor;
425 unsigned short device;
426 unsigned int serial; /* serial number */
427 unsigned char pnpver; /* Plug & Play version */
428 unsigned char productver; /* product version */
429 unsigned char checksum; /* if zero - checksum passed */
430 unsigned char pad1;
431};
432
433//extern struct pci_bus *pci_root; /* root bus */
434//extern struct pci_dev *pci_devices; /* list of all devices */
435
436/*
437 * Error values that may be returned by PCI functions.
438 */
439#define PCIBIOS_SUCCESSFUL 0x00
440#define PCIBIOS_FUNC_NOT_SUPPORTED 0x81
441#define PCIBIOS_BAD_VENDOR_ID 0x83
442#define PCIBIOS_DEVICE_NOT_FOUND 0x86
443#define PCIBIOS_BAD_REGISTER_NUMBER 0x87
444#define PCIBIOS_SET_FAILED 0x88
445#define PCIBIOS_BUFFER_TOO_SMALL 0x89
446
447/* Low-level architecture-dependent routines */
448
449struct pci_ops {
450 int (*read_byte)(struct pci_dev *, int where, u8 *val);
451 int (*read_word)(struct pci_dev *, int where, u16 *val);
452 int (*read_dword)(struct pci_dev *, int where, u32 *val);
453 int (*write_byte)(struct pci_dev *, int where, u8 val);
454 int (*write_word)(struct pci_dev *, int where, u16 val);
455 int (*write_dword)(struct pci_dev *, int where, u32 val);
456};
457
458void pcibios_init(void);
459void pcibios_fixup_bus(struct pci_bus *);
460int pcibios_enable_device(struct pci_dev *);
461char *pcibios_setup (char *str);
462
463void pcibios_update_resource(struct pci_dev *, struct resource *,
464 struct resource *, int);
465void pcibios_update_irq(struct pci_dev *, int irq);
466
467/* Backward compatibility, don't use in new code! */
468
469int pcibios_present(void);
470#define pci_present pcibios_present
471int pcibios_read_config_byte (unsigned char bus, unsigned char dev_fn,
472 unsigned char where, unsigned char *val);
473int pcibios_read_config_word (unsigned char bus, unsigned char dev_fn,
474 unsigned char where, unsigned short *val);
475int pcibios_read_config_dword (unsigned char bus, unsigned char dev_fn,
476 unsigned char where, unsigned int *val);
477int pcibios_write_config_byte (unsigned char bus, unsigned char dev_fn,
478 unsigned char where, unsigned char val);
479int pcibios_write_config_word (unsigned char bus, unsigned char dev_fn,
480 unsigned char where, unsigned short val);
481int pcibios_write_config_dword (unsigned char bus, unsigned char dev_fn,
482 unsigned char where, unsigned int val);
483int pcibios_find_class (unsigned int class_code, unsigned short index, unsigned char *bus, unsigned char *dev_fn);
484int pcibios_find_device (unsigned short vendor, unsigned short dev_id,
485 unsigned short index, unsigned char *bus,
486 unsigned char *dev_fn);
487
488/* Generic PCI interface functions */
489
490void pci_init(void);
491struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops, void *sysdata);
492int pci_proc_attach_device(struct pci_dev *dev);
493int pci_proc_detach_device(struct pci_dev *dev);
494void pci_name_device(struct pci_dev *dev);
495void pci_read_bridge_bases(struct pci_bus *child);
496struct resource *pci_find_parent_resource(struct pci_dev *dev, struct resource *res);
497
498struct pci_dev *pci_find_device (unsigned int vendor, unsigned int device, struct pci_dev *from);
499struct pci_dev *pci_find_subsys (unsigned int vendor, unsigned int device,
500 unsigned int ss_vendor, unsigned int ss_device,
501 struct pci_dev *from);
502struct pci_dev *pci_find_class (unsigned int _class, struct pci_dev *from);
503struct pci_dev *pci_find_slot (unsigned int bus, unsigned int devfn);
504int pci_find_capability (struct pci_dev *dev, int cap);
505int pci_dma_supported(struct pci_dev *dev, unsigned long mask);
506
507#define PCI_ANY_ID (~0)
508
509int pci_read_config_byte(struct pci_dev *dev, int where, u8 *val);
510int pci_read_config_word(struct pci_dev *dev, int where, u16 *val);
511int pci_read_config_dword(struct pci_dev *dev, int where, u32 *val);
512int pci_write_config_byte(struct pci_dev *dev, int where, u8 val);
513int pci_write_config_word(struct pci_dev *dev, int where, u16 val);
514int pci_write_config_dword(struct pci_dev *dev, int where, u32 val);
515int pci_enable_device(struct pci_dev *dev);
516void pci_set_master(struct pci_dev *dev);
517int pci_set_power_state(struct pci_dev *dev, int state);
518
519/* Helper functions for low-level code (drivers/pci/setup.c) */
520
521int pci_claim_resource(struct pci_dev *, int);
522void pci_assign_unassigned_resources(u32 min_io, u32 min_mem);
523void pci_set_bus_ranges(void);
524void pci_fixup_irqs(u8 (*)(struct pci_dev *, u8 *),
525 int (*)(struct pci_dev *, u8, u8));
526
527/*
528 * simple PCI probing for drivers (drivers/pci/helper.c)
529 */
530
531struct pci_simple_probe_entry;
532typedef int (*pci_simple_probe_callback) (struct pci_dev *dev, int match_num,
533 const struct pci_simple_probe_entry *ent,
534 void *drvr_data);
535
536struct pci_simple_probe_entry {
537 unsigned short vendor; /* vendor id, PCI_ANY_ID, or 0 for last entry */
538 unsigned short device; /* device id, PCI_ANY_ID, or 0 for last entry */
539 unsigned short subsys_vendor; /* subsystem vendor id, 0 for don't care */
540 unsigned short subsys_device; /* subsystem device id, 0 for don't care */
541 void *dev_data; /* driver-private, entry-specific data */
542};
543
544int pci_simple_probe (const struct pci_simple_probe_entry *list,
545 size_t match_limit, pci_simple_probe_callback cb,
546 void *drvr_data);
547
548
549
550/*
551 * If the system does not have PCI, clearly these return errors. Define
552 * these as simple inline functions to avoid hair in drivers.
553 */
554
555/*
556 * The world is not perfect and supplies us with broken PCI devices.
557 * For at least a part of these bugs we need a work-around, so both
558 * generic (drivers/pci/quirks.c) and per-architecture code can define
559 * fixup hooks to be called for particular buggy devices.
560 */
561
562struct pci_fixup {
563 int pass;
564 u16 vendor, device; /* You can use PCI_ANY_ID here of course */
565 void (*hook)(struct pci_dev *dev);
566};
567
568extern struct pci_fixup pcibios_fixups[];
569
570#define PCI_FIXUP_HEADER 1 /* Called immediately after reading configuration header */
571#define PCI_FIXUP_FINAL 2 /* Final phase of device fixups */
572
573void pci_fixup_device(int pass, struct pci_dev *dev);
574
575extern int pci_pci_problems;
576#define PCIPCI_FAIL 1
577#define PCIPCI_TRITON 2
578#define PCIPCI_NATOMA 4
579
580
581struct pci_device_id {
582 unsigned int vendor, device;
583 unsigned int subvendor, subdevice;
584 unsigned int class, class_mask;
585 unsigned long driver_data;
586};
587
588struct pci_driver {
589 struct list_head node;
590 struct pci_dev *dev;
591 char *name;
592 const struct pci_device_id *id_table; /* NULL if wants all devices */
593 int (*probe)(struct pci_dev *dev, const struct pci_device_id *id); /* New device inserted */
594 void (*remove)(struct pci_dev *dev); /* Device removed (NULL if not a hot-plug capable driver) */
595 int (*suspend)(struct pci_dev *dev, u32 stgate); /* Device suspended */
596 int (*resume)(struct pci_dev *dev); /* Device woken up */
597 void (*shutdown) (struct pci_dev *dev);
598 struct device_driver driver;
599};
600
601/*
602 * Device identifier
603 */
604#define PM_PCI_ID(dev) ((dev)->bus->number << 16 | (dev)->devfn)
605
606#define PCI_GET_DRIVER_DATA pci_get_driver_data
607#define PCI_SET_DRIVER_DATA pci_set_driver_data
608
609int pci_register_driver(struct pci_driver *driver);
610int pci_module_init(struct pci_driver *drv);
611
612int pci_unregister_driver(struct pci_driver *driver);
613
614
615#define pci_dev_g(n) list_entry(n, struct pci_dev, global_list)
616#define pci_dev_b(n) list_entry(n, struct pci_dev, bus_list)
617
618#define pci_for_each_dev(dev) \
619 for(dev = pci_devices; dev; dev = dev->next)
620
621#define pci_resource_start(dev,bar) \
622 (((dev)->resource[(bar)].flags & PCI_BASE_ADDRESS_SPACE) ? \
623 ((dev)->resource[(bar)].start & PCI_BASE_ADDRESS_IO_MASK) : \
624 ((dev)->resource[(bar)].start & PCI_BASE_ADDRESS_MEM_MASK))
625
626#define pci_resource_end(dev,bar) \
627 (((dev)->resource[(bar)].flags & PCI_BASE_ADDRESS_SPACE) ? \
628 ((dev)->resource[(bar)].end & PCI_BASE_ADDRESS_IO_MASK) : \
629 ((dev)->resource[(bar)].end & PCI_BASE_ADDRESS_MEM_MASK))
630
631/*
632 #define pci_resource_end(dev,bar) ((dev)->resource[(bar)].end)
633 */
634#define pci_resource_flags(dev,bar) ((dev)->resource[(bar)].flags)
635
636#define pci_resource_len(dev,bar) \
637 ((pci_resource_start((dev),(bar)) == 0 && \
638 pci_resource_end((dev),(bar)) == \
639 pci_resource_start((dev),(bar))) ? 0 : \
640 \
641 (pci_resource_end((dev),(bar)) - \
642 pci_resource_start((dev),(bar))))
643
644extern struct pci_dev pci_devices[];
645extern struct pci_bus pci_busses[];
646
647/*
648 *
649 */
650const struct pci_device_id *pci_match_id(const struct pci_device_id *ids, struct pci_dev *dev);
651unsigned long pci_get_size (struct pci_dev *dev, int n_base);
652
653int pci_get_flags (struct pci_dev *dev, int n_base);
654int pci_set_power_state(struct pci_dev *dev, int new_state);
655int pci_enable_device(struct pci_dev *dev);
656int pci_find_capability(struct pci_dev *dev, int cap);
657
658void *pci_alloc_consistent(struct pci_dev *, long, dma_addr_t *);
659void pci_free_consistent(struct pci_dev *, long, void *, dma_addr_t);
660
661int pci_dma_supported(struct pci_dev *, dma_addr_t mask);
662void pci_release_regions(struct pci_dev *pdev);
663int pci_request_regions(struct pci_dev *pdev, char *res_name);
664
665void pci_disable_device(struct pci_dev *dev);
666
667int pci_save_state(struct pci_dev *dev);
668int pci_restore_state(struct pci_dev *dev);
669
670unsigned long pci_get_dma_mask(struct pci_dev *);
671#define pci_set_dma_mask(pci, mask) (pci->dma_mask = mask, 0)
672
673void *pci_get_driver_data (struct pci_dev *dev);
674void pci_set_driver_data (struct pci_dev *dev, void *driver_data);
675
676#define PCI_DEVICE(vend,dev) \
677 .vendor = (vend), .device = (dev), \
678 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
679
680#define pci_get_device pci_find_device
681#define pci_dev_put(x)
682
683#define to_pci_dev(n) container_of(n, struct pci_dev, dev)
684
685#pragma pack() //!!! by vladest
686
687#endif /* __KERNEL__ */
688
689static inline unsigned char snd_pci_revision(struct pci_dev *pci)
690{
691 unsigned char rev;
692 pci_read_config_byte(pci, PCI_REVISION_ID, &rev);
693 return rev;
694}
695
696/* MSI */
697extern int snd_pci_enable_msi(struct pci_dev *dev);
698#undef pci_enable_msi
699#define pci_enable_msi(dev) snd_pci_enable_msi(dev)
700#undef pci_disable_msi
701#define pci_disable_msi(dev)
702extern int snd_pci_dev_present(const struct pci_device_id *ids);
703#define pci_dev_present(x) snd_pci_dev_present(x)
704extern void * __ioremap(unsigned long offset, unsigned long size, unsigned long flags);
705static inline void *pci_ioremap_bar(struct pci_dev *pdev, int bar)
706{
707 return __ioremap(pci_resource_start(pdev, bar),
708 pci_resource_len(pdev, bar),0x010);
709}
710
711#define PCI_VDEVICE(vendor, device) \
712 PCI_VENDOR_ID_##vendor, (device), \
713 PCI_ANY_ID, PCI_ANY_ID, 0, 0
714
715#define pci_clear_master(x)
716
717/* originally it's __devinitconst but we use __devinitdata to be compatible
718 * with older kernels
719 */
720#define DEFINE_PCI_DEVICE_TABLE(_table) \
721 const struct pci_device_id _table[] __devinitdata
722
723/**
724 * module_pci_driver() - Helper macro for registering a PCI driver
725 * @__pci_driver: pci_driver struct
726 *
727 * Helper macro for PCI drivers which do not do anything special in module
728 * init/exit. This eliminates a lot of boilerplate. Each module may only
729 * use this macro once, and calling it replaces module_init() and module_exit()
730 */
731#define module_pci_driver(__pci_driver) \
732 module_driver(__pci_driver, pci_register_driver, \
733 pci_unregister_driver)
734
735static inline bool pci_dev_run_wake(struct pci_dev *dev) { return 0; }
736
737/*
738 * Similar to the helpers above, these manipulate per-pci_dev
739 * driver-specific data. They are really just a wrapper around
740 * the generic device structure functions of these calls.
741 */
742static inline void *pci_get_drvdata(struct pci_dev *pdev)
743{
744 return dev_get_drvdata(&pdev->dev);
745}
746
747static inline void pci_set_drvdata(struct pci_dev *pdev, void *data)
748{
749 dev_set_drvdata(&pdev->dev, data);
750}
751/* If you want to know what to call your pci_dev, ask this function.
752 * Again, it's a wrapper around the generic device.
753 */
754static inline const char *pci_name(struct pci_dev *pdev)
755{
756 return dev_name(&pdev->dev);
757}
758
759/**
760 * PCI_DEVICE_SUB - macro used to describe a specific pci device with subsystem
761 * @vend: the 16 bit PCI Vendor ID
762 * @dev: the 16 bit PCI Device ID
763 * @subvend: the 16 bit PCI Subvendor ID
764 * @subdev: the 16 bit PCI Subdevice ID
765 *
766 * This macro is used to create a struct pci_device_id that matches a
767 * specific device with subsystem information.
768 */
769#define PCI_DEVICE_SUB(vend, dev, subvend, subdev) \
770 .vendor = (vend), .device = (dev), \
771 .subvendor = (subvend), .subdevice = (subdev)
772
773int pci_status_get_and_clear_errors(struct pci_dev *pdev);
774#define PCI_STATUS_ERROR_BITS (PCI_STATUS_DETECTED_PARITY | \
775 PCI_STATUS_SIG_SYSTEM_ERROR | \
776 PCI_STATUS_REC_MASTER_ABORT | \
777 PCI_STATUS_REC_TARGET_ABORT | \
778 PCI_STATUS_SIG_TARGET_ABORT | \
779 PCI_STATUS_PARITY)
780
781#define dev_is_pci(d) (true)
782int pcim_enable_device(struct pci_dev *pdev);
783int pcim_iomap_regions(struct pci_dev *pdev, int mask, const char *name);
784void __iomem *pcim_iomap(struct pci_dev *pdev, int bar, unsigned long maxlen);
785
786static inline int pci_is_managed(struct pci_dev *pdev)
787{
788 return pdev->is_managed;
789}
790void pci_intx(struct pci_dev *pdev, int enable);
791#define PCI_STD_NUM_BARS 6 /* Number of standard BARs */
792int __must_check pci_request_region(struct pci_dev *, int, char *);
793void pci_release_region(struct pci_dev *, int);
794void __iomem * const *pcim_iomap_table(struct pci_dev *pdev);
795#define for_each_pci_dev(d) while ((d = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, d)) != NULL)
796
797/**
798 * PCI_DEVICE_DATA - macro used to describe a specific PCI device in very short form
799 * @vend: the vendor name (without PCI_VENDOR_ID_ prefix)
800 * @dev: the device name (without PCI_DEVICE_ID_<vend>_ prefix)
801 * @data: the driver data to be filled
802 *
803 * This macro is used to create a struct pci_device_id that matches a
804 * specific PCI device. The subvendor, and subdevice fields will be set
805 * to PCI_ANY_ID.
806 */
807#define PCI_DEVICE_DATA(vend, dev, data) \
808 .vendor = PCI_VENDOR_ID_##vend, .device = PCI_DEVICE_ID_##vend##_##dev, \
809 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, 0, 0, \
810 .driver_data = (unsigned long)(data)
811
812#endif /* LINUX_PCI_H */
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