source: GPL/trunk/include/linux/pci.h@ 717

Last change on this file since 717 was 717, checked in by David Azarewicz, 3 years ago

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1/*
2 * PCI defines and function prototypes
3 * Copyright 1994, Drew Eckhardt
4 * Copyright 1997--1999 Martin Mares <mj@atrey.karlin.mff.cuni.cz>
5 *
6 * For more information, please consult the following manuals (look at
7 * http://www.pcisig.com/ for how to get them):
8 *
9 * PCI BIOS Specification
10 * PCI Local Bus Specification
11 * PCI to PCI Bridge Specification
12 * PCI System Design Guide
13 */
14
15#ifndef LINUX_PCI_H
16#define LINUX_PCI_H
17
18#include <linux/mod_devicetable.h>
19
20#include <linux/types.h>
21#include <linux/list.h>
22#include <linux/kobject.h>
23#include <linux/device.h>
24#include <linux/pm.h>
25#include <linux/io.h>
26
27#pragma pack(1) //!!! by vladest
28/*
29 * Under PCI, each device has 256 bytes of configuration address space,
30 * of which the first 64 bytes are standardized as follows:
31 */
32#define PCI_VENDOR_ID 0x00 /* 16 bits */
33#define PCI_DEVICE_ID 0x02 /* 16 bits */
34#define PCI_COMMAND 0x04 /* 16 bits */
35#define PCI_COMMAND_IO 0x1 /* Enable response in I/O space */
36#define PCI_COMMAND_MEMORY 0x2 /* Enable response in Memory space */
37#define PCI_COMMAND_MASTER 0x4 /* Enable bus mastering */
38#define PCI_COMMAND_SPECIAL 0x8 /* Enable response to special cycles */
39#define PCI_COMMAND_INVALIDATE 0x10 /* Use memory write and invalidate */
40#define PCI_COMMAND_VGA_PALETTE 0x20 /* Enable palette snooping */
41#define PCI_COMMAND_PARITY 0x40 /* Enable parity checking */
42#define PCI_COMMAND_WAIT 0x80 /* Enable address/data stepping */
43#define PCI_COMMAND_SERR 0x100 /* Enable SERR */
44#define PCI_COMMAND_FAST_BACK 0x200 /* Enable back-to-back writes */
45
46#define PCI_STATUS 0x06 /* 16 bits */
47#define PCI_STATUS_CAP_LIST 0x10 /* Support Capability List */
48#define PCI_STATUS_66MHZ 0x20 /* Support 66 Mhz PCI 2.1 bus */
49#define PCI_STATUS_UDF 0x40 /* Support User Definable Features [obsolete] */
50#define PCI_STATUS_FAST_BACK 0x80 /* Accept fast-back to back */
51#define PCI_STATUS_PARITY 0x100 /* Detected parity error */
52#define PCI_STATUS_DEVSEL_MASK 0x600 /* DEVSEL timing */
53#define PCI_STATUS_DEVSEL_FAST 0x000
54#define PCI_STATUS_DEVSEL_MEDIUM 0x200
55#define PCI_STATUS_DEVSEL_SLOW 0x400
56#define PCI_STATUS_SIG_TARGET_ABORT 0x800 /* Set on target abort */
57#define PCI_STATUS_REC_TARGET_ABORT 0x1000 /* Master ack of " */
58#define PCI_STATUS_REC_MASTER_ABORT 0x2000 /* Set on master abort */
59#define PCI_STATUS_SIG_SYSTEM_ERROR 0x4000 /* Set when we drive SERR */
60#define PCI_STATUS_DETECTED_PARITY 0x8000 /* Set on parity error */
61
62#define PCI_CLASS_REVISION 0x08 /* High 24 bits are class, low 8
63 revision */
64#define PCI_REVISION_ID 0x08 /* Revision ID */
65#define PCI_CLASS_PROG 0x09 /* Reg. Level Programming Interface */
66#define PCI_CLASS_DEVICE 0x0a /* Device class */
67
68#define PCI_CACHE_LINE_SIZE 0x0c /* 8 bits */
69#define PCI_LATENCY_TIMER 0x0d /* 8 bits */
70#define PCI_HEADER_TYPE 0x0e /* 8 bits */
71#define PCI_HEADER_TYPE_NORMAL 0
72#define PCI_HEADER_TYPE_BRIDGE 1
73#define PCI_HEADER_TYPE_CARDBUS 2
74
75#define PCI_BIST 0x0f /* 8 bits */
76#define PCI_BIST_CODE_MASK 0x0f /* Return result */
77#define PCI_BIST_START 0x40 /* 1 to start BIST, 2 secs or less */
78#define PCI_BIST_CAPABLE 0x80 /* 1 if BIST capable */
79
80/*
81 * Base addresses specify locations in memory or I/O space.
82 * Decoded size can be determined by writing a value of
83 * 0xffffffff to the register, and reading it back. Only
84 * 1 bits are decoded.
85 */
86#define PCI_BASE_ADDRESS_0 0x10 /* 32 bits */
87#define PCI_BASE_ADDRESS_1 0x14 /* 32 bits [htype 0,1 only] */
88#define PCI_BASE_ADDRESS_2 0x18 /* 32 bits [htype 0 only] */
89#define PCI_BASE_ADDRESS_3 0x1c /* 32 bits */
90#define PCI_BASE_ADDRESS_4 0x20 /* 32 bits */
91#define PCI_BASE_ADDRESS_5 0x24 /* 32 bits */
92#define PCI_BASE_ADDRESS_SPACE 0x01 /* 0 = memory, 1 = I/O */
93#define PCI_BASE_ADDRESS_SPACE_IO 0x01
94#define PCI_BASE_ADDRESS_SPACE_MEMORY 0x00
95#define PCI_BASE_ADDRESS_MEM_TYPE_MASK 0x06
96#define PCI_BASE_ADDRESS_MEM_TYPE_32 0x00 /* 32 bit address */
97#define PCI_BASE_ADDRESS_MEM_TYPE_1M 0x02 /* Below 1M [obsolete] */
98#define PCI_BASE_ADDRESS_MEM_TYPE_64 0x04 /* 64 bit address */
99#define PCI_BASE_ADDRESS_MEM_PREFETCH 0x08 /* prefetchable? */
100#define PCI_BASE_ADDRESS_MEM_MASK (~0x0fUL)
101#define PCI_BASE_ADDRESS_IO_MASK (~0x03UL)
102/* bit 1 is reserved if address_space = 1 */
103
104/* Header type 0 (normal devices) */
105#define PCI_CARDBUS_CIS 0x28
106#define PCI_SUBSYSTEM_VENDOR_ID 0x2c
107#define PCI_SUBSYSTEM_ID 0x2e
108#define PCI_ROM_ADDRESS 0x30 /* Bits 31..11 are address, 10..1 reserved */
109#define PCI_ROM_ADDRESS_ENABLE 0x01
110#define PCI_ROM_ADDRESS_MASK (~0x7ffUL)
111
112#define PCI_CAPABILITY_LIST 0x34 /* Offset of first capability list entry */
113
114/* 0x35-0x3b are reserved */
115#define PCI_INTERRUPT_LINE 0x3c /* 8 bits */
116#define PCI_INTERRUPT_PIN 0x3d /* 8 bits */
117#define PCI_MIN_GNT 0x3e /* 8 bits */
118#define PCI_MAX_LAT 0x3f /* 8 bits */
119
120/* Header type 1 (PCI-to-PCI bridges) */
121#define PCI_PRIMARY_BUS 0x18 /* Primary bus number */
122#define PCI_SECONDARY_BUS 0x19 /* Secondary bus number */
123#define PCI_SUBORDINATE_BUS 0x1a /* Highest bus number behind the bridge */
124#define PCI_SEC_LATENCY_TIMER 0x1b /* Latency timer for secondary interface */
125#define PCI_IO_BASE 0x1c /* I/O range behind the bridge */
126#define PCI_IO_LIMIT 0x1d
127#define PCI_IO_RANGE_TYPE_MASK 0x0f /* I/O bridging type */
128#define PCI_IO_RANGE_TYPE_16 0x00
129#define PCI_IO_RANGE_TYPE_32 0x01
130#define PCI_IO_RANGE_MASK ~0x0f
131#define PCI_SEC_STATUS 0x1e /* Secondary status register, only bit 14 used */
132#define PCI_MEMORY_BASE 0x20 /* Memory range behind */
133#define PCI_MEMORY_LIMIT 0x22
134#define PCI_MEMORY_RANGE_TYPE_MASK 0x0f
135#define PCI_MEMORY_RANGE_MASK ~0x0f
136#define PCI_PREF_MEMORY_BASE 0x24 /* Prefetchable memory range behind */
137#define PCI_PREF_MEMORY_LIMIT 0x26
138#define PCI_PREF_RANGE_TYPE_MASK 0x0f
139#define PCI_PREF_RANGE_TYPE_32 0x00
140#define PCI_PREF_RANGE_TYPE_64 0x01
141#define PCI_PREF_RANGE_MASK ~0x0f
142#define PCI_PREF_BASE_UPPER32 0x28 /* Upper half of prefetchable memory range */
143#define PCI_PREF_LIMIT_UPPER32 0x2c
144#define PCI_IO_BASE_UPPER16 0x30 /* Upper half of I/O addresses */
145#define PCI_IO_LIMIT_UPPER16 0x32
146/* 0x34 same as for htype 0 */
147/* 0x35-0x3b is reserved */
148#define PCI_ROM_ADDRESS1 0x38 /* Same as PCI_ROM_ADDRESS, but for htype 1 */
149/* 0x3c-0x3d are same as for htype 0 */
150#define PCI_BRIDGE_CONTROL 0x3e
151#define PCI_BRIDGE_CTL_PARITY 0x01 /* Enable parity detection on secondary interface */
152#define PCI_BRIDGE_CTL_SERR 0x02 /* The same for SERR forwarding */
153#define PCI_BRIDGE_CTL_NO_ISA 0x04 /* Disable bridging of ISA ports */
154#define PCI_BRIDGE_CTL_VGA 0x08 /* Forward VGA addresses */
155#define PCI_BRIDGE_CTL_MASTER_ABORT 0x20 /* Report master aborts */
156#define PCI_BRIDGE_CTL_BUS_RESET 0x40 /* Secondary bus reset */
157#define PCI_BRIDGE_CTL_FAST_BACK 0x80 /* Fast Back2Back enabled on secondary interface */
158
159/* Header type 2 (CardBus bridges) */
160/* 0x14-0x15 reserved */
161#define PCI_CB_CAPABILITY_LIST 0x14
162#define PCI_CB_SEC_STATUS 0x16 /* Secondary status */
163#define PCI_CB_PRIMARY_BUS 0x18 /* PCI bus number */
164#define PCI_CB_CARD_BUS 0x19 /* CardBus bus number */
165#define PCI_CB_SUBORDINATE_BUS 0x1a /* Subordinate bus number */
166#define PCI_CB_LATENCY_TIMER 0x1b /* CardBus latency timer */
167#define PCI_CB_MEMORY_BASE_0 0x1c
168#define PCI_CB_MEMORY_LIMIT_0 0x20
169#define PCI_CB_MEMORY_BASE_1 0x24
170#define PCI_CB_MEMORY_LIMIT_1 0x28
171#define PCI_CB_IO_BASE_0 0x2c
172#define PCI_CB_IO_BASE_0_HI 0x2e
173#define PCI_CB_IO_LIMIT_0 0x30
174#define PCI_CB_IO_LIMIT_0_HI 0x32
175#define PCI_CB_IO_BASE_1 0x34
176#define PCI_CB_IO_BASE_1_HI 0x36
177#define PCI_CB_IO_LIMIT_1 0x38
178#define PCI_CB_IO_LIMIT_1_HI 0x3a
179#define PCI_CB_IO_RANGE_MASK ~0x03
180/* 0x3c-0x3d are same as for htype 0 */
181#define PCI_CB_BRIDGE_CONTROL 0x3e
182#define PCI_CB_BRIDGE_CTL_PARITY 0x01 /* Similar to standard bridge control register */
183#define PCI_CB_BRIDGE_CTL_SERR 0x02
184#define PCI_CB_BRIDGE_CTL_ISA 0x04
185#define PCI_CB_BRIDGE_CTL_VGA 0x08
186#define PCI_CB_BRIDGE_CTL_MASTER_ABORT 0x20
187#define PCI_CB_BRIDGE_CTL_CB_RESET 0x40 /* CardBus reset */
188#define PCI_CB_BRIDGE_CTL_16BIT_INT 0x80 /* Enable interrupt for 16-bit cards */
189#define PCI_CB_BRIDGE_CTL_PREFETCH_MEM0 0x100 /* Prefetch enable for both memory regions */
190#define PCI_CB_BRIDGE_CTL_PREFETCH_MEM1 0x200
191#define PCI_CB_BRIDGE_CTL_POST_WRITES 0x400
192#define PCI_CB_SUBSYSTEM_VENDOR_ID 0x40
193#define PCI_CB_SUBSYSTEM_ID 0x42
194#define PCI_CB_LEGACY_MODE_BASE 0x44 /* 16-bit PC Card legacy mode base address (ExCa) */
195/* 0x48-0x7f reserved */
196
197/* Capability lists */
198
199#define PCI_CAP_LIST_ID 0 /* Capability ID */
200#define PCI_CAP_ID_PM 0x01 /* Power Management */
201#define PCI_CAP_ID_AGP 0x02 /* Accelerated Graphics Port */
202#define PCI_CAP_ID_VPD 0x03 /* Vital Product Data */
203#define PCI_CAP_ID_SLOTID 0x04 /* Slot Identification */
204#define PCI_CAP_ID_MSI 0x05 /* Message Signalled Interrupts */
205#define PCI_CAP_ID_CHSWP 0x06 /* CompactPCI HotSwap */
206#define PCI_CAP_LIST_NEXT 1 /* Next capability in the list */
207#define PCI_CAP_FLAGS 2 /* Capability defined flags (16 bits) */
208#define PCI_CAP_SIZEOF 4
209
210/* Power Management Registers */
211#define PCI_PM_PMC 2 /* PM Capabilities Register */
212#define PCI_PM_CAP_VER_MASK 0x0007 /* Version */
213#define PCI_PM_CAP_PME_CLOCK 0x0008 /* PME clock required */
214#define PCI_PM_CAP_AUX_POWER 0x0010 /* Auxilliary power support */
215#define PCI_PM_CAP_DSI 0x0020 /* Device specific initialization */
216#define PCI_PM_CAP_D1 0x0200 /* D1 power state support */
217#define PCI_PM_CAP_D2 0x0400 /* D2 power state support */
218#define PCI_PM_CAP_PME 0x0800 /* PME pin supported */
219#define PCI_PM_CTRL 4 /* PM control and status register */
220#define PCI_PM_CTRL_STATE_MASK 0x0003 /* Current power state (D0 to D3) */
221#define PCI_PM_CTRL_PME_ENABLE 0x0100 /* PME pin enable */
222#define PCI_PM_CTRL_DATA_SEL_MASK 0x1e00 /* Data select (??) */
223#define PCI_PM_CTRL_DATA_SCALE_MASK 0x6000 /* Data scale (??) */
224#define PCI_PM_CTRL_PME_STATUS 0x8000 /* PME pin status */
225#define PCI_PM_PPB_EXTENSIONS 6 /* PPB support extensions (??) */
226#define PCI_PM_PPB_B2_B3 0x40 /* Stop clock when in D3hot (??) */
227#define PCI_PM_BPCC_ENABLE 0x80 /* Bus power/clock control enable (??) */
228#define PCI_PM_DATA_REGISTER 7 /* (??) */
229#define PCI_PM_SIZEOF 8
230
231/* AGP registers */
232
233#define PCI_AGP_VERSION 2 /* BCD version number */
234#define PCI_AGP_RFU 3 /* Rest of capability flags */
235#define PCI_AGP_STATUS 4 /* Status register */
236#define PCI_AGP_STATUS_RQ_MASK 0xff000000 /* Maximum number of requests - 1 */
237#define PCI_AGP_STATUS_SBA 0x0200 /* Sideband addressing supported */
238#define PCI_AGP_STATUS_64BIT 0x0020 /* 64-bit addressing supported */
239#define PCI_AGP_STATUS_FW 0x0010 /* FW transfers supported */
240#define PCI_AGP_STATUS_RATE4 0x0004 /* 4x transfer rate supported */
241#define PCI_AGP_STATUS_RATE2 0x0002 /* 2x transfer rate supported */
242#define PCI_AGP_STATUS_RATE1 0x0001 /* 1x transfer rate supported */
243#define PCI_AGP_COMMAND 8 /* Control register */
244#define PCI_AGP_COMMAND_RQ_MASK 0xff000000 /* Master: Maximum number of requests */
245#define PCI_AGP_COMMAND_SBA 0x0200 /* Sideband addressing enabled */
246#define PCI_AGP_COMMAND_AGP 0x0100 /* Allow processing of AGP transactions */
247#define PCI_AGP_COMMAND_64BIT 0x0020 /* Allow processing of 64-bit addresses */
248#define PCI_AGP_COMMAND_FW 0x0010 /* Force FW transfers */
249#define PCI_AGP_COMMAND_RATE4 0x0004 /* Use 4x rate */
250#define PCI_AGP_COMMAND_RATE2 0x0002 /* Use 4x rate */
251#define PCI_AGP_COMMAND_RATE1 0x0001 /* Use 4x rate */
252#define PCI_AGP_SIZEOF 12
253
254/* Slot Identification */
255
256#define PCI_SID_ESR 2 /* Expansion Slot Register */
257#define PCI_SID_ESR_NSLOTS 0x1f /* Number of expansion slots available */
258#define PCI_SID_ESR_FIC 0x20 /* First In Chassis Flag */
259#define PCI_SID_CHASSIS_NR 3 /* Chassis Number */
260
261/* Message Signalled Interrupts registers */
262
263#define PCI_MSI_FLAGS 2 /* Various flags */
264#define PCI_MSI_FLAGS_64BIT 0x80 /* 64-bit addresses allowed */
265#define PCI_MSI_FLAGS_QSIZE 0x70 /* Message queue size configured */
266#define PCI_MSI_FLAGS_QMASK 0x0e /* Maximum queue size available */
267#define PCI_MSI_FLAGS_ENABLE 0x01 /* MSI feature enabled */
268#define PCI_MSI_RFU 3 /* Rest of capability flags */
269#define PCI_MSI_ADDRESS_LO 4 /* Lower 32 bits */
270#define PCI_MSI_ADDRESS_HI 8 /* Upper 32 bits (if PCI_MSI_FLAGS_64BIT set) */
271#define PCI_MSI_DATA_32 8 /* 16 bits of data for 32-bit devices */
272#define PCI_MSI_DATA_64 12 /* 16 bits of data for 64-bit devices */
273
274/* Include the ID list */
275
276#include <linux/pci_ids.h>
277
278/*
279 * The PCI interface treats multi-function devices as independent
280 * devices. The slot/function address of each device is encoded
281 * in a single byte as follows:
282 *
283 * 7:3 = slot
284 * 2:0 = function
285 */
286#define PCI_DEVFN(slot,func) ((((slot) & 0x1f) << 3) | ((func) & 0x07))
287#define PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f)
288#define PCI_FUNC(devfn) ((devfn) & 0x07)
289
290#ifdef __KERNEL__
291
292#include <linux/types.h>
293#include <linux/ioport.h>
294
295#include <asm/pci.h>
296#define BUS_ID_SIZE 20
297#define DEVICE_COUNT_COMPATIBLE 4
298#define DEVICE_COUNT_IRQ 2
299#define DEVICE_COUNT_DMA 2
300#define DEVICE_COUNT_RESOURCE 12
301
302typedef struct pci_dev;
303
304#define PCI_D0 0
305#define PCI_D1 1
306#define PCI_D2 2
307#define PCI_D3hot 3
308#define PCI_D3cold 4
309#define pci_choose_state(pci,state) ((state) ? PCI_D3hot : PCI_D0)
310
311struct dev_pm_info2 {
312 unsigned int async_suspend:1;
313 bool is_prepared:1; /* Owned by the PM core */
314 u32 power_state;
315 u8 * saved_state;
316 atomic_t pm_users;
317 struct device * pm_parent;
318 struct list_head entry;
319};
320
321/*
322 * The pci_dev structure is used to describe both PCI and ISAPnP devices.
323 */
324struct pci_dev {
325 int active; /* device is active */
326 int ro; /* Read/Only */
327
328 struct pci_bus *bus; /* bus this device is on */
329 struct pci_dev *sibling; /* next device on this bus */
330 struct pci_dev *next; /* chain of all devices */
331
332 void *sysdata; /* hook for sys-specific extension */
333 struct proc_dir_entry *procent; /* device entry in /proc/bus/pci */
334
335 struct device dev;
336 unsigned int class; /* 3 bytes: (base,sub,prog-if) */
337 u8 revision; /* PCI revision, low byte of class word */
338 unsigned int devfn; /* encoded device & function index */
339 unsigned short vendor;
340 unsigned short device;
341 unsigned short subsystem_vendor;
342 unsigned short subsystem_device;
343 u8 hdr_type; /* PCI header type (`multi' flag masked out) */
344 u8 rom_base_reg; /* Which config register controls the ROM */
345
346 unsigned short regs;
347
348 u32 current_state; /* Current operating state. In ACPI-speak,
349 this is D0-D3, D0 being fully functional,
350 and D3 being off. */
351
352 /* device is compatible with these IDs */
353 unsigned short vendor_compatible[DEVICE_COUNT_COMPATIBLE];
354 unsigned short device_compatible[DEVICE_COUNT_COMPATIBLE];
355
356 /*
357 * Instead of touching interrupt line and base address registers
358 * directly, use the values stored here. They might be different!
359 */
360 unsigned int irq;
361 unsigned char irq_pin;
362 struct resource resource[DEVICE_COUNT_RESOURCE]; /* I/O and memory regions + expansion ROMs */
363 struct resource dma_resource[DEVICE_COUNT_DMA];
364 struct resource irq_resource[DEVICE_COUNT_IRQ];
365
366 char name[48]; /* Device name */
367 char slot_name[8]; /* Slot name */
368
369 void *driver_data;
370 u64 dma_mask; /* Mask of the bits of bus address this
371 device implements. Normally this is
372 0xffffffff. You only need to change
373 this if your device has broken DMA
374 or supports 64-bit transfers. */
375 unsigned int no_64bit_msi:1; /* device may only use 32-bit MSIs */
376
377 int (*prepare)(struct pci_dev *dev);
378 int (*activate)(struct pci_dev *dev);
379 int (*deactivate)(struct pci_dev *dev);
380#ifdef TARGET_OS2
381//DAZ unsigned int picirq;
382//DAZ unsigned int apicirq;
383 unsigned long hAdapter;
384//AT unsigned long hDevice;
385 void *pcidriver;
386#endif
387};
388
389/*
390 * For PCI devices, the region numbers are assigned this way:
391 *
392 * 0-5 standard PCI regions
393 * 6 expansion ROM
394 * 7-10 bridges: address space assigned to buses behind the bridge
395 */
396
397#define PCI_ROM_RESOURCE 6
398#define PCI_BRIDGE_RESOURCES 7
399#define PCI_NUM_RESOURCES 11
400
401#define PCI_REGION_FLAG_MASK 0x0f /* These bits of resource flags tell us the PCI region flags */
402
403struct pci_bus {
404 struct pci_bus *parent; /* parent bus this bridge is on */
405 struct pci_bus *children; /* chain of P2P bridges on this bus */
406 struct pci_bus *next; /* chain of all PCI buses */
407 struct pci_ops *ops; /* configuration access functions */
408
409 struct pci_dev *self; /* bridge device as seen by parent */
410 struct pci_dev *devices; /* devices behind this bridge */
411 struct resource *resource[4]; /* address space routed to this bus */
412
413 void *sysdata; /* hook for sys-specific extension */
414 struct proc_dir_entry *procdir; /* directory entry in /proc/bus/pci */
415
416 unsigned char number; /* bus number */
417 unsigned char primary; /* number of primary bridge */
418 unsigned char secondary; /* number of secondary bridge */
419 unsigned char subordinate; /* max number of subordinate buses */
420
421 char name[48];
422 unsigned short vendor;
423 unsigned short device;
424 unsigned int serial; /* serial number */
425 unsigned char pnpver; /* Plug & Play version */
426 unsigned char productver; /* product version */
427 unsigned char checksum; /* if zero - checksum passed */
428 unsigned char pad1;
429};
430
431//extern struct pci_bus *pci_root; /* root bus */
432//extern struct pci_dev *pci_devices; /* list of all devices */
433
434/*
435 * Error values that may be returned by PCI functions.
436 */
437#define PCIBIOS_SUCCESSFUL 0x00
438#define PCIBIOS_FUNC_NOT_SUPPORTED 0x81
439#define PCIBIOS_BAD_VENDOR_ID 0x83
440#define PCIBIOS_DEVICE_NOT_FOUND 0x86
441#define PCIBIOS_BAD_REGISTER_NUMBER 0x87
442#define PCIBIOS_SET_FAILED 0x88
443#define PCIBIOS_BUFFER_TOO_SMALL 0x89
444
445/* Low-level architecture-dependent routines */
446
447struct pci_ops {
448 int (*read_byte)(struct pci_dev *, int where, u8 *val);
449 int (*read_word)(struct pci_dev *, int where, u16 *val);
450 int (*read_dword)(struct pci_dev *, int where, u32 *val);
451 int (*write_byte)(struct pci_dev *, int where, u8 val);
452 int (*write_word)(struct pci_dev *, int where, u16 val);
453 int (*write_dword)(struct pci_dev *, int where, u32 val);
454};
455
456void pcibios_init(void);
457void pcibios_fixup_bus(struct pci_bus *);
458int pcibios_enable_device(struct pci_dev *);
459char *pcibios_setup (char *str);
460
461void pcibios_update_resource(struct pci_dev *, struct resource *,
462 struct resource *, int);
463void pcibios_update_irq(struct pci_dev *, int irq);
464
465/* Backward compatibility, don't use in new code! */
466
467int pcibios_present(void);
468#define pci_present pcibios_present
469int pcibios_read_config_byte (unsigned char bus, unsigned char dev_fn,
470 unsigned char where, unsigned char *val);
471int pcibios_read_config_word (unsigned char bus, unsigned char dev_fn,
472 unsigned char where, unsigned short *val);
473int pcibios_read_config_dword (unsigned char bus, unsigned char dev_fn,
474 unsigned char where, unsigned int *val);
475int pcibios_write_config_byte (unsigned char bus, unsigned char dev_fn,
476 unsigned char where, unsigned char val);
477int pcibios_write_config_word (unsigned char bus, unsigned char dev_fn,
478 unsigned char where, unsigned short val);
479int pcibios_write_config_dword (unsigned char bus, unsigned char dev_fn,
480 unsigned char where, unsigned int val);
481int pcibios_find_class (unsigned int class_code, unsigned short index, unsigned char *bus, unsigned char *dev_fn);
482int pcibios_find_device (unsigned short vendor, unsigned short dev_id,
483 unsigned short index, unsigned char *bus,
484 unsigned char *dev_fn);
485
486/* Generic PCI interface functions */
487
488void pci_init(void);
489struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops, void *sysdata);
490int pci_proc_attach_device(struct pci_dev *dev);
491int pci_proc_detach_device(struct pci_dev *dev);
492void pci_name_device(struct pci_dev *dev);
493void pci_read_bridge_bases(struct pci_bus *child);
494struct resource *pci_find_parent_resource(struct pci_dev *dev, struct resource *res);
495
496struct pci_dev *pci_find_device (unsigned int vendor, unsigned int device, struct pci_dev *from);
497struct pci_dev *pci_find_subsys (unsigned int vendor, unsigned int device,
498 unsigned int ss_vendor, unsigned int ss_device,
499 struct pci_dev *from);
500struct pci_dev *pci_find_class (unsigned int _class, struct pci_dev *from);
501struct pci_dev *pci_find_slot (unsigned int bus, unsigned int devfn);
502int pci_find_capability (struct pci_dev *dev, int cap);
503int pci_dma_supported(struct pci_dev *dev, unsigned long mask);
504
505#define PCI_ANY_ID (~0)
506
507int pci_read_config_byte(struct pci_dev *dev, int where, u8 *val);
508int pci_read_config_word(struct pci_dev *dev, int where, u16 *val);
509int pci_read_config_dword(struct pci_dev *dev, int where, u32 *val);
510int pci_write_config_byte(struct pci_dev *dev, int where, u8 val);
511int pci_write_config_word(struct pci_dev *dev, int where, u16 val);
512int pci_write_config_dword(struct pci_dev *dev, int where, u32 val);
513int pci_enable_device(struct pci_dev *dev);
514void pci_set_master(struct pci_dev *dev);
515int pci_set_power_state(struct pci_dev *dev, int state);
516
517/* Helper functions for low-level code (drivers/pci/setup.c) */
518
519int pci_claim_resource(struct pci_dev *, int);
520void pci_assign_unassigned_resources(u32 min_io, u32 min_mem);
521void pci_set_bus_ranges(void);
522void pci_fixup_irqs(u8 (*)(struct pci_dev *, u8 *),
523 int (*)(struct pci_dev *, u8, u8));
524
525/*
526 * simple PCI probing for drivers (drivers/pci/helper.c)
527 */
528
529struct pci_simple_probe_entry;
530typedef int (*pci_simple_probe_callback) (struct pci_dev *dev, int match_num,
531 const struct pci_simple_probe_entry *ent,
532 void *drvr_data);
533
534struct pci_simple_probe_entry {
535 unsigned short vendor; /* vendor id, PCI_ANY_ID, or 0 for last entry */
536 unsigned short device; /* device id, PCI_ANY_ID, or 0 for last entry */
537 unsigned short subsys_vendor; /* subsystem vendor id, 0 for don't care */
538 unsigned short subsys_device; /* subsystem device id, 0 for don't care */
539 void *dev_data; /* driver-private, entry-specific data */
540};
541
542int pci_simple_probe (const struct pci_simple_probe_entry *list,
543 size_t match_limit, pci_simple_probe_callback cb,
544 void *drvr_data);
545
546
547
548/*
549 * If the system does not have PCI, clearly these return errors. Define
550 * these as simple inline functions to avoid hair in drivers.
551 */
552
553/*
554 * The world is not perfect and supplies us with broken PCI devices.
555 * For at least a part of these bugs we need a work-around, so both
556 * generic (drivers/pci/quirks.c) and per-architecture code can define
557 * fixup hooks to be called for particular buggy devices.
558 */
559
560struct pci_fixup {
561 int pass;
562 u16 vendor, device; /* You can use PCI_ANY_ID here of course */
563 void (*hook)(struct pci_dev *dev);
564};
565
566extern struct pci_fixup pcibios_fixups[];
567
568#define PCI_FIXUP_HEADER 1 /* Called immediately after reading configuration header */
569#define PCI_FIXUP_FINAL 2 /* Final phase of device fixups */
570
571void pci_fixup_device(int pass, struct pci_dev *dev);
572
573extern int pci_pci_problems;
574#define PCIPCI_FAIL 1
575#define PCIPCI_TRITON 2
576#define PCIPCI_NATOMA 4
577
578
579struct pci_device_id {
580 unsigned int vendor, device;
581 unsigned int subvendor, subdevice;
582 unsigned int class, class_mask;
583 unsigned long driver_data;
584};
585
586struct pci_driver {
587 struct list_head node;
588 struct pci_dev *dev;
589 char *name;
590 const struct pci_device_id *id_table; /* NULL if wants all devices */
591 int (*probe)(struct pci_dev *dev, const struct pci_device_id *id); /* New device inserted */
592 void (*remove)(struct pci_dev *dev); /* Device removed (NULL if not a hot-plug capable driver) */
593 int (*suspend)(struct pci_dev *dev, u32 stgate); /* Device suspended */
594 int (*resume)(struct pci_dev *dev); /* Device woken up */
595 void (*shutdown) (struct pci_dev *dev);
596 struct device_driver driver;
597};
598
599/*
600 * Device identifier
601 */
602#define PM_PCI_ID(dev) ((dev)->bus->number << 16 | (dev)->devfn)
603
604#define PCI_GET_DRIVER_DATA pci_get_driver_data
605#define PCI_SET_DRIVER_DATA pci_set_driver_data
606
607int pci_register_driver(struct pci_driver *driver);
608int pci_module_init(struct pci_driver *drv);
609
610int pci_unregister_driver(struct pci_driver *driver);
611
612
613#define pci_dev_g(n) list_entry(n, struct pci_dev, global_list)
614#define pci_dev_b(n) list_entry(n, struct pci_dev, bus_list)
615
616#define pci_for_each_dev(dev) \
617 for(dev = pci_devices; dev; dev = dev->next)
618
619#define pci_resource_start(dev,bar) \
620 (((dev)->resource[(bar)].flags & PCI_BASE_ADDRESS_SPACE) ? \
621 ((dev)->resource[(bar)].start & PCI_BASE_ADDRESS_IO_MASK) : \
622 ((dev)->resource[(bar)].start & PCI_BASE_ADDRESS_MEM_MASK))
623
624#define pci_resource_end(dev,bar) \
625 (((dev)->resource[(bar)].flags & PCI_BASE_ADDRESS_SPACE) ? \
626 ((dev)->resource[(bar)].end & PCI_BASE_ADDRESS_IO_MASK) : \
627 ((dev)->resource[(bar)].end & PCI_BASE_ADDRESS_MEM_MASK))
628
629/*
630 #define pci_resource_end(dev,bar) ((dev)->resource[(bar)].end)
631 */
632#define pci_resource_flags(dev,bar) ((dev)->resource[(bar)].flags)
633
634#define pci_resource_len(dev,bar) \
635 ((pci_resource_start((dev),(bar)) == 0 && \
636 pci_resource_end((dev),(bar)) == \
637 pci_resource_start((dev),(bar))) ? 0 : \
638 \
639 (pci_resource_end((dev),(bar)) - \
640 pci_resource_start((dev),(bar))))
641
642extern struct pci_dev pci_devices[];
643extern struct pci_bus pci_busses[];
644
645/*
646 *
647 */
648const struct pci_device_id *pci_match_id(const struct pci_device_id *ids, struct pci_dev *dev);
649unsigned long pci_get_size (struct pci_dev *dev, int n_base);
650
651int pci_get_flags (struct pci_dev *dev, int n_base);
652int pci_set_power_state(struct pci_dev *dev, int new_state);
653int pci_enable_device(struct pci_dev *dev);
654int pci_find_capability(struct pci_dev *dev, int cap);
655
656void *pci_alloc_consistent(struct pci_dev *, long, dma_addr_t *);
657void pci_free_consistent(struct pci_dev *, long, void *, dma_addr_t);
658
659int pci_dma_supported(struct pci_dev *, dma_addr_t mask);
660void pci_release_regions(struct pci_dev *pdev);
661int pci_request_regions(struct pci_dev *pdev, char *res_name);
662
663void pci_disable_device(struct pci_dev *dev);
664
665int pci_save_state(struct pci_dev *dev);
666int pci_restore_state(struct pci_dev *dev);
667
668unsigned long pci_get_dma_mask(struct pci_dev *);
669#define pci_set_dma_mask(pci, mask) (pci->dma_mask = mask, 0)
670
671void *pci_get_driver_data (struct pci_dev *dev);
672void pci_set_driver_data (struct pci_dev *dev, void *driver_data);
673
674#define pci_get_drvdata(a) pci_get_driver_data(a)
675#define pci_set_drvdata(a,b) pci_set_driver_data(a, b)
676
677#define PCI_DEVICE(vend,dev) \
678 .vendor = (vend), .device = (dev), \
679 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
680
681#define pci_get_device pci_find_device
682#define pci_dev_put(x)
683
684#define to_pci_dev(n) container_of(n, struct pci_dev, dev)
685
686#pragma pack() //!!! by vladest
687
688#endif /* __KERNEL__ */
689
690static inline unsigned char snd_pci_revision(struct pci_dev *pci)
691{
692 unsigned char rev;
693 pci_read_config_byte(pci, PCI_REVISION_ID, &rev);
694 return rev;
695}
696
697/* pci_intx() wrapper */
698#define pci_intx(pci,x)
699
700/* MSI */
701extern int snd_pci_enable_msi(struct pci_dev *dev);
702#undef pci_enable_msi
703#define pci_enable_msi(dev) snd_pci_enable_msi(dev)
704#undef pci_disable_msi
705#define pci_disable_msi(dev)
706extern int snd_pci_dev_present(const struct pci_device_id *ids);
707#define pci_dev_present(x) snd_pci_dev_present(x)
708extern void * __ioremap(unsigned long offset, unsigned long size, unsigned long flags);
709static inline void *pci_ioremap_bar(struct pci_dev *pdev, int bar)
710{
711 return __ioremap(pci_resource_start(pdev, bar),
712 pci_resource_len(pdev, bar),0x010);
713}
714
715#define PCI_VDEVICE(vendor, device) \
716 PCI_VENDOR_ID_##vendor, (device), \
717 PCI_ANY_ID, PCI_ANY_ID, 0, 0
718
719#define pci_clear_master(x)
720
721/* originally it's __devinitconst but we use __devinitdata to be compatible
722 * with older kernels
723 */
724#define DEFINE_PCI_DEVICE_TABLE(_table) \
725 const struct pci_device_id _table[] __devinitdata
726
727/**
728 * module_pci_driver() - Helper macro for registering a PCI driver
729 * @__pci_driver: pci_driver struct
730 *
731 * Helper macro for PCI drivers which do not do anything special in module
732 * init/exit. This eliminates a lot of boilerplate. Each module may only
733 * use this macro once, and calling it replaces module_init() and module_exit()
734 */
735#define module_pci_driver(__pci_driver) \
736 module_driver(__pci_driver, pci_register_driver, \
737 pci_unregister_driver)
738
739static inline bool pci_dev_run_wake(struct pci_dev *dev) { return 0; }
740
741/* If you want to know what to call your pci_dev, ask this function.
742 * Again, it's a wrapper around the generic device.
743 */
744static inline const char *pci_name(struct pci_dev *pdev)
745{
746 return dev_name(&pdev->dev);
747}
748
749/**
750 * PCI_DEVICE_SUB - macro used to describe a specific pci device with subsystem
751 * @vend: the 16 bit PCI Vendor ID
752 * @dev: the 16 bit PCI Device ID
753 * @subvend: the 16 bit PCI Subvendor ID
754 * @subdev: the 16 bit PCI Subdevice ID
755 *
756 * This macro is used to create a struct pci_device_id that matches a
757 * specific device with subsystem information.
758 */
759#define PCI_DEVICE_SUB(vend, dev, subvend, subdev) \
760 .vendor = (vend), .device = (dev), \
761 .subvendor = (subvend), .subdevice = (subdev)
762
763int pci_status_get_and_clear_errors(struct pci_dev *pdev);
764#define PCI_STATUS_ERROR_BITS (PCI_STATUS_DETECTED_PARITY | \
765 PCI_STATUS_SIG_SYSTEM_ERROR | \
766 PCI_STATUS_REC_MASTER_ABORT | \
767 PCI_STATUS_REC_TARGET_ABORT | \
768 PCI_STATUS_SIG_TARGET_ABORT | \
769 PCI_STATUS_PARITY)
770
771#define dev_is_pci(d) (true)
772int pcim_enable_device(struct pci_dev *pdev);
773#define pcim_iomap pci_iomap
774int pcim_iomap_regions(struct pci_dev *pdev, int mask, const char *name);
775#endif /* LINUX_PCI_H */
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