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A Performance-Driven Placement Algorithm with Simultaneous Place&Route Optimization for Analog IC's

Authors:

Juan A. Prieto,

Adoracion Rueda,

Jose M. Quintana,

Jose L. HuertasAuthors Info & Claims

EDTC '97: Proceedings of the 1997 European conference on Design and Test

Page 389

Published: 17 March 1997 Publication History

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Abstract

This paper presents a performance-driven placement algorithm for automatic layout generation of analog IC's. The main innovations of our approach are essentially: (i) an integrated Place&Route optimization algorithm which is able to provide a realistic measurement of the interconnect parasitics, that is a key issue in performance-driven approaches; and (ii) the simultaneous consideration in the cost function of two levels of symmetries: global symmetry with respect to virtual axes and local symmetry affecting groups of cells. The flexibility and efficiency of the algorithm is mainly due to the use of the same slicing-tree representation for placement and global routing, and to the heuristic algorithm we propose for the global routing estimate. The feasibility of the proposed approach has been demonstrated with several practical examples.

References

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Cited By

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Ou HChien HChang Y(2013)Simultaneous analog placement and routing with current flow and current density considerationsProceedings of the 50th Annual Design Automation Conference10.1145/2463209.2488739(1-6)Online publication date: 29-May-2013
https://dl.acm.org/doi/10.1145/2463209.2488739
Gielen GRutenbar R(2001)Synthesis of analog and mixed-signal integrated electronic circuitsFormal engineering design synthesis10.5555/762002.762016(391-427)Online publication date: 1-Jan-2001
https://dl.acm.org/doi/10.5555/762002.762016
Prieto JRueda AGrout IPeralías EHuertas JRichardson ADewilde PRammig FMusgrave G(1998)An approach to realistic fault prediction and layout design for testability in analog circuitsProceedings of the conference on Design, automation and test in Europe10.5555/368058.368455(905-911)Online publication date: 23-Feb-1998
https://dl.acm.org/doi/10.5555/368058.368455

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EDTC '97: Proceedings of the 1997 European conference on Design and Test

March 1997

596 pages

ISBN:0818677864

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IEEE Computer Society

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Published: 17 March 1997

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EDTC96: European Design and Test Conference

March 17 - 20, 1997

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Ou HChien HChang Y(2013)Simultaneous analog placement and routing with current flow and current density considerationsProceedings of the 50th Annual Design Automation Conference10.1145/2463209.2488739(1-6)Online publication date: 29-May-2013
https://dl.acm.org/doi/10.1145/2463209.2488739
Gielen GRutenbar R(2001)Synthesis of analog and mixed-signal integrated electronic circuitsFormal engineering design synthesis10.5555/762002.762016(391-427)Online publication date: 1-Jan-2001
https://dl.acm.org/doi/10.5555/762002.762016
Prieto JRueda AGrout IPeralías EHuertas JRichardson ADewilde PRammig FMusgrave G(1998)An approach to realistic fault prediction and layout design for testability in analog circuitsProceedings of the conference on Design, automation and test in Europe10.5555/368058.368455(905-911)Online publication date: 23-Feb-1998
https://dl.acm.org/doi/10.5555/368058.368455

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Routability-driven placement algorithm for analog integrated circuits

Performance-driven simultaneous placement and routing for FPGA's

A robust detailed placement for mixed-size IC designs

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Routability-driven placement algorithm for analog integrated circuits

Performance-driven simultaneous placement and routing for FPGA's

A robust detailed placement for mixed-size IC designs

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