Automatic generation of parasitic constraints for performance-constrained physical design of analog circuits
U Choudhury… - IEEE transactions on …, 1993 - ieeexplore.ieee.org
U Choudhury, A Sangiovanni-Vincentelli
IEEE transactions on computer-aided design of integrated circuits …, 1993•ieeexplore.ieee.orgA design methodology for the physical design of analog circuits is proposed. The
methodology is based on the automatic generation of constraints on parasitics introduced
during the layout phase from constraints on the functional performance of the circuit. In this
novel performance-constrained approach, the parasitic constraints drive the layout tools to
reduce the need for further layout iterations. Parasitic constraint generation involves (1)
generation of a set of bounding constraints on the critical parasitics of a circuit to provide …
methodology is based on the automatic generation of constraints on parasitics introduced
during the layout phase from constraints on the functional performance of the circuit. In this
novel performance-constrained approach, the parasitic constraints drive the layout tools to
reduce the need for further layout iterations. Parasitic constraint generation involves (1)
generation of a set of bounding constraints on the critical parasitics of a circuit to provide …
A design methodology for the physical design of analog circuits is proposed. The methodology is based on the automatic generation of constraints on parasitics introduced during the layout phase from constraints on the functional performance of the circuit. In this novel performance-constrained approach, the parasitic constraints drive the layout tools to reduce the need for further layout iterations. Parasitic constraint generation involves (1) generation of a set of bounding constraints on the critical parasitics of a circuit to provide maximum flexibility to the layout tools while meeting the performance constraints; and (2) deriving a set of matching constraints on the parasitics from matched-node-pair and matched-branch-pair information in differential circuits. The constraint generator PARCAR is described and results presented for test circuits.< >
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