Changeset 305 for GPL/branches/uniaud-2.0/alsa-kernel/pci/cmipci.c
- Timestamp:
- Mar 24, 2008, 2:43:42 AM (17 years ago)
- File:
-
- 1 edited
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- Unmodified
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GPL/branches/uniaud-2.0/alsa-kernel/pci/cmipci.c
r135 r305 17 17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 18 18 */ 19 19 20 20 /* Does not work. Warning may block system in capture mode */ 21 21 /* #define USE_VAR48KRATE */ 22 22 23 #include <sound/driver.h>24 23 #include <asm/io.h> 25 //#include <linux/interrupt.h> 24 #include <linux/delay.h> 25 #include <linux/interrupt.h> 26 26 #include <linux/init.h> 27 #include <linux/delay.h> 28 //#include <linux/pci.h> 27 #include <linux/pci.h> 29 28 #include <linux/slab.h> 29 #include <linux/gameport.h> 30 #include <linux/moduleparam.h> 31 #include <linux/mutex.h> 30 32 #include <sound/core.h> 31 33 #include <sound/info.h> … … 37 39 #include <sound/sb.h> 38 40 #include <sound/asoundef.h> 39 #define SNDRV_GET_ID40 41 #include <sound/initval.h> 41 42 … … 43 44 MODULE_DESCRIPTION("C-Media CMI8x38 PCI"); 44 45 MODULE_LICENSE("GPL"); 45 MODULE_CLASSES("{sound}"); 46 MODULE_DEVICES("{{C-Media,CMI8738}," 47 "{C-Media,CMI8738B}," 48 "{C-Media,CMI8338A}," 49 "{C-Media,CMI8338B}}"); 50 51 extern int midi_port; 46 MODULE_SUPPORTED_DEVICE("{{C-Media,CMI8738}," 47 "{C-Media,CMI8738B}," 48 "{C-Media,CMI8338A}," 49 "{C-Media,CMI8338B}}"); 50 51 #if defined(CONFIG_GAMEPORT) || (defined(MODULE) && defined(CONFIG_GAMEPORT_MODULE)) 52 #define SUPPORT_JOYSTICK 1 53 #endif 52 54 53 55 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */ 54 56 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */ 55 57 static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable switches */ 56 //MPU disabled for now until it's fully supported by the MMPM2 driver 57 static long mpu_port[SNDRV_CARDS] = {-1,-1,-1,-1,-1,-1,-1,-1}; 58 static long fm_port[SNDRV_CARDS] = {0x388, -1,-1,-1,-1,-1,-1,-1}; 59 60 static int soft_ac3[SNDRV_CARDS] = {0,1,1,1,1,1,1,1}; 61 62 MODULE_PARM(index, "1-" __MODULE_STRING(SNDRV_CARDS) "i"); 58 static long mpu_port[SNDRV_CARDS]; 59 static long fm_port[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)]=1}; 60 static int soft_ac3[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)]=1}; 61 #ifdef SUPPORT_JOYSTICK 62 static int joystick_port[SNDRV_CARDS]; 63 #endif 64 65 module_param_array(index, int, NULL, 0444); 63 66 MODULE_PARM_DESC(index, "Index value for C-Media PCI soundcard."); 64 MODULE_PARM_SYNTAX(index, SNDRV_INDEX_DESC); 65 MODULE_PARM(id, "1-" __MODULE_STRING(SNDRV_CARDS) "s"); 67 module_param_array(id, charp, NULL, 0444); 66 68 MODULE_PARM_DESC(id, "ID string for C-Media PCI soundcard."); 67 MODULE_PARM_SYNTAX(id, SNDRV_ID_DESC); 68 MODULE_PARM(enable, "1-" __MODULE_STRING(SNDRV_CARDS) "i"); 69 module_param_array(enable, bool, NULL, 0444); 69 70 MODULE_PARM_DESC(enable, "Enable C-Media PCI soundcard."); 70 MODULE_PARM_SYNTAX(enable, SNDRV_ENABLE_DESC); 71 MODULE_PARM(mpu_port, "1-" __MODULE_STRING(SNDRV_CARDS) "l"); 71 module_param_array(mpu_port, long, NULL, 0444); 72 72 MODULE_PARM_DESC(mpu_port, "MPU-401 port."); 73 MODULE_PARM_SYNTAX(mpu_port, SNDRV_ENABLED ",allows:{{-1},{0x330},{0x320},{0x310},{0x300}},dialog:list"); 74 MODULE_PARM(fm_port, "1-" __MODULE_STRING(SNDRV_CARDS) "l"); 73 module_param_array(fm_port, long, NULL, 0444); 75 74 MODULE_PARM_DESC(fm_port, "FM port."); 76 MODULE_PARM_SYNTAX(fm_port, SNDRV_ENABLED ",allows:{{-1},{0x388},{0x3c8},{0x3e0},{0x3e8}},dialog:list"); 77 #ifdef DO_SOFT_AC3 78 MODULE_PARM(soft_ac3, "1-" __MODULE_STRING(SNDRV_CARDS) "l"); 75 module_param_array(soft_ac3, bool, NULL, 0444); 79 76 MODULE_PARM_DESC(soft_ac3, "Sofware-conversion of raw SPDIF packets (model 033 only)."); 80 MODULE_PARM_SYNTAX(soft_ac3, SNDRV_ENABLED "," SNDRV_BOOLEAN_TRUE_DESC); 77 #ifdef SUPPORT_JOYSTICK 78 module_param_array(joystick_port, int, NULL, 0444); 79 MODULE_PARM_DESC(joystick_port, "Joystick port address."); 81 80 #endif 82 81 83 #ifndef PCI_DEVICE_ID_CMEDIA_CM873884 #define PCI_DEVICE_ID_CMEDIA_CM8738 0x011185 #endif86 #ifndef PCI_DEVICE_ID_CMEDIA_CM8738B87 #define PCI_DEVICE_ID_CMEDIA_CM8738B 0x011288 #endif89 90 //#define SIX_CH_HACK91 82 /* 92 83 * CM8x38 registers definition … … 104 95 105 96 #define CM_REG_FUNCTRL1 0x04 106 #define CM_ ASFC_MASK 0x0000E000 /* ADCsampling frequency */107 #define CM_ ASFC_SHIFT 13108 #define CM_ DSFC_MASK 0x00001C00 /* DACsampling frequency */109 #define CM_ DSFC_SHIFT 1097 #define CM_DSFC_MASK 0x0000E000 /* channel 1 (DAC?) sampling frequency */ 98 #define CM_DSFC_SHIFT 13 99 #define CM_ASFC_MASK 0x00001C00 /* channel 0 (ADC?) sampling frequency */ 100 #define CM_ASFC_SHIFT 10 110 101 #define CM_SPDF_1 0x00000200 /* SPDIF IN/OUT at channel B */ 111 102 #define CM_SPDF_0 0x00000100 /* SPDIF OUT only channel A */ 112 #define CM_SPDFLOOP 0x00000080 /* ext. SPDIIF/ OUT -> INloopback */103 #define CM_SPDFLOOP 0x00000080 /* ext. SPDIIF/IN -> OUT loopback */ 113 104 #define CM_SPDO2DAC 0x00000040 /* SPDIF/OUT can be heard from internal DAC */ 114 105 #define CM_INTRM 0x00000020 /* master control block (MCB) interrupt enabled */ 115 106 #define CM_BREQ 0x00000010 /* bus master enabled */ 116 107 #define CM_VOICE_EN 0x00000008 /* legacy voice (SB16,FM) */ 117 #define CM_UART_EN 0x00000004 /* UART */ 118 #define CM_JYSTK_EN 0x00000002 /* joy stick */ 108 #define CM_UART_EN 0x00000004 /* legacy UART */ 109 #define CM_JYSTK_EN 0x00000002 /* legacy joystick */ 110 #define CM_ZVPORT 0x00000001 /* ZVPORT */ 119 111 120 112 #define CM_REG_CHFORMAT 0x08 121 113 122 114 #define CM_CHB3D5C 0x80000000 /* 5,6 channels */ 115 #define CM_FMOFFSET2 0x40000000 /* initial FM PCM offset 2 when Fmute=1 */ 123 116 #define CM_CHB3D 0x20000000 /* 4 channels */ 124 117 125 118 #define CM_CHIP_MASK1 0x1f000000 126 119 #define CM_CHIP_037 0x01000000 127 120 #define CM_SETLAT48 0x00800000 /* set latency timer 48h */ 121 #define CM_EDGEIRQ 0x00400000 /* emulated edge trigger legacy IRQ */ 122 #define CM_SPD24SEL39 0x00200000 /* 24-bit spdif: model 039 */ 123 #define CM_AC3EN1 0x00100000 /* enable AC3: model 037 */ 128 124 #define CM_SPDIF_SELECT1 0x00080000 /* for model <= 037 ? */ 129 #define CM_AC3EN1 0x00100000 /* enable AC3: model 037 */130 125 #define CM_SPD24SEL 0x00020000 /* 24bit spdif: model 037 */ 131 126 /* #define CM_SPDIF_INVERSE 0x00010000 */ /* ??? */ 132 127 133 #define CM_ADCBITLEN_MASK 0x0000C000 128 #define CM_ADCBITLEN_MASK 0x0000C000 134 129 #define CM_ADCBITLEN_16 0x00000000 135 130 #define CM_ADCBITLEN_15 0x00004000 … … 137 132 #define CM_ADCBITLEN_13 0x0000C000 138 133 139 #define CM_ADCDACLEN_MASK 0x00003000 134 #define CM_ADCDACLEN_MASK 0x00003000 /* model 037 */ 140 135 #define CM_ADCDACLEN_060 0x00000000 141 136 #define CM_ADCDACLEN_066 0x00001000 … … 143 138 #define CM_ADCDACLEN_280 0x00003000 144 139 140 #define CM_ADCDLEN_MASK 0x00003000 /* model 039 */ 141 #define CM_ADCDLEN_ORIGINAL 0x00000000 142 #define CM_ADCDLEN_EXTRA 0x00001000 143 #define CM_ADCDLEN_24K 0x00002000 144 #define CM_ADCDLEN_WEIGHT 0x00003000 145 145 146 #define CM_CH1_SRATE_176K 0x00000800 147 #define CM_CH1_SRATE_96K 0x00000800 /* model 055? */ 146 148 #define CM_CH1_SRATE_88K 0x00000400 147 149 #define CM_CH0_SRATE_176K 0x00000200 150 #define CM_CH0_SRATE_96K 0x00000200 /* model 055? */ 148 151 #define CM_CH0_SRATE_88K 0x00000100 152 #define CM_CH0_SRATE_128K 0x00000300 153 #define CM_CH0_SRATE_MASK 0x00000300 149 154 150 155 #define CM_SPDIF_INVERSE2 0x00000080 /* model 055? */ 151 152 #define CM_CH1FMT_MASK 0x0000000C 156 #define CM_DBLSPDS 0x00000040 /* double SPDIF sample rate 88.2/96 */ 157 #define CM_POLVALID 0x00000020 /* inverse SPDIF/IN valid bit */ 158 #define CM_SPDLOCKED 0x00000010 159 160 #define CM_CH1FMT_MASK 0x0000000C /* bit 3: 16 bits, bit 2: stereo */ 153 161 #define CM_CH1FMT_SHIFT 2 154 #define CM_CH0FMT_MASK 0x00000003 162 #define CM_CH0FMT_MASK 0x00000003 /* bit 1: 16 bits, bit 0: stereo */ 155 163 #define CM_CH0FMT_SHIFT 0 156 164 157 165 #define CM_REG_INT_HLDCLR 0x0C 158 166 #define CM_CHIP_MASK2 0xff000000 167 #define CM_CHIP_8768 0x20000000 168 #define CM_CHIP_055 0x08000000 159 169 #define CM_CHIP_039 0x04000000 160 170 #define CM_CHIP_039_6CH 0x01000000 161 #define CM_CHIP_055 0x08000000 162 #define CM_CHIP_8768 0x20000000 171 #define CM_UNKNOWN_INT_EN 0x00080000 /* ? */ 163 172 #define CM_TDMA_INT_EN 0x00040000 164 173 #define CM_CH1_INT_EN 0x00020000 165 174 #define CM_CH0_INT_EN 0x00010000 166 #define CM_INT_HOLD 0x00000002167 #define CM_INT_CLEAR 0x00000001168 175 169 176 #define CM_REG_INT_STATUS 0x10 … … 184 191 185 192 #define CM_REG_LEGACY_CTRL 0x14 186 #define CM_NXCHG 0x80000000 /* h/w multi channels?*/193 #define CM_NXCHG 0x80000000 /* don't map base reg dword->sample */ 187 194 #define CM_VMPU_MASK 0x60000000 /* MPU401 i/o port address */ 188 195 #define CM_VMPU_330 0x00000000 … … 190 197 #define CM_VMPU_310 0x40000000 191 198 #define CM_VMPU_300 0x60000000 199 #define CM_ENWR8237 0x10000000 /* enable bus master to write 8237 base reg */ 192 200 #define CM_VSBSEL_MASK 0x0C000000 /* SB16 base address */ 193 201 #define CM_VSBSEL_220 0x00000000 … … 200 208 #define CM_FMSEL_3E0 0x02000000 201 209 #define CM_FMSEL_3E8 0x03000000 202 #define CM_ENSPDOUT 0x00800000 /* enable X PDIF/OUT to I/O interface */203 #define CM_SPDCOPYRHT 0x00400000 /* s et copyright spdif in/out */210 #define CM_ENSPDOUT 0x00800000 /* enable XSPDIF/OUT to I/O interface */ 211 #define CM_SPDCOPYRHT 0x00400000 /* spdif in/out copyright bit */ 204 212 #define CM_DAC2SPDO 0x00200000 /* enable wave+fm_midi -> SPDIF/OUT */ 205 #define CM_SETRETRY 0x00010000 /* 0: legacy i/o wait (default), 1: legacy i/o bus retry */ 213 #define CM_INVIDWEN 0x00100000 /* internal vendor ID write enable, model 039? */ 214 #define CM_SETRETRY 0x00100000 /* 0: legacy i/o wait (default), 1: legacy i/o bus retry */ 215 #define CM_C_EEACCESS 0x00080000 /* direct programming eeprom regs */ 216 #define CM_C_EECS 0x00040000 217 #define CM_C_EEDI46 0x00020000 218 #define CM_C_EECK46 0x00010000 206 219 #define CM_CHB3D6C 0x00008000 /* 5.1 channels support */ 207 #define CM_LINE_AS_BASS 0x00006000 /* use line-in as bass */ 220 #define CM_CENTR2LIN 0x00004000 /* line-in as center out */ 221 #define CM_BASE2LIN 0x00002000 /* line-in as bass out */ 222 #define CM_EXBASEN 0x00001000 /* external bass input enable */ 208 223 209 224 #define CM_REG_MISC_CTRL 0x18 210 #define CM_PWD 0x80000000 225 #define CM_PWD 0x80000000 /* power down */ 211 226 #define CM_RESET 0x40000000 212 #define CM_SFIL_MASK 0x30000000 213 #define CM_TXVX 0x08000000 214 #define CM_N4SPK3D 0x04000000 /* 4ch output */ 227 #define CM_SFIL_MASK 0x30000000 /* filter control at front end DAC, model 037? */ 228 #define CM_VMGAIN 0x10000000 /* analog master amp +6dB, model 039? */ 229 #define CM_TXVX 0x08000000 /* model 037? */ 230 #define CM_N4SPK3D 0x04000000 /* copy front to rear */ 215 231 #define CM_SPDO5V 0x02000000 /* 5V spdif output (1 = 0.5v (coax)) */ 216 232 #define CM_SPDIF48K 0x01000000 /* write */ 217 233 #define CM_SPATUS48K 0x01000000 /* read */ 218 #define CM_ENDBDAC 0x00800000 /* enable d ualdac */234 #define CM_ENDBDAC 0x00800000 /* enable double dac */ 219 235 #define CM_XCHGDAC 0x00400000 /* 0: front=ch0, 1: front=ch1 */ 220 236 #define CM_SPD32SEL 0x00200000 /* 0: 16bit SPDIF, 1: 32bit */ 221 #define CM_SPDFLOOPI 0x00100000 /* int. SPDIF- IN -> int. OUT*/222 #define CM_FM_EN 0x00080000 /* ena lbeFM */237 #define CM_SPDFLOOPI 0x00100000 /* int. SPDIF-OUT -> int. IN */ 238 #define CM_FM_EN 0x00080000 /* enable legacy FM */ 223 239 #define CM_AC3EN2 0x00040000 /* enable AC3: model 039 */ 224 #define CM_VIDWPDSB 0x00010000 240 #define CM_ENWRASID 0x00010000 /* choose writable internal SUBID (audio) */ 241 #define CM_VIDWPDSB 0x00010000 /* model 037? */ 225 242 #define CM_SPDF_AC97 0x00008000 /* 0: SPDIF/OUT 44.1K, 1: 48K */ 226 #define CM_MASK_EN 0x00004000 227 #define CM_VIDWPPRT 0x00002000 228 #define CM_SFILENB 0x00001000 229 #define CM_MMODE_MASK 0x00000E00 243 #define CM_MASK_EN 0x00004000 /* activate channel mask on legacy DMA */ 244 #define CM_ENWRMSID 0x00002000 /* choose writable internal SUBID (modem) */ 245 #define CM_VIDWPPRT 0x00002000 /* model 037? */ 246 #define CM_SFILENB 0x00001000 /* filter stepping at front end DAC, model 037? */ 247 #define CM_MMODE_MASK 0x00000E00 /* model DAA interface mode */ 230 248 #define CM_SPDIF_SELECT2 0x00000100 /* for model > 039 ? */ 231 249 #define CM_ENCENTER 0x00000080 232 #define CM_FLINKON 0x00000040 233 #define CM_FLINKOFF 0x00000020 234 #define CM_MIDSMP 0x00000010 235 #define CM_UPDDMA_MASK 0x0000000C 236 #define CM_TWAIT_MASK 0x00000003 237 238 /* byte */ 250 #define CM_FLINKON 0x00000040 /* force modem link detection on, model 037 */ 251 #define CM_MUTECH1 0x00000040 /* mute PCI ch1 to DAC */ 252 #define CM_FLINKOFF 0x00000020 /* force modem link detection off, model 037 */ 253 #define CM_MIDSMP 0x00000010 /* 1/2 interpolation at front end DAC */ 254 #define CM_UPDDMA_MASK 0x0000000C /* TDMA position update notification */ 255 #define CM_UPDDMA_2048 0x00000000 256 #define CM_UPDDMA_1024 0x00000004 257 #define CM_UPDDMA_512 0x00000008 258 #define CM_UPDDMA_256 0x0000000C 259 #define CM_TWAIT_MASK 0x00000003 /* model 037 */ 260 #define CM_TWAIT1 0x00000002 /* FM i/o cycle, 0: 48, 1: 64 PCICLKs */ 261 #define CM_TWAIT0 0x00000001 /* i/o cycle, 0: 4, 1: 6 PCICLKs */ 262 263 #define CM_REG_TDMA_POSITION 0x1C 264 #define CM_TDMA_CNT_MASK 0xFFFF0000 /* current byte/word count */ 265 #define CM_TDMA_ADR_MASK 0x0000FFFF /* current address */ 266 267 /* byte */ 239 268 #define CM_REG_MIXER0 0x20 269 #define CM_REG_SBVR 0x20 /* write: sb16 version */ 270 #define CM_REG_DEV 0x20 /* read: hardware device version */ 271 272 #define CM_REG_MIXER21 0x21 273 #define CM_UNKNOWN_21_MASK 0x78 /* ? */ 274 #define CM_X_ADPCM 0x04 /* SB16 ADPCM enable */ 275 #define CM_PROINV 0x02 /* SBPro left/right channel switching */ 276 #define CM_X_SB16 0x01 /* SB16 compatible */ 240 277 241 278 #define CM_REG_SB16_DATA 0x22 … … 252 289 #define CM_WSMUTE 0x40 /* mute PCM */ 253 290 #define CM_WSMUTE_SHIFT 6 254 #define CM_ SPK40x20 /* lin-in -> rear line out */255 #define CM_ SPK4_SHIFT5291 #define CM_REAR2LIN 0x20 /* lin-in -> rear line out */ 292 #define CM_REAR2LIN_SHIFT 5 256 293 #define CM_REAR2FRONT 0x10 /* exchange rear/front */ 257 294 #define CM_REAR2FRONT_SHIFT 4 … … 279 316 #define CM_MICGAINZ_SHIFT 0 280 317 281 #define CM_REG_MIXER3 318 #define CM_REG_MIXER3 0x24 282 319 #define CM_REG_AUX_VOL 0x26 283 320 #define CM_VAUXL_MASK 0xf0 … … 285 322 286 323 #define CM_REG_MISC 0x27 324 #define CM_UNKNOWN_27_MASK 0xd8 /* ? */ 287 325 #define CM_XGPO1 0x20 288 326 // #define CM_XGPBIO 0x04 … … 290 328 #define CM_SPDIF_INVERSE 0x04 /* spdif input phase inverse (model 037) */ 291 329 #define CM_SPDVALID 0x02 /* spdif input valid check */ 292 #define CM_DMAUTO 0x01 330 #define CM_DMAUTO 0x01 /* SB16 DMA auto detect */ 293 331 294 332 #define CM_REG_AC97 0x28 /* hmmm.. do we have ac97 link? */ … … 319 357 #define CM_RLOOPREN 0x04 /* Rec. R-channel enable */ 320 358 #define CM_RLOOPLEN 0x02 /* Rec. L-channel enable */ 321 #define CM_VADMIC3 0x01/* Mic record boost */359 #define CM_VADMIC3 0x01 /* Mic record boost */ 322 360 323 361 /* … … 331 369 * extended registers 332 370 */ 333 #define CM_REG_CH0_FRAME1 0x80 /* base address */334 #define CM_REG_CH0_FRAME2 0x84 371 #define CM_REG_CH0_FRAME1 0x80 /* write: base address */ 372 #define CM_REG_CH0_FRAME2 0x84 /* read: current address */ 335 373 #define CM_REG_CH1_FRAME1 0x88 /* 0-15: count of samples at bus master; buffer size */ 336 374 #define CM_REG_CH1_FRAME2 0x8C /* 16-31: count of samples at codec; fragment size */ 337 #define CM_REG_EXT_MISC 0x90 338 #define CM_REG_MISC_CTRL_8768 0x92 /* reg. name the same as 0x18 */ 339 #define CM_CHB3D8C 0x20 /* 7.1 channels support */ 340 #define CM_SPD32FMT 0x10 /* SPDIF/IN 32k */ 341 #define CM_ADC2SPDIF 0x08 /* ADC output to SPDIF/OUT */ 342 #define CM_SHAREADC 0x04 /* DAC in ADC as Center/LFE */ 343 #define CM_REALTCMP 0x02 /* monitor the CMPL/CMPR of ADC */ 344 #define CM_INVLRCK 0x01 /* invert ZVPORT's LRCK */ 375 376 #define CM_REG_EXT_MISC 0x90 377 #define CM_ADC48K44K 0x10000000 /* ADC parameters group, 0: 44k, 1: 48k */ 378 #define CM_CHB3D8C 0x00200000 /* 7.1 channels support */ 379 #define CM_SPD32FMT 0x00100000 /* SPDIF/IN 32k sample rate */ 380 #define CM_ADC2SPDIF 0x00080000 /* ADC output to SPDIF/OUT */ 381 #define CM_SHAREADC 0x00040000 /* DAC in ADC as Center/LFE */ 382 #define CM_REALTCMP 0x00020000 /* monitor the CMPL/CMPR of ADC */ 383 #define CM_INVLRCK 0x00010000 /* invert ZVPORT's LRCK */ 384 #define CM_UNKNOWN_90_MASK 0x0000FFFF /* ? */ 385 345 386 /* 346 387 * size of i/o region … … 350 391 #define CM_EXTENT_SYNTH 0x4 351 392 352 /*353 * pci ids354 */355 #ifndef PCI_VENDOR_ID_CMEDIA356 #define PCI_VENDOR_ID_CMEDIA 0x13F6357 #endif358 #ifndef PCI_DEVICE_ID_CMEDIA_CM8338A359 #define PCI_DEVICE_ID_CMEDIA_CM8338A 0x0100360 #endif361 #ifndef PCI_DEVICE_ID_CMEDIA_CM8338B362 #define PCI_DEVICE_ID_CMEDIA_CM8338B 0x0101363 #endif364 #ifndef PCI_DEVICE_ID_CMEDIA_CM8738365 #define PCI_DEVICE_ID_CMEDIA_CM8738 0x0111366 #endif367 #ifndef PCI_DEVICE_ID_CMEDIA_CM8738B368 #define PCI_DEVICE_ID_CMEDIA_CM8738B 0x0112369 #endif370 393 371 394 /* … … 408 431 409 432 struct cmipci_pcm { 410 struct snd_pcm_substream *substream; 411 int running; /* dac/adc running? */ 412 unsigned int dma_size; /* in frames */ 413 unsigned int period_size; /* in frames */ 414 unsigned int offset; /* physical address of the buffer */ 415 unsigned int fmt; /* format bits */ 416 int ch; /* channel (0/1) */ 417 unsigned int is_dac; /* is dac? */ 418 int bytes_per_frame; 419 int shift; 433 struct snd_pcm_substream *substream; 434 u8 running; /* dac/adc running? */ 435 u8 fmt; /* format bits */ 436 u8 is_dac; 437 u8 needs_silencing; 438 unsigned int dma_size; /* in frames */ 439 unsigned int shift; 440 unsigned int ch; /* channel (0/1) */ 441 unsigned int offset; /* physical address of the buffer */ 420 442 }; 421 443 422 444 /* mixer elements toggled/resumed during ac3 playback */ 423 445 struct cmipci_mixer_auto_switches { 424 425 446 const char *name; /* switch to toggle */ 447 int toggle_on; /* value to change when ac3 mode */ 426 448 }; 427 449 static const struct cmipci_mixer_auto_switches cm_saved_mixer[] = { 428 429 430 431 432 450 {"PCM Playback Switch", 0}, 451 {"IEC958 Output Switch", 1}, 452 {"IEC958 Mix Analog", 0}, 453 // {"IEC958 Out To DAC", 1}, // no longer used 454 {"IEC958 Loop", 0}, 433 455 }; 434 435 456 #define CM_SAVED_MIXERS ARRAY_SIZE(cm_saved_mixer) 436 457 437 458 struct cmipci { 438 struct snd_card *card; 439 440 struct pci_dev *pci; 441 unsigned int device; /* device ID */ 442 int irq; 443 444 unsigned long iobase; 445 unsigned int ctrl; /* FUNCTRL0 current value */ 446 447 struct snd_pcm *pcm; /* DAC/ADC PCM */ 448 struct snd_pcm *pcm2; /* 2nd DAC */ 449 struct snd_pcm *pcm_spdif; /* SPDIF */ 450 451 int chip_version; 452 int max_channels; 453 unsigned int has_dual_dac: 1; 454 unsigned int can_ac3_sw: 1; 455 unsigned int can_ac3_hw: 1; 456 unsigned int can_multi_ch: 1; 457 unsigned int do_soft_ac3: 1; 458 459 unsigned int spdif_playback_avail: 1; /* spdif ready? */ 460 unsigned int spdif_playback_enabled: 1; /* spdif switch enabled? */ 461 int spdif_counter; /* for software AC3 */ 462 463 unsigned int dig_status; 464 unsigned int dig_pcm_status; 465 466 struct snd_pcm_hardware_t *hw_info[3]; /* for playbacks */ 467 468 int opened[2]; /* open mode */ 469 struct semaphore open_mutex; 470 471 int mixer_insensitive: 1; 472 struct snd_kcontrol *mixer_res_ctl[CM_SAVED_MIXERS]; 473 int mixer_res_status[CM_SAVED_MIXERS]; 474 475 struct cmipci_pcm channel[2]; /* ch0 - DAC, ch1 - ADC or 2nd DAC */ 476 477 /* external MIDI */ 478 struct snd_rawmidi *rmidi; 479 480 spinlock_t reg_lock; 459 struct snd_card *card; 460 461 struct pci_dev *pci; 462 unsigned int device; /* device ID */ 463 int irq; 464 465 unsigned long iobase; 466 unsigned int ctrl; /* FUNCTRL0 current value */ 467 468 struct snd_pcm *pcm; /* DAC/ADC PCM */ 469 struct snd_pcm *pcm2; /* 2nd DAC */ 470 struct snd_pcm *pcm_spdif; /* SPDIF */ 471 472 int chip_version; 473 int max_channels; 474 unsigned int can_ac3_sw: 1; 475 unsigned int can_ac3_hw: 1; 476 unsigned int can_multi_ch: 1; 477 unsigned int can_96k: 1; /* samplerate above 48k */ 478 unsigned int do_soft_ac3: 1; 479 480 unsigned int spdif_playback_avail: 1; /* spdif ready? */ 481 unsigned int spdif_playback_enabled: 1; /* spdif switch enabled? */ 482 int spdif_counter; /* for software AC3 */ 483 484 unsigned int dig_status; 485 unsigned int dig_pcm_status; 486 487 struct snd_pcm_hardware *hw_info[3]; /* for playbacks */ 488 489 int opened[2]; /* open mode */ 490 struct mutex open_mutex; 491 492 unsigned int mixer_insensitive: 1; 493 struct snd_kcontrol *mixer_res_ctl[CM_SAVED_MIXERS]; 494 int mixer_res_status[CM_SAVED_MIXERS]; 495 496 struct cmipci_pcm channel[2]; /* ch0 - DAC, ch1 - ADC or 2nd DAC */ 497 498 /* external MIDI */ 499 struct snd_rawmidi *rmidi; 500 501 #ifdef SUPPORT_JOYSTICK 502 struct gameport *gameport; 503 #endif 504 505 spinlock_t reg_lock; 481 506 482 507 #ifdef CONFIG_PM 483 484 508 unsigned int saved_regs[0x20]; 509 unsigned char saved_mixers[0x20]; 485 510 #endif 486 511 }; … … 490 515 static inline void snd_cmipci_write(struct cmipci *cm, unsigned int cmd, unsigned int data) 491 516 { 492 517 outl(data, cm->iobase + cmd); 493 518 } 494 519 495 520 static inline unsigned int snd_cmipci_read(struct cmipci *cm, unsigned int cmd) 496 521 { 497 522 return inl(cm->iobase + cmd); 498 523 } 499 524 … … 501 526 static inline void snd_cmipci_write_w(struct cmipci *cm, unsigned int cmd, unsigned short data) 502 527 { 503 528 outw(data, cm->iobase + cmd); 504 529 } 505 530 506 531 static inline unsigned short snd_cmipci_read_w(struct cmipci *cm, unsigned int cmd) 507 532 { 508 533 return inw(cm->iobase + cmd); 509 534 } 510 535 … … 512 537 static inline void snd_cmipci_write_b(struct cmipci *cm, unsigned int cmd, unsigned char data) 513 538 { 514 539 outb(data, cm->iobase + cmd); 515 540 } 516 541 517 542 static inline unsigned char snd_cmipci_read_b(struct cmipci *cm, unsigned int cmd) 518 543 { 519 544 return inb(cm->iobase + cmd); 520 545 } 521 546 … … 566 591 } 567 592 593 568 594 /* 569 595 * PCM interface … … 578 604 static unsigned int snd_cmipci_rate_freq(unsigned int rate) 579 605 { 580 unsigned int i; 581 for (i = 0; i < ARRAY_SIZE(rates); i++) { 582 if (rates[i] == rate) 583 return i; 584 } 585 snd_BUG(); 586 return 0; 606 unsigned int i; 607 608 for (i = 0; i < ARRAY_SIZE(rates); i++) { 609 if (rates[i] == rate) 610 return i; 611 } 612 snd_BUG(); 613 return 0; 587 614 } 588 615 … … 595 622 static int snd_cmipci_pll_rmn(unsigned int rate, unsigned int adcmult, int *r, int *m, int *n) 596 623 { 597 598 599 600 601 602 603 604 605 606 607 608 609 610 611 612 613 614 615 616 617 618 619 620 621 622 623 624 625 626 624 unsigned int delta, tolerance; 625 int xm, xn, xr; 626 627 for (*r = 0; rate < CM_MAXIMUM_RATE/adcmult; *r += (1<<5)) 628 rate <<= 1; 629 *n = -1; 630 if (*r > 0xff) 631 goto out; 632 tolerance = rate*CM_TOLERANCE_RATE; 633 634 for (xn = (1+2); xn < (0x1f+2); xn++) { 635 for (xm = (1+2); xm < (0xff+2); xm++) { 636 xr = ((CM_REFFREQ_XIN/adcmult) * xm) / xn; 637 638 if (xr < rate) 639 delta = rate - xr; 640 else 641 delta = xr - rate; 642 643 /* 644 * If we found one, remember this, 645 * and try to find a closer one 646 */ 647 if (delta < tolerance) { 648 tolerance = delta; 649 *m = xm - 2; 650 *n = xn - 2; 651 } 652 } 653 } 627 654 out: 628 655 return (*n > -1); 629 656 } 630 657 … … 637 664 static void snd_cmipci_set_pll(struct cmipci *cm, unsigned int rate, unsigned int slot) 638 665 { 639 640 641 642 643 644 645 646 647 648 649 650 651 666 unsigned int reg = CM_REG_PLL + slot; 667 /* 668 * Guess that this programs at reg. 0x04 the pos 15:13/12:10 669 * for DSFC/ASFC (000 upto 111). 670 */ 671 672 /* FIXME: Init (Do we've to set an other register first before programming?) */ 673 674 /* FIXME: Is this correct? Or shouldn't the m/n/r values be used for that? */ 675 snd_cmipci_write_b(cm, reg, rate>>8); 676 snd_cmipci_write_b(cm, reg, rate&0xff); 677 678 /* FIXME: Setup (Do we've to set an other register first to enable this?) */ 652 679 } 653 680 #endif /* USE_VAR48KRATE */ 654 681 655 682 static int snd_cmipci_hw_params(struct snd_pcm_substream *substream, 656 657 { 658 683 struct snd_pcm_hw_params *hw_params) 684 { 685 return snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params)); 659 686 } 660 687 661 688 static int snd_cmipci_playback2_hw_params(struct snd_pcm_substream *substream, 662 struct snd_pcm_hw_params *hw_params) 663 { 664 struct cmipci *cm = snd_pcm_substream_chip(substream); 665 if (params_channels(hw_params) > 2) { 666 down(&cm->open_mutex); 667 #if 0 // vladest 668 if (cm->opened[CM_CH_PLAY]) { 669 up(&cm->open_mutex); 670 return -EBUSY; 671 } 672 #endif 673 /* reserve the channel A */ 674 cm->opened[CM_CH_PLAY] = CM_OPEN_PLAYBACK_MULTI; 675 up(&cm->open_mutex); 676 } 677 return snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params)); 689 struct snd_pcm_hw_params *hw_params) 690 { 691 struct cmipci *cm = snd_pcm_substream_chip(substream); 692 if (params_channels(hw_params) > 2) { 693 mutex_lock(&cm->open_mutex); 694 if (cm->opened[CM_CH_PLAY]) { 695 mutex_unlock(&cm->open_mutex); 696 return -EBUSY; 697 } 698 /* reserve the channel A */ 699 cm->opened[CM_CH_PLAY] = CM_OPEN_PLAYBACK_MULTI; 700 mutex_unlock(&cm->open_mutex); 701 } 702 return snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params)); 678 703 } 679 704 680 705 static void snd_cmipci_ch_reset(struct cmipci *cm, int ch) 681 706 { 682 683 684 685 707 int reset = CM_RST_CH0 << (cm->channel[ch].ch); 708 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl | reset); 709 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl & ~reset); 710 udelay(10); 686 711 } 687 712 688 713 static int snd_cmipci_hw_free(struct snd_pcm_substream *substream) 689 714 { 690 691 } 692 693 694 /* 695 */ 696 697 static unsigned int hw_channels[] = {1, 2, 4, 5,6, 8};715 return snd_pcm_lib_free_pages(substream); 716 } 717 718 719 /* 720 */ 721 722 static unsigned int hw_channels[] = {1, 2, 4, 6, 8}; 698 723 static struct snd_pcm_hw_constraint_list hw_constraints_channels_4 = { 699 700 701 724 .count = 3, 725 .list = hw_channels, 726 .mask = 0, 702 727 }; 703 728 static struct snd_pcm_hw_constraint_list hw_constraints_channels_6 = { 729 .count = 4, 730 .list = hw_channels, 731 .mask = 0, 732 }; 733 static struct snd_pcm_hw_constraint_list hw_constraints_channels_8 = { 704 734 .count = 5, 705 735 .list = hw_channels, 706 736 .mask = 0, 707 737 }; 708 static struct snd_pcm_hw_constraint_list hw_constraints_channels_8 = {709 .count = 6,710 .list = hw_channels,711 .mask = 0,712 };713 738 714 739 static int set_dac_channels(struct cmipci *cm, struct cmipci_pcm *rec, int channels) 715 740 { 716 if (channels > 2) { 717 if (! cm->can_multi_ch) 718 return -EINVAL; 719 if (rec->fmt != 0x03) /* stereo 16bit only */ 720 return -EINVAL; 721 722 spin_lock_irq(&cm->reg_lock); 723 snd_cmipci_set_bit(cm, CM_REG_LEGACY_CTRL, CM_NXCHG); 724 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_XCHGDAC); 725 if (channels > 4) { 726 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_CHB3D); 727 snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_CHB3D5C); 728 } else { 729 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_CHB3D5C); 730 snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_CHB3D); 731 } 732 if (channels >= 6) { 733 snd_cmipci_set_bit(cm, CM_REG_LEGACY_CTRL, CM_CHB3D6C); 734 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_ENCENTER); 735 } else { 736 snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_CHB3D6C); 737 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_ENCENTER); 738 } 739 if (cm->chip_version == 68) { 740 if (channels == 8) { 741 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL_8768, CM_CHB3D8C); 742 } else { 743 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL_8768, CM_CHB3D8C); 744 } 745 } 746 spin_unlock_irq(&cm->reg_lock); 747 748 } else { 749 if (cm->can_multi_ch) { 750 spin_lock_irq(&cm->reg_lock); 751 snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_NXCHG); 752 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_CHB3D); 753 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_CHB3D5C); 754 snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_CHB3D6C); 755 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_ENCENTER); 756 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_XCHGDAC); 757 spin_unlock_irq(&cm->reg_lock); 758 } 759 } 760 return 0; 741 if (channels > 2) { 742 if (!cm->can_multi_ch || !rec->ch) 743 return -EINVAL; 744 if (rec->fmt != 0x03) /* stereo 16bit only */ 745 return -EINVAL; 746 } 747 748 if (cm->can_multi_ch) { 749 spin_lock_irq(&cm->reg_lock); 750 if (channels > 2) { 751 snd_cmipci_set_bit(cm, CM_REG_LEGACY_CTRL, CM_NXCHG); 752 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_XCHGDAC); 753 } else { 754 snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_NXCHG); 755 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_XCHGDAC); 756 } 757 if (channels == 8) 758 snd_cmipci_set_bit(cm, CM_REG_EXT_MISC, CM_CHB3D8C); 759 else 760 snd_cmipci_clear_bit(cm, CM_REG_EXT_MISC, CM_CHB3D8C); 761 if (channels == 6) { 762 snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_CHB3D5C); 763 snd_cmipci_set_bit(cm, CM_REG_LEGACY_CTRL, CM_CHB3D6C); 764 } else { 765 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_CHB3D5C); 766 snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_CHB3D6C); 767 } 768 if (channels == 4) 769 snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_CHB3D); 770 else 771 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_CHB3D); 772 spin_unlock_irq(&cm->reg_lock); 773 } 774 return 0; 761 775 } 762 776 … … 767 781 */ 768 782 static int snd_cmipci_pcm_prepare(struct cmipci *cm, struct cmipci_pcm *rec, 769 struct snd_pcm_substream *substream) 770 { 771 unsigned int reg, freq, val; 772 struct snd_pcm_runtime *runtime = substream->runtime; 773 774 rec->fmt = 0; 775 rec->shift = 0; 776 if (snd_pcm_format_width(runtime->format) >= 16) { 777 rec->fmt |= 0x02; 778 if (snd_pcm_format_width(runtime->format) > 16) 779 rec->shift++; /* 24/32bit */ 780 } 781 if (runtime->channels > 1) 782 rec->fmt |= 0x01; 783 if (rec->is_dac && set_dac_channels(cm, rec, runtime->channels) < 0) { 784 snd_printd("cannot set dac channels\n"); 785 return -EINVAL; 786 } 787 788 rec->offset = runtime->dma_addr; 789 /* buffer and period sizes in frame */ 790 rec->dma_size = runtime->buffer_size << rec->shift; 791 rec->period_size = runtime->period_size << rec->shift; 792 if (runtime->channels > 2) { 793 /* multi-channels */ 794 rec->dma_size = (rec->dma_size * runtime->channels) / 2; 795 rec->period_size = (rec->period_size * runtime->channels) / 2; 796 } 797 798 spin_lock_irq(&cm->reg_lock); 799 800 /* set buffer address */ 801 reg = rec->ch ? CM_REG_CH1_FRAME1 : CM_REG_CH0_FRAME1; 802 snd_cmipci_write(cm, reg, rec->offset); 803 /* program sample counts */ 804 reg = rec->ch ? CM_REG_CH1_FRAME2 : CM_REG_CH0_FRAME2; 805 snd_cmipci_write_w(cm, reg, rec->dma_size - 1); 806 snd_cmipci_write_w(cm, reg + 2, rec->period_size - 1); 807 808 /* set adc/dac flag */ 809 val = rec->ch ? CM_CHADC1 : CM_CHADC0; 810 if (rec->is_dac) 811 cm->ctrl &= ~val; 812 else 813 cm->ctrl |= val; 814 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl); 815 //snd_printd("cmipci: functrl0 = %08x\n", cm->ctrl); 816 817 /* set sample rate */ 818 freq = snd_cmipci_rate_freq(runtime->rate); 819 val = snd_cmipci_read(cm, CM_REG_FUNCTRL1); 820 if (rec->ch) { 821 val &= ~CM_ASFC_MASK; 822 val |= (freq << CM_ASFC_SHIFT) & CM_ASFC_MASK; 823 } else { 824 val &= ~CM_DSFC_MASK; 825 val |= (freq << CM_DSFC_SHIFT) & CM_DSFC_MASK; 826 } 827 snd_cmipci_write(cm, CM_REG_FUNCTRL1, val); 828 //snd_printd("cmipci: functrl1 = %08x\n", val); 829 830 /* set format */ 831 val = snd_cmipci_read(cm, CM_REG_CHFORMAT); 832 if (rec->ch) { 833 val &= ~CM_CH1FMT_MASK; 834 val |= rec->fmt << CM_CH1FMT_SHIFT; 835 } else { 836 val &= ~CM_CH0FMT_MASK; 837 val |= rec->fmt << CM_CH0FMT_SHIFT; 838 } 839 snd_cmipci_write(cm, CM_REG_CHFORMAT, val); 840 //snd_printd("cmipci: chformat = %08x\n", val); 841 842 rec->running = 0; 843 spin_unlock_irq(&cm->reg_lock); 844 845 return 0; 783 struct snd_pcm_substream *substream) 784 { 785 unsigned int reg, freq, freq_ext, val; 786 unsigned int period_size; 787 struct snd_pcm_runtime *runtime = substream->runtime; 788 789 rec->fmt = 0; 790 rec->shift = 0; 791 if (snd_pcm_format_width(runtime->format) >= 16) { 792 rec->fmt |= 0x02; 793 if (snd_pcm_format_width(runtime->format) > 16) 794 rec->shift++; /* 24/32bit */ 795 } 796 if (runtime->channels > 1) 797 rec->fmt |= 0x01; 798 if (rec->is_dac && set_dac_channels(cm, rec, runtime->channels) < 0) { 799 snd_printd("cannot set dac channels\n"); 800 return -EINVAL; 801 } 802 803 rec->offset = runtime->dma_addr; 804 /* buffer and period sizes in frame */ 805 rec->dma_size = runtime->buffer_size << rec->shift; 806 period_size = runtime->period_size << rec->shift; 807 if (runtime->channels > 2) { 808 /* multi-channels */ 809 rec->dma_size = (rec->dma_size * runtime->channels) / 2; 810 period_size = (period_size * runtime->channels) / 2; 811 } 812 813 spin_lock_irq(&cm->reg_lock); 814 815 /* set buffer address */ 816 reg = rec->ch ? CM_REG_CH1_FRAME1 : CM_REG_CH0_FRAME1; 817 snd_cmipci_write(cm, reg, rec->offset); 818 /* program sample counts */ 819 reg = rec->ch ? CM_REG_CH1_FRAME2 : CM_REG_CH0_FRAME2; 820 snd_cmipci_write_w(cm, reg, rec->dma_size - 1); 821 snd_cmipci_write_w(cm, reg + 2, period_size - 1); 822 823 /* set adc/dac flag */ 824 val = rec->ch ? CM_CHADC1 : CM_CHADC0; 825 if (rec->is_dac) 826 cm->ctrl &= ~val; 827 else 828 cm->ctrl |= val; 829 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl); 830 //snd_printd("cmipci: functrl0 = %08x\n", cm->ctrl); 831 832 /* set sample rate */ 833 freq = 0; 834 freq_ext = 0; 835 if (runtime->rate > 48000) 836 switch (runtime->rate) { 837 case 88200: freq_ext = CM_CH0_SRATE_88K; break; 838 case 96000: freq_ext = CM_CH0_SRATE_96K; break; 839 case 128000: freq_ext = CM_CH0_SRATE_128K; break; 840 default: snd_BUG(); break; 841 } 842 else 843 freq = snd_cmipci_rate_freq(runtime->rate); 844 val = snd_cmipci_read(cm, CM_REG_FUNCTRL1); 845 if (rec->ch) { 846 val &= ~CM_DSFC_MASK; 847 val |= (freq << CM_DSFC_SHIFT) & CM_DSFC_MASK; 848 } else { 849 val &= ~CM_ASFC_MASK; 850 val |= (freq << CM_ASFC_SHIFT) & CM_ASFC_MASK; 851 } 852 snd_cmipci_write(cm, CM_REG_FUNCTRL1, val); 853 //snd_printd("cmipci: functrl1 = %08x\n", val); 854 855 /* set format */ 856 val = snd_cmipci_read(cm, CM_REG_CHFORMAT); 857 if (rec->ch) { 858 val &= ~CM_CH1FMT_MASK; 859 val |= rec->fmt << CM_CH1FMT_SHIFT; 860 } else { 861 val &= ~CM_CH0FMT_MASK; 862 val |= rec->fmt << CM_CH0FMT_SHIFT; 863 } 864 if (cm->can_96k) { 865 val &= ~(CM_CH0_SRATE_MASK << (rec->ch * 2)); 866 val |= freq_ext << (rec->ch * 2); 867 } 868 snd_cmipci_write(cm, CM_REG_CHFORMAT, val); 869 //snd_printd("cmipci: chformat = %08x\n", val); 870 871 if (!rec->is_dac && cm->chip_version) { 872 if (runtime->rate > 44100) 873 snd_cmipci_set_bit(cm, CM_REG_EXT_MISC, CM_ADC48K44K); 874 else 875 snd_cmipci_clear_bit(cm, CM_REG_EXT_MISC, CM_ADC48K44K); 876 } 877 878 rec->running = 0; 879 spin_unlock_irq(&cm->reg_lock); 880 881 return 0; 846 882 } 847 883 … … 850 886 */ 851 887 static int snd_cmipci_pcm_trigger(struct cmipci *cm, struct cmipci_pcm *rec, 852 struct snd_pcm_substream *substream, int cmd) 853 { 854 unsigned int inthld, chen, reset, pause; 855 int result = 0; 856 857 inthld = CM_CH0_INT_EN << rec->ch; 858 chen = CM_CHEN0 << rec->ch; 859 reset = CM_RST_CH0 << rec->ch; 860 pause = CM_PAUSE0 << rec->ch; 861 862 spin_lock(&cm->reg_lock); 863 switch (cmd) { 864 case SNDRV_PCM_TRIGGER_START: 865 rec->running = 1; 866 /* set interrupt */ 867 snd_cmipci_set_bit(cm, CM_REG_INT_HLDCLR, inthld); 868 cm->ctrl |= chen; 869 /* enable channel */ 870 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl); 871 //snd_printd("cmipci: functrl0 = %08x\n", cm->ctrl); 872 break; 873 case SNDRV_PCM_TRIGGER_STOP: 874 rec->running = 0; 875 /* disable interrupt */ 876 snd_cmipci_clear_bit(cm, CM_REG_INT_HLDCLR, inthld); 877 /* reset */ 878 cm->ctrl &= ~chen; 879 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl | reset); 880 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl & ~reset); 881 break; 882 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 883 case SNDRV_PCM_TRIGGER_SUSPEND: 884 cm->ctrl |= pause; 885 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl); 886 break; 887 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 888 case SNDRV_PCM_TRIGGER_RESUME: 889 cm->ctrl &= ~pause; 890 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl); 891 break; 892 default: 893 result = -EINVAL; 894 break; 895 } 896 spin_unlock(&cm->reg_lock); 897 return result; 888 int cmd) 889 { 890 unsigned int inthld, chen, reset, pause; 891 int result = 0; 892 893 inthld = CM_CH0_INT_EN << rec->ch; 894 chen = CM_CHEN0 << rec->ch; 895 reset = CM_RST_CH0 << rec->ch; 896 pause = CM_PAUSE0 << rec->ch; 897 898 spin_lock(&cm->reg_lock); 899 switch (cmd) { 900 case SNDRV_PCM_TRIGGER_START: 901 rec->running = 1; 902 /* set interrupt */ 903 snd_cmipci_set_bit(cm, CM_REG_INT_HLDCLR, inthld); 904 cm->ctrl |= chen; 905 /* enable channel */ 906 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl); 907 //snd_printd("cmipci: functrl0 = %08x\n", cm->ctrl); 908 break; 909 case SNDRV_PCM_TRIGGER_STOP: 910 rec->running = 0; 911 /* disable interrupt */ 912 snd_cmipci_clear_bit(cm, CM_REG_INT_HLDCLR, inthld); 913 /* reset */ 914 cm->ctrl &= ~chen; 915 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl | reset); 916 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl & ~reset); 917 rec->needs_silencing = rec->is_dac; 918 break; 919 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 920 case SNDRV_PCM_TRIGGER_SUSPEND: 921 cm->ctrl |= pause; 922 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl); 923 break; 924 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 925 case SNDRV_PCM_TRIGGER_RESUME: 926 cm->ctrl &= ~pause; 927 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl); 928 break; 929 default: 930 result = -EINVAL; 931 break; 932 } 933 spin_unlock(&cm->reg_lock); 934 return result; 898 935 } 899 936 … … 902 939 */ 903 940 static snd_pcm_uframes_t snd_cmipci_pcm_pointer(struct cmipci *cm, struct cmipci_pcm *rec, 904 905 { 906 907 908 909 941 struct snd_pcm_substream *substream) 942 { 943 size_t ptr; 944 unsigned int reg; 945 if (!rec->running) 946 return 0; 910 947 #if 1 // this seems better.. 911 912 913 948 reg = rec->ch ? CM_REG_CH1_FRAME2 : CM_REG_CH0_FRAME2; 949 ptr = rec->dma_size - (snd_cmipci_read_w(cm, reg) + 1); 950 ptr >>= rec->shift; 914 951 #else 915 916 917 952 reg = rec->ch ? CM_REG_CH1_FRAME1 : CM_REG_CH0_FRAME1; 953 ptr = snd_cmipci_read(cm, reg) - rec->offset; 954 ptr = bytes_to_frames(substream->runtime, ptr); 918 955 #endif 919 920 921 956 if (substream->runtime->channels > 2) 957 ptr = (ptr * 2) / substream->runtime->channels; 958 return ptr; 922 959 } 923 960 … … 925 962 * playback 926 963 */ 964 927 965 static int snd_cmipci_playback_trigger(struct snd_pcm_substream *substream, 928 929 { 930 931 return snd_cmipci_pcm_trigger(cm, &cm->channel[CM_CH_PLAY], substream, cmd);966 int cmd) 967 { 968 struct cmipci *cm = snd_pcm_substream_chip(substream); 969 return snd_cmipci_pcm_trigger(cm, &cm->channel[CM_CH_PLAY], cmd); 932 970 } 933 971 934 972 static snd_pcm_uframes_t snd_cmipci_playback_pointer(struct snd_pcm_substream *substream) 935 973 { 936 937 974 struct cmipci *cm = snd_pcm_substream_chip(substream); 975 return snd_cmipci_pcm_pointer(cm, &cm->channel[CM_CH_PLAY], substream); 938 976 } 939 977 … … 945 983 946 984 static int snd_cmipci_capture_trigger(struct snd_pcm_substream *substream, 947 948 { 949 950 return snd_cmipci_pcm_trigger(cm, &cm->channel[CM_CH_CAPT], substream, cmd);985 int cmd) 986 { 987 struct cmipci *cm = snd_pcm_substream_chip(substream); 988 return snd_cmipci_pcm_trigger(cm, &cm->channel[CM_CH_CAPT], cmd); 951 989 } 952 990 953 991 static snd_pcm_uframes_t snd_cmipci_capture_pointer(struct snd_pcm_substream *substream) 954 992 { 955 956 993 struct cmipci *cm = snd_pcm_substream_chip(substream); 994 return snd_cmipci_pcm_pointer(cm, &cm->channel[CM_CH_CAPT], substream); 957 995 } 958 996 … … 963 1001 964 1002 static int snd_cmipci_spdif_default_info(struct snd_kcontrol *kcontrol, 965 966 { 967 968 969 1003 struct snd_ctl_elem_info *uinfo) 1004 { 1005 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958; 1006 uinfo->count = 1; 1007 return 0; 970 1008 } 971 1009 972 1010 static int snd_cmipci_spdif_default_get(struct snd_kcontrol *kcontrol, 973 974 { 975 976 977 978 979 980 981 982 1011 struct snd_ctl_elem_value *ucontrol) 1012 { 1013 struct cmipci *chip = snd_kcontrol_chip(kcontrol); 1014 int i; 1015 1016 spin_lock_irq(&chip->reg_lock); 1017 for (i = 0; i < 4; i++) 1018 ucontrol->value.iec958.status[i] = (chip->dig_status >> (i * 8)) & 0xff; 1019 spin_unlock_irq(&chip->reg_lock); 1020 return 0; 983 1021 } 984 1022 985 1023 static int snd_cmipci_spdif_default_put(struct snd_kcontrol *kcontrol, 986 987 { 988 989 990 991 992 993 994 995 996 997 998 999 1024 struct snd_ctl_elem_value *ucontrol) 1025 { 1026 struct cmipci *chip = snd_kcontrol_chip(kcontrol); 1027 int i, change; 1028 unsigned int val; 1029 1030 val = 0; 1031 spin_lock_irq(&chip->reg_lock); 1032 for (i = 0; i < 4; i++) 1033 val |= (unsigned int)ucontrol->value.iec958.status[i] << (i * 8); 1034 change = val != chip->dig_status; 1035 chip->dig_status = val; 1036 spin_unlock_irq(&chip->reg_lock); 1037 return change; 1000 1038 } 1001 1039 1002 1040 static struct snd_kcontrol_new snd_cmipci_spdif_default __devinitdata = 1003 1041 { 1004 SNDRV_CTL_ELEM_IFACE_PCM,0,0,1005 SNDRV_CTL_NAME_IEC958("",PLAYBACK,DEFAULT),0,0,0,1006 1007 1008 snd_cmipci_spdif_default_put,0 1042 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 1043 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,DEFAULT), 1044 .info = snd_cmipci_spdif_default_info, 1045 .get = snd_cmipci_spdif_default_get, 1046 .put = snd_cmipci_spdif_default_put 1009 1047 }; 1010 1048 1011 1049 static int snd_cmipci_spdif_mask_info(struct snd_kcontrol *kcontrol, 1012 1013 { 1014 1015 1016 1050 struct snd_ctl_elem_info *uinfo) 1051 { 1052 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958; 1053 uinfo->count = 1; 1054 return 0; 1017 1055 } 1018 1056 1019 1057 static int snd_cmipci_spdif_mask_get(struct snd_kcontrol *kcontrol, 1020 1021 { 1022 1023 1024 1025 1026 1058 struct snd_ctl_elem_value *ucontrol) 1059 { 1060 ucontrol->value.iec958.status[0] = 0xff; 1061 ucontrol->value.iec958.status[1] = 0xff; 1062 ucontrol->value.iec958.status[2] = 0xff; 1063 ucontrol->value.iec958.status[3] = 0xff; 1064 return 0; 1027 1065 } 1028 1066 1029 1067 static struct snd_kcontrol_new snd_cmipci_spdif_mask __devinitdata = 1030 1068 { 1031 SNDRV_CTL_ELEM_IFACE_MIXER,0,0,1032 SNDRV_CTL_NAME_IEC958("",PLAYBACK,CON_MASK),0,1033 SNDRV_CTL_ELEM_ACCESS_READ,0,1034 1035 snd_cmipci_spdif_mask_get,0,0 1069 .access = SNDRV_CTL_ELEM_ACCESS_READ, 1070 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 1071 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,CON_MASK), 1072 .info = snd_cmipci_spdif_mask_info, 1073 .get = snd_cmipci_spdif_mask_get, 1036 1074 }; 1037 1075 1038 1076 static int snd_cmipci_spdif_stream_info(struct snd_kcontrol *kcontrol, 1039 1040 { 1041 1042 1043 1077 struct snd_ctl_elem_info *uinfo) 1078 { 1079 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958; 1080 uinfo->count = 1; 1081 return 0; 1044 1082 } 1045 1083 1046 1084 static int snd_cmipci_spdif_stream_get(struct snd_kcontrol *kcontrol, 1047 1048 { 1049 1050 1051 1052 1053 1054 1055 1056 1085 struct snd_ctl_elem_value *ucontrol) 1086 { 1087 struct cmipci *chip = snd_kcontrol_chip(kcontrol); 1088 int i; 1089 1090 spin_lock_irq(&chip->reg_lock); 1091 for (i = 0; i < 4; i++) 1092 ucontrol->value.iec958.status[i] = (chip->dig_pcm_status >> (i * 8)) & 0xff; 1093 spin_unlock_irq(&chip->reg_lock); 1094 return 0; 1057 1095 } 1058 1096 1059 1097 static int snd_cmipci_spdif_stream_put(struct snd_kcontrol *kcontrol, 1060 1061 { 1062 1063 1064 1065 1066 1067 1068 1069 1070 1071 1072 1073 1098 struct snd_ctl_elem_value *ucontrol) 1099 { 1100 struct cmipci *chip = snd_kcontrol_chip(kcontrol); 1101 int i, change; 1102 unsigned int val; 1103 1104 val = 0; 1105 spin_lock_irq(&chip->reg_lock); 1106 for (i = 0; i < 4; i++) 1107 val |= (unsigned int)ucontrol->value.iec958.status[i] << (i * 8); 1108 change = val != chip->dig_pcm_status; 1109 chip->dig_pcm_status = val; 1110 spin_unlock_irq(&chip->reg_lock); 1111 return change; 1074 1112 } 1075 1113 1076 1114 static struct snd_kcontrol_new snd_cmipci_spdif_stream __devinitdata = 1077 1115 { 1078 SNDRV_CTL_ELEM_IFACE_PCM,0,0,1079 SNDRV_CTL_NAME_IEC958("",PLAYBACK,PCM_STREAM),0,1080 SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_INACTIVE,0,1081 1082 1083 snd_cmipci_spdif_stream_put,0 1116 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_INACTIVE, 1117 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 1118 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,PCM_STREAM), 1119 .info = snd_cmipci_spdif_stream_info, 1120 .get = snd_cmipci_spdif_stream_get, 1121 .put = snd_cmipci_spdif_stream_put 1084 1122 }; 1085 1123 … … 1090 1128 static int save_mixer_state(struct cmipci *cm) 1091 1129 { 1092 if (! cm->mixer_insensitive) { 1093 struct snd_ctl_elem_value *val; 1094 unsigned int i; 1095 val = kmalloc(sizeof(*val), GFP_ATOMIC); 1096 if (!val) 1097 return -ENOMEM; 1098 for (i = 0; i < CM_SAVED_MIXERS; i++) { 1099 struct snd_kcontrol *ctl = cm->mixer_res_ctl[i]; 1100 if (ctl) { 1101 int event; 1102 memset(val, 0, sizeof(*val)); 1103 ctl->get(ctl, val); 1104 cm->mixer_res_status[i] = val->value.integer.value[0]; 1105 val->value.integer.value[0] = cm_saved_mixer[i].toggle_on; 1106 event = SNDRV_CTL_EVENT_MASK_INFO; 1107 if (cm->mixer_res_status[i] != val->value.integer.value[0]) { 1108 ctl->put(ctl, val); /* toggle */ 1109 event |= SNDRV_CTL_EVENT_MASK_VALUE; 1110 } 1111 ctl->vd[0].access |= SNDRV_CTL_ELEM_ACCESS_INACTIVE; 1112 snd_ctl_notify(cm->card, event, &ctl->id); 1113 } 1114 } 1115 kfree(val); 1116 cm->mixer_insensitive = 1; 1117 } 1118 return 0; 1130 if (! cm->mixer_insensitive) { 1131 struct snd_ctl_elem_value *val; 1132 unsigned int i; 1133 1134 val = kmalloc(sizeof(*val), GFP_ATOMIC); 1135 if (!val) 1136 return -ENOMEM; 1137 for (i = 0; i < CM_SAVED_MIXERS; i++) { 1138 struct snd_kcontrol *ctl = cm->mixer_res_ctl[i]; 1139 if (ctl) { 1140 int event; 1141 memset(val, 0, sizeof(*val)); 1142 ctl->get(ctl, val); 1143 cm->mixer_res_status[i] = val->value.integer.value[0]; 1144 val->value.integer.value[0] = cm_saved_mixer[i].toggle_on; 1145 event = SNDRV_CTL_EVENT_MASK_INFO; 1146 if (cm->mixer_res_status[i] != val->value.integer.value[0]) { 1147 ctl->put(ctl, val); /* toggle */ 1148 event |= SNDRV_CTL_EVENT_MASK_VALUE; 1149 } 1150 ctl->vd[0].access |= SNDRV_CTL_ELEM_ACCESS_INACTIVE; 1151 snd_ctl_notify(cm->card, event, &ctl->id); 1152 } 1153 } 1154 kfree(val); 1155 cm->mixer_insensitive = 1; 1156 } 1157 return 0; 1119 1158 } 1120 1159 … … 1123 1162 static void restore_mixer_state(struct cmipci *cm) 1124 1163 { 1125 1126 1127 1128 1129 1130 1131 1132 1133 1134 1135 1136 1137 1138 1139 1140 1141 1142 1143 1144 1145 1146 1147 1148 1149 1150 1151 1152 1164 if (cm->mixer_insensitive) { 1165 struct snd_ctl_elem_value *val; 1166 unsigned int i; 1167 1168 val = kmalloc(sizeof(*val), GFP_KERNEL); 1169 if (!val) 1170 return; 1171 cm->mixer_insensitive = 0; /* at first clear this; 1172 otherwise the changes will be ignored */ 1173 for (i = 0; i < CM_SAVED_MIXERS; i++) { 1174 struct snd_kcontrol *ctl = cm->mixer_res_ctl[i]; 1175 if (ctl) { 1176 int event; 1177 1178 memset(val, 0, sizeof(*val)); 1179 ctl->vd[0].access &= ~SNDRV_CTL_ELEM_ACCESS_INACTIVE; 1180 ctl->get(ctl, val); 1181 event = SNDRV_CTL_EVENT_MASK_INFO; 1182 if (val->value.integer.value[0] != cm->mixer_res_status[i]) { 1183 val->value.integer.value[0] = cm->mixer_res_status[i]; 1184 ctl->put(ctl, val); 1185 event |= SNDRV_CTL_EVENT_MASK_VALUE; 1186 } 1187 snd_ctl_notify(cm->card, event, &ctl->id); 1188 } 1189 } 1190 kfree(val); 1191 } 1153 1192 } 1154 1193 … … 1156 1195 static void setup_ac3(struct cmipci *cm, struct snd_pcm_substream *subs, int do_ac3, int rate) 1157 1196 { 1158 1159 1160 1161 1162 1163 1164 1165 1166 1167 1168 1169 1170 1171 1172 1173 1174 1175 1176 1177 1178 1179 1180 1181 1182 1183 1184 1185 1186 1187 1188 1189 1190 1191 1192 1193 1194 1195 1196 1197 1198 1199 1200 1197 if (do_ac3) { 1198 /* AC3EN for 037 */ 1199 snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_AC3EN1); 1200 /* AC3EN for 039 */ 1201 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_AC3EN2); 1202 1203 if (cm->can_ac3_hw) { 1204 /* SPD24SEL for 037, 0x02 */ 1205 /* SPD24SEL for 039, 0x20, but cannot be set */ 1206 snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_SPD24SEL); 1207 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL); 1208 } else { /* can_ac3_sw */ 1209 /* SPD32SEL for 037 & 039, 0x20 */ 1210 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL); 1211 /* set 176K sample rate to fix 033 HW bug */ 1212 if (cm->chip_version == 33) { 1213 if (rate >= 48000) { 1214 snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_PLAYBACK_SRATE_176K); 1215 } else { 1216 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_PLAYBACK_SRATE_176K); 1217 } 1218 } 1219 } 1220 1221 } else { 1222 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_AC3EN1); 1223 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_AC3EN2); 1224 1225 if (cm->can_ac3_hw) { 1226 /* chip model >= 37 */ 1227 if (snd_pcm_format_width(subs->runtime->format) > 16) { 1228 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL); 1229 snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_SPD24SEL); 1230 } else { 1231 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL); 1232 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_SPD24SEL); 1233 } 1234 } else { 1235 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL); 1236 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_SPD24SEL); 1237 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_PLAYBACK_SRATE_176K); 1238 } 1239 } 1201 1240 } 1202 1241 1203 1242 static int setup_spdif_playback(struct cmipci *cm, struct snd_pcm_substream *subs, int up, int do_ac3) 1204 1243 { 1205 int rate, err; 1206 1207 rate = subs->runtime->rate; 1208 1209 if (up && do_ac3) 1210 if ((err = save_mixer_state(cm)) < 0) 1211 return err; 1212 1213 spin_lock_irq(&cm->reg_lock); 1214 cm->spdif_playback_avail = up; 1215 if (up) { 1216 /* they are controlled via "IEC958 Output Switch" */ 1217 /* snd_cmipci_set_bit(cm, CM_REG_LEGACY_CTRL, CM_ENSPDOUT); */ 1218 /* snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_SPDO2DAC); */ 1219 if (cm->spdif_playback_enabled) 1220 snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_PLAYBACK_SPDF); 1221 setup_ac3(cm, subs, do_ac3, rate); 1222 1223 if (rate == 48000) 1224 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_SPDIF48K | CM_SPDF_AC97); 1225 else 1226 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_SPDIF48K | CM_SPDF_AC97); 1227 1228 } else { 1229 /* they are controlled via "IEC958 Output Switch" */ 1230 /* snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_ENSPDOUT); */ 1231 /* snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_SPDO2DAC); */ 1232 snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_PLAYBACK_SPDF); 1233 setup_ac3(cm, subs, 0, 0); 1234 } 1235 spin_unlock_irq(&cm->reg_lock); 1236 return 0; 1244 int rate, err; 1245 1246 rate = subs->runtime->rate; 1247 1248 if (up && do_ac3) 1249 if ((err = save_mixer_state(cm)) < 0) 1250 return err; 1251 1252 spin_lock_irq(&cm->reg_lock); 1253 cm->spdif_playback_avail = up; 1254 if (up) { 1255 /* they are controlled via "IEC958 Output Switch" */ 1256 /* snd_cmipci_set_bit(cm, CM_REG_LEGACY_CTRL, CM_ENSPDOUT); */ 1257 /* snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_SPDO2DAC); */ 1258 if (cm->spdif_playback_enabled) 1259 snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_PLAYBACK_SPDF); 1260 setup_ac3(cm, subs, do_ac3, rate); 1261 1262 if (rate == 48000 || rate == 96000) 1263 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_SPDIF48K | CM_SPDF_AC97); 1264 else 1265 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_SPDIF48K | CM_SPDF_AC97); 1266 if (rate > 48000) 1267 snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_DBLSPDS); 1268 else 1269 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_DBLSPDS); 1270 } else { 1271 /* they are controlled via "IEC958 Output Switch" */ 1272 /* snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_ENSPDOUT); */ 1273 /* snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_SPDO2DAC); */ 1274 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_DBLSPDS); 1275 snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_PLAYBACK_SPDF); 1276 setup_ac3(cm, subs, 0, 0); 1277 } 1278 spin_unlock_irq(&cm->reg_lock); 1279 return 0; 1237 1280 } 1238 1281 … … 1245 1288 static int snd_cmipci_playback_prepare(struct snd_pcm_substream *substream) 1246 1289 { 1247 struct cmipci *cm = snd_pcm_substream_chip(substream); 1248 int rate = substream->runtime->rate; 1249 int err, do_spdif, do_ac3 = 0; 1250 do_spdif = ((rate == 44100 || rate == 48000) && 1251 substream->runtime->format == SNDRV_PCM_FORMAT_S16_LE && 1252 substream->runtime->channels == 2); 1253 if (do_spdif && cm->can_ac3_hw) 1254 do_ac3 = cm->dig_pcm_status & IEC958_AES0_NONAUDIO; 1255 if ((err = setup_spdif_playback(cm, substream, do_spdif, do_ac3)) < 0) 1256 return err; 1257 return snd_cmipci_pcm_prepare(cm, &cm->channel[CM_CH_PLAY], substream); 1290 struct cmipci *cm = snd_pcm_substream_chip(substream); 1291 int rate = substream->runtime->rate; 1292 int err, do_spdif, do_ac3 = 0; 1293 1294 do_spdif = (rate >= 44100 && rate <= 96000 && 1295 substream->runtime->format == SNDRV_PCM_FORMAT_S16_LE && 1296 substream->runtime->channels == 2); 1297 if (do_spdif && cm->can_ac3_hw) 1298 do_ac3 = cm->dig_pcm_status & IEC958_AES0_NONAUDIO; 1299 if ((err = setup_spdif_playback(cm, substream, do_spdif, do_ac3)) < 0) 1300 return err; 1301 return snd_cmipci_pcm_prepare(cm, &cm->channel[CM_CH_PLAY], substream); 1258 1302 } 1259 1303 … … 1261 1305 static int snd_cmipci_playback_spdif_prepare(struct snd_pcm_substream *substream) 1262 1306 { 1263 struct cmipci *cm = snd_pcm_substream_chip(substream); 1264 int err, do_ac3; 1265 if (cm->can_ac3_hw) 1266 do_ac3 = cm->dig_pcm_status & IEC958_AES0_NONAUDIO; 1267 else 1268 do_ac3 = 1; /* doesn't matter */ 1269 if ((err = setup_spdif_playback(cm, substream, 1, do_ac3)) < 0) 1270 return err; 1271 return snd_cmipci_pcm_prepare(cm, &cm->channel[CM_CH_PLAY], substream); 1307 struct cmipci *cm = snd_pcm_substream_chip(substream); 1308 int err, do_ac3; 1309 1310 if (cm->can_ac3_hw) 1311 do_ac3 = cm->dig_pcm_status & IEC958_AES0_NONAUDIO; 1312 else 1313 do_ac3 = 1; /* doesn't matter */ 1314 if ((err = setup_spdif_playback(cm, substream, 1, do_ac3)) < 0) 1315 return err; 1316 return snd_cmipci_pcm_prepare(cm, &cm->channel[CM_CH_PLAY], substream); 1317 } 1318 1319 /* 1320 * Apparently, the samples last played on channel A stay in some buffer, even 1321 * after the channel is reset, and get added to the data for the rear DACs when 1322 * playing a multichannel stream on channel B. This is likely to generate 1323 * wraparounds and thus distortions. 1324 * To avoid this, we play at least one zero sample after the actual stream has 1325 * stopped. 1326 */ 1327 static void snd_cmipci_silence_hack(struct cmipci *cm, struct cmipci_pcm *rec) 1328 { 1329 struct snd_pcm_runtime *runtime = rec->substream->runtime; 1330 unsigned int reg, val; 1331 1332 if (rec->needs_silencing && runtime && runtime->dma_area) { 1333 /* set up a small silence buffer */ 1334 memset(runtime->dma_area, 0, PAGE_SIZE); 1335 reg = rec->ch ? CM_REG_CH1_FRAME2 : CM_REG_CH0_FRAME2; 1336 val = ((PAGE_SIZE / 4) - 1) | (((PAGE_SIZE / 4) / 2 - 1) << 16); 1337 snd_cmipci_write(cm, reg, val); 1338 1339 /* configure for 16 bits, 2 channels, 8 kHz */ 1340 if (runtime->channels > 2) 1341 set_dac_channels(cm, rec, 2); 1342 spin_lock_irq(&cm->reg_lock); 1343 val = snd_cmipci_read(cm, CM_REG_FUNCTRL1); 1344 val &= ~(CM_ASFC_MASK << (rec->ch * 3)); 1345 val |= (4 << CM_ASFC_SHIFT) << (rec->ch * 3); 1346 snd_cmipci_write(cm, CM_REG_FUNCTRL1, val); 1347 val = snd_cmipci_read(cm, CM_REG_CHFORMAT); 1348 val &= ~(CM_CH0FMT_MASK << (rec->ch * 2)); 1349 val |= (3 << CM_CH0FMT_SHIFT) << (rec->ch * 2); 1350 if (cm->can_96k) 1351 val &= ~(CM_CH0_SRATE_MASK << (rec->ch * 2)); 1352 snd_cmipci_write(cm, CM_REG_CHFORMAT, val); 1353 1354 /* start stream (we don't need interrupts) */ 1355 cm->ctrl |= CM_CHEN0 << rec->ch; 1356 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl); 1357 spin_unlock_irq(&cm->reg_lock); 1358 1359 msleep(1); 1360 1361 /* stop and reset stream */ 1362 spin_lock_irq(&cm->reg_lock); 1363 cm->ctrl &= ~(CM_CHEN0 << rec->ch); 1364 val = CM_RST_CH0 << rec->ch; 1365 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl | val); 1366 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl & ~val); 1367 spin_unlock_irq(&cm->reg_lock); 1368 1369 rec->needs_silencing = 0; 1370 } 1272 1371 } 1273 1372 1274 1373 static int snd_cmipci_playback_hw_free(struct snd_pcm_substream *substream) 1275 1374 { 1276 struct cmipci *cm = snd_pcm_substream_chip(substream); 1277 setup_spdif_playback(cm, substream, 0, 0); 1278 restore_mixer_state(cm); 1279 return snd_cmipci_hw_free(substream); 1375 struct cmipci *cm = snd_pcm_substream_chip(substream); 1376 setup_spdif_playback(cm, substream, 0, 0); 1377 restore_mixer_state(cm); 1378 snd_cmipci_silence_hack(cm, &cm->channel[0]); 1379 return snd_cmipci_hw_free(substream); 1380 } 1381 1382 static int snd_cmipci_playback2_hw_free(struct snd_pcm_substream *substream) 1383 { 1384 struct cmipci *cm = snd_pcm_substream_chip(substream); 1385 snd_cmipci_silence_hack(cm, &cm->channel[1]); 1386 return snd_cmipci_hw_free(substream); 1280 1387 } 1281 1388 … … 1283 1390 static int snd_cmipci_capture_prepare(struct snd_pcm_substream *substream) 1284 1391 { 1285 1286 1392 struct cmipci *cm = snd_pcm_substream_chip(substream); 1393 return snd_cmipci_pcm_prepare(cm, &cm->channel[CM_CH_CAPT], substream); 1287 1394 } 1288 1395 … … 1290 1397 static int snd_cmipci_capture_spdif_prepare(struct snd_pcm_substream *substream) 1291 1398 { 1292 struct cmipci *cm = snd_pcm_substream_chip(substream); 1293 1294 spin_lock_irq(&cm->reg_lock); 1295 snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_CAPTURE_SPDF); 1296 spin_unlock_irq(&cm->reg_lock); 1297 1298 return snd_cmipci_pcm_prepare(cm, &cm->channel[CM_CH_CAPT], substream); 1399 struct cmipci *cm = snd_pcm_substream_chip(substream); 1400 1401 spin_lock_irq(&cm->reg_lock); 1402 snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_CAPTURE_SPDF); 1403 if (cm->can_96k) { 1404 if (substream->runtime->rate > 48000) 1405 snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_DBLSPDS); 1406 else 1407 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_DBLSPDS); 1408 } 1409 if (snd_pcm_format_width(substream->runtime->format) > 16) 1410 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL); 1411 else 1412 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL); 1413 1414 spin_unlock_irq(&cm->reg_lock); 1415 1416 return snd_cmipci_pcm_prepare(cm, &cm->channel[CM_CH_CAPT], substream); 1299 1417 } 1300 1418 1301 1419 static int snd_cmipci_capture_spdif_hw_free(struct snd_pcm_substream *subs) 1302 1420 { 1303 struct cmipci *cm = snd_pcm_substream_chip(subs); 1304 1305 spin_lock_irq(&cm->reg_lock); 1306 snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_CAPTURE_SPDF); 1307 spin_unlock_irq(&cm->reg_lock); 1308 1309 return snd_cmipci_hw_free(subs); 1421 struct cmipci *cm = snd_pcm_substream_chip(subs); 1422 1423 spin_lock_irq(&cm->reg_lock); 1424 snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_CAPTURE_SPDF); 1425 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL); 1426 spin_unlock_irq(&cm->reg_lock); 1427 1428 return snd_cmipci_hw_free(subs); 1310 1429 } 1311 1430 … … 1314 1433 * interrupt handler 1315 1434 */ 1316 static irqreturn_t snd_cmipci_interrupt(int irq, void *dev_id, struct pt_regs *regs) 1317 { 1318 struct cmipci *cm = dev_id; 1319 unsigned int status, mask = 0; 1320 #ifdef DEBUG 1321 // dprintf(("i")); 1322 #endif 1323 /* fastpath out, to ease interrupt sharing */ 1324 status = snd_cmipci_read(cm, CM_REG_INT_STATUS); 1325 if (!(status & CM_INTR)) 1326 return IRQ_NONE; 1327 1328 1329 /* acknowledge interrupt */ 1330 spin_lock(&cm->reg_lock); 1331 if (status & CM_CHINT0) 1332 mask |= CM_CH0_INT_EN; 1333 if (status & CM_CHINT1) 1334 mask |= CM_CH1_INT_EN; 1335 snd_cmipci_clear_bit(cm, CM_REG_INT_HLDCLR, mask); 1336 snd_cmipci_set_bit(cm, CM_REG_INT_HLDCLR, mask); 1337 spin_unlock(&cm->reg_lock); 1338 1339 if (cm->rmidi && (status & CM_UARTINT)) 1340 snd_mpu401_uart_interrupt(irq, cm->rmidi->private_data, regs); 1341 1342 if (cm->pcm) { 1343 if ((status & CM_CHINT0) && cm->channel[0].running) 1344 snd_pcm_period_elapsed(cm->channel[0].substream); 1345 if ((status & CM_CHINT1) && cm->channel[1].running) 1346 snd_pcm_period_elapsed(cm->channel[1].substream); 1347 } 1348 return IRQ_HANDLED; 1435 static irqreturn_t snd_cmipci_interrupt(int irq, void *dev_id) 1436 { 1437 struct cmipci *cm = dev_id; 1438 unsigned int status, mask = 0; 1439 1440 /* fastpath out, to ease interrupt sharing */ 1441 status = snd_cmipci_read(cm, CM_REG_INT_STATUS); 1442 if (!(status & CM_INTR)) 1443 return IRQ_NONE; 1444 1445 /* acknowledge interrupt */ 1446 spin_lock(&cm->reg_lock); 1447 if (status & CM_CHINT0) 1448 mask |= CM_CH0_INT_EN; 1449 if (status & CM_CHINT1) 1450 mask |= CM_CH1_INT_EN; 1451 snd_cmipci_clear_bit(cm, CM_REG_INT_HLDCLR, mask); 1452 snd_cmipci_set_bit(cm, CM_REG_INT_HLDCLR, mask); 1453 spin_unlock(&cm->reg_lock); 1454 1455 if (cm->rmidi && (status & CM_UARTINT)) 1456 snd_mpu401_uart_interrupt(irq, cm->rmidi->private_data); 1457 1458 if (cm->pcm) { 1459 if ((status & CM_CHINT0) && cm->channel[0].running) 1460 snd_pcm_period_elapsed(cm->channel[0].substream); 1461 if ((status & CM_CHINT1) && cm->channel[1].running) 1462 snd_pcm_period_elapsed(cm->channel[1].substream); 1463 } 1464 return IRQ_HANDLED; 1349 1465 } 1350 1466 … … 1357 1473 { 1358 1474 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED | 1359 1360 1475 SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE | 1476 SNDRV_PCM_INFO_RESUME | SNDRV_PCM_INFO_MMAP_VALID), 1361 1477 .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE, 1362 1478 .rates = SNDRV_PCM_RATE_5512 | SNDRV_PCM_RATE_8000_48000, … … 1377 1493 { 1378 1494 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED | 1379 1380 1495 SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE | 1496 SNDRV_PCM_INFO_RESUME | SNDRV_PCM_INFO_MMAP_VALID), 1381 1497 .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE, 1382 1498 .rates = SNDRV_PCM_RATE_5512 | SNDRV_PCM_RATE_8000_48000, … … 1397 1513 { 1398 1514 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED | 1399 1400 1515 SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE | 1516 SNDRV_PCM_INFO_RESUME | SNDRV_PCM_INFO_MMAP_VALID), 1401 1517 .formats = SNDRV_PCM_FMTBIT_S16_LE, 1402 1518 .rates = SNDRV_PCM_RATE_5512 | SNDRV_PCM_RATE_8000_48000, … … 1417 1533 { 1418 1534 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED | 1419 1420 1535 SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE | 1536 SNDRV_PCM_INFO_RESUME | SNDRV_PCM_INFO_MMAP_VALID), 1421 1537 .formats = SNDRV_PCM_FMTBIT_S16_LE, 1422 1538 .rates = SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000, … … 1437 1553 { 1438 1554 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED | 1439 1440 1555 SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE | 1556 SNDRV_PCM_INFO_RESUME | SNDRV_PCM_INFO_MMAP_VALID), 1441 1557 .formats = SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE, 1442 1558 .rates = SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000, … … 1457 1573 { 1458 1574 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED | 1459 SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE | 1460 SNDRV_PCM_INFO_RESUME | SNDRV_PCM_INFO_MMAP_VALID), 1461 .formats = SNDRV_PCM_FMTBIT_S16_LE, 1575 SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE | 1576 SNDRV_PCM_INFO_RESUME | SNDRV_PCM_INFO_MMAP_VALID), 1577 .formats = SNDRV_PCM_FMTBIT_S16_LE | 1578 SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE, 1462 1579 .rates = SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000, 1463 1580 .rate_min = 44100, … … 1473 1590 }; 1474 1591 1592 static unsigned int rate_constraints[] = { 5512, 8000, 11025, 16000, 22050, 1593 32000, 44100, 48000, 88200, 96000, 128000 }; 1594 static struct snd_pcm_hw_constraint_list hw_constraints_rates = { 1595 .count = ARRAY_SIZE(rate_constraints), 1596 .list = rate_constraints, 1597 .mask = 0, 1598 }; 1475 1599 1476 1600 /* … … 1479 1603 static int open_device_check(struct cmipci *cm, int mode, struct snd_pcm_substream *subs) 1480 1604 { 1481 1482 1483 1484 1485 1486 1487 1488 down(&cm->open_mutex);1489 1490 up(&cm->open_mutex);1491 1492 1493 1494 1495 1496 1497 1498 1499 1500 1501 1502 up(&cm->open_mutex);1503 1605 int ch = mode & CM_OPEN_CH_MASK; 1606 1607 /* FIXME: a file should wait until the device becomes free 1608 * when it's opened on blocking mode. however, since the current 1609 * pcm framework doesn't pass file pointer before actually opened, 1610 * we can't know whether blocking mode or not in open callback.. 1611 */ 1612 mutex_lock(&cm->open_mutex); 1613 if (cm->opened[ch]) { 1614 mutex_unlock(&cm->open_mutex); 1615 return -EBUSY; 1616 } 1617 cm->opened[ch] = mode; 1618 cm->channel[ch].substream = subs; 1619 if (! (mode & CM_OPEN_DAC)) { 1620 /* disable dual DAC mode */ 1621 cm->channel[ch].is_dac = 0; 1622 spin_lock_irq(&cm->reg_lock); 1623 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_ENDBDAC); 1624 spin_unlock_irq(&cm->reg_lock); 1625 } 1626 mutex_unlock(&cm->open_mutex); 1627 return 0; 1504 1628 } 1505 1629 1506 1630 static void close_device_check(struct cmipci *cm, int mode) 1507 1631 { 1508 int ch = mode & CM_OPEN_CH_MASK; 1509 1510 down(&cm->open_mutex); 1511 1512 if (cm->opened[ch] == mode) { 1513 if (cm->channel[ch].substream) { 1514 snd_cmipci_ch_reset(cm, ch); 1515 cm->channel[ch].running = 0; 1516 cm->channel[ch].substream = NULL; 1517 } 1518 cm->opened[ch] = 0; 1519 if (! cm->channel[ch].is_dac) { 1520 /* enable dual DAC mode again */ 1521 cm->channel[ch].is_dac = 1; 1522 spin_lock_irq(&cm->reg_lock); 1523 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_ENDBDAC); 1524 spin_unlock_irq(&cm->reg_lock); 1525 } 1526 } 1527 up(&cm->open_mutex); 1632 int ch = mode & CM_OPEN_CH_MASK; 1633 1634 mutex_lock(&cm->open_mutex); 1635 if (cm->opened[ch] == mode) { 1636 if (cm->channel[ch].substream) { 1637 snd_cmipci_ch_reset(cm, ch); 1638 cm->channel[ch].running = 0; 1639 cm->channel[ch].substream = NULL; 1640 } 1641 cm->opened[ch] = 0; 1642 if (! cm->channel[ch].is_dac) { 1643 /* enable dual DAC mode again */ 1644 cm->channel[ch].is_dac = 1; 1645 spin_lock_irq(&cm->reg_lock); 1646 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_ENDBDAC); 1647 spin_unlock_irq(&cm->reg_lock); 1648 } 1649 } 1650 mutex_unlock(&cm->open_mutex); 1528 1651 } 1529 1652 … … 1533 1656 static int snd_cmipci_playback_open(struct snd_pcm_substream *substream) 1534 1657 { 1535 struct cmipci *cm = snd_pcm_substream_chip(substream); 1536 struct snd_pcm_runtime *runtime = substream->runtime; 1537 int err; 1538 1539 if ((err = open_device_check(cm, CM_OPEN_PLAYBACK, substream)) < 0) 1540 return err; 1541 runtime->hw = snd_cmipci_playback; 1542 runtime->hw.channels_max = cm->max_channels; 1543 snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 0, 0x10000); 1544 return 0; 1658 struct cmipci *cm = snd_pcm_substream_chip(substream); 1659 struct snd_pcm_runtime *runtime = substream->runtime; 1660 int err; 1661 1662 if ((err = open_device_check(cm, CM_OPEN_PLAYBACK, substream)) < 0) 1663 return err; 1664 runtime->hw = snd_cmipci_playback; 1665 if (cm->chip_version == 68) { 1666 runtime->hw.rates |= SNDRV_PCM_RATE_88200 | 1667 SNDRV_PCM_RATE_96000; 1668 runtime->hw.rate_max = 96000; 1669 } else if (cm->chip_version == 55) { 1670 err = snd_pcm_hw_constraint_list(runtime, 0, 1671 SNDRV_PCM_HW_PARAM_RATE, &hw_constraints_rates); 1672 if (err < 0) 1673 return err; 1674 runtime->hw.rates |= SNDRV_PCM_RATE_KNOT; 1675 runtime->hw.rate_max = 128000; 1676 } 1677 snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 0, 0x10000); 1678 cm->dig_pcm_status = cm->dig_status; 1679 return 0; 1545 1680 } 1546 1681 1547 1682 static int snd_cmipci_capture_open(struct snd_pcm_substream *substream) 1548 1683 { 1549 struct cmipci *cm = snd_pcm_substream_chip(substream); 1550 struct snd_pcm_runtime *runtime = substream->runtime; 1551 int err; 1552 1553 if ((err = open_device_check(cm, CM_OPEN_CAPTURE, substream)) < 0) 1554 return err; 1555 runtime->hw = snd_cmipci_capture; 1556 if (cm->chip_version == 68) { // 8768 only supports 44k/48k recording 1557 runtime->hw.rate_min = 41000; 1558 runtime->hw.rates = SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000; 1559 } 1560 snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 0, 0x10000); 1561 return 0; 1684 struct cmipci *cm = snd_pcm_substream_chip(substream); 1685 struct snd_pcm_runtime *runtime = substream->runtime; 1686 int err; 1687 1688 if ((err = open_device_check(cm, CM_OPEN_CAPTURE, substream)) < 0) 1689 return err; 1690 runtime->hw = snd_cmipci_capture; 1691 if (cm->chip_version == 68) { // 8768 only supports 44k/48k recording 1692 runtime->hw.rate_min = 41000; 1693 runtime->hw.rates = SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000; 1694 } else if (cm->chip_version == 55) { 1695 err = snd_pcm_hw_constraint_list(runtime, 0, 1696 SNDRV_PCM_HW_PARAM_RATE, &hw_constraints_rates); 1697 if (err < 0) 1698 return err; 1699 runtime->hw.rates |= SNDRV_PCM_RATE_KNOT; 1700 runtime->hw.rate_max = 128000; 1701 } 1702 snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 0, 0x10000); 1703 return 0; 1562 1704 } 1563 1705 1564 1706 static int snd_cmipci_playback2_open(struct snd_pcm_substream *substream) 1565 1707 { 1566 struct cmipci *cm = snd_pcm_substream_chip(substream); 1567 struct snd_pcm_runtime *runtime = substream->runtime; 1568 int err; 1569 1570 if ((err = open_device_check(cm, CM_OPEN_PLAYBACK2, substream)) < 0) /* use channel B */ 1571 return err; 1572 runtime->hw = snd_cmipci_playback2; 1573 down(&cm->open_mutex); 1574 //if (! cm->opened[CM_CH_PLAY]) { 1575 if (1) { /* f&%$&g uniaud16 doesnt close stream */ 1576 if (cm->can_multi_ch) { 1577 runtime->hw.channels_max = cm->max_channels; 1578 if (cm->max_channels == 4) 1579 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, &hw_constraints_channels_4); 1580 else if (cm->max_channels == 6) 1581 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, &hw_constraints_channels_6); 1582 else if (cm->max_channels == 8) 1583 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, &hw_constraints_channels_8); 1584 } 1585 snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 0, 0x10000); 1586 } 1587 up(&cm->open_mutex); 1588 // printk("opened: %i, can MC: %i, max ch: %i, hw max ch: %i\n", 1589 // cm->opened[CM_CH_PLAY], cm->can_multi_ch, cm->max_channels, runtime->hw.channels_max); 1590 return 0; 1708 struct cmipci *cm = snd_pcm_substream_chip(substream); 1709 struct snd_pcm_runtime *runtime = substream->runtime; 1710 int err; 1711 1712 if ((err = open_device_check(cm, CM_OPEN_PLAYBACK2, substream)) < 0) /* use channel B */ 1713 return err; 1714 runtime->hw = snd_cmipci_playback2; 1715 mutex_lock(&cm->open_mutex); 1716 if (! cm->opened[CM_CH_PLAY]) { 1717 if (cm->can_multi_ch) { 1718 runtime->hw.channels_max = cm->max_channels; 1719 if (cm->max_channels == 4) 1720 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, &hw_constraints_channels_4); 1721 else if (cm->max_channels == 6) 1722 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, &hw_constraints_channels_6); 1723 else if (cm->max_channels == 8) 1724 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, &hw_constraints_channels_8); 1725 } 1726 } 1727 mutex_unlock(&cm->open_mutex); 1728 if (cm->chip_version == 68) { 1729 runtime->hw.rates |= SNDRV_PCM_RATE_88200 | 1730 SNDRV_PCM_RATE_96000; 1731 runtime->hw.rate_max = 96000; 1732 } else if (cm->chip_version == 55) { 1733 err = snd_pcm_hw_constraint_list(runtime, 0, 1734 SNDRV_PCM_HW_PARAM_RATE, &hw_constraints_rates); 1735 if (err < 0) 1736 return err; 1737 runtime->hw.rates |= SNDRV_PCM_RATE_KNOT; 1738 runtime->hw.rate_max = 128000; 1739 } 1740 snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 0, 0x10000); 1741 return 0; 1591 1742 } 1592 1743 1593 1744 static int snd_cmipci_playback_spdif_open(struct snd_pcm_substream *substream) 1594 1745 { 1595 struct cmipci *cm = snd_pcm_substream_chip(substream); 1596 struct snd_pcm_runtime *runtime = substream->runtime; 1597 int err; 1598 1599 if ((err = open_device_check(cm, CM_OPEN_SPDIF_PLAYBACK, substream)) < 0) /* use channel A */ 1600 return err; 1601 if (cm->can_ac3_hw) { 1602 runtime->hw = snd_cmipci_playback_spdif; 1603 if (cm->chip_version >= 37) 1604 runtime->hw.formats |= SNDRV_PCM_FMTBIT_S32_LE; 1605 } else { 1606 runtime->hw = snd_cmipci_playback_iec958_subframe; 1607 } 1608 snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 0, 0x40000); 1609 cm->dig_pcm_status = cm->dig_status; 1610 return 0; 1746 struct cmipci *cm = snd_pcm_substream_chip(substream); 1747 struct snd_pcm_runtime *runtime = substream->runtime; 1748 int err; 1749 1750 if ((err = open_device_check(cm, CM_OPEN_SPDIF_PLAYBACK, substream)) < 0) /* use channel A */ 1751 return err; 1752 if (cm->can_ac3_hw) { 1753 runtime->hw = snd_cmipci_playback_spdif; 1754 if (cm->chip_version >= 37) { 1755 runtime->hw.formats |= SNDRV_PCM_FMTBIT_S32_LE; 1756 snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24); 1757 } 1758 if (cm->can_96k) { 1759 runtime->hw.rates |= SNDRV_PCM_RATE_88200 | 1760 SNDRV_PCM_RATE_96000; 1761 runtime->hw.rate_max = 96000; 1762 } 1763 } else { 1764 runtime->hw = snd_cmipci_playback_iec958_subframe; 1765 } 1766 snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 0, 0x40000); 1767 cm->dig_pcm_status = cm->dig_status; 1768 return 0; 1611 1769 } 1612 1770 1613 1771 static int snd_cmipci_capture_spdif_open(struct snd_pcm_substream *substream) 1614 1772 { 1615 struct cmipci *cm = snd_pcm_substream_chip(substream); 1616 struct snd_pcm_runtime *runtime = substream->runtime; 1617 int err; 1618 1619 if ((err = open_device_check(cm, CM_OPEN_SPDIF_CAPTURE, substream)) < 0) /* use channel B */ 1620 return err; 1621 runtime->hw = snd_cmipci_capture_spdif; 1622 snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 0, 0x40000); 1623 return 0; 1773 struct cmipci *cm = snd_pcm_substream_chip(substream); 1774 struct snd_pcm_runtime *runtime = substream->runtime; 1775 int err; 1776 1777 if ((err = open_device_check(cm, CM_OPEN_SPDIF_CAPTURE, substream)) < 0) /* use channel B */ 1778 return err; 1779 runtime->hw = snd_cmipci_capture_spdif; 1780 if (cm->can_96k && !(cm->chip_version == 68)) { 1781 runtime->hw.rates |= SNDRV_PCM_RATE_88200 | 1782 SNDRV_PCM_RATE_96000; 1783 runtime->hw.rate_max = 96000; 1784 } 1785 snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 0, 0x40000); 1786 return 0; 1624 1787 } 1625 1788 … … 1630 1793 static int snd_cmipci_playback_close(struct snd_pcm_substream *substream) 1631 1794 { 1632 1633 1634 1795 struct cmipci *cm = snd_pcm_substream_chip(substream); 1796 close_device_check(cm, CM_OPEN_PLAYBACK); 1797 return 0; 1635 1798 } 1636 1799 1637 1800 static int snd_cmipci_capture_close(struct snd_pcm_substream *substream) 1638 1801 { 1639 1640 1641 1802 struct cmipci *cm = snd_pcm_substream_chip(substream); 1803 close_device_check(cm, CM_OPEN_CAPTURE); 1804 return 0; 1642 1805 } 1643 1806 1644 1807 static int snd_cmipci_playback2_close(struct snd_pcm_substream *substream) 1645 1808 { 1646 1647 1648 1649 1809 struct cmipci *cm = snd_pcm_substream_chip(substream); 1810 close_device_check(cm, CM_OPEN_PLAYBACK2); 1811 close_device_check(cm, CM_OPEN_PLAYBACK_MULTI); 1812 return 0; 1650 1813 } 1651 1814 1652 1815 static int snd_cmipci_playback_spdif_close(struct snd_pcm_substream *substream) 1653 1816 { 1654 1655 1656 1817 struct cmipci *cm = snd_pcm_substream_chip(substream); 1818 close_device_check(cm, CM_OPEN_SPDIF_PLAYBACK); 1819 return 0; 1657 1820 } 1658 1821 1659 1822 static int snd_cmipci_capture_spdif_close(struct snd_pcm_substream *substream) 1660 1823 { 1661 1662 1663 1824 struct cmipci *cm = snd_pcm_substream_chip(substream); 1825 close_device_check(cm, CM_OPEN_SPDIF_CAPTURE); 1826 return 0; 1664 1827 } 1665 1828 … … 1695 1858 .ioctl = snd_pcm_lib_ioctl, 1696 1859 .hw_params = snd_cmipci_playback2_hw_params, 1697 .hw_free = snd_cmipci_ hw_free,1860 .hw_free = snd_cmipci_playback2_hw_free, 1698 1861 .prepare = snd_cmipci_capture_prepare, /* channel B */ 1699 1862 .trigger = snd_cmipci_capture_trigger, /* channel B */ … … 1723 1886 }; 1724 1887 1725 /* 1726 */ 1727 1728 static void snd_cmipci_pcm_free(struct snd_pcm *pcm) 1729 { 1730 snd_pcm_lib_preallocate_free_for_all(pcm); 1731 } 1888 1889 /* 1890 */ 1732 1891 1733 1892 static int __devinit snd_cmipci_pcm_new(struct cmipci *cm, int device) 1734 1893 { 1735 struct snd_pcm *pcm; 1736 int err; 1737 1738 err = snd_pcm_new(cm->card, cm->card->driver, device, 1, 1, &pcm); 1739 if (err < 0) 1740 return err; 1741 1742 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cmipci_playback_ops); 1743 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_cmipci_capture_ops); 1744 1745 pcm->private_data = cm; 1746 pcm->private_free = snd_cmipci_pcm_free; 1747 pcm->info_flags = 0; 1748 strcpy(pcm->name, "C-Media PCI DAC/ADC"); 1749 cm->pcm = pcm; 1750 1751 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV, 1752 snd_dma_pci_data(cm->pci), 64*1024, 128*1024); 1753 1754 return 0; 1894 struct snd_pcm *pcm; 1895 int err; 1896 1897 err = snd_pcm_new(cm->card, cm->card->driver, device, 1, 1, &pcm); 1898 if (err < 0) 1899 return err; 1900 1901 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cmipci_playback_ops); 1902 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_cmipci_capture_ops); 1903 1904 pcm->private_data = cm; 1905 pcm->info_flags = 0; 1906 strcpy(pcm->name, "C-Media PCI DAC/ADC"); 1907 cm->pcm = pcm; 1908 1909 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV, 1910 snd_dma_pci_data(cm->pci), 64*1024, 128*1024); 1911 1912 return 0; 1755 1913 } 1756 1914 1757 1915 static int __devinit snd_cmipci_pcm2_new(struct cmipci *cm, int device) 1758 1916 { 1759 struct snd_pcm *pcm; 1760 int err; 1761 1762 err = snd_pcm_new(cm->card, cm->card->driver, device, 1, 0, &pcm); 1763 if (err < 0) 1764 return err; 1765 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cmipci_playback2_ops); 1766 pcm->private_data = cm; 1767 pcm->private_free = snd_cmipci_pcm_free; 1768 pcm->info_flags = 0; 1769 strcpy(pcm->name, "C-Media PCI 2nd DAC"); 1770 cm->pcm2 = pcm; 1771 1772 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV, 1773 snd_dma_pci_data(cm->pci), 64*1024, 128*1024); 1774 1775 return 0; 1917 struct snd_pcm *pcm; 1918 int err; 1919 1920 err = snd_pcm_new(cm->card, cm->card->driver, device, 1, 0, &pcm); 1921 if (err < 0) 1922 return err; 1923 1924 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cmipci_playback2_ops); 1925 1926 pcm->private_data = cm; 1927 pcm->info_flags = 0; 1928 strcpy(pcm->name, "C-Media PCI 2nd DAC"); 1929 cm->pcm2 = pcm; 1930 1931 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV, 1932 snd_dma_pci_data(cm->pci), 64*1024, 128*1024); 1933 1934 return 0; 1776 1935 } 1777 1936 1778 1937 static int __devinit snd_cmipci_pcm_spdif_new(struct cmipci *cm, int device) 1779 1938 { 1780 struct snd_pcm *pcm; 1781 int err; 1782 1783 err = snd_pcm_new(cm->card, cm->card->driver, device, 1, 1, &pcm); 1784 if (err < 0) 1785 return err; 1786 1787 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cmipci_playback_spdif_ops); 1788 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_cmipci_capture_spdif_ops); 1789 1790 pcm->private_data = cm; 1791 pcm->private_free = snd_cmipci_pcm_free; 1792 pcm->info_flags = 0; 1793 strcpy(pcm->name, "C-Media PCI IEC958"); 1794 cm->pcm_spdif = pcm; 1795 1796 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV, 1797 snd_dma_pci_data(cm->pci), 64*1024, 128*1024); 1798 1799 return 0; 1939 struct snd_pcm *pcm; 1940 int err; 1941 1942 err = snd_pcm_new(cm->card, cm->card->driver, device, 1, 1, &pcm); 1943 if (err < 0) 1944 return err; 1945 1946 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cmipci_playback_spdif_ops); 1947 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_cmipci_capture_spdif_ops); 1948 1949 pcm->private_data = cm; 1950 pcm->info_flags = 0; 1951 strcpy(pcm->name, "C-Media PCI IEC958"); 1952 cm->pcm_spdif = pcm; 1953 1954 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV, 1955 snd_dma_pci_data(cm->pci), 64*1024, 128*1024); 1956 1957 return 0; 1800 1958 } 1801 1959 … … 1811 1969 static void snd_cmipci_mixer_write(struct cmipci *s, unsigned char idx, unsigned char data) 1812 1970 { 1813 1814 1971 outb(idx, s->iobase + CM_REG_SB16_ADDR); 1972 outb(data, s->iobase + CM_REG_SB16_DATA); 1815 1973 } 1816 1974 1817 1975 static unsigned char snd_cmipci_mixer_read(struct cmipci *s, unsigned char idx) 1818 1976 { 1819 1820 1821 1822 1823 1977 unsigned char v; 1978 1979 outb(idx, s->iobase + CM_REG_SB16_ADDR); 1980 v = inb(s->iobase + CM_REG_SB16_DATA); 1981 return v; 1824 1982 } 1825 1983 … … 1828 1986 */ 1829 1987 struct cmipci_sb_reg { 1830 1831 1832 1833 1834 1988 unsigned int left_reg, right_reg; 1989 unsigned int left_shift, right_shift; 1990 unsigned int mask; 1991 unsigned int invert: 1; 1992 unsigned int stereo: 1; 1835 1993 }; 1836 1994 1837 1995 #define COMPOSE_SB_REG(lreg,rreg,lshift,rshift,mask,invert,stereo) \ 1838 1996 ((lreg) | ((rreg) << 8) | (lshift << 16) | (rshift << 19) | (mask << 24) | (invert << 22) | (stereo << 23)) 1839 1997 1840 1998 #define CMIPCI_DOUBLE(xname, left_reg, right_reg, left_shift, right_shift, mask, invert, stereo) \ 1841 { SNDRV_CTL_ELEM_IFACE_MIXER, 0, 0, xname, 0, \ 1842 0, 0, snd_cmipci_info_volume, \ 1843 snd_cmipci_get_volume, snd_cmipci_put_volume, \ 1844 0,\ 1845 COMPOSE_SB_REG(left_reg, right_reg, left_shift, right_shift, mask, invert, stereo), \ 1846 } 1999 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ 2000 .info = snd_cmipci_info_volume, \ 2001 .get = snd_cmipci_get_volume, .put = snd_cmipci_put_volume, \ 2002 .private_value = COMPOSE_SB_REG(left_reg, right_reg, left_shift, right_shift, mask, invert, stereo), \ 2003 } 1847 2004 1848 2005 #define CMIPCI_SB_VOL_STEREO(xname,reg,shift,mask) CMIPCI_DOUBLE(xname, reg, reg+1, shift, shift, mask, 0, 1) … … 1853 2010 static void cmipci_sb_reg_decode(struct cmipci_sb_reg *r, unsigned long val) 1854 2011 { 1855 1856 1857 1858 1859 1860 1861 2012 r->left_reg = val & 0xff; 2013 r->right_reg = (val >> 8) & 0xff; 2014 r->left_shift = (val >> 16) & 0x07; 2015 r->right_shift = (val >> 19) & 0x07; 2016 r->invert = (val >> 22) & 1; 2017 r->stereo = (val >> 23) & 1; 2018 r->mask = (val >> 24) & 0xff; 1862 2019 } 1863 2020 1864 2021 static int snd_cmipci_info_volume(struct snd_kcontrol *kcontrol, 1865 1866 { 1867 1868 1869 1870 1871 1872 1873 1874 1875 } 1876 2022 struct snd_ctl_elem_info *uinfo) 2023 { 2024 struct cmipci_sb_reg reg; 2025 2026 cmipci_sb_reg_decode(®, kcontrol->private_value); 2027 uinfo->type = reg.mask == 1 ? SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER; 2028 uinfo->count = reg.stereo + 1; 2029 uinfo->value.integer.min = 0; 2030 uinfo->value.integer.max = reg.mask; 2031 return 0; 2032 } 2033 1877 2034 static int snd_cmipci_get_volume(struct snd_kcontrol *kcontrol, 1878 1879 { 1880 1881 1882 1883 1884 1885 1886 1887 1888 1889 1890 1891 1892 1893 1894 1895 1896 1897 2035 struct snd_ctl_elem_value *ucontrol) 2036 { 2037 struct cmipci *cm = snd_kcontrol_chip(kcontrol); 2038 struct cmipci_sb_reg reg; 2039 int val; 2040 2041 cmipci_sb_reg_decode(®, kcontrol->private_value); 2042 spin_lock_irq(&cm->reg_lock); 2043 val = (snd_cmipci_mixer_read(cm, reg.left_reg) >> reg.left_shift) & reg.mask; 2044 if (reg.invert) 2045 val = reg.mask - val; 2046 ucontrol->value.integer.value[0] = val; 2047 if (reg.stereo) { 2048 val = (snd_cmipci_mixer_read(cm, reg.right_reg) >> reg.right_shift) & reg.mask; 2049 if (reg.invert) 2050 val = reg.mask - val; 2051 ucontrol->value.integer.value[1] = val; 2052 } 2053 spin_unlock_irq(&cm->reg_lock); 2054 return 0; 1898 2055 } 1899 2056 1900 2057 static int snd_cmipci_put_volume(struct snd_kcontrol *kcontrol, 1901 1902 { 1903 1904 1905 1906 1907 1908 1909 1910 1911 1912 1913 1914 1915 1916 1917 1918 1919 1920 1921 1922 1923 1924 1925 1926 1927 1928 1929 1930 1931 1932 1933 1934 1935 1936 2058 struct snd_ctl_elem_value *ucontrol) 2059 { 2060 struct cmipci *cm = snd_kcontrol_chip(kcontrol); 2061 struct cmipci_sb_reg reg; 2062 int change; 2063 int left, right, oleft, oright; 2064 2065 cmipci_sb_reg_decode(®, kcontrol->private_value); 2066 left = ucontrol->value.integer.value[0] & reg.mask; 2067 if (reg.invert) 2068 left = reg.mask - left; 2069 left <<= reg.left_shift; 2070 if (reg.stereo) { 2071 right = ucontrol->value.integer.value[1] & reg.mask; 2072 if (reg.invert) 2073 right = reg.mask - right; 2074 right <<= reg.right_shift; 2075 } else 2076 right = 0; 2077 spin_lock_irq(&cm->reg_lock); 2078 oleft = snd_cmipci_mixer_read(cm, reg.left_reg); 2079 left |= oleft & ~(reg.mask << reg.left_shift); 2080 change = left != oleft; 2081 if (reg.stereo) { 2082 if (reg.left_reg != reg.right_reg) { 2083 snd_cmipci_mixer_write(cm, reg.left_reg, left); 2084 oright = snd_cmipci_mixer_read(cm, reg.right_reg); 2085 } else 2086 oright = left; 2087 right |= oright & ~(reg.mask << reg.right_shift); 2088 change |= right != oright; 2089 snd_cmipci_mixer_write(cm, reg.right_reg, right); 2090 } else 2091 snd_cmipci_mixer_write(cm, reg.left_reg, left); 2092 spin_unlock_irq(&cm->reg_lock); 2093 return change; 1937 2094 } 1938 2095 … … 1941 2098 */ 1942 2099 #define CMIPCI_SB_INPUT_SW(xname, left_shift, right_shift) \ 1943 { SNDRV_CTL_ELEM_IFACE_MIXER, 0, 0, xname, 0, \1944 0, 0,snd_cmipci_info_input_sw, \1945 snd_cmipci_get_input_sw,snd_cmipci_put_input_sw, \1946 0, \1947 COMPOSE_SB_REG(SB_DSP4_INPUT_LEFT, SB_DSP4_INPUT_RIGHT, left_shift, right_shift, 1, 0, 1), \ 1948 } 2100 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ 2101 .info = snd_cmipci_info_input_sw, \ 2102 .get = snd_cmipci_get_input_sw, .put = snd_cmipci_put_input_sw, \ 2103 .private_value = COMPOSE_SB_REG(SB_DSP4_INPUT_LEFT, SB_DSP4_INPUT_RIGHT, left_shift, right_shift, 1, 0, 1), \ 2104 } 2105 1949 2106 static int snd_cmipci_info_input_sw(struct snd_kcontrol *kcontrol, 1950 1951 { 1952 1953 1954 1955 1956 1957 } 1958 2107 struct snd_ctl_elem_info *uinfo) 2108 { 2109 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN; 2110 uinfo->count = 4; 2111 uinfo->value.integer.min = 0; 2112 uinfo->value.integer.max = 1; 2113 return 0; 2114 } 2115 1959 2116 static int snd_cmipci_get_input_sw(struct snd_kcontrol *kcontrol, 1960 1961 { 1962 1963 1964 1965 1966 1967 1968 1969 1970 1971 1972 1973 1974 1975 2117 struct snd_ctl_elem_value *ucontrol) 2118 { 2119 struct cmipci *cm = snd_kcontrol_chip(kcontrol); 2120 struct cmipci_sb_reg reg; 2121 int val1, val2; 2122 2123 cmipci_sb_reg_decode(®, kcontrol->private_value); 2124 spin_lock_irq(&cm->reg_lock); 2125 val1 = snd_cmipci_mixer_read(cm, reg.left_reg); 2126 val2 = snd_cmipci_mixer_read(cm, reg.right_reg); 2127 spin_unlock_irq(&cm->reg_lock); 2128 ucontrol->value.integer.value[0] = (val1 >> reg.left_shift) & 1; 2129 ucontrol->value.integer.value[1] = (val2 >> reg.left_shift) & 1; 2130 ucontrol->value.integer.value[2] = (val1 >> reg.right_shift) & 1; 2131 ucontrol->value.integer.value[3] = (val2 >> reg.right_shift) & 1; 2132 return 0; 1976 2133 } 1977 2134 1978 2135 static int snd_cmipci_put_input_sw(struct snd_kcontrol *kcontrol, 1979 1980 { 1981 1982 1983 1984 1985 1986 1987 1988 1989 1990 1991 1992 1993 1994 1995 1996 1997 1998 1999 2000 2136 struct snd_ctl_elem_value *ucontrol) 2137 { 2138 struct cmipci *cm = snd_kcontrol_chip(kcontrol); 2139 struct cmipci_sb_reg reg; 2140 int change; 2141 int val1, val2, oval1, oval2; 2142 2143 cmipci_sb_reg_decode(®, kcontrol->private_value); 2144 spin_lock_irq(&cm->reg_lock); 2145 oval1 = snd_cmipci_mixer_read(cm, reg.left_reg); 2146 oval2 = snd_cmipci_mixer_read(cm, reg.right_reg); 2147 val1 = oval1 & ~((1 << reg.left_shift) | (1 << reg.right_shift)); 2148 val2 = oval2 & ~((1 << reg.left_shift) | (1 << reg.right_shift)); 2149 val1 |= (ucontrol->value.integer.value[0] & 1) << reg.left_shift; 2150 val2 |= (ucontrol->value.integer.value[1] & 1) << reg.left_shift; 2151 val1 |= (ucontrol->value.integer.value[2] & 1) << reg.right_shift; 2152 val2 |= (ucontrol->value.integer.value[3] & 1) << reg.right_shift; 2153 change = val1 != oval1 || val2 != oval2; 2154 snd_cmipci_mixer_write(cm, reg.left_reg, val1); 2155 snd_cmipci_mixer_write(cm, reg.right_reg, val2); 2156 spin_unlock_irq(&cm->reg_lock); 2157 return change; 2001 2158 } 2002 2159 … … 2006 2163 2007 2164 #define CMIPCI_MIXER_SW_STEREO(xname, reg, lshift, rshift, invert) \ 2008 { SNDRV_CTL_ELEM_IFACE_MIXER, 0, 0, xname, 0, \ 2009 0, 0, snd_cmipci_info_native_mixer, \ 2010 snd_cmipci_get_native_mixer, snd_cmipci_put_native_mixer, \ 2011 0, \ 2012 COMPOSE_SB_REG(reg, reg, lshift, rshift, 1, invert, 1), \ 2013 } 2165 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ 2166 .info = snd_cmipci_info_native_mixer, \ 2167 .get = snd_cmipci_get_native_mixer, .put = snd_cmipci_put_native_mixer, \ 2168 .private_value = COMPOSE_SB_REG(reg, reg, lshift, rshift, 1, invert, 1), \ 2169 } 2014 2170 2015 2171 #define CMIPCI_MIXER_SW_MONO(xname, reg, shift, invert) \ 2016 { SNDRV_CTL_ELEM_IFACE_MIXER, 0, 0, xname, 0, \ 2017 0, 0, snd_cmipci_info_native_mixer, \ 2018 snd_cmipci_get_native_mixer, snd_cmipci_put_native_mixer, \ 2019 0, \ 2020 COMPOSE_SB_REG(reg, reg, shift, shift, 1, invert, 0), \ 2021 } 2172 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ 2173 .info = snd_cmipci_info_native_mixer, \ 2174 .get = snd_cmipci_get_native_mixer, .put = snd_cmipci_put_native_mixer, \ 2175 .private_value = COMPOSE_SB_REG(reg, reg, shift, shift, 1, invert, 0), \ 2176 } 2022 2177 2023 2178 #define CMIPCI_MIXER_VOL_STEREO(xname, reg, lshift, rshift, mask) \ 2024 { SNDRV_CTL_ELEM_IFACE_MIXER, 0, 0, xname, 0, \ 2025 0, 0, snd_cmipci_info_native_mixer, \ 2026 snd_cmipci_get_native_mixer, snd_cmipci_put_native_mixer, \ 2027 0, \ 2028 COMPOSE_SB_REG(reg, reg, lshift, rshift, mask, 0, 1), \ 2029 } 2179 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ 2180 .info = snd_cmipci_info_native_mixer, \ 2181 .get = snd_cmipci_get_native_mixer, .put = snd_cmipci_put_native_mixer, \ 2182 .private_value = COMPOSE_SB_REG(reg, reg, lshift, rshift, mask, 0, 1), \ 2183 } 2030 2184 2031 2185 #define CMIPCI_MIXER_VOL_MONO(xname, reg, shift, mask) \ 2032 { SNDRV_CTL_ELEM_IFACE_MIXER, 0, 0, xname, 0, \ 2033 0, 0, snd_cmipci_info_native_mixer, \ 2034 snd_cmipci_get_native_mixer, snd_cmipci_put_native_mixer, \ 2035 0, \ 2036 COMPOSE_SB_REG(reg, reg, shift, shift, mask, 0, 0), \ 2037 } 2186 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ 2187 .info = snd_cmipci_info_native_mixer, \ 2188 .get = snd_cmipci_get_native_mixer, .put = snd_cmipci_put_native_mixer, \ 2189 .private_value = COMPOSE_SB_REG(reg, reg, shift, shift, mask, 0, 0), \ 2190 } 2038 2191 2039 2192 static int snd_cmipci_info_native_mixer(struct snd_kcontrol *kcontrol, 2040 2041 { 2042 2043 2044 2045 2046 2047 2048 2049 2193 struct snd_ctl_elem_info *uinfo) 2194 { 2195 struct cmipci_sb_reg reg; 2196 2197 cmipci_sb_reg_decode(®, kcontrol->private_value); 2198 uinfo->type = reg.mask == 1 ? SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER; 2199 uinfo->count = reg.stereo + 1; 2200 uinfo->value.integer.min = 0; 2201 uinfo->value.integer.max = reg.mask; 2202 return 0; 2050 2203 2051 2204 } 2052 2205 2053 2206 static int snd_cmipci_get_native_mixer(struct snd_kcontrol *kcontrol, 2054 2055 { 2056 2057 2058 2059 2060 2061 2062 2063 2064 2065 2066 2067 2068 2069 2070 2071 2072 2073 2074 2207 struct snd_ctl_elem_value *ucontrol) 2208 { 2209 struct cmipci *cm = snd_kcontrol_chip(kcontrol); 2210 struct cmipci_sb_reg reg; 2211 unsigned char oreg, val; 2212 2213 cmipci_sb_reg_decode(®, kcontrol->private_value); 2214 spin_lock_irq(&cm->reg_lock); 2215 oreg = inb(cm->iobase + reg.left_reg); 2216 val = (oreg >> reg.left_shift) & reg.mask; 2217 if (reg.invert) 2218 val = reg.mask - val; 2219 ucontrol->value.integer.value[0] = val; 2220 if (reg.stereo) { 2221 val = (oreg >> reg.right_shift) & reg.mask; 2222 if (reg.invert) 2223 val = reg.mask - val; 2224 ucontrol->value.integer.value[1] = val; 2225 } 2226 spin_unlock_irq(&cm->reg_lock); 2227 return 0; 2075 2228 } 2076 2229 2077 2230 static int snd_cmipci_put_native_mixer(struct snd_kcontrol *kcontrol, 2078 2079 { 2080 2081 2082 2083 2084 2085 2086 2087 2088 2089 2090 2091 2092 2093 2094 2095 2096 2097 2098 2099 2100 2101 2231 struct snd_ctl_elem_value *ucontrol) 2232 { 2233 struct cmipci *cm = snd_kcontrol_chip(kcontrol); 2234 struct cmipci_sb_reg reg; 2235 unsigned char oreg, nreg, val; 2236 2237 cmipci_sb_reg_decode(®, kcontrol->private_value); 2238 spin_lock_irq(&cm->reg_lock); 2239 oreg = inb(cm->iobase + reg.left_reg); 2240 val = ucontrol->value.integer.value[0] & reg.mask; 2241 if (reg.invert) 2242 val = reg.mask - val; 2243 nreg = oreg & ~(reg.mask << reg.left_shift); 2244 nreg |= (val << reg.left_shift); 2245 if (reg.stereo) { 2246 val = ucontrol->value.integer.value[1] & reg.mask; 2247 if (reg.invert) 2248 val = reg.mask - val; 2249 nreg &= ~(reg.mask << reg.right_shift); 2250 nreg |= (val << reg.right_shift); 2251 } 2252 outb(nreg, cm->iobase + reg.left_reg); 2253 spin_unlock_irq(&cm->reg_lock); 2254 return (nreg != oreg); 2102 2255 } 2103 2256 … … 2106 2259 */ 2107 2260 static int snd_cmipci_get_native_mixer_sensitive(struct snd_kcontrol *kcontrol, 2108 2109 { 2110 2111 2261 struct snd_ctl_elem_value *ucontrol) 2262 { 2263 //struct cmipci *cm = snd_kcontrol_chip(kcontrol); 2264 return snd_cmipci_get_native_mixer(kcontrol, ucontrol); 2112 2265 } 2113 2266 2114 2267 static int snd_cmipci_put_native_mixer_sensitive(struct snd_kcontrol *kcontrol, 2115 struct snd_ctl_elem_value *ucontrol) 2116 { 2117 struct cmipci *cm = snd_kcontrol_chip(kcontrol); 2118 if (cm->mixer_insensitive) { 2119 /* ignored */ 2120 return 0; 2121 } 2122 return snd_cmipci_put_native_mixer(kcontrol, ucontrol); 2123 } 2268 struct snd_ctl_elem_value *ucontrol) 2269 { 2270 struct cmipci *cm = snd_kcontrol_chip(kcontrol); 2271 if (cm->mixer_insensitive) { 2272 /* ignored */ 2273 return 0; 2274 } 2275 return snd_cmipci_put_native_mixer(kcontrol, ucontrol); 2276 } 2277 2124 2278 2125 2279 static struct snd_kcontrol_new snd_cmipci_mixers[] __devinitdata = { 2126 CMIPCI_SB_VOL_STEREO("Master Playback Volume", SB_DSP4_MASTER_DEV, 3, 31), 2127 CMIPCI_MIXER_SW_MONO("3D Control - Switch", CM_REG_MIXER1, CM_X3DEN_SHIFT, 0), 2128 CMIPCI_SB_VOL_STEREO("PCM Playback Volume", SB_DSP4_PCM_DEV, 3, 31), 2129 //CMIPCI_MIXER_SW_MONO("PCM Playback Switch", CM_REG_MIXER1, CM_WSMUTE_SHIFT, 1), 2130 { /* switch with sensitivity */ 2131 SNDRV_CTL_ELEM_IFACE_MIXER,0,0, 2132 "PCM Playback Switch",0,0,0, 2133 snd_cmipci_info_native_mixer, 2134 snd_cmipci_get_native_mixer_sensitive, 2135 snd_cmipci_put_native_mixer_sensitive, 2136 0, 2137 COMPOSE_SB_REG(CM_REG_MIXER1, CM_REG_MIXER1, CM_WSMUTE_SHIFT, CM_WSMUTE_SHIFT, 1, 1, 0), 2138 }, 2139 CMIPCI_MIXER_SW_STEREO("PCM Capture Switch", CM_REG_MIXER1, CM_WAVEINL_SHIFT, CM_WAVEINR_SHIFT, 0), 2140 CMIPCI_SB_VOL_STEREO("Synth Playback Volume", SB_DSP4_SYNTH_DEV, 3, 31), 2141 CMIPCI_MIXER_SW_MONO("Synth Playback Switch", CM_REG_MIXER1, CM_FMMUTE_SHIFT, 1), 2142 CMIPCI_SB_INPUT_SW("Synth Capture Route", 6, 5), 2143 CMIPCI_SB_VOL_STEREO("CD Playback Volume", SB_DSP4_CD_DEV, 3, 31), 2144 CMIPCI_SB_SW_STEREO("CD Playback Switch", 2, 1), 2145 CMIPCI_SB_INPUT_SW("CD Capture Route", 2, 1), 2146 CMIPCI_SB_VOL_STEREO("Line Playback Volume", SB_DSP4_LINE_DEV, 3, 31), 2147 CMIPCI_SB_SW_STEREO("Line Playback Switch", 4, 3), 2148 CMIPCI_SB_INPUT_SW("Line Capture Route", 4, 3), 2149 CMIPCI_SB_VOL_MONO("Mic Playback Volume", SB_DSP4_MIC_DEV, 3, 31), 2150 CMIPCI_SB_SW_MONO("Mic Playback Switch", 0), 2151 CMIPCI_DOUBLE("Mic Capture Switch", SB_DSP4_INPUT_LEFT, SB_DSP4_INPUT_RIGHT, 0, 0, 1, 0, 0), 2152 CMIPCI_SB_VOL_MONO("PC Speaker Playback Volume", SB_DSP4_SPEAKER_DEV, 6, 3), 2153 CMIPCI_MIXER_VOL_STEREO("Aux Playback Volume", CM_REG_AUX_VOL, 4, 0, 15), 2154 CMIPCI_MIXER_SW_STEREO("Aux Playback Switch", CM_REG_MIXER2, CM_VAUXLM_SHIFT, CM_VAUXRM_SHIFT, 0), 2155 CMIPCI_MIXER_SW_STEREO("Aux Capture Switch", CM_REG_MIXER2, CM_RAUXLEN_SHIFT, CM_RAUXREN_SHIFT, 0), 2156 CMIPCI_MIXER_SW_MONO("Mic Boost Playback Switch", CM_REG_MIXER2, CM_MICGAINZ_SHIFT, 1), 2157 CMIPCI_MIXER_VOL_MONO("Mic Capture Volume", CM_REG_MIXER2, CM_VADMIC_SHIFT, 7), 2158 CMIPCI_SB_VOL_MONO("Phone Playback Volume", CM_REG_EXTENT_IND, 5, 7), 2159 CMIPCI_DOUBLE("Phone Playback Switch", CM_REG_EXTENT_IND, CM_REG_EXTENT_IND, 4, 4, 1, 0, 0), 2160 CMIPCI_DOUBLE("PC Speaker Playback Switch", CM_REG_EXTENT_IND, CM_REG_EXTENT_IND, 3, 3, 1, 0, 0), 2161 CMIPCI_DOUBLE("Mic Boost Capture Switch", CM_REG_EXTENT_IND, CM_REG_EXTENT_IND, 0, 0, 1, 0, 0), 2280 CMIPCI_SB_VOL_STEREO("Master Playback Volume", SB_DSP4_MASTER_DEV, 3, 31), 2281 CMIPCI_MIXER_SW_MONO("3D Control - Switch", CM_REG_MIXER1, CM_X3DEN_SHIFT, 0), 2282 CMIPCI_SB_VOL_STEREO("PCM Playback Volume", SB_DSP4_PCM_DEV, 3, 31), 2283 //CMIPCI_MIXER_SW_MONO("PCM Playback Switch", CM_REG_MIXER1, CM_WSMUTE_SHIFT, 1), 2284 { /* switch with sensitivity */ 2285 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, 2286 .name = "PCM Playback Switch", 2287 .info = snd_cmipci_info_native_mixer, 2288 .get = snd_cmipci_get_native_mixer_sensitive, 2289 .put = snd_cmipci_put_native_mixer_sensitive, 2290 .private_value = COMPOSE_SB_REG(CM_REG_MIXER1, CM_REG_MIXER1, CM_WSMUTE_SHIFT, CM_WSMUTE_SHIFT, 1, 1, 0), 2291 }, 2292 CMIPCI_MIXER_SW_STEREO("PCM Capture Switch", CM_REG_MIXER1, CM_WAVEINL_SHIFT, CM_WAVEINR_SHIFT, 0), 2293 CMIPCI_SB_VOL_STEREO("Synth Playback Volume", SB_DSP4_SYNTH_DEV, 3, 31), 2294 CMIPCI_MIXER_SW_MONO("Synth Playback Switch", CM_REG_MIXER1, CM_FMMUTE_SHIFT, 1), 2295 CMIPCI_SB_INPUT_SW("Synth Capture Route", 6, 5), 2296 CMIPCI_SB_VOL_STEREO("CD Playback Volume", SB_DSP4_CD_DEV, 3, 31), 2297 CMIPCI_SB_SW_STEREO("CD Playback Switch", 2, 1), 2298 CMIPCI_SB_INPUT_SW("CD Capture Route", 2, 1), 2299 CMIPCI_SB_VOL_STEREO("Line Playback Volume", SB_DSP4_LINE_DEV, 3, 31), 2300 CMIPCI_SB_SW_STEREO("Line Playback Switch", 4, 3), 2301 CMIPCI_SB_INPUT_SW("Line Capture Route", 4, 3), 2302 CMIPCI_SB_VOL_MONO("Mic Playback Volume", SB_DSP4_MIC_DEV, 3, 31), 2303 CMIPCI_SB_SW_MONO("Mic Playback Switch", 0), 2304 CMIPCI_DOUBLE("Mic Capture Switch", SB_DSP4_INPUT_LEFT, SB_DSP4_INPUT_RIGHT, 0, 0, 1, 0, 0), 2305 CMIPCI_SB_VOL_MONO("PC Speaker Playback Volume", SB_DSP4_SPEAKER_DEV, 6, 3), 2306 CMIPCI_MIXER_VOL_STEREO("Aux Playback Volume", CM_REG_AUX_VOL, 4, 0, 15), 2307 CMIPCI_MIXER_SW_STEREO("Aux Playback Switch", CM_REG_MIXER2, CM_VAUXLM_SHIFT, CM_VAUXRM_SHIFT, 0), 2308 CMIPCI_MIXER_SW_STEREO("Aux Capture Switch", CM_REG_MIXER2, CM_RAUXLEN_SHIFT, CM_RAUXREN_SHIFT, 0), 2309 CMIPCI_MIXER_SW_MONO("Mic Boost Playback Switch", CM_REG_MIXER2, CM_MICGAINZ_SHIFT, 1), 2310 CMIPCI_MIXER_VOL_MONO("Mic Capture Volume", CM_REG_MIXER2, CM_VADMIC_SHIFT, 7), 2311 CMIPCI_SB_VOL_MONO("Phone Playback Volume", CM_REG_EXTENT_IND, 5, 7), 2312 CMIPCI_DOUBLE("Phone Playback Switch", CM_REG_EXTENT_IND, CM_REG_EXTENT_IND, 4, 4, 1, 0, 0), 2313 CMIPCI_DOUBLE("PC Speaker Playback Switch", CM_REG_EXTENT_IND, CM_REG_EXTENT_IND, 3, 3, 1, 0, 0), 2314 CMIPCI_DOUBLE("Mic Boost Capture Switch", CM_REG_EXTENT_IND, CM_REG_EXTENT_IND, 0, 0, 1, 0, 0), 2162 2315 }; 2163 2316 … … 2167 2320 2168 2321 struct cmipci_switch_args { 2169 2170 2171 2172 2173 unsigned int ac3_sensitive: 1;/* access forbidden during2174 2175 2322 int reg; /* register index */ 2323 unsigned int mask; /* mask bits */ 2324 unsigned int mask_on; /* mask bits to turn on */ 2325 unsigned int is_byte: 1; /* byte access? */ 2326 unsigned int ac3_sensitive: 1; /* access forbidden during 2327 * non-audio operation? 2328 */ 2176 2329 }; 2177 2330 2178 static int snd_cmipci_uswitch_info(struct snd_kcontrol *kcontrol, 2179 struct snd_ctl_elem_info *uinfo) 2180 { 2181 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN; 2182 uinfo->count = 1; 2183 uinfo->value.integer.min = 0; 2184 uinfo->value.integer.max = 1; 2185 return 0; 2186 } 2331 #define snd_cmipci_uswitch_info snd_ctl_boolean_mono_info 2187 2332 2188 2333 static int _snd_cmipci_uswitch_get(struct snd_kcontrol *kcontrol, 2189 2190 2191 { 2192 2193 2194 2195 2196 2197 2198 2199 2200 2201 2202 2203 2204 2205 2206 2207 2334 struct snd_ctl_elem_value *ucontrol, 2335 struct cmipci_switch_args *args) 2336 { 2337 unsigned int val; 2338 struct cmipci *cm = snd_kcontrol_chip(kcontrol); 2339 2340 spin_lock_irq(&cm->reg_lock); 2341 if (args->ac3_sensitive && cm->mixer_insensitive) { 2342 ucontrol->value.integer.value[0] = 0; 2343 spin_unlock_irq(&cm->reg_lock); 2344 return 0; 2345 } 2346 if (args->is_byte) 2347 val = inb(cm->iobase + args->reg); 2348 else 2349 val = snd_cmipci_read(cm, args->reg); 2350 ucontrol->value.integer.value[0] = ((val & args->mask) == args->mask_on) ? 1 : 0; 2351 spin_unlock_irq(&cm->reg_lock); 2352 return 0; 2208 2353 } 2209 2354 2210 2355 static int snd_cmipci_uswitch_get(struct snd_kcontrol *kcontrol, 2211 2212 { 2213 2214 2215 2216 2356 struct snd_ctl_elem_value *ucontrol) 2357 { 2358 struct cmipci_switch_args *args; 2359 args = (struct cmipci_switch_args *)kcontrol->private_value; 2360 snd_assert(args != NULL, return -EINVAL); 2361 return _snd_cmipci_uswitch_get(kcontrol, ucontrol, args); 2217 2362 } 2218 2363 2219 2364 static int _snd_cmipci_uswitch_put(struct snd_kcontrol *kcontrol, 2220 struct snd_ctl_elem_value *ucontrol, 2221 struct cmipci_switch_args *args) 2222 { 2223 unsigned int val; 2224 int change; 2225 struct cmipci *cm = snd_kcontrol_chip(kcontrol); 2226 2227 spin_lock_irq(&cm->reg_lock); 2228 if (args->ac3_sensitive && cm->mixer_insensitive) { 2229 /* ignored */ 2230 spin_unlock_irq(&cm->reg_lock); 2231 return 0; 2232 } 2233 if (args->is_byte) 2234 val = inb(cm->iobase + args->reg); 2235 else 2236 val = snd_cmipci_read(cm, args->reg); 2237 change = (val & args->mask) != (ucontrol->value.integer.value[0] ? args->mask : 0); 2238 if (change) { 2239 val &= ~args->mask; 2240 if (ucontrol->value.integer.value[0]) 2241 val |= args->mask_on; 2242 else 2243 val |= (args->mask & ~args->mask_on); 2244 if (args->is_byte) 2245 outb((unsigned char)val, cm->iobase + args->reg); 2246 else 2247 snd_cmipci_write(cm, args->reg, val); 2248 } 2249 spin_unlock_irq(&cm->reg_lock); 2250 return change; 2365 struct snd_ctl_elem_value *ucontrol, 2366 struct cmipci_switch_args *args) 2367 { 2368 unsigned int val; 2369 int change; 2370 struct cmipci *cm = snd_kcontrol_chip(kcontrol); 2371 2372 spin_lock_irq(&cm->reg_lock); 2373 if (args->ac3_sensitive && cm->mixer_insensitive) { 2374 /* ignored */ 2375 spin_unlock_irq(&cm->reg_lock); 2376 return 0; 2377 } 2378 if (args->is_byte) 2379 val = inb(cm->iobase + args->reg); 2380 else 2381 val = snd_cmipci_read(cm, args->reg); 2382 change = (val & args->mask) != (ucontrol->value.integer.value[0] ? 2383 args->mask_on : (args->mask & ~args->mask_on)); 2384 if (change) { 2385 val &= ~args->mask; 2386 if (ucontrol->value.integer.value[0]) 2387 val |= args->mask_on; 2388 else 2389 val |= (args->mask & ~args->mask_on); 2390 if (args->is_byte) 2391 outb((unsigned char)val, cm->iobase + args->reg); 2392 else 2393 snd_cmipci_write(cm, args->reg, val); 2394 } 2395 spin_unlock_irq(&cm->reg_lock); 2396 return change; 2251 2397 } 2252 2398 2253 2399 static int snd_cmipci_uswitch_put(struct snd_kcontrol *kcontrol, 2254 2255 { 2256 2257 2258 2259 2400 struct snd_ctl_elem_value *ucontrol) 2401 { 2402 struct cmipci_switch_args *args; 2403 args = (struct cmipci_switch_args *)kcontrol->private_value; 2404 snd_assert(args != NULL, return -EINVAL); 2405 return _snd_cmipci_uswitch_put(kcontrol, ucontrol, args); 2260 2406 } 2261 2407 2262 2408 #define DEFINE_SWITCH_ARG(sname, xreg, xmask, xmask_on, xis_byte, xac3) \ 2263 2264 2265 2266 2267 2268 2269 2270 2409 static struct cmipci_switch_args cmipci_switch_arg_##sname = { \ 2410 .reg = xreg, \ 2411 .mask = xmask, \ 2412 .mask_on = xmask_on, \ 2413 .is_byte = xis_byte, \ 2414 .ac3_sensitive = xac3, \ 2415 } 2416 2271 2417 #define DEFINE_BIT_SWITCH_ARG(sname, xreg, xmask, xis_byte, xac3) \ 2272 2418 DEFINE_SWITCH_ARG(sname, xreg, xmask, xmask, xis_byte, xac3) 2273 2419 2274 2420 #if 0 /* these will be controlled in pcm device */ … … 2296 2442 #endif 2297 2443 DEFINE_BIT_SWITCH_ARG(fourch, CM_REG_MISC_CTRL, CM_N4SPK3D, 0, 0); 2298 DEFINE_BIT_SWITCH_ARG(line_rear, CM_REG_MIXER1, CM_SPK4, 1, 0);2299 DEFINE_BIT_SWITCH_ARG(line_bass, CM_REG_LEGACY_CTRL, CM_LINE_AS_BASS, 0, 0);2300 DEFINE_BIT_SWITCH_ARG(joystick, CM_REG_FUNCTRL1, CM_JYSTK_EN, 0, 0); 2444 // DEFINE_BIT_SWITCH_ARG(line_rear, CM_REG_MIXER1, CM_REAR2LIN, 1, 0); 2445 // DEFINE_BIT_SWITCH_ARG(line_bass, CM_REG_LEGACY_CTRL, CM_CENTR2LIN|CM_BASE2LIN, 0, 0); 2446 // DEFINE_BIT_SWITCH_ARG(joystick, CM_REG_FUNCTRL1, CM_JYSTK_EN, 0, 0); /* now module option */ 2301 2447 DEFINE_SWITCH_ARG(modem, CM_REG_MISC_CTRL, CM_FLINKON|CM_FLINKOFF, CM_FLINKON, 0, 0); 2302 2448 2303 //Can't compile in non-KEE mode without extra pointer in structure2304 //(watcom complains it can't convert a far ptr to ulong even though it's2305 // safe to do so in this case)2306 2449 #define DEFINE_SWITCH(sname, stype, sarg) \ 2307 { stype, 0, 0, \ 2308 sname, 0, 0, 0, \ 2309 snd_cmipci_uswitch_info, \ 2310 snd_cmipci_uswitch_get, \ 2311 snd_cmipci_uswitch_put, \ 2312 0, \ 2313 (unsigned long)&cmipci_switch_arg_##sarg,\ 2314 } 2450 { .name = sname, \ 2451 .iface = stype, \ 2452 .info = snd_cmipci_uswitch_info, \ 2453 .get = snd_cmipci_uswitch_get, \ 2454 .put = snd_cmipci_uswitch_put, \ 2455 .private_value = (unsigned long)&cmipci_switch_arg_##sarg,\ 2456 } 2315 2457 2316 2458 #define DEFINE_CARD_SWITCH(sname, sarg) DEFINE_SWITCH(sname, SNDRV_CTL_ELEM_IFACE_CARD, sarg) … … 2323 2465 */ 2324 2466 static int snd_cmipci_spdout_enable_get(struct snd_kcontrol *kcontrol, 2325 2326 { 2327 2328 2329 2330 2467 struct snd_ctl_elem_value *ucontrol) 2468 { 2469 int changed; 2470 changed = _snd_cmipci_uswitch_get(kcontrol, ucontrol, &cmipci_switch_arg_spdif_enable); 2471 changed |= _snd_cmipci_uswitch_get(kcontrol, ucontrol, &cmipci_switch_arg_spdo2dac); 2472 return changed; 2331 2473 } 2332 2474 2333 2475 static int snd_cmipci_spdout_enable_put(struct snd_kcontrol *kcontrol, 2334 struct snd_ctl_elem_value *ucontrol) 2335 { 2336 struct cmipci *chip = snd_kcontrol_chip(kcontrol); 2337 int changed; 2338 changed = _snd_cmipci_uswitch_put(kcontrol, ucontrol, &cmipci_switch_arg_spdif_enable); 2339 changed |= _snd_cmipci_uswitch_put(kcontrol, ucontrol, &cmipci_switch_arg_spdo2dac); 2340 if (changed) { 2341 if (ucontrol->value.integer.value[0]) { 2342 if (chip->spdif_playback_avail) 2343 snd_cmipci_set_bit(chip, CM_REG_FUNCTRL1, CM_PLAYBACK_SPDF); 2344 } else { 2345 if (chip->spdif_playback_avail) 2346 snd_cmipci_clear_bit(chip, CM_REG_FUNCTRL1, CM_PLAYBACK_SPDF); 2347 } 2348 } 2349 chip->spdif_playback_enabled = ucontrol->value.integer.value[0]; 2350 return changed; 2351 } 2476 struct snd_ctl_elem_value *ucontrol) 2477 { 2478 struct cmipci *chip = snd_kcontrol_chip(kcontrol); 2479 int changed; 2480 changed = _snd_cmipci_uswitch_put(kcontrol, ucontrol, &cmipci_switch_arg_spdif_enable); 2481 changed |= _snd_cmipci_uswitch_put(kcontrol, ucontrol, &cmipci_switch_arg_spdo2dac); 2482 if (changed) { 2483 if (ucontrol->value.integer.value[0]) { 2484 if (chip->spdif_playback_avail) 2485 snd_cmipci_set_bit(chip, CM_REG_FUNCTRL1, CM_PLAYBACK_SPDF); 2486 } else { 2487 if (chip->spdif_playback_avail) 2488 snd_cmipci_clear_bit(chip, CM_REG_FUNCTRL1, CM_PLAYBACK_SPDF); 2489 } 2490 } 2491 chip->spdif_playback_enabled = ucontrol->value.integer.value[0]; 2492 return changed; 2493 } 2494 2352 2495 2353 2496 static int snd_cmipci_line_in_mode_info(struct snd_kcontrol *kcontrol, … … 2370 2513 if (cm->chip_version >= 39) { 2371 2514 val = snd_cmipci_read(cm, CM_REG_LEGACY_CTRL); 2372 if (val & CM_LINE_AS_BASS)2515 if (val & (CM_CENTR2LIN | CM_BASE2LIN)) 2373 2516 return 2; 2374 2517 } 2375 2518 val = snd_cmipci_read_b(cm, CM_REG_MIXER1); 2376 if (val & CM_ SPK4)2519 if (val & CM_REAR2LIN) 2377 2520 return 1; 2378 2521 return 0; … … 2398 2541 spin_lock_irq(&cm->reg_lock); 2399 2542 if (ucontrol->value.enumerated.item[0] == 2) 2400 change = snd_cmipci_set_bit(cm, CM_REG_LEGACY_CTRL, CM_ LINE_AS_BASS);2543 change = snd_cmipci_set_bit(cm, CM_REG_LEGACY_CTRL, CM_CENTR2LIN | CM_BASE2LIN); 2401 2544 else 2402 change = snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_ LINE_AS_BASS);2545 change = snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_CENTR2LIN | CM_BASE2LIN); 2403 2546 if (ucontrol->value.enumerated.item[0] == 1) 2404 change |= snd_cmipci_set_bit_b(cm, CM_REG_MIXER1, CM_ SPK4);2547 change |= snd_cmipci_set_bit_b(cm, CM_REG_MIXER1, CM_REAR2LIN); 2405 2548 else 2406 change |= snd_cmipci_clear_bit_b(cm, CM_REG_MIXER1, CM_ SPK4);2549 change |= snd_cmipci_clear_bit_b(cm, CM_REG_MIXER1, CM_REAR2LIN); 2407 2550 spin_unlock_irq(&cm->reg_lock); 2408 2551 return change; … … 2428 2571 /* same bit as spdi_phase */ 2429 2572 spin_lock_irq(&cm->reg_lock); 2430 ucontrol->value.enumerated.item[0] = 2573 ucontrol->value.enumerated.item[0] = 2431 2574 (snd_cmipci_read_b(cm, CM_REG_MISC) & CM_SPDIF_INVERSE) ? 1 : 0; 2432 2575 spin_unlock_irq(&cm->reg_lock); … … 2468 2611 static struct snd_kcontrol_new snd_cmipci_8738_mixer_switches[] __devinitdata = { 2469 2612 #if 0 /* controlled in pcm device */ 2470 2471 2472 2613 DEFINE_MIXER_SWITCH("IEC958 In Record", spdif_in), 2614 DEFINE_MIXER_SWITCH("IEC958 Out", spdif_out), 2615 DEFINE_MIXER_SWITCH("IEC958 Out To DAC", spdo2dac), 2473 2616 #endif 2474 // DEFINE_MIXER_SWITCH("IEC958 Output Switch", spdif_enable), 2475 { 2476 SNDRV_CTL_ELEM_IFACE_MIXER,0,0, 2477 "IEC958 Output Switch",0,0, 0, 2478 snd_cmipci_uswitch_info, 2479 snd_cmipci_spdout_enable_get, 2480 snd_cmipci_spdout_enable_put,0 2481 }, 2482 DEFINE_MIXER_SWITCH("IEC958 In Valid", spdi_valid), 2483 DEFINE_MIXER_SWITCH("IEC958 Copyright", spdif_copyright), 2484 DEFINE_MIXER_SWITCH("IEC958 5V", spdo_5v), 2485 // DEFINE_MIXER_SWITCH("IEC958 In/Out 48KHz", spdo_48k), 2486 DEFINE_MIXER_SWITCH("IEC958 Loop", spdif_loop), 2487 DEFINE_MIXER_SWITCH("IEC958 In Monitor", spdi_monitor), 2617 // DEFINE_MIXER_SWITCH("IEC958 Output Switch", spdif_enable), 2618 { .name = "IEC958 Output Switch", 2619 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, 2620 .info = snd_cmipci_uswitch_info, 2621 .get = snd_cmipci_spdout_enable_get, 2622 .put = snd_cmipci_spdout_enable_put, 2623 }, 2624 DEFINE_MIXER_SWITCH("IEC958 In Valid", spdi_valid), 2625 DEFINE_MIXER_SWITCH("IEC958 Copyright", spdif_copyright), 2626 DEFINE_MIXER_SWITCH("IEC958 5V", spdo_5v), 2627 // DEFINE_MIXER_SWITCH("IEC958 In/Out 48KHz", spdo_48k), 2628 DEFINE_MIXER_SWITCH("IEC958 Loop", spdif_loop), 2629 DEFINE_MIXER_SWITCH("IEC958 In Monitor", spdi_monitor), 2488 2630 }; 2489 2631 2490 2632 /* only for model 033/037 */ 2491 2633 static struct snd_kcontrol_new snd_cmipci_old_mixer_switches[] __devinitdata = { 2492 2493 2494 2634 DEFINE_MIXER_SWITCH("IEC958 Mix Analog", spdif_dac_out), 2635 DEFINE_MIXER_SWITCH("IEC958 In Phase Inverse", spdi_phase), 2636 DEFINE_MIXER_SWITCH("IEC958 In Select", spdif_in_sel1), 2495 2637 }; 2496 2638 … … 2509 2651 2510 2652 /* card control switches */ 2511 static struct snd_kcontrol_new snd_cmipci_control_switches[] __devinitdata = { 2512 DEFINE_CARD_SWITCH("Joystick", joystick), 2513 DEFINE_CARD_SWITCH("Modem", modem), 2514 }; 2653 static struct snd_kcontrol_new snd_cmipci_modem_switch __devinitdata = 2654 DEFINE_CARD_SWITCH("Modem", modem); 2655 2515 2656 2516 2657 static int __devinit snd_cmipci_mixer_new(struct cmipci *cm, int pcm_spdif_device) 2517 2658 { 2518 struct snd_card *card; 2519 struct snd_kcontrol_new *sw; 2520 struct snd_kcontrol *kctl; 2521 unsigned int idx; 2522 int err; 2523 2524 snd_assert(cm != NULL && cm->card != NULL, return -EINVAL); 2525 2526 card = cm->card; 2527 2528 strcpy(card->mixername, "CMedia PCI"); 2529 2530 spin_lock_irq(&cm->reg_lock); 2531 snd_cmipci_mixer_write(cm, 0x00, 0x00); /* mixer reset */ 2532 spin_unlock_irq(&cm->reg_lock); 2533 2534 for (idx = 0; idx < ARRAY_SIZE(snd_cmipci_mixers); idx++) { 2535 if (cm->chip_version == 68) { // 8768 has no PCM volume 2536 if (!strcmp(snd_cmipci_mixers[idx].name, 2537 "PCM Playback Volume")) 2538 continue; 2539 } 2540 if ((err = snd_ctl_add(card, snd_ctl_new1(&snd_cmipci_mixers[idx], cm))) < 0) 2541 return err; 2542 } 2543 2544 /* mixer switches */ 2545 sw = snd_cmipci_mixer_switches; 2546 for (idx = 0; idx < ARRAY_SIZE(snd_cmipci_mixer_switches); idx++, sw++) { 2547 err = snd_ctl_add(cm->card, snd_ctl_new1(sw, cm)); 2548 if (err < 0) 2549 return err; 2550 } 2551 if (! cm->can_multi_ch) { 2552 err = snd_ctl_add(cm->card, snd_ctl_new1(&snd_cmipci_nomulti_switch, cm)); 2553 if (err < 0) 2554 return err; 2555 } 2556 if (cm->device == PCI_DEVICE_ID_CMEDIA_CM8738 || 2557 cm->device == PCI_DEVICE_ID_CMEDIA_CM8738B) { 2558 sw = snd_cmipci_8738_mixer_switches; 2559 for (idx = 0; idx < ARRAY_SIZE(snd_cmipci_8738_mixer_switches); idx++, sw++) { 2560 err = snd_ctl_add(cm->card, snd_ctl_new1(sw, cm)); 2561 if (err < 0) 2562 return err; 2563 } 2564 if (cm->can_ac3_hw) { 2565 if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_cmipci_spdif_default, cm))) < 0) 2566 return err; 2567 kctl->id.device = pcm_spdif_device; 2568 if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_cmipci_spdif_mask, cm))) < 0) 2569 return err; 2570 kctl->id.device = pcm_spdif_device; 2571 if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_cmipci_spdif_stream, cm))) < 0) 2572 return err; 2573 kctl->id.device = pcm_spdif_device; 2574 } 2575 if (cm->chip_version <= 37) { 2576 sw = snd_cmipci_old_mixer_switches; 2577 for (idx = 0; idx < ARRAY_SIZE(snd_cmipci_old_mixer_switches); idx++, sw++) { 2578 err = snd_ctl_add(cm->card, snd_ctl_new1(sw, cm)); 2579 if (err < 0) 2580 return err; 2581 } 2582 } 2583 } 2584 if (cm->chip_version >= 39) { 2585 sw = snd_cmipci_extra_mixer_switches; 2586 for (idx = 0; idx < ARRAY_SIZE(snd_cmipci_extra_mixer_switches); idx++, sw++) { 2587 err = snd_ctl_add(cm->card, snd_ctl_new1(sw, cm)); 2588 if (err < 0) 2589 return err; 2590 } 2591 } 2592 2593 /* card switches */ 2594 sw = snd_cmipci_control_switches; 2595 for (idx = 0; idx < ARRAY_SIZE(snd_cmipci_control_switches); idx++, sw++) { 2596 err = snd_ctl_add(cm->card, snd_ctl_new1(sw, cm)); 2597 if (err < 0) 2598 return err; 2599 } 2600 2601 for (idx = 0; idx < CM_SAVED_MIXERS; idx++) { 2602 struct snd_ctl_elem_id id; 2603 struct snd_kcontrol *ctl; 2604 memset(&id, 0, sizeof(id)); 2605 id.iface = SNDRV_CTL_ELEM_IFACE_MIXER; 2606 strcpy(id.name, cm_saved_mixer[idx].name); 2607 if ((ctl = snd_ctl_find_id(cm->card, &id)) != NULL) 2608 cm->mixer_res_ctl[idx] = ctl; 2609 } 2610 2611 return 0; 2659 struct snd_card *card; 2660 struct snd_kcontrol_new *sw; 2661 struct snd_kcontrol *kctl; 2662 unsigned int idx; 2663 int err; 2664 2665 snd_assert(cm != NULL && cm->card != NULL, return -EINVAL); 2666 2667 card = cm->card; 2668 2669 strcpy(card->mixername, "CMedia PCI"); 2670 2671 spin_lock_irq(&cm->reg_lock); 2672 snd_cmipci_mixer_write(cm, 0x00, 0x00); /* mixer reset */ 2673 spin_unlock_irq(&cm->reg_lock); 2674 2675 for (idx = 0; idx < ARRAY_SIZE(snd_cmipci_mixers); idx++) { 2676 if (cm->chip_version == 68) { // 8768 has no PCM volume 2677 if (!strcmp(snd_cmipci_mixers[idx].name, 2678 "PCM Playback Volume")) 2679 continue; 2680 } 2681 if ((err = snd_ctl_add(card, snd_ctl_new1(&snd_cmipci_mixers[idx], cm))) < 0) 2682 return err; 2683 } 2684 2685 /* mixer switches */ 2686 sw = snd_cmipci_mixer_switches; 2687 for (idx = 0; idx < ARRAY_SIZE(snd_cmipci_mixer_switches); idx++, sw++) { 2688 err = snd_ctl_add(cm->card, snd_ctl_new1(sw, cm)); 2689 if (err < 0) 2690 return err; 2691 } 2692 if (! cm->can_multi_ch) { 2693 err = snd_ctl_add(cm->card, snd_ctl_new1(&snd_cmipci_nomulti_switch, cm)); 2694 if (err < 0) 2695 return err; 2696 } 2697 if (cm->device == PCI_DEVICE_ID_CMEDIA_CM8738 || 2698 cm->device == PCI_DEVICE_ID_CMEDIA_CM8738B) { 2699 sw = snd_cmipci_8738_mixer_switches; 2700 for (idx = 0; idx < ARRAY_SIZE(snd_cmipci_8738_mixer_switches); idx++, sw++) { 2701 err = snd_ctl_add(cm->card, snd_ctl_new1(sw, cm)); 2702 if (err < 0) 2703 return err; 2704 } 2705 if (cm->can_ac3_hw) { 2706 if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_cmipci_spdif_default, cm))) < 0) 2707 return err; 2708 kctl->id.device = pcm_spdif_device; 2709 if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_cmipci_spdif_mask, cm))) < 0) 2710 return err; 2711 kctl->id.device = pcm_spdif_device; 2712 if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_cmipci_spdif_stream, cm))) < 0) 2713 return err; 2714 kctl->id.device = pcm_spdif_device; 2715 } 2716 if (cm->chip_version <= 37) { 2717 sw = snd_cmipci_old_mixer_switches; 2718 for (idx = 0; idx < ARRAY_SIZE(snd_cmipci_old_mixer_switches); idx++, sw++) { 2719 err = snd_ctl_add(cm->card, snd_ctl_new1(sw, cm)); 2720 if (err < 0) 2721 return err; 2722 } 2723 } 2724 } 2725 if (cm->chip_version >= 39) { 2726 sw = snd_cmipci_extra_mixer_switches; 2727 for (idx = 0; idx < ARRAY_SIZE(snd_cmipci_extra_mixer_switches); idx++, sw++) { 2728 err = snd_ctl_add(cm->card, snd_ctl_new1(sw, cm)); 2729 if (err < 0) 2730 return err; 2731 } 2732 } 2733 2734 /* card switches */ 2735 /* 2736 * newer chips don't have the register bits to force modem link 2737 * detection; the bit that was FLINKON now mutes CH1 2738 */ 2739 if (cm->chip_version < 39) { 2740 err = snd_ctl_add(cm->card, 2741 snd_ctl_new1(&snd_cmipci_modem_switch, cm)); 2742 if (err < 0) 2743 return err; 2744 } 2745 2746 for (idx = 0; idx < CM_SAVED_MIXERS; idx++) { 2747 struct snd_ctl_elem_id id; 2748 struct snd_kcontrol *ctl; 2749 memset(&id, 0, sizeof(id)); 2750 id.iface = SNDRV_CTL_ELEM_IFACE_MIXER; 2751 strcpy(id.name, cm_saved_mixer[idx].name); 2752 if ((ctl = snd_ctl_find_id(cm->card, &id)) != NULL) 2753 cm->mixer_res_ctl[idx] = ctl; 2754 } 2755 2756 return 0; 2612 2757 } 2613 2758 … … 2617 2762 */ 2618 2763 2619 static void snd_cmipci_proc_read(struct snd_info_entry *entry, 2620 struct snd_info_buffer *buffer) 2621 { 2622 struct cmipci *cm = entry->private_data; 2623 int i;2624 2625 snd_iprintf(buffer, "%s\n\n", cm->card->longname); 2626 for (i = 0; i < 0x40; i++) { 2627 int v = inb(cm->iobase + i); 2628 if (i % 4 == 0)2629 snd_iprintf(buffer, "%02x: ", i);2630 snd_iprintf(buffer, "%02x", v);2631 if (i % 4 == 3)2632 snd_iprintf(buffer, "\n");2633 else 2634 snd_iprintf(buffer, " "); 2635 } 2764 #ifdef CONFIG_PROC_FS 2765 static void snd_cmipci_proc_read(struct snd_info_entry *entry, 2766 struct snd_info_buffer *buffer) 2767 { 2768 struct cmipci *cm = entry->private_data; 2769 int i, v; 2770 2771 snd_iprintf(buffer, "%s\n", cm->card->longname); 2772 for (i = 0; i < 0x94; i++) { 2773 if (i == 0x28) 2774 i = 0x90; 2775 v = inb(cm->iobase + i); 2776 if (i % 4 == 0) 2777 snd_iprintf(buffer, "\n%02x:", i); 2778 snd_iprintf(buffer, " %02x", v); 2779 } 2780 snd_iprintf(buffer, "\n"); 2636 2781 } 2637 2782 2638 2783 static void __devinit snd_cmipci_proc_init(struct cmipci *cm) 2639 2784 { 2640 struct snd_info_entry *entry; 2641 if (! snd_card_proc_new(cm->card, "cmipci", &entry)) 2642 snd_info_set_text_ops(entry, cm, 1024, snd_cmipci_proc_read); 2643 } 2644 2645 static struct pci_device_id snd_cmipci_ids[] __devinitdata = { 2646 {PCI_VENDOR_ID_CMEDIA, PCI_DEVICE_ID_CMEDIA_CM8338A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, 2647 {PCI_VENDOR_ID_CMEDIA, PCI_DEVICE_ID_CMEDIA_CM8338B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, 2648 {PCI_VENDOR_ID_CMEDIA, PCI_DEVICE_ID_CMEDIA_CM8738, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, 2649 {PCI_VENDOR_ID_CMEDIA, PCI_DEVICE_ID_CMEDIA_CM8738B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, 2650 {PCI_VENDOR_ID_AL, PCI_DEVICE_ID_CMEDIA_CM8738, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, 2651 {0,}, 2785 struct snd_info_entry *entry; 2786 2787 if (! snd_card_proc_new(cm->card, "cmipci", &entry)) 2788 snd_info_set_text_ops(entry, cm, snd_cmipci_proc_read); 2789 } 2790 #else /* !CONFIG_PROC_FS */ 2791 static inline void snd_cmipci_proc_init(struct cmipci *cm) {} 2792 #endif 2793 2794 2795 static struct pci_device_id snd_cmipci_ids[] = { 2796 {PCI_VENDOR_ID_CMEDIA, PCI_DEVICE_ID_CMEDIA_CM8338A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, 2797 {PCI_VENDOR_ID_CMEDIA, PCI_DEVICE_ID_CMEDIA_CM8338B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, 2798 {PCI_VENDOR_ID_CMEDIA, PCI_DEVICE_ID_CMEDIA_CM8738, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, 2799 {PCI_VENDOR_ID_CMEDIA, PCI_DEVICE_ID_CMEDIA_CM8738B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, 2800 {PCI_VENDOR_ID_AL, PCI_DEVICE_ID_CMEDIA_CM8738, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, 2801 {0,}, 2652 2802 }; 2653 2803 … … 2659 2809 static void __devinit query_chip(struct cmipci *cm) 2660 2810 { 2661 unsigned int detect; 2662 2663 /* check reg 0Ch, bit 24-31 */ 2664 detect = snd_cmipci_read(cm, CM_REG_INT_HLDCLR) & CM_CHIP_MASK2; 2665 if (! detect) { 2666 /* check reg 08h, bit 24-28 */ 2667 detect = snd_cmipci_read(cm, CM_REG_CHFORMAT) & CM_CHIP_MASK1; 2668 if (! detect) { 2669 cm->chip_version = 33; 2670 cm->max_channels = 4; 2671 if (cm->do_soft_ac3) 2672 cm->can_ac3_sw = 1; 2673 else 2674 cm->can_ac3_hw = 1; 2675 cm->has_dual_dac = 1; 2676 } else { 2677 // printk("detect = %x\n", detect); 2678 2679 cm->chip_version = 37; 2680 cm->max_channels = 4; 2681 cm->can_ac3_hw = 1; 2682 cm->has_dual_dac = 1; 2683 cm->can_multi_ch = 1; 2684 } 2685 } else { 2686 /* check reg 0Ch, bit 26 */ 2687 if (detect & CM_CHIP_8768) { 2688 cm->chip_version = 68; 2689 cm->max_channels = 8; 2690 cm->can_ac3_hw = 1; 2691 cm->has_dual_dac = 1; 2692 cm->can_multi_ch = 1; 2693 } else if (detect & CM_CHIP_055) { 2694 cm->chip_version = 55; 2695 cm->max_channels = 6; 2696 cm->can_ac3_hw = 1; 2697 cm->has_dual_dac = 1; 2698 cm->can_multi_ch = 1; 2699 } else if (detect & CM_CHIP_039) { 2700 cm->chip_version = 39; 2701 if (detect & CM_CHIP_039_6CH) /* 4 or 6 channels */ 2702 cm->max_channels = 6; 2703 else 2704 cm->max_channels = 4; 2705 cm->can_ac3_hw = 1; 2706 cm->has_dual_dac = 1; 2707 cm->can_multi_ch = 1; 2708 } else { 2709 printk(KERN_ERR "chip %x version not supported\n", detect); 2710 } 2711 } 2712 } 2811 unsigned int detect; 2812 2813 /* check reg 0Ch, bit 24-31 */ 2814 detect = snd_cmipci_read(cm, CM_REG_INT_HLDCLR) & CM_CHIP_MASK2; 2815 if (! detect) { 2816 /* check reg 08h, bit 24-28 */ 2817 detect = snd_cmipci_read(cm, CM_REG_CHFORMAT) & CM_CHIP_MASK1; 2818 switch (detect) { 2819 case 0: 2820 cm->chip_version = 33; 2821 if (cm->do_soft_ac3) 2822 cm->can_ac3_sw = 1; 2823 else 2824 cm->can_ac3_hw = 1; 2825 break; 2826 case CM_CHIP_037: 2827 cm->chip_version = 37; 2828 cm->can_ac3_hw = 1; 2829 break; 2830 default: 2831 cm->chip_version = 39; 2832 cm->can_ac3_hw = 1; 2833 break; 2834 } 2835 cm->max_channels = 2; 2836 } else { 2837 if (detect & CM_CHIP_039) { 2838 cm->chip_version = 39; 2839 if (detect & CM_CHIP_039_6CH) /* 4 or 6 channels */ 2840 cm->max_channels = 6; 2841 else 2842 cm->max_channels = 4; 2843 } else if (detect & CM_CHIP_8768) { 2844 cm->chip_version = 68; 2845 cm->max_channels = 8; 2846 cm->can_96k = 1; 2847 } else { 2848 cm->chip_version = 55; 2849 cm->max_channels = 6; 2850 cm->can_96k = 1; 2851 } 2852 cm->can_ac3_hw = 1; 2853 cm->can_multi_ch = 1; 2854 } 2855 } 2856 2857 #ifdef SUPPORT_JOYSTICK 2858 static int __devinit snd_cmipci_create_gameport(struct cmipci *cm, int dev) 2859 { 2860 static int ports[] = { 0x201, 0x200, 0 }; /* FIXME: majority is 0x201? */ 2861 struct gameport *gp; 2862 struct resource *r = NULL; 2863 int i, io_port = 0; 2864 2865 if (joystick_port[dev] == 0) 2866 return -ENODEV; 2867 2868 if (joystick_port[dev] == 1) { /* auto-detect */ 2869 for (i = 0; ports[i]; i++) { 2870 io_port = ports[i]; 2871 r = request_region(io_port, 1, "CMIPCI gameport"); 2872 if (r) 2873 break; 2874 } 2875 } else { 2876 io_port = joystick_port[dev]; 2877 r = request_region(io_port, 1, "CMIPCI gameport"); 2878 } 2879 2880 if (!r) { 2881 printk(KERN_WARNING "cmipci: cannot reserve joystick ports\n"); 2882 return -EBUSY; 2883 } 2884 2885 cm->gameport = gp = gameport_allocate_port(); 2886 if (!gp) { 2887 printk(KERN_ERR "cmipci: cannot allocate memory for gameport\n"); 2888 release_and_free_resource(r); 2889 return -ENOMEM; 2890 } 2891 gameport_set_name(gp, "C-Media Gameport"); 2892 gameport_set_phys(gp, "pci%s/gameport0", pci_name(cm->pci)); 2893 gameport_set_dev_parent(gp, &cm->pci->dev); 2894 gp->io = io_port; 2895 gameport_set_port_data(gp, r); 2896 2897 snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_JYSTK_EN); 2898 2899 gameport_register_port(cm->gameport); 2900 2901 return 0; 2902 } 2903 2904 static void snd_cmipci_free_gameport(struct cmipci *cm) 2905 { 2906 if (cm->gameport) { 2907 struct resource *r = gameport_get_port_data(cm->gameport); 2908 2909 gameport_unregister_port(cm->gameport); 2910 cm->gameport = NULL; 2911 2912 snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_JYSTK_EN); 2913 release_and_free_resource(r); 2914 } 2915 } 2916 #else 2917 static inline int snd_cmipci_create_gameport(struct cmipci *cm, int dev) { return -ENOSYS; } 2918 static inline void snd_cmipci_free_gameport(struct cmipci *cm) { } 2919 #endif 2713 2920 2714 2921 static int snd_cmipci_free(struct cmipci *cm) 2715 2922 { 2716 if (cm->irq >= 0) { 2717 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_FM_EN); 2718 snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_ENSPDOUT); 2719 snd_cmipci_write(cm, CM_REG_INT_HLDCLR, 0); /* disable ints */ 2720 snd_cmipci_ch_reset(cm, CM_CH_PLAY); 2721 snd_cmipci_ch_reset(cm, CM_CH_CAPT); 2722 snd_cmipci_write(cm, CM_REG_FUNCTRL0, 0); /* disable channels */ 2723 snd_cmipci_write(cm, CM_REG_FUNCTRL1, 0); 2724 2725 /* reset mixer */ 2726 snd_cmipci_mixer_write(cm, 0, 0); 2727 2728 synchronize_irq(cm->irq); 2729 2730 free_irq(cm->irq, cm); 2731 } 2732 pci_release_regions(cm->pci); 2733 kfree(cm); 2734 return 0; 2923 if (cm->irq >= 0) { 2924 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_FM_EN); 2925 snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_ENSPDOUT); 2926 snd_cmipci_write(cm, CM_REG_INT_HLDCLR, 0); /* disable ints */ 2927 snd_cmipci_ch_reset(cm, CM_CH_PLAY); 2928 snd_cmipci_ch_reset(cm, CM_CH_CAPT); 2929 snd_cmipci_write(cm, CM_REG_FUNCTRL0, 0); /* disable channels */ 2930 snd_cmipci_write(cm, CM_REG_FUNCTRL1, 0); 2931 2932 /* reset mixer */ 2933 snd_cmipci_mixer_write(cm, 0, 0); 2934 2935 synchronize_irq(cm->irq); 2936 2937 free_irq(cm->irq, cm); 2938 } 2939 2940 snd_cmipci_free_gameport(cm); 2941 pci_release_regions(cm->pci); 2942 pci_disable_device(cm->pci); 2943 kfree(cm); 2944 return 0; 2735 2945 } 2736 2946 2737 2947 static int snd_cmipci_dev_free(struct snd_device *device) 2738 2948 { 2739 2740 2949 struct cmipci *cm = device->device_data; 2950 return snd_cmipci_free(cm); 2741 2951 } 2742 2952 2743 2953 static int __devinit snd_cmipci_create_fm(struct cmipci *cm, long fm_port) 2744 2954 { 2745 long iosynth; 2746 unsigned int val; 2747 struct snd_opl3 *opl3; 2748 int err; 2749 2750 /* first try FM regs in PCI port range */ 2751 iosynth = cm->iobase + CM_REG_FM_PCI; 2752 err = snd_opl3_create(cm->card, iosynth, iosynth + 2, 2753 OPL3_HW_OPL3, 1, &opl3); 2754 if (err < 0) { 2755 /* then try legacy ports */ 2756 val = snd_cmipci_read(cm, CM_REG_LEGACY_CTRL) & ~CM_FMSEL_MASK; 2757 iosynth = fm_port; 2758 switch (iosynth) { 2759 case 0x3E8: val |= CM_FMSEL_3E8; break; 2760 case 0x3E0: val |= CM_FMSEL_3E0; break; 2761 case 0x3C8: val |= CM_FMSEL_3C8; break; 2762 case 0x388: val |= CM_FMSEL_388; break; 2763 default: 2764 return 0; 2765 } 2766 snd_cmipci_write(cm, CM_REG_LEGACY_CTRL, val); 2767 /* enable FM */ 2768 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_FM_EN); 2769 2770 if (snd_opl3_create(cm->card, iosynth, iosynth + 2, 2771 OPL3_HW_OPL3, 0, &opl3) < 0) { 2772 printk(KERN_ERR "cmipci: no OPL device at %#lx, " 2773 "skipping...\n", iosynth); 2774 /* disable FM */ 2775 snd_cmipci_write(cm, CM_REG_LEGACY_CTRL, 2776 val & ~CM_FMSEL_MASK); 2777 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_FM_EN); 2778 return 0; 2779 } 2780 } 2781 if ((err = snd_opl3_hwdep_new(opl3, 0, 1, NULL)) < 0) { 2782 printk(KERN_ERR "cmipci: cannot create OPL3 hwdep\n"); 2783 return err; 2784 } 2785 return 0; 2955 long iosynth; 2956 unsigned int val; 2957 struct snd_opl3 *opl3; 2958 int err; 2959 2960 if (!fm_port) 2961 goto disable_fm; 2962 2963 if (cm->chip_version >= 39) { 2964 /* first try FM regs in PCI port range */ 2965 iosynth = cm->iobase + CM_REG_FM_PCI; 2966 err = snd_opl3_create(cm->card, iosynth, iosynth + 2, 2967 OPL3_HW_OPL3, 1, &opl3); 2968 } else { 2969 err = -EIO; 2970 } 2971 if (err < 0) { 2972 /* then try legacy ports */ 2973 val = snd_cmipci_read(cm, CM_REG_LEGACY_CTRL) & ~CM_FMSEL_MASK; 2974 iosynth = fm_port; 2975 switch (iosynth) { 2976 case 0x3E8: val |= CM_FMSEL_3E8; break; 2977 case 0x3E0: val |= CM_FMSEL_3E0; break; 2978 case 0x3C8: val |= CM_FMSEL_3C8; break; 2979 case 0x388: val |= CM_FMSEL_388; break; 2980 default: 2981 goto disable_fm; 2982 } 2983 snd_cmipci_write(cm, CM_REG_LEGACY_CTRL, val); 2984 /* enable FM */ 2985 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_FM_EN); 2986 2987 if (snd_opl3_create(cm->card, iosynth, iosynth + 2, 2988 OPL3_HW_OPL3, 0, &opl3) < 0) { 2989 printk(KERN_ERR "cmipci: no OPL device at %#lx, " 2990 "skipping...\n", iosynth); 2991 goto disable_fm; 2992 } 2993 } 2994 if ((err = snd_opl3_hwdep_new(opl3, 0, 1, NULL)) < 0) { 2995 printk(KERN_ERR "cmipci: cannot create OPL3 hwdep\n"); 2996 return err; 2997 } 2998 return 0; 2999 3000 disable_fm: 3001 snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_FMSEL_MASK); 3002 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_FM_EN); 3003 return 0; 2786 3004 } 2787 3005 2788 3006 static int __devinit snd_cmipci_create(struct snd_card *card, struct pci_dev *pci, 2789 int dev, struct cmipci **rcmipci) 2790 { 2791 struct cmipci *cm; 2792 int err; 2793 static struct snd_device_ops ops = { 2794 .dev_free = snd_cmipci_dev_free, 2795 }; 2796 unsigned int val = 0; 2797 unsigned long iomidi; 2798 int integrated_midi; 2799 int pcm_index, pcm_spdif_index; 2800 2801 *rcmipci = NULL; 2802 2803 if ((err = pci_enable_device(pci)) < 0) 2804 return err; 2805 2806 cm = kcalloc(1, sizeof(*cm), GFP_KERNEL); 2807 if (cm == NULL) 2808 return -ENOMEM; 2809 2810 spin_lock_init(&cm->reg_lock); 2811 init_MUTEX(&cm->open_mutex); 2812 cm->device = pci->device; 2813 cm->card = card; 2814 cm->pci = pci; 2815 cm->irq = -1; 2816 cm->channel[0].ch = 0; 2817 cm->channel[1].ch = 1; 2818 cm->channel[0].is_dac = cm->channel[1].is_dac = 1; /* dual DAC mode */ 2819 2820 if ((err = pci_request_regions(pci, card->driver)) < 0) { 2821 kfree(cm); 2822 return err; 2823 } 2824 cm->iobase = pci_resource_start(pci, 0); 2825 if (request_irq(pci->irq, snd_cmipci_interrupt, SA_INTERRUPT|SA_SHIRQ, card->driver, cm)) { 2826 snd_printk("unable to grab IRQ %d\n", pci->irq); 2827 err = -EBUSY; 2828 goto __error; 2829 } 2830 cm->irq = pci->irq; 2831 2832 pci_set_master(cm->pci); 2833 2834 /* 2835 * check chip version, max channels and capabilities 2836 */ 2837 2838 cm->chip_version = 0; 2839 cm->max_channels = 2; 2840 cm->do_soft_ac3 = soft_ac3[dev]; 2841 if (pci->device != PCI_DEVICE_ID_CMEDIA_CM8338A && 2842 pci->device != PCI_DEVICE_ID_CMEDIA_CM8338B) 2843 query_chip(cm); 2844 /* added -MCx suffix for chip supporting multi-channels */ 2845 if (cm->can_multi_ch) 2846 sprintf(cm->card->driver + strlen(cm->card->driver), 2847 "-MC%d", cm->max_channels); 2848 else if (cm->can_ac3_sw) 2849 strcpy(cm->card->driver + strlen(cm->card->driver), "-SWIEC"); 2850 cm->dig_status = SNDRV_PCM_DEFAULT_CON_SPDIF; 2851 cm->dig_pcm_status = SNDRV_PCM_DEFAULT_CON_SPDIF; 3007 int dev, struct cmipci **rcmipci) 3008 { 3009 struct cmipci *cm; 3010 int err; 3011 static struct snd_device_ops ops = { 3012 .dev_free = snd_cmipci_dev_free, 3013 }; 3014 unsigned int val; 3015 long iomidi; 3016 int integrated_midi = 0; 3017 char modelstr[16]; 3018 int pcm_index, pcm_spdif_index; 3019 static struct pci_device_id intel_82437vx[] = { 3020 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437VX) }, 3021 {0}, 3022 }; 3023 3024 *rcmipci = NULL; 3025 3026 if ((err = pci_enable_device(pci)) < 0) 3027 return err; 3028 3029 cm = kzalloc(sizeof(*cm), GFP_KERNEL); 3030 if (cm == NULL) { 3031 pci_disable_device(pci); 3032 return -ENOMEM; 3033 } 3034 3035 spin_lock_init(&cm->reg_lock); 3036 mutex_init(&cm->open_mutex); 3037 cm->device = pci->device; 3038 cm->card = card; 3039 cm->pci = pci; 3040 cm->irq = -1; 3041 cm->channel[0].ch = 0; 3042 cm->channel[1].ch = 1; 3043 cm->channel[0].is_dac = cm->channel[1].is_dac = 1; /* dual DAC mode */ 3044 3045 if ((err = pci_request_regions(pci, card->driver)) < 0) { 3046 kfree(cm); 3047 pci_disable_device(pci); 3048 return err; 3049 } 3050 cm->iobase = pci_resource_start(pci, 0); 3051 3052 if (request_irq(pci->irq, snd_cmipci_interrupt, 3053 IRQF_SHARED, card->driver, cm)) { 3054 snd_printk(KERN_ERR "unable to grab IRQ %d\n", pci->irq); 3055 snd_cmipci_free(cm); 3056 return -EBUSY; 3057 } 3058 cm->irq = pci->irq; 3059 3060 pci_set_master(cm->pci); 3061 3062 /* 3063 * check chip version, max channels and capabilities 3064 */ 3065 3066 cm->chip_version = 0; 3067 cm->max_channels = 2; 3068 cm->do_soft_ac3 = soft_ac3[dev]; 3069 3070 if (pci->device != PCI_DEVICE_ID_CMEDIA_CM8338A && 3071 pci->device != PCI_DEVICE_ID_CMEDIA_CM8338B) 3072 query_chip(cm); 3073 /* added -MCx suffix for chip supporting multi-channels */ 3074 if (cm->can_multi_ch) 3075 sprintf(cm->card->driver + strlen(cm->card->driver), 3076 "-MC%d", cm->max_channels); 3077 else if (cm->can_ac3_sw) 3078 strcpy(cm->card->driver + strlen(cm->card->driver), "-SWIEC"); 3079 3080 cm->dig_status = SNDRV_PCM_DEFAULT_CON_SPDIF; 3081 cm->dig_pcm_status = SNDRV_PCM_DEFAULT_CON_SPDIF; 2852 3082 2853 3083 #if CM_CH_PLAY == 1 2854 3084 cm->ctrl = CM_CHADC0; /* default FUNCNTRL0 */ 2855 3085 #else 2856 3086 cm->ctrl = CM_CHADC1; /* default FUNCNTRL0 */ 2857 3087 #endif 2858 3088 2859 /* initialize codec registers */ 2860 snd_cmipci_write(cm, CM_REG_INT_HLDCLR, 0); /* disable ints */ 2861 snd_cmipci_ch_reset(cm, CM_CH_PLAY); 2862 snd_cmipci_ch_reset(cm, CM_CH_CAPT); 2863 snd_cmipci_write(cm, CM_REG_FUNCTRL0, 0); /* disable channels */ 2864 snd_cmipci_write(cm, CM_REG_FUNCTRL1, 0); 2865 2866 snd_cmipci_write(cm, CM_REG_CHFORMAT, 0); 2867 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_ENDBDAC|CM_N4SPK3D); 3089 /* initialize codec registers */ 3090 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_RESET); 3091 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_RESET); 3092 snd_cmipci_write(cm, CM_REG_INT_HLDCLR, 0); /* disable ints */ 3093 snd_cmipci_ch_reset(cm, CM_CH_PLAY); 3094 snd_cmipci_ch_reset(cm, CM_CH_CAPT); 3095 snd_cmipci_write(cm, CM_REG_FUNCTRL0, 0); /* disable channels */ 3096 snd_cmipci_write(cm, CM_REG_FUNCTRL1, 0); 3097 3098 snd_cmipci_write(cm, CM_REG_CHFORMAT, 0); 3099 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_ENDBDAC|CM_N4SPK3D); 2868 3100 #if CM_CH_PLAY == 1 2869 3101 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_XCHGDAC); 2870 3102 #else 2871 3103 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_XCHGDAC); 2872 3104 #endif 2873 /* Set Bus Master Request */ 2874 snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_BREQ); 2875 2876 /* Assume TX and compatible chip set (Autodetection required for VX chip sets) */ 2877 switch (pci->device) { 2878 case PCI_DEVICE_ID_CMEDIA_CM8738: 2879 case PCI_DEVICE_ID_CMEDIA_CM8738B: 2880 /* PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437VX */ 2881 if (! pci_find_device(0x8086, 0x7030, NULL)) 2882 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_TXVX); 2883 break; 2884 default: 2885 break; 2886 } 2887 2888 integrated_midi = snd_cmipci_read_b(cm, CM_REG_MPU_PCI) != 0xff; 2889 if (integrated_midi) 2890 iomidi = cm->iobase + CM_REG_MPU_PCI; 2891 else { 2892 iomidi = mpu_port[dev]; 2893 switch (iomidi) { 2894 case 0x320: val = CM_VMPU_320; break; 2895 case 0x310: val = CM_VMPU_310; break; 2896 case 0x300: val = CM_VMPU_300; break; 2897 case 0x330: val = CM_VMPU_330; break; 2898 default: 2899 iomidi = 0; break; 2900 } 2901 if (iomidi > 0) { 2902 snd_cmipci_write(cm, CM_REG_LEGACY_CTRL, val); 2903 /* enable UART */ 2904 snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_UART_EN); 2905 } 2906 } 2907 2908 if ((err = snd_cmipci_create_fm(cm, fm_port[dev])) < 0) 2909 return err; 2910 2911 /* reset mixer */ 2912 snd_cmipci_mixer_write(cm, 0, 0); 2913 2914 snd_cmipci_proc_init(cm); 2915 2916 /* create pcm devices */ 2917 pcm_index = pcm_spdif_index = 0; 2918 #ifdef SIX_CH_HACK 2919 if (cm->has_dual_dac) { 2920 if ((err = snd_cmipci_pcm2_new(cm, pcm_index)) < 0) 2921 goto __error; 2922 pcm_index++; 2923 } 2924 2925 if ((err = snd_cmipci_pcm_new(cm, pcm_index)) < 0) 2926 goto __error; 2927 pcm_index++; 2928 #else 2929 if ((err = snd_cmipci_pcm_new(cm, pcm_index)) < 0) 2930 goto __error; 2931 pcm_index++; 2932 2933 if (cm->has_dual_dac) { 2934 if ((err = snd_cmipci_pcm2_new(cm, pcm_index)) < 0) 2935 goto __error; 2936 pcm_index++; 2937 } 2938 #endif 2939 if (cm->can_ac3_hw || cm->can_ac3_sw) { 2940 pcm_spdif_index = pcm_index; 2941 if ((err = snd_cmipci_pcm_spdif_new(cm, pcm_index)) < 0) 2942 goto __error; 2943 } 2944 2945 /* create mixer interface & switches */ 2946 if ((err = snd_cmipci_mixer_new(cm, pcm_spdif_index)) < 0) 2947 goto __error; 2948 2949 if (iomidi > 0) { 2950 if ((err = snd_mpu401_uart_new(card, 0, MPU401_HW_CMIPCI, 2951 iomidi, 2952 (integrated_midi ? 2953 MPU401_INFO_INTEGRATED : 0), 2954 cm->irq, 0, &cm->rmidi)) < 0) { 2955 printk(KERN_ERR "cmipci: no UART401 device at 0x%lx\n", iomidi); 2956 } 2957 } 2958 2959 if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, cm, &ops)) < 0) { 2960 snd_cmipci_free(cm); 2961 return err; 2962 } 3105 if (cm->chip_version) { 3106 snd_cmipci_write_b(cm, CM_REG_EXT_MISC, 0x20); /* magic */ 3107 snd_cmipci_write_b(cm, CM_REG_EXT_MISC + 1, 0x09); /* more magic */ 3108 } 3109 /* Set Bus Master Request */ 3110 snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_BREQ); 3111 3112 /* Assume TX and compatible chip set (Autodetection required for VX chip sets) */ 3113 switch (pci->device) { 3114 case PCI_DEVICE_ID_CMEDIA_CM8738: 3115 case PCI_DEVICE_ID_CMEDIA_CM8738B: 3116 if (!pci_dev_present(intel_82437vx)) 3117 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_TXVX); 3118 break; 3119 default: 3120 break; 3121 } 3122 3123 if (cm->chip_version < 68) { 3124 val = pci->device < 0x110 ? 8338 : 8738; 3125 } else { 3126 switch (snd_cmipci_read_b(cm, CM_REG_INT_HLDCLR + 3) & 0x03) { 3127 case 0: 3128 val = 8769; 3129 break; 3130 case 2: 3131 val = 8762; 3132 break; 3133 default: 3134 switch ((pci->subsystem_vendor << 16) | 3135 pci->subsystem_device) { 3136 case 0x13f69761: 3137 case 0x584d3741: 3138 case 0x584d3751: 3139 case 0x584d3761: 3140 case 0x584d3771: 3141 case 0x72848384: 3142 val = 8770; 3143 break; 3144 default: 3145 val = 8768; 3146 break; 3147 } 3148 } 3149 } 3150 sprintf(card->shortname, "C-Media CMI%d", val); 3151 if (cm->chip_version < 68) 3152 sprintf(modelstr, " (model %d)", cm->chip_version); 3153 else 3154 modelstr[0] = '\0'; 3155 sprintf(card->longname, "%s%s at %#lx, irq %i", 3156 card->shortname, modelstr, cm->iobase, cm->irq); 3157 3158 if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, cm, &ops)) < 0) { 3159 snd_cmipci_free(cm); 3160 return err; 3161 } 3162 3163 if (cm->chip_version >= 39) { 3164 val = snd_cmipci_read_b(cm, CM_REG_MPU_PCI + 1); 3165 if (val != 0x00 && val != 0xff) { 3166 iomidi = cm->iobase + CM_REG_MPU_PCI; 3167 integrated_midi = 1; 3168 } 3169 } 3170 if (!integrated_midi) { 3171 val = 0; 3172 iomidi = mpu_port[dev]; 3173 switch (iomidi) { 3174 case 0x320: val = CM_VMPU_320; break; 3175 case 0x310: val = CM_VMPU_310; break; 3176 case 0x300: val = CM_VMPU_300; break; 3177 case 0x330: val = CM_VMPU_330; break; 3178 default: 3179 iomidi = 0; break; 3180 } 3181 if (iomidi > 0) { 3182 snd_cmipci_write(cm, CM_REG_LEGACY_CTRL, val); 3183 /* enable UART */ 3184 snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_UART_EN); 3185 if (inb(iomidi + 1) == 0xff) { 3186 snd_printk(KERN_ERR "cannot enable MPU-401 port" 3187 " at %#lx\n", iomidi); 3188 snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, 3189 CM_UART_EN); 3190 iomidi = 0; 3191 } 3192 } 3193 } 3194 3195 if (cm->chip_version < 68) { 3196 err = snd_cmipci_create_fm(cm, fm_port[dev]); 3197 if (err < 0) 3198 return err; 3199 } 3200 3201 /* reset mixer */ 3202 snd_cmipci_mixer_write(cm, 0, 0); 3203 3204 snd_cmipci_proc_init(cm); 3205 3206 /* create pcm devices */ 3207 pcm_index = pcm_spdif_index = 0; 3208 if ((err = snd_cmipci_pcm_new(cm, pcm_index)) < 0) 3209 return err; 3210 pcm_index++; 3211 if ((err = snd_cmipci_pcm2_new(cm, pcm_index)) < 0) 3212 return err; 3213 pcm_index++; 3214 if (cm->can_ac3_hw || cm->can_ac3_sw) { 3215 pcm_spdif_index = pcm_index; 3216 if ((err = snd_cmipci_pcm_spdif_new(cm, pcm_index)) < 0) 3217 return err; 3218 } 3219 3220 /* create mixer interface & switches */ 3221 if ((err = snd_cmipci_mixer_new(cm, pcm_spdif_index)) < 0) 3222 return err; 3223 3224 if (iomidi > 0) { 3225 if ((err = snd_mpu401_uart_new(card, 0, MPU401_HW_CMIPCI, 3226 iomidi, 3227 (integrated_midi ? 3228 MPU401_INFO_INTEGRATED : 0), 3229 cm->irq, 0, &cm->rmidi)) < 0) { 3230 printk(KERN_ERR "cmipci: no UART401 device at 0x%lx\n", iomidi); 3231 } 3232 } 3233 2963 3234 #ifdef USE_VAR48KRATE 2964 2965 2966 2967 2968 2969 2970 3235 for (val = 0; val < ARRAY_SIZE(rates); val++) 3236 snd_cmipci_set_pll(cm, rates[val], val); 3237 3238 /* 3239 * (Re-)Enable external switch spdo_48k 3240 */ 3241 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_SPDIF48K|CM_SPDF_AC97); 2971 3242 #endif /* USE_VAR48KRATE */ 2972 3243 2973 *rcmipci = cm; 2974 return 0; 2975 2976 __error: 2977 snd_cmipci_free(cm); 2978 return err; 3244 if (snd_cmipci_create_gameport(cm, dev) < 0) 3245 snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_JYSTK_EN); 3246 3247 snd_card_set_dev(card, &pci->dev); 3248 3249 *rcmipci = cm; 3250 return 0; 2979 3251 } 2980 3252 … … 2985 3257 2986 3258 static int __devinit snd_cmipci_probe(struct pci_dev *pci, 2987 const struct pci_device_id *pci_id) 2988 { 2989 static int dev; 2990 struct snd_card *card; 2991 struct cmipci *cm; 2992 int err; 2993 #ifdef DEBUG 2994 dprintf(("snd_cmipci_probe")); 2995 #endif 2996 if (dev >= SNDRV_CARDS) 2997 return -ENODEV; 2998 if (! enable[dev]) { 2999 dev++; 3000 return -ENOENT; 3001 } 3002 3003 card = snd_card_new(index[dev], id[dev], THIS_MODULE, 0); 3004 if (card == NULL) 3005 return -ENOMEM; 3006 3007 switch (pci->device) { 3008 case PCI_DEVICE_ID_CMEDIA_CM8738: 3009 case PCI_DEVICE_ID_CMEDIA_CM8738B: 3010 strcpy(card->driver, "CMI8738"); 3011 break; 3012 case PCI_DEVICE_ID_CMEDIA_CM8338A: 3013 case PCI_DEVICE_ID_CMEDIA_CM8338B: 3014 strcpy(card->driver, "CMI8338"); 3015 break; 3016 default: 3017 strcpy(card->driver, "CMIPCI"); 3018 break; 3019 } 3020 3021 if ((err = snd_cmipci_create(card, pci, dev, &cm)) < 0) { 3022 snd_card_free(card); 3023 return err; 3024 } 3025 card->private_data = cm; 3026 3027 sprintf(card->shortname, "C-Media PCI %s", card->driver); 3028 sprintf(card->longname, "%s (model %d) at 0x%lx, irq %i", 3029 card->shortname, 3030 cm->chip_version, 3031 cm->iobase, 3032 cm->irq); 3033 3034 3035 #ifdef DEBUG 3036 dprintf(("%s is detected\n", card->longname)); 3037 #endif 3038 3039 if ((err = snd_card_register(card)) < 0) { 3040 snd_card_free(card); 3041 return err; 3042 } 3043 3044 pci_set_drvdata(pci, card); 3045 dev++; 3046 3047 return 0; 3259 const struct pci_device_id *pci_id) 3260 { 3261 static int dev; 3262 struct snd_card *card; 3263 struct cmipci *cm; 3264 int err; 3265 3266 if (dev >= SNDRV_CARDS) 3267 return -ENODEV; 3268 if (! enable[dev]) { 3269 dev++; 3270 return -ENOENT; 3271 } 3272 3273 card = snd_card_new(index[dev], id[dev], THIS_MODULE, 0); 3274 if (card == NULL) 3275 return -ENOMEM; 3276 3277 switch (pci->device) { 3278 case PCI_DEVICE_ID_CMEDIA_CM8738: 3279 case PCI_DEVICE_ID_CMEDIA_CM8738B: 3280 strcpy(card->driver, "CMI8738"); 3281 break; 3282 case PCI_DEVICE_ID_CMEDIA_CM8338A: 3283 case PCI_DEVICE_ID_CMEDIA_CM8338B: 3284 strcpy(card->driver, "CMI8338"); 3285 break; 3286 default: 3287 strcpy(card->driver, "CMIPCI"); 3288 break; 3289 } 3290 3291 if ((err = snd_cmipci_create(card, pci, dev, &cm)) < 0) { 3292 snd_card_free(card); 3293 return err; 3294 } 3295 card->private_data = cm; 3296 3297 if ((err = snd_card_register(card)) < 0) { 3298 snd_card_free(card); 3299 return err; 3300 } 3301 pci_set_drvdata(pci, card); 3302 dev++; 3303 return 0; 3048 3304 3049 3305 } … … 3051 3307 static void __devexit snd_cmipci_remove(struct pci_dev *pci) 3052 3308 { 3053 snd_card_free(pci_get_drvdata(pci)); 3054 pci_set_drvdata(pci, NULL); 3055 } 3309 snd_card_free(pci_get_drvdata(pci)); 3310 pci_set_drvdata(pci, NULL); 3311 } 3312 3056 3313 3057 3314 #ifdef CONFIG_PM … … 3060 3317 */ 3061 3318 static unsigned char saved_regs[] = { 3062 3063 3064 3065 3066 3319 CM_REG_FUNCTRL1, CM_REG_CHFORMAT, CM_REG_LEGACY_CTRL, CM_REG_MISC_CTRL, 3320 CM_REG_MIXER0, CM_REG_MIXER1, CM_REG_MIXER2, CM_REG_MIXER3, CM_REG_PLL, 3321 CM_REG_CH0_FRAME1, CM_REG_CH0_FRAME2, 3322 CM_REG_CH1_FRAME1, CM_REG_CH1_FRAME2, CM_REG_EXT_MISC, 3323 CM_REG_INT_STATUS, CM_REG_INT_HLDCLR, CM_REG_FUNCTRL0, 3067 3324 }; 3068 3325 3069 3326 static unsigned char saved_mixers[] = { 3070 3071 3072 3073 3074 3075 3076 3077 3327 SB_DSP4_MASTER_DEV, SB_DSP4_MASTER_DEV + 1, 3328 SB_DSP4_PCM_DEV, SB_DSP4_PCM_DEV + 1, 3329 SB_DSP4_SYNTH_DEV, SB_DSP4_SYNTH_DEV + 1, 3330 SB_DSP4_CD_DEV, SB_DSP4_CD_DEV + 1, 3331 SB_DSP4_LINE_DEV, SB_DSP4_LINE_DEV + 1, 3332 SB_DSP4_MIC_DEV, SB_DSP4_SPEAKER_DEV, 3333 CM_REG_EXTENT_IND, SB_DSP4_OUTPUT_SW, 3334 SB_DSP4_INPUT_LEFT, SB_DSP4_INPUT_RIGHT, 3078 3335 }; 3079 3336 3080 3337 static int snd_cmipci_suspend(struct pci_dev *pci, pm_message_t state) 3081 3338 { 3082 3083 3084 3085 3086 3087 3088 3089 3090 3091 3092 3093 3094 3095 3096 3097 3098 3099 3100 3101 pci_set_power_state(pci, PCI_D3hot);3102 pci_disable_device(pci);3103 pci_save_state(pci);3104 3339 struct snd_card *card = pci_get_drvdata(pci); 3340 struct cmipci *cm = card->private_data; 3341 int i; 3342 3343 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot); 3344 3345 snd_pcm_suspend_all(cm->pcm); 3346 snd_pcm_suspend_all(cm->pcm2); 3347 snd_pcm_suspend_all(cm->pcm_spdif); 3348 3349 /* save registers */ 3350 for (i = 0; i < ARRAY_SIZE(saved_regs); i++) 3351 cm->saved_regs[i] = snd_cmipci_read(cm, saved_regs[i]); 3352 for (i = 0; i < ARRAY_SIZE(saved_mixers); i++) 3353 cm->saved_mixers[i] = snd_cmipci_mixer_read(cm, saved_mixers[i]); 3354 3355 /* disable ints */ 3356 snd_cmipci_write(cm, CM_REG_INT_HLDCLR, 0); 3357 3358 pci_disable_device(pci); 3359 pci_save_state(pci); 3360 pci_set_power_state(pci, pci_choose_state(pci, state)); 3361 return 0; 3105 3362 } 3106 3363 3107 3364 static int snd_cmipci_resume(struct pci_dev *pci) 3108 3365 { 3109 struct snd_card *card = pci_get_drvdata(pci); 3110 struct cmipci *cm = card->private_data; 3111 int i; 3112 3113 pci_restore_state(pci); 3114 pci_enable_device(pci); 3115 pci_set_power_state(pci, PCI_D0); 3116 pci_set_master(pci); 3117 3118 /* reset / initialize to a sane state */ 3119 snd_cmipci_write(cm, CM_REG_INT_HLDCLR, 0); 3120 snd_cmipci_ch_reset(cm, CM_CH_PLAY); 3121 snd_cmipci_ch_reset(cm, CM_CH_CAPT); 3122 snd_cmipci_mixer_write(cm, 0, 0); 3123 3124 /* restore registers */ 3125 for (i = 0; i < ARRAY_SIZE(saved_regs); i++) 3126 snd_cmipci_write(cm, saved_regs[i], cm->saved_regs[i]); 3127 for (i = 0; i < ARRAY_SIZE(saved_mixers); i++) 3128 snd_cmipci_mixer_write(cm, saved_mixers[i], cm->saved_mixers[i]); 3129 3130 snd_power_change_state(card, SNDRV_CTL_POWER_D0); 3131 return 0; 3366 struct snd_card *card = pci_get_drvdata(pci); 3367 struct cmipci *cm = card->private_data; 3368 int i; 3369 3370 pci_set_power_state(pci, PCI_D0); 3371 pci_restore_state(pci); 3372 if (pci_enable_device(pci) < 0) { 3373 printk(KERN_ERR "cmipci: pci_enable_device failed, " 3374 "disabling device\n"); 3375 snd_card_disconnect(card); 3376 return -EIO; 3377 } 3378 pci_set_master(pci); 3379 3380 /* reset / initialize to a sane state */ 3381 snd_cmipci_write(cm, CM_REG_INT_HLDCLR, 0); 3382 snd_cmipci_ch_reset(cm, CM_CH_PLAY); 3383 snd_cmipci_ch_reset(cm, CM_CH_CAPT); 3384 snd_cmipci_mixer_write(cm, 0, 0); 3385 3386 /* restore registers */ 3387 for (i = 0; i < ARRAY_SIZE(saved_regs); i++) 3388 snd_cmipci_write(cm, saved_regs[i], cm->saved_regs[i]); 3389 for (i = 0; i < ARRAY_SIZE(saved_mixers); i++) 3390 snd_cmipci_mixer_write(cm, saved_mixers[i], cm->saved_mixers[i]); 3391 3392 snd_power_change_state(card, SNDRV_CTL_POWER_D0); 3393 return 0; 3132 3394 } 3133 3395 #endif /* CONFIG_PM */ … … 3137 3399 .id_table = snd_cmipci_ids, 3138 3400 .probe = snd_cmipci_probe, 3139 .remove = snd_cmipci_remove,3401 .remove = __devexit_p(snd_cmipci_remove), 3140 3402 #ifdef CONFIG_PM 3141 3142 3143 3403 .suspend = snd_cmipci_suspend, 3404 .resume = snd_cmipci_resume, 3405 #endif 3144 3406 }; 3145 3407 3146 3408 static int __init alsa_card_cmipci_init(void) 3147 3409 { 3148 int err; 3149 3150 #ifdef TARGET_OS2 3151 if (midi_port > 0) mpu_port[0] = midi_port; 3152 #endif 3153 3154 if ((err = pci_module_init(&driver)) < 0) { 3155 #ifdef MODULE 3156 // printk(KERN_ERR "C-Media PCI soundcard not found or device busy\n"); 3157 #endif 3158 return err; 3159 } 3160 return 0; 3410 return pci_register_driver(&driver); 3161 3411 } 3162 3412 3163 3413 static void __exit alsa_card_cmipci_exit(void) 3164 3414 { 3165 3415 pci_unregister_driver(&driver); 3166 3416 } 3167 3417 3168 3418 module_init(alsa_card_cmipci_init) 3169 3419 module_exit(alsa_card_cmipci_exit) 3170 3171 #ifndef MODULE3172 3173 /* format is: snd-cmipci=enable,index,id,3174 mpu_port,fm_port */3175 3176 static int __init alsa_card_cmipci_setup(char *str)3177 {3178 static unsigned __initdata nr_dev = 0;3179 3180 if (nr_dev >= SNDRV_CARDS)3181 return 0;3182 (void)(get_option(&str,&enable[nr_dev]) == 2 &&3183 get_option(&str,&index[nr_dev]) == 2 &&3184 get_id(&str,&id[nr_dev]) == 2 &&3185 get_option(&str,(int *)&mpu_port[nr_dev]) == 2 &&3186 get_option(&str,(int *)&fm_port[nr_dev]) == 2);3187 nr_dev++;3188 return 1;3189 }3190 3191 __setup("snd-cmipci=", alsa_card_cmipci_setup);3192 3193 #endif /* ifndef MODULE */
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