source: GPL/trunk/alsa-kernel/pci/cmipci.c@ 135

Last change on this file since 135 was 135, checked in by stevenhl, 18 years ago

Get rid of spurious warnings
File size: 106.0 KB
Line 
1/*
2 * Driver for C-Media CMI8338 and 8738 PCI soundcards.
3 * Copyright (c) 2000 by Takashi Iwai <tiwai@suse.de>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19
20/* Does not work. Warning may block system in capture mode */
21/* #define USE_VAR48KRATE */
22
23#include <sound/driver.h>
24#include <asm/io.h>
25//#include <linux/interrupt.h>
26#include <linux/init.h>
27#include <linux/delay.h>
28//#include <linux/pci.h>
29#include <linux/slab.h>
30#include <sound/core.h>
31#include <sound/info.h>
32#include <sound/control.h>
33#include <sound/pcm.h>
34#include <sound/rawmidi.h>
35#include <sound/mpu401.h>
36#include <sound/opl3.h>
37#include <sound/sb.h>
38#include <sound/asoundef.h>
39#define SNDRV_GET_ID
40#include <sound/initval.h>
41
42MODULE_AUTHOR("Takashi Iwai <tiwai@suse.de>");
43MODULE_DESCRIPTION("C-Media CMI8x38 PCI");
44MODULE_LICENSE("GPL");
45MODULE_CLASSES("{sound}");
46MODULE_DEVICES("{{C-Media,CMI8738},"
47 "{C-Media,CMI8738B},"
48 "{C-Media,CMI8338A},"
49 "{C-Media,CMI8338B}}");
50
51extern int midi_port;
52
53static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
54static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
55static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable switches */
56//MPU disabled for now until it's fully supported by the MMPM2 driver
57static long mpu_port[SNDRV_CARDS] = {-1,-1,-1,-1,-1,-1,-1,-1};
58static long fm_port[SNDRV_CARDS] = {0x388, -1,-1,-1,-1,-1,-1,-1};
59
60static int soft_ac3[SNDRV_CARDS] = {0,1,1,1,1,1,1,1};
61
62MODULE_PARM(index, "1-" __MODULE_STRING(SNDRV_CARDS) "i");
63MODULE_PARM_DESC(index, "Index value for C-Media PCI soundcard.");
64MODULE_PARM_SYNTAX(index, SNDRV_INDEX_DESC);
65MODULE_PARM(id, "1-" __MODULE_STRING(SNDRV_CARDS) "s");
66MODULE_PARM_DESC(id, "ID string for C-Media PCI soundcard.");
67MODULE_PARM_SYNTAX(id, SNDRV_ID_DESC);
68MODULE_PARM(enable, "1-" __MODULE_STRING(SNDRV_CARDS) "i");
69MODULE_PARM_DESC(enable, "Enable C-Media PCI soundcard.");
70MODULE_PARM_SYNTAX(enable, SNDRV_ENABLE_DESC);
71MODULE_PARM(mpu_port, "1-" __MODULE_STRING(SNDRV_CARDS) "l");
72MODULE_PARM_DESC(mpu_port, "MPU-401 port.");
73MODULE_PARM_SYNTAX(mpu_port, SNDRV_ENABLED ",allows:{{-1},{0x330},{0x320},{0x310},{0x300}},dialog:list");
74MODULE_PARM(fm_port, "1-" __MODULE_STRING(SNDRV_CARDS) "l");
75MODULE_PARM_DESC(fm_port, "FM port.");
76MODULE_PARM_SYNTAX(fm_port, SNDRV_ENABLED ",allows:{{-1},{0x388},{0x3c8},{0x3e0},{0x3e8}},dialog:list");
77#ifdef DO_SOFT_AC3
78MODULE_PARM(soft_ac3, "1-" __MODULE_STRING(SNDRV_CARDS) "l");
79MODULE_PARM_DESC(soft_ac3, "Sofware-conversion of raw SPDIF packets (model 033 only).");
80MODULE_PARM_SYNTAX(soft_ac3, SNDRV_ENABLED "," SNDRV_BOOLEAN_TRUE_DESC);
81#endif
82
83#ifndef PCI_DEVICE_ID_CMEDIA_CM8738
84#define PCI_DEVICE_ID_CMEDIA_CM8738 0x0111
85#endif
86#ifndef PCI_DEVICE_ID_CMEDIA_CM8738B
87#define PCI_DEVICE_ID_CMEDIA_CM8738B 0x0112
88#endif
89
90//#define SIX_CH_HACK
91/*
92 * CM8x38 registers definition
93 */
94
95#define CM_REG_FUNCTRL0 0x00
96#define CM_RST_CH1 0x00080000
97#define CM_RST_CH0 0x00040000
98#define CM_CHEN1 0x00020000 /* ch1: enable */
99#define CM_CHEN0 0x00010000 /* ch0: enable */
100#define CM_PAUSE1 0x00000008 /* ch1: pause */
101#define CM_PAUSE0 0x00000004 /* ch0: pause */
102#define CM_CHADC1 0x00000002 /* ch1, 0:playback, 1:record */
103#define CM_CHADC0 0x00000001 /* ch0, 0:playback, 1:record */
104
105#define CM_REG_FUNCTRL1 0x04
106#define CM_ASFC_MASK 0x0000E000 /* ADC sampling frequency */
107#define CM_ASFC_SHIFT 13
108#define CM_DSFC_MASK 0x00001C00 /* DAC sampling frequency */
109#define CM_DSFC_SHIFT 10
110#define CM_SPDF_1 0x00000200 /* SPDIF IN/OUT at channel B */
111#define CM_SPDF_0 0x00000100 /* SPDIF OUT only channel A */
112#define CM_SPDFLOOP 0x00000080 /* ext. SPDIIF/OUT -> IN loopback */
113#define CM_SPDO2DAC 0x00000040 /* SPDIF/OUT can be heard from internal DAC */
114#define CM_INTRM 0x00000020 /* master control block (MCB) interrupt enabled */
115#define CM_BREQ 0x00000010 /* bus master enabled */
116#define CM_VOICE_EN 0x00000008 /* legacy voice (SB16,FM) */
117#define CM_UART_EN 0x00000004 /* UART */
118#define CM_JYSTK_EN 0x00000002 /* joy stick */
119
120#define CM_REG_CHFORMAT 0x08
121
122#define CM_CHB3D5C 0x80000000 /* 5,6 channels */
123#define CM_CHB3D 0x20000000 /* 4 channels */
124
125#define CM_CHIP_MASK1 0x1f000000
126#define CM_CHIP_037 0x01000000
127
128#define CM_SPDIF_SELECT1 0x00080000 /* for model <= 037 ? */
129#define CM_AC3EN1 0x00100000 /* enable AC3: model 037 */
130#define CM_SPD24SEL 0x00020000 /* 24bit spdif: model 037 */
131/* #define CM_SPDIF_INVERSE 0x00010000 */ /* ??? */
132
133#define CM_ADCBITLEN_MASK 0x0000C000
134#define CM_ADCBITLEN_16 0x00000000
135#define CM_ADCBITLEN_15 0x00004000
136#define CM_ADCBITLEN_14 0x00008000
137#define CM_ADCBITLEN_13 0x0000C000
138
139#define CM_ADCDACLEN_MASK 0x00003000
140#define CM_ADCDACLEN_060 0x00000000
141#define CM_ADCDACLEN_066 0x00001000
142#define CM_ADCDACLEN_130 0x00002000
143#define CM_ADCDACLEN_280 0x00003000
144
145#define CM_CH1_SRATE_176K 0x00000800
146#define CM_CH1_SRATE_88K 0x00000400
147#define CM_CH0_SRATE_176K 0x00000200
148#define CM_CH0_SRATE_88K 0x00000100
149
150#define CM_SPDIF_INVERSE2 0x00000080 /* model 055? */
151
152#define CM_CH1FMT_MASK 0x0000000C
153#define CM_CH1FMT_SHIFT 2
154#define CM_CH0FMT_MASK 0x00000003
155#define CM_CH0FMT_SHIFT 0
156
157#define CM_REG_INT_HLDCLR 0x0C
158#define CM_CHIP_MASK2 0xff000000
159#define CM_CHIP_039 0x04000000
160#define CM_CHIP_039_6CH 0x01000000
161#define CM_CHIP_055 0x08000000
162#define CM_CHIP_8768 0x20000000
163#define CM_TDMA_INT_EN 0x00040000
164#define CM_CH1_INT_EN 0x00020000
165#define CM_CH0_INT_EN 0x00010000
166#define CM_INT_HOLD 0x00000002
167#define CM_INT_CLEAR 0x00000001
168
169#define CM_REG_INT_STATUS 0x10
170#define CM_INTR 0x80000000
171#define CM_VCO 0x08000000 /* Voice Control? CMI8738 */
172#define CM_MCBINT 0x04000000 /* Master Control Block abort cond.? */
173#define CM_UARTINT 0x00010000
174#define CM_LTDMAINT 0x00008000
175#define CM_HTDMAINT 0x00004000
176#define CM_XDO46 0x00000080 /* Modell 033? Direct programming EEPROM (read data register) */
177#define CM_LHBTOG 0x00000040 /* High/Low status from DMA ctrl register */
178#define CM_LEG_HDMA 0x00000020 /* Legacy is in High DMA channel */
179#define CM_LEG_STEREO 0x00000010 /* Legacy is in Stereo mode */
180#define CM_CH1BUSY 0x00000008
181#define CM_CH0BUSY 0x00000004
182#define CM_CHINT1 0x00000002
183#define CM_CHINT0 0x00000001
184
185#define CM_REG_LEGACY_CTRL 0x14
186#define CM_NXCHG 0x80000000 /* h/w multi channels? */
187#define CM_VMPU_MASK 0x60000000 /* MPU401 i/o port address */
188#define CM_VMPU_330 0x00000000
189#define CM_VMPU_320 0x20000000
190#define CM_VMPU_310 0x40000000
191#define CM_VMPU_300 0x60000000
192#define CM_VSBSEL_MASK 0x0C000000 /* SB16 base address */
193#define CM_VSBSEL_220 0x00000000
194#define CM_VSBSEL_240 0x04000000
195#define CM_VSBSEL_260 0x08000000
196#define CM_VSBSEL_280 0x0C000000
197#define CM_FMSEL_MASK 0x03000000 /* FM OPL3 base address */
198#define CM_FMSEL_388 0x00000000
199#define CM_FMSEL_3C8 0x01000000
200#define CM_FMSEL_3E0 0x02000000
201#define CM_FMSEL_3E8 0x03000000
202#define CM_ENSPDOUT 0x00800000 /* enable XPDIF/OUT to I/O interface */
203#define CM_SPDCOPYRHT 0x00400000 /* set copyright spdif in/out */
204#define CM_DAC2SPDO 0x00200000 /* enable wave+fm_midi -> SPDIF/OUT */
205#define CM_SETRETRY 0x00010000 /* 0: legacy i/o wait (default), 1: legacy i/o bus retry */
206#define CM_CHB3D6C 0x00008000 /* 5.1 channels support */
207#define CM_LINE_AS_BASS 0x00006000 /* use line-in as bass */
208
209#define CM_REG_MISC_CTRL 0x18
210#define CM_PWD 0x80000000
211#define CM_RESET 0x40000000
212#define CM_SFIL_MASK 0x30000000
213#define CM_TXVX 0x08000000
214#define CM_N4SPK3D 0x04000000 /* 4ch output */
215#define CM_SPDO5V 0x02000000 /* 5V spdif output (1 = 0.5v (coax)) */
216#define CM_SPDIF48K 0x01000000 /* write */
217#define CM_SPATUS48K 0x01000000 /* read */
218#define CM_ENDBDAC 0x00800000 /* enable dual dac */
219#define CM_XCHGDAC 0x00400000 /* 0: front=ch0, 1: front=ch1 */
220#define CM_SPD32SEL 0x00200000 /* 0: 16bit SPDIF, 1: 32bit */
221#define CM_SPDFLOOPI 0x00100000 /* int. SPDIF-IN -> int. OUT */
222#define CM_FM_EN 0x00080000 /* enalbe FM */
223#define CM_AC3EN2 0x00040000 /* enable AC3: model 039 */
224#define CM_VIDWPDSB 0x00010000
225#define CM_SPDF_AC97 0x00008000 /* 0: SPDIF/OUT 44.1K, 1: 48K */
226#define CM_MASK_EN 0x00004000
227#define CM_VIDWPPRT 0x00002000
228#define CM_SFILENB 0x00001000
229#define CM_MMODE_MASK 0x00000E00
230#define CM_SPDIF_SELECT2 0x00000100 /* for model > 039 ? */
231#define CM_ENCENTER 0x00000080
232#define CM_FLINKON 0x00000040
233#define CM_FLINKOFF 0x00000020
234#define CM_MIDSMP 0x00000010
235#define CM_UPDDMA_MASK 0x0000000C
236#define CM_TWAIT_MASK 0x00000003
237
238/* byte */
239#define CM_REG_MIXER0 0x20
240
241#define CM_REG_SB16_DATA 0x22
242#define CM_REG_SB16_ADDR 0x23
243
244#define CM_REFFREQ_XIN (315*1000*1000)/22 /* 14.31818 Mhz reference clock frequency pin XIN */
245#define CM_ADCMULT_XIN 512 /* Guessed (487 best for 44.1kHz, not for 88/176kHz) */
246#define CM_TOLERANCE_RATE 0.001 /* Tolerance sample rate pitch (1000ppm) */
247#define CM_MAXIMUM_RATE 80000000 /* Note more than 80MHz */
248
249#define CM_REG_MIXER1 0x24
250#define CM_FMMUTE 0x80 /* mute FM */
251#define CM_FMMUTE_SHIFT 7
252#define CM_WSMUTE 0x40 /* mute PCM */
253#define CM_WSMUTE_SHIFT 6
254#define CM_SPK4 0x20 /* lin-in -> rear line out */
255#define CM_SPK4_SHIFT 5
256#define CM_REAR2FRONT 0x10 /* exchange rear/front */
257#define CM_REAR2FRONT_SHIFT 4
258#define CM_WAVEINL 0x08 /* digital wave rec. left chan */
259#define CM_WAVEINL_SHIFT 3
260#define CM_WAVEINR 0x04 /* digical wave rec. right */
261#define CM_WAVEINR_SHIFT 2
262#define CM_X3DEN 0x02 /* 3D surround enable */
263#define CM_X3DEN_SHIFT 1
264#define CM_CDPLAY 0x01 /* enable SPDIF/IN PCM -> DAC */
265#define CM_CDPLAY_SHIFT 0
266
267#define CM_REG_MIXER2 0x25
268#define CM_RAUXREN 0x80 /* AUX right capture */
269#define CM_RAUXREN_SHIFT 7
270#define CM_RAUXLEN 0x40 /* AUX left capture */
271#define CM_RAUXLEN_SHIFT 6
272#define CM_VAUXRM 0x20 /* AUX right mute */
273#define CM_VAUXRM_SHIFT 5
274#define CM_VAUXLM 0x10 /* AUX left mute */
275#define CM_VAUXLM_SHIFT 4
276#define CM_VADMIC_MASK 0x0e /* mic gain level (0-3) << 1 */
277#define CM_VADMIC_SHIFT 1
278#define CM_MICGAINZ 0x01 /* mic boost */
279#define CM_MICGAINZ_SHIFT 0
280
281#define CM_REG_MIXER3 0x24
282#define CM_REG_AUX_VOL 0x26
283#define CM_VAUXL_MASK 0xf0
284#define CM_VAUXR_MASK 0x0f
285
286#define CM_REG_MISC 0x27
287#define CM_XGPO1 0x20
288// #define CM_XGPBIO 0x04
289#define CM_MIC_CENTER_LFE 0x04 /* mic as center/lfe out? (model 039 or later?) */
290#define CM_SPDIF_INVERSE 0x04 /* spdif input phase inverse (model 037) */
291#define CM_SPDVALID 0x02 /* spdif input valid check */
292#define CM_DMAUTO 0x01
293
294#define CM_REG_AC97 0x28 /* hmmm.. do we have ac97 link? */
295/*
296 * For CMI-8338 (0x28 - 0x2b) .. is this valid for CMI-8738
297 * or identical with AC97 codec?
298 */
299#define CM_REG_EXTERN_CODEC CM_REG_AC97
300
301/*
302 * MPU401 pci port index address 0x40 - 0x4f (CMI-8738 spec ver. 0.6)
303 */
304#define CM_REG_MPU_PCI 0x40
305
306/*
307 * FM pci port index address 0x50 - 0x5f (CMI-8738 spec ver. 0.6)
308 */
309#define CM_REG_FM_PCI 0x50
310
311/*
312 * access from SB-mixer port
313 */
314#define CM_REG_EXTENT_IND 0xf0
315#define CM_VPHONE_MASK 0xe0 /* Phone volume control (0-3) << 5 */
316#define CM_VPHONE_SHIFT 5
317#define CM_VPHOM 0x10 /* Phone mute control */
318#define CM_VSPKM 0x08 /* Speaker mute control, default high */
319#define CM_RLOOPREN 0x04 /* Rec. R-channel enable */
320#define CM_RLOOPLEN 0x02 /* Rec. L-channel enable */
321#define CM_VADMIC3 0x01 /* Mic record boost */
322
323/*
324 * CMI-8338 spec ver 0.5 (this is not valid for CMI-8738):
325 * the 8 registers 0xf8 - 0xff are used for programming m/n counter by the PLL
326 * unit (readonly?).
327 */
328#define CM_REG_PLL 0xf8
329
330/*
331 * extended registers
332 */
333#define CM_REG_CH0_FRAME1 0x80 /* base address */
334#define CM_REG_CH0_FRAME2 0x84
335#define CM_REG_CH1_FRAME1 0x88 /* 0-15: count of samples at bus master; buffer size */
336#define CM_REG_CH1_FRAME2 0x8C /* 16-31: count of samples at codec; fragment size */
337#define CM_REG_EXT_MISC 0x90
338#define CM_REG_MISC_CTRL_8768 0x92 /* reg. name the same as 0x18 */
339#define CM_CHB3D8C 0x20 /* 7.1 channels support */
340#define CM_SPD32FMT 0x10 /* SPDIF/IN 32k */
341#define CM_ADC2SPDIF 0x08 /* ADC output to SPDIF/OUT */
342#define CM_SHAREADC 0x04 /* DAC in ADC as Center/LFE */
343#define CM_REALTCMP 0x02 /* monitor the CMPL/CMPR of ADC */
344#define CM_INVLRCK 0x01 /* invert ZVPORT's LRCK */
345/*
346 * size of i/o region
347 */
348#define CM_EXTENT_CODEC 0x100
349#define CM_EXTENT_MIDI 0x2
350#define CM_EXTENT_SYNTH 0x4
351
352/*
353 * pci ids
354 */
355#ifndef PCI_VENDOR_ID_CMEDIA
356#define PCI_VENDOR_ID_CMEDIA 0x13F6
357#endif
358#ifndef PCI_DEVICE_ID_CMEDIA_CM8338A
359#define PCI_DEVICE_ID_CMEDIA_CM8338A 0x0100
360#endif
361#ifndef PCI_DEVICE_ID_CMEDIA_CM8338B
362#define PCI_DEVICE_ID_CMEDIA_CM8338B 0x0101
363#endif
364#ifndef PCI_DEVICE_ID_CMEDIA_CM8738
365#define PCI_DEVICE_ID_CMEDIA_CM8738 0x0111
366#endif
367#ifndef PCI_DEVICE_ID_CMEDIA_CM8738B
368#define PCI_DEVICE_ID_CMEDIA_CM8738B 0x0112
369#endif
370
371/*
372 * channels for playback / capture
373 */
374#define CM_CH_PLAY 0
375#define CM_CH_CAPT 1
376
377/*
378 * flags to check device open/close
379 */
380#define CM_OPEN_NONE 0
381#define CM_OPEN_CH_MASK 0x01
382#define CM_OPEN_DAC 0x10
383#define CM_OPEN_ADC 0x20
384#define CM_OPEN_SPDIF 0x40
385#define CM_OPEN_MCHAN 0x80
386#define CM_OPEN_PLAYBACK (CM_CH_PLAY | CM_OPEN_DAC)
387#define CM_OPEN_PLAYBACK2 (CM_CH_CAPT | CM_OPEN_DAC)
388#define CM_OPEN_PLAYBACK_MULTI (CM_CH_PLAY | CM_OPEN_DAC | CM_OPEN_MCHAN)
389#define CM_OPEN_CAPTURE (CM_CH_CAPT | CM_OPEN_ADC)
390#define CM_OPEN_SPDIF_PLAYBACK (CM_CH_PLAY | CM_OPEN_DAC | CM_OPEN_SPDIF)
391#define CM_OPEN_SPDIF_CAPTURE (CM_CH_CAPT | CM_OPEN_ADC | CM_OPEN_SPDIF)
392
393
394#if CM_CH_PLAY == 1
395#define CM_PLAYBACK_SRATE_176K CM_CH1_SRATE_176K
396#define CM_PLAYBACK_SPDF CM_SPDF_1
397#define CM_CAPTURE_SPDF CM_SPDF_0
398#else
399#define CM_PLAYBACK_SRATE_176K CM_CH0_SRATE_176K
400#define CM_PLAYBACK_SPDF CM_SPDF_0
401#define CM_CAPTURE_SPDF CM_SPDF_1
402#endif
403
404
405/*
406 * driver data
407 */
408
409struct cmipci_pcm {
410 struct snd_pcm_substream *substream;
411 int running; /* dac/adc running? */
412 unsigned int dma_size; /* in frames */
413 unsigned int period_size; /* in frames */
414 unsigned int offset; /* physical address of the buffer */
415 unsigned int fmt; /* format bits */
416 int ch; /* channel (0/1) */
417 unsigned int is_dac; /* is dac? */
418 int bytes_per_frame;
419 int shift;
420};
421
422/* mixer elements toggled/resumed during ac3 playback */
423struct cmipci_mixer_auto_switches {
424 const char *name; /* switch to toggle */
425 int toggle_on; /* value to change when ac3 mode */
426};
427static const struct cmipci_mixer_auto_switches cm_saved_mixer[] = {
428 {"PCM Playback Switch", 0},
429 {"IEC958 Output Switch", 1},
430 {"IEC958 Mix Analog", 0},
431 // {"IEC958 Out To DAC", 1}, // no longer used
432 {"IEC958 Loop", 0},
433};
434
435#define CM_SAVED_MIXERS ARRAY_SIZE(cm_saved_mixer)
436
437struct cmipci {
438 struct snd_card *card;
439
440 struct pci_dev *pci;
441 unsigned int device; /* device ID */
442 int irq;
443
444 unsigned long iobase;
445 unsigned int ctrl; /* FUNCTRL0 current value */
446
447 struct snd_pcm *pcm; /* DAC/ADC PCM */
448 struct snd_pcm *pcm2; /* 2nd DAC */
449 struct snd_pcm *pcm_spdif; /* SPDIF */
450
451 int chip_version;
452 int max_channels;
453 unsigned int has_dual_dac: 1;
454 unsigned int can_ac3_sw: 1;
455 unsigned int can_ac3_hw: 1;
456 unsigned int can_multi_ch: 1;
457 unsigned int do_soft_ac3: 1;
458
459 unsigned int spdif_playback_avail: 1; /* spdif ready? */
460 unsigned int spdif_playback_enabled: 1; /* spdif switch enabled? */
461 int spdif_counter; /* for software AC3 */
462
463 unsigned int dig_status;
464 unsigned int dig_pcm_status;
465
466 struct snd_pcm_hardware_t *hw_info[3]; /* for playbacks */
467
468 int opened[2]; /* open mode */
469 struct semaphore open_mutex;
470
471 int mixer_insensitive: 1;
472 struct snd_kcontrol *mixer_res_ctl[CM_SAVED_MIXERS];
473 int mixer_res_status[CM_SAVED_MIXERS];
474
475 struct cmipci_pcm channel[2]; /* ch0 - DAC, ch1 - ADC or 2nd DAC */
476
477 /* external MIDI */
478 struct snd_rawmidi *rmidi;
479
480 spinlock_t reg_lock;
481
482#ifdef CONFIG_PM
483 unsigned int saved_regs[0x20];
484 unsigned char saved_mixers[0x20];
485#endif
486};
487
488
489/* read/write operations for dword register */
490static inline void snd_cmipci_write(struct cmipci *cm, unsigned int cmd, unsigned int data)
491{
492 outl(data, cm->iobase + cmd);
493}
494
495static inline unsigned int snd_cmipci_read(struct cmipci *cm, unsigned int cmd)
496{
497 return inl(cm->iobase + cmd);
498}
499
500/* read/write operations for word register */
501static inline void snd_cmipci_write_w(struct cmipci *cm, unsigned int cmd, unsigned short data)
502{
503 outw(data, cm->iobase + cmd);
504}
505
506static inline unsigned short snd_cmipci_read_w(struct cmipci *cm, unsigned int cmd)
507{
508 return inw(cm->iobase + cmd);
509}
510
511/* read/write operations for byte register */
512static inline void snd_cmipci_write_b(struct cmipci *cm, unsigned int cmd, unsigned char data)
513{
514 outb(data, cm->iobase + cmd);
515}
516
517static inline unsigned char snd_cmipci_read_b(struct cmipci *cm, unsigned int cmd)
518{
519 return inb(cm->iobase + cmd);
520}
521
522/* bit operations for dword register */
523static int snd_cmipci_set_bit(struct cmipci *cm, unsigned int cmd, unsigned int flag)
524{
525 unsigned int val, oval;
526 val = oval = inl(cm->iobase + cmd);
527 val |= flag;
528 if (val == oval)
529 return 0;
530 outl(val, cm->iobase + cmd);
531 return 1;
532}
533
534static int snd_cmipci_clear_bit(struct cmipci *cm, unsigned int cmd, unsigned int flag)
535{
536 unsigned int val, oval;
537 val = oval = inl(cm->iobase + cmd);
538 val &= ~flag;
539 if (val == oval)
540 return 0;
541 outl(val, cm->iobase + cmd);
542 return 1;
543}
544
545/* bit operations for byte register */
546static int snd_cmipci_set_bit_b(struct cmipci *cm, unsigned int cmd, unsigned char flag)
547{
548 unsigned char val, oval;
549 val = oval = inb(cm->iobase + cmd);
550 val |= flag;
551 if (val == oval)
552 return 0;
553 outb(val, cm->iobase + cmd);
554 return 1;
555}
556
557static int snd_cmipci_clear_bit_b(struct cmipci *cm, unsigned int cmd, unsigned char flag)
558{
559 unsigned char val, oval;
560 val = oval = inb(cm->iobase + cmd);
561 val &= ~flag;
562 if (val == oval)
563 return 0;
564 outb(val, cm->iobase + cmd);
565 return 1;
566}
567
568/*
569 * PCM interface
570 */
571
572/*
573 * calculate frequency
574 */
575
576static unsigned int rates[] = { 5512, 11025, 22050, 44100, 8000, 16000, 32000, 48000 };
577
578static unsigned int snd_cmipci_rate_freq(unsigned int rate)
579{
580 unsigned int i;
581 for (i = 0; i < ARRAY_SIZE(rates); i++) {
582 if (rates[i] == rate)
583 return i;
584 }
585 snd_BUG();
586 return 0;
587}
588
589#ifdef USE_VAR48KRATE
590/*
591 * Determine PLL values for frequency setup, maybe the CMI8338 (CMI8738???)
592 * does it this way .. maybe not. Never get any information from C-Media about
593 * that <werner@suse.de>.
594 */
595static int snd_cmipci_pll_rmn(unsigned int rate, unsigned int adcmult, int *r, int *m, int *n)
596{
597 unsigned int delta, tolerance;
598 int xm, xn, xr;
599
600 for (*r = 0; rate < CM_MAXIMUM_RATE/adcmult; *r += (1<<5))
601 rate <<= 1;
602 *n = -1;
603 if (*r > 0xff)
604 goto out;
605 tolerance = rate*CM_TOLERANCE_RATE;
606
607 for (xn = (1+2); xn < (0x1f+2); xn++) {
608 for (xm = (1+2); xm < (0xff+2); xm++) {
609 xr = ((CM_REFFREQ_XIN/adcmult) * xm) / xn;
610
611 if (xr < rate)
612 delta = rate - xr;
613 else
614 delta = xr - rate;
615
616 /*
617 * If we found one, remember this,
618 * and try to find a closer one
619 */
620 if (delta < tolerance) {
621 tolerance = delta;
622 *m = xm - 2;
623 *n = xn - 2;
624 }
625 }
626 }
627out:
628 return (*n > -1);
629}
630
631/*
632 * Program pll register bits, I assume that the 8 registers 0xf8 upto 0xff
633 * are mapped onto the 8 ADC/DAC sampling frequency which can be choosen
634 * at the register CM_REG_FUNCTRL1 (0x04).
635 * Problem: other ways are also possible (any information about that?)
636 */
637static void snd_cmipci_set_pll(struct cmipci *cm, unsigned int rate, unsigned int slot)
638{
639 unsigned int reg = CM_REG_PLL + slot;
640 /*
641 * Guess that this programs at reg. 0x04 the pos 15:13/12:10
642 * for DSFC/ASFC (000 upto 111).
643 */
644
645 /* FIXME: Init (Do we've to set an other register first before programming?) */
646
647 /* FIXME: Is this correct? Or shouldn't the m/n/r values be used for that? */
648 snd_cmipci_write_b(cm, reg, rate>>8);
649 snd_cmipci_write_b(cm, reg, rate&0xff);
650
651 /* FIXME: Setup (Do we've to set an other register first to enable this?) */
652}
653#endif /* USE_VAR48KRATE */
654
655static int snd_cmipci_hw_params(struct snd_pcm_substream *substream,
656 struct snd_pcm_hw_params *hw_params)
657{
658 return snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params));
659}
660
661static int snd_cmipci_playback2_hw_params(struct snd_pcm_substream *substream,
662 struct snd_pcm_hw_params *hw_params)
663{
664 struct cmipci *cm = snd_pcm_substream_chip(substream);
665 if (params_channels(hw_params) > 2) {
666 down(&cm->open_mutex);
667#if 0 // vladest
668 if (cm->opened[CM_CH_PLAY]) {
669 up(&cm->open_mutex);
670 return -EBUSY;
671 }
672#endif
673 /* reserve the channel A */
674 cm->opened[CM_CH_PLAY] = CM_OPEN_PLAYBACK_MULTI;
675 up(&cm->open_mutex);
676 }
677 return snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params));
678}
679
680static void snd_cmipci_ch_reset(struct cmipci *cm, int ch)
681{
682 int reset = CM_RST_CH0 << (cm->channel[ch].ch);
683 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl | reset);
684 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl & ~reset);
685 udelay(10);
686}
687
688static int snd_cmipci_hw_free(struct snd_pcm_substream *substream)
689{
690 return snd_pcm_lib_free_pages(substream);
691}
692
693
694/*
695 */
696
697static unsigned int hw_channels[] = {1, 2, 4, 5, 6, 8};
698static struct snd_pcm_hw_constraint_list hw_constraints_channels_4 = {
699 .count = 3,
700 .list = hw_channels,
701 .mask = 0,
702};
703static struct snd_pcm_hw_constraint_list hw_constraints_channels_6 = {
704 .count = 5,
705 .list = hw_channels,
706 .mask = 0,
707};
708static struct snd_pcm_hw_constraint_list hw_constraints_channels_8 = {
709 .count = 6,
710 .list = hw_channels,
711 .mask = 0,
712};
713
714static int set_dac_channels(struct cmipci *cm, struct cmipci_pcm *rec, int channels)
715{
716 if (channels > 2) {
717 if (! cm->can_multi_ch)
718 return -EINVAL;
719 if (rec->fmt != 0x03) /* stereo 16bit only */
720 return -EINVAL;
721
722 spin_lock_irq(&cm->reg_lock);
723 snd_cmipci_set_bit(cm, CM_REG_LEGACY_CTRL, CM_NXCHG);
724 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_XCHGDAC);
725 if (channels > 4) {
726 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_CHB3D);
727 snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_CHB3D5C);
728 } else {
729 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_CHB3D5C);
730 snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_CHB3D);
731 }
732 if (channels >= 6) {
733 snd_cmipci_set_bit(cm, CM_REG_LEGACY_CTRL, CM_CHB3D6C);
734 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_ENCENTER);
735 } else {
736 snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_CHB3D6C);
737 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_ENCENTER);
738 }
739 if (cm->chip_version == 68) {
740 if (channels == 8) {
741 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL_8768, CM_CHB3D8C);
742 } else {
743 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL_8768, CM_CHB3D8C);
744 }
745 }
746 spin_unlock_irq(&cm->reg_lock);
747
748 } else {
749 if (cm->can_multi_ch) {
750 spin_lock_irq(&cm->reg_lock);
751 snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_NXCHG);
752 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_CHB3D);
753 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_CHB3D5C);
754 snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_CHB3D6C);
755 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_ENCENTER);
756 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_XCHGDAC);
757 spin_unlock_irq(&cm->reg_lock);
758 }
759 }
760 return 0;
761}
762
763
764/*
765 * prepare playback/capture channel
766 * channel to be used must have been set in rec->ch.
767 */
768static int snd_cmipci_pcm_prepare(struct cmipci *cm, struct cmipci_pcm *rec,
769 struct snd_pcm_substream *substream)
770{
771 unsigned int reg, freq, val;
772 struct snd_pcm_runtime *runtime = substream->runtime;
773
774 rec->fmt = 0;
775 rec->shift = 0;
776 if (snd_pcm_format_width(runtime->format) >= 16) {
777 rec->fmt |= 0x02;
778 if (snd_pcm_format_width(runtime->format) > 16)
779 rec->shift++; /* 24/32bit */
780 }
781 if (runtime->channels > 1)
782 rec->fmt |= 0x01;
783 if (rec->is_dac && set_dac_channels(cm, rec, runtime->channels) < 0) {
784 snd_printd("cannot set dac channels\n");
785 return -EINVAL;
786 }
787
788 rec->offset = runtime->dma_addr;
789 /* buffer and period sizes in frame */
790 rec->dma_size = runtime->buffer_size << rec->shift;
791 rec->period_size = runtime->period_size << rec->shift;
792 if (runtime->channels > 2) {
793 /* multi-channels */
794 rec->dma_size = (rec->dma_size * runtime->channels) / 2;
795 rec->period_size = (rec->period_size * runtime->channels) / 2;
796 }
797
798 spin_lock_irq(&cm->reg_lock);
799
800 /* set buffer address */
801 reg = rec->ch ? CM_REG_CH1_FRAME1 : CM_REG_CH0_FRAME1;
802 snd_cmipci_write(cm, reg, rec->offset);
803 /* program sample counts */
804 reg = rec->ch ? CM_REG_CH1_FRAME2 : CM_REG_CH0_FRAME2;
805 snd_cmipci_write_w(cm, reg, rec->dma_size - 1);
806 snd_cmipci_write_w(cm, reg + 2, rec->period_size - 1);
807
808 /* set adc/dac flag */
809 val = rec->ch ? CM_CHADC1 : CM_CHADC0;
810 if (rec->is_dac)
811 cm->ctrl &= ~val;
812 else
813 cm->ctrl |= val;
814 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl);
815 //snd_printd("cmipci: functrl0 = %08x\n", cm->ctrl);
816
817 /* set sample rate */
818 freq = snd_cmipci_rate_freq(runtime->rate);
819 val = snd_cmipci_read(cm, CM_REG_FUNCTRL1);
820 if (rec->ch) {
821 val &= ~CM_ASFC_MASK;
822 val |= (freq << CM_ASFC_SHIFT) & CM_ASFC_MASK;
823 } else {
824 val &= ~CM_DSFC_MASK;
825 val |= (freq << CM_DSFC_SHIFT) & CM_DSFC_MASK;
826 }
827 snd_cmipci_write(cm, CM_REG_FUNCTRL1, val);
828 //snd_printd("cmipci: functrl1 = %08x\n", val);
829
830 /* set format */
831 val = snd_cmipci_read(cm, CM_REG_CHFORMAT);
832 if (rec->ch) {
833 val &= ~CM_CH1FMT_MASK;
834 val |= rec->fmt << CM_CH1FMT_SHIFT;
835 } else {
836 val &= ~CM_CH0FMT_MASK;
837 val |= rec->fmt << CM_CH0FMT_SHIFT;
838 }
839 snd_cmipci_write(cm, CM_REG_CHFORMAT, val);
840 //snd_printd("cmipci: chformat = %08x\n", val);
841
842 rec->running = 0;
843 spin_unlock_irq(&cm->reg_lock);
844
845 return 0;
846}
847
848/*
849 * PCM trigger/stop
850 */
851static int snd_cmipci_pcm_trigger(struct cmipci *cm, struct cmipci_pcm *rec,
852 struct snd_pcm_substream *substream, int cmd)
853{
854 unsigned int inthld, chen, reset, pause;
855 int result = 0;
856
857 inthld = CM_CH0_INT_EN << rec->ch;
858 chen = CM_CHEN0 << rec->ch;
859 reset = CM_RST_CH0 << rec->ch;
860 pause = CM_PAUSE0 << rec->ch;
861
862 spin_lock(&cm->reg_lock);
863 switch (cmd) {
864 case SNDRV_PCM_TRIGGER_START:
865 rec->running = 1;
866 /* set interrupt */
867 snd_cmipci_set_bit(cm, CM_REG_INT_HLDCLR, inthld);
868 cm->ctrl |= chen;
869 /* enable channel */
870 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl);
871 //snd_printd("cmipci: functrl0 = %08x\n", cm->ctrl);
872 break;
873 case SNDRV_PCM_TRIGGER_STOP:
874 rec->running = 0;
875 /* disable interrupt */
876 snd_cmipci_clear_bit(cm, CM_REG_INT_HLDCLR, inthld);
877 /* reset */
878 cm->ctrl &= ~chen;
879 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl | reset);
880 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl & ~reset);
881 break;
882 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
883 case SNDRV_PCM_TRIGGER_SUSPEND:
884 cm->ctrl |= pause;
885 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl);
886 break;
887 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
888 case SNDRV_PCM_TRIGGER_RESUME:
889 cm->ctrl &= ~pause;
890 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl);
891 break;
892 default:
893 result = -EINVAL;
894 break;
895 }
896 spin_unlock(&cm->reg_lock);
897 return result;
898}
899
900/*
901 * return the current pointer
902 */
903static snd_pcm_uframes_t snd_cmipci_pcm_pointer(struct cmipci *cm, struct cmipci_pcm *rec,
904 struct snd_pcm_substream *substream)
905{
906 size_t ptr;
907 unsigned int reg;
908 if (!rec->running)
909 return 0;
910#if 1 // this seems better..
911 reg = rec->ch ? CM_REG_CH1_FRAME2 : CM_REG_CH0_FRAME2;
912 ptr = rec->dma_size - (snd_cmipci_read_w(cm, reg) + 1);
913 ptr >>= rec->shift;
914#else
915 reg = rec->ch ? CM_REG_CH1_FRAME1 : CM_REG_CH0_FRAME1;
916 ptr = snd_cmipci_read(cm, reg) - rec->offset;
917 ptr = bytes_to_frames(substream->runtime, ptr);
918#endif
919 if (substream->runtime->channels > 2)
920 ptr = (ptr * 2) / substream->runtime->channels;
921 return ptr;
922}
923
924/*
925 * playback
926 */
927static int snd_cmipci_playback_trigger(struct snd_pcm_substream *substream,
928 int cmd)
929{
930 struct cmipci *cm = snd_pcm_substream_chip(substream);
931 return snd_cmipci_pcm_trigger(cm, &cm->channel[CM_CH_PLAY], substream, cmd);
932}
933
934static snd_pcm_uframes_t snd_cmipci_playback_pointer(struct snd_pcm_substream *substream)
935{
936 struct cmipci *cm = snd_pcm_substream_chip(substream);
937 return snd_cmipci_pcm_pointer(cm, &cm->channel[CM_CH_PLAY], substream);
938}
939
940
941
942/*
943 * capture
944 */
945
946static int snd_cmipci_capture_trigger(struct snd_pcm_substream *substream,
947 int cmd)
948{
949 struct cmipci *cm = snd_pcm_substream_chip(substream);
950 return snd_cmipci_pcm_trigger(cm, &cm->channel[CM_CH_CAPT], substream, cmd);
951}
952
953static snd_pcm_uframes_t snd_cmipci_capture_pointer(struct snd_pcm_substream *substream)
954{
955 struct cmipci *cm = snd_pcm_substream_chip(substream);
956 return snd_cmipci_pcm_pointer(cm, &cm->channel[CM_CH_CAPT], substream);
957}
958
959
960/*
961 * hw preparation for spdif
962 */
963
964static int snd_cmipci_spdif_default_info(struct snd_kcontrol *kcontrol,
965 struct snd_ctl_elem_info *uinfo)
966{
967 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
968 uinfo->count = 1;
969 return 0;
970}
971
972static int snd_cmipci_spdif_default_get(struct snd_kcontrol *kcontrol,
973 struct snd_ctl_elem_value *ucontrol)
974{
975 struct cmipci *chip = snd_kcontrol_chip(kcontrol);
976 int i;
977
978 spin_lock_irq(&chip->reg_lock);
979 for (i = 0; i < 4; i++)
980 ucontrol->value.iec958.status[i] = (chip->dig_status >> (i * 8)) & 0xff;
981 spin_unlock_irq(&chip->reg_lock);
982 return 0;
983}
984
985static int snd_cmipci_spdif_default_put(struct snd_kcontrol *kcontrol,
986 struct snd_ctl_elem_value *ucontrol)
987{
988 struct cmipci *chip = snd_kcontrol_chip(kcontrol);
989 int i, change;
990 unsigned int val;
991
992 val = 0;
993 spin_lock_irq(&chip->reg_lock);
994 for (i = 0; i < 4; i++)
995 val |= (unsigned int)ucontrol->value.iec958.status[i] << (i * 8);
996 change = val != chip->dig_status;
997 chip->dig_status = val;
998 spin_unlock_irq(&chip->reg_lock);
999 return change;
1000}
1001
1002static struct snd_kcontrol_new snd_cmipci_spdif_default __devinitdata =
1003{
1004 SNDRV_CTL_ELEM_IFACE_PCM,0,0,
1005 SNDRV_CTL_NAME_IEC958("",PLAYBACK,DEFAULT),0,0,0,
1006 snd_cmipci_spdif_default_info,
1007 snd_cmipci_spdif_default_get,
1008 snd_cmipci_spdif_default_put,0
1009};
1010
1011static int snd_cmipci_spdif_mask_info(struct snd_kcontrol *kcontrol,
1012 struct snd_ctl_elem_info *uinfo)
1013{
1014 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1015 uinfo->count = 1;
1016 return 0;
1017}
1018
1019static int snd_cmipci_spdif_mask_get(struct snd_kcontrol *kcontrol,
1020 struct snd_ctl_elem_value *ucontrol)
1021{
1022 ucontrol->value.iec958.status[0] = 0xff;
1023 ucontrol->value.iec958.status[1] = 0xff;
1024 ucontrol->value.iec958.status[2] = 0xff;
1025 ucontrol->value.iec958.status[3] = 0xff;
1026 return 0;
1027}
1028
1029static struct snd_kcontrol_new snd_cmipci_spdif_mask __devinitdata =
1030{
1031 SNDRV_CTL_ELEM_IFACE_MIXER,0,0,
1032 SNDRV_CTL_NAME_IEC958("",PLAYBACK,CON_MASK),0,
1033 SNDRV_CTL_ELEM_ACCESS_READ,0,
1034 snd_cmipci_spdif_mask_info,
1035 snd_cmipci_spdif_mask_get,0,0
1036};
1037
1038static int snd_cmipci_spdif_stream_info(struct snd_kcontrol *kcontrol,
1039 struct snd_ctl_elem_info *uinfo)
1040{
1041 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1042 uinfo->count = 1;
1043 return 0;
1044}
1045
1046static int snd_cmipci_spdif_stream_get(struct snd_kcontrol *kcontrol,
1047 struct snd_ctl_elem_value *ucontrol)
1048{
1049 struct cmipci *chip = snd_kcontrol_chip(kcontrol);
1050 int i;
1051
1052 spin_lock_irq(&chip->reg_lock);
1053 for (i = 0; i < 4; i++)
1054 ucontrol->value.iec958.status[i] = (chip->dig_pcm_status >> (i * 8)) & 0xff;
1055 spin_unlock_irq(&chip->reg_lock);
1056 return 0;
1057}
1058
1059static int snd_cmipci_spdif_stream_put(struct snd_kcontrol *kcontrol,
1060 struct snd_ctl_elem_value *ucontrol)
1061{
1062 struct cmipci *chip = snd_kcontrol_chip(kcontrol);
1063 int i, change;
1064 unsigned int val;
1065
1066 val = 0;
1067 spin_lock_irq(&chip->reg_lock);
1068 for (i = 0; i < 4; i++)
1069 val |= (unsigned int)ucontrol->value.iec958.status[i] << (i * 8);
1070 change = val != chip->dig_pcm_status;
1071 chip->dig_pcm_status = val;
1072 spin_unlock_irq(&chip->reg_lock);
1073 return change;
1074}
1075
1076static struct snd_kcontrol_new snd_cmipci_spdif_stream __devinitdata =
1077{
1078 SNDRV_CTL_ELEM_IFACE_PCM,0,0,
1079 SNDRV_CTL_NAME_IEC958("",PLAYBACK,PCM_STREAM),0,
1080 SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_INACTIVE,0,
1081 snd_cmipci_spdif_stream_info,
1082 snd_cmipci_spdif_stream_get,
1083 snd_cmipci_spdif_stream_put,0
1084};
1085
1086/*
1087 */
1088
1089/* save mixer setting and mute for AC3 playback */
1090static int save_mixer_state(struct cmipci *cm)
1091{
1092 if (! cm->mixer_insensitive) {
1093 struct snd_ctl_elem_value *val;
1094 unsigned int i;
1095 val = kmalloc(sizeof(*val), GFP_ATOMIC);
1096 if (!val)
1097 return -ENOMEM;
1098 for (i = 0; i < CM_SAVED_MIXERS; i++) {
1099 struct snd_kcontrol *ctl = cm->mixer_res_ctl[i];
1100 if (ctl) {
1101 int event;
1102 memset(val, 0, sizeof(*val));
1103 ctl->get(ctl, val);
1104 cm->mixer_res_status[i] = val->value.integer.value[0];
1105 val->value.integer.value[0] = cm_saved_mixer[i].toggle_on;
1106 event = SNDRV_CTL_EVENT_MASK_INFO;
1107 if (cm->mixer_res_status[i] != val->value.integer.value[0]) {
1108 ctl->put(ctl, val); /* toggle */
1109 event |= SNDRV_CTL_EVENT_MASK_VALUE;
1110 }
1111 ctl->vd[0].access |= SNDRV_CTL_ELEM_ACCESS_INACTIVE;
1112 snd_ctl_notify(cm->card, event, &ctl->id);
1113 }
1114 }
1115 kfree(val);
1116 cm->mixer_insensitive = 1;
1117 }
1118 return 0;
1119}
1120
1121
1122/* restore the previously saved mixer status */
1123static void restore_mixer_state(struct cmipci *cm)
1124{
1125 if (cm->mixer_insensitive) {
1126 struct snd_ctl_elem_value *val;
1127 unsigned int i;
1128
1129 val = kmalloc(sizeof(*val), GFP_KERNEL);
1130 if (!val)
1131 return;
1132 cm->mixer_insensitive = 0; /* at first clear this;
1133 otherwise the changes will be ignored */
1134 for (i = 0; i < CM_SAVED_MIXERS; i++) {
1135 struct snd_kcontrol *ctl = cm->mixer_res_ctl[i];
1136 if (ctl) {
1137 int event;
1138
1139 memset(val, 0, sizeof(*val));
1140 ctl->vd[0].access &= ~SNDRV_CTL_ELEM_ACCESS_INACTIVE;
1141 ctl->get(ctl, val);
1142 event = SNDRV_CTL_EVENT_MASK_INFO;
1143 if (val->value.integer.value[0] != cm->mixer_res_status[i]) {
1144 val->value.integer.value[0] = cm->mixer_res_status[i];
1145 ctl->put(ctl, val);
1146 event |= SNDRV_CTL_EVENT_MASK_VALUE;
1147 }
1148 snd_ctl_notify(cm->card, event, &ctl->id);
1149 }
1150 }
1151 kfree(val);
1152 }
1153}
1154
1155/* spinlock held! */
1156static void setup_ac3(struct cmipci *cm, struct snd_pcm_substream *subs, int do_ac3, int rate)
1157{
1158 if (do_ac3) {
1159 /* AC3EN for 037 */
1160 snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_AC3EN1);
1161 /* AC3EN for 039 */
1162 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_AC3EN2);
1163
1164 if (cm->can_ac3_hw) {
1165 /* SPD24SEL for 037, 0x02 */
1166 /* SPD24SEL for 039, 0x20, but cannot be set */
1167 snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_SPD24SEL);
1168 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
1169 } else { /* can_ac3_sw */
1170 /* SPD32SEL for 037 & 039, 0x20 */
1171 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
1172 /* set 176K sample rate to fix 033 HW bug */
1173 if (cm->chip_version == 33) {
1174 if (rate >= 48000) {
1175 snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_PLAYBACK_SRATE_176K);
1176 } else {
1177 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_PLAYBACK_SRATE_176K);
1178 }
1179 }
1180 }
1181
1182 } else {
1183 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_AC3EN1);
1184 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_AC3EN2);
1185
1186 if (cm->can_ac3_hw) {
1187 /* chip model >= 37 */
1188 if (snd_pcm_format_width(subs->runtime->format) > 16) {
1189 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
1190 snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_SPD24SEL);
1191 } else {
1192 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
1193 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_SPD24SEL);
1194 }
1195 } else {
1196 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
1197 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_SPD24SEL);
1198 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_PLAYBACK_SRATE_176K);
1199 }
1200 }
1201}
1202
1203static int setup_spdif_playback(struct cmipci *cm, struct snd_pcm_substream *subs, int up, int do_ac3)
1204{
1205 int rate, err;
1206
1207 rate = subs->runtime->rate;
1208
1209 if (up && do_ac3)
1210 if ((err = save_mixer_state(cm)) < 0)
1211 return err;
1212
1213 spin_lock_irq(&cm->reg_lock);
1214 cm->spdif_playback_avail = up;
1215 if (up) {
1216 /* they are controlled via "IEC958 Output Switch" */
1217 /* snd_cmipci_set_bit(cm, CM_REG_LEGACY_CTRL, CM_ENSPDOUT); */
1218 /* snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_SPDO2DAC); */
1219 if (cm->spdif_playback_enabled)
1220 snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_PLAYBACK_SPDF);
1221 setup_ac3(cm, subs, do_ac3, rate);
1222
1223 if (rate == 48000)
1224 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_SPDIF48K | CM_SPDF_AC97);
1225 else
1226 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_SPDIF48K | CM_SPDF_AC97);
1227
1228 } else {
1229 /* they are controlled via "IEC958 Output Switch" */
1230 /* snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_ENSPDOUT); */
1231 /* snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_SPDO2DAC); */
1232 snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_PLAYBACK_SPDF);
1233 setup_ac3(cm, subs, 0, 0);
1234 }
1235 spin_unlock_irq(&cm->reg_lock);
1236 return 0;
1237}
1238
1239
1240/*
1241 * preparation
1242 */
1243
1244/* playback - enable spdif only on the certain condition */
1245static int snd_cmipci_playback_prepare(struct snd_pcm_substream *substream)
1246{
1247 struct cmipci *cm = snd_pcm_substream_chip(substream);
1248 int rate = substream->runtime->rate;
1249 int err, do_spdif, do_ac3 = 0;
1250 do_spdif = ((rate == 44100 || rate == 48000) &&
1251 substream->runtime->format == SNDRV_PCM_FORMAT_S16_LE &&
1252 substream->runtime->channels == 2);
1253 if (do_spdif && cm->can_ac3_hw)
1254 do_ac3 = cm->dig_pcm_status & IEC958_AES0_NONAUDIO;
1255 if ((err = setup_spdif_playback(cm, substream, do_spdif, do_ac3)) < 0)
1256 return err;
1257 return snd_cmipci_pcm_prepare(cm, &cm->channel[CM_CH_PLAY], substream);
1258}
1259
1260/* playback (via device #2) - enable spdif always */
1261static int snd_cmipci_playback_spdif_prepare(struct snd_pcm_substream *substream)
1262{
1263 struct cmipci *cm = snd_pcm_substream_chip(substream);
1264 int err, do_ac3;
1265 if (cm->can_ac3_hw)
1266 do_ac3 = cm->dig_pcm_status & IEC958_AES0_NONAUDIO;
1267 else
1268 do_ac3 = 1; /* doesn't matter */
1269 if ((err = setup_spdif_playback(cm, substream, 1, do_ac3)) < 0)
1270 return err;
1271 return snd_cmipci_pcm_prepare(cm, &cm->channel[CM_CH_PLAY], substream);
1272}
1273
1274static int snd_cmipci_playback_hw_free(struct snd_pcm_substream *substream)
1275{
1276 struct cmipci *cm = snd_pcm_substream_chip(substream);
1277 setup_spdif_playback(cm, substream, 0, 0);
1278 restore_mixer_state(cm);
1279 return snd_cmipci_hw_free(substream);
1280}
1281
1282/* capture */
1283static int snd_cmipci_capture_prepare(struct snd_pcm_substream *substream)
1284{
1285 struct cmipci *cm = snd_pcm_substream_chip(substream);
1286 return snd_cmipci_pcm_prepare(cm, &cm->channel[CM_CH_CAPT], substream);
1287}
1288
1289/* capture with spdif (via device #2) */
1290static int snd_cmipci_capture_spdif_prepare(struct snd_pcm_substream *substream)
1291{
1292 struct cmipci *cm = snd_pcm_substream_chip(substream);
1293
1294 spin_lock_irq(&cm->reg_lock);
1295 snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_CAPTURE_SPDF);
1296 spin_unlock_irq(&cm->reg_lock);
1297
1298 return snd_cmipci_pcm_prepare(cm, &cm->channel[CM_CH_CAPT], substream);
1299}
1300
1301static int snd_cmipci_capture_spdif_hw_free(struct snd_pcm_substream *subs)
1302{
1303 struct cmipci *cm = snd_pcm_substream_chip(subs);
1304
1305 spin_lock_irq(&cm->reg_lock);
1306 snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_CAPTURE_SPDF);
1307 spin_unlock_irq(&cm->reg_lock);
1308
1309 return snd_cmipci_hw_free(subs);
1310}
1311
1312
1313/*
1314 * interrupt handler
1315 */
1316static irqreturn_t snd_cmipci_interrupt(int irq, void *dev_id, struct pt_regs *regs)
1317{
1318 struct cmipci *cm = dev_id;
1319 unsigned int status, mask = 0;
1320#ifdef DEBUG
1321 // dprintf(("i"));
1322#endif
1323 /* fastpath out, to ease interrupt sharing */
1324 status = snd_cmipci_read(cm, CM_REG_INT_STATUS);
1325 if (!(status & CM_INTR))
1326 return IRQ_NONE;
1327
1328
1329 /* acknowledge interrupt */
1330 spin_lock(&cm->reg_lock);
1331 if (status & CM_CHINT0)
1332 mask |= CM_CH0_INT_EN;
1333 if (status & CM_CHINT1)
1334 mask |= CM_CH1_INT_EN;
1335 snd_cmipci_clear_bit(cm, CM_REG_INT_HLDCLR, mask);
1336 snd_cmipci_set_bit(cm, CM_REG_INT_HLDCLR, mask);
1337 spin_unlock(&cm->reg_lock);
1338
1339 if (cm->rmidi && (status & CM_UARTINT))
1340 snd_mpu401_uart_interrupt(irq, cm->rmidi->private_data, regs);
1341
1342 if (cm->pcm) {
1343 if ((status & CM_CHINT0) && cm->channel[0].running)
1344 snd_pcm_period_elapsed(cm->channel[0].substream);
1345 if ((status & CM_CHINT1) && cm->channel[1].running)
1346 snd_pcm_period_elapsed(cm->channel[1].substream);
1347 }
1348 return IRQ_HANDLED;
1349}
1350
1351/*
1352 * h/w infos
1353 */
1354
1355/* playback on channel A */
1356static struct snd_pcm_hardware snd_cmipci_playback =
1357{
1358 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1359 SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE |
1360 SNDRV_PCM_INFO_RESUME | SNDRV_PCM_INFO_MMAP_VALID),
1361 .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
1362 .rates = SNDRV_PCM_RATE_5512 | SNDRV_PCM_RATE_8000_48000,
1363 .rate_min = 5512,
1364 .rate_max = 48000,
1365 .channels_min = 1,
1366 .channels_max = 2,
1367 .buffer_bytes_max = (128*1024),
1368 .period_bytes_min = 64,
1369 .period_bytes_max = (128*1024),
1370 .periods_min = 2,
1371 .periods_max = 1024,
1372 .fifo_size = 0,
1373};
1374
1375/* capture on channel B */
1376static struct snd_pcm_hardware snd_cmipci_capture =
1377{
1378 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1379 SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE |
1380 SNDRV_PCM_INFO_RESUME | SNDRV_PCM_INFO_MMAP_VALID),
1381 .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
1382 .rates = SNDRV_PCM_RATE_5512 | SNDRV_PCM_RATE_8000_48000,
1383 .rate_min = 5512,
1384 .rate_max = 48000,
1385 .channels_min = 1,
1386 .channels_max = 2,
1387 .buffer_bytes_max = (128*1024),
1388 .period_bytes_min = 64,
1389 .period_bytes_max = (128*1024),
1390 .periods_min = 2,
1391 .periods_max = 1024,
1392 .fifo_size = 0,
1393};
1394
1395/* playback on channel B - stereo 16bit only? */
1396static struct snd_pcm_hardware snd_cmipci_playback2 =
1397{
1398 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1399 SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE |
1400 SNDRV_PCM_INFO_RESUME | SNDRV_PCM_INFO_MMAP_VALID),
1401 .formats = SNDRV_PCM_FMTBIT_S16_LE,
1402 .rates = SNDRV_PCM_RATE_5512 | SNDRV_PCM_RATE_8000_48000,
1403 .rate_min = 5512,
1404 .rate_max = 48000,
1405 .channels_min = 2,
1406 .channels_max = 2,
1407 .buffer_bytes_max = (128*1024),
1408 .period_bytes_min = 64,
1409 .period_bytes_max = (128*1024),
1410 .periods_min = 2,
1411 .periods_max = 1024,
1412 .fifo_size = 0,
1413};
1414
1415/* spdif playback on channel A */
1416static struct snd_pcm_hardware snd_cmipci_playback_spdif =
1417{
1418 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1419 SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE |
1420 SNDRV_PCM_INFO_RESUME | SNDRV_PCM_INFO_MMAP_VALID),
1421 .formats = SNDRV_PCM_FMTBIT_S16_LE,
1422 .rates = SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000,
1423 .rate_min = 44100,
1424 .rate_max = 48000,
1425 .channels_min = 2,
1426 .channels_max = 2,
1427 .buffer_bytes_max = (128*1024),
1428 .period_bytes_min = 64,
1429 .period_bytes_max = (128*1024),
1430 .periods_min = 2,
1431 .periods_max = 1024,
1432 .fifo_size = 0,
1433};
1434
1435/* spdif playback on channel A (32bit, IEC958 subframes) */
1436static struct snd_pcm_hardware snd_cmipci_playback_iec958_subframe =
1437{
1438 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1439 SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE |
1440 SNDRV_PCM_INFO_RESUME | SNDRV_PCM_INFO_MMAP_VALID),
1441 .formats = SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE,
1442 .rates = SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000,
1443 .rate_min = 44100,
1444 .rate_max = 48000,
1445 .channels_min = 2,
1446 .channels_max = 2,
1447 .buffer_bytes_max = (128*1024),
1448 .period_bytes_min = 64,
1449 .period_bytes_max = (128*1024),
1450 .periods_min = 2,
1451 .periods_max = 1024,
1452 .fifo_size = 0,
1453};
1454
1455/* spdif capture on channel B */
1456static struct snd_pcm_hardware snd_cmipci_capture_spdif =
1457{
1458 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1459 SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE |
1460 SNDRV_PCM_INFO_RESUME | SNDRV_PCM_INFO_MMAP_VALID),
1461 .formats = SNDRV_PCM_FMTBIT_S16_LE,
1462 .rates = SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000,
1463 .rate_min = 44100,
1464 .rate_max = 48000,
1465 .channels_min = 2,
1466 .channels_max = 2,
1467 .buffer_bytes_max = (128*1024),
1468 .period_bytes_min = 64,
1469 .period_bytes_max = (128*1024),
1470 .periods_min = 2,
1471 .periods_max = 1024,
1472 .fifo_size = 0,
1473};
1474
1475
1476/*
1477 * check device open/close
1478 */
1479static int open_device_check(struct cmipci *cm, int mode, struct snd_pcm_substream *subs)
1480{
1481 int ch = mode & CM_OPEN_CH_MASK;
1482
1483 /* FIXME: a file should wait until the device becomes free
1484 * when it's opened on blocking mode. however, since the current
1485 * pcm framework doesn't pass file pointer before actually opened,
1486 * we can't know whether blocking mode or not in open callback..
1487 */
1488 down(&cm->open_mutex);
1489 if (cm->opened[ch]) {
1490 up(&cm->open_mutex);
1491 return -EBUSY;
1492 }
1493 cm->opened[ch] = mode;
1494 cm->channel[ch].substream = subs;
1495 if (! (mode & CM_OPEN_DAC)) {
1496 /* disable dual DAC mode */
1497 cm->channel[ch].is_dac = 0;
1498 spin_lock_irq(&cm->reg_lock);
1499 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_ENDBDAC);
1500 spin_unlock_irq(&cm->reg_lock);
1501 }
1502 up(&cm->open_mutex);
1503 return 0;
1504}
1505
1506static void close_device_check(struct cmipci *cm, int mode)
1507{
1508 int ch = mode & CM_OPEN_CH_MASK;
1509
1510 down(&cm->open_mutex);
1511
1512 if (cm->opened[ch] == mode) {
1513 if (cm->channel[ch].substream) {
1514 snd_cmipci_ch_reset(cm, ch);
1515 cm->channel[ch].running = 0;
1516 cm->channel[ch].substream = NULL;
1517 }
1518 cm->opened[ch] = 0;
1519 if (! cm->channel[ch].is_dac) {
1520 /* enable dual DAC mode again */
1521 cm->channel[ch].is_dac = 1;
1522 spin_lock_irq(&cm->reg_lock);
1523 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_ENDBDAC);
1524 spin_unlock_irq(&cm->reg_lock);
1525 }
1526 }
1527 up(&cm->open_mutex);
1528}
1529
1530/*
1531 */
1532
1533static int snd_cmipci_playback_open(struct snd_pcm_substream *substream)
1534{
1535 struct cmipci *cm = snd_pcm_substream_chip(substream);
1536 struct snd_pcm_runtime *runtime = substream->runtime;
1537 int err;
1538
1539 if ((err = open_device_check(cm, CM_OPEN_PLAYBACK, substream)) < 0)
1540 return err;
1541 runtime->hw = snd_cmipci_playback;
1542 runtime->hw.channels_max = cm->max_channels;
1543 snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 0, 0x10000);
1544 return 0;
1545}
1546
1547static int snd_cmipci_capture_open(struct snd_pcm_substream *substream)
1548{
1549 struct cmipci *cm = snd_pcm_substream_chip(substream);
1550 struct snd_pcm_runtime *runtime = substream->runtime;
1551 int err;
1552
1553 if ((err = open_device_check(cm, CM_OPEN_CAPTURE, substream)) < 0)
1554 return err;
1555 runtime->hw = snd_cmipci_capture;
1556 if (cm->chip_version == 68) { // 8768 only supports 44k/48k recording
1557 runtime->hw.rate_min = 41000;
1558 runtime->hw.rates = SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000;
1559 }
1560 snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 0, 0x10000);
1561 return 0;
1562}
1563
1564static int snd_cmipci_playback2_open(struct snd_pcm_substream *substream)
1565{
1566 struct cmipci *cm = snd_pcm_substream_chip(substream);
1567 struct snd_pcm_runtime *runtime = substream->runtime;
1568 int err;
1569
1570 if ((err = open_device_check(cm, CM_OPEN_PLAYBACK2, substream)) < 0) /* use channel B */
1571 return err;
1572 runtime->hw = snd_cmipci_playback2;
1573 down(&cm->open_mutex);
1574 //if (! cm->opened[CM_CH_PLAY]) {
1575 if (1) { /* f&%$&g uniaud16 doesnt close stream */
1576 if (cm->can_multi_ch) {
1577 runtime->hw.channels_max = cm->max_channels;
1578 if (cm->max_channels == 4)
1579 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, &hw_constraints_channels_4);
1580 else if (cm->max_channels == 6)
1581 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, &hw_constraints_channels_6);
1582 else if (cm->max_channels == 8)
1583 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, &hw_constraints_channels_8);
1584 }
1585 snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 0, 0x10000);
1586 }
1587 up(&cm->open_mutex);
1588// printk("opened: %i, can MC: %i, max ch: %i, hw max ch: %i\n",
1589// cm->opened[CM_CH_PLAY], cm->can_multi_ch, cm->max_channels, runtime->hw.channels_max);
1590 return 0;
1591}
1592
1593static int snd_cmipci_playback_spdif_open(struct snd_pcm_substream *substream)
1594{
1595 struct cmipci *cm = snd_pcm_substream_chip(substream);
1596 struct snd_pcm_runtime *runtime = substream->runtime;
1597 int err;
1598
1599 if ((err = open_device_check(cm, CM_OPEN_SPDIF_PLAYBACK, substream)) < 0) /* use channel A */
1600 return err;
1601 if (cm->can_ac3_hw) {
1602 runtime->hw = snd_cmipci_playback_spdif;
1603 if (cm->chip_version >= 37)
1604 runtime->hw.formats |= SNDRV_PCM_FMTBIT_S32_LE;
1605 } else {
1606 runtime->hw = snd_cmipci_playback_iec958_subframe;
1607 }
1608 snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 0, 0x40000);
1609 cm->dig_pcm_status = cm->dig_status;
1610 return 0;
1611}
1612
1613static int snd_cmipci_capture_spdif_open(struct snd_pcm_substream *substream)
1614{
1615 struct cmipci *cm = snd_pcm_substream_chip(substream);
1616 struct snd_pcm_runtime *runtime = substream->runtime;
1617 int err;
1618
1619 if ((err = open_device_check(cm, CM_OPEN_SPDIF_CAPTURE, substream)) < 0) /* use channel B */
1620 return err;
1621 runtime->hw = snd_cmipci_capture_spdif;
1622 snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 0, 0x40000);
1623 return 0;
1624}
1625
1626
1627/*
1628 */
1629
1630static int snd_cmipci_playback_close(struct snd_pcm_substream *substream)
1631{
1632 struct cmipci *cm = snd_pcm_substream_chip(substream);
1633 close_device_check(cm, CM_OPEN_PLAYBACK);
1634 return 0;
1635}
1636
1637static int snd_cmipci_capture_close(struct snd_pcm_substream *substream)
1638{
1639 struct cmipci *cm = snd_pcm_substream_chip(substream);
1640 close_device_check(cm, CM_OPEN_CAPTURE);
1641 return 0;
1642}
1643
1644static int snd_cmipci_playback2_close(struct snd_pcm_substream *substream)
1645{
1646 struct cmipci *cm = snd_pcm_substream_chip(substream);
1647 close_device_check(cm, CM_OPEN_PLAYBACK2);
1648 close_device_check(cm, CM_OPEN_PLAYBACK_MULTI);
1649 return 0;
1650}
1651
1652static int snd_cmipci_playback_spdif_close(struct snd_pcm_substream *substream)
1653{
1654 struct cmipci *cm = snd_pcm_substream_chip(substream);
1655 close_device_check(cm, CM_OPEN_SPDIF_PLAYBACK);
1656 return 0;
1657}
1658
1659static int snd_cmipci_capture_spdif_close(struct snd_pcm_substream *substream)
1660{
1661 struct cmipci *cm = snd_pcm_substream_chip(substream);
1662 close_device_check(cm, CM_OPEN_SPDIF_CAPTURE);
1663 return 0;
1664}
1665
1666
1667/*
1668 */
1669
1670static struct snd_pcm_ops snd_cmipci_playback_ops = {
1671 .open = snd_cmipci_playback_open,
1672 .close = snd_cmipci_playback_close,
1673 .ioctl = snd_pcm_lib_ioctl,
1674 .hw_params = snd_cmipci_hw_params,
1675 .hw_free = snd_cmipci_playback_hw_free,
1676 .prepare = snd_cmipci_playback_prepare,
1677 .trigger = snd_cmipci_playback_trigger,
1678 .pointer = snd_cmipci_playback_pointer,
1679};
1680
1681static struct snd_pcm_ops snd_cmipci_capture_ops = {
1682 .open = snd_cmipci_capture_open,
1683 .close = snd_cmipci_capture_close,
1684 .ioctl = snd_pcm_lib_ioctl,
1685 .hw_params = snd_cmipci_hw_params,
1686 .hw_free = snd_cmipci_hw_free,
1687 .prepare = snd_cmipci_capture_prepare,
1688 .trigger = snd_cmipci_capture_trigger,
1689 .pointer = snd_cmipci_capture_pointer,
1690};
1691
1692static struct snd_pcm_ops snd_cmipci_playback2_ops = {
1693 .open = snd_cmipci_playback2_open,
1694 .close = snd_cmipci_playback2_close,
1695 .ioctl = snd_pcm_lib_ioctl,
1696 .hw_params = snd_cmipci_playback2_hw_params,
1697 .hw_free = snd_cmipci_hw_free,
1698 .prepare = snd_cmipci_capture_prepare, /* channel B */
1699 .trigger = snd_cmipci_capture_trigger, /* channel B */
1700 .pointer = snd_cmipci_capture_pointer, /* channel B */
1701};
1702
1703static struct snd_pcm_ops snd_cmipci_playback_spdif_ops = {
1704 .open = snd_cmipci_playback_spdif_open,
1705 .close = snd_cmipci_playback_spdif_close,
1706 .ioctl = snd_pcm_lib_ioctl,
1707 .hw_params = snd_cmipci_hw_params,
1708 .hw_free = snd_cmipci_playback_hw_free,
1709 .prepare = snd_cmipci_playback_spdif_prepare, /* set up rate */
1710 .trigger = snd_cmipci_playback_trigger,
1711 .pointer = snd_cmipci_playback_pointer,
1712};
1713
1714static struct snd_pcm_ops snd_cmipci_capture_spdif_ops = {
1715 .open = snd_cmipci_capture_spdif_open,
1716 .close = snd_cmipci_capture_spdif_close,
1717 .ioctl = snd_pcm_lib_ioctl,
1718 .hw_params = snd_cmipci_hw_params,
1719 .hw_free = snd_cmipci_capture_spdif_hw_free,
1720 .prepare = snd_cmipci_capture_spdif_prepare,
1721 .trigger = snd_cmipci_capture_trigger,
1722 .pointer = snd_cmipci_capture_pointer,
1723};
1724
1725/*
1726 */
1727
1728static void snd_cmipci_pcm_free(struct snd_pcm *pcm)
1729{
1730 snd_pcm_lib_preallocate_free_for_all(pcm);
1731}
1732
1733static int __devinit snd_cmipci_pcm_new(struct cmipci *cm, int device)
1734{
1735 struct snd_pcm *pcm;
1736 int err;
1737
1738 err = snd_pcm_new(cm->card, cm->card->driver, device, 1, 1, &pcm);
1739 if (err < 0)
1740 return err;
1741
1742 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cmipci_playback_ops);
1743 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_cmipci_capture_ops);
1744
1745 pcm->private_data = cm;
1746 pcm->private_free = snd_cmipci_pcm_free;
1747 pcm->info_flags = 0;
1748 strcpy(pcm->name, "C-Media PCI DAC/ADC");
1749 cm->pcm = pcm;
1750
1751 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1752 snd_dma_pci_data(cm->pci), 64*1024, 128*1024);
1753
1754 return 0;
1755}
1756
1757static int __devinit snd_cmipci_pcm2_new(struct cmipci *cm, int device)
1758{
1759 struct snd_pcm *pcm;
1760 int err;
1761
1762 err = snd_pcm_new(cm->card, cm->card->driver, device, 1, 0, &pcm);
1763 if (err < 0)
1764 return err;
1765 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cmipci_playback2_ops);
1766 pcm->private_data = cm;
1767 pcm->private_free = snd_cmipci_pcm_free;
1768 pcm->info_flags = 0;
1769 strcpy(pcm->name, "C-Media PCI 2nd DAC");
1770 cm->pcm2 = pcm;
1771
1772 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1773 snd_dma_pci_data(cm->pci), 64*1024, 128*1024);
1774
1775 return 0;
1776}
1777
1778static int __devinit snd_cmipci_pcm_spdif_new(struct cmipci *cm, int device)
1779{
1780 struct snd_pcm *pcm;
1781 int err;
1782
1783 err = snd_pcm_new(cm->card, cm->card->driver, device, 1, 1, &pcm);
1784 if (err < 0)
1785 return err;
1786
1787 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cmipci_playback_spdif_ops);
1788 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_cmipci_capture_spdif_ops);
1789
1790 pcm->private_data = cm;
1791 pcm->private_free = snd_cmipci_pcm_free;
1792 pcm->info_flags = 0;
1793 strcpy(pcm->name, "C-Media PCI IEC958");
1794 cm->pcm_spdif = pcm;
1795
1796 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1797 snd_dma_pci_data(cm->pci), 64*1024, 128*1024);
1798
1799 return 0;
1800}
1801
1802/*
1803 * mixer interface:
1804 * - CM8338/8738 has a compatible mixer interface with SB16, but
1805 * lack of some elements like tone control, i/o gain and AGC.
1806 * - Access to native registers:
1807 * - A 3D switch
1808 * - Output mute switches
1809 */
1810
1811static void snd_cmipci_mixer_write(struct cmipci *s, unsigned char idx, unsigned char data)
1812{
1813 outb(idx, s->iobase + CM_REG_SB16_ADDR);
1814 outb(data, s->iobase + CM_REG_SB16_DATA);
1815}
1816
1817static unsigned char snd_cmipci_mixer_read(struct cmipci *s, unsigned char idx)
1818{
1819 unsigned char v;
1820
1821 outb(idx, s->iobase + CM_REG_SB16_ADDR);
1822 v = inb(s->iobase + CM_REG_SB16_DATA);
1823 return v;
1824}
1825
1826/*
1827 * general mixer element
1828 */
1829struct cmipci_sb_reg {
1830 unsigned int left_reg, right_reg;
1831 unsigned int left_shift, right_shift;
1832 unsigned int mask;
1833 unsigned int invert: 1;
1834 unsigned int stereo: 1;
1835};
1836
1837#define COMPOSE_SB_REG(lreg,rreg,lshift,rshift,mask,invert,stereo) \
1838 ((lreg) | ((rreg) << 8) | (lshift << 16) | (rshift << 19) | (mask << 24) | (invert << 22) | (stereo << 23))
1839
1840#define CMIPCI_DOUBLE(xname, left_reg, right_reg, left_shift, right_shift, mask, invert, stereo) \
1841 { SNDRV_CTL_ELEM_IFACE_MIXER, 0, 0, xname, 0, \
1842 0, 0, snd_cmipci_info_volume, \
1843 snd_cmipci_get_volume, snd_cmipci_put_volume, \
1844 0,\
1845 COMPOSE_SB_REG(left_reg, right_reg, left_shift, right_shift, mask, invert, stereo), \
1846 }
1847
1848#define CMIPCI_SB_VOL_STEREO(xname,reg,shift,mask) CMIPCI_DOUBLE(xname, reg, reg+1, shift, shift, mask, 0, 1)
1849#define CMIPCI_SB_VOL_MONO(xname,reg,shift,mask) CMIPCI_DOUBLE(xname, reg, reg, shift, shift, mask, 0, 0)
1850#define CMIPCI_SB_SW_STEREO(xname,lshift,rshift) CMIPCI_DOUBLE(xname, SB_DSP4_OUTPUT_SW, SB_DSP4_OUTPUT_SW, lshift, rshift, 1, 0, 1)
1851#define CMIPCI_SB_SW_MONO(xname,shift) CMIPCI_DOUBLE(xname, SB_DSP4_OUTPUT_SW, SB_DSP4_OUTPUT_SW, shift, shift, 1, 0, 0)
1852
1853static void cmipci_sb_reg_decode(struct cmipci_sb_reg *r, unsigned long val)
1854{
1855 r->left_reg = val & 0xff;
1856 r->right_reg = (val >> 8) & 0xff;
1857 r->left_shift = (val >> 16) & 0x07;
1858 r->right_shift = (val >> 19) & 0x07;
1859 r->invert = (val >> 22) & 1;
1860 r->stereo = (val >> 23) & 1;
1861 r->mask = (val >> 24) & 0xff;
1862}
1863
1864static int snd_cmipci_info_volume(struct snd_kcontrol *kcontrol,
1865 struct snd_ctl_elem_info *uinfo)
1866{
1867 struct cmipci_sb_reg reg;
1868
1869 cmipci_sb_reg_decode(&reg, kcontrol->private_value);
1870 uinfo->type = reg.mask == 1 ? SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER;
1871 uinfo->count = reg.stereo + 1;
1872 uinfo->value.integer.min = 0;
1873 uinfo->value.integer.max = reg.mask;
1874 return 0;
1875}
1876
1877static int snd_cmipci_get_volume(struct snd_kcontrol *kcontrol,
1878 struct snd_ctl_elem_value *ucontrol)
1879{
1880 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
1881 struct cmipci_sb_reg reg;
1882 int val;
1883
1884 cmipci_sb_reg_decode(&reg, kcontrol->private_value);
1885 spin_lock_irq(&cm->reg_lock);
1886 val = (snd_cmipci_mixer_read(cm, reg.left_reg) >> reg.left_shift) & reg.mask;
1887 if (reg.invert)
1888 val = reg.mask - val;
1889 ucontrol->value.integer.value[0] = val;
1890 if (reg.stereo) {
1891 val = (snd_cmipci_mixer_read(cm, reg.right_reg) >> reg.right_shift) & reg.mask;
1892 if (reg.invert)
1893 val = reg.mask - val;
1894 ucontrol->value.integer.value[1] = val;
1895 }
1896 spin_unlock_irq(&cm->reg_lock);
1897 return 0;
1898}
1899
1900static int snd_cmipci_put_volume(struct snd_kcontrol *kcontrol,
1901 struct snd_ctl_elem_value *ucontrol)
1902{
1903 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
1904 struct cmipci_sb_reg reg;
1905 int change;
1906 int left, right, oleft, oright;
1907
1908 cmipci_sb_reg_decode(&reg, kcontrol->private_value);
1909 left = ucontrol->value.integer.value[0] & reg.mask;
1910 if (reg.invert)
1911 left = reg.mask - left;
1912 left <<= reg.left_shift;
1913 if (reg.stereo) {
1914 right = ucontrol->value.integer.value[1] & reg.mask;
1915 if (reg.invert)
1916 right = reg.mask - right;
1917 right <<= reg.right_shift;
1918 } else
1919 right = 0;
1920 spin_lock_irq(&cm->reg_lock);
1921 oleft = snd_cmipci_mixer_read(cm, reg.left_reg);
1922 left |= oleft & ~(reg.mask << reg.left_shift);
1923 change = left != oleft;
1924 if (reg.stereo) {
1925 if (reg.left_reg != reg.right_reg) {
1926 snd_cmipci_mixer_write(cm, reg.left_reg, left);
1927 oright = snd_cmipci_mixer_read(cm, reg.right_reg);
1928 } else
1929 oright = left;
1930 right |= oright & ~(reg.mask << reg.right_shift);
1931 change |= right != oright;
1932 snd_cmipci_mixer_write(cm, reg.right_reg, right);
1933 } else
1934 snd_cmipci_mixer_write(cm, reg.left_reg, left);
1935 spin_unlock_irq(&cm->reg_lock);
1936 return change;
1937}
1938
1939/*
1940 * input route (left,right) -> (left,right)
1941 */
1942#define CMIPCI_SB_INPUT_SW(xname, left_shift, right_shift) \
1943 { SNDRV_CTL_ELEM_IFACE_MIXER, 0, 0, xname, 0, \
1944 0, 0, snd_cmipci_info_input_sw, \
1945 snd_cmipci_get_input_sw, snd_cmipci_put_input_sw, \
1946 0, \
1947 COMPOSE_SB_REG(SB_DSP4_INPUT_LEFT, SB_DSP4_INPUT_RIGHT, left_shift, right_shift, 1, 0, 1), \
1948 }
1949static int snd_cmipci_info_input_sw(struct snd_kcontrol *kcontrol,
1950 struct snd_ctl_elem_info *uinfo)
1951{
1952 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
1953 uinfo->count = 4;
1954 uinfo->value.integer.min = 0;
1955 uinfo->value.integer.max = 1;
1956 return 0;
1957}
1958
1959static int snd_cmipci_get_input_sw(struct snd_kcontrol *kcontrol,
1960 struct snd_ctl_elem_value *ucontrol)
1961{
1962 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
1963 struct cmipci_sb_reg reg;
1964 int val1, val2;
1965
1966 cmipci_sb_reg_decode(&reg, kcontrol->private_value);
1967 spin_lock_irq(&cm->reg_lock);
1968 val1 = snd_cmipci_mixer_read(cm, reg.left_reg);
1969 val2 = snd_cmipci_mixer_read(cm, reg.right_reg);
1970 spin_unlock_irq(&cm->reg_lock);
1971 ucontrol->value.integer.value[0] = (val1 >> reg.left_shift) & 1;
1972 ucontrol->value.integer.value[1] = (val2 >> reg.left_shift) & 1;
1973 ucontrol->value.integer.value[2] = (val1 >> reg.right_shift) & 1;
1974 ucontrol->value.integer.value[3] = (val2 >> reg.right_shift) & 1;
1975 return 0;
1976}
1977
1978static int snd_cmipci_put_input_sw(struct snd_kcontrol *kcontrol,
1979 struct snd_ctl_elem_value *ucontrol)
1980{
1981 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
1982 struct cmipci_sb_reg reg;
1983 int change;
1984 int val1, val2, oval1, oval2;
1985
1986 cmipci_sb_reg_decode(&reg, kcontrol->private_value);
1987 spin_lock_irq(&cm->reg_lock);
1988 oval1 = snd_cmipci_mixer_read(cm, reg.left_reg);
1989 oval2 = snd_cmipci_mixer_read(cm, reg.right_reg);
1990 val1 = oval1 & ~((1 << reg.left_shift) | (1 << reg.right_shift));
1991 val2 = oval2 & ~((1 << reg.left_shift) | (1 << reg.right_shift));
1992 val1 |= (ucontrol->value.integer.value[0] & 1) << reg.left_shift;
1993 val2 |= (ucontrol->value.integer.value[1] & 1) << reg.left_shift;
1994 val1 |= (ucontrol->value.integer.value[2] & 1) << reg.right_shift;
1995 val2 |= (ucontrol->value.integer.value[3] & 1) << reg.right_shift;
1996 change = val1 != oval1 || val2 != oval2;
1997 snd_cmipci_mixer_write(cm, reg.left_reg, val1);
1998 snd_cmipci_mixer_write(cm, reg.right_reg, val2);
1999 spin_unlock_irq(&cm->reg_lock);
2000 return change;
2001}
2002
2003/*
2004 * native mixer switches/volumes
2005 */
2006
2007#define CMIPCI_MIXER_SW_STEREO(xname, reg, lshift, rshift, invert) \
2008 { SNDRV_CTL_ELEM_IFACE_MIXER, 0, 0, xname, 0, \
2009 0, 0, snd_cmipci_info_native_mixer, \
2010 snd_cmipci_get_native_mixer, snd_cmipci_put_native_mixer, \
2011 0, \
2012 COMPOSE_SB_REG(reg, reg, lshift, rshift, 1, invert, 1), \
2013 }
2014
2015#define CMIPCI_MIXER_SW_MONO(xname, reg, shift, invert) \
2016 { SNDRV_CTL_ELEM_IFACE_MIXER, 0, 0, xname, 0, \
2017 0, 0, snd_cmipci_info_native_mixer, \
2018 snd_cmipci_get_native_mixer, snd_cmipci_put_native_mixer, \
2019 0, \
2020 COMPOSE_SB_REG(reg, reg, shift, shift, 1, invert, 0), \
2021 }
2022
2023#define CMIPCI_MIXER_VOL_STEREO(xname, reg, lshift, rshift, mask) \
2024 { SNDRV_CTL_ELEM_IFACE_MIXER, 0, 0, xname, 0, \
2025 0, 0, snd_cmipci_info_native_mixer, \
2026 snd_cmipci_get_native_mixer, snd_cmipci_put_native_mixer, \
2027 0, \
2028 COMPOSE_SB_REG(reg, reg, lshift, rshift, mask, 0, 1), \
2029 }
2030
2031#define CMIPCI_MIXER_VOL_MONO(xname, reg, shift, mask) \
2032 { SNDRV_CTL_ELEM_IFACE_MIXER, 0, 0, xname, 0, \
2033 0, 0, snd_cmipci_info_native_mixer, \
2034 snd_cmipci_get_native_mixer, snd_cmipci_put_native_mixer, \
2035 0, \
2036 COMPOSE_SB_REG(reg, reg, shift, shift, mask, 0, 0), \
2037 }
2038
2039static int snd_cmipci_info_native_mixer(struct snd_kcontrol *kcontrol,
2040 struct snd_ctl_elem_info *uinfo)
2041{
2042 struct cmipci_sb_reg reg;
2043
2044 cmipci_sb_reg_decode(&reg, kcontrol->private_value);
2045 uinfo->type = reg.mask == 1 ? SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER;
2046 uinfo->count = reg.stereo + 1;
2047 uinfo->value.integer.min = 0;
2048 uinfo->value.integer.max = reg.mask;
2049 return 0;
2050
2051}
2052
2053static int snd_cmipci_get_native_mixer(struct snd_kcontrol *kcontrol,
2054 struct snd_ctl_elem_value *ucontrol)
2055{
2056 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2057 struct cmipci_sb_reg reg;
2058 unsigned char oreg, val;
2059
2060 cmipci_sb_reg_decode(&reg, kcontrol->private_value);
2061 spin_lock_irq(&cm->reg_lock);
2062 oreg = inb(cm->iobase + reg.left_reg);
2063 val = (oreg >> reg.left_shift) & reg.mask;
2064 if (reg.invert)
2065 val = reg.mask - val;
2066 ucontrol->value.integer.value[0] = val;
2067 if (reg.stereo) {
2068 val = (oreg >> reg.right_shift) & reg.mask;
2069 if (reg.invert)
2070 val = reg.mask - val;
2071 ucontrol->value.integer.value[1] = val;
2072 }
2073 spin_unlock_irq(&cm->reg_lock);
2074 return 0;
2075}
2076
2077static int snd_cmipci_put_native_mixer(struct snd_kcontrol *kcontrol,
2078 struct snd_ctl_elem_value *ucontrol)
2079{
2080 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2081 struct cmipci_sb_reg reg;
2082 unsigned char oreg, nreg, val;
2083
2084 cmipci_sb_reg_decode(&reg, kcontrol->private_value);
2085 spin_lock_irq(&cm->reg_lock);
2086 oreg = inb(cm->iobase + reg.left_reg);
2087 val = ucontrol->value.integer.value[0] & reg.mask;
2088 if (reg.invert)
2089 val = reg.mask - val;
2090 nreg = oreg & ~(reg.mask << reg.left_shift);
2091 nreg |= (val << reg.left_shift);
2092 if (reg.stereo) {
2093 val = ucontrol->value.integer.value[1] & reg.mask;
2094 if (reg.invert)
2095 val = reg.mask - val;
2096 nreg &= ~(reg.mask << reg.right_shift);
2097 nreg |= (val << reg.right_shift);
2098 }
2099 outb(nreg, cm->iobase + reg.left_reg);
2100 spin_unlock_irq(&cm->reg_lock);
2101 return (nreg != oreg);
2102}
2103
2104/*
2105 * special case - check mixer sensitivity
2106 */
2107static int snd_cmipci_get_native_mixer_sensitive(struct snd_kcontrol *kcontrol,
2108 struct snd_ctl_elem_value *ucontrol)
2109{
2110 //struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2111 return snd_cmipci_get_native_mixer(kcontrol, ucontrol);
2112}
2113
2114static int snd_cmipci_put_native_mixer_sensitive(struct snd_kcontrol *kcontrol,
2115 struct snd_ctl_elem_value *ucontrol)
2116{
2117 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2118 if (cm->mixer_insensitive) {
2119 /* ignored */
2120 return 0;
2121 }
2122 return snd_cmipci_put_native_mixer(kcontrol, ucontrol);
2123}
2124
2125static struct snd_kcontrol_new snd_cmipci_mixers[] __devinitdata = {
2126 CMIPCI_SB_VOL_STEREO("Master Playback Volume", SB_DSP4_MASTER_DEV, 3, 31),
2127 CMIPCI_MIXER_SW_MONO("3D Control - Switch", CM_REG_MIXER1, CM_X3DEN_SHIFT, 0),
2128 CMIPCI_SB_VOL_STEREO("PCM Playback Volume", SB_DSP4_PCM_DEV, 3, 31),
2129 //CMIPCI_MIXER_SW_MONO("PCM Playback Switch", CM_REG_MIXER1, CM_WSMUTE_SHIFT, 1),
2130 { /* switch with sensitivity */
2131 SNDRV_CTL_ELEM_IFACE_MIXER,0,0,
2132 "PCM Playback Switch",0,0,0,
2133 snd_cmipci_info_native_mixer,
2134 snd_cmipci_get_native_mixer_sensitive,
2135 snd_cmipci_put_native_mixer_sensitive,
2136 0,
2137 COMPOSE_SB_REG(CM_REG_MIXER1, CM_REG_MIXER1, CM_WSMUTE_SHIFT, CM_WSMUTE_SHIFT, 1, 1, 0),
2138 },
2139 CMIPCI_MIXER_SW_STEREO("PCM Capture Switch", CM_REG_MIXER1, CM_WAVEINL_SHIFT, CM_WAVEINR_SHIFT, 0),
2140 CMIPCI_SB_VOL_STEREO("Synth Playback Volume", SB_DSP4_SYNTH_DEV, 3, 31),
2141 CMIPCI_MIXER_SW_MONO("Synth Playback Switch", CM_REG_MIXER1, CM_FMMUTE_SHIFT, 1),
2142 CMIPCI_SB_INPUT_SW("Synth Capture Route", 6, 5),
2143 CMIPCI_SB_VOL_STEREO("CD Playback Volume", SB_DSP4_CD_DEV, 3, 31),
2144 CMIPCI_SB_SW_STEREO("CD Playback Switch", 2, 1),
2145 CMIPCI_SB_INPUT_SW("CD Capture Route", 2, 1),
2146 CMIPCI_SB_VOL_STEREO("Line Playback Volume", SB_DSP4_LINE_DEV, 3, 31),
2147 CMIPCI_SB_SW_STEREO("Line Playback Switch", 4, 3),
2148 CMIPCI_SB_INPUT_SW("Line Capture Route", 4, 3),
2149 CMIPCI_SB_VOL_MONO("Mic Playback Volume", SB_DSP4_MIC_DEV, 3, 31),
2150 CMIPCI_SB_SW_MONO("Mic Playback Switch", 0),
2151 CMIPCI_DOUBLE("Mic Capture Switch", SB_DSP4_INPUT_LEFT, SB_DSP4_INPUT_RIGHT, 0, 0, 1, 0, 0),
2152 CMIPCI_SB_VOL_MONO("PC Speaker Playback Volume", SB_DSP4_SPEAKER_DEV, 6, 3),
2153 CMIPCI_MIXER_VOL_STEREO("Aux Playback Volume", CM_REG_AUX_VOL, 4, 0, 15),
2154 CMIPCI_MIXER_SW_STEREO("Aux Playback Switch", CM_REG_MIXER2, CM_VAUXLM_SHIFT, CM_VAUXRM_SHIFT, 0),
2155 CMIPCI_MIXER_SW_STEREO("Aux Capture Switch", CM_REG_MIXER2, CM_RAUXLEN_SHIFT, CM_RAUXREN_SHIFT, 0),
2156 CMIPCI_MIXER_SW_MONO("Mic Boost Playback Switch", CM_REG_MIXER2, CM_MICGAINZ_SHIFT, 1),
2157 CMIPCI_MIXER_VOL_MONO("Mic Capture Volume", CM_REG_MIXER2, CM_VADMIC_SHIFT, 7),
2158 CMIPCI_SB_VOL_MONO("Phone Playback Volume", CM_REG_EXTENT_IND, 5, 7),
2159 CMIPCI_DOUBLE("Phone Playback Switch", CM_REG_EXTENT_IND, CM_REG_EXTENT_IND, 4, 4, 1, 0, 0),
2160 CMIPCI_DOUBLE("PC Speaker Playback Switch", CM_REG_EXTENT_IND, CM_REG_EXTENT_IND, 3, 3, 1, 0, 0),
2161 CMIPCI_DOUBLE("Mic Boost Capture Switch", CM_REG_EXTENT_IND, CM_REG_EXTENT_IND, 0, 0, 1, 0, 0),
2162};
2163
2164/*
2165 * other switches
2166 */
2167
2168struct cmipci_switch_args {
2169 int reg; /* register index */
2170 unsigned int mask; /* mask bits */
2171 unsigned int mask_on; /* mask bits to turn on */
2172 int is_byte: 1; /* byte access? */
2173 unsigned int ac3_sensitive: 1; /* access forbidden during
2174 * non-audio operation?
2175 */
2176};
2177
2178static int snd_cmipci_uswitch_info(struct snd_kcontrol *kcontrol,
2179 struct snd_ctl_elem_info *uinfo)
2180{
2181 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
2182 uinfo->count = 1;
2183 uinfo->value.integer.min = 0;
2184 uinfo->value.integer.max = 1;
2185 return 0;
2186}
2187
2188static int _snd_cmipci_uswitch_get(struct snd_kcontrol *kcontrol,
2189 struct snd_ctl_elem_value *ucontrol,
2190 struct cmipci_switch_args *args)
2191{
2192 unsigned int val;
2193 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2194
2195 spin_lock_irq(&cm->reg_lock);
2196 if (args->ac3_sensitive && cm->mixer_insensitive) {
2197 ucontrol->value.integer.value[0] = 0;
2198 spin_unlock_irq(&cm->reg_lock);
2199 return 0;
2200 }
2201 if (args->is_byte)
2202 val = inb(cm->iobase + args->reg);
2203 else
2204 val = snd_cmipci_read(cm, args->reg);
2205 ucontrol->value.integer.value[0] = ((val & args->mask) == args->mask_on) ? 1 : 0;
2206 spin_unlock_irq(&cm->reg_lock);
2207 return 0;
2208}
2209
2210static int snd_cmipci_uswitch_get(struct snd_kcontrol *kcontrol,
2211 struct snd_ctl_elem_value *ucontrol)
2212{
2213 struct cmipci_switch_args *args;
2214 args = (struct cmipci_switch_args *)kcontrol->private_value;
2215 snd_assert(args != NULL, return -EINVAL);
2216 return _snd_cmipci_uswitch_get(kcontrol, ucontrol, args);
2217}
2218
2219static int _snd_cmipci_uswitch_put(struct snd_kcontrol *kcontrol,
2220 struct snd_ctl_elem_value *ucontrol,
2221 struct cmipci_switch_args *args)
2222{
2223 unsigned int val;
2224 int change;
2225 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2226
2227 spin_lock_irq(&cm->reg_lock);
2228 if (args->ac3_sensitive && cm->mixer_insensitive) {
2229 /* ignored */
2230 spin_unlock_irq(&cm->reg_lock);
2231 return 0;
2232 }
2233 if (args->is_byte)
2234 val = inb(cm->iobase + args->reg);
2235 else
2236 val = snd_cmipci_read(cm, args->reg);
2237 change = (val & args->mask) != (ucontrol->value.integer.value[0] ? args->mask : 0);
2238 if (change) {
2239 val &= ~args->mask;
2240 if (ucontrol->value.integer.value[0])
2241 val |= args->mask_on;
2242 else
2243 val |= (args->mask & ~args->mask_on);
2244 if (args->is_byte)
2245 outb((unsigned char)val, cm->iobase + args->reg);
2246 else
2247 snd_cmipci_write(cm, args->reg, val);
2248 }
2249 spin_unlock_irq(&cm->reg_lock);
2250 return change;
2251}
2252
2253static int snd_cmipci_uswitch_put(struct snd_kcontrol *kcontrol,
2254 struct snd_ctl_elem_value *ucontrol)
2255{
2256 struct cmipci_switch_args *args;
2257 args = (struct cmipci_switch_args *)kcontrol->private_value;
2258 snd_assert(args != NULL, return -EINVAL);
2259 return _snd_cmipci_uswitch_put(kcontrol, ucontrol, args);
2260}
2261
2262#define DEFINE_SWITCH_ARG(sname, xreg, xmask, xmask_on, xis_byte, xac3) \
2263 static struct cmipci_switch_args cmipci_switch_arg_##sname = { \
2264 xreg, \
2265 xmask, \
2266 xmask_on, \
2267 xis_byte, \
2268 xac3, \
2269 }
2270
2271#define DEFINE_BIT_SWITCH_ARG(sname, xreg, xmask, xis_byte, xac3) \
2272 DEFINE_SWITCH_ARG(sname, xreg, xmask, xmask, xis_byte, xac3)
2273
2274#if 0 /* these will be controlled in pcm device */
2275DEFINE_BIT_SWITCH_ARG(spdif_in, CM_REG_FUNCTRL1, CM_SPDF_1, 0, 0);
2276DEFINE_BIT_SWITCH_ARG(spdif_out, CM_REG_FUNCTRL1, CM_SPDF_0, 0, 0);
2277#endif
2278DEFINE_BIT_SWITCH_ARG(spdif_in_sel1, CM_REG_CHFORMAT, CM_SPDIF_SELECT1, 0, 0);
2279DEFINE_BIT_SWITCH_ARG(spdif_in_sel2, CM_REG_MISC_CTRL, CM_SPDIF_SELECT2, 0, 0);
2280DEFINE_BIT_SWITCH_ARG(spdif_enable, CM_REG_LEGACY_CTRL, CM_ENSPDOUT, 0, 0);
2281DEFINE_BIT_SWITCH_ARG(spdo2dac, CM_REG_FUNCTRL1, CM_SPDO2DAC, 0, 1);
2282DEFINE_BIT_SWITCH_ARG(spdi_valid, CM_REG_MISC, CM_SPDVALID, 1, 0);
2283DEFINE_BIT_SWITCH_ARG(spdif_copyright, CM_REG_LEGACY_CTRL, CM_SPDCOPYRHT, 0, 0);
2284DEFINE_BIT_SWITCH_ARG(spdif_dac_out, CM_REG_LEGACY_CTRL, CM_DAC2SPDO, 0, 1);
2285DEFINE_SWITCH_ARG(spdo_5v, CM_REG_MISC_CTRL, CM_SPDO5V, 0, 0, 0); /* inverse: 0 = 5V */
2286// DEFINE_BIT_SWITCH_ARG(spdo_48k, CM_REG_MISC_CTRL, CM_SPDF_AC97|CM_SPDIF48K, 0, 1);
2287DEFINE_BIT_SWITCH_ARG(spdif_loop, CM_REG_FUNCTRL1, CM_SPDFLOOP, 0, 1);
2288DEFINE_BIT_SWITCH_ARG(spdi_monitor, CM_REG_MIXER1, CM_CDPLAY, 1, 0);
2289/* DEFINE_BIT_SWITCH_ARG(spdi_phase, CM_REG_CHFORMAT, CM_SPDIF_INVERSE, 0, 0); */
2290DEFINE_BIT_SWITCH_ARG(spdi_phase, CM_REG_MISC, CM_SPDIF_INVERSE, 1, 0);
2291DEFINE_BIT_SWITCH_ARG(spdi_phase2, CM_REG_CHFORMAT, CM_SPDIF_INVERSE2, 0, 0);
2292#if CM_CH_PLAY == 1
2293DEFINE_SWITCH_ARG(exchange_dac, CM_REG_MISC_CTRL, CM_XCHGDAC, 0, 0, 0); /* reversed */
2294#else
2295DEFINE_SWITCH_ARG(exchange_dac, CM_REG_MISC_CTRL, CM_XCHGDAC, CM_XCHGDAC, 0, 0);
2296#endif
2297DEFINE_BIT_SWITCH_ARG(fourch, CM_REG_MISC_CTRL, CM_N4SPK3D, 0, 0);
2298DEFINE_BIT_SWITCH_ARG(line_rear, CM_REG_MIXER1, CM_SPK4, 1, 0);
2299DEFINE_BIT_SWITCH_ARG(line_bass, CM_REG_LEGACY_CTRL, CM_LINE_AS_BASS, 0, 0);
2300DEFINE_BIT_SWITCH_ARG(joystick, CM_REG_FUNCTRL1, CM_JYSTK_EN, 0, 0);
2301DEFINE_SWITCH_ARG(modem, CM_REG_MISC_CTRL, CM_FLINKON|CM_FLINKOFF, CM_FLINKON, 0, 0);
2302
2303//Can't compile in non-KEE mode without extra pointer in structure
2304//(watcom complains it can't convert a far ptr to ulong even though it's
2305// safe to do so in this case)
2306#define DEFINE_SWITCH(sname, stype, sarg) \
2307 { stype, 0, 0, \
2308 sname, 0, 0, 0, \
2309 snd_cmipci_uswitch_info, \
2310 snd_cmipci_uswitch_get, \
2311 snd_cmipci_uswitch_put, \
2312 0, \
2313 (unsigned long)&cmipci_switch_arg_##sarg,\
2314 }
2315
2316#define DEFINE_CARD_SWITCH(sname, sarg) DEFINE_SWITCH(sname, SNDRV_CTL_ELEM_IFACE_CARD, sarg)
2317#define DEFINE_MIXER_SWITCH(sname, sarg) DEFINE_SWITCH(sname, SNDRV_CTL_ELEM_IFACE_MIXER, sarg)
2318
2319
2320/*
2321 * callbacks for spdif output switch
2322 * needs toggle two registers..
2323 */
2324static int snd_cmipci_spdout_enable_get(struct snd_kcontrol *kcontrol,
2325 struct snd_ctl_elem_value *ucontrol)
2326{
2327 int changed;
2328 changed = _snd_cmipci_uswitch_get(kcontrol, ucontrol, &cmipci_switch_arg_spdif_enable);
2329 changed |= _snd_cmipci_uswitch_get(kcontrol, ucontrol, &cmipci_switch_arg_spdo2dac);
2330 return changed;
2331}
2332
2333static int snd_cmipci_spdout_enable_put(struct snd_kcontrol *kcontrol,
2334 struct snd_ctl_elem_value *ucontrol)
2335{
2336 struct cmipci *chip = snd_kcontrol_chip(kcontrol);
2337 int changed;
2338 changed = _snd_cmipci_uswitch_put(kcontrol, ucontrol, &cmipci_switch_arg_spdif_enable);
2339 changed |= _snd_cmipci_uswitch_put(kcontrol, ucontrol, &cmipci_switch_arg_spdo2dac);
2340 if (changed) {
2341 if (ucontrol->value.integer.value[0]) {
2342 if (chip->spdif_playback_avail)
2343 snd_cmipci_set_bit(chip, CM_REG_FUNCTRL1, CM_PLAYBACK_SPDF);
2344 } else {
2345 if (chip->spdif_playback_avail)
2346 snd_cmipci_clear_bit(chip, CM_REG_FUNCTRL1, CM_PLAYBACK_SPDF);
2347 }
2348 }
2349 chip->spdif_playback_enabled = ucontrol->value.integer.value[0];
2350 return changed;
2351}
2352
2353static int snd_cmipci_line_in_mode_info(struct snd_kcontrol *kcontrol,
2354 struct snd_ctl_elem_info *uinfo)
2355{
2356 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2357 static char *texts[3] = { "Line-In", "Rear Output", "Bass Output" };
2358 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2359 uinfo->count = 1;
2360 uinfo->value.enumerated.items = cm->chip_version >= 39 ? 3 : 2;
2361 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
2362 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
2363 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
2364 return 0;
2365}
2366
2367static inline unsigned int get_line_in_mode(struct cmipci *cm)
2368{
2369 unsigned int val;
2370 if (cm->chip_version >= 39) {
2371 val = snd_cmipci_read(cm, CM_REG_LEGACY_CTRL);
2372 if (val & CM_LINE_AS_BASS)
2373 return 2;
2374 }
2375 val = snd_cmipci_read_b(cm, CM_REG_MIXER1);
2376 if (val & CM_SPK4)
2377 return 1;
2378 return 0;
2379}
2380
2381static int snd_cmipci_line_in_mode_get(struct snd_kcontrol *kcontrol,
2382 struct snd_ctl_elem_value *ucontrol)
2383{
2384 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2385
2386 spin_lock_irq(&cm->reg_lock);
2387 ucontrol->value.enumerated.item[0] = get_line_in_mode(cm);
2388 spin_unlock_irq(&cm->reg_lock);
2389 return 0;
2390}
2391
2392static int snd_cmipci_line_in_mode_put(struct snd_kcontrol *kcontrol,
2393 struct snd_ctl_elem_value *ucontrol)
2394{
2395 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2396 int change;
2397
2398 spin_lock_irq(&cm->reg_lock);
2399 if (ucontrol->value.enumerated.item[0] == 2)
2400 change = snd_cmipci_set_bit(cm, CM_REG_LEGACY_CTRL, CM_LINE_AS_BASS);
2401 else
2402 change = snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_LINE_AS_BASS);
2403 if (ucontrol->value.enumerated.item[0] == 1)
2404 change |= snd_cmipci_set_bit_b(cm, CM_REG_MIXER1, CM_SPK4);
2405 else
2406 change |= snd_cmipci_clear_bit_b(cm, CM_REG_MIXER1, CM_SPK4);
2407 spin_unlock_irq(&cm->reg_lock);
2408 return change;
2409}
2410
2411static int snd_cmipci_mic_in_mode_info(struct snd_kcontrol *kcontrol,
2412 struct snd_ctl_elem_info *uinfo)
2413{
2414 static char *texts[2] = { "Mic-In", "Center/LFE Output" };
2415 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2416 uinfo->count = 1;
2417 uinfo->value.enumerated.items = 2;
2418 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
2419 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
2420 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
2421 return 0;
2422}
2423
2424static int snd_cmipci_mic_in_mode_get(struct snd_kcontrol *kcontrol,
2425 struct snd_ctl_elem_value *ucontrol)
2426{
2427 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2428 /* same bit as spdi_phase */
2429 spin_lock_irq(&cm->reg_lock);
2430 ucontrol->value.enumerated.item[0] =
2431 (snd_cmipci_read_b(cm, CM_REG_MISC) & CM_SPDIF_INVERSE) ? 1 : 0;
2432 spin_unlock_irq(&cm->reg_lock);
2433 return 0;
2434}
2435
2436static int snd_cmipci_mic_in_mode_put(struct snd_kcontrol *kcontrol,
2437 struct snd_ctl_elem_value *ucontrol)
2438{
2439 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2440 int change;
2441
2442 spin_lock_irq(&cm->reg_lock);
2443 if (ucontrol->value.enumerated.item[0])
2444 change = snd_cmipci_set_bit_b(cm, CM_REG_MISC, CM_SPDIF_INVERSE);
2445 else
2446 change = snd_cmipci_clear_bit_b(cm, CM_REG_MISC, CM_SPDIF_INVERSE);
2447 spin_unlock_irq(&cm->reg_lock);
2448 return change;
2449}
2450
2451/* both for CM8338/8738 */
2452static struct snd_kcontrol_new snd_cmipci_mixer_switches[] __devinitdata = {
2453 DEFINE_MIXER_SWITCH("Four Channel Mode", fourch),
2454 {
2455 .name = "Line-In Mode",
2456 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2457 .info = snd_cmipci_line_in_mode_info,
2458 .get = snd_cmipci_line_in_mode_get,
2459 .put = snd_cmipci_line_in_mode_put,
2460 },
2461};
2462
2463/* for non-multichannel chips */
2464static struct snd_kcontrol_new snd_cmipci_nomulti_switch __devinitdata =
2465DEFINE_MIXER_SWITCH("Exchange DAC", exchange_dac);
2466
2467/* only for CM8738 */
2468static struct snd_kcontrol_new snd_cmipci_8738_mixer_switches[] __devinitdata = {
2469#if 0 /* controlled in pcm device */
2470 DEFINE_MIXER_SWITCH("IEC958 In Record", spdif_in),
2471 DEFINE_MIXER_SWITCH("IEC958 Out", spdif_out),
2472 DEFINE_MIXER_SWITCH("IEC958 Out To DAC", spdo2dac),
2473#endif
2474 // DEFINE_MIXER_SWITCH("IEC958 Output Switch", spdif_enable),
2475 {
2476 SNDRV_CTL_ELEM_IFACE_MIXER,0,0,
2477 "IEC958 Output Switch",0,0, 0,
2478 snd_cmipci_uswitch_info,
2479 snd_cmipci_spdout_enable_get,
2480 snd_cmipci_spdout_enable_put,0
2481 },
2482 DEFINE_MIXER_SWITCH("IEC958 In Valid", spdi_valid),
2483 DEFINE_MIXER_SWITCH("IEC958 Copyright", spdif_copyright),
2484 DEFINE_MIXER_SWITCH("IEC958 5V", spdo_5v),
2485 // DEFINE_MIXER_SWITCH("IEC958 In/Out 48KHz", spdo_48k),
2486 DEFINE_MIXER_SWITCH("IEC958 Loop", spdif_loop),
2487 DEFINE_MIXER_SWITCH("IEC958 In Monitor", spdi_monitor),
2488};
2489
2490/* only for model 033/037 */
2491static struct snd_kcontrol_new snd_cmipci_old_mixer_switches[] __devinitdata = {
2492 DEFINE_MIXER_SWITCH("IEC958 Mix Analog", spdif_dac_out),
2493 DEFINE_MIXER_SWITCH("IEC958 In Phase Inverse", spdi_phase),
2494 DEFINE_MIXER_SWITCH("IEC958 In Select", spdif_in_sel1),
2495};
2496
2497/* only for model 039 or later */
2498static struct snd_kcontrol_new snd_cmipci_extra_mixer_switches[] __devinitdata = {
2499 DEFINE_MIXER_SWITCH("IEC958 In Select", spdif_in_sel2),
2500 DEFINE_MIXER_SWITCH("IEC958 In Phase Inverse", spdi_phase2),
2501 {
2502 .name = "Mic-In Mode",
2503 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2504 .info = snd_cmipci_mic_in_mode_info,
2505 .get = snd_cmipci_mic_in_mode_get,
2506 .put = snd_cmipci_mic_in_mode_put,
2507 }
2508};
2509
2510/* card control switches */
2511static struct snd_kcontrol_new snd_cmipci_control_switches[] __devinitdata = {
2512 DEFINE_CARD_SWITCH("Joystick", joystick),
2513 DEFINE_CARD_SWITCH("Modem", modem),
2514};
2515
2516static int __devinit snd_cmipci_mixer_new(struct cmipci *cm, int pcm_spdif_device)
2517{
2518 struct snd_card *card;
2519 struct snd_kcontrol_new *sw;
2520 struct snd_kcontrol *kctl;
2521 unsigned int idx;
2522 int err;
2523
2524 snd_assert(cm != NULL && cm->card != NULL, return -EINVAL);
2525
2526 card = cm->card;
2527
2528 strcpy(card->mixername, "CMedia PCI");
2529
2530 spin_lock_irq(&cm->reg_lock);
2531 snd_cmipci_mixer_write(cm, 0x00, 0x00); /* mixer reset */
2532 spin_unlock_irq(&cm->reg_lock);
2533
2534 for (idx = 0; idx < ARRAY_SIZE(snd_cmipci_mixers); idx++) {
2535 if (cm->chip_version == 68) { // 8768 has no PCM volume
2536 if (!strcmp(snd_cmipci_mixers[idx].name,
2537 "PCM Playback Volume"))
2538 continue;
2539 }
2540 if ((err = snd_ctl_add(card, snd_ctl_new1(&snd_cmipci_mixers[idx], cm))) < 0)
2541 return err;
2542 }
2543
2544 /* mixer switches */
2545 sw = snd_cmipci_mixer_switches;
2546 for (idx = 0; idx < ARRAY_SIZE(snd_cmipci_mixer_switches); idx++, sw++) {
2547 err = snd_ctl_add(cm->card, snd_ctl_new1(sw, cm));
2548 if (err < 0)
2549 return err;
2550 }
2551 if (! cm->can_multi_ch) {
2552 err = snd_ctl_add(cm->card, snd_ctl_new1(&snd_cmipci_nomulti_switch, cm));
2553 if (err < 0)
2554 return err;
2555 }
2556 if (cm->device == PCI_DEVICE_ID_CMEDIA_CM8738 ||
2557 cm->device == PCI_DEVICE_ID_CMEDIA_CM8738B) {
2558 sw = snd_cmipci_8738_mixer_switches;
2559 for (idx = 0; idx < ARRAY_SIZE(snd_cmipci_8738_mixer_switches); idx++, sw++) {
2560 err = snd_ctl_add(cm->card, snd_ctl_new1(sw, cm));
2561 if (err < 0)
2562 return err;
2563 }
2564 if (cm->can_ac3_hw) {
2565 if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_cmipci_spdif_default, cm))) < 0)
2566 return err;
2567 kctl->id.device = pcm_spdif_device;
2568 if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_cmipci_spdif_mask, cm))) < 0)
2569 return err;
2570 kctl->id.device = pcm_spdif_device;
2571 if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_cmipci_spdif_stream, cm))) < 0)
2572 return err;
2573 kctl->id.device = pcm_spdif_device;
2574 }
2575 if (cm->chip_version <= 37) {
2576 sw = snd_cmipci_old_mixer_switches;
2577 for (idx = 0; idx < ARRAY_SIZE(snd_cmipci_old_mixer_switches); idx++, sw++) {
2578 err = snd_ctl_add(cm->card, snd_ctl_new1(sw, cm));
2579 if (err < 0)
2580 return err;
2581 }
2582 }
2583 }
2584 if (cm->chip_version >= 39) {
2585 sw = snd_cmipci_extra_mixer_switches;
2586 for (idx = 0; idx < ARRAY_SIZE(snd_cmipci_extra_mixer_switches); idx++, sw++) {
2587 err = snd_ctl_add(cm->card, snd_ctl_new1(sw, cm));
2588 if (err < 0)
2589 return err;
2590 }
2591 }
2592
2593 /* card switches */
2594 sw = snd_cmipci_control_switches;
2595 for (idx = 0; idx < ARRAY_SIZE(snd_cmipci_control_switches); idx++, sw++) {
2596 err = snd_ctl_add(cm->card, snd_ctl_new1(sw, cm));
2597 if (err < 0)
2598 return err;
2599 }
2600
2601 for (idx = 0; idx < CM_SAVED_MIXERS; idx++) {
2602 struct snd_ctl_elem_id id;
2603 struct snd_kcontrol *ctl;
2604 memset(&id, 0, sizeof(id));
2605 id.iface = SNDRV_CTL_ELEM_IFACE_MIXER;
2606 strcpy(id.name, cm_saved_mixer[idx].name);
2607 if ((ctl = snd_ctl_find_id(cm->card, &id)) != NULL)
2608 cm->mixer_res_ctl[idx] = ctl;
2609 }
2610
2611 return 0;
2612}
2613
2614
2615/*
2616 * proc interface
2617 */
2618
2619static void snd_cmipci_proc_read(struct snd_info_entry *entry,
2620 struct snd_info_buffer *buffer)
2621{
2622 struct cmipci *cm = entry->private_data;
2623 int i;
2624
2625 snd_iprintf(buffer, "%s\n\n", cm->card->longname);
2626 for (i = 0; i < 0x40; i++) {
2627 int v = inb(cm->iobase + i);
2628 if (i % 4 == 0)
2629 snd_iprintf(buffer, "%02x: ", i);
2630 snd_iprintf(buffer, "%02x", v);
2631 if (i % 4 == 3)
2632 snd_iprintf(buffer, "\n");
2633 else
2634 snd_iprintf(buffer, " ");
2635 }
2636}
2637
2638static void __devinit snd_cmipci_proc_init(struct cmipci *cm)
2639{
2640 struct snd_info_entry *entry;
2641 if (! snd_card_proc_new(cm->card, "cmipci", &entry))
2642 snd_info_set_text_ops(entry, cm, 1024, snd_cmipci_proc_read);
2643}
2644
2645static struct pci_device_id snd_cmipci_ids[] __devinitdata = {
2646 {PCI_VENDOR_ID_CMEDIA, PCI_DEVICE_ID_CMEDIA_CM8338A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
2647 {PCI_VENDOR_ID_CMEDIA, PCI_DEVICE_ID_CMEDIA_CM8338B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
2648 {PCI_VENDOR_ID_CMEDIA, PCI_DEVICE_ID_CMEDIA_CM8738, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
2649 {PCI_VENDOR_ID_CMEDIA, PCI_DEVICE_ID_CMEDIA_CM8738B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
2650 {PCI_VENDOR_ID_AL, PCI_DEVICE_ID_CMEDIA_CM8738, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
2651 {0,},
2652};
2653
2654
2655/*
2656 * check chip version and capabilities
2657 * driver name is modified according to the chip model
2658 */
2659static void __devinit query_chip(struct cmipci *cm)
2660{
2661 unsigned int detect;
2662
2663 /* check reg 0Ch, bit 24-31 */
2664 detect = snd_cmipci_read(cm, CM_REG_INT_HLDCLR) & CM_CHIP_MASK2;
2665 if (! detect) {
2666 /* check reg 08h, bit 24-28 */
2667 detect = snd_cmipci_read(cm, CM_REG_CHFORMAT) & CM_CHIP_MASK1;
2668 if (! detect) {
2669 cm->chip_version = 33;
2670 cm->max_channels = 4;
2671 if (cm->do_soft_ac3)
2672 cm->can_ac3_sw = 1;
2673 else
2674 cm->can_ac3_hw = 1;
2675 cm->has_dual_dac = 1;
2676 } else {
2677 // printk("detect = %x\n", detect);
2678
2679 cm->chip_version = 37;
2680 cm->max_channels = 4;
2681 cm->can_ac3_hw = 1;
2682 cm->has_dual_dac = 1;
2683 cm->can_multi_ch = 1;
2684 }
2685 } else {
2686 /* check reg 0Ch, bit 26 */
2687 if (detect & CM_CHIP_8768) {
2688 cm->chip_version = 68;
2689 cm->max_channels = 8;
2690 cm->can_ac3_hw = 1;
2691 cm->has_dual_dac = 1;
2692 cm->can_multi_ch = 1;
2693 } else if (detect & CM_CHIP_055) {
2694 cm->chip_version = 55;
2695 cm->max_channels = 6;
2696 cm->can_ac3_hw = 1;
2697 cm->has_dual_dac = 1;
2698 cm->can_multi_ch = 1;
2699 } else if (detect & CM_CHIP_039) {
2700 cm->chip_version = 39;
2701 if (detect & CM_CHIP_039_6CH) /* 4 or 6 channels */
2702 cm->max_channels = 6;
2703 else
2704 cm->max_channels = 4;
2705 cm->can_ac3_hw = 1;
2706 cm->has_dual_dac = 1;
2707 cm->can_multi_ch = 1;
2708 } else {
2709 printk(KERN_ERR "chip %x version not supported\n", detect);
2710 }
2711 }
2712}
2713
2714static int snd_cmipci_free(struct cmipci *cm)
2715{
2716 if (cm->irq >= 0) {
2717 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_FM_EN);
2718 snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_ENSPDOUT);
2719 snd_cmipci_write(cm, CM_REG_INT_HLDCLR, 0); /* disable ints */
2720 snd_cmipci_ch_reset(cm, CM_CH_PLAY);
2721 snd_cmipci_ch_reset(cm, CM_CH_CAPT);
2722 snd_cmipci_write(cm, CM_REG_FUNCTRL0, 0); /* disable channels */
2723 snd_cmipci_write(cm, CM_REG_FUNCTRL1, 0);
2724
2725 /* reset mixer */
2726 snd_cmipci_mixer_write(cm, 0, 0);
2727
2728 synchronize_irq(cm->irq);
2729
2730 free_irq(cm->irq, cm);
2731 }
2732 pci_release_regions(cm->pci);
2733 kfree(cm);
2734 return 0;
2735}
2736
2737static int snd_cmipci_dev_free(struct snd_device *device)
2738{
2739 struct cmipci *cm = device->device_data;
2740 return snd_cmipci_free(cm);
2741}
2742
2743static int __devinit snd_cmipci_create_fm(struct cmipci *cm, long fm_port)
2744{
2745 long iosynth;
2746 unsigned int val;
2747 struct snd_opl3 *opl3;
2748 int err;
2749
2750 /* first try FM regs in PCI port range */
2751 iosynth = cm->iobase + CM_REG_FM_PCI;
2752 err = snd_opl3_create(cm->card, iosynth, iosynth + 2,
2753 OPL3_HW_OPL3, 1, &opl3);
2754 if (err < 0) {
2755 /* then try legacy ports */
2756 val = snd_cmipci_read(cm, CM_REG_LEGACY_CTRL) & ~CM_FMSEL_MASK;
2757 iosynth = fm_port;
2758 switch (iosynth) {
2759 case 0x3E8: val |= CM_FMSEL_3E8; break;
2760 case 0x3E0: val |= CM_FMSEL_3E0; break;
2761 case 0x3C8: val |= CM_FMSEL_3C8; break;
2762 case 0x388: val |= CM_FMSEL_388; break;
2763 default:
2764 return 0;
2765 }
2766 snd_cmipci_write(cm, CM_REG_LEGACY_CTRL, val);
2767 /* enable FM */
2768 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_FM_EN);
2769
2770 if (snd_opl3_create(cm->card, iosynth, iosynth + 2,
2771 OPL3_HW_OPL3, 0, &opl3) < 0) {
2772 printk(KERN_ERR "cmipci: no OPL device at %#lx, "
2773 "skipping...\n", iosynth);
2774 /* disable FM */
2775 snd_cmipci_write(cm, CM_REG_LEGACY_CTRL,
2776 val & ~CM_FMSEL_MASK);
2777 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_FM_EN);
2778 return 0;
2779 }
2780 }
2781 if ((err = snd_opl3_hwdep_new(opl3, 0, 1, NULL)) < 0) {
2782 printk(KERN_ERR "cmipci: cannot create OPL3 hwdep\n");
2783 return err;
2784 }
2785 return 0;
2786}
2787
2788static int __devinit snd_cmipci_create(struct snd_card *card, struct pci_dev *pci,
2789 int dev, struct cmipci **rcmipci)
2790{
2791 struct cmipci *cm;
2792 int err;
2793 static struct snd_device_ops ops = {
2794 .dev_free = snd_cmipci_dev_free,
2795 };
2796 unsigned int val = 0;
2797 unsigned long iomidi;
2798 int integrated_midi;
2799 int pcm_index, pcm_spdif_index;
2800
2801 *rcmipci = NULL;
2802
2803 if ((err = pci_enable_device(pci)) < 0)
2804 return err;
2805
2806 cm = kcalloc(1, sizeof(*cm), GFP_KERNEL);
2807 if (cm == NULL)
2808 return -ENOMEM;
2809
2810 spin_lock_init(&cm->reg_lock);
2811 init_MUTEX(&cm->open_mutex);
2812 cm->device = pci->device;
2813 cm->card = card;
2814 cm->pci = pci;
2815 cm->irq = -1;
2816 cm->channel[0].ch = 0;
2817 cm->channel[1].ch = 1;
2818 cm->channel[0].is_dac = cm->channel[1].is_dac = 1; /* dual DAC mode */
2819
2820 if ((err = pci_request_regions(pci, card->driver)) < 0) {
2821 kfree(cm);
2822 return err;
2823 }
2824 cm->iobase = pci_resource_start(pci, 0);
2825 if (request_irq(pci->irq, snd_cmipci_interrupt, SA_INTERRUPT|SA_SHIRQ, card->driver, cm)) {
2826 snd_printk("unable to grab IRQ %d\n", pci->irq);
2827 err = -EBUSY;
2828 goto __error;
2829 }
2830 cm->irq = pci->irq;
2831
2832 pci_set_master(cm->pci);
2833
2834 /*
2835 * check chip version, max channels and capabilities
2836 */
2837
2838 cm->chip_version = 0;
2839 cm->max_channels = 2;
2840 cm->do_soft_ac3 = soft_ac3[dev];
2841 if (pci->device != PCI_DEVICE_ID_CMEDIA_CM8338A &&
2842 pci->device != PCI_DEVICE_ID_CMEDIA_CM8338B)
2843 query_chip(cm);
2844 /* added -MCx suffix for chip supporting multi-channels */
2845 if (cm->can_multi_ch)
2846 sprintf(cm->card->driver + strlen(cm->card->driver),
2847 "-MC%d", cm->max_channels);
2848 else if (cm->can_ac3_sw)
2849 strcpy(cm->card->driver + strlen(cm->card->driver), "-SWIEC");
2850 cm->dig_status = SNDRV_PCM_DEFAULT_CON_SPDIF;
2851 cm->dig_pcm_status = SNDRV_PCM_DEFAULT_CON_SPDIF;
2852
2853#if CM_CH_PLAY == 1
2854 cm->ctrl = CM_CHADC0; /* default FUNCNTRL0 */
2855#else
2856 cm->ctrl = CM_CHADC1; /* default FUNCNTRL0 */
2857#endif
2858
2859 /* initialize codec registers */
2860 snd_cmipci_write(cm, CM_REG_INT_HLDCLR, 0); /* disable ints */
2861 snd_cmipci_ch_reset(cm, CM_CH_PLAY);
2862 snd_cmipci_ch_reset(cm, CM_CH_CAPT);
2863 snd_cmipci_write(cm, CM_REG_FUNCTRL0, 0); /* disable channels */
2864 snd_cmipci_write(cm, CM_REG_FUNCTRL1, 0);
2865
2866 snd_cmipci_write(cm, CM_REG_CHFORMAT, 0);
2867 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_ENDBDAC|CM_N4SPK3D);
2868#if CM_CH_PLAY == 1
2869 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_XCHGDAC);
2870#else
2871 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_XCHGDAC);
2872#endif
2873 /* Set Bus Master Request */
2874 snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_BREQ);
2875
2876 /* Assume TX and compatible chip set (Autodetection required for VX chip sets) */
2877 switch (pci->device) {
2878 case PCI_DEVICE_ID_CMEDIA_CM8738:
2879 case PCI_DEVICE_ID_CMEDIA_CM8738B:
2880 /* PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437VX */
2881 if (! pci_find_device(0x8086, 0x7030, NULL))
2882 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_TXVX);
2883 break;
2884 default:
2885 break;
2886 }
2887
2888 integrated_midi = snd_cmipci_read_b(cm, CM_REG_MPU_PCI) != 0xff;
2889 if (integrated_midi)
2890 iomidi = cm->iobase + CM_REG_MPU_PCI;
2891 else {
2892 iomidi = mpu_port[dev];
2893 switch (iomidi) {
2894 case 0x320: val = CM_VMPU_320; break;
2895 case 0x310: val = CM_VMPU_310; break;
2896 case 0x300: val = CM_VMPU_300; break;
2897 case 0x330: val = CM_VMPU_330; break;
2898 default:
2899 iomidi = 0; break;
2900 }
2901 if (iomidi > 0) {
2902 snd_cmipci_write(cm, CM_REG_LEGACY_CTRL, val);
2903 /* enable UART */
2904 snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_UART_EN);
2905 }
2906 }
2907
2908 if ((err = snd_cmipci_create_fm(cm, fm_port[dev])) < 0)
2909 return err;
2910
2911 /* reset mixer */
2912 snd_cmipci_mixer_write(cm, 0, 0);
2913
2914 snd_cmipci_proc_init(cm);
2915
2916 /* create pcm devices */
2917 pcm_index = pcm_spdif_index = 0;
2918#ifdef SIX_CH_HACK
2919 if (cm->has_dual_dac) {
2920 if ((err = snd_cmipci_pcm2_new(cm, pcm_index)) < 0)
2921 goto __error;
2922 pcm_index++;
2923 }
2924
2925 if ((err = snd_cmipci_pcm_new(cm, pcm_index)) < 0)
2926 goto __error;
2927 pcm_index++;
2928#else
2929 if ((err = snd_cmipci_pcm_new(cm, pcm_index)) < 0)
2930 goto __error;
2931 pcm_index++;
2932
2933 if (cm->has_dual_dac) {
2934 if ((err = snd_cmipci_pcm2_new(cm, pcm_index)) < 0)
2935 goto __error;
2936 pcm_index++;
2937 }
2938#endif
2939 if (cm->can_ac3_hw || cm->can_ac3_sw) {
2940 pcm_spdif_index = pcm_index;
2941 if ((err = snd_cmipci_pcm_spdif_new(cm, pcm_index)) < 0)
2942 goto __error;
2943 }
2944
2945 /* create mixer interface & switches */
2946 if ((err = snd_cmipci_mixer_new(cm, pcm_spdif_index)) < 0)
2947 goto __error;
2948
2949 if (iomidi > 0) {
2950 if ((err = snd_mpu401_uart_new(card, 0, MPU401_HW_CMIPCI,
2951 iomidi,
2952 (integrated_midi ?
2953 MPU401_INFO_INTEGRATED : 0),
2954 cm->irq, 0, &cm->rmidi)) < 0) {
2955 printk(KERN_ERR "cmipci: no UART401 device at 0x%lx\n", iomidi);
2956 }
2957 }
2958
2959 if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, cm, &ops)) < 0) {
2960 snd_cmipci_free(cm);
2961 return err;
2962 }
2963#ifdef USE_VAR48KRATE
2964 for (val = 0; val < ARRAY_SIZE(rates); val++)
2965 snd_cmipci_set_pll(cm, rates[val], val);
2966
2967 /*
2968 * (Re-)Enable external switch spdo_48k
2969 */
2970 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_SPDIF48K|CM_SPDF_AC97);
2971#endif /* USE_VAR48KRATE */
2972
2973 *rcmipci = cm;
2974 return 0;
2975
2976 __error:
2977 snd_cmipci_free(cm);
2978 return err;
2979}
2980
2981/*
2982 */
2983
2984MODULE_DEVICE_TABLE(pci, snd_cmipci_ids);
2985
2986static int __devinit snd_cmipci_probe(struct pci_dev *pci,
2987 const struct pci_device_id *pci_id)
2988{
2989 static int dev;
2990 struct snd_card *card;
2991 struct cmipci *cm;
2992 int err;
2993#ifdef DEBUG
2994 dprintf(("snd_cmipci_probe"));
2995#endif
2996 if (dev >= SNDRV_CARDS)
2997 return -ENODEV;
2998 if (! enable[dev]) {
2999 dev++;
3000 return -ENOENT;
3001 }
3002
3003 card = snd_card_new(index[dev], id[dev], THIS_MODULE, 0);
3004 if (card == NULL)
3005 return -ENOMEM;
3006
3007 switch (pci->device) {
3008 case PCI_DEVICE_ID_CMEDIA_CM8738:
3009 case PCI_DEVICE_ID_CMEDIA_CM8738B:
3010 strcpy(card->driver, "CMI8738");
3011 break;
3012 case PCI_DEVICE_ID_CMEDIA_CM8338A:
3013 case PCI_DEVICE_ID_CMEDIA_CM8338B:
3014 strcpy(card->driver, "CMI8338");
3015 break;
3016 default:
3017 strcpy(card->driver, "CMIPCI");
3018 break;
3019 }
3020
3021 if ((err = snd_cmipci_create(card, pci, dev, &cm)) < 0) {
3022 snd_card_free(card);
3023 return err;
3024 }
3025 card->private_data = cm;
3026
3027 sprintf(card->shortname, "C-Media PCI %s", card->driver);
3028 sprintf(card->longname, "%s (model %d) at 0x%lx, irq %i",
3029 card->shortname,
3030 cm->chip_version,
3031 cm->iobase,
3032 cm->irq);
3033
3034
3035#ifdef DEBUG
3036 dprintf(("%s is detected\n", card->longname));
3037#endif
3038
3039 if ((err = snd_card_register(card)) < 0) {
3040 snd_card_free(card);
3041 return err;
3042 }
3043
3044 pci_set_drvdata(pci, card);
3045 dev++;
3046
3047 return 0;
3048
3049}
3050
3051static void __devexit snd_cmipci_remove(struct pci_dev *pci)
3052{
3053 snd_card_free(pci_get_drvdata(pci));
3054 pci_set_drvdata(pci, NULL);
3055}
3056
3057#ifdef CONFIG_PM
3058/*
3059 * power management
3060 */
3061static unsigned char saved_regs[] = {
3062 CM_REG_FUNCTRL1, CM_REG_CHFORMAT, CM_REG_LEGACY_CTRL, CM_REG_MISC_CTRL,
3063 CM_REG_MIXER0, CM_REG_MIXER1, CM_REG_MIXER2, CM_REG_MIXER3, CM_REG_PLL,
3064 CM_REG_CH0_FRAME1, CM_REG_CH0_FRAME2,
3065 CM_REG_CH1_FRAME1, CM_REG_CH1_FRAME2, CM_REG_EXT_MISC,
3066 CM_REG_INT_STATUS, CM_REG_INT_HLDCLR, CM_REG_FUNCTRL0,
3067};
3068
3069static unsigned char saved_mixers[] = {
3070 SB_DSP4_MASTER_DEV, SB_DSP4_MASTER_DEV + 1,
3071 SB_DSP4_PCM_DEV, SB_DSP4_PCM_DEV + 1,
3072 SB_DSP4_SYNTH_DEV, SB_DSP4_SYNTH_DEV + 1,
3073 SB_DSP4_CD_DEV, SB_DSP4_CD_DEV + 1,
3074 SB_DSP4_LINE_DEV, SB_DSP4_LINE_DEV + 1,
3075 SB_DSP4_MIC_DEV, SB_DSP4_SPEAKER_DEV,
3076 CM_REG_EXTENT_IND, SB_DSP4_OUTPUT_SW,
3077 SB_DSP4_INPUT_LEFT, SB_DSP4_INPUT_RIGHT,
3078};
3079
3080static int snd_cmipci_suspend(struct pci_dev *pci, pm_message_t state)
3081{
3082 struct snd_card *card = pci_get_drvdata(pci);
3083 struct cmipci *cm = card->private_data;
3084 int i;
3085
3086 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
3087
3088 snd_pcm_suspend_all(cm->pcm);
3089 snd_pcm_suspend_all(cm->pcm2);
3090 snd_pcm_suspend_all(cm->pcm_spdif);
3091
3092 /* save registers */
3093 for (i = 0; i < ARRAY_SIZE(saved_regs); i++)
3094 cm->saved_regs[i] = snd_cmipci_read(cm, saved_regs[i]);
3095 for (i = 0; i < ARRAY_SIZE(saved_mixers); i++)
3096 cm->saved_mixers[i] = snd_cmipci_mixer_read(cm, saved_mixers[i]);
3097
3098 /* disable ints */
3099 snd_cmipci_write(cm, CM_REG_INT_HLDCLR, 0);
3100
3101 pci_set_power_state(pci, PCI_D3hot);
3102 pci_disable_device(pci);
3103 pci_save_state(pci);
3104 return 0;
3105}
3106
3107static int snd_cmipci_resume(struct pci_dev *pci)
3108{
3109 struct snd_card *card = pci_get_drvdata(pci);
3110 struct cmipci *cm = card->private_data;
3111 int i;
3112
3113 pci_restore_state(pci);
3114 pci_enable_device(pci);
3115 pci_set_power_state(pci, PCI_D0);
3116 pci_set_master(pci);
3117
3118 /* reset / initialize to a sane state */
3119 snd_cmipci_write(cm, CM_REG_INT_HLDCLR, 0);
3120 snd_cmipci_ch_reset(cm, CM_CH_PLAY);
3121 snd_cmipci_ch_reset(cm, CM_CH_CAPT);
3122 snd_cmipci_mixer_write(cm, 0, 0);
3123
3124 /* restore registers */
3125 for (i = 0; i < ARRAY_SIZE(saved_regs); i++)
3126 snd_cmipci_write(cm, saved_regs[i], cm->saved_regs[i]);
3127 for (i = 0; i < ARRAY_SIZE(saved_mixers); i++)
3128 snd_cmipci_mixer_write(cm, saved_mixers[i], cm->saved_mixers[i]);
3129
3130 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
3131 return 0;
3132}
3133#endif /* CONFIG_PM */
3134
3135static struct pci_driver driver = {
3136 .name = "C-Media PCI",
3137 .id_table = snd_cmipci_ids,
3138 .probe = snd_cmipci_probe,
3139 .remove = snd_cmipci_remove,
3140#ifdef CONFIG_PM
3141 .suspend = snd_cmipci_suspend,
3142 .resume = snd_cmipci_resume,
3143 #endif
3144};
3145
3146static int __init alsa_card_cmipci_init(void)
3147{
3148 int err;
3149
3150#ifdef TARGET_OS2
3151 if (midi_port > 0) mpu_port[0] = midi_port;
3152#endif
3153
3154 if ((err = pci_module_init(&driver)) < 0) {
3155#ifdef MODULE
3156 // printk(KERN_ERR "C-Media PCI soundcard not found or device busy\n");
3157#endif
3158 return err;
3159 }
3160 return 0;
3161}
3162
3163static void __exit alsa_card_cmipci_exit(void)
3164{
3165 pci_unregister_driver(&driver);
3166}
3167
3168module_init(alsa_card_cmipci_init)
3169module_exit(alsa_card_cmipci_exit)
3170
3171#ifndef MODULE
3172
3173/* format is: snd-cmipci=enable,index,id,
3174 mpu_port,fm_port */
3175
3176static int __init alsa_card_cmipci_setup(char *str)
3177{
3178 static unsigned __initdata nr_dev = 0;
3179
3180 if (nr_dev >= SNDRV_CARDS)
3181 return 0;
3182 (void)(get_option(&str,&enable[nr_dev]) == 2 &&
3183 get_option(&str,&index[nr_dev]) == 2 &&
3184 get_id(&str,&id[nr_dev]) == 2 &&
3185 get_option(&str,(int *)&mpu_port[nr_dev]) == 2 &&
3186 get_option(&str,(int *)&fm_port[nr_dev]) == 2);
3187 nr_dev++;
3188 return 1;
3189}
3190
3191__setup("snd-cmipci=", alsa_card_cmipci_setup);
3192
3193#endif /* ifndef MODULE */
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