source: GPL/trunk/alsa-kernel/pci/intel8x0.c@ 426

Last change on this file since 426 was 426, checked in by Paul Smedley, 16 years ago

Update alsa-kernel to ALSA 1.0.20 level
File size: 93.6 KB
Line 
1/*
2 * ALSA driver for Intel ICH (i8x0) chipsets
3 *
4 * Copyright (c) 2000 Jaroslav Kysela <perex@perex.cz>
5 *
6 *
7 * This code also contains alpha support for SiS 735 chipsets provided
8 * by Mike Pieper <mptei@users.sourceforge.net>. We have no datasheet
9 * for SiS735, so the code is not fully functional.
10 *
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
25
26 *
27 */
28
29#include <asm/io.h>
30#include <linux/delay.h>
31#include <linux/interrupt.h>
32#include <linux/init.h>
33#include <linux/pci.h>
34#include <linux/slab.h>
35#include <linux/moduleparam.h>
36#include <sound/core.h>
37#include <sound/pcm.h>
38#include <sound/ac97_codec.h>
39#include <sound/info.h>
40#include <sound/initval.h>
41/* for 440MX workaround */
42#include <asm/pgtable.h>
43#ifndef TARGET_OS2
44#include <asm/cacheflush.h>
45#endif
46
47MODULE_AUTHOR("Jaroslav Kysela <perex@perex.cz>");
48MODULE_DESCRIPTION("Intel 82801AA,82901AB,i810,i820,i830,i840,i845,MX440; SiS 7012; Ali 5455");
49MODULE_LICENSE("GPL");
50MODULE_SUPPORTED_DEVICE("{{Intel,82801AA-ICH},"
51 "{Intel,82901AB-ICH0},"
52 "{Intel,82801BA-ICH2},"
53 "{Intel,82801CA-ICH3},"
54 "{Intel,82801DB-ICH4},"
55 "{Intel,ICH5},"
56 "{Intel,ICH6},"
57 "{Intel,ICH7},"
58 "{Intel,6300ESB},"
59 "{Intel,ESB2},"
60 "{Intel,MX440},"
61 "{SiS,SI7012},"
62 "{NVidia,nForce Audio},"
63 "{NVidia,nForce2 Audio},"
64 "{NVidia,nForce3 Audio},"
65 "{NVidia,MCP04},"
66 "{NVidia,MCP501},"
67 "{NVidia,CK804},"
68 "{NVidia,CK8},"
69 "{NVidia,CK8S},"
70 "{AMD,AMD768},"
71 "{AMD,AMD8111},"
72 "{ALI,M5455}}");
73
74static int index = SNDRV_DEFAULT_IDX1; /* Index 0-MAX */
75static char *id = SNDRV_DEFAULT_STR1; /* ID for this card */
76static int ac97_clock;
77static char *ac97_quirk;
78static int buggy_semaphore;
79static int buggy_irq = -1; /* auto-check */
80static int xbox;
81static int spdif_aclink = -1;
82
83module_param(index, int, 0444);
84MODULE_PARM_DESC(index, "Index value for Intel i8x0 soundcard.");
85module_param(id, charp, 0444);
86MODULE_PARM_DESC(id, "ID string for Intel i8x0 soundcard.");
87module_param(ac97_clock, int, 0444);
88MODULE_PARM_DESC(ac97_clock, "AC'97 codec clock (0 = whitelist + auto-detect, 1 = force autodetect).");
89module_param(ac97_quirk, charp, 0444);
90MODULE_PARM_DESC(ac97_quirk, "AC'97 workaround for strange hardware.");
91module_param(buggy_semaphore, bool, 0444);
92MODULE_PARM_DESC(buggy_semaphore, "Enable workaround for hardwares with problematic codec semaphores.");
93module_param(buggy_irq, bool, 0444);
94MODULE_PARM_DESC(buggy_irq, "Enable workaround for buggy interrupts on some motherboards.");
95module_param(xbox, bool, 0444);
96MODULE_PARM_DESC(xbox, "Set to 1 for Xbox, if you have problems with the AC'97 codec detection.");
97module_param(spdif_aclink, int, 0444);
98MODULE_PARM_DESC(spdif_aclink, "S/PDIF over AC-link.");
99
100/* just for backward compatibility */
101static int enable;
102module_param(enable, bool, 0444);
103static int joystick;
104module_param(joystick, int, 0444);
105
106/*
107 * Direct registers
108 */
109enum { DEVICE_INTEL, DEVICE_INTEL_ICH4, DEVICE_SIS, DEVICE_ALI, DEVICE_NFORCE };
110
111#define ICHREG(x) ICH_REG_##x
112
113#define DEFINE_REGSET(name,base) \
114enum { \
115 ICH_REG_##name##_BDBAR = base + 0x0, /* dword - buffer descriptor list base address */ \
116 ICH_REG_##name##_CIV = base + 0x04, /* byte - current index value */ \
117 ICH_REG_##name##_LVI = base + 0x05, /* byte - last valid index */ \
118 ICH_REG_##name##_SR = base + 0x06, /* byte - status register */ \
119 ICH_REG_##name##_PICB = base + 0x08, /* word - position in current buffer */ \
120 ICH_REG_##name##_PIV = base + 0x0a, /* byte - prefetched index value */ \
121 ICH_REG_##name##_CR = base + 0x0b, /* byte - control register */ \
122};
123
124/* busmaster blocks */
125DEFINE_REGSET(OFF, 0); /* offset */
126DEFINE_REGSET(PI, 0x00); /* PCM in */
127DEFINE_REGSET(PO, 0x10); /* PCM out */
128DEFINE_REGSET(MC, 0x20); /* Mic in */
129
130/* ICH4 busmaster blocks */
131DEFINE_REGSET(MC2, 0x40); /* Mic in 2 */
132DEFINE_REGSET(PI2, 0x50); /* PCM in 2 */
133DEFINE_REGSET(SP, 0x60); /* SPDIF out */
134
135/* values for each busmaster block */
136
137/* LVI */
138#define ICH_REG_LVI_MASK 0x1f
139
140/* SR */
141#define ICH_FIFOE 0x10 /* FIFO error */
142#define ICH_BCIS 0x08 /* buffer completion interrupt status */
143#define ICH_LVBCI 0x04 /* last valid buffer completion interrupt */
144#define ICH_CELV 0x02 /* current equals last valid */
145#define ICH_DCH 0x01 /* DMA controller halted */
146
147/* PIV */
148#define ICH_REG_PIV_MASK 0x1f /* mask */
149
150/* CR */
151#define ICH_IOCE 0x10 /* interrupt on completion enable */
152#define ICH_FEIE 0x08 /* fifo error interrupt enable */
153#define ICH_LVBIE 0x04 /* last valid buffer interrupt enable */
154#define ICH_RESETREGS 0x02 /* reset busmaster registers */
155#define ICH_STARTBM 0x01 /* start busmaster operation */
156
157
158/* global block */
159#define ICH_REG_GLOB_CNT 0x2c /* dword - global control */
160#define ICH_PCM_SPDIF_MASK 0xc0000000 /* s/pdif pcm slot mask (ICH4) */
161#define ICH_PCM_SPDIF_NONE 0x00000000 /* reserved - undefined */
162#define ICH_PCM_SPDIF_78 0x40000000 /* s/pdif pcm on slots 7&8 */
163#define ICH_PCM_SPDIF_69 0x80000000 /* s/pdif pcm on slots 6&9 */
164#define ICH_PCM_SPDIF_1011 0xc0000000 /* s/pdif pcm on slots 10&11 */
165#define ICH_PCM_20BIT 0x00400000 /* 20-bit samples (ICH4) */
166#define ICH_PCM_246_MASK 0x00300000 /* chan mask (not all chips) */
167#define ICH_PCM_8 0x00300000 /* 8 channels (not all chips) */
168#define ICH_PCM_6 0x00200000 /* 6 channels (not all chips) */
169#define ICH_PCM_4 0x00100000 /* 4 channels (not all chips) */
170#define ICH_PCM_2 0x00000000 /* 2 channels (stereo) */
171#define ICH_SIS_PCM_246_MASK 0x000000c0 /* 6 channels (SIS7012) */
172#define ICH_SIS_PCM_6 0x00000080 /* 6 channels (SIS7012) */
173#define ICH_SIS_PCM_4 0x00000040 /* 4 channels (SIS7012) */
174#define ICH_SIS_PCM_2 0x00000000 /* 2 channels (SIS7012) */
175#define ICH_TRIE 0x00000040 /* tertiary resume interrupt enable */
176#define ICH_SRIE 0x00000020 /* secondary resume interrupt enable */
177#define ICH_PRIE 0x00000010 /* primary resume interrupt enable */
178#define ICH_ACLINK 0x00000008 /* AClink shut off */
179#define ICH_AC97WARM 0x00000004 /* AC'97 warm reset */
180#define ICH_AC97COLD 0x00000002 /* AC'97 cold reset */
181#define ICH_GIE 0x00000001 /* GPI interrupt enable */
182#define ICH_REG_GLOB_STA 0x30 /* dword - global status */
183#define ICH_TRI 0x20000000 /* ICH4: tertiary (AC_SDIN2) resume interrupt */
184#define ICH_TCR 0x10000000 /* ICH4: tertiary (AC_SDIN2) codec ready */
185#define ICH_BCS 0x08000000 /* ICH4: bit clock stopped */
186#define ICH_SPINT 0x04000000 /* ICH4: S/PDIF interrupt */
187#define ICH_P2INT 0x02000000 /* ICH4: PCM2-In interrupt */
188#define ICH_M2INT 0x01000000 /* ICH4: Mic2-In interrupt */
189#define ICH_SAMPLE_CAP 0x00c00000 /* ICH4: sample capability bits (RO) */
190#define ICH_SAMPLE_16_20 0x00400000 /* ICH4: 16- and 20-bit samples */
191#define ICH_MULTICHAN_CAP 0x00300000 /* ICH4: multi-channel capability bits (RO) */
192#define ICH_SIS_TRI 0x00080000 /* SIS: tertiary resume irq */
193#define ICH_SIS_TCR 0x00040000 /* SIS: tertiary codec ready */
194#define ICH_MD3 0x00020000 /* modem power down semaphore */
195#define ICH_AD3 0x00010000 /* audio power down semaphore */
196#define ICH_RCS 0x00008000 /* read completion status */
197#define ICH_BIT3 0x00004000 /* bit 3 slot 12 */
198#define ICH_BIT2 0x00002000 /* bit 2 slot 12 */
199#define ICH_BIT1 0x00001000 /* bit 1 slot 12 */
200#define ICH_SRI 0x00000800 /* secondary (AC_SDIN1) resume interrupt */
201#define ICH_PRI 0x00000400 /* primary (AC_SDIN0) resume interrupt */
202#define ICH_SCR 0x00000200 /* secondary (AC_SDIN1) codec ready */
203#define ICH_PCR 0x00000100 /* primary (AC_SDIN0) codec ready */
204#define ICH_MCINT 0x00000080 /* MIC capture interrupt */
205#define ICH_POINT 0x00000040 /* playback interrupt */
206#define ICH_PIINT 0x00000020 /* capture interrupt */
207#define ICH_NVSPINT 0x00000010 /* nforce spdif interrupt */
208#define ICH_MOINT 0x00000004 /* modem playback interrupt */
209#define ICH_MIINT 0x00000002 /* modem capture interrupt */
210#define ICH_GSCI 0x00000001 /* GPI status change interrupt */
211#define ICH_REG_ACC_SEMA 0x34 /* byte - codec write semaphore */
212#define ICH_CAS 0x01 /* codec access semaphore */
213#define ICH_REG_SDM 0x80
214#define ICH_DI2L_MASK 0x000000c0 /* PCM In 2, Mic In 2 data in line */
215#define ICH_DI2L_SHIFT 6
216#define ICH_DI1L_MASK 0x00000030 /* PCM In 1, Mic In 1 data in line */
217#define ICH_DI1L_SHIFT 4
218#define ICH_SE 0x00000008 /* steer enable */
219#define ICH_LDI_MASK 0x00000003 /* last codec read data input */
220
221#define ICH_MAX_FRAGS 32 /* max hw frags */
222
223
224/*
225 * registers for Ali5455
226 */
227
228/* ALi 5455 busmaster blocks */
229DEFINE_REGSET(AL_PI, 0x40); /* ALi PCM in */
230DEFINE_REGSET(AL_PO, 0x50); /* Ali PCM out */
231DEFINE_REGSET(AL_MC, 0x60); /* Ali Mic in */
232DEFINE_REGSET(AL_CDC_SPO, 0x70); /* Ali Codec SPDIF out */
233DEFINE_REGSET(AL_CENTER, 0x80); /* Ali center out */
234DEFINE_REGSET(AL_LFE, 0x90); /* Ali center out */
235DEFINE_REGSET(AL_CLR_SPI, 0xa0); /* Ali Controller SPDIF in */
236DEFINE_REGSET(AL_CLR_SPO, 0xb0); /* Ali Controller SPDIF out */
237DEFINE_REGSET(AL_I2S, 0xc0); /* Ali I2S in */
238DEFINE_REGSET(AL_PI2, 0xd0); /* Ali PCM2 in */
239DEFINE_REGSET(AL_MC2, 0xe0); /* Ali Mic2 in */
240
241enum {
242 ICH_REG_ALI_SCR = 0x00, /* System Control Register */
243 ICH_REG_ALI_SSR = 0x04, /* System Status Register */
244 ICH_REG_ALI_DMACR = 0x08, /* DMA Control Register */
245 ICH_REG_ALI_FIFOCR1 = 0x0c, /* FIFO Control Register 1 */
246 ICH_REG_ALI_INTERFACECR = 0x10, /* Interface Control Register */
247 ICH_REG_ALI_INTERRUPTCR = 0x14, /* Interrupt control Register */
248 ICH_REG_ALI_INTERRUPTSR = 0x18, /* Interrupt Status Register */
249 ICH_REG_ALI_FIFOCR2 = 0x1c, /* FIFO Control Register 2 */
250 ICH_REG_ALI_CPR = 0x20, /* Command Port Register */
251 ICH_REG_ALI_CPR_ADDR = 0x22, /* ac97 addr write */
252 ICH_REG_ALI_SPR = 0x24, /* Status Port Register */
253 ICH_REG_ALI_SPR_ADDR = 0x26, /* ac97 addr read */
254 ICH_REG_ALI_FIFOCR3 = 0x2c, /* FIFO Control Register 3 */
255 ICH_REG_ALI_TTSR = 0x30, /* Transmit Tag Slot Register */
256 ICH_REG_ALI_RTSR = 0x34, /* Receive Tag Slot Register */
257 ICH_REG_ALI_CSPSR = 0x38, /* Command/Status Port Status Register */
258 ICH_REG_ALI_CAS = 0x3c, /* Codec Write Semaphore Register */
259 ICH_REG_ALI_HWVOL = 0xf0, /* hardware volume control/status */
260 ICH_REG_ALI_I2SCR = 0xf4, /* I2S control/status */
261 ICH_REG_ALI_SPDIFCSR = 0xf8, /* spdif channel status register */
262 ICH_REG_ALI_SPDIFICS = 0xfc, /* spdif interface control/status */
263};
264
265#define ALI_CAS_SEM_BUSY 0x80000000
266#define ALI_CPR_ADDR_SECONDARY 0x100
267#define ALI_CPR_ADDR_READ 0x80
268#define ALI_CSPSR_CODEC_READY 0x08
269#define ALI_CSPSR_READ_OK 0x02
270#define ALI_CSPSR_WRITE_OK 0x01
271
272/* interrupts for the whole chip by interrupt status register finish */
273
274#define ALI_INT_MICIN2 (1<<26)
275#define ALI_INT_PCMIN2 (1<<25)
276#define ALI_INT_I2SIN (1<<24)
277#define ALI_INT_SPDIFOUT (1<<23) /* controller spdif out INTERRUPT */
278#define ALI_INT_SPDIFIN (1<<22)
279#define ALI_INT_LFEOUT (1<<21)
280#define ALI_INT_CENTEROUT (1<<20)
281#define ALI_INT_CODECSPDIFOUT (1<<19)
282#define ALI_INT_MICIN (1<<18)
283#define ALI_INT_PCMOUT (1<<17)
284#define ALI_INT_PCMIN (1<<16)
285#define ALI_INT_CPRAIS (1<<7) /* command port available */
286#define ALI_INT_SPRAIS (1<<5) /* status port available */
287#define ALI_INT_GPIO (1<<1)
288#define ALI_INT_MASK (ALI_INT_SPDIFOUT|ALI_INT_CODECSPDIFOUT|\
289 ALI_INT_MICIN|ALI_INT_PCMOUT|ALI_INT_PCMIN)
290
291#define ICH_ALI_SC_RESET (1<<31) /* master reset */
292#define ICH_ALI_SC_AC97_DBL (1<<30)
293#define ICH_ALI_SC_CODEC_SPDF (3<<20) /* 1=7/8, 2=6/9, 3=10/11 */
294#define ICH_ALI_SC_IN_BITS (3<<18)
295#define ICH_ALI_SC_OUT_BITS (3<<16)
296#define ICH_ALI_SC_6CH_CFG (3<<14)
297#define ICH_ALI_SC_PCM_4 (1<<8)
298#define ICH_ALI_SC_PCM_6 (2<<8)
299#define ICH_ALI_SC_PCM_246_MASK (3<<8)
300
301#define ICH_ALI_SS_SEC_ID (3<<5)
302#define ICH_ALI_SS_PRI_ID (3<<3)
303
304#define ICH_ALI_IF_AC97SP (1<<21)
305#define ICH_ALI_IF_MC (1<<20)
306#define ICH_ALI_IF_PI (1<<19)
307#define ICH_ALI_IF_MC2 (1<<18)
308#define ICH_ALI_IF_PI2 (1<<17)
309#define ICH_ALI_IF_LINE_SRC (1<<15) /* 0/1 = slot 3/6 */
310#define ICH_ALI_IF_MIC_SRC (1<<14) /* 0/1 = slot 3/6 */
311#define ICH_ALI_IF_SPDF_SRC (3<<12) /* 00 = PCM, 01 = AC97-in, 10 = spdif-in, 11 = i2s */
312#define ICH_ALI_IF_AC97_OUT (3<<8) /* 00 = PCM, 10 = spdif-in, 11 = i2s */
313#define ICH_ALI_IF_PO_SPDF (1<<3)
314#define ICH_ALI_IF_PO (1<<1)
315
316/*
317 *
318 */
319
320enum {
321 ICHD_PCMIN,
322 ICHD_PCMOUT,
323 ICHD_MIC,
324 ICHD_MIC2,
325 ICHD_PCM2IN,
326 ICHD_SPBAR,
327 ICHD_LAST = ICHD_SPBAR
328};
329enum {
330 NVD_PCMIN,
331 NVD_PCMOUT,
332 NVD_MIC,
333 NVD_SPBAR,
334 NVD_LAST = NVD_SPBAR
335};
336enum {
337 ALID_PCMIN,
338 ALID_PCMOUT,
339 ALID_MIC,
340 ALID_AC97SPDIFOUT,
341 ALID_SPDIFIN,
342 ALID_SPDIFOUT,
343 ALID_LAST = ALID_SPDIFOUT
344};
345
346#define get_ichdev(substream) (substream->runtime->private_data)
347
348struct ichdev {
349 unsigned int ichd; /* ich device number */
350 unsigned long reg_offset; /* offset to bmaddr */
351 u32 *bdbar; /* CPU address (32bit) */
352 unsigned int bdbar_addr; /* PCI bus address (32bit) */
353 struct snd_pcm_substream *substream;
354 unsigned int physbuf; /* physical address (32bit) */
355 unsigned int size;
356 unsigned int fragsize;
357 unsigned int fragsize1;
358 unsigned int position;
359 unsigned int pos_shift;
360 unsigned int last_pos;
361 unsigned long last_pos_jiffies;
362 unsigned int jiffy_to_bytes;
363 int frags;
364 int lvi;
365 int lvi_frag;
366 int civ;
367 int ack;
368 int ack_reload;
369 unsigned int ack_bit;
370 unsigned int roff_sr;
371 unsigned int roff_picb;
372 unsigned int int_sta_mask; /* interrupt status mask */
373 unsigned int ali_slot; /* ALI DMA slot */
374 struct ac97_pcm *pcm;
375 int pcm_open_flag;
376 unsigned int page_attr_changed: 1;
377 unsigned int suspended: 1;
378};
379
380struct intel8x0 {
381 unsigned int device_type;
382
383 int irq;
384
385 void __iomem *addr;
386 void __iomem *bmaddr;
387
388 struct pci_dev *pci;
389 struct snd_card *card;
390
391 int pcm_devs;
392 struct snd_pcm *pcm[6];
393 struct ichdev ichd[6];
394
395 unsigned multi4: 1,
396 multi6: 1,
397 multi8 :1,
398 dra: 1,
399 smp20bit: 1;
400 unsigned in_ac97_init: 1,
401 in_sdin_init: 1;
402 unsigned in_measurement: 1; /* during ac97 clock measurement */
403 unsigned fix_nocache: 1; /* workaround for 440MX */
404 unsigned buggy_irq: 1; /* workaround for buggy mobos */
405 unsigned xbox: 1; /* workaround for Xbox AC'97 detection */
406 unsigned buggy_semaphore: 1; /* workaround for buggy codec semaphore */
407
408 int spdif_idx; /* SPDIF BAR index; *_SPBAR or -1 if use PCMOUT */
409 unsigned int sdm_saved; /* SDM reg value */
410
411 struct snd_ac97_bus *ac97_bus;
412 struct snd_ac97 *ac97[3];
413 unsigned int ac97_sdin[3];
414 unsigned int max_codecs, ncodecs;
415 unsigned int *codec_bit;
416 unsigned int codec_isr_bits;
417 unsigned int codec_ready_bits;
418
419 spinlock_t reg_lock;
420
421 u32 bdbars_count;
422 struct snd_dma_buffer bdbars;
423 u32 int_sta_reg; /* interrupt status register */
424 u32 int_sta_mask; /* interrupt status mask */
425};
426
427static struct pci_device_id snd_intel8x0_ids[] = {
428 { 0x8086, 0x2415, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* 82801AA */
429 { 0x8086, 0x2425, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* 82901AB */
430 { 0x8086, 0x2445, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* 82801BA */
431 { 0x8086, 0x2485, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* ICH3 */
432 { 0x8086, 0x24c5, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL_ICH4 }, /* ICH4 */
433 { 0x8086, 0x24d5, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL_ICH4 }, /* ICH5 */
434 { 0x8086, 0x25a6, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL_ICH4 }, /* ESB */
435 { 0x8086, 0x266e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL_ICH4 }, /* ICH6 */
436 { 0x8086, 0x27de, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL_ICH4 }, /* ICH7 */
437 { 0x8086, 0x2698, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL_ICH4 }, /* ESB2 */
438 { 0x8086, 0x7195, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* 440MX */
439 { 0x1039, 0x7012, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_SIS }, /* SI7012 */
440 { 0x10de, 0x01b1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE }, /* NFORCE */
441 { 0x10de, 0x003a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE }, /* MCP04 */
442 { 0x10de, 0x006a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE }, /* NFORCE2 */
443 { 0x10de, 0x0059, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE }, /* CK804 */
444 { 0x10de, 0x008a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE }, /* CK8 */
445 { 0x10de, 0x00da, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE }, /* NFORCE3 */
446 { 0x10de, 0x00ea, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE }, /* CK8S */
447 { 0x10de, 0x026b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE }, /* MCP51 */
448 { 0x1022, 0x746d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* AMD8111 */
449 { 0x1022, 0x7445, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* AMD768 */
450 { 0x10b9, 0x5455, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_ALI }, /* Ali5455 */
451 { 0, }
452};
453
454MODULE_DEVICE_TABLE(pci, snd_intel8x0_ids);
455
456/*
457 * Lowlevel I/O - busmaster
458 */
459
460static inline u8 igetbyte(struct intel8x0 *chip, u32 offset)
461{
462 return ioread8(chip->bmaddr + offset);
463}
464
465static inline u16 igetword(struct intel8x0 *chip, u32 offset)
466{
467 return ioread16(chip->bmaddr + offset);
468}
469
470static inline u32 igetdword(struct intel8x0 *chip, u32 offset)
471{
472 return ioread32(chip->bmaddr + offset);
473}
474
475static inline void iputbyte(struct intel8x0 *chip, u32 offset, u8 val)
476{
477 iowrite8(val, chip->bmaddr + offset);
478}
479
480static inline void iputword(struct intel8x0 *chip, u32 offset, u16 val)
481{
482 iowrite16(val, chip->bmaddr + offset);
483}
484
485static inline void iputdword(struct intel8x0 *chip, u32 offset, u32 val)
486{
487 iowrite32(val, chip->bmaddr + offset);
488}
489
490/*
491 * Lowlevel I/O - AC'97 registers
492 */
493
494static inline u16 iagetword(struct intel8x0 *chip, u32 offset)
495{
496 return ioread16(chip->addr + offset);
497}
498
499static inline void iaputword(struct intel8x0 *chip, u32 offset, u16 val)
500{
501 iowrite16(val, chip->addr + offset);
502}
503
504/*
505 * Basic I/O
506 */
507
508/*
509 * access to AC97 codec via normal i/o (for ICH and SIS7012)
510 */
511
512static int snd_intel8x0_codec_semaphore(struct intel8x0 *chip, unsigned int codec)
513{
514 int time;
515
516 if (codec > 2)
517 return -EIO;
518 if (chip->in_sdin_init) {
519 /* we don't know the ready bit assignment at the moment */
520 /* so we check any */
521 codec = chip->codec_isr_bits;
522 } else {
523 codec = chip->codec_bit[chip->ac97_sdin[codec]];
524 }
525
526 /* codec ready ? */
527 if ((igetdword(chip, ICHREG(GLOB_STA)) & codec) == 0)
528 return -EIO;
529
530 if (chip->buggy_semaphore)
531 return 0; /* just ignore ... */
532
533 /* Anyone holding a semaphore for 1 msec should be shot... */
534 time = 100;
535 do {
536 if (!(igetbyte(chip, ICHREG(ACC_SEMA)) & ICH_CAS))
537 return 0;
538 udelay(10);
539 } while (time--);
540
541 /* access to some forbidden (non existant) ac97 registers will not
542 * reset the semaphore. So even if you don't get the semaphore, still
543 * continue the access. We don't need the semaphore anyway. */
544 snd_printk(KERN_ERR "codec_semaphore: semaphore is not ready [0x%x][0x%x]\n",
545 igetbyte(chip, ICHREG(ACC_SEMA)), igetdword(chip, ICHREG(GLOB_STA)));
546 iagetword(chip, 0); /* clear semaphore flag */
547 /* I don't care about the semaphore */
548 return -EBUSY;
549}
550
551static void snd_intel8x0_codec_write(struct snd_ac97 *ac97,
552 unsigned short reg,
553 unsigned short val)
554{
555 struct intel8x0 *chip = ac97->private_data;
556
557 if (snd_intel8x0_codec_semaphore(chip, ac97->num) < 0) {
558 if (! chip->in_ac97_init)
559 snd_printk(KERN_ERR "codec_write %d: semaphore is not ready for register 0x%x\n", ac97->num, reg);
560 }
561 iaputword(chip, reg + ac97->num * 0x80, val);
562}
563
564static unsigned short snd_intel8x0_codec_read(struct snd_ac97 *ac97,
565 unsigned short reg)
566{
567 struct intel8x0 *chip = ac97->private_data;
568 unsigned short res;
569 unsigned int tmp;
570
571 if (snd_intel8x0_codec_semaphore(chip, ac97->num) < 0) {
572 if (! chip->in_ac97_init)
573 snd_printk(KERN_ERR "codec_read %d: semaphore is not ready for register 0x%x\n", ac97->num, reg);
574 res = 0xffff;
575 } else {
576 res = iagetword(chip, reg + ac97->num * 0x80);
577 if ((tmp = igetdword(chip, ICHREG(GLOB_STA))) & ICH_RCS) {
578 /* reset RCS and preserve other R/WC bits */
579 iputdword(chip, ICHREG(GLOB_STA), tmp &
580 ~(chip->codec_ready_bits | ICH_GSCI));
581 if (! chip->in_ac97_init)
582 snd_printk(KERN_ERR "codec_read %d: read timeout for register 0x%x\n", ac97->num, reg);
583 res = 0xffff;
584 }
585 }
586 return res;
587}
588
589static void __devinit snd_intel8x0_codec_read_test(struct intel8x0 *chip,
590 unsigned int codec)
591{
592 unsigned int tmp;
593
594 if (snd_intel8x0_codec_semaphore(chip, codec) >= 0) {
595 iagetword(chip, codec * 0x80);
596 if ((tmp = igetdword(chip, ICHREG(GLOB_STA))) & ICH_RCS) {
597 /* reset RCS and preserve other R/WC bits */
598 iputdword(chip, ICHREG(GLOB_STA), tmp &
599 ~(chip->codec_ready_bits | ICH_GSCI));
600 }
601 }
602}
603
604/*
605 * access to AC97 for Ali5455
606 */
607static int snd_intel8x0_ali_codec_ready(struct intel8x0 *chip, int mask)
608{
609 int count = 0;
610 for (count = 0; count < 0x7f; count++) {
611 int val = igetbyte(chip, ICHREG(ALI_CSPSR));
612 if (val & mask)
613 return 0;
614 }
615 if (! chip->in_ac97_init)
616 snd_printd(KERN_WARNING "intel8x0: AC97 codec ready timeout.\n");
617 return -EBUSY;
618}
619
620static int snd_intel8x0_ali_codec_semaphore(struct intel8x0 *chip)
621{
622 int time = 100;
623 if (chip->buggy_semaphore)
624 return 0; /* just ignore ... */
625 while (--time && (igetdword(chip, ICHREG(ALI_CAS)) & ALI_CAS_SEM_BUSY))
626 udelay(1);
627 if (! time && ! chip->in_ac97_init)
628 snd_printk(KERN_WARNING "ali_codec_semaphore timeout\n");
629 return snd_intel8x0_ali_codec_ready(chip, ALI_CSPSR_CODEC_READY);
630}
631
632static unsigned short snd_intel8x0_ali_codec_read(struct snd_ac97 *ac97, unsigned short reg)
633{
634 struct intel8x0 *chip = ac97->private_data;
635 unsigned short data = 0xffff;
636
637 if (snd_intel8x0_ali_codec_semaphore(chip))
638 goto __err;
639 reg |= ALI_CPR_ADDR_READ;
640 if (ac97->num)
641 reg |= ALI_CPR_ADDR_SECONDARY;
642 iputword(chip, ICHREG(ALI_CPR_ADDR), reg);
643 if (snd_intel8x0_ali_codec_ready(chip, ALI_CSPSR_READ_OK))
644 goto __err;
645 data = igetword(chip, ICHREG(ALI_SPR));
646 __err:
647 return data;
648}
649
650static void snd_intel8x0_ali_codec_write(struct snd_ac97 *ac97, unsigned short reg,
651 unsigned short val)
652{
653 struct intel8x0 *chip = ac97->private_data;
654
655 if (snd_intel8x0_ali_codec_semaphore(chip))
656 return;
657 iputword(chip, ICHREG(ALI_CPR), val);
658 if (ac97->num)
659 reg |= ALI_CPR_ADDR_SECONDARY;
660 iputword(chip, ICHREG(ALI_CPR_ADDR), reg);
661 snd_intel8x0_ali_codec_ready(chip, ALI_CSPSR_WRITE_OK);
662}
663
664
665/*
666 * DMA I/O
667 */
668static void snd_intel8x0_setup_periods(struct intel8x0 *chip, struct ichdev *ichdev)
669{
670 int idx;
671 u32 *bdbar = ichdev->bdbar;
672 unsigned long port = ichdev->reg_offset;
673
674 iputdword(chip, port + ICH_REG_OFF_BDBAR, ichdev->bdbar_addr);
675 if (ichdev->size == ichdev->fragsize) {
676 ichdev->ack_reload = ichdev->ack = 2;
677 ichdev->fragsize1 = ichdev->fragsize >> 1;
678 for (idx = 0; idx < (ICH_REG_LVI_MASK + 1) * 2; idx += 4) {
679 bdbar[idx + 0] = cpu_to_le32(ichdev->physbuf);
680 bdbar[idx + 1] = cpu_to_le32(0x80000000 | /* interrupt on completion */
681 ichdev->fragsize1 >> ichdev->pos_shift);
682 bdbar[idx + 2] = cpu_to_le32(ichdev->physbuf + (ichdev->size >> 1));
683 bdbar[idx + 3] = cpu_to_le32(0x80000000 | /* interrupt on completion */
684 ichdev->fragsize1 >> ichdev->pos_shift);
685 }
686 ichdev->frags = 2;
687 } else {
688 ichdev->ack_reload = ichdev->ack = 1;
689 ichdev->fragsize1 = ichdev->fragsize;
690 for (idx = 0; idx < (ICH_REG_LVI_MASK + 1) * 2; idx += 2) {
691 bdbar[idx + 0] = cpu_to_le32(ichdev->physbuf +
692 (((idx >> 1) * ichdev->fragsize) %
693 ichdev->size));
694 bdbar[idx + 1] = cpu_to_le32(0x80000000 | /* interrupt on completion */
695 ichdev->fragsize >> ichdev->pos_shift);
696#if 0
697 printk(KERN_DEBUG "bdbar[%i] = 0x%x [0x%x]\n",
698 idx + 0, bdbar[idx + 0], bdbar[idx + 1]);
699#endif
700 }
701 ichdev->frags = ichdev->size / ichdev->fragsize;
702 }
703 iputbyte(chip, port + ICH_REG_OFF_LVI, ichdev->lvi = ICH_REG_LVI_MASK);
704 ichdev->civ = 0;
705 iputbyte(chip, port + ICH_REG_OFF_CIV, 0);
706 ichdev->lvi_frag = ICH_REG_LVI_MASK % ichdev->frags;
707 ichdev->position = 0;
708#if 0
709 printk(KERN_DEBUG "lvi_frag = %i, frags = %i, period_size = 0x%x, "
710 "period_size1 = 0x%x\n",
711 ichdev->lvi_frag, ichdev->frags, ichdev->fragsize,
712 ichdev->fragsize1);
713#endif
714 /* clear interrupts */
715 iputbyte(chip, port + ichdev->roff_sr, ICH_FIFOE | ICH_BCIS | ICH_LVBCI);
716}
717
718#ifdef __i386__
719/*
720 * Intel 82443MX running a 100MHz processor system bus has a hardware bug,
721 * which aborts PCI busmaster for audio transfer. A workaround is to set
722 * the pages as non-cached. For details, see the errata in
723 * http://www.intel.com/design/chipsets/specupdt/245051.htm
724 */
725static void fill_nocache(void *buf, int size, int nocache)
726{
727 size = (size + PAGE_SIZE - 1) >> PAGE_SHIFT;
728 if (nocache)
729 set_pages_uc(virt_to_page(buf), size);
730 else
731 set_pages_wb(virt_to_page(buf), size);
732}
733#else
734#define fill_nocache(buf, size, nocache) do { ; } while (0)
735#endif
736
737/*
738 * Interrupt handler
739 */
740
741static inline void snd_intel8x0_update(struct intel8x0 *chip, struct ichdev *ichdev)
742{
743 unsigned long port = ichdev->reg_offset;
744 unsigned long flags;
745 int status, civ, i, step;
746 int ack = 0;
747
748 spin_lock_irqsave(&chip->reg_lock, flags);
749 status = igetbyte(chip, port + ichdev->roff_sr);
750 civ = igetbyte(chip, port + ICH_REG_OFF_CIV);
751 if (!(status & ICH_BCIS)) {
752 step = 0;
753 } else if (civ == ichdev->civ) {
754 // snd_printd("civ same %d\n", civ);
755 step = 1;
756 ichdev->civ++;
757 ichdev->civ &= ICH_REG_LVI_MASK;
758 } else {
759 step = civ - ichdev->civ;
760 if (step < 0)
761 step += ICH_REG_LVI_MASK + 1;
762 // if (step != 1)
763 // snd_printd("step = %d, %d -> %d\n", step, ichdev->civ, civ);
764 ichdev->civ = civ;
765 }
766
767 ichdev->position += step * ichdev->fragsize1;
768 if (! chip->in_measurement)
769 ichdev->position %= ichdev->size;
770 ichdev->lvi += step;
771 ichdev->lvi &= ICH_REG_LVI_MASK;
772 iputbyte(chip, port + ICH_REG_OFF_LVI, ichdev->lvi);
773 for (i = 0; i < step; i++) {
774 ichdev->lvi_frag++;
775 ichdev->lvi_frag %= ichdev->frags;
776 ichdev->bdbar[ichdev->lvi * 2] = cpu_to_le32(ichdev->physbuf + ichdev->lvi_frag * ichdev->fragsize1);
777#if 0
778 printk(KERN_DEBUG "new: bdbar[%i] = 0x%x [0x%x], prefetch = %i, "
779 "all = 0x%x, 0x%x\n",
780 ichdev->lvi * 2, ichdev->bdbar[ichdev->lvi * 2],
781 ichdev->bdbar[ichdev->lvi * 2 + 1], inb(ICH_REG_OFF_PIV + port),
782 inl(port + 4), inb(port + ICH_REG_OFF_CR));
783#endif
784 if (--ichdev->ack == 0) {
785 ichdev->ack = ichdev->ack_reload;
786 ack = 1;
787 }
788 }
789 spin_unlock_irqrestore(&chip->reg_lock, flags);
790 if (ack && ichdev->substream) {
791 snd_pcm_period_elapsed(ichdev->substream);
792 }
793 iputbyte(chip, port + ichdev->roff_sr,
794 status & (ICH_FIFOE | ICH_BCIS | ICH_LVBCI));
795}
796
797static irqreturn_t snd_intel8x0_interrupt(int irq, void *dev_id)
798{
799 struct intel8x0 *chip = dev_id;
800 struct ichdev *ichdev;
801 unsigned int status;
802 unsigned int i;
803
804 status = igetdword(chip, chip->int_sta_reg);
805 if (status == 0xffffffff) /* we are not yet resumed */
806 return IRQ_NONE;
807
808 if ((status & chip->int_sta_mask) == 0) {
809 if (status) {
810 /* ack */
811 iputdword(chip, chip->int_sta_reg, status);
812 if (! chip->buggy_irq)
813 status = 0;
814 }
815 return IRQ_RETVAL(status);
816 }
817
818 for (i = 0; i < chip->bdbars_count; i++) {
819 ichdev = &chip->ichd[i];
820 if (status & ichdev->int_sta_mask)
821 snd_intel8x0_update(chip, ichdev);
822 }
823
824 /* ack them */
825 iputdword(chip, chip->int_sta_reg, status & chip->int_sta_mask);
826
827 return IRQ_HANDLED;
828}
829
830/*
831 * PCM part
832 */
833
834static int snd_intel8x0_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
835{
836 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
837 struct ichdev *ichdev = get_ichdev(substream);
838 unsigned char val = 0;
839 unsigned long port = ichdev->reg_offset;
840
841 switch (cmd) {
842 case SNDRV_PCM_TRIGGER_RESUME:
843 ichdev->suspended = 0;
844 /* fallthru */
845 case SNDRV_PCM_TRIGGER_START:
846 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
847 val = ICH_IOCE | ICH_STARTBM;
848 ichdev->last_pos = ichdev->position;
849 ichdev->last_pos_jiffies = jiffies;
850 break;
851 case SNDRV_PCM_TRIGGER_SUSPEND:
852 ichdev->suspended = 1;
853 /* fallthru */
854 case SNDRV_PCM_TRIGGER_STOP:
855 val = 0;
856 break;
857 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
858 val = ICH_IOCE;
859 break;
860 default:
861 return -EINVAL;
862 }
863 iputbyte(chip, port + ICH_REG_OFF_CR, val);
864 if (cmd == SNDRV_PCM_TRIGGER_STOP) {
865 /* wait until DMA stopped */
866 while (!(igetbyte(chip, port + ichdev->roff_sr) & ICH_DCH)) ;
867 /* reset whole DMA things */
868 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_RESETREGS);
869 }
870 return 0;
871}
872
873static int snd_intel8x0_ali_trigger(struct snd_pcm_substream *substream, int cmd)
874{
875 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
876 struct ichdev *ichdev = get_ichdev(substream);
877 unsigned long port = ichdev->reg_offset;
878 static int fiforeg[] = {
879 ICHREG(ALI_FIFOCR1), ICHREG(ALI_FIFOCR2), ICHREG(ALI_FIFOCR3)
880 };
881 unsigned int val, fifo;
882
883 val = igetdword(chip, ICHREG(ALI_DMACR));
884 switch (cmd) {
885 case SNDRV_PCM_TRIGGER_RESUME:
886 ichdev->suspended = 0;
887 /* fallthru */
888 case SNDRV_PCM_TRIGGER_START:
889 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
890 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
891 /* clear FIFO for synchronization of channels */
892 fifo = igetdword(chip, fiforeg[ichdev->ali_slot / 4]);
893 fifo &= ~(0xff << (ichdev->ali_slot % 4));
894 fifo |= 0x83 << (ichdev->ali_slot % 4);
895 iputdword(chip, fiforeg[ichdev->ali_slot / 4], fifo);
896 }
897 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_IOCE);
898 val &= ~(1 << (ichdev->ali_slot + 16)); /* clear PAUSE flag */
899 /* start DMA */
900 iputdword(chip, ICHREG(ALI_DMACR), val | (1 << ichdev->ali_slot));
901 break;
902 case SNDRV_PCM_TRIGGER_SUSPEND:
903 ichdev->suspended = 1;
904 /* fallthru */
905 case SNDRV_PCM_TRIGGER_STOP:
906 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
907 /* pause */
908 iputdword(chip, ICHREG(ALI_DMACR), val | (1 << (ichdev->ali_slot + 16)));
909 iputbyte(chip, port + ICH_REG_OFF_CR, 0);
910 while (igetbyte(chip, port + ICH_REG_OFF_CR))
911 ;
912 if (cmd == SNDRV_PCM_TRIGGER_PAUSE_PUSH)
913 break;
914 /* reset whole DMA things */
915 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_RESETREGS);
916 /* clear interrupts */
917 iputbyte(chip, port + ICH_REG_OFF_SR,
918 igetbyte(chip, port + ICH_REG_OFF_SR) | 0x1e);
919 iputdword(chip, ICHREG(ALI_INTERRUPTSR),
920 igetdword(chip, ICHREG(ALI_INTERRUPTSR)) & ichdev->int_sta_mask);
921 break;
922 default:
923 return -EINVAL;
924 }
925 return 0;
926}
927
928static int snd_intel8x0_hw_params(struct snd_pcm_substream *substream,
929 struct snd_pcm_hw_params *hw_params)
930{
931 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
932 struct ichdev *ichdev = get_ichdev(substream);
933 struct snd_pcm_runtime *runtime = substream->runtime;
934 int dbl = params_rate(hw_params) > 48000;
935 int err;
936
937 if (chip->fix_nocache && ichdev->page_attr_changed) {
938 fill_nocache(runtime->dma_area, runtime->dma_bytes, 0); /* clear */
939 ichdev->page_attr_changed = 0;
940 }
941 err = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params));
942 if (err < 0)
943 return err;
944 if (chip->fix_nocache) {
945 if (runtime->dma_area && ! ichdev->page_attr_changed) {
946 fill_nocache(runtime->dma_area, runtime->dma_bytes, 1);
947 ichdev->page_attr_changed = 1;
948 }
949 }
950 if (ichdev->pcm_open_flag) {
951 snd_ac97_pcm_close(ichdev->pcm);
952 ichdev->pcm_open_flag = 0;
953 }
954 err = snd_ac97_pcm_open(ichdev->pcm, params_rate(hw_params),
955 params_channels(hw_params),
956 ichdev->pcm->r[dbl].slots);
957 if (err >= 0) {
958 ichdev->pcm_open_flag = 1;
959 /* Force SPDIF setting */
960 if (ichdev->ichd == ICHD_PCMOUT && chip->spdif_idx < 0)
961 snd_ac97_set_rate(ichdev->pcm->r[0].codec[0], AC97_SPDIF,
962 params_rate(hw_params));
963 }
964 return err;
965}
966
967static int snd_intel8x0_hw_free(struct snd_pcm_substream *substream)
968{
969 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
970 struct ichdev *ichdev = get_ichdev(substream);
971
972 if (ichdev->pcm_open_flag) {
973 snd_ac97_pcm_close(ichdev->pcm);
974 ichdev->pcm_open_flag = 0;
975 }
976 if (chip->fix_nocache && ichdev->page_attr_changed) {
977 fill_nocache(substream->runtime->dma_area, substream->runtime->dma_bytes, 0);
978 ichdev->page_attr_changed = 0;
979 }
980 return snd_pcm_lib_free_pages(substream);
981}
982
983static void snd_intel8x0_setup_pcm_out(struct intel8x0 *chip,
984 struct snd_pcm_runtime *runtime)
985{
986 unsigned int cnt;
987 int dbl = runtime->rate > 48000;
988
989 spin_lock_irq(&chip->reg_lock);
990 switch (chip->device_type) {
991 case DEVICE_ALI:
992 cnt = igetdword(chip, ICHREG(ALI_SCR));
993 cnt &= ~ICH_ALI_SC_PCM_246_MASK;
994 if (runtime->channels == 4 || dbl)
995 cnt |= ICH_ALI_SC_PCM_4;
996 else if (runtime->channels == 6)
997 cnt |= ICH_ALI_SC_PCM_6;
998 iputdword(chip, ICHREG(ALI_SCR), cnt);
999 break;
1000 case DEVICE_SIS:
1001 cnt = igetdword(chip, ICHREG(GLOB_CNT));
1002 cnt &= ~ICH_SIS_PCM_246_MASK;
1003 if (runtime->channels == 4 || dbl)
1004 cnt |= ICH_SIS_PCM_4;
1005 else if (runtime->channels == 6)
1006 cnt |= ICH_SIS_PCM_6;
1007 iputdword(chip, ICHREG(GLOB_CNT), cnt);
1008 break;
1009 default:
1010 cnt = igetdword(chip, ICHREG(GLOB_CNT));
1011 cnt &= ~(ICH_PCM_246_MASK | ICH_PCM_20BIT);
1012 if (runtime->channels == 4 || dbl)
1013 cnt |= ICH_PCM_4;
1014 else if (runtime->channels == 6)
1015 cnt |= ICH_PCM_6;
1016 else if (runtime->channels == 8)
1017 cnt |= ICH_PCM_8;
1018 if (chip->device_type == DEVICE_NFORCE) {
1019 /* reset to 2ch once to keep the 6 channel data in alignment,
1020 * to start from Front Left always
1021 */
1022 if (cnt & ICH_PCM_246_MASK) {
1023 iputdword(chip, ICHREG(GLOB_CNT), cnt & ~ICH_PCM_246_MASK);
1024 spin_unlock_irq(&chip->reg_lock);
1025 msleep(50); /* grrr... */
1026 spin_lock_irq(&chip->reg_lock);
1027 }
1028 } else if (chip->device_type == DEVICE_INTEL_ICH4) {
1029 if (runtime->sample_bits > 16)
1030 cnt |= ICH_PCM_20BIT;
1031 }
1032 iputdword(chip, ICHREG(GLOB_CNT), cnt);
1033 break;
1034 }
1035 spin_unlock_irq(&chip->reg_lock);
1036}
1037
1038static int snd_intel8x0_pcm_prepare(struct snd_pcm_substream *substream)
1039{
1040 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1041 struct snd_pcm_runtime *runtime = substream->runtime;
1042 struct ichdev *ichdev = get_ichdev(substream);
1043
1044 ichdev->physbuf = runtime->dma_addr;
1045 ichdev->size = snd_pcm_lib_buffer_bytes(substream);
1046 ichdev->fragsize = snd_pcm_lib_period_bytes(substream);
1047 if (ichdev->ichd == ICHD_PCMOUT) {
1048 snd_intel8x0_setup_pcm_out(chip, runtime);
1049 if (chip->device_type == DEVICE_INTEL_ICH4)
1050 ichdev->pos_shift = (runtime->sample_bits > 16) ? 2 : 1;
1051 }
1052 snd_intel8x0_setup_periods(chip, ichdev);
1053 ichdev->jiffy_to_bytes = (runtime->rate * 4 * ichdev->pos_shift) / HZ;
1054 return 0;
1055}
1056
1057static snd_pcm_uframes_t snd_intel8x0_pcm_pointer(struct snd_pcm_substream *substream)
1058{
1059 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1060 struct ichdev *ichdev = get_ichdev(substream);
1061 size_t ptr1, ptr;
1062 int civ, timeout = 10;
1063 unsigned int position;
1064
1065 spin_lock(&chip->reg_lock);
1066 do {
1067 civ = igetbyte(chip, ichdev->reg_offset + ICH_REG_OFF_CIV);
1068 ptr1 = igetword(chip, ichdev->reg_offset + ichdev->roff_picb);
1069 position = ichdev->position;
1070 if (ptr1 == 0) {
1071 udelay(10);
1072 continue;
1073 }
1074 if (civ == igetbyte(chip, ichdev->reg_offset + ICH_REG_OFF_CIV) &&
1075 ptr1 == igetword(chip, ichdev->reg_offset + ichdev->roff_picb))
1076 break;
1077 } while (timeout--);
1078 if (ptr1 != 0) {
1079 ptr1 <<= ichdev->pos_shift;
1080 ptr = ichdev->fragsize1 - ptr1;
1081 ptr += position;
1082 ichdev->last_pos = ptr;
1083 ichdev->last_pos_jiffies = jiffies;
1084 } else {
1085 ptr1 = jiffies - ichdev->last_pos_jiffies;
1086 if (ptr1)
1087 ptr1 -= 1;
1088 ptr = ichdev->last_pos + ptr1 * ichdev->jiffy_to_bytes;
1089 ptr %= ichdev->size;
1090 }
1091 spin_unlock(&chip->reg_lock);
1092 if (ptr >= ichdev->size)
1093 return 0;
1094 return bytes_to_frames(substream->runtime, ptr);
1095}
1096
1097static struct snd_pcm_hardware snd_intel8x0_stream =
1098{
1099 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1100 SNDRV_PCM_INFO_BLOCK_TRANSFER |
1101 SNDRV_PCM_INFO_MMAP_VALID |
1102 SNDRV_PCM_INFO_PAUSE |
1103 SNDRV_PCM_INFO_RESUME),
1104 .formats = SNDRV_PCM_FMTBIT_S16_LE,
1105 .rates = SNDRV_PCM_RATE_48000,
1106 .rate_min = 48000,
1107 .rate_max = 48000,
1108 .channels_min = 2,
1109 .channels_max = 2,
1110 .buffer_bytes_max = 128 * 1024,
1111 .period_bytes_min = 32,
1112 .period_bytes_max = 128 * 1024,
1113 .periods_min = 1,
1114 .periods_max = 1024,
1115 .fifo_size = 0,
1116};
1117
1118static unsigned int channels4[] = {
1119 2, 4,
1120};
1121
1122static struct snd_pcm_hw_constraint_list hw_constraints_channels4 = {
1123 .count = ARRAY_SIZE(channels4),
1124 .list = channels4,
1125 .mask = 0,
1126};
1127
1128static unsigned int channels6[] = {
1129 2, 4, 6,
1130};
1131
1132static struct snd_pcm_hw_constraint_list hw_constraints_channels6 = {
1133 .count = ARRAY_SIZE(channels6),
1134 .list = channels6,
1135 .mask = 0,
1136};
1137
1138static unsigned int channels8[] = {
1139 2, 4, 6, 8,
1140};
1141
1142static struct snd_pcm_hw_constraint_list hw_constraints_channels8 = {
1143 .count = ARRAY_SIZE(channels8),
1144 .list = channels8,
1145 .mask = 0,
1146};
1147
1148static int snd_intel8x0_pcm_open(struct snd_pcm_substream *substream, struct ichdev *ichdev)
1149{
1150 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1151 struct snd_pcm_runtime *runtime = substream->runtime;
1152 int err;
1153
1154 ichdev->substream = substream;
1155 runtime->hw = snd_intel8x0_stream;
1156 runtime->hw.rates = ichdev->pcm->rates;
1157 snd_pcm_limit_hw_rates(runtime);
1158 if (chip->device_type == DEVICE_SIS) {
1159 runtime->hw.buffer_bytes_max = 64*1024;
1160 runtime->hw.period_bytes_max = 64*1024;
1161 }
1162 if ((err = snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS)) < 0)
1163 return err;
1164 runtime->private_data = ichdev;
1165 return 0;
1166}
1167
1168static int snd_intel8x0_playback_open(struct snd_pcm_substream *substream)
1169{
1170 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1171 struct snd_pcm_runtime *runtime = substream->runtime;
1172 int err;
1173
1174 err = snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_PCMOUT]);
1175 if (err < 0)
1176 return err;
1177
1178 if (chip->multi8) {
1179 runtime->hw.channels_max = 8;
1180 snd_pcm_hw_constraint_list(runtime, 0,
1181 SNDRV_PCM_HW_PARAM_CHANNELS,
1182 &hw_constraints_channels8);
1183 } else if (chip->multi6) {
1184 runtime->hw.channels_max = 6;
1185 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
1186 &hw_constraints_channels6);
1187 } else if (chip->multi4) {
1188 runtime->hw.channels_max = 4;
1189 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
1190 &hw_constraints_channels4);
1191 }
1192 if (chip->dra) {
1193 snd_ac97_pcm_double_rate_rules(runtime);
1194 }
1195 if (chip->smp20bit) {
1196 runtime->hw.formats |= SNDRV_PCM_FMTBIT_S32_LE;
1197 snd_pcm_hw_constraint_msbits(runtime, 0, 32, 20);
1198 }
1199 return 0;
1200}
1201
1202static int snd_intel8x0_playback_close(struct snd_pcm_substream *substream)
1203{
1204 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1205
1206 chip->ichd[ICHD_PCMOUT].substream = NULL;
1207 return 0;
1208}
1209
1210static int snd_intel8x0_capture_open(struct snd_pcm_substream *substream)
1211{
1212 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1213
1214 return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_PCMIN]);
1215}
1216
1217static int snd_intel8x0_capture_close(struct snd_pcm_substream *substream)
1218{
1219 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1220
1221 chip->ichd[ICHD_PCMIN].substream = NULL;
1222 return 0;
1223}
1224
1225static int snd_intel8x0_mic_open(struct snd_pcm_substream *substream)
1226{
1227 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1228
1229 return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_MIC]);
1230}
1231
1232static int snd_intel8x0_mic_close(struct snd_pcm_substream *substream)
1233{
1234 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1235
1236 chip->ichd[ICHD_MIC].substream = NULL;
1237 return 0;
1238}
1239
1240static int snd_intel8x0_mic2_open(struct snd_pcm_substream *substream)
1241{
1242 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1243
1244 return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_MIC2]);
1245}
1246
1247static int snd_intel8x0_mic2_close(struct snd_pcm_substream *substream)
1248{
1249 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1250
1251 chip->ichd[ICHD_MIC2].substream = NULL;
1252 return 0;
1253}
1254
1255static int snd_intel8x0_capture2_open(struct snd_pcm_substream *substream)
1256{
1257 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1258
1259 return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_PCM2IN]);
1260}
1261
1262static int snd_intel8x0_capture2_close(struct snd_pcm_substream *substream)
1263{
1264 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1265
1266 chip->ichd[ICHD_PCM2IN].substream = NULL;
1267 return 0;
1268}
1269
1270static int snd_intel8x0_spdif_open(struct snd_pcm_substream *substream)
1271{
1272 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1273 int idx = chip->device_type == DEVICE_NFORCE ? NVD_SPBAR : ICHD_SPBAR;
1274
1275 return snd_intel8x0_pcm_open(substream, &chip->ichd[idx]);
1276}
1277
1278static int snd_intel8x0_spdif_close(struct snd_pcm_substream *substream)
1279{
1280 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1281 int idx = chip->device_type == DEVICE_NFORCE ? NVD_SPBAR : ICHD_SPBAR;
1282
1283 chip->ichd[idx].substream = NULL;
1284 return 0;
1285}
1286
1287static int snd_intel8x0_ali_ac97spdifout_open(struct snd_pcm_substream *substream)
1288{
1289 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1290 unsigned int val;
1291
1292 spin_lock_irq(&chip->reg_lock);
1293 val = igetdword(chip, ICHREG(ALI_INTERFACECR));
1294 val |= ICH_ALI_IF_AC97SP;
1295 iputdword(chip, ICHREG(ALI_INTERFACECR), val);
1296 /* also needs to set ALI_SC_CODEC_SPDF correctly */
1297 spin_unlock_irq(&chip->reg_lock);
1298
1299 return snd_intel8x0_pcm_open(substream, &chip->ichd[ALID_AC97SPDIFOUT]);
1300}
1301
1302static int snd_intel8x0_ali_ac97spdifout_close(struct snd_pcm_substream *substream)
1303{
1304 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1305 unsigned int val;
1306
1307 chip->ichd[ALID_AC97SPDIFOUT].substream = NULL;
1308 spin_lock_irq(&chip->reg_lock);
1309 val = igetdword(chip, ICHREG(ALI_INTERFACECR));
1310 val &= ~ICH_ALI_IF_AC97SP;
1311 iputdword(chip, ICHREG(ALI_INTERFACECR), val);
1312 spin_unlock_irq(&chip->reg_lock);
1313
1314 return 0;
1315}
1316
1317#if 0 // NYI
1318static int snd_intel8x0_ali_spdifin_open(struct snd_pcm_substream *substream)
1319{
1320 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1321
1322 return snd_intel8x0_pcm_open(substream, &chip->ichd[ALID_SPDIFIN]);
1323}
1324
1325static int snd_intel8x0_ali_spdifin_close(struct snd_pcm_substream *substream)
1326{
1327 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1328
1329 chip->ichd[ALID_SPDIFIN].substream = NULL;
1330 return 0;
1331}
1332
1333static int snd_intel8x0_ali_spdifout_open(struct snd_pcm_substream *substream)
1334{
1335 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1336
1337 return snd_intel8x0_pcm_open(substream, &chip->ichd[ALID_SPDIFOUT]);
1338}
1339
1340static int snd_intel8x0_ali_spdifout_close(struct snd_pcm_substream *substream)
1341{
1342 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1343
1344 chip->ichd[ALID_SPDIFOUT].substream = NULL;
1345 return 0;
1346}
1347#endif
1348
1349static struct snd_pcm_ops snd_intel8x0_playback_ops = {
1350 .open = snd_intel8x0_playback_open,
1351 .close = snd_intel8x0_playback_close,
1352 .ioctl = snd_pcm_lib_ioctl,
1353 .hw_params = snd_intel8x0_hw_params,
1354 .hw_free = snd_intel8x0_hw_free,
1355 .prepare = snd_intel8x0_pcm_prepare,
1356 .trigger = snd_intel8x0_pcm_trigger,
1357 .pointer = snd_intel8x0_pcm_pointer,
1358};
1359
1360static struct snd_pcm_ops snd_intel8x0_capture_ops = {
1361 .open = snd_intel8x0_capture_open,
1362 .close = snd_intel8x0_capture_close,
1363 .ioctl = snd_pcm_lib_ioctl,
1364 .hw_params = snd_intel8x0_hw_params,
1365 .hw_free = snd_intel8x0_hw_free,
1366 .prepare = snd_intel8x0_pcm_prepare,
1367 .trigger = snd_intel8x0_pcm_trigger,
1368 .pointer = snd_intel8x0_pcm_pointer,
1369};
1370
1371static struct snd_pcm_ops snd_intel8x0_capture_mic_ops = {
1372 .open = snd_intel8x0_mic_open,
1373 .close = snd_intel8x0_mic_close,
1374 .ioctl = snd_pcm_lib_ioctl,
1375 .hw_params = snd_intel8x0_hw_params,
1376 .hw_free = snd_intel8x0_hw_free,
1377 .prepare = snd_intel8x0_pcm_prepare,
1378 .trigger = snd_intel8x0_pcm_trigger,
1379 .pointer = snd_intel8x0_pcm_pointer,
1380};
1381
1382static struct snd_pcm_ops snd_intel8x0_capture_mic2_ops = {
1383 .open = snd_intel8x0_mic2_open,
1384 .close = snd_intel8x0_mic2_close,
1385 .ioctl = snd_pcm_lib_ioctl,
1386 .hw_params = snd_intel8x0_hw_params,
1387 .hw_free = snd_intel8x0_hw_free,
1388 .prepare = snd_intel8x0_pcm_prepare,
1389 .trigger = snd_intel8x0_pcm_trigger,
1390 .pointer = snd_intel8x0_pcm_pointer,
1391};
1392
1393static struct snd_pcm_ops snd_intel8x0_capture2_ops = {
1394 .open = snd_intel8x0_capture2_open,
1395 .close = snd_intel8x0_capture2_close,
1396 .ioctl = snd_pcm_lib_ioctl,
1397 .hw_params = snd_intel8x0_hw_params,
1398 .hw_free = snd_intel8x0_hw_free,
1399 .prepare = snd_intel8x0_pcm_prepare,
1400 .trigger = snd_intel8x0_pcm_trigger,
1401 .pointer = snd_intel8x0_pcm_pointer,
1402};
1403
1404static struct snd_pcm_ops snd_intel8x0_spdif_ops = {
1405 .open = snd_intel8x0_spdif_open,
1406 .close = snd_intel8x0_spdif_close,
1407 .ioctl = snd_pcm_lib_ioctl,
1408 .hw_params = snd_intel8x0_hw_params,
1409 .hw_free = snd_intel8x0_hw_free,
1410 .prepare = snd_intel8x0_pcm_prepare,
1411 .trigger = snd_intel8x0_pcm_trigger,
1412 .pointer = snd_intel8x0_pcm_pointer,
1413};
1414
1415static struct snd_pcm_ops snd_intel8x0_ali_playback_ops = {
1416 .open = snd_intel8x0_playback_open,
1417 .close = snd_intel8x0_playback_close,
1418 .ioctl = snd_pcm_lib_ioctl,
1419 .hw_params = snd_intel8x0_hw_params,
1420 .hw_free = snd_intel8x0_hw_free,
1421 .prepare = snd_intel8x0_pcm_prepare,
1422 .trigger = snd_intel8x0_ali_trigger,
1423 .pointer = snd_intel8x0_pcm_pointer,
1424};
1425
1426static struct snd_pcm_ops snd_intel8x0_ali_capture_ops = {
1427 .open = snd_intel8x0_capture_open,
1428 .close = snd_intel8x0_capture_close,
1429 .ioctl = snd_pcm_lib_ioctl,
1430 .hw_params = snd_intel8x0_hw_params,
1431 .hw_free = snd_intel8x0_hw_free,
1432 .prepare = snd_intel8x0_pcm_prepare,
1433 .trigger = snd_intel8x0_ali_trigger,
1434 .pointer = snd_intel8x0_pcm_pointer,
1435};
1436
1437static struct snd_pcm_ops snd_intel8x0_ali_capture_mic_ops = {
1438 .open = snd_intel8x0_mic_open,
1439 .close = snd_intel8x0_mic_close,
1440 .ioctl = snd_pcm_lib_ioctl,
1441 .hw_params = snd_intel8x0_hw_params,
1442 .hw_free = snd_intel8x0_hw_free,
1443 .prepare = snd_intel8x0_pcm_prepare,
1444 .trigger = snd_intel8x0_ali_trigger,
1445 .pointer = snd_intel8x0_pcm_pointer,
1446};
1447
1448static struct snd_pcm_ops snd_intel8x0_ali_ac97spdifout_ops = {
1449 .open = snd_intel8x0_ali_ac97spdifout_open,
1450 .close = snd_intel8x0_ali_ac97spdifout_close,
1451 .ioctl = snd_pcm_lib_ioctl,
1452 .hw_params = snd_intel8x0_hw_params,
1453 .hw_free = snd_intel8x0_hw_free,
1454 .prepare = snd_intel8x0_pcm_prepare,
1455 .trigger = snd_intel8x0_ali_trigger,
1456 .pointer = snd_intel8x0_pcm_pointer,
1457};
1458
1459#if 0 // NYI
1460static struct snd_pcm_ops snd_intel8x0_ali_spdifin_ops = {
1461 .open = snd_intel8x0_ali_spdifin_open,
1462 .close = snd_intel8x0_ali_spdifin_close,
1463 .ioctl = snd_pcm_lib_ioctl,
1464 .hw_params = snd_intel8x0_hw_params,
1465 .hw_free = snd_intel8x0_hw_free,
1466 .prepare = snd_intel8x0_pcm_prepare,
1467 .trigger = snd_intel8x0_pcm_trigger,
1468 .pointer = snd_intel8x0_pcm_pointer,
1469};
1470
1471static struct snd_pcm_ops snd_intel8x0_ali_spdifout_ops = {
1472 .open = snd_intel8x0_ali_spdifout_open,
1473 .close = snd_intel8x0_ali_spdifout_close,
1474 .ioctl = snd_pcm_lib_ioctl,
1475 .hw_params = snd_intel8x0_hw_params,
1476 .hw_free = snd_intel8x0_hw_free,
1477 .prepare = snd_intel8x0_pcm_prepare,
1478 .trigger = snd_intel8x0_pcm_trigger,
1479 .pointer = snd_intel8x0_pcm_pointer,
1480};
1481#endif // NYI
1482
1483struct ich_pcm_table {
1484 char *suffix;
1485 struct snd_pcm_ops *playback_ops;
1486 struct snd_pcm_ops *capture_ops;
1487 size_t prealloc_size;
1488 size_t prealloc_max_size;
1489 int ac97_idx;
1490};
1491
1492static int __devinit snd_intel8x0_pcm1(struct intel8x0 *chip, int device,
1493 struct ich_pcm_table *rec)
1494{
1495 struct snd_pcm *pcm;
1496 int err;
1497 char name[32];
1498
1499 if (rec->suffix)
1500 sprintf(name, "Intel ICH - %s", rec->suffix);
1501 else
1502 strcpy(name, "Intel ICH");
1503 err = snd_pcm_new(chip->card, name, device,
1504 rec->playback_ops ? 1 : 0,
1505 rec->capture_ops ? 1 : 0, &pcm);
1506 if (err < 0)
1507 return err;
1508
1509 if (rec->playback_ops)
1510 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, rec->playback_ops);
1511 if (rec->capture_ops)
1512 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, rec->capture_ops);
1513
1514 pcm->private_data = chip;
1515 pcm->info_flags = 0;
1516 if (rec->suffix)
1517 sprintf(pcm->name, "%s - %s", chip->card->shortname, rec->suffix);
1518 else
1519 strcpy(pcm->name, chip->card->shortname);
1520 chip->pcm[device] = pcm;
1521
1522 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1523 snd_dma_pci_data(chip->pci),
1524 rec->prealloc_size, rec->prealloc_max_size);
1525
1526 return 0;
1527}
1528
1529static struct ich_pcm_table intel_pcms[] __devinitdata = {
1530 {
1531 .playback_ops = &snd_intel8x0_playback_ops,
1532 .capture_ops = &snd_intel8x0_capture_ops,
1533 .prealloc_size = 64 * 1024,
1534 .prealloc_max_size = 128 * 1024,
1535 },
1536 {
1537 .suffix = "MIC ADC",
1538 .capture_ops = &snd_intel8x0_capture_mic_ops,
1539 .prealloc_size = 0,
1540 .prealloc_max_size = 128 * 1024,
1541 .ac97_idx = ICHD_MIC,
1542 },
1543 {
1544 .suffix = "MIC2 ADC",
1545 .capture_ops = &snd_intel8x0_capture_mic2_ops,
1546 .prealloc_size = 0,
1547 .prealloc_max_size = 128 * 1024,
1548 .ac97_idx = ICHD_MIC2,
1549 },
1550 {
1551 .suffix = "ADC2",
1552 .capture_ops = &snd_intel8x0_capture2_ops,
1553 .prealloc_size = 0,
1554 .prealloc_max_size = 128 * 1024,
1555 .ac97_idx = ICHD_PCM2IN,
1556 },
1557 {
1558 .suffix = "IEC958",
1559 .playback_ops = &snd_intel8x0_spdif_ops,
1560 .prealloc_size = 64 * 1024,
1561 .prealloc_max_size = 128 * 1024,
1562 .ac97_idx = ICHD_SPBAR,
1563 },
1564};
1565
1566static struct ich_pcm_table nforce_pcms[] __devinitdata = {
1567 {
1568 .playback_ops = &snd_intel8x0_playback_ops,
1569 .capture_ops = &snd_intel8x0_capture_ops,
1570 .prealloc_size = 64 * 1024,
1571 .prealloc_max_size = 128 * 1024,
1572 },
1573 {
1574 .suffix = "MIC ADC",
1575 .capture_ops = &snd_intel8x0_capture_mic_ops,
1576 .prealloc_size = 0,
1577 .prealloc_max_size = 128 * 1024,
1578 .ac97_idx = NVD_MIC,
1579 },
1580 {
1581 .suffix = "IEC958",
1582 .playback_ops = &snd_intel8x0_spdif_ops,
1583 .prealloc_size = 64 * 1024,
1584 .prealloc_max_size = 128 * 1024,
1585 .ac97_idx = NVD_SPBAR,
1586 },
1587};
1588
1589static struct ich_pcm_table ali_pcms[] __devinitdata = {
1590 {
1591 .playback_ops = &snd_intel8x0_ali_playback_ops,
1592 .capture_ops = &snd_intel8x0_ali_capture_ops,
1593 .prealloc_size = 64 * 1024,
1594 .prealloc_max_size = 128 * 1024,
1595 },
1596 {
1597 .suffix = "MIC ADC",
1598 .capture_ops = &snd_intel8x0_ali_capture_mic_ops,
1599 .prealloc_size = 0,
1600 .prealloc_max_size = 128 * 1024,
1601 .ac97_idx = ALID_MIC,
1602 },
1603 {
1604 .suffix = "IEC958",
1605 .playback_ops = &snd_intel8x0_ali_ac97spdifout_ops,
1606 /* .capture_ops = &snd_intel8x0_ali_spdifin_ops, */
1607 .prealloc_size = 64 * 1024,
1608 .prealloc_max_size = 128 * 1024,
1609 .ac97_idx = ALID_AC97SPDIFOUT,
1610 },
1611#if 0 // NYI
1612 {
1613 .suffix = "HW IEC958",
1614 .playback_ops = &snd_intel8x0_ali_spdifout_ops,
1615 .prealloc_size = 64 * 1024,
1616 .prealloc_max_size = 128 * 1024,
1617 },
1618#endif
1619};
1620
1621static int __devinit snd_intel8x0_pcm(struct intel8x0 *chip)
1622{
1623 int i, tblsize, device, err;
1624 struct ich_pcm_table *tbl, *rec;
1625
1626 switch (chip->device_type) {
1627 case DEVICE_INTEL_ICH4:
1628 tbl = intel_pcms;
1629 tblsize = ARRAY_SIZE(intel_pcms);
1630 if (spdif_aclink)
1631 tblsize--;
1632 break;
1633 case DEVICE_NFORCE:
1634 tbl = nforce_pcms;
1635 tblsize = ARRAY_SIZE(nforce_pcms);
1636 if (spdif_aclink)
1637 tblsize--;
1638 break;
1639 case DEVICE_ALI:
1640 tbl = ali_pcms;
1641 tblsize = ARRAY_SIZE(ali_pcms);
1642 break;
1643 default:
1644 tbl = intel_pcms;
1645 tblsize = 2;
1646 break;
1647 }
1648
1649 device = 0;
1650 for (i = 0; i < tblsize; i++) {
1651 rec = tbl + i;
1652 if (i > 0 && rec->ac97_idx) {
1653 /* activate PCM only when associated AC'97 codec */
1654 if (! chip->ichd[rec->ac97_idx].pcm)
1655 continue;
1656 }
1657 err = snd_intel8x0_pcm1(chip, device, rec);
1658 if (err < 0)
1659 return err;
1660 device++;
1661 }
1662
1663 chip->pcm_devs = device;
1664 return 0;
1665}
1666
1667
1668/*
1669 * Mixer part
1670 */
1671
1672static void snd_intel8x0_mixer_free_ac97_bus(struct snd_ac97_bus *bus)
1673{
1674 struct intel8x0 *chip = bus->private_data;
1675 chip->ac97_bus = NULL;
1676}
1677
1678static void snd_intel8x0_mixer_free_ac97(struct snd_ac97 *ac97)
1679{
1680 struct intel8x0 *chip = ac97->private_data;
1681 chip->ac97[ac97->num] = NULL;
1682}
1683
1684static struct ac97_pcm ac97_pcm_defs[] __devinitdata = {
1685 /* front PCM */
1686 {
1687 .exclusive = 1,
1688 .r =
1689 {
1690 {
1691 .slots = (1 << AC97_SLOT_PCM_LEFT) |
1692 (1 << AC97_SLOT_PCM_RIGHT) |
1693 (1 << AC97_SLOT_PCM_CENTER) |
1694 (1 << AC97_SLOT_PCM_SLEFT) |
1695 (1 << AC97_SLOT_PCM_SRIGHT) |
1696 (1 << AC97_SLOT_LFE)
1697 },
1698 {
1699 .slots = (1 << AC97_SLOT_PCM_LEFT) |
1700 (1 << AC97_SLOT_PCM_RIGHT) |
1701 (1 << AC97_SLOT_PCM_LEFT_0) |
1702 (1 << AC97_SLOT_PCM_RIGHT_0)
1703 }
1704 }
1705 },
1706 /* PCM IN #1 */
1707 {
1708 .stream = 1,
1709 .exclusive = 1,
1710 .r = { {
1711 .slots = (1 << AC97_SLOT_PCM_LEFT) |
1712 (1 << AC97_SLOT_PCM_RIGHT)
1713 }
1714 }
1715 },
1716 /* MIC IN #1 */
1717 {
1718 .stream = 1,
1719 .exclusive = 1,
1720 .r = { {
1721 .slots = (1 << AC97_SLOT_MIC)
1722 }
1723 }
1724 },
1725 /* S/PDIF PCM */
1726 {
1727 .exclusive = 1,
1728 .spdif = 1,
1729 .r = { {
1730 .slots = (1 << AC97_SLOT_SPDIF_LEFT2) |
1731 (1 << AC97_SLOT_SPDIF_RIGHT2)
1732 }
1733 }
1734 },
1735 /* PCM IN #2 */
1736 {
1737 .stream = 1,
1738 .exclusive = 1,
1739 .r = { {
1740 .slots = (1 << AC97_SLOT_PCM_LEFT) |
1741 (1 << AC97_SLOT_PCM_RIGHT)
1742 }
1743 }
1744 },
1745 /* MIC IN #2 */
1746 {
1747 .stream = 1,
1748 .exclusive = 1,
1749 .r = { {
1750 .slots = (1 << AC97_SLOT_MIC)
1751 }
1752 }
1753 },
1754};
1755
1756static struct ac97_quirk ac97_quirks[] __devinitdata = {
1757 {
1758 .subvendor = 0x0e11,
1759 .subdevice = 0x000e,
1760 .name = "Compaq Deskpro EN", /* AD1885 */
1761 .type = AC97_TUNE_HP_ONLY
1762 },
1763 {
1764 .subvendor = 0x0e11,
1765 .subdevice = 0x008a,
1766 .name = "Compaq Evo W4000", /* AD1885 */
1767 .type = AC97_TUNE_HP_ONLY
1768 },
1769 {
1770 .subvendor = 0x0e11,
1771 .subdevice = 0x00b8,
1772 .name = "Compaq Evo D510C",
1773 .type = AC97_TUNE_HP_ONLY
1774 },
1775 {
1776 .subvendor = 0x0e11,
1777 .subdevice = 0x0860,
1778 .name = "HP/Compaq nx7010",
1779 .type = AC97_TUNE_MUTE_LED
1780 },
1781 {
1782 .subvendor = 0x1014,
1783 .subdevice = 0x1f00,
1784 .name = "MS-9128",
1785 .type = AC97_TUNE_ALC_JACK
1786 },
1787 {
1788 .subvendor = 0x1014,
1789 .subdevice = 0x0267,
1790 .name = "IBM NetVista A30p", /* AD1981B */
1791 .type = AC97_TUNE_HP_ONLY
1792 },
1793 {
1794 .subvendor = 0x1025,
1795 .subdevice = 0x0082,
1796 .name = "Acer Travelmate 2310",
1797 .type = AC97_TUNE_HP_ONLY
1798 },
1799 {
1800 .subvendor = 0x1025,
1801 .subdevice = 0x0083,
1802 .name = "Acer Aspire 3003LCi",
1803 .type = AC97_TUNE_HP_ONLY
1804 },
1805 {
1806 .subvendor = 0x1028,
1807 .subdevice = 0x00d8,
1808 .name = "Dell Precision 530", /* AD1885 */
1809 .type = AC97_TUNE_HP_ONLY
1810 },
1811 {
1812 .subvendor = 0x1028,
1813 .subdevice = 0x010d,
1814 .name = "Dell", /* which model? AD1885 */
1815 .type = AC97_TUNE_HP_ONLY
1816 },
1817 {
1818 .subvendor = 0x1028,
1819 .subdevice = 0x0126,
1820 .name = "Dell Optiplex GX260", /* AD1981A */
1821 .type = AC97_TUNE_HP_ONLY
1822 },
1823 {
1824 .subvendor = 0x1028,
1825 .subdevice = 0x012c,
1826 .name = "Dell Precision 650", /* AD1981A */
1827 .type = AC97_TUNE_HP_ONLY
1828 },
1829 {
1830 .subvendor = 0x1028,
1831 .subdevice = 0x012d,
1832 .name = "Dell Precision 450", /* AD1981B*/
1833 .type = AC97_TUNE_HP_ONLY
1834 },
1835 {
1836 .subvendor = 0x1028,
1837 .subdevice = 0x0147,
1838 .name = "Dell", /* which model? AD1981B*/
1839 .type = AC97_TUNE_HP_ONLY
1840 },
1841 {
1842 .subvendor = 0x1028,
1843 .subdevice = 0x0151,
1844 .name = "Dell Optiplex GX270", /* AD1981B */
1845 .type = AC97_TUNE_HP_ONLY
1846 },
1847 {
1848 .subvendor = 0x1028,
1849 .subdevice = 0x014e,
1850 .name = "Dell D800", /* STAC9750/51 */
1851 .type = AC97_TUNE_HP_ONLY
1852 },
1853 {
1854 .subvendor = 0x1028,
1855 .subdevice = 0x0163,
1856 .name = "Dell Unknown", /* STAC9750/51 */
1857 .type = AC97_TUNE_HP_ONLY
1858 },
1859 {
1860 .subvendor = 0x1028,
1861 .subdevice = 0x016a,
1862 .name = "Dell Inspiron 8600", /* STAC9750/51 */
1863 .type = AC97_TUNE_HP_ONLY
1864 },
1865 {
1866 .subvendor = 0x1028,
1867 .subdevice = 0x0186,
1868 .name = "Dell Latitude D810", /* cf. Malone #41015 */
1869 .type = AC97_TUNE_HP_MUTE_LED
1870 },
1871 {
1872 .subvendor = 0x1028,
1873 .subdevice = 0x0188,
1874 .name = "Dell Inspiron 6000",
1875 .type = AC97_TUNE_HP_MUTE_LED /* cf. Malone #41015 */
1876 },
1877 {
1878 .subvendor = 0x1028,
1879 .subdevice = 0x0191,
1880 .name = "Dell Inspiron 8600",
1881 .type = AC97_TUNE_HP_ONLY
1882 },
1883 {
1884 .subvendor = 0x103c,
1885 .subdevice = 0x006d,
1886 .name = "HP zv5000",
1887 .type = AC97_TUNE_MUTE_LED /*AD1981B*/
1888 },
1889 { /* FIXME: which codec? */
1890 .subvendor = 0x103c,
1891 .subdevice = 0x00c3,
1892 .name = "HP xw6000",
1893 .type = AC97_TUNE_HP_ONLY
1894 },
1895 {
1896 .subvendor = 0x103c,
1897 .subdevice = 0x088c,
1898 .name = "HP nc8000",
1899 .type = AC97_TUNE_HP_MUTE_LED
1900 },
1901 {
1902 .subvendor = 0x103c,
1903 .subdevice = 0x0890,
1904 .name = "HP nc6000",
1905 .type = AC97_TUNE_MUTE_LED
1906 },
1907 {
1908 .subvendor = 0x103c,
1909 .subdevice = 0x129d,
1910 .name = "HP xw8000",
1911 .type = AC97_TUNE_HP_ONLY
1912 },
1913 {
1914 .subvendor = 0x103c,
1915 .subdevice = 0x0938,
1916 .name = "HP nc4200",
1917 .type = AC97_TUNE_HP_MUTE_LED
1918 },
1919 {
1920 .subvendor = 0x103c,
1921 .subdevice = 0x099c,
1922 .name = "HP nx6110/nc6120",
1923 .type = AC97_TUNE_HP_MUTE_LED
1924 },
1925 {
1926 .subvendor = 0x103c,
1927 .subdevice = 0x0944,
1928 .name = "HP nc6220",
1929 .type = AC97_TUNE_HP_MUTE_LED
1930 },
1931 {
1932 .subvendor = 0x103c,
1933 .subdevice = 0x0934,
1934 .name = "HP nc8220",
1935 .type = AC97_TUNE_HP_MUTE_LED
1936 },
1937 {
1938 .subvendor = 0x103c,
1939 .subdevice = 0x12f1,
1940 .name = "HP xw8200", /* AD1981B*/
1941 .type = AC97_TUNE_HP_ONLY
1942 },
1943 {
1944 .subvendor = 0x103c,
1945 .subdevice = 0x12f2,
1946 .name = "HP xw6200",
1947 .type = AC97_TUNE_HP_ONLY
1948 },
1949 {
1950 .subvendor = 0x103c,
1951 .subdevice = 0x3008,
1952 .name = "HP xw4200", /* AD1981B*/
1953 .type = AC97_TUNE_HP_ONLY
1954 },
1955 {
1956 .subvendor = 0x104d,
1957 .subdevice = 0x8197,
1958 .name = "Sony S1XP",
1959 .type = AC97_TUNE_INV_EAPD
1960 },
1961 {
1962 .subvendor = 0x1043,
1963 .subdevice = 0x80f3,
1964 .name = "ASUS ICH5/AD1985",
1965 .type = AC97_TUNE_AD_SHARING
1966 },
1967 {
1968 .subvendor = 0x10cf,
1969 .subdevice = 0x11c3,
1970 .name = "Fujitsu-Siemens E4010",
1971 .type = AC97_TUNE_HP_ONLY
1972 },
1973 {
1974 .subvendor = 0x10cf,
1975 .subdevice = 0x1225,
1976 .name = "Fujitsu-Siemens T3010",
1977 .type = AC97_TUNE_HP_ONLY
1978 },
1979 {
1980 .subvendor = 0x10cf,
1981 .subdevice = 0x1253,
1982 .name = "Fujitsu S6210", /* STAC9750/51 */
1983 .type = AC97_TUNE_HP_ONLY
1984 },
1985 {
1986 .subvendor = 0x10cf,
1987 .subdevice = 0x127d,
1988 .name = "Fujitsu Lifebook P7010",
1989 .type = AC97_TUNE_HP_ONLY
1990 },
1991 {
1992 .subvendor = 0x10cf,
1993 .subdevice = 0x127e,
1994 .name = "Fujitsu Lifebook C1211D",
1995 .type = AC97_TUNE_HP_ONLY
1996 },
1997 {
1998 .subvendor = 0x10cf,
1999 .subdevice = 0x12ec,
2000 .name = "Fujitsu-Siemens 4010",
2001 .type = AC97_TUNE_HP_ONLY
2002 },
2003 {
2004 .subvendor = 0x10cf,
2005 .subdevice = 0x12f2,
2006 .name = "Fujitsu-Siemens Celsius H320",
2007 .type = AC97_TUNE_SWAP_HP
2008 },
2009 {
2010 .subvendor = 0x10f1,
2011 .subdevice = 0x2665,
2012 .name = "Fujitsu-Siemens Celsius", /* AD1981? */
2013 .type = AC97_TUNE_HP_ONLY
2014 },
2015 {
2016 .subvendor = 0x10f1,
2017 .subdevice = 0x2885,
2018 .name = "AMD64 Mobo", /* ALC650 */
2019 .type = AC97_TUNE_HP_ONLY
2020 },
2021 {
2022 .subvendor = 0x10f1,
2023 .subdevice = 0x2895,
2024 .name = "Tyan Thunder K8WE",
2025 .type = AC97_TUNE_HP_ONLY
2026 },
2027 {
2028 .subvendor = 0x10f7,
2029 .subdevice = 0x834c,
2030 .name = "Panasonic CF-R4",
2031 .type = AC97_TUNE_HP_ONLY,
2032 },
2033 {
2034 .subvendor = 0x110a,
2035 .subdevice = 0x0056,
2036 .name = "Fujitsu-Siemens Scenic", /* AD1981? */
2037 .type = AC97_TUNE_HP_ONLY
2038 },
2039 {
2040 .subvendor = 0x11d4,
2041 .subdevice = 0x5375,
2042 .name = "ADI AD1985 (discrete)",
2043 .type = AC97_TUNE_HP_ONLY
2044 },
2045 {
2046 .subvendor = 0x1462,
2047 .subdevice = 0x5470,
2048 .name = "MSI P4 ATX 645 Ultra",
2049 .type = AC97_TUNE_HP_ONLY
2050 },
2051 {
2052 .subvendor = 0x1734,
2053 .subdevice = 0x0088,
2054 .name = "Fujitsu-Siemens D1522", /* AD1981 */
2055 .type = AC97_TUNE_HP_ONLY
2056 },
2057 {
2058 .subvendor = 0x8086,
2059 .subdevice = 0x2000,
2060 .mask = 0xfff0,
2061 .name = "Intel ICH5/AD1985",
2062 .type = AC97_TUNE_AD_SHARING
2063 },
2064 {
2065 .subvendor = 0x8086,
2066 .subdevice = 0x4000,
2067 .mask = 0xfff0,
2068 .name = "Intel ICH5/AD1985",
2069 .type = AC97_TUNE_AD_SHARING
2070 },
2071 {
2072 .subvendor = 0x8086,
2073 .subdevice = 0x4856,
2074 .name = "Intel D845WN (82801BA)",
2075 .type = AC97_TUNE_SWAP_HP
2076 },
2077 {
2078 .subvendor = 0x8086,
2079 .subdevice = 0x4d44,
2080 .name = "Intel D850EMV2", /* AD1885 */
2081 .type = AC97_TUNE_HP_ONLY
2082 },
2083 {
2084 .subvendor = 0x8086,
2085 .subdevice = 0x4d56,
2086 .name = "Intel ICH/AD1885",
2087 .type = AC97_TUNE_HP_ONLY
2088 },
2089 {
2090 .subvendor = 0x8086,
2091 .subdevice = 0x6000,
2092 .mask = 0xfff0,
2093 .name = "Intel ICH5/AD1985",
2094 .type = AC97_TUNE_AD_SHARING
2095 },
2096 {
2097 .subvendor = 0x8086,
2098 .subdevice = 0xe000,
2099 .mask = 0xfff0,
2100 .name = "Intel ICH5/AD1985",
2101 .type = AC97_TUNE_AD_SHARING
2102 },
2103#if 0 /* FIXME: this seems wrong on most boards */
2104 {
2105 .subvendor = 0x8086,
2106 .subdevice = 0xa000,
2107 .mask = 0xfff0,
2108 .name = "Intel ICH5/AD1985",
2109 .type = AC97_TUNE_HP_ONLY
2110 },
2111#endif
2112 {0} /* terminator */
2113};
2114
2115static int __devinit snd_intel8x0_mixer(struct intel8x0 *chip, int ac97_clock,
2116 const char *quirk_override)
2117{
2118 struct snd_ac97_bus *pbus;
2119 struct snd_ac97_template ac97;
2120 int err;
2121 unsigned int i, codecs;
2122 unsigned int glob_sta = 0;
2123 struct snd_ac97_bus_ops *ops;
2124 static struct snd_ac97_bus_ops standard_bus_ops = {
2125 .write = snd_intel8x0_codec_write,
2126 .read = snd_intel8x0_codec_read,
2127 };
2128 static struct snd_ac97_bus_ops ali_bus_ops = {
2129 .write = snd_intel8x0_ali_codec_write,
2130 .read = snd_intel8x0_ali_codec_read,
2131 };
2132
2133 chip->spdif_idx = -1; /* use PCMOUT (or disabled) */
2134 if (!spdif_aclink) {
2135 switch (chip->device_type) {
2136 case DEVICE_NFORCE:
2137 chip->spdif_idx = NVD_SPBAR;
2138 break;
2139 case DEVICE_ALI:
2140 chip->spdif_idx = ALID_AC97SPDIFOUT;
2141 break;
2142 case DEVICE_INTEL_ICH4:
2143 chip->spdif_idx = ICHD_SPBAR;
2144 break;
2145 };
2146 }
2147
2148 chip->in_ac97_init = 1;
2149
2150 memset(&ac97, 0, sizeof(ac97));
2151 ac97.private_data = chip;
2152 ac97.private_free = snd_intel8x0_mixer_free_ac97;
2153 ac97.scaps = AC97_SCAP_SKIP_MODEM | AC97_SCAP_POWER_SAVE;
2154 if (chip->xbox)
2155 ac97.scaps |= AC97_SCAP_DETECT_BY_VENDOR;
2156 if (chip->device_type != DEVICE_ALI) {
2157 glob_sta = igetdword(chip, ICHREG(GLOB_STA));
2158 ops = &standard_bus_ops;
2159 chip->in_sdin_init = 1;
2160 codecs = 0;
2161 for (i = 0; i < chip->max_codecs; i++) {
2162 if (! (glob_sta & chip->codec_bit[i]))
2163 continue;
2164 if (chip->device_type == DEVICE_INTEL_ICH4) {
2165 snd_intel8x0_codec_read_test(chip, codecs);
2166 chip->ac97_sdin[codecs] =
2167 igetbyte(chip, ICHREG(SDM)) & ICH_LDI_MASK;
2168 if (snd_BUG_ON(chip->ac97_sdin[codecs] >= 3))
2169 chip->ac97_sdin[codecs] = 0;
2170 } else
2171 chip->ac97_sdin[codecs] = i;
2172 codecs++;
2173 }
2174 chip->in_sdin_init = 0;
2175 if (! codecs)
2176 codecs = 1;
2177 } else {
2178 ops = &ali_bus_ops;
2179 codecs = 1;
2180 /* detect the secondary codec */
2181 for (i = 0; i < 100; i++) {
2182 unsigned int reg = igetdword(chip, ICHREG(ALI_RTSR));
2183 if (reg & 0x40) {
2184 codecs = 2;
2185 break;
2186 }
2187 iputdword(chip, ICHREG(ALI_RTSR), reg | 0x40);
2188 udelay(1);
2189 }
2190 }
2191 if ((err = snd_ac97_bus(chip->card, 0, ops, chip, &pbus)) < 0)
2192 goto __err;
2193 pbus->private_free = snd_intel8x0_mixer_free_ac97_bus;
2194 if (ac97_clock >= 8000 && ac97_clock <= 48000)
2195 pbus->clock = ac97_clock;
2196 /* FIXME: my test board doesn't work well with VRA... */
2197 if (chip->device_type == DEVICE_ALI)
2198 pbus->no_vra = 1;
2199 else
2200 pbus->dra = 1;
2201 chip->ac97_bus = pbus;
2202 chip->ncodecs = codecs;
2203
2204 ac97.pci = chip->pci;
2205 for (i = 0; i < codecs; i++) {
2206 ac97.num = i;
2207 if ((err = snd_ac97_mixer(pbus, &ac97, &chip->ac97[i])) < 0) {
2208 if (err != -EACCES)
2209 snd_printk(KERN_ERR "Unable to initialize codec #%d\n", i);
2210 if (i == 0)
2211 goto __err;
2212 }
2213 }
2214 /* tune up the primary codec */
2215 snd_ac97_tune_hardware(chip->ac97[0], ac97_quirks, quirk_override);
2216 /* enable separate SDINs for ICH4 */
2217 if (chip->device_type == DEVICE_INTEL_ICH4)
2218 pbus->isdin = 1;
2219 /* find the available PCM streams */
2220 i = ARRAY_SIZE(ac97_pcm_defs);
2221 if (chip->device_type != DEVICE_INTEL_ICH4)
2222 i -= 2; /* do not allocate PCM2IN and MIC2 */
2223 if (chip->spdif_idx < 0)
2224 i--; /* do not allocate S/PDIF */
2225 err = snd_ac97_pcm_assign(pbus, i, ac97_pcm_defs);
2226 if (err < 0)
2227 goto __err;
2228 chip->ichd[ICHD_PCMOUT].pcm = &pbus->pcms[0];
2229 chip->ichd[ICHD_PCMIN].pcm = &pbus->pcms[1];
2230 chip->ichd[ICHD_MIC].pcm = &pbus->pcms[2];
2231 if (chip->spdif_idx >= 0)
2232 chip->ichd[chip->spdif_idx].pcm = &pbus->pcms[3];
2233 if (chip->device_type == DEVICE_INTEL_ICH4) {
2234 chip->ichd[ICHD_PCM2IN].pcm = &pbus->pcms[4];
2235 chip->ichd[ICHD_MIC2].pcm = &pbus->pcms[5];
2236 }
2237 /* enable separate SDINs for ICH4 */
2238 if (chip->device_type == DEVICE_INTEL_ICH4) {
2239 struct ac97_pcm *pcm = chip->ichd[ICHD_PCM2IN].pcm;
2240 u8 tmp = igetbyte(chip, ICHREG(SDM));
2241 tmp &= ~(ICH_DI2L_MASK|ICH_DI1L_MASK);
2242 if (pcm) {
2243 tmp |= ICH_SE; /* steer enable for multiple SDINs */
2244 tmp |= chip->ac97_sdin[0] << ICH_DI1L_SHIFT;
2245 for (i = 1; i < 4; i++) {
2246 if (pcm->r[0].codec[i]) {
2247 tmp |= chip->ac97_sdin[pcm->r[0].codec[1]->num] << ICH_DI2L_SHIFT;
2248 break;
2249 }
2250 }
2251 } else {
2252 tmp &= ~ICH_SE; /* steer disable */
2253 }
2254 iputbyte(chip, ICHREG(SDM), tmp);
2255 }
2256 if (pbus->pcms[0].r[0].slots & (1 << AC97_SLOT_PCM_SLEFT)) {
2257 chip->multi4 = 1;
2258 if (pbus->pcms[0].r[0].slots & (1 << AC97_SLOT_LFE)) {
2259 chip->multi6 = 1;
2260 if (chip->ac97[0]->flags & AC97_HAS_8CH)
2261 chip->multi8 = 1;
2262 }
2263 }
2264 if (pbus->pcms[0].r[1].rslots[0]) {
2265 chip->dra = 1;
2266 }
2267 if (chip->device_type == DEVICE_INTEL_ICH4) {
2268 if ((igetdword(chip, ICHREG(GLOB_STA)) & ICH_SAMPLE_CAP) == ICH_SAMPLE_16_20)
2269 chip->smp20bit = 1;
2270 }
2271 if (chip->device_type == DEVICE_NFORCE && !spdif_aclink) {
2272 /* 48kHz only */
2273 chip->ichd[chip->spdif_idx].pcm->rates = SNDRV_PCM_RATE_48000;
2274 }
2275 if (chip->device_type == DEVICE_INTEL_ICH4 && !spdif_aclink) {
2276 /* use slot 10/11 for SPDIF */
2277 u32 val;
2278 val = igetdword(chip, ICHREG(GLOB_CNT)) & ~ICH_PCM_SPDIF_MASK;
2279 val |= ICH_PCM_SPDIF_1011;
2280 iputdword(chip, ICHREG(GLOB_CNT), val);
2281 snd_ac97_update_bits(chip->ac97[0], AC97_EXTENDED_STATUS, 0x03 << 4, 0x03 << 4);
2282 }
2283 chip->in_ac97_init = 0;
2284 return 0;
2285
2286 __err:
2287 /* clear the cold-reset bit for the next chance */
2288 if (chip->device_type != DEVICE_ALI)
2289 iputdword(chip, ICHREG(GLOB_CNT),
2290 igetdword(chip, ICHREG(GLOB_CNT)) & ~ICH_AC97COLD);
2291 return err;
2292}
2293
2294
2295/*
2296 *
2297 */
2298
2299static void do_ali_reset(struct intel8x0 *chip)
2300{
2301 iputdword(chip, ICHREG(ALI_SCR), ICH_ALI_SC_RESET);
2302 iputdword(chip, ICHREG(ALI_FIFOCR1), 0x83838383);
2303 iputdword(chip, ICHREG(ALI_FIFOCR2), 0x83838383);
2304 iputdword(chip, ICHREG(ALI_FIFOCR3), 0x83838383);
2305 iputdword(chip, ICHREG(ALI_INTERFACECR),
2306 ICH_ALI_IF_PI|ICH_ALI_IF_PO);
2307 iputdword(chip, ICHREG(ALI_INTERRUPTCR), 0x00000000);
2308 iputdword(chip, ICHREG(ALI_INTERRUPTSR), 0x00000000);
2309}
2310
2311#ifdef CONFIG_SND_AC97_POWER_SAVE
2312static struct snd_pci_quirk ich_chip_reset_mode[] = {
2313 SND_PCI_QUIRK(0x1014, 0x051f, "Thinkpad R32", 1),
2314 { } /* end */
2315};
2316
2317static int snd_intel8x0_ich_chip_cold_reset(struct intel8x0 *chip)
2318{
2319 unsigned int cnt;
2320 /* ACLink on, 2 channels */
2321
2322 if (snd_pci_quirk_lookup(chip->pci, ich_chip_reset_mode))
2323 return -EIO;
2324
2325 cnt = igetdword(chip, ICHREG(GLOB_CNT));
2326 cnt &= ~(ICH_ACLINK | ICH_PCM_246_MASK);
2327
2328 /* do cold reset - the full ac97 powerdown may leave the controller
2329 * in a warm state but actually it cannot communicate with the codec.
2330 */
2331 iputdword(chip, ICHREG(GLOB_CNT), cnt & ~ICH_AC97COLD);
2332 cnt = igetdword(chip, ICHREG(GLOB_CNT));
2333 udelay(10);
2334 iputdword(chip, ICHREG(GLOB_CNT), cnt | ICH_AC97COLD);
2335 msleep(1);
2336 return 0;
2337}
2338#define snd_intel8x0_ich_chip_can_cold_reset(chip) \
2339 (!snd_pci_quirk_lookup(chip->pci, ich_chip_reset_mode))
2340#else
2341#define snd_intel8x0_ich_chip_cold_reset(chip) 0
2342#define snd_intel8x0_ich_chip_can_cold_reset(chip) (0)
2343#endif
2344
2345static int snd_intel8x0_ich_chip_reset(struct intel8x0 *chip)
2346{
2347 unsigned long end_time;
2348 unsigned int cnt;
2349 /* ACLink on, 2 channels */
2350 cnt = igetdword(chip, ICHREG(GLOB_CNT));
2351 cnt &= ~(ICH_ACLINK | ICH_PCM_246_MASK);
2352 /* finish cold or do warm reset */
2353 cnt |= (cnt & ICH_AC97COLD) == 0 ? ICH_AC97COLD : ICH_AC97WARM;
2354 iputdword(chip, ICHREG(GLOB_CNT), cnt);
2355 end_time = (jiffies + (HZ / 4)) + 1;
2356 do {
2357 if ((igetdword(chip, ICHREG(GLOB_CNT)) & ICH_AC97WARM) == 0)
2358 return 0;
2359 schedule_timeout_uninterruptible(1);
2360 } while (time_after_eq(end_time, jiffies));
2361 snd_printk(KERN_ERR "AC'97 warm reset still in progress? [0x%x]\n",
2362 igetdword(chip, ICHREG(GLOB_CNT)));
2363 return -EIO;
2364}
2365
2366static int snd_intel8x0_ich_chip_init(struct intel8x0 *chip, int probing)
2367{
2368 unsigned long end_time;
2369 unsigned int status, nstatus;
2370 unsigned int cnt;
2371 int err;
2372
2373 /* put logic to right state */
2374 /* first clear status bits */
2375 status = ICH_RCS | ICH_MCINT | ICH_POINT | ICH_PIINT;
2376 if (chip->device_type == DEVICE_NFORCE)
2377 status |= ICH_NVSPINT;
2378 cnt = igetdword(chip, ICHREG(GLOB_STA));
2379 iputdword(chip, ICHREG(GLOB_STA), cnt & status);
2380
2381 if (snd_intel8x0_ich_chip_can_cold_reset(chip))
2382 err = snd_intel8x0_ich_chip_cold_reset(chip);
2383 else
2384 err = snd_intel8x0_ich_chip_reset(chip);
2385 if (err < 0)
2386 return err;
2387
2388 if (probing) {
2389 /* wait for any codec ready status.
2390 * Once it becomes ready it should remain ready
2391 * as long as we do not disable the ac97 link.
2392 */
2393 end_time = jiffies + HZ;
2394 do {
2395 status = igetdword(chip, ICHREG(GLOB_STA)) &
2396 chip->codec_isr_bits;
2397 if (status)
2398 break;
2399 schedule_timeout_uninterruptible(1);
2400 } while (time_after_eq(end_time, jiffies));
2401 if (! status) {
2402 /* no codec is found */
2403 snd_printk(KERN_ERR "codec_ready: codec is not ready [0x%x]\n",
2404 igetdword(chip, ICHREG(GLOB_STA)));
2405 return -EIO;
2406 }
2407
2408 /* wait for other codecs ready status. */
2409 end_time = jiffies + HZ / 4;
2410 while (status != chip->codec_isr_bits &&
2411 time_after_eq(end_time, jiffies)) {
2412 schedule_timeout_uninterruptible(1);
2413 status |= igetdword(chip, ICHREG(GLOB_STA)) &
2414 chip->codec_isr_bits;
2415 }
2416
2417 } else {
2418 /* resume phase */
2419 int i;
2420 status = 0;
2421 for (i = 0; i < chip->ncodecs; i++)
2422 if (chip->ac97[i])
2423 status |= chip->codec_bit[chip->ac97_sdin[i]];
2424 /* wait until all the probed codecs are ready */
2425 end_time = jiffies + HZ;
2426 do {
2427 nstatus = igetdword(chip, ICHREG(GLOB_STA)) &
2428 chip->codec_isr_bits;
2429 if (status == nstatus)
2430 break;
2431 schedule_timeout_uninterruptible(1);
2432 } while (time_after_eq(end_time, jiffies));
2433 }
2434
2435 if (chip->device_type == DEVICE_SIS) {
2436 /* unmute the output on SIS7012 */
2437 iputword(chip, 0x4c, igetword(chip, 0x4c) | 1);
2438 }
2439 if (chip->device_type == DEVICE_NFORCE && !spdif_aclink) {
2440 /* enable SPDIF interrupt */
2441 unsigned int val;
2442 pci_read_config_dword(chip->pci, 0x4c, &val);
2443 val |= 0x1000000;
2444 pci_write_config_dword(chip->pci, 0x4c, val);
2445 }
2446 return 0;
2447}
2448
2449static int snd_intel8x0_ali_chip_init(struct intel8x0 *chip, int probing)
2450{
2451 u32 reg;
2452 int i = 0;
2453
2454 reg = igetdword(chip, ICHREG(ALI_SCR));
2455 if ((reg & 2) == 0) /* Cold required */
2456 reg |= 2;
2457 else
2458 reg |= 1; /* Warm */
2459 reg &= ~0x80000000; /* ACLink on */
2460 iputdword(chip, ICHREG(ALI_SCR), reg);
2461
2462 for (i = 0; i < HZ / 2; i++) {
2463 if (! (igetdword(chip, ICHREG(ALI_INTERRUPTSR)) & ALI_INT_GPIO))
2464 goto __ok;
2465 schedule_timeout_uninterruptible(1);
2466 }
2467 snd_printk(KERN_ERR "AC'97 reset failed.\n");
2468 if (probing)
2469 return -EIO;
2470
2471 __ok:
2472 for (i = 0; i < HZ / 2; i++) {
2473 reg = igetdword(chip, ICHREG(ALI_RTSR));
2474 if (reg & 0x80) /* primary codec */
2475 break;
2476 iputdword(chip, ICHREG(ALI_RTSR), reg | 0x80);
2477 schedule_timeout_uninterruptible(1);
2478 }
2479
2480 do_ali_reset(chip);
2481 return 0;
2482}
2483
2484static int snd_intel8x0_chip_init(struct intel8x0 *chip, int probing)
2485{
2486 unsigned int i, timeout;
2487 int err;
2488
2489 if (chip->device_type != DEVICE_ALI) {
2490 if ((err = snd_intel8x0_ich_chip_init(chip, probing)) < 0)
2491 return err;
2492 iagetword(chip, 0); /* clear semaphore flag */
2493 } else {
2494 if ((err = snd_intel8x0_ali_chip_init(chip, probing)) < 0)
2495 return err;
2496 }
2497
2498 /* disable interrupts */
2499 for (i = 0; i < chip->bdbars_count; i++)
2500 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, 0x00);
2501 /* reset channels */
2502 for (i = 0; i < chip->bdbars_count; i++)
2503 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, ICH_RESETREGS);
2504 for (i = 0; i < chip->bdbars_count; i++) {
2505 timeout = 100000;
2506 while (--timeout != 0) {
2507 if ((igetbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset) & ICH_RESETREGS) == 0)
2508 break;
2509 }
2510 if (timeout == 0)
2511 printk(KERN_ERR "intel8x0: reset of registers failed?\n");
2512 }
2513 /* initialize Buffer Descriptor Lists */
2514 for (i = 0; i < chip->bdbars_count; i++)
2515 iputdword(chip, ICH_REG_OFF_BDBAR + chip->ichd[i].reg_offset,
2516 chip->ichd[i].bdbar_addr);
2517 return 0;
2518}
2519
2520static int snd_intel8x0_free(struct intel8x0 *chip)
2521{
2522 unsigned int i;
2523
2524 if (chip->irq < 0)
2525 goto __hw_end;
2526 /* disable interrupts */
2527 for (i = 0; i < chip->bdbars_count; i++)
2528 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, 0x00);
2529 /* reset channels */
2530 for (i = 0; i < chip->bdbars_count; i++)
2531 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, ICH_RESETREGS);
2532 if (chip->device_type == DEVICE_NFORCE && !spdif_aclink) {
2533 /* stop the spdif interrupt */
2534 unsigned int val;
2535 pci_read_config_dword(chip->pci, 0x4c, &val);
2536 val &= ~0x1000000;
2537 pci_write_config_dword(chip->pci, 0x4c, val);
2538 }
2539 /* --- */
2540
2541 __hw_end:
2542 if (chip->irq >= 0)
2543 free_irq(chip->irq, chip);
2544 if (chip->bdbars.area) {
2545 if (chip->fix_nocache)
2546 fill_nocache(chip->bdbars.area, chip->bdbars.bytes, 0);
2547 snd_dma_free_pages(&chip->bdbars);
2548 }
2549 if (chip->addr)
2550 pci_iounmap(chip->pci, chip->addr);
2551 if (chip->bmaddr)
2552 pci_iounmap(chip->pci, chip->bmaddr);
2553 pci_release_regions(chip->pci);
2554 pci_disable_device(chip->pci);
2555 kfree(chip);
2556 return 0;
2557}
2558
2559#ifdef CONFIG_PM
2560/*
2561 * power management
2562 */
2563static int intel8x0_suspend(struct pci_dev *pci, pm_message_t state)
2564{
2565 struct snd_card *card = pci_get_drvdata(pci);
2566 struct intel8x0 *chip = card->private_data;
2567 int i;
2568
2569 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
2570 for (i = 0; i < chip->pcm_devs; i++)
2571 snd_pcm_suspend_all(chip->pcm[i]);
2572 /* clear nocache */
2573 if (chip->fix_nocache) {
2574 for (i = 0; i < chip->bdbars_count; i++) {
2575 struct ichdev *ichdev = &chip->ichd[i];
2576 if (ichdev->substream && ichdev->page_attr_changed) {
2577 struct snd_pcm_runtime *runtime = ichdev->substream->runtime;
2578 if (runtime->dma_area)
2579 fill_nocache(runtime->dma_area, runtime->dma_bytes, 0);
2580 }
2581 }
2582 }
2583 for (i = 0; i < chip->ncodecs; i++)
2584 snd_ac97_suspend(chip->ac97[i]);
2585 if (chip->device_type == DEVICE_INTEL_ICH4)
2586 chip->sdm_saved = igetbyte(chip, ICHREG(SDM));
2587
2588 if (chip->irq >= 0) {
2589 free_irq(chip->irq, chip);
2590 chip->irq = -1;
2591 }
2592 pci_disable_device(pci);
2593 pci_save_state(pci);
2594 /* The call below may disable built-in speaker on some laptops
2595 * after S2RAM. So, don't touch it.
2596 */
2597 /* pci_set_power_state(pci, pci_choose_state(pci, state)); */
2598 return 0;
2599}
2600
2601static int intel8x0_resume(struct pci_dev *pci)
2602{
2603 struct snd_card *card = pci_get_drvdata(pci);
2604 struct intel8x0 *chip = card->private_data;
2605 int i;
2606
2607 pci_set_power_state(pci, PCI_D0);
2608 pci_restore_state(pci);
2609 if (pci_enable_device(pci) < 0) {
2610 printk(KERN_ERR "intel8x0: pci_enable_device failed, "
2611 "disabling device\n");
2612 snd_card_disconnect(card);
2613 return -EIO;
2614 }
2615 pci_set_master(pci);
2616 snd_intel8x0_chip_init(chip, 0);
2617 if (request_irq(pci->irq, snd_intel8x0_interrupt,
2618 IRQF_SHARED, card->shortname, chip)) {
2619 printk(KERN_ERR "intel8x0: unable to grab IRQ %d, "
2620 "disabling device\n", pci->irq);
2621 snd_card_disconnect(card);
2622 return -EIO;
2623 }
2624 chip->irq = pci->irq;
2625 synchronize_irq(chip->irq);
2626
2627 /* re-initialize mixer stuff */
2628 if (chip->device_type == DEVICE_INTEL_ICH4 && !spdif_aclink) {
2629 /* enable separate SDINs for ICH4 */
2630 iputbyte(chip, ICHREG(SDM), chip->sdm_saved);
2631 /* use slot 10/11 for SPDIF */
2632 iputdword(chip, ICHREG(GLOB_CNT),
2633 (igetdword(chip, ICHREG(GLOB_CNT)) & ~ICH_PCM_SPDIF_MASK) |
2634 ICH_PCM_SPDIF_1011);
2635 }
2636
2637 /* refill nocache */
2638 if (chip->fix_nocache)
2639 fill_nocache(chip->bdbars.area, chip->bdbars.bytes, 1);
2640
2641 for (i = 0; i < chip->ncodecs; i++)
2642 snd_ac97_resume(chip->ac97[i]);
2643
2644 /* refill nocache */
2645 if (chip->fix_nocache) {
2646 for (i = 0; i < chip->bdbars_count; i++) {
2647 struct ichdev *ichdev = &chip->ichd[i];
2648 if (ichdev->substream && ichdev->page_attr_changed) {
2649 struct snd_pcm_runtime *runtime = ichdev->substream->runtime;
2650 if (runtime->dma_area)
2651 fill_nocache(runtime->dma_area, runtime->dma_bytes, 1);
2652 }
2653 }
2654 }
2655
2656 /* resume status */
2657 for (i = 0; i < chip->bdbars_count; i++) {
2658 struct ichdev *ichdev = &chip->ichd[i];
2659 unsigned long port = ichdev->reg_offset;
2660 if (! ichdev->substream || ! ichdev->suspended)
2661 continue;
2662 if (ichdev->ichd == ICHD_PCMOUT)
2663 snd_intel8x0_setup_pcm_out(chip, ichdev->substream->runtime);
2664 iputdword(chip, port + ICH_REG_OFF_BDBAR, ichdev->bdbar_addr);
2665 iputbyte(chip, port + ICH_REG_OFF_LVI, ichdev->lvi);
2666 iputbyte(chip, port + ICH_REG_OFF_CIV, ichdev->civ);
2667 iputbyte(chip, port + ichdev->roff_sr, ICH_FIFOE | ICH_BCIS | ICH_LVBCI);
2668 }
2669
2670 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
2671 return 0;
2672}
2673#endif /* CONFIG_PM */
2674
2675#define INTEL8X0_TESTBUF_SIZE 32768 /* enough large for one shot */
2676
2677static void __devinit intel8x0_measure_ac97_clock(struct intel8x0 *chip)
2678{
2679 struct snd_pcm_substream *subs;
2680 struct ichdev *ichdev;
2681 unsigned long port;
2682 unsigned long pos, pos1, t;
2683 int civ, timeout = 1000, attempt = 1;
2684 struct timespec start_time, stop_time;
2685
2686 if (chip->ac97_bus->clock != 48000)
2687 return; /* specified in module option */
2688
2689 __again:
2690 subs = chip->pcm[0]->streams[0].substream;
2691 if (! subs || subs->dma_buffer.bytes < INTEL8X0_TESTBUF_SIZE) {
2692 snd_printk(KERN_WARNING "no playback buffer allocated - aborting measure ac97 clock\n");
2693 return;
2694 }
2695 ichdev = &chip->ichd[ICHD_PCMOUT];
2696 ichdev->physbuf = subs->dma_buffer.addr;
2697 ichdev->size = ichdev->fragsize = INTEL8X0_TESTBUF_SIZE;
2698 ichdev->substream = NULL; /* don't process interrupts */
2699
2700 /* set rate */
2701 if (snd_ac97_set_rate(chip->ac97[0], AC97_PCM_FRONT_DAC_RATE, 48000) < 0) {
2702 snd_printk(KERN_ERR "cannot set ac97 rate: clock = %d\n", chip->ac97_bus->clock);
2703 return;
2704 }
2705 snd_intel8x0_setup_periods(chip, ichdev);
2706 port = ichdev->reg_offset;
2707 spin_lock_irq(&chip->reg_lock);
2708 chip->in_measurement = 1;
2709 /* trigger */
2710 if (chip->device_type != DEVICE_ALI)
2711 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_IOCE | ICH_STARTBM);
2712 else {
2713 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_IOCE);
2714 iputdword(chip, ICHREG(ALI_DMACR), 1 << ichdev->ali_slot);
2715 }
2716 do_posix_clock_monotonic_gettime(&start_time);
2717 spin_unlock_irq(&chip->reg_lock);
2718 msleep(50);
2719 spin_lock_irq(&chip->reg_lock);
2720 /* check the position */
2721 do {
2722 civ = igetbyte(chip, ichdev->reg_offset + ICH_REG_OFF_CIV);
2723 pos1 = igetword(chip, ichdev->reg_offset + ichdev->roff_picb);
2724 if (pos1 == 0) {
2725 udelay(10);
2726 continue;
2727 }
2728 if (civ == igetbyte(chip, ichdev->reg_offset + ICH_REG_OFF_CIV) &&
2729 pos1 == igetword(chip, ichdev->reg_offset + ichdev->roff_picb))
2730 break;
2731 } while (timeout--);
2732 if (pos1 == 0) { /* oops, this value is not reliable */
2733 pos = 0;
2734 } else {
2735 pos = ichdev->fragsize1;
2736 pos -= pos1 << ichdev->pos_shift;
2737 pos += ichdev->position;
2738 }
2739 chip->in_measurement = 0;
2740 do_posix_clock_monotonic_gettime(&stop_time);
2741 /* stop */
2742 if (chip->device_type == DEVICE_ALI) {
2743 iputdword(chip, ICHREG(ALI_DMACR), 1 << (ichdev->ali_slot + 16));
2744 iputbyte(chip, port + ICH_REG_OFF_CR, 0);
2745 while (igetbyte(chip, port + ICH_REG_OFF_CR))
2746 ;
2747 } else {
2748 iputbyte(chip, port + ICH_REG_OFF_CR, 0);
2749 while (!(igetbyte(chip, port + ichdev->roff_sr) & ICH_DCH))
2750 ;
2751 }
2752 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_RESETREGS);
2753 spin_unlock_irq(&chip->reg_lock);
2754
2755 if (pos == 0) {
2756 snd_printk(KERN_ERR "intel8x0: measure - unreliable DMA position..\n");
2757 __retry:
2758 if (attempt < 3) {
2759 msleep(300);
2760 attempt++;
2761 goto __again;
2762 }
2763 goto __end;
2764 }
2765
2766 pos /= 4;
2767 t = stop_time.tv_sec - start_time.tv_sec;
2768 t *= 1000000;
2769 t += (stop_time.tv_nsec - start_time.tv_nsec) / 1000;
2770 printk(KERN_INFO "%s: measured %lu usecs (%lu samples)\n", __func__, t, pos);
2771 if (t == 0) {
2772 snd_printk(KERN_ERR "intel8x0: ?? calculation error..\n");
2773 goto __retry;
2774 }
2775 pos *= 1000;
2776 pos = (pos / t) * 1000 + ((pos % t) * 1000) / t;
2777 if (pos < 40000 || pos >= 60000) {
2778 /* abnormal value. hw problem? */
2779 printk(KERN_INFO "intel8x0: measured clock %ld rejected\n", pos);
2780 goto __retry;
2781 } else if (pos > 40500 && pos < 41500)
2782 /* first exception - 41000Hz reference clock */
2783 chip->ac97_bus->clock = 41000;
2784 else if (pos > 43600 && pos < 44600)
2785 /* second exception - 44100HZ reference clock */
2786 chip->ac97_bus->clock = 44100;
2787 else if (pos < 47500 || pos > 48500)
2788 /* not 48000Hz, tuning the clock.. */
2789 chip->ac97_bus->clock = (chip->ac97_bus->clock * 48000) / pos;
2790 __end:
2791 printk(KERN_INFO "intel8x0: clocking to %d\n", chip->ac97_bus->clock);
2792 snd_ac97_update_power(chip->ac97[0], AC97_PCM_FRONT_DAC_RATE, 0);
2793}
2794
2795static struct snd_pci_quirk intel8x0_clock_list[] __devinitdata = {
2796 SND_PCI_QUIRK(0x0e11, 0x008a, "AD1885", 41000),
2797 SND_PCI_QUIRK(0x1028, 0x00be, "AD1885", 44100),
2798 SND_PCI_QUIRK(0x1028, 0x0177, "AD1980", 48000),
2799 SND_PCI_QUIRK(0x1028, 0x01ad, "AD1981B", 48000),
2800 SND_PCI_QUIRK(0x1043, 0x80f3, "AD1985", 48000),
2801 {0} /* terminator */
2802};
2803
2804static int __devinit intel8x0_in_clock_list(struct intel8x0 *chip)
2805{
2806 struct pci_dev *pci = chip->pci;
2807 const struct snd_pci_quirk *wl;
2808
2809 wl = snd_pci_quirk_lookup(pci, intel8x0_clock_list);
2810 if (!wl)
2811 return 0;
2812 printk(KERN_INFO "intel8x0: white list rate for %04x:%04x is %i\n",
2813 pci->subsystem_vendor, pci->subsystem_device, wl->value);
2814 chip->ac97_bus->clock = wl->value;
2815 return 1;
2816}
2817
2818#ifdef CONFIG_PROC_FS
2819static void snd_intel8x0_proc_read(struct snd_info_entry * entry,
2820 struct snd_info_buffer *buffer)
2821{
2822 struct intel8x0 *chip = entry->private_data;
2823 unsigned int tmp;
2824
2825 snd_iprintf(buffer, "Intel8x0\n\n");
2826 if (chip->device_type == DEVICE_ALI)
2827 return;
2828 tmp = igetdword(chip, ICHREG(GLOB_STA));
2829 snd_iprintf(buffer, "Global control : 0x%08x\n", igetdword(chip, ICHREG(GLOB_CNT)));
2830 snd_iprintf(buffer, "Global status : 0x%08x\n", tmp);
2831 if (chip->device_type == DEVICE_INTEL_ICH4)
2832 snd_iprintf(buffer, "SDM : 0x%08x\n", igetdword(chip, ICHREG(SDM)));
2833 snd_iprintf(buffer, "AC'97 codecs ready :");
2834 if (tmp & chip->codec_isr_bits) {
2835 int i;
2836 static const char *codecs[3] = {
2837 "primary", "secondary", "tertiary"
2838 };
2839 for (i = 0; i < chip->max_codecs; i++)
2840 if (tmp & chip->codec_bit[i])
2841 snd_iprintf(buffer, " %s", codecs[i]);
2842 } else
2843 snd_iprintf(buffer, " none");
2844 snd_iprintf(buffer, "\n");
2845 if (chip->device_type == DEVICE_INTEL_ICH4 ||
2846 chip->device_type == DEVICE_SIS)
2847 snd_iprintf(buffer, "AC'97 codecs SDIN : %i %i %i\n",
2848 chip->ac97_sdin[0],
2849 chip->ac97_sdin[1],
2850 chip->ac97_sdin[2]);
2851}
2852
2853static void __devinit snd_intel8x0_proc_init(struct intel8x0 * chip)
2854{
2855 struct snd_info_entry *entry;
2856
2857 if (! snd_card_proc_new(chip->card, "intel8x0", &entry))
2858 snd_info_set_text_ops(entry, chip, snd_intel8x0_proc_read);
2859}
2860#else
2861#define snd_intel8x0_proc_init(x)
2862#endif
2863
2864static int snd_intel8x0_dev_free(struct snd_device *device)
2865{
2866 struct intel8x0 *chip = device->device_data;
2867 return snd_intel8x0_free(chip);
2868}
2869
2870struct ich_reg_info {
2871 unsigned int int_sta_mask;
2872 unsigned int offset;
2873};
2874
2875static unsigned int ich_codec_bits[3] = {
2876 ICH_PCR, ICH_SCR, ICH_TCR
2877};
2878static unsigned int sis_codec_bits[3] = {
2879 ICH_PCR, ICH_SCR, ICH_SIS_TCR
2880};
2881
2882static int __devinit snd_intel8x0_create(struct snd_card *card,
2883 struct pci_dev *pci,
2884 unsigned long device_type,
2885 struct intel8x0 ** r_intel8x0)
2886{
2887 struct intel8x0 *chip;
2888 int err;
2889 unsigned int i;
2890 unsigned int int_sta_masks;
2891 struct ichdev *ichdev;
2892 static struct snd_device_ops ops = {
2893 .dev_free = snd_intel8x0_dev_free,
2894 };
2895
2896 static unsigned int bdbars[] = {
2897 3, /* DEVICE_INTEL */
2898 6, /* DEVICE_INTEL_ICH4 */
2899 3, /* DEVICE_SIS */
2900 6, /* DEVICE_ALI */
2901 4, /* DEVICE_NFORCE */
2902 };
2903 static struct ich_reg_info intel_regs[6] = {
2904 { ICH_PIINT, 0 },
2905 { ICH_POINT, 0x10 },
2906 { ICH_MCINT, 0x20 },
2907 { ICH_M2INT, 0x40 },
2908 { ICH_P2INT, 0x50 },
2909 { ICH_SPINT, 0x60 },
2910 };
2911 static struct ich_reg_info nforce_regs[4] = {
2912 { ICH_PIINT, 0 },
2913 { ICH_POINT, 0x10 },
2914 { ICH_MCINT, 0x20 },
2915 { ICH_NVSPINT, 0x70 },
2916 };
2917 static struct ich_reg_info ali_regs[6] = {
2918 { ALI_INT_PCMIN, 0x40 },
2919 { ALI_INT_PCMOUT, 0x50 },
2920 { ALI_INT_MICIN, 0x60 },
2921 { ALI_INT_CODECSPDIFOUT, 0x70 },
2922 { ALI_INT_SPDIFIN, 0xa0 },
2923 { ALI_INT_SPDIFOUT, 0xb0 },
2924 };
2925 struct ich_reg_info *tbl;
2926
2927 *r_intel8x0 = NULL;
2928
2929 if ((err = pci_enable_device(pci)) < 0)
2930 return err;
2931
2932 chip = kzalloc(sizeof(*chip), GFP_KERNEL);
2933 if (chip == NULL) {
2934 pci_disable_device(pci);
2935 return -ENOMEM;
2936 }
2937 spin_lock_init(&chip->reg_lock);
2938 chip->device_type = device_type;
2939 chip->card = card;
2940 chip->pci = pci;
2941 chip->irq = -1;
2942
2943 /* module parameters */
2944 chip->buggy_irq = buggy_irq;
2945 chip->buggy_semaphore = buggy_semaphore;
2946 if (xbox)
2947 chip->xbox = 1;
2948
2949 if (pci->vendor == PCI_VENDOR_ID_INTEL &&
2950 pci->device == PCI_DEVICE_ID_INTEL_440MX)
2951 chip->fix_nocache = 1; /* enable workaround */
2952
2953 if ((err = pci_request_regions(pci, card->shortname)) < 0) {
2954 kfree(chip);
2955 pci_disable_device(pci);
2956 return err;
2957 }
2958
2959 if (device_type == DEVICE_ALI) {
2960 /* ALI5455 has no ac97 region */
2961 chip->bmaddr = pci_iomap(pci, 0, 0);
2962 goto port_inited;
2963 }
2964
2965 if (pci_resource_flags(pci, 2) & IORESOURCE_MEM) /* ICH4 and Nforce */
2966 chip->addr = pci_iomap(pci, 2, 0);
2967 else
2968 chip->addr = pci_iomap(pci, 0, 0);
2969 if (!chip->addr) {
2970 snd_printk(KERN_ERR "AC'97 space ioremap problem\n");
2971 snd_intel8x0_free(chip);
2972 return -EIO;
2973 }
2974 if (pci_resource_flags(pci, 3) & IORESOURCE_MEM) /* ICH4 */
2975 chip->bmaddr = pci_iomap(pci, 3, 0);
2976 else
2977 chip->bmaddr = pci_iomap(pci, 1, 0);
2978 if (!chip->bmaddr) {
2979 snd_printk(KERN_ERR "Controller space ioremap problem\n");
2980 snd_intel8x0_free(chip);
2981 return -EIO;
2982 }
2983
2984 port_inited:
2985 chip->bdbars_count = bdbars[device_type];
2986
2987 /* initialize offsets */
2988 switch (device_type) {
2989 case DEVICE_NFORCE:
2990 tbl = nforce_regs;
2991 break;
2992 case DEVICE_ALI:
2993 tbl = ali_regs;
2994 break;
2995 default:
2996 tbl = intel_regs;
2997 break;
2998 }
2999 for (i = 0; i < chip->bdbars_count; i++) {
3000 ichdev = &chip->ichd[i];
3001 ichdev->ichd = i;
3002 ichdev->reg_offset = tbl[i].offset;
3003 ichdev->int_sta_mask = tbl[i].int_sta_mask;
3004 if (device_type == DEVICE_SIS) {
3005 /* SiS 7012 swaps the registers */
3006 ichdev->roff_sr = ICH_REG_OFF_PICB;
3007 ichdev->roff_picb = ICH_REG_OFF_SR;
3008 } else {
3009 ichdev->roff_sr = ICH_REG_OFF_SR;
3010 ichdev->roff_picb = ICH_REG_OFF_PICB;
3011 }
3012 if (device_type == DEVICE_ALI)
3013 ichdev->ali_slot = (ichdev->reg_offset - 0x40) / 0x10;
3014 /* SIS7012 handles the pcm data in bytes, others are in samples */
3015 ichdev->pos_shift = (device_type == DEVICE_SIS) ? 0 : 1;
3016 }
3017
3018 /* allocate buffer descriptor lists */
3019 /* the start of each lists must be aligned to 8 bytes */
3020 if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(pci),
3021 chip->bdbars_count * sizeof(u32) * ICH_MAX_FRAGS * 2,
3022 &chip->bdbars) < 0) {
3023 snd_intel8x0_free(chip);
3024 snd_printk(KERN_ERR "intel8x0: cannot allocate buffer descriptors\n");
3025 return -ENOMEM;
3026 }
3027 /* tables must be aligned to 8 bytes here, but the kernel pages
3028 are much bigger, so we don't care (on i386) */
3029 /* workaround for 440MX */
3030 if (chip->fix_nocache)
3031 fill_nocache(chip->bdbars.area, chip->bdbars.bytes, 1);
3032 int_sta_masks = 0;
3033 for (i = 0; i < chip->bdbars_count; i++) {
3034 ichdev = &chip->ichd[i];
3035 ichdev->bdbar = ((u32 *)chip->bdbars.area) +
3036 (i * ICH_MAX_FRAGS * 2);
3037 ichdev->bdbar_addr = chip->bdbars.addr +
3038 (i * sizeof(u32) * ICH_MAX_FRAGS * 2);
3039 int_sta_masks |= ichdev->int_sta_mask;
3040 }
3041 chip->int_sta_reg = device_type == DEVICE_ALI ?
3042 ICH_REG_ALI_INTERRUPTSR : ICH_REG_GLOB_STA;
3043 chip->int_sta_mask = int_sta_masks;
3044
3045 pci_set_master(pci);
3046
3047 switch(chip->device_type) {
3048 case DEVICE_INTEL_ICH4:
3049 /* ICH4 can have three codecs */
3050 chip->max_codecs = 3;
3051 chip->codec_bit = ich_codec_bits;
3052 chip->codec_ready_bits = ICH_PRI | ICH_SRI | ICH_TRI;
3053 break;
3054 case DEVICE_SIS:
3055 /* recent SIS7012 can have three codecs */
3056 chip->max_codecs = 3;
3057 chip->codec_bit = sis_codec_bits;
3058 chip->codec_ready_bits = ICH_PRI | ICH_SRI | ICH_SIS_TRI;
3059 break;
3060 default:
3061 /* others up to two codecs */
3062 chip->max_codecs = 2;
3063 chip->codec_bit = ich_codec_bits;
3064 chip->codec_ready_bits = ICH_PRI | ICH_SRI;
3065 break;
3066 }
3067 for (i = 0; i < chip->max_codecs; i++)
3068 chip->codec_isr_bits |= chip->codec_bit[i];
3069
3070 if ((err = snd_intel8x0_chip_init(chip, 1)) < 0) {
3071 snd_intel8x0_free(chip);
3072 return err;
3073 }
3074
3075 /* request irq after initializaing int_sta_mask, etc */
3076 if (request_irq(pci->irq, snd_intel8x0_interrupt,
3077 IRQF_SHARED, card->shortname, chip)) {
3078 snd_printk(KERN_ERR "unable to grab IRQ %d\n", pci->irq);
3079 snd_intel8x0_free(chip);
3080 return -EBUSY;
3081 }
3082 chip->irq = pci->irq;
3083
3084 if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) < 0) {
3085 snd_intel8x0_free(chip);
3086 return err;
3087 }
3088
3089 snd_card_set_dev(card, &pci->dev);
3090
3091 *r_intel8x0 = chip;
3092 return 0;
3093}
3094
3095static struct shortname_table {
3096 unsigned int id;
3097 const char *s;
3098} shortnames[] __devinitdata = {
3099 { PCI_DEVICE_ID_INTEL_82801AA_5, "Intel 82801AA-ICH" },
3100 { PCI_DEVICE_ID_INTEL_82801AB_5, "Intel 82901AB-ICH0" },
3101 { PCI_DEVICE_ID_INTEL_82801BA_4, "Intel 82801BA-ICH2" },
3102 { PCI_DEVICE_ID_INTEL_440MX, "Intel 440MX" },
3103 { PCI_DEVICE_ID_INTEL_82801CA_5, "Intel 82801CA-ICH3" },
3104 { PCI_DEVICE_ID_INTEL_82801DB_5, "Intel 82801DB-ICH4" },
3105 { PCI_DEVICE_ID_INTEL_82801EB_5, "Intel ICH5" },
3106 { PCI_DEVICE_ID_INTEL_ESB_5, "Intel 6300ESB" },
3107 { PCI_DEVICE_ID_INTEL_ICH6_18, "Intel ICH6" },
3108 { PCI_DEVICE_ID_INTEL_ICH7_20, "Intel ICH7" },
3109 { PCI_DEVICE_ID_INTEL_ESB2_14, "Intel ESB2" },
3110 { PCI_DEVICE_ID_SI_7012, "SiS SI7012" },
3111 { PCI_DEVICE_ID_NVIDIA_MCP1_AUDIO, "NVidia nForce" },
3112 { PCI_DEVICE_ID_NVIDIA_MCP2_AUDIO, "NVidia nForce2" },
3113 { PCI_DEVICE_ID_NVIDIA_MCP3_AUDIO, "NVidia nForce3" },
3114 { PCI_DEVICE_ID_NVIDIA_CK8S_AUDIO, "NVidia CK8S" },
3115 { PCI_DEVICE_ID_NVIDIA_CK804_AUDIO, "NVidia CK804" },
3116 { PCI_DEVICE_ID_NVIDIA_CK8_AUDIO, "NVidia CK8" },
3117 { 0x003a, "NVidia MCP04" },
3118 { 0x746d, "AMD AMD8111" },
3119 { 0x7445, "AMD AMD768" },
3120 { 0x5455, "ALi M5455" },
3121 { 0, NULL },
3122};
3123
3124static struct snd_pci_quirk spdif_aclink_defaults[] __devinitdata = {
3125 SND_PCI_QUIRK(0x147b, 0x1c1a, "ASUS KN8", 1),
3126 {0} /* end */
3127};
3128
3129/* look up white/black list for SPDIF over ac-link */
3130static int __devinit check_default_spdif_aclink(struct pci_dev *pci)
3131{
3132#ifndef TARGET_OS2
3133 const struct snd_pci_quirk *w;
3134
3135 w = snd_pci_quirk_lookup(pci, spdif_aclink_defaults);
3136 if (w) {
3137 if (w->value)
3138 snd_printdd(KERN_INFO "intel8x0: Using SPDIF over "
3139 "AC-Link for %s\n", w->name);
3140 else
3141 snd_printdd(KERN_INFO "intel8x0: Using integrated "
3142 "SPDIF DMA for %s\n", w->name);
3143 return w->value;
3144 }
3145#endif
3146 return 0;
3147}
3148
3149static int __devinit snd_intel8x0_probe(struct pci_dev *pci,
3150 const struct pci_device_id *pci_id)
3151{
3152 struct snd_card *card;
3153 struct intel8x0 *chip;
3154 int err;
3155 struct shortname_table *name;
3156
3157 err = snd_card_create(index, id, THIS_MODULE, 0, &card);
3158 if (err < 0)
3159 return err;
3160
3161 if (spdif_aclink < 0)
3162 spdif_aclink = check_default_spdif_aclink(pci);
3163
3164 strcpy(card->driver, "ICH");
3165 if (!spdif_aclink) {
3166 switch (pci_id->driver_data) {
3167 case DEVICE_NFORCE:
3168 strcpy(card->driver, "NFORCE");
3169 break;
3170 case DEVICE_INTEL_ICH4:
3171 strcpy(card->driver, "ICH4");
3172 }
3173 }
3174
3175 strcpy(card->shortname, "Intel ICH");
3176 for (name = shortnames; name->id; name++) {
3177 if (pci->device == name->id) {
3178 strcpy(card->shortname, name->s);
3179 break;
3180 }
3181 }
3182
3183 if (buggy_irq < 0) {
3184 /* some Nforce[2] and ICH boards have problems with IRQ handling.
3185 * Needs to return IRQ_HANDLED for unknown irqs.
3186 */
3187 if (pci_id->driver_data == DEVICE_NFORCE)
3188 buggy_irq = 1;
3189 else
3190 buggy_irq = 0;
3191 }
3192
3193 if ((err = snd_intel8x0_create(card, pci, pci_id->driver_data,
3194 &chip)) < 0) {
3195 snd_card_free(card);
3196 return err;
3197 }
3198 card->private_data = chip;
3199
3200 if ((err = snd_intel8x0_mixer(chip, ac97_clock, ac97_quirk)) < 0) {
3201 snd_card_free(card);
3202 return err;
3203 }
3204 if ((err = snd_intel8x0_pcm(chip)) < 0) {
3205 snd_card_free(card);
3206 return err;
3207 }
3208
3209 snd_intel8x0_proc_init(chip);
3210
3211 snprintf(card->longname, sizeof(card->longname),
3212 "%s with %s at irq %i", card->shortname,
3213 snd_ac97_get_short_name(chip->ac97[0]), chip->irq);
3214
3215 if (ac97_clock == 0 || ac97_clock == 1) {
3216 if (ac97_clock == 0) {
3217 if (intel8x0_in_clock_list(chip) == 0)
3218 intel8x0_measure_ac97_clock(chip);
3219 } else {
3220 intel8x0_measure_ac97_clock(chip);
3221 }
3222 }
3223
3224 if ((err = snd_card_register(card)) < 0) {
3225 snd_card_free(card);
3226 return err;
3227 }
3228 pci_set_drvdata(pci, card);
3229 return 0;
3230}
3231
3232static void __devexit snd_intel8x0_remove(struct pci_dev *pci)
3233{
3234 snd_card_free(pci_get_drvdata(pci));
3235 pci_set_drvdata(pci, NULL);
3236}
3237
3238static struct pci_driver driver = {
3239 .name = "Intel ICH",
3240 .id_table = snd_intel8x0_ids,
3241 .probe = snd_intel8x0_probe,
3242 .remove = __devexit_p(snd_intel8x0_remove),
3243#ifdef CONFIG_PM
3244 .suspend = intel8x0_suspend,
3245 .resume = intel8x0_resume,
3246#endif
3247};
3248
3249
3250static int __init alsa_card_intel8x0_init(void)
3251{
3252 return pci_register_driver(&driver);
3253}
3254
3255static void __exit alsa_card_intel8x0_exit(void)
3256{
3257 pci_unregister_driver(&driver);
3258}
3259
3260module_init(alsa_card_intel8x0_init)
3261module_exit(alsa_card_intel8x0_exit)
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