source: GPL/trunk/alsa-kernel/pci/intel8x0.c@ 424

Last change on this file since 424 was 410, checked in by Paul Smedley, 17 years ago

Update ALSA core to 1.0.19 level
File size: 91.1 KB
Line 
1/*
2 * ALSA driver for Intel ICH (i8x0) chipsets
3 *
4 * Copyright (c) 2000 Jaroslav Kysela <perex@perex.cz>
5 *
6 *
7 * This code also contains alpha support for SiS 735 chipsets provided
8 * by Mike Pieper <mptei@users.sourceforge.net>. We have no datasheet
9 * for SiS735, so the code is not fully functional.
10 *
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
25
26 *
27 */
28
29#include <asm/io.h>
30#include <linux/delay.h>
31#include <linux/interrupt.h>
32#include <linux/init.h>
33#include <linux/pci.h>
34#include <linux/slab.h>
35#include <linux/moduleparam.h>
36#include <sound/core.h>
37#include <sound/pcm.h>
38#include <sound/ac97_codec.h>
39#include <sound/info.h>
40#include <sound/initval.h>
41/* for 440MX workaround */
42#include <asm/pgtable.h>
43#ifndef TARGET_OS2
44#include <asm/cacheflush.h>
45#endif
46
47MODULE_AUTHOR("Jaroslav Kysela <perex@perex.cz>");
48MODULE_DESCRIPTION("Intel 82801AA,82901AB,i810,i820,i830,i840,i845,MX440; SiS 7012; Ali 5455");
49MODULE_LICENSE("GPL");
50MODULE_SUPPORTED_DEVICE("{{Intel,82801AA-ICH},"
51 "{Intel,82901AB-ICH0},"
52 "{Intel,82801BA-ICH2},"
53 "{Intel,82801CA-ICH3},"
54 "{Intel,82801DB-ICH4},"
55 "{Intel,ICH5},"
56 "{Intel,ICH6},"
57 "{Intel,ICH7},"
58 "{Intel,6300ESB},"
59 "{Intel,ESB2},"
60 "{Intel,MX440},"
61 "{SiS,SI7012},"
62 "{NVidia,nForce Audio},"
63 "{NVidia,nForce2 Audio},"
64 "{NVidia,nForce3 Audio},"
65 "{NVidia,MCP04},"
66 "{NVidia,MCP501},"
67 "{NVidia,CK804},"
68 "{NVidia,CK8},"
69 "{NVidia,CK8S},"
70 "{AMD,AMD768},"
71 "{AMD,AMD8111},"
72 "{ALI,M5455}}");
73
74static int index = SNDRV_DEFAULT_IDX1; /* Index 0-MAX */
75static char *id = SNDRV_DEFAULT_STR1; /* ID for this card */
76static int ac97_clock;
77static char *ac97_quirk;
78static int buggy_semaphore;
79static int buggy_irq = -1; /* auto-check */
80static int xbox;
81static int spdif_aclink = -1;
82
83module_param(index, int, 0444);
84MODULE_PARM_DESC(index, "Index value for Intel i8x0 soundcard.");
85module_param(id, charp, 0444);
86MODULE_PARM_DESC(id, "ID string for Intel i8x0 soundcard.");
87module_param(ac97_clock, int, 0444);
88MODULE_PARM_DESC(ac97_clock, "AC'97 codec clock (0 = whitelist + auto-detect, 1 = force autodetect).");
89module_param(ac97_quirk, charp, 0444);
90MODULE_PARM_DESC(ac97_quirk, "AC'97 workaround for strange hardware.");
91module_param(buggy_semaphore, bool, 0444);
92MODULE_PARM_DESC(buggy_semaphore, "Enable workaround for hardwares with problematic codec semaphores.");
93module_param(buggy_irq, bool, 0444);
94MODULE_PARM_DESC(buggy_irq, "Enable workaround for buggy interrupts on some motherboards.");
95module_param(xbox, bool, 0444);
96MODULE_PARM_DESC(xbox, "Set to 1 for Xbox, if you have problems with the AC'97 codec detection.");
97module_param(spdif_aclink, int, 0444);
98MODULE_PARM_DESC(spdif_aclink, "S/PDIF over AC-link.");
99
100/* just for backward compatibility */
101static int enable;
102module_param(enable, bool, 0444);
103static int joystick;
104module_param(joystick, int, 0444);
105
106/*
107 * Direct registers
108 */
109enum { DEVICE_INTEL, DEVICE_INTEL_ICH4, DEVICE_SIS, DEVICE_ALI, DEVICE_NFORCE };
110
111#define ICHREG(x) ICH_REG_##x
112
113#define DEFINE_REGSET(name,base) \
114enum { \
115 ICH_REG_##name##_BDBAR = base + 0x0, /* dword - buffer descriptor list base address */ \
116 ICH_REG_##name##_CIV = base + 0x04, /* byte - current index value */ \
117 ICH_REG_##name##_LVI = base + 0x05, /* byte - last valid index */ \
118 ICH_REG_##name##_SR = base + 0x06, /* byte - status register */ \
119 ICH_REG_##name##_PICB = base + 0x08, /* word - position in current buffer */ \
120 ICH_REG_##name##_PIV = base + 0x0a, /* byte - prefetched index value */ \
121 ICH_REG_##name##_CR = base + 0x0b, /* byte - control register */ \
122};
123
124/* busmaster blocks */
125DEFINE_REGSET(OFF, 0); /* offset */
126DEFINE_REGSET(PI, 0x00); /* PCM in */
127DEFINE_REGSET(PO, 0x10); /* PCM out */
128DEFINE_REGSET(MC, 0x20); /* Mic in */
129
130/* ICH4 busmaster blocks */
131DEFINE_REGSET(MC2, 0x40); /* Mic in 2 */
132DEFINE_REGSET(PI2, 0x50); /* PCM in 2 */
133DEFINE_REGSET(SP, 0x60); /* SPDIF out */
134
135/* values for each busmaster block */
136
137/* LVI */
138#define ICH_REG_LVI_MASK 0x1f
139
140/* SR */
141#define ICH_FIFOE 0x10 /* FIFO error */
142#define ICH_BCIS 0x08 /* buffer completion interrupt status */
143#define ICH_LVBCI 0x04 /* last valid buffer completion interrupt */
144#define ICH_CELV 0x02 /* current equals last valid */
145#define ICH_DCH 0x01 /* DMA controller halted */
146
147/* PIV */
148#define ICH_REG_PIV_MASK 0x1f /* mask */
149
150/* CR */
151#define ICH_IOCE 0x10 /* interrupt on completion enable */
152#define ICH_FEIE 0x08 /* fifo error interrupt enable */
153#define ICH_LVBIE 0x04 /* last valid buffer interrupt enable */
154#define ICH_RESETREGS 0x02 /* reset busmaster registers */
155#define ICH_STARTBM 0x01 /* start busmaster operation */
156
157
158/* global block */
159#define ICH_REG_GLOB_CNT 0x2c /* dword - global control */
160#define ICH_PCM_SPDIF_MASK 0xc0000000 /* s/pdif pcm slot mask (ICH4) */
161#define ICH_PCM_SPDIF_NONE 0x00000000 /* reserved - undefined */
162#define ICH_PCM_SPDIF_78 0x40000000 /* s/pdif pcm on slots 7&8 */
163#define ICH_PCM_SPDIF_69 0x80000000 /* s/pdif pcm on slots 6&9 */
164#define ICH_PCM_SPDIF_1011 0xc0000000 /* s/pdif pcm on slots 10&11 */
165#define ICH_PCM_20BIT 0x00400000 /* 20-bit samples (ICH4) */
166#define ICH_PCM_246_MASK 0x00300000 /* chan mask (not all chips) */
167#define ICH_PCM_8 0x00300000 /* 8 channels (not all chips) */
168#define ICH_PCM_6 0x00200000 /* 6 channels (not all chips) */
169#define ICH_PCM_4 0x00100000 /* 4 channels (not all chips) */
170#define ICH_PCM_2 0x00000000 /* 2 channels (stereo) */
171#define ICH_SIS_PCM_246_MASK 0x000000c0 /* 6 channels (SIS7012) */
172#define ICH_SIS_PCM_6 0x00000080 /* 6 channels (SIS7012) */
173#define ICH_SIS_PCM_4 0x00000040 /* 4 channels (SIS7012) */
174#define ICH_SIS_PCM_2 0x00000000 /* 2 channels (SIS7012) */
175#define ICH_TRIE 0x00000040 /* tertiary resume interrupt enable */
176#define ICH_SRIE 0x00000020 /* secondary resume interrupt enable */
177#define ICH_PRIE 0x00000010 /* primary resume interrupt enable */
178#define ICH_ACLINK 0x00000008 /* AClink shut off */
179#define ICH_AC97WARM 0x00000004 /* AC'97 warm reset */
180#define ICH_AC97COLD 0x00000002 /* AC'97 cold reset */
181#define ICH_GIE 0x00000001 /* GPI interrupt enable */
182#define ICH_REG_GLOB_STA 0x30 /* dword - global status */
183#define ICH_TRI 0x20000000 /* ICH4: tertiary (AC_SDIN2) resume interrupt */
184#define ICH_TCR 0x10000000 /* ICH4: tertiary (AC_SDIN2) codec ready */
185#define ICH_BCS 0x08000000 /* ICH4: bit clock stopped */
186#define ICH_SPINT 0x04000000 /* ICH4: S/PDIF interrupt */
187#define ICH_P2INT 0x02000000 /* ICH4: PCM2-In interrupt */
188#define ICH_M2INT 0x01000000 /* ICH4: Mic2-In interrupt */
189#define ICH_SAMPLE_CAP 0x00c00000 /* ICH4: sample capability bits (RO) */
190#define ICH_SAMPLE_16_20 0x00400000 /* ICH4: 16- and 20-bit samples */
191#define ICH_MULTICHAN_CAP 0x00300000 /* ICH4: multi-channel capability bits (RO) */
192#define ICH_SIS_TRI 0x00080000 /* SIS: tertiary resume irq */
193#define ICH_SIS_TCR 0x00040000 /* SIS: tertiary codec ready */
194#define ICH_MD3 0x00020000 /* modem power down semaphore */
195#define ICH_AD3 0x00010000 /* audio power down semaphore */
196#define ICH_RCS 0x00008000 /* read completion status */
197#define ICH_BIT3 0x00004000 /* bit 3 slot 12 */
198#define ICH_BIT2 0x00002000 /* bit 2 slot 12 */
199#define ICH_BIT1 0x00001000 /* bit 1 slot 12 */
200#define ICH_SRI 0x00000800 /* secondary (AC_SDIN1) resume interrupt */
201#define ICH_PRI 0x00000400 /* primary (AC_SDIN0) resume interrupt */
202#define ICH_SCR 0x00000200 /* secondary (AC_SDIN1) codec ready */
203#define ICH_PCR 0x00000100 /* primary (AC_SDIN0) codec ready */
204#define ICH_MCINT 0x00000080 /* MIC capture interrupt */
205#define ICH_POINT 0x00000040 /* playback interrupt */
206#define ICH_PIINT 0x00000020 /* capture interrupt */
207#define ICH_NVSPINT 0x00000010 /* nforce spdif interrupt */
208#define ICH_MOINT 0x00000004 /* modem playback interrupt */
209#define ICH_MIINT 0x00000002 /* modem capture interrupt */
210#define ICH_GSCI 0x00000001 /* GPI status change interrupt */
211#define ICH_REG_ACC_SEMA 0x34 /* byte - codec write semaphore */
212#define ICH_CAS 0x01 /* codec access semaphore */
213#define ICH_REG_SDM 0x80
214#define ICH_DI2L_MASK 0x000000c0 /* PCM In 2, Mic In 2 data in line */
215#define ICH_DI2L_SHIFT 6
216#define ICH_DI1L_MASK 0x00000030 /* PCM In 1, Mic In 1 data in line */
217#define ICH_DI1L_SHIFT 4
218#define ICH_SE 0x00000008 /* steer enable */
219#define ICH_LDI_MASK 0x00000003 /* last codec read data input */
220
221#define ICH_MAX_FRAGS 32 /* max hw frags */
222
223
224/*
225 * registers for Ali5455
226 */
227
228/* ALi 5455 busmaster blocks */
229DEFINE_REGSET(AL_PI, 0x40); /* ALi PCM in */
230DEFINE_REGSET(AL_PO, 0x50); /* Ali PCM out */
231DEFINE_REGSET(AL_MC, 0x60); /* Ali Mic in */
232DEFINE_REGSET(AL_CDC_SPO, 0x70); /* Ali Codec SPDIF out */
233DEFINE_REGSET(AL_CENTER, 0x80); /* Ali center out */
234DEFINE_REGSET(AL_LFE, 0x90); /* Ali center out */
235DEFINE_REGSET(AL_CLR_SPI, 0xa0); /* Ali Controller SPDIF in */
236DEFINE_REGSET(AL_CLR_SPO, 0xb0); /* Ali Controller SPDIF out */
237DEFINE_REGSET(AL_I2S, 0xc0); /* Ali I2S in */
238DEFINE_REGSET(AL_PI2, 0xd0); /* Ali PCM2 in */
239DEFINE_REGSET(AL_MC2, 0xe0); /* Ali Mic2 in */
240
241enum {
242 ICH_REG_ALI_SCR = 0x00, /* System Control Register */
243 ICH_REG_ALI_SSR = 0x04, /* System Status Register */
244 ICH_REG_ALI_DMACR = 0x08, /* DMA Control Register */
245 ICH_REG_ALI_FIFOCR1 = 0x0c, /* FIFO Control Register 1 */
246 ICH_REG_ALI_INTERFACECR = 0x10, /* Interface Control Register */
247 ICH_REG_ALI_INTERRUPTCR = 0x14, /* Interrupt control Register */
248 ICH_REG_ALI_INTERRUPTSR = 0x18, /* Interrupt Status Register */
249 ICH_REG_ALI_FIFOCR2 = 0x1c, /* FIFO Control Register 2 */
250 ICH_REG_ALI_CPR = 0x20, /* Command Port Register */
251 ICH_REG_ALI_CPR_ADDR = 0x22, /* ac97 addr write */
252 ICH_REG_ALI_SPR = 0x24, /* Status Port Register */
253 ICH_REG_ALI_SPR_ADDR = 0x26, /* ac97 addr read */
254 ICH_REG_ALI_FIFOCR3 = 0x2c, /* FIFO Control Register 3 */
255 ICH_REG_ALI_TTSR = 0x30, /* Transmit Tag Slot Register */
256 ICH_REG_ALI_RTSR = 0x34, /* Receive Tag Slot Register */
257 ICH_REG_ALI_CSPSR = 0x38, /* Command/Status Port Status Register */
258 ICH_REG_ALI_CAS = 0x3c, /* Codec Write Semaphore Register */
259 ICH_REG_ALI_HWVOL = 0xf0, /* hardware volume control/status */
260 ICH_REG_ALI_I2SCR = 0xf4, /* I2S control/status */
261 ICH_REG_ALI_SPDIFCSR = 0xf8, /* spdif channel status register */
262 ICH_REG_ALI_SPDIFICS = 0xfc, /* spdif interface control/status */
263};
264
265#define ALI_CAS_SEM_BUSY 0x80000000
266#define ALI_CPR_ADDR_SECONDARY 0x100
267#define ALI_CPR_ADDR_READ 0x80
268#define ALI_CSPSR_CODEC_READY 0x08
269#define ALI_CSPSR_READ_OK 0x02
270#define ALI_CSPSR_WRITE_OK 0x01
271
272/* interrupts for the whole chip by interrupt status register finish */
273
274#define ALI_INT_MICIN2 (1<<26)
275#define ALI_INT_PCMIN2 (1<<25)
276#define ALI_INT_I2SIN (1<<24)
277#define ALI_INT_SPDIFOUT (1<<23) /* controller spdif out INTERRUPT */
278#define ALI_INT_SPDIFIN (1<<22)
279#define ALI_INT_LFEOUT (1<<21)
280#define ALI_INT_CENTEROUT (1<<20)
281#define ALI_INT_CODECSPDIFOUT (1<<19)
282#define ALI_INT_MICIN (1<<18)
283#define ALI_INT_PCMOUT (1<<17)
284#define ALI_INT_PCMIN (1<<16)
285#define ALI_INT_CPRAIS (1<<7) /* command port available */
286#define ALI_INT_SPRAIS (1<<5) /* status port available */
287#define ALI_INT_GPIO (1<<1)
288#define ALI_INT_MASK (ALI_INT_SPDIFOUT|ALI_INT_CODECSPDIFOUT|\
289 ALI_INT_MICIN|ALI_INT_PCMOUT|ALI_INT_PCMIN)
290
291#define ICH_ALI_SC_RESET (1<<31) /* master reset */
292#define ICH_ALI_SC_AC97_DBL (1<<30)
293#define ICH_ALI_SC_CODEC_SPDF (3<<20) /* 1=7/8, 2=6/9, 3=10/11 */
294#define ICH_ALI_SC_IN_BITS (3<<18)
295#define ICH_ALI_SC_OUT_BITS (3<<16)
296#define ICH_ALI_SC_6CH_CFG (3<<14)
297#define ICH_ALI_SC_PCM_4 (1<<8)
298#define ICH_ALI_SC_PCM_6 (2<<8)
299#define ICH_ALI_SC_PCM_246_MASK (3<<8)
300
301#define ICH_ALI_SS_SEC_ID (3<<5)
302#define ICH_ALI_SS_PRI_ID (3<<3)
303
304#define ICH_ALI_IF_AC97SP (1<<21)
305#define ICH_ALI_IF_MC (1<<20)
306#define ICH_ALI_IF_PI (1<<19)
307#define ICH_ALI_IF_MC2 (1<<18)
308#define ICH_ALI_IF_PI2 (1<<17)
309#define ICH_ALI_IF_LINE_SRC (1<<15) /* 0/1 = slot 3/6 */
310#define ICH_ALI_IF_MIC_SRC (1<<14) /* 0/1 = slot 3/6 */
311#define ICH_ALI_IF_SPDF_SRC (3<<12) /* 00 = PCM, 01 = AC97-in, 10 = spdif-in, 11 = i2s */
312#define ICH_ALI_IF_AC97_OUT (3<<8) /* 00 = PCM, 10 = spdif-in, 11 = i2s */
313#define ICH_ALI_IF_PO_SPDF (1<<3)
314#define ICH_ALI_IF_PO (1<<1)
315
316/*
317 *
318 */
319
320enum {
321 ICHD_PCMIN,
322 ICHD_PCMOUT,
323 ICHD_MIC,
324 ICHD_MIC2,
325 ICHD_PCM2IN,
326 ICHD_SPBAR,
327 ICHD_LAST = ICHD_SPBAR
328};
329enum {
330 NVD_PCMIN,
331 NVD_PCMOUT,
332 NVD_MIC,
333 NVD_SPBAR,
334 NVD_LAST = NVD_SPBAR
335};
336enum {
337 ALID_PCMIN,
338 ALID_PCMOUT,
339 ALID_MIC,
340 ALID_AC97SPDIFOUT,
341 ALID_SPDIFIN,
342 ALID_SPDIFOUT,
343 ALID_LAST = ALID_SPDIFOUT
344};
345
346#define get_ichdev(substream) (substream->runtime->private_data)
347
348struct ichdev {
349 unsigned int ichd; /* ich device number */
350 unsigned long reg_offset; /* offset to bmaddr */
351 u32 *bdbar; /* CPU address (32bit) */
352 unsigned int bdbar_addr; /* PCI bus address (32bit) */
353 struct snd_pcm_substream *substream;
354 unsigned int physbuf; /* physical address (32bit) */
355 unsigned int size;
356 unsigned int fragsize;
357 unsigned int fragsize1;
358 unsigned int position;
359 unsigned int pos_shift;
360 int frags;
361 int lvi;
362 int lvi_frag;
363 int civ;
364 int ack;
365 int ack_reload;
366 unsigned int ack_bit;
367 unsigned int roff_sr;
368 unsigned int roff_picb;
369 unsigned int int_sta_mask; /* interrupt status mask */
370 unsigned int ali_slot; /* ALI DMA slot */
371 struct ac97_pcm *pcm;
372 int pcm_open_flag;
373 unsigned int page_attr_changed: 1;
374 unsigned int suspended: 1;
375};
376
377struct intel8x0 {
378 unsigned int device_type;
379
380 int irq;
381
382 void __iomem *addr;
383 void __iomem *bmaddr;
384
385 struct pci_dev *pci;
386 struct snd_card *card;
387
388 int pcm_devs;
389 struct snd_pcm *pcm[6];
390 struct ichdev ichd[6];
391
392 unsigned multi4: 1,
393 multi6: 1,
394 multi8 :1,
395 dra: 1,
396 smp20bit: 1;
397 unsigned in_ac97_init: 1,
398 in_sdin_init: 1;
399 unsigned in_measurement: 1; /* during ac97 clock measurement */
400 unsigned fix_nocache: 1; /* workaround for 440MX */
401 unsigned buggy_irq: 1; /* workaround for buggy mobos */
402 unsigned xbox: 1; /* workaround for Xbox AC'97 detection */
403 unsigned buggy_semaphore: 1; /* workaround for buggy codec semaphore */
404
405 int spdif_idx; /* SPDIF BAR index; *_SPBAR or -1 if use PCMOUT */
406 unsigned int sdm_saved; /* SDM reg value */
407
408 struct snd_ac97_bus *ac97_bus;
409 struct snd_ac97 *ac97[3];
410 unsigned int ac97_sdin[3];
411 unsigned int max_codecs, ncodecs;
412 unsigned int *codec_bit;
413 unsigned int codec_isr_bits;
414 unsigned int codec_ready_bits;
415
416 spinlock_t reg_lock;
417
418 u32 bdbars_count;
419 struct snd_dma_buffer bdbars;
420 u32 int_sta_reg; /* interrupt status register */
421 u32 int_sta_mask; /* interrupt status mask */
422};
423
424static struct pci_device_id snd_intel8x0_ids[] = {
425 { 0x8086, 0x2415, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* 82801AA */
426 { 0x8086, 0x2425, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* 82901AB */
427 { 0x8086, 0x2445, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* 82801BA */
428 { 0x8086, 0x2485, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* ICH3 */
429 { 0x8086, 0x24c5, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL_ICH4 }, /* ICH4 */
430 { 0x8086, 0x24d5, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL_ICH4 }, /* ICH5 */
431 { 0x8086, 0x25a6, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL_ICH4 }, /* ESB */
432 { 0x8086, 0x266e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL_ICH4 }, /* ICH6 */
433 { 0x8086, 0x27de, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL_ICH4 }, /* ICH7 */
434 { 0x8086, 0x2698, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL_ICH4 }, /* ESB2 */
435 { 0x8086, 0x7195, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* 440MX */
436 { 0x1039, 0x7012, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_SIS }, /* SI7012 */
437 { 0x10de, 0x01b1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE }, /* NFORCE */
438 { 0x10de, 0x003a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE }, /* MCP04 */
439 { 0x10de, 0x006a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE }, /* NFORCE2 */
440 { 0x10de, 0x0059, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE }, /* CK804 */
441 { 0x10de, 0x008a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE }, /* CK8 */
442 { 0x10de, 0x00da, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE }, /* NFORCE3 */
443 { 0x10de, 0x00ea, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE }, /* CK8S */
444 { 0x10de, 0x026b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE }, /* MCP51 */
445 { 0x1022, 0x746d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* AMD8111 */
446 { 0x1022, 0x7445, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* AMD768 */
447 { 0x10b9, 0x5455, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_ALI }, /* Ali5455 */
448 { 0, }
449};
450
451MODULE_DEVICE_TABLE(pci, snd_intel8x0_ids);
452
453/*
454 * Lowlevel I/O - busmaster
455 */
456
457static inline u8 igetbyte(struct intel8x0 *chip, u32 offset)
458{
459 return ioread8(chip->bmaddr + offset);
460}
461
462static inline u16 igetword(struct intel8x0 *chip, u32 offset)
463{
464 return ioread16(chip->bmaddr + offset);
465}
466
467static inline u32 igetdword(struct intel8x0 *chip, u32 offset)
468{
469 return ioread32(chip->bmaddr + offset);
470}
471
472static inline void iputbyte(struct intel8x0 *chip, u32 offset, u8 val)
473{
474 iowrite8(val, chip->bmaddr + offset);
475}
476
477static inline void iputword(struct intel8x0 *chip, u32 offset, u16 val)
478{
479 iowrite16(val, chip->bmaddr + offset);
480}
481
482static inline void iputdword(struct intel8x0 *chip, u32 offset, u32 val)
483{
484 iowrite32(val, chip->bmaddr + offset);
485}
486
487/*
488 * Lowlevel I/O - AC'97 registers
489 */
490
491static inline u16 iagetword(struct intel8x0 *chip, u32 offset)
492{
493 return ioread16(chip->addr + offset);
494}
495
496static inline void iaputword(struct intel8x0 *chip, u32 offset, u16 val)
497{
498 iowrite16(val, chip->addr + offset);
499}
500
501/*
502 * Basic I/O
503 */
504
505/*
506 * access to AC97 codec via normal i/o (for ICH and SIS7012)
507 */
508
509static int snd_intel8x0_codec_semaphore(struct intel8x0 *chip, unsigned int codec)
510{
511 int time;
512
513 if (codec > 2)
514 return -EIO;
515 if (chip->in_sdin_init) {
516 /* we don't know the ready bit assignment at the moment */
517 /* so we check any */
518 codec = chip->codec_isr_bits;
519 } else {
520 codec = chip->codec_bit[chip->ac97_sdin[codec]];
521 }
522
523 /* codec ready ? */
524 if ((igetdword(chip, ICHREG(GLOB_STA)) & codec) == 0)
525 return -EIO;
526
527 if (chip->buggy_semaphore)
528 return 0; /* just ignore ... */
529
530 /* Anyone holding a semaphore for 1 msec should be shot... */
531 time = 100;
532 do {
533 if (!(igetbyte(chip, ICHREG(ACC_SEMA)) & ICH_CAS))
534 return 0;
535 udelay(10);
536 } while (time--);
537
538 /* access to some forbidden (non existant) ac97 registers will not
539 * reset the semaphore. So even if you don't get the semaphore, still
540 * continue the access. We don't need the semaphore anyway. */
541 snd_printk(KERN_ERR "codec_semaphore: semaphore is not ready [0x%x][0x%x]\n",
542 igetbyte(chip, ICHREG(ACC_SEMA)), igetdword(chip, ICHREG(GLOB_STA)));
543 iagetword(chip, 0); /* clear semaphore flag */
544 /* I don't care about the semaphore */
545 return -EBUSY;
546}
547
548static void snd_intel8x0_codec_write(struct snd_ac97 *ac97,
549 unsigned short reg,
550 unsigned short val)
551{
552 struct intel8x0 *chip = ac97->private_data;
553
554 if (snd_intel8x0_codec_semaphore(chip, ac97->num) < 0) {
555 if (! chip->in_ac97_init)
556 snd_printk(KERN_ERR "codec_write %d: semaphore is not ready for register 0x%x\n", ac97->num, reg);
557 }
558 iaputword(chip, reg + ac97->num * 0x80, val);
559}
560
561static unsigned short snd_intel8x0_codec_read(struct snd_ac97 *ac97,
562 unsigned short reg)
563{
564 struct intel8x0 *chip = ac97->private_data;
565 unsigned short res;
566 unsigned int tmp;
567
568 if (snd_intel8x0_codec_semaphore(chip, ac97->num) < 0) {
569 if (! chip->in_ac97_init)
570 snd_printk(KERN_ERR "codec_read %d: semaphore is not ready for register 0x%x\n", ac97->num, reg);
571 res = 0xffff;
572 } else {
573 res = iagetword(chip, reg + ac97->num * 0x80);
574 if ((tmp = igetdword(chip, ICHREG(GLOB_STA))) & ICH_RCS) {
575 /* reset RCS and preserve other R/WC bits */
576 iputdword(chip, ICHREG(GLOB_STA), tmp &
577 ~(chip->codec_ready_bits | ICH_GSCI));
578 if (! chip->in_ac97_init)
579 snd_printk(KERN_ERR "codec_read %d: read timeout for register 0x%x\n", ac97->num, reg);
580 res = 0xffff;
581 }
582 }
583 return res;
584}
585
586static void __devinit snd_intel8x0_codec_read_test(struct intel8x0 *chip,
587 unsigned int codec)
588{
589 unsigned int tmp;
590
591 if (snd_intel8x0_codec_semaphore(chip, codec) >= 0) {
592 iagetword(chip, codec * 0x80);
593 if ((tmp = igetdword(chip, ICHREG(GLOB_STA))) & ICH_RCS) {
594 /* reset RCS and preserve other R/WC bits */
595 iputdword(chip, ICHREG(GLOB_STA), tmp &
596 ~(chip->codec_ready_bits | ICH_GSCI));
597 }
598 }
599}
600
601/*
602 * access to AC97 for Ali5455
603 */
604static int snd_intel8x0_ali_codec_ready(struct intel8x0 *chip, int mask)
605{
606 int count = 0;
607 for (count = 0; count < 0x7f; count++) {
608 int val = igetbyte(chip, ICHREG(ALI_CSPSR));
609 if (val & mask)
610 return 0;
611 }
612 if (! chip->in_ac97_init)
613 snd_printd(KERN_WARNING "intel8x0: AC97 codec ready timeout.\n");
614 return -EBUSY;
615}
616
617static int snd_intel8x0_ali_codec_semaphore(struct intel8x0 *chip)
618{
619 int time = 100;
620 if (chip->buggy_semaphore)
621 return 0; /* just ignore ... */
622 while (time-- && (igetdword(chip, ICHREG(ALI_CAS)) & ALI_CAS_SEM_BUSY))
623 udelay(1);
624 if (! time && ! chip->in_ac97_init)
625 snd_printk(KERN_WARNING "ali_codec_semaphore timeout\n");
626 return snd_intel8x0_ali_codec_ready(chip, ALI_CSPSR_CODEC_READY);
627}
628
629static unsigned short snd_intel8x0_ali_codec_read(struct snd_ac97 *ac97, unsigned short reg)
630{
631 struct intel8x0 *chip = ac97->private_data;
632 unsigned short data = 0xffff;
633
634 if (snd_intel8x0_ali_codec_semaphore(chip))
635 goto __err;
636 reg |= ALI_CPR_ADDR_READ;
637 if (ac97->num)
638 reg |= ALI_CPR_ADDR_SECONDARY;
639 iputword(chip, ICHREG(ALI_CPR_ADDR), reg);
640 if (snd_intel8x0_ali_codec_ready(chip, ALI_CSPSR_READ_OK))
641 goto __err;
642 data = igetword(chip, ICHREG(ALI_SPR));
643 __err:
644 return data;
645}
646
647static void snd_intel8x0_ali_codec_write(struct snd_ac97 *ac97, unsigned short reg,
648 unsigned short val)
649{
650 struct intel8x0 *chip = ac97->private_data;
651
652 if (snd_intel8x0_ali_codec_semaphore(chip))
653 return;
654 iputword(chip, ICHREG(ALI_CPR), val);
655 if (ac97->num)
656 reg |= ALI_CPR_ADDR_SECONDARY;
657 iputword(chip, ICHREG(ALI_CPR_ADDR), reg);
658 snd_intel8x0_ali_codec_ready(chip, ALI_CSPSR_WRITE_OK);
659}
660
661
662/*
663 * DMA I/O
664 */
665static void snd_intel8x0_setup_periods(struct intel8x0 *chip, struct ichdev *ichdev)
666{
667 int idx;
668 u32 *bdbar = ichdev->bdbar;
669 unsigned long port = ichdev->reg_offset;
670
671 iputdword(chip, port + ICH_REG_OFF_BDBAR, ichdev->bdbar_addr);
672 if (ichdev->size == ichdev->fragsize) {
673 ichdev->ack_reload = ichdev->ack = 2;
674 ichdev->fragsize1 = ichdev->fragsize >> 1;
675 for (idx = 0; idx < (ICH_REG_LVI_MASK + 1) * 2; idx += 4) {
676 bdbar[idx + 0] = cpu_to_le32(ichdev->physbuf);
677 bdbar[idx + 1] = cpu_to_le32(0x80000000 | /* interrupt on completion */
678 ichdev->fragsize1 >> ichdev->pos_shift);
679 bdbar[idx + 2] = cpu_to_le32(ichdev->physbuf + (ichdev->size >> 1));
680 bdbar[idx + 3] = cpu_to_le32(0x80000000 | /* interrupt on completion */
681 ichdev->fragsize1 >> ichdev->pos_shift);
682 }
683 ichdev->frags = 2;
684 } else {
685 ichdev->ack_reload = ichdev->ack = 1;
686 ichdev->fragsize1 = ichdev->fragsize;
687 for (idx = 0; idx < (ICH_REG_LVI_MASK + 1) * 2; idx += 2) {
688 bdbar[idx + 0] = cpu_to_le32(ichdev->physbuf +
689 (((idx >> 1) * ichdev->fragsize) %
690 ichdev->size));
691 bdbar[idx + 1] = cpu_to_le32(0x80000000 | /* interrupt on completion */
692 ichdev->fragsize >> ichdev->pos_shift);
693#if 0
694 printk("bdbar[%i] = 0x%x [0x%x]\n",
695 idx + 0, bdbar[idx + 0], bdbar[idx + 1]);
696#endif
697 }
698 ichdev->frags = ichdev->size / ichdev->fragsize;
699 }
700 iputbyte(chip, port + ICH_REG_OFF_LVI, ichdev->lvi = ICH_REG_LVI_MASK);
701 ichdev->civ = 0;
702 iputbyte(chip, port + ICH_REG_OFF_CIV, 0);
703 ichdev->lvi_frag = ICH_REG_LVI_MASK % ichdev->frags;
704 ichdev->position = 0;
705#if 0
706 printk("lvi_frag = %i, frags = %i, period_size = 0x%x, period_size1 = 0x%x\n",
707 ichdev->lvi_frag, ichdev->frags, ichdev->fragsize, ichdev->fragsize1);
708#endif
709 /* clear interrupts */
710 iputbyte(chip, port + ichdev->roff_sr, ICH_FIFOE | ICH_BCIS | ICH_LVBCI);
711}
712
713#ifdef __i386__
714/*
715 * Intel 82443MX running a 100MHz processor system bus has a hardware bug,
716 * which aborts PCI busmaster for audio transfer. A workaround is to set
717 * the pages as non-cached. For details, see the errata in
718 * http://www.intel.com/design/chipsets/specupdt/245051.htm
719 */
720static void fill_nocache(void *buf, int size, int nocache)
721{
722 size = (size + PAGE_SIZE - 1) >> PAGE_SHIFT;
723 if (nocache)
724 set_pages_uc(virt_to_page(buf), size);
725 else
726 set_pages_wb(virt_to_page(buf), size);
727}
728#else
729#define fill_nocache(buf, size, nocache) do { ; } while (0)
730#endif
731
732/*
733 * Interrupt handler
734 */
735
736static inline void snd_intel8x0_update(struct intel8x0 *chip, struct ichdev *ichdev)
737{
738 unsigned long port = ichdev->reg_offset;
739 unsigned long flags;
740 int status, civ, i, step;
741 int ack = 0;
742
743 spin_lock_irqsave(&chip->reg_lock, flags);
744 status = igetbyte(chip, port + ichdev->roff_sr);
745 civ = igetbyte(chip, port + ICH_REG_OFF_CIV);
746 if (!(status & ICH_BCIS)) {
747 step = 0;
748 } else if (civ == ichdev->civ) {
749 // snd_printd("civ same %d\n", civ);
750 step = 1;
751 ichdev->civ++;
752 ichdev->civ &= ICH_REG_LVI_MASK;
753 } else {
754 step = civ - ichdev->civ;
755 if (step < 0)
756 step += ICH_REG_LVI_MASK + 1;
757 // if (step != 1)
758 // snd_printd("step = %d, %d -> %d\n", step, ichdev->civ, civ);
759 ichdev->civ = civ;
760 }
761
762 ichdev->position += step * ichdev->fragsize1;
763 if (! chip->in_measurement)
764 ichdev->position %= ichdev->size;
765 ichdev->lvi += step;
766 ichdev->lvi &= ICH_REG_LVI_MASK;
767 iputbyte(chip, port + ICH_REG_OFF_LVI, ichdev->lvi);
768 for (i = 0; i < step; i++) {
769 ichdev->lvi_frag++;
770 ichdev->lvi_frag %= ichdev->frags;
771 ichdev->bdbar[ichdev->lvi * 2] = cpu_to_le32(ichdev->physbuf + ichdev->lvi_frag * ichdev->fragsize1);
772#if 0
773 printk("new: bdbar[%i] = 0x%x [0x%x], prefetch = %i, all = 0x%x, 0x%x\n",
774 ichdev->lvi * 2, ichdev->bdbar[ichdev->lvi * 2],
775 ichdev->bdbar[ichdev->lvi * 2 + 1], inb(ICH_REG_OFF_PIV + port),
776 inl(port + 4), inb(port + ICH_REG_OFF_CR));
777#endif
778 if (--ichdev->ack == 0) {
779 ichdev->ack = ichdev->ack_reload;
780 ack = 1;
781 }
782 }
783 spin_unlock_irqrestore(&chip->reg_lock, flags);
784 if (ack && ichdev->substream) {
785 snd_pcm_period_elapsed(ichdev->substream);
786 }
787 iputbyte(chip, port + ichdev->roff_sr,
788 status & (ICH_FIFOE | ICH_BCIS | ICH_LVBCI));
789}
790
791static irqreturn_t snd_intel8x0_interrupt(int irq, void *dev_id)
792{
793 struct intel8x0 *chip = dev_id;
794 struct ichdev *ichdev;
795 unsigned int status;
796 unsigned int i;
797
798 status = igetdword(chip, chip->int_sta_reg);
799 if (status == 0xffffffff) /* we are not yet resumed */
800 return IRQ_NONE;
801
802 if ((status & chip->int_sta_mask) == 0) {
803 if (status) {
804 /* ack */
805 iputdword(chip, chip->int_sta_reg, status);
806 if (! chip->buggy_irq)
807 status = 0;
808 }
809 return IRQ_RETVAL(status);
810 }
811
812 for (i = 0; i < chip->bdbars_count; i++) {
813 ichdev = &chip->ichd[i];
814 if (status & ichdev->int_sta_mask)
815 snd_intel8x0_update(chip, ichdev);
816 }
817
818 /* ack them */
819 iputdword(chip, chip->int_sta_reg, status & chip->int_sta_mask);
820
821 return IRQ_HANDLED;
822}
823
824/*
825 * PCM part
826 */
827
828static int snd_intel8x0_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
829{
830 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
831 struct ichdev *ichdev = get_ichdev(substream);
832 unsigned char val = 0;
833 unsigned long port = ichdev->reg_offset;
834
835 switch (cmd) {
836 case SNDRV_PCM_TRIGGER_RESUME:
837 ichdev->suspended = 0;
838 /* fallthru */
839 case SNDRV_PCM_TRIGGER_START:
840 val = ICH_IOCE | ICH_STARTBM;
841 break;
842 case SNDRV_PCM_TRIGGER_SUSPEND:
843 ichdev->suspended = 1;
844 /* fallthru */
845 case SNDRV_PCM_TRIGGER_STOP:
846 val = 0;
847 break;
848 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
849 val = ICH_IOCE;
850 break;
851 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
852 val = ICH_IOCE | ICH_STARTBM;
853 break;
854 default:
855 return -EINVAL;
856 }
857 iputbyte(chip, port + ICH_REG_OFF_CR, val);
858 if (cmd == SNDRV_PCM_TRIGGER_STOP) {
859 /* wait until DMA stopped */
860 while (!(igetbyte(chip, port + ichdev->roff_sr) & ICH_DCH)) ;
861 /* reset whole DMA things */
862 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_RESETREGS);
863 }
864 return 0;
865}
866
867static int snd_intel8x0_ali_trigger(struct snd_pcm_substream *substream, int cmd)
868{
869 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
870 struct ichdev *ichdev = get_ichdev(substream);
871 unsigned long port = ichdev->reg_offset;
872 static int fiforeg[] = {
873 ICHREG(ALI_FIFOCR1), ICHREG(ALI_FIFOCR2), ICHREG(ALI_FIFOCR3)
874 };
875 unsigned int val, fifo;
876
877 val = igetdword(chip, ICHREG(ALI_DMACR));
878 switch (cmd) {
879 case SNDRV_PCM_TRIGGER_RESUME:
880 ichdev->suspended = 0;
881 /* fallthru */
882 case SNDRV_PCM_TRIGGER_START:
883 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
884 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
885 /* clear FIFO for synchronization of channels */
886 fifo = igetdword(chip, fiforeg[ichdev->ali_slot / 4]);
887 fifo &= ~(0xff << (ichdev->ali_slot % 4));
888 fifo |= 0x83 << (ichdev->ali_slot % 4);
889 iputdword(chip, fiforeg[ichdev->ali_slot / 4], fifo);
890 }
891 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_IOCE);
892 val &= ~(1 << (ichdev->ali_slot + 16)); /* clear PAUSE flag */
893 /* start DMA */
894 iputdword(chip, ICHREG(ALI_DMACR), val | (1 << ichdev->ali_slot));
895 break;
896 case SNDRV_PCM_TRIGGER_SUSPEND:
897 ichdev->suspended = 1;
898 /* fallthru */
899 case SNDRV_PCM_TRIGGER_STOP:
900 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
901 /* pause */
902 iputdword(chip, ICHREG(ALI_DMACR), val | (1 << (ichdev->ali_slot + 16)));
903 iputbyte(chip, port + ICH_REG_OFF_CR, 0);
904 while (igetbyte(chip, port + ICH_REG_OFF_CR))
905 ;
906 if (cmd == SNDRV_PCM_TRIGGER_PAUSE_PUSH)
907 break;
908 /* reset whole DMA things */
909 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_RESETREGS);
910 /* clear interrupts */
911 iputbyte(chip, port + ICH_REG_OFF_SR,
912 igetbyte(chip, port + ICH_REG_OFF_SR) | 0x1e);
913 iputdword(chip, ICHREG(ALI_INTERRUPTSR),
914 igetdword(chip, ICHREG(ALI_INTERRUPTSR)) & ichdev->int_sta_mask);
915 break;
916 default:
917 return -EINVAL;
918 }
919 return 0;
920}
921
922static int snd_intel8x0_hw_params(struct snd_pcm_substream *substream,
923 struct snd_pcm_hw_params *hw_params)
924{
925 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
926 struct ichdev *ichdev = get_ichdev(substream);
927 struct snd_pcm_runtime *runtime = substream->runtime;
928 int dbl = params_rate(hw_params) > 48000;
929 int err;
930
931 if (chip->fix_nocache && ichdev->page_attr_changed) {
932 fill_nocache(runtime->dma_area, runtime->dma_bytes, 0); /* clear */
933 ichdev->page_attr_changed = 0;
934 }
935 err = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params));
936 if (err < 0)
937 return err;
938 if (chip->fix_nocache) {
939 if (runtime->dma_area && ! ichdev->page_attr_changed) {
940 fill_nocache(runtime->dma_area, runtime->dma_bytes, 1);
941 ichdev->page_attr_changed = 1;
942 }
943 }
944 if (ichdev->pcm_open_flag) {
945 snd_ac97_pcm_close(ichdev->pcm);
946 ichdev->pcm_open_flag = 0;
947 }
948 err = snd_ac97_pcm_open(ichdev->pcm, params_rate(hw_params),
949 params_channels(hw_params),
950 ichdev->pcm->r[dbl].slots);
951 if (err >= 0) {
952 ichdev->pcm_open_flag = 1;
953 /* Force SPDIF setting */
954 if (ichdev->ichd == ICHD_PCMOUT && chip->spdif_idx < 0)
955 snd_ac97_set_rate(ichdev->pcm->r[0].codec[0], AC97_SPDIF,
956 params_rate(hw_params));
957 }
958 return err;
959}
960
961static int snd_intel8x0_hw_free(struct snd_pcm_substream *substream)
962{
963 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
964 struct ichdev *ichdev = get_ichdev(substream);
965
966 if (ichdev->pcm_open_flag) {
967 snd_ac97_pcm_close(ichdev->pcm);
968 ichdev->pcm_open_flag = 0;
969 }
970 if (chip->fix_nocache && ichdev->page_attr_changed) {
971 fill_nocache(substream->runtime->dma_area, substream->runtime->dma_bytes, 0);
972 ichdev->page_attr_changed = 0;
973 }
974 return snd_pcm_lib_free_pages(substream);
975}
976
977static void snd_intel8x0_setup_pcm_out(struct intel8x0 *chip,
978 struct snd_pcm_runtime *runtime)
979{
980 unsigned int cnt;
981 int dbl = runtime->rate > 48000;
982
983 spin_lock_irq(&chip->reg_lock);
984 switch (chip->device_type) {
985 case DEVICE_ALI:
986 cnt = igetdword(chip, ICHREG(ALI_SCR));
987 cnt &= ~ICH_ALI_SC_PCM_246_MASK;
988 if (runtime->channels == 4 || dbl)
989 cnt |= ICH_ALI_SC_PCM_4;
990 else if (runtime->channels == 6)
991 cnt |= ICH_ALI_SC_PCM_6;
992 iputdword(chip, ICHREG(ALI_SCR), cnt);
993 break;
994 case DEVICE_SIS:
995 cnt = igetdword(chip, ICHREG(GLOB_CNT));
996 cnt &= ~ICH_SIS_PCM_246_MASK;
997 if (runtime->channels == 4 || dbl)
998 cnt |= ICH_SIS_PCM_4;
999 else if (runtime->channels == 6)
1000 cnt |= ICH_SIS_PCM_6;
1001 iputdword(chip, ICHREG(GLOB_CNT), cnt);
1002 break;
1003 default:
1004 cnt = igetdword(chip, ICHREG(GLOB_CNT));
1005 cnt &= ~(ICH_PCM_246_MASK | ICH_PCM_20BIT);
1006 if (runtime->channels == 4 || dbl)
1007 cnt |= ICH_PCM_4;
1008 else if (runtime->channels == 6)
1009 cnt |= ICH_PCM_6;
1010 else if (runtime->channels == 8)
1011 cnt |= ICH_PCM_8;
1012 if (chip->device_type == DEVICE_NFORCE) {
1013 /* reset to 2ch once to keep the 6 channel data in alignment,
1014 * to start from Front Left always
1015 */
1016 if (cnt & ICH_PCM_246_MASK) {
1017 iputdword(chip, ICHREG(GLOB_CNT), cnt & ~ICH_PCM_246_MASK);
1018 spin_unlock_irq(&chip->reg_lock);
1019 msleep(50); /* grrr... */
1020 spin_lock_irq(&chip->reg_lock);
1021 }
1022 } else if (chip->device_type == DEVICE_INTEL_ICH4) {
1023 if (runtime->sample_bits > 16)
1024 cnt |= ICH_PCM_20BIT;
1025 }
1026 iputdword(chip, ICHREG(GLOB_CNT), cnt);
1027 break;
1028 }
1029 spin_unlock_irq(&chip->reg_lock);
1030}
1031
1032static int snd_intel8x0_pcm_prepare(struct snd_pcm_substream *substream)
1033{
1034 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1035 struct snd_pcm_runtime *runtime = substream->runtime;
1036 struct ichdev *ichdev = get_ichdev(substream);
1037
1038 ichdev->physbuf = runtime->dma_addr;
1039 ichdev->size = snd_pcm_lib_buffer_bytes(substream);
1040 ichdev->fragsize = snd_pcm_lib_period_bytes(substream);
1041 if (ichdev->ichd == ICHD_PCMOUT) {
1042 snd_intel8x0_setup_pcm_out(chip, runtime);
1043 if (chip->device_type == DEVICE_INTEL_ICH4)
1044 ichdev->pos_shift = (runtime->sample_bits > 16) ? 2 : 1;
1045 }
1046 snd_intel8x0_setup_periods(chip, ichdev);
1047 return 0;
1048}
1049
1050static snd_pcm_uframes_t snd_intel8x0_pcm_pointer(struct snd_pcm_substream *substream)
1051{
1052 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1053 struct ichdev *ichdev = get_ichdev(substream);
1054 size_t ptr1, ptr;
1055 int civ, timeout = 100;
1056 unsigned int position;
1057
1058 spin_lock(&chip->reg_lock);
1059 do {
1060 civ = igetbyte(chip, ichdev->reg_offset + ICH_REG_OFF_CIV);
1061 ptr1 = igetword(chip, ichdev->reg_offset + ichdev->roff_picb);
1062 position = ichdev->position;
1063 if (ptr1 == 0) {
1064 udelay(10);
1065 continue;
1066 }
1067 if (civ == igetbyte(chip, ichdev->reg_offset + ICH_REG_OFF_CIV) &&
1068 ptr1 == igetword(chip, ichdev->reg_offset + ichdev->roff_picb))
1069 break;
1070 } while (timeout--);
1071 ptr1 <<= ichdev->pos_shift;
1072 ptr = ichdev->fragsize1 - ptr1;
1073 ptr += position;
1074 spin_unlock(&chip->reg_lock);
1075 if (ptr >= ichdev->size)
1076 return 0;
1077 return bytes_to_frames(substream->runtime, ptr);
1078}
1079
1080static struct snd_pcm_hardware snd_intel8x0_stream =
1081{
1082 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1083 SNDRV_PCM_INFO_BLOCK_TRANSFER |
1084 SNDRV_PCM_INFO_MMAP_VALID |
1085 SNDRV_PCM_INFO_PAUSE |
1086 SNDRV_PCM_INFO_RESUME),
1087 .formats = SNDRV_PCM_FMTBIT_S16_LE,
1088 .rates = SNDRV_PCM_RATE_48000,
1089 .rate_min = 48000,
1090 .rate_max = 48000,
1091 .channels_min = 2,
1092 .channels_max = 2,
1093 .buffer_bytes_max = 128 * 1024,
1094 .period_bytes_min = 32,
1095 .period_bytes_max = 128 * 1024,
1096 .periods_min = 1,
1097 .periods_max = 1024,
1098 .fifo_size = 0,
1099};
1100
1101static unsigned int channels4[] = {
1102 2, 4,
1103};
1104
1105static struct snd_pcm_hw_constraint_list hw_constraints_channels4 = {
1106 .count = ARRAY_SIZE(channels4),
1107 .list = channels4,
1108 .mask = 0,
1109};
1110
1111static unsigned int channels6[] = {
1112 2, 4, 6,
1113};
1114
1115static struct snd_pcm_hw_constraint_list hw_constraints_channels6 = {
1116 .count = ARRAY_SIZE(channels6),
1117 .list = channels6,
1118 .mask = 0,
1119};
1120
1121static unsigned int channels8[] = {
1122 2, 4, 6, 8,
1123};
1124
1125static struct snd_pcm_hw_constraint_list hw_constraints_channels8 = {
1126 .count = ARRAY_SIZE(channels8),
1127 .list = channels8,
1128 .mask = 0,
1129};
1130
1131static int snd_intel8x0_pcm_open(struct snd_pcm_substream *substream, struct ichdev *ichdev)
1132{
1133 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1134 struct snd_pcm_runtime *runtime = substream->runtime;
1135 int err;
1136
1137 ichdev->substream = substream;
1138 runtime->hw = snd_intel8x0_stream;
1139 runtime->hw.rates = ichdev->pcm->rates;
1140 snd_pcm_limit_hw_rates(runtime);
1141 if (chip->device_type == DEVICE_SIS) {
1142 runtime->hw.buffer_bytes_max = 64*1024;
1143 runtime->hw.period_bytes_max = 64*1024;
1144 }
1145 if ((err = snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS)) < 0)
1146 return err;
1147 runtime->private_data = ichdev;
1148 return 0;
1149}
1150
1151static int snd_intel8x0_playback_open(struct snd_pcm_substream *substream)
1152{
1153 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1154 struct snd_pcm_runtime *runtime = substream->runtime;
1155 int err;
1156
1157 err = snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_PCMOUT]);
1158 if (err < 0)
1159 return err;
1160
1161 if (chip->multi8) {
1162 runtime->hw.channels_max = 8;
1163 snd_pcm_hw_constraint_list(runtime, 0,
1164 SNDRV_PCM_HW_PARAM_CHANNELS,
1165 &hw_constraints_channels8);
1166 } else if (chip->multi6) {
1167 runtime->hw.channels_max = 6;
1168 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
1169 &hw_constraints_channels6);
1170 } else if (chip->multi4) {
1171 runtime->hw.channels_max = 4;
1172 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
1173 &hw_constraints_channels4);
1174 }
1175 if (chip->dra) {
1176 snd_ac97_pcm_double_rate_rules(runtime);
1177 }
1178 if (chip->smp20bit) {
1179 runtime->hw.formats |= SNDRV_PCM_FMTBIT_S32_LE;
1180 snd_pcm_hw_constraint_msbits(runtime, 0, 32, 20);
1181 }
1182 return 0;
1183}
1184
1185static int snd_intel8x0_playback_close(struct snd_pcm_substream *substream)
1186{
1187 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1188
1189 chip->ichd[ICHD_PCMOUT].substream = NULL;
1190 return 0;
1191}
1192
1193static int snd_intel8x0_capture_open(struct snd_pcm_substream *substream)
1194{
1195 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1196
1197 return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_PCMIN]);
1198}
1199
1200static int snd_intel8x0_capture_close(struct snd_pcm_substream *substream)
1201{
1202 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1203
1204 chip->ichd[ICHD_PCMIN].substream = NULL;
1205 return 0;
1206}
1207
1208static int snd_intel8x0_mic_open(struct snd_pcm_substream *substream)
1209{
1210 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1211
1212 return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_MIC]);
1213}
1214
1215static int snd_intel8x0_mic_close(struct snd_pcm_substream *substream)
1216{
1217 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1218
1219 chip->ichd[ICHD_MIC].substream = NULL;
1220 return 0;
1221}
1222
1223static int snd_intel8x0_mic2_open(struct snd_pcm_substream *substream)
1224{
1225 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1226
1227 return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_MIC2]);
1228}
1229
1230static int snd_intel8x0_mic2_close(struct snd_pcm_substream *substream)
1231{
1232 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1233
1234 chip->ichd[ICHD_MIC2].substream = NULL;
1235 return 0;
1236}
1237
1238static int snd_intel8x0_capture2_open(struct snd_pcm_substream *substream)
1239{
1240 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1241
1242 return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_PCM2IN]);
1243}
1244
1245static int snd_intel8x0_capture2_close(struct snd_pcm_substream *substream)
1246{
1247 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1248
1249 chip->ichd[ICHD_PCM2IN].substream = NULL;
1250 return 0;
1251}
1252
1253static int snd_intel8x0_spdif_open(struct snd_pcm_substream *substream)
1254{
1255 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1256 int idx = chip->device_type == DEVICE_NFORCE ? NVD_SPBAR : ICHD_SPBAR;
1257
1258 return snd_intel8x0_pcm_open(substream, &chip->ichd[idx]);
1259}
1260
1261static int snd_intel8x0_spdif_close(struct snd_pcm_substream *substream)
1262{
1263 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1264 int idx = chip->device_type == DEVICE_NFORCE ? NVD_SPBAR : ICHD_SPBAR;
1265
1266 chip->ichd[idx].substream = NULL;
1267 return 0;
1268}
1269
1270static int snd_intel8x0_ali_ac97spdifout_open(struct snd_pcm_substream *substream)
1271{
1272 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1273 unsigned int val;
1274
1275 spin_lock_irq(&chip->reg_lock);
1276 val = igetdword(chip, ICHREG(ALI_INTERFACECR));
1277 val |= ICH_ALI_IF_AC97SP;
1278 iputdword(chip, ICHREG(ALI_INTERFACECR), val);
1279 /* also needs to set ALI_SC_CODEC_SPDF correctly */
1280 spin_unlock_irq(&chip->reg_lock);
1281
1282 return snd_intel8x0_pcm_open(substream, &chip->ichd[ALID_AC97SPDIFOUT]);
1283}
1284
1285static int snd_intel8x0_ali_ac97spdifout_close(struct snd_pcm_substream *substream)
1286{
1287 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1288 unsigned int val;
1289
1290 chip->ichd[ALID_AC97SPDIFOUT].substream = NULL;
1291 spin_lock_irq(&chip->reg_lock);
1292 val = igetdword(chip, ICHREG(ALI_INTERFACECR));
1293 val &= ~ICH_ALI_IF_AC97SP;
1294 iputdword(chip, ICHREG(ALI_INTERFACECR), val);
1295 spin_unlock_irq(&chip->reg_lock);
1296
1297 return 0;
1298}
1299
1300#if 0 // NYI
1301static int snd_intel8x0_ali_spdifin_open(struct snd_pcm_substream *substream)
1302{
1303 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1304
1305 return snd_intel8x0_pcm_open(substream, &chip->ichd[ALID_SPDIFIN]);
1306}
1307
1308static int snd_intel8x0_ali_spdifin_close(struct snd_pcm_substream *substream)
1309{
1310 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1311
1312 chip->ichd[ALID_SPDIFIN].substream = NULL;
1313 return 0;
1314}
1315
1316static int snd_intel8x0_ali_spdifout_open(struct snd_pcm_substream *substream)
1317{
1318 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1319
1320 return snd_intel8x0_pcm_open(substream, &chip->ichd[ALID_SPDIFOUT]);
1321}
1322
1323static int snd_intel8x0_ali_spdifout_close(struct snd_pcm_substream *substream)
1324{
1325 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1326
1327 chip->ichd[ALID_SPDIFOUT].substream = NULL;
1328 return 0;
1329}
1330#endif
1331
1332static struct snd_pcm_ops snd_intel8x0_playback_ops = {
1333 .open = snd_intel8x0_playback_open,
1334 .close = snd_intel8x0_playback_close,
1335 .ioctl = snd_pcm_lib_ioctl,
1336 .hw_params = snd_intel8x0_hw_params,
1337 .hw_free = snd_intel8x0_hw_free,
1338 .prepare = snd_intel8x0_pcm_prepare,
1339 .trigger = snd_intel8x0_pcm_trigger,
1340 .pointer = snd_intel8x0_pcm_pointer,
1341};
1342
1343static struct snd_pcm_ops snd_intel8x0_capture_ops = {
1344 .open = snd_intel8x0_capture_open,
1345 .close = snd_intel8x0_capture_close,
1346 .ioctl = snd_pcm_lib_ioctl,
1347 .hw_params = snd_intel8x0_hw_params,
1348 .hw_free = snd_intel8x0_hw_free,
1349 .prepare = snd_intel8x0_pcm_prepare,
1350 .trigger = snd_intel8x0_pcm_trigger,
1351 .pointer = snd_intel8x0_pcm_pointer,
1352};
1353
1354static struct snd_pcm_ops snd_intel8x0_capture_mic_ops = {
1355 .open = snd_intel8x0_mic_open,
1356 .close = snd_intel8x0_mic_close,
1357 .ioctl = snd_pcm_lib_ioctl,
1358 .hw_params = snd_intel8x0_hw_params,
1359 .hw_free = snd_intel8x0_hw_free,
1360 .prepare = snd_intel8x0_pcm_prepare,
1361 .trigger = snd_intel8x0_pcm_trigger,
1362 .pointer = snd_intel8x0_pcm_pointer,
1363};
1364
1365static struct snd_pcm_ops snd_intel8x0_capture_mic2_ops = {
1366 .open = snd_intel8x0_mic2_open,
1367 .close = snd_intel8x0_mic2_close,
1368 .ioctl = snd_pcm_lib_ioctl,
1369 .hw_params = snd_intel8x0_hw_params,
1370 .hw_free = snd_intel8x0_hw_free,
1371 .prepare = snd_intel8x0_pcm_prepare,
1372 .trigger = snd_intel8x0_pcm_trigger,
1373 .pointer = snd_intel8x0_pcm_pointer,
1374};
1375
1376static struct snd_pcm_ops snd_intel8x0_capture2_ops = {
1377 .open = snd_intel8x0_capture2_open,
1378 .close = snd_intel8x0_capture2_close,
1379 .ioctl = snd_pcm_lib_ioctl,
1380 .hw_params = snd_intel8x0_hw_params,
1381 .hw_free = snd_intel8x0_hw_free,
1382 .prepare = snd_intel8x0_pcm_prepare,
1383 .trigger = snd_intel8x0_pcm_trigger,
1384 .pointer = snd_intel8x0_pcm_pointer,
1385};
1386
1387static struct snd_pcm_ops snd_intel8x0_spdif_ops = {
1388 .open = snd_intel8x0_spdif_open,
1389 .close = snd_intel8x0_spdif_close,
1390 .ioctl = snd_pcm_lib_ioctl,
1391 .hw_params = snd_intel8x0_hw_params,
1392 .hw_free = snd_intel8x0_hw_free,
1393 .prepare = snd_intel8x0_pcm_prepare,
1394 .trigger = snd_intel8x0_pcm_trigger,
1395 .pointer = snd_intel8x0_pcm_pointer,
1396};
1397
1398static struct snd_pcm_ops snd_intel8x0_ali_playback_ops = {
1399 .open = snd_intel8x0_playback_open,
1400 .close = snd_intel8x0_playback_close,
1401 .ioctl = snd_pcm_lib_ioctl,
1402 .hw_params = snd_intel8x0_hw_params,
1403 .hw_free = snd_intel8x0_hw_free,
1404 .prepare = snd_intel8x0_pcm_prepare,
1405 .trigger = snd_intel8x0_ali_trigger,
1406 .pointer = snd_intel8x0_pcm_pointer,
1407};
1408
1409static struct snd_pcm_ops snd_intel8x0_ali_capture_ops = {
1410 .open = snd_intel8x0_capture_open,
1411 .close = snd_intel8x0_capture_close,
1412 .ioctl = snd_pcm_lib_ioctl,
1413 .hw_params = snd_intel8x0_hw_params,
1414 .hw_free = snd_intel8x0_hw_free,
1415 .prepare = snd_intel8x0_pcm_prepare,
1416 .trigger = snd_intel8x0_ali_trigger,
1417 .pointer = snd_intel8x0_pcm_pointer,
1418};
1419
1420static struct snd_pcm_ops snd_intel8x0_ali_capture_mic_ops = {
1421 .open = snd_intel8x0_mic_open,
1422 .close = snd_intel8x0_mic_close,
1423 .ioctl = snd_pcm_lib_ioctl,
1424 .hw_params = snd_intel8x0_hw_params,
1425 .hw_free = snd_intel8x0_hw_free,
1426 .prepare = snd_intel8x0_pcm_prepare,
1427 .trigger = snd_intel8x0_ali_trigger,
1428 .pointer = snd_intel8x0_pcm_pointer,
1429};
1430
1431static struct snd_pcm_ops snd_intel8x0_ali_ac97spdifout_ops = {
1432 .open = snd_intel8x0_ali_ac97spdifout_open,
1433 .close = snd_intel8x0_ali_ac97spdifout_close,
1434 .ioctl = snd_pcm_lib_ioctl,
1435 .hw_params = snd_intel8x0_hw_params,
1436 .hw_free = snd_intel8x0_hw_free,
1437 .prepare = snd_intel8x0_pcm_prepare,
1438 .trigger = snd_intel8x0_ali_trigger,
1439 .pointer = snd_intel8x0_pcm_pointer,
1440};
1441
1442#if 0 // NYI
1443static struct snd_pcm_ops snd_intel8x0_ali_spdifin_ops = {
1444 .open = snd_intel8x0_ali_spdifin_open,
1445 .close = snd_intel8x0_ali_spdifin_close,
1446 .ioctl = snd_pcm_lib_ioctl,
1447 .hw_params = snd_intel8x0_hw_params,
1448 .hw_free = snd_intel8x0_hw_free,
1449 .prepare = snd_intel8x0_pcm_prepare,
1450 .trigger = snd_intel8x0_pcm_trigger,
1451 .pointer = snd_intel8x0_pcm_pointer,
1452};
1453
1454static struct snd_pcm_ops snd_intel8x0_ali_spdifout_ops = {
1455 .open = snd_intel8x0_ali_spdifout_open,
1456 .close = snd_intel8x0_ali_spdifout_close,
1457 .ioctl = snd_pcm_lib_ioctl,
1458 .hw_params = snd_intel8x0_hw_params,
1459 .hw_free = snd_intel8x0_hw_free,
1460 .prepare = snd_intel8x0_pcm_prepare,
1461 .trigger = snd_intel8x0_pcm_trigger,
1462 .pointer = snd_intel8x0_pcm_pointer,
1463};
1464#endif // NYI
1465
1466struct ich_pcm_table {
1467 char *suffix;
1468 struct snd_pcm_ops *playback_ops;
1469 struct snd_pcm_ops *capture_ops;
1470 size_t prealloc_size;
1471 size_t prealloc_max_size;
1472 int ac97_idx;
1473};
1474
1475static int __devinit snd_intel8x0_pcm1(struct intel8x0 *chip, int device,
1476 struct ich_pcm_table *rec)
1477{
1478 struct snd_pcm *pcm;
1479 int err;
1480 char name[32];
1481
1482 if (rec->suffix)
1483 sprintf(name, "Intel ICH - %s", rec->suffix);
1484 else
1485 strcpy(name, "Intel ICH");
1486 err = snd_pcm_new(chip->card, name, device,
1487 rec->playback_ops ? 1 : 0,
1488 rec->capture_ops ? 1 : 0, &pcm);
1489 if (err < 0)
1490 return err;
1491
1492 if (rec->playback_ops)
1493 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, rec->playback_ops);
1494 if (rec->capture_ops)
1495 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, rec->capture_ops);
1496
1497 pcm->private_data = chip;
1498 pcm->info_flags = 0;
1499 if (rec->suffix)
1500 sprintf(pcm->name, "%s - %s", chip->card->shortname, rec->suffix);
1501 else
1502 strcpy(pcm->name, chip->card->shortname);
1503 chip->pcm[device] = pcm;
1504
1505 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1506 snd_dma_pci_data(chip->pci),
1507 rec->prealloc_size, rec->prealloc_max_size);
1508
1509 return 0;
1510}
1511
1512static struct ich_pcm_table intel_pcms[] __devinitdata = {
1513 {
1514 .playback_ops = &snd_intel8x0_playback_ops,
1515 .capture_ops = &snd_intel8x0_capture_ops,
1516 .prealloc_size = 64 * 1024,
1517 .prealloc_max_size = 128 * 1024,
1518 },
1519 {
1520 .suffix = "MIC ADC",
1521 .capture_ops = &snd_intel8x0_capture_mic_ops,
1522 .prealloc_size = 0,
1523 .prealloc_max_size = 128 * 1024,
1524 .ac97_idx = ICHD_MIC,
1525 },
1526 {
1527 .suffix = "MIC2 ADC",
1528 .capture_ops = &snd_intel8x0_capture_mic2_ops,
1529 .prealloc_size = 0,
1530 .prealloc_max_size = 128 * 1024,
1531 .ac97_idx = ICHD_MIC2,
1532 },
1533 {
1534 .suffix = "ADC2",
1535 .capture_ops = &snd_intel8x0_capture2_ops,
1536 .prealloc_size = 0,
1537 .prealloc_max_size = 128 * 1024,
1538 .ac97_idx = ICHD_PCM2IN,
1539 },
1540 {
1541 .suffix = "IEC958",
1542 .playback_ops = &snd_intel8x0_spdif_ops,
1543 .prealloc_size = 64 * 1024,
1544 .prealloc_max_size = 128 * 1024,
1545 .ac97_idx = ICHD_SPBAR,
1546 },
1547};
1548
1549static struct ich_pcm_table nforce_pcms[] __devinitdata = {
1550 {
1551 .playback_ops = &snd_intel8x0_playback_ops,
1552 .capture_ops = &snd_intel8x0_capture_ops,
1553 .prealloc_size = 64 * 1024,
1554 .prealloc_max_size = 128 * 1024,
1555 },
1556 {
1557 .suffix = "MIC ADC",
1558 .capture_ops = &snd_intel8x0_capture_mic_ops,
1559 .prealloc_size = 0,
1560 .prealloc_max_size = 128 * 1024,
1561 .ac97_idx = NVD_MIC,
1562 },
1563 {
1564 .suffix = "IEC958",
1565 .playback_ops = &snd_intel8x0_spdif_ops,
1566 .prealloc_size = 64 * 1024,
1567 .prealloc_max_size = 128 * 1024,
1568 .ac97_idx = NVD_SPBAR,
1569 },
1570};
1571
1572static struct ich_pcm_table ali_pcms[] __devinitdata = {
1573 {
1574 .playback_ops = &snd_intel8x0_ali_playback_ops,
1575 .capture_ops = &snd_intel8x0_ali_capture_ops,
1576 .prealloc_size = 64 * 1024,
1577 .prealloc_max_size = 128 * 1024,
1578 },
1579 {
1580 .suffix = "MIC ADC",
1581 .capture_ops = &snd_intel8x0_ali_capture_mic_ops,
1582 .prealloc_size = 0,
1583 .prealloc_max_size = 128 * 1024,
1584 .ac97_idx = ALID_MIC,
1585 },
1586 {
1587 .suffix = "IEC958",
1588 .playback_ops = &snd_intel8x0_ali_ac97spdifout_ops,
1589 /* .capture_ops = &snd_intel8x0_ali_spdifin_ops, */
1590 .prealloc_size = 64 * 1024,
1591 .prealloc_max_size = 128 * 1024,
1592 .ac97_idx = ALID_AC97SPDIFOUT,
1593 },
1594#if 0 // NYI
1595 {
1596 .suffix = "HW IEC958",
1597 .playback_ops = &snd_intel8x0_ali_spdifout_ops,
1598 .prealloc_size = 64 * 1024,
1599 .prealloc_max_size = 128 * 1024,
1600 },
1601#endif
1602};
1603
1604static int __devinit snd_intel8x0_pcm(struct intel8x0 *chip)
1605{
1606 int i, tblsize, device, err;
1607 struct ich_pcm_table *tbl, *rec;
1608
1609 switch (chip->device_type) {
1610 case DEVICE_INTEL_ICH4:
1611 tbl = intel_pcms;
1612 tblsize = ARRAY_SIZE(intel_pcms);
1613 if (spdif_aclink)
1614 tblsize--;
1615 break;
1616 case DEVICE_NFORCE:
1617 tbl = nforce_pcms;
1618 tblsize = ARRAY_SIZE(nforce_pcms);
1619 if (spdif_aclink)
1620 tblsize--;
1621 break;
1622 case DEVICE_ALI:
1623 tbl = ali_pcms;
1624 tblsize = ARRAY_SIZE(ali_pcms);
1625 break;
1626 default:
1627 tbl = intel_pcms;
1628 tblsize = 2;
1629 break;
1630 }
1631
1632 device = 0;
1633 for (i = 0; i < tblsize; i++) {
1634 rec = tbl + i;
1635 if (i > 0 && rec->ac97_idx) {
1636 /* activate PCM only when associated AC'97 codec */
1637 if (! chip->ichd[rec->ac97_idx].pcm)
1638 continue;
1639 }
1640 err = snd_intel8x0_pcm1(chip, device, rec);
1641 if (err < 0)
1642 return err;
1643 device++;
1644 }
1645
1646 chip->pcm_devs = device;
1647 return 0;
1648}
1649
1650
1651/*
1652 * Mixer part
1653 */
1654
1655static void snd_intel8x0_mixer_free_ac97_bus(struct snd_ac97_bus *bus)
1656{
1657 struct intel8x0 *chip = bus->private_data;
1658 chip->ac97_bus = NULL;
1659}
1660
1661static void snd_intel8x0_mixer_free_ac97(struct snd_ac97 *ac97)
1662{
1663 struct intel8x0 *chip = ac97->private_data;
1664 chip->ac97[ac97->num] = NULL;
1665}
1666
1667static struct ac97_pcm ac97_pcm_defs[] __devinitdata = {
1668 /* front PCM */
1669 {
1670 .exclusive = 1,
1671 .r =
1672 {
1673 {
1674 .slots = (1 << AC97_SLOT_PCM_LEFT) |
1675 (1 << AC97_SLOT_PCM_RIGHT) |
1676 (1 << AC97_SLOT_PCM_CENTER) |
1677 (1 << AC97_SLOT_PCM_SLEFT) |
1678 (1 << AC97_SLOT_PCM_SRIGHT) |
1679 (1 << AC97_SLOT_LFE)
1680 },
1681 {
1682 .slots = (1 << AC97_SLOT_PCM_LEFT) |
1683 (1 << AC97_SLOT_PCM_RIGHT) |
1684 (1 << AC97_SLOT_PCM_LEFT_0) |
1685 (1 << AC97_SLOT_PCM_RIGHT_0)
1686 }
1687 }
1688 },
1689 /* PCM IN #1 */
1690 {
1691 .stream = 1,
1692 .exclusive = 1,
1693 .r = { {
1694 .slots = (1 << AC97_SLOT_PCM_LEFT) |
1695 (1 << AC97_SLOT_PCM_RIGHT)
1696 }
1697 }
1698 },
1699 /* MIC IN #1 */
1700 {
1701 .stream = 1,
1702 .exclusive = 1,
1703 .r = { {
1704 .slots = (1 << AC97_SLOT_MIC)
1705 }
1706 }
1707 },
1708 /* S/PDIF PCM */
1709 {
1710 .exclusive = 1,
1711 .spdif = 1,
1712 .r = { {
1713 .slots = (1 << AC97_SLOT_SPDIF_LEFT2) |
1714 (1 << AC97_SLOT_SPDIF_RIGHT2)
1715 }
1716 }
1717 },
1718 /* PCM IN #2 */
1719 {
1720 .stream = 1,
1721 .exclusive = 1,
1722 .r = { {
1723 .slots = (1 << AC97_SLOT_PCM_LEFT) |
1724 (1 << AC97_SLOT_PCM_RIGHT)
1725 }
1726 }
1727 },
1728 /* MIC IN #2 */
1729 {
1730 .stream = 1,
1731 .exclusive = 1,
1732 .r = { {
1733 .slots = (1 << AC97_SLOT_MIC)
1734 }
1735 }
1736 },
1737};
1738
1739static struct ac97_quirk ac97_quirks[] __devinitdata = {
1740 {
1741 .subvendor = 0x0e11,
1742 .subdevice = 0x000e,
1743 .name = "Compaq Deskpro EN", /* AD1885 */
1744 .type = AC97_TUNE_HP_ONLY
1745 },
1746 {
1747 .subvendor = 0x0e11,
1748 .subdevice = 0x008a,
1749 .name = "Compaq Evo W4000", /* AD1885 */
1750 .type = AC97_TUNE_HP_ONLY
1751 },
1752 {
1753 .subvendor = 0x0e11,
1754 .subdevice = 0x00b8,
1755 .name = "Compaq Evo D510C",
1756 .type = AC97_TUNE_HP_ONLY
1757 },
1758 {
1759 .subvendor = 0x0e11,
1760 .subdevice = 0x0860,
1761 .name = "HP/Compaq nx7010",
1762 .type = AC97_TUNE_MUTE_LED
1763 },
1764 {
1765 .subvendor = 0x1014,
1766 .subdevice = 0x1f00,
1767 .name = "MS-9128",
1768 .type = AC97_TUNE_ALC_JACK
1769 },
1770 {
1771 .subvendor = 0x1014,
1772 .subdevice = 0x0267,
1773 .name = "IBM NetVista A30p", /* AD1981B */
1774 .type = AC97_TUNE_HP_ONLY
1775 },
1776 {
1777 .subvendor = 0x1025,
1778 .subdevice = 0x0082,
1779 .name = "Acer Travelmate 2310",
1780 .type = AC97_TUNE_HP_ONLY
1781 },
1782 {
1783 .subvendor = 0x1025,
1784 .subdevice = 0x0083,
1785 .name = "Acer Aspire 3003LCi",
1786 .type = AC97_TUNE_HP_ONLY
1787 },
1788 {
1789 .subvendor = 0x1028,
1790 .subdevice = 0x00d8,
1791 .name = "Dell Precision 530", /* AD1885 */
1792 .type = AC97_TUNE_HP_ONLY
1793 },
1794 {
1795 .subvendor = 0x1028,
1796 .subdevice = 0x010d,
1797 .name = "Dell", /* which model? AD1885 */
1798 .type = AC97_TUNE_HP_ONLY
1799 },
1800 {
1801 .subvendor = 0x1028,
1802 .subdevice = 0x0126,
1803 .name = "Dell Optiplex GX260", /* AD1981A */
1804 .type = AC97_TUNE_HP_ONLY
1805 },
1806 {
1807 .subvendor = 0x1028,
1808 .subdevice = 0x012c,
1809 .name = "Dell Precision 650", /* AD1981A */
1810 .type = AC97_TUNE_HP_ONLY
1811 },
1812 {
1813 .subvendor = 0x1028,
1814 .subdevice = 0x012d,
1815 .name = "Dell Precision 450", /* AD1981B*/
1816 .type = AC97_TUNE_HP_ONLY
1817 },
1818 {
1819 .subvendor = 0x1028,
1820 .subdevice = 0x0147,
1821 .name = "Dell", /* which model? AD1981B*/
1822 .type = AC97_TUNE_HP_ONLY
1823 },
1824 {
1825 .subvendor = 0x1028,
1826 .subdevice = 0x0151,
1827 .name = "Dell Optiplex GX270", /* AD1981B */
1828 .type = AC97_TUNE_HP_ONLY
1829 },
1830 {
1831 .subvendor = 0x1028,
1832 .subdevice = 0x014e,
1833 .name = "Dell D800", /* STAC9750/51 */
1834 .type = AC97_TUNE_HP_ONLY
1835 },
1836 {
1837 .subvendor = 0x1028,
1838 .subdevice = 0x0163,
1839 .name = "Dell Unknown", /* STAC9750/51 */
1840 .type = AC97_TUNE_HP_ONLY
1841 },
1842 {
1843 .subvendor = 0x1028,
1844 .subdevice = 0x0186,
1845 .name = "Dell Latitude D810", /* cf. Malone #41015 */
1846 .type = AC97_TUNE_HP_MUTE_LED
1847 },
1848 {
1849 .subvendor = 0x1028,
1850 .subdevice = 0x0188,
1851 .name = "Dell Inspiron 6000",
1852 .type = AC97_TUNE_HP_MUTE_LED /* cf. Malone #41015 */
1853 },
1854 {
1855 .subvendor = 0x1028,
1856 .subdevice = 0x0191,
1857 .name = "Dell Inspiron 8600",
1858 .type = AC97_TUNE_HP_ONLY
1859 },
1860 {
1861 .subvendor = 0x103c,
1862 .subdevice = 0x006d,
1863 .name = "HP zv5000",
1864 .type = AC97_TUNE_MUTE_LED /*AD1981B*/
1865 },
1866 { /* FIXME: which codec? */
1867 .subvendor = 0x103c,
1868 .subdevice = 0x00c3,
1869 .name = "HP xw6000",
1870 .type = AC97_TUNE_HP_ONLY
1871 },
1872 {
1873 .subvendor = 0x103c,
1874 .subdevice = 0x088c,
1875 .name = "HP nc8000",
1876 .type = AC97_TUNE_HP_MUTE_LED
1877 },
1878 {
1879 .subvendor = 0x103c,
1880 .subdevice = 0x0890,
1881 .name = "HP nc6000",
1882 .type = AC97_TUNE_MUTE_LED
1883 },
1884 {
1885 .subvendor = 0x103c,
1886 .subdevice = 0x0934,
1887 .name = "HP nx8220",
1888 .type = AC97_TUNE_MUTE_LED
1889 },
1890 {
1891 .subvendor = 0x103c,
1892 .subdevice = 0x129d,
1893 .name = "HP xw8000",
1894 .type = AC97_TUNE_HP_ONLY
1895 },
1896 {
1897 .subvendor = 0x103c,
1898 .subdevice = 0x0938,
1899 .name = "HP nc4200",
1900 .type = AC97_TUNE_HP_MUTE_LED
1901 },
1902 {
1903 .subvendor = 0x103c,
1904 .subdevice = 0x099c,
1905 .name = "HP nx6110/nc6120",
1906 .type = AC97_TUNE_HP_MUTE_LED
1907 },
1908 {
1909 .subvendor = 0x103c,
1910 .subdevice = 0x0944,
1911 .name = "HP nc6220",
1912 .type = AC97_TUNE_HP_MUTE_LED
1913 },
1914 {
1915 .subvendor = 0x103c,
1916 .subdevice = 0x0934,
1917 .name = "HP nc8220",
1918 .type = AC97_TUNE_HP_MUTE_LED
1919 },
1920 {
1921 .subvendor = 0x103c,
1922 .subdevice = 0x12f1,
1923 .name = "HP xw8200", /* AD1981B*/
1924 .type = AC97_TUNE_HP_ONLY
1925 },
1926 {
1927 .subvendor = 0x103c,
1928 .subdevice = 0x12f2,
1929 .name = "HP xw6200",
1930 .type = AC97_TUNE_HP_ONLY
1931 },
1932 {
1933 .subvendor = 0x103c,
1934 .subdevice = 0x3008,
1935 .name = "HP xw4200", /* AD1981B*/
1936 .type = AC97_TUNE_HP_ONLY
1937 },
1938 {
1939 .subvendor = 0x104d,
1940 .subdevice = 0x8197,
1941 .name = "Sony S1XP",
1942 .type = AC97_TUNE_INV_EAPD
1943 },
1944 {
1945 .subvendor = 0x1043,
1946 .subdevice = 0x80f3,
1947 .name = "ASUS ICH5/AD1985",
1948 .type = AC97_TUNE_AD_SHARING
1949 },
1950 {
1951 .subvendor = 0x10cf,
1952 .subdevice = 0x11c3,
1953 .name = "Fujitsu-Siemens E4010",
1954 .type = AC97_TUNE_HP_ONLY
1955 },
1956 {
1957 .subvendor = 0x10cf,
1958 .subdevice = 0x1225,
1959 .name = "Fujitsu-Siemens T3010",
1960 .type = AC97_TUNE_HP_ONLY
1961 },
1962 {
1963 .subvendor = 0x10cf,
1964 .subdevice = 0x1253,
1965 .name = "Fujitsu S6210", /* STAC9750/51 */
1966 .type = AC97_TUNE_HP_ONLY
1967 },
1968 {
1969 .subvendor = 0x10cf,
1970 .subdevice = 0x127d,
1971 .name = "Fujitsu Lifebook P7010",
1972 .type = AC97_TUNE_HP_ONLY
1973 },
1974 {
1975 .subvendor = 0x10cf,
1976 .subdevice = 0x127e,
1977 .name = "Fujitsu Lifebook C1211D",
1978 .type = AC97_TUNE_HP_ONLY
1979 },
1980 {
1981 .subvendor = 0x10cf,
1982 .subdevice = 0x12ec,
1983 .name = "Fujitsu-Siemens 4010",
1984 .type = AC97_TUNE_HP_ONLY
1985 },
1986 {
1987 .subvendor = 0x10cf,
1988 .subdevice = 0x12f2,
1989 .name = "Fujitsu-Siemens Celsius H320",
1990 .type = AC97_TUNE_SWAP_HP
1991 },
1992 {
1993 .subvendor = 0x10f1,
1994 .subdevice = 0x2665,
1995 .name = "Fujitsu-Siemens Celsius", /* AD1981? */
1996 .type = AC97_TUNE_HP_ONLY
1997 },
1998 {
1999 .subvendor = 0x10f1,
2000 .subdevice = 0x2885,
2001 .name = "AMD64 Mobo", /* ALC650 */
2002 .type = AC97_TUNE_HP_ONLY
2003 },
2004 {
2005 .subvendor = 0x10f1,
2006 .subdevice = 0x2895,
2007 .name = "Tyan Thunder K8WE",
2008 .type = AC97_TUNE_HP_ONLY
2009 },
2010 {
2011 .subvendor = 0x10f7,
2012 .subdevice = 0x834c,
2013 .name = "Panasonic CF-R4",
2014 .type = AC97_TUNE_HP_ONLY,
2015 },
2016 {
2017 .subvendor = 0x110a,
2018 .subdevice = 0x0056,
2019 .name = "Fujitsu-Siemens Scenic", /* AD1981? */
2020 .type = AC97_TUNE_HP_ONLY
2021 },
2022 {
2023 .subvendor = 0x11d4,
2024 .subdevice = 0x5375,
2025 .name = "ADI AD1985 (discrete)",
2026 .type = AC97_TUNE_HP_ONLY
2027 },
2028 {
2029 .subvendor = 0x1462,
2030 .subdevice = 0x5470,
2031 .name = "MSI P4 ATX 645 Ultra",
2032 .type = AC97_TUNE_HP_ONLY
2033 },
2034 {
2035 .subvendor = 0x1734,
2036 .subdevice = 0x0088,
2037 .name = "Fujitsu-Siemens D1522", /* AD1981 */
2038 .type = AC97_TUNE_HP_ONLY
2039 },
2040 {
2041 .subvendor = 0x8086,
2042 .subdevice = 0x2000,
2043 .mask = 0xfff0,
2044 .name = "Intel ICH5/AD1985",
2045 .type = AC97_TUNE_AD_SHARING
2046 },
2047 {
2048 .subvendor = 0x8086,
2049 .subdevice = 0x4000,
2050 .mask = 0xfff0,
2051 .name = "Intel ICH5/AD1985",
2052 .type = AC97_TUNE_AD_SHARING
2053 },
2054 {
2055 .subvendor = 0x8086,
2056 .subdevice = 0x4856,
2057 .name = "Intel D845WN (82801BA)",
2058 .type = AC97_TUNE_SWAP_HP
2059 },
2060 {
2061 .subvendor = 0x8086,
2062 .subdevice = 0x4d44,
2063 .name = "Intel D850EMV2", /* AD1885 */
2064 .type = AC97_TUNE_HP_ONLY
2065 },
2066 {
2067 .subvendor = 0x8086,
2068 .subdevice = 0x4d56,
2069 .name = "Intel ICH/AD1885",
2070 .type = AC97_TUNE_HP_ONLY
2071 },
2072 {
2073 .subvendor = 0x8086,
2074 .subdevice = 0x6000,
2075 .mask = 0xfff0,
2076 .name = "Intel ICH5/AD1985",
2077 .type = AC97_TUNE_AD_SHARING
2078 },
2079 {
2080 .subvendor = 0x8086,
2081 .subdevice = 0xe000,
2082 .mask = 0xfff0,
2083 .name = "Intel ICH5/AD1985",
2084 .type = AC97_TUNE_AD_SHARING
2085 },
2086#if 0 /* FIXME: this seems wrong on most boards */
2087 {
2088 .subvendor = 0x8086,
2089 .subdevice = 0xa000,
2090 .mask = 0xfff0,
2091 .name = "Intel ICH5/AD1985",
2092 .type = AC97_TUNE_HP_ONLY
2093 },
2094#endif
2095 {0} /* terminator */
2096};
2097
2098static int __devinit snd_intel8x0_mixer(struct intel8x0 *chip, int ac97_clock,
2099 const char *quirk_override)
2100{
2101 struct snd_ac97_bus *pbus;
2102 struct snd_ac97_template ac97;
2103 int err;
2104 unsigned int i, codecs;
2105 unsigned int glob_sta = 0;
2106 struct snd_ac97_bus_ops *ops;
2107 static struct snd_ac97_bus_ops standard_bus_ops = {
2108 .write = snd_intel8x0_codec_write,
2109 .read = snd_intel8x0_codec_read,
2110 };
2111 static struct snd_ac97_bus_ops ali_bus_ops = {
2112 .write = snd_intel8x0_ali_codec_write,
2113 .read = snd_intel8x0_ali_codec_read,
2114 };
2115
2116 chip->spdif_idx = -1; /* use PCMOUT (or disabled) */
2117 if (!spdif_aclink) {
2118 switch (chip->device_type) {
2119 case DEVICE_NFORCE:
2120 chip->spdif_idx = NVD_SPBAR;
2121 break;
2122 case DEVICE_ALI:
2123 chip->spdif_idx = ALID_AC97SPDIFOUT;
2124 break;
2125 case DEVICE_INTEL_ICH4:
2126 chip->spdif_idx = ICHD_SPBAR;
2127 break;
2128 };
2129 }
2130
2131 chip->in_ac97_init = 1;
2132
2133 memset(&ac97, 0, sizeof(ac97));
2134 ac97.private_data = chip;
2135 ac97.private_free = snd_intel8x0_mixer_free_ac97;
2136 ac97.scaps = AC97_SCAP_SKIP_MODEM | AC97_SCAP_POWER_SAVE;
2137 if (chip->xbox)
2138 ac97.scaps |= AC97_SCAP_DETECT_BY_VENDOR;
2139 if (chip->device_type != DEVICE_ALI) {
2140 glob_sta = igetdword(chip, ICHREG(GLOB_STA));
2141 ops = &standard_bus_ops;
2142 chip->in_sdin_init = 1;
2143 codecs = 0;
2144 for (i = 0; i < chip->max_codecs; i++) {
2145 if (! (glob_sta & chip->codec_bit[i]))
2146 continue;
2147 if (chip->device_type == DEVICE_INTEL_ICH4) {
2148 snd_intel8x0_codec_read_test(chip, codecs);
2149 chip->ac97_sdin[codecs] =
2150 igetbyte(chip, ICHREG(SDM)) & ICH_LDI_MASK;
2151 if (snd_BUG_ON(chip->ac97_sdin[codecs] >= 3))
2152 chip->ac97_sdin[codecs] = 0;
2153 } else
2154 chip->ac97_sdin[codecs] = i;
2155 codecs++;
2156 }
2157 chip->in_sdin_init = 0;
2158 if (! codecs)
2159 codecs = 1;
2160 } else {
2161 ops = &ali_bus_ops;
2162 codecs = 1;
2163 /* detect the secondary codec */
2164 for (i = 0; i < 100; i++) {
2165 unsigned int reg = igetdword(chip, ICHREG(ALI_RTSR));
2166 if (reg & 0x40) {
2167 codecs = 2;
2168 break;
2169 }
2170 iputdword(chip, ICHREG(ALI_RTSR), reg | 0x40);
2171 udelay(1);
2172 }
2173 }
2174 if ((err = snd_ac97_bus(chip->card, 0, ops, chip, &pbus)) < 0)
2175 goto __err;
2176 pbus->private_free = snd_intel8x0_mixer_free_ac97_bus;
2177 if (ac97_clock >= 8000 && ac97_clock <= 48000)
2178 pbus->clock = ac97_clock;
2179 /* FIXME: my test board doesn't work well with VRA... */
2180 if (chip->device_type == DEVICE_ALI)
2181 pbus->no_vra = 1;
2182 else
2183 pbus->dra = 1;
2184 chip->ac97_bus = pbus;
2185 chip->ncodecs = codecs;
2186
2187 ac97.pci = chip->pci;
2188 for (i = 0; i < codecs; i++) {
2189 ac97.num = i;
2190 if ((err = snd_ac97_mixer(pbus, &ac97, &chip->ac97[i])) < 0) {
2191 if (err != -EACCES)
2192 snd_printk(KERN_ERR "Unable to initialize codec #%d\n", i);
2193 if (i == 0)
2194 goto __err;
2195 }
2196 }
2197 /* tune up the primary codec */
2198 snd_ac97_tune_hardware(chip->ac97[0], ac97_quirks, quirk_override);
2199 /* enable separate SDINs for ICH4 */
2200 if (chip->device_type == DEVICE_INTEL_ICH4)
2201 pbus->isdin = 1;
2202 /* find the available PCM streams */
2203 i = ARRAY_SIZE(ac97_pcm_defs);
2204 if (chip->device_type != DEVICE_INTEL_ICH4)
2205 i -= 2; /* do not allocate PCM2IN and MIC2 */
2206 if (chip->spdif_idx < 0)
2207 i--; /* do not allocate S/PDIF */
2208 err = snd_ac97_pcm_assign(pbus, i, ac97_pcm_defs);
2209 if (err < 0)
2210 goto __err;
2211 chip->ichd[ICHD_PCMOUT].pcm = &pbus->pcms[0];
2212 chip->ichd[ICHD_PCMIN].pcm = &pbus->pcms[1];
2213 chip->ichd[ICHD_MIC].pcm = &pbus->pcms[2];
2214 if (chip->spdif_idx >= 0)
2215 chip->ichd[chip->spdif_idx].pcm = &pbus->pcms[3];
2216 if (chip->device_type == DEVICE_INTEL_ICH4) {
2217 chip->ichd[ICHD_PCM2IN].pcm = &pbus->pcms[4];
2218 chip->ichd[ICHD_MIC2].pcm = &pbus->pcms[5];
2219 }
2220 /* enable separate SDINs for ICH4 */
2221 if (chip->device_type == DEVICE_INTEL_ICH4) {
2222 struct ac97_pcm *pcm = chip->ichd[ICHD_PCM2IN].pcm;
2223 u8 tmp = igetbyte(chip, ICHREG(SDM));
2224 tmp &= ~(ICH_DI2L_MASK|ICH_DI1L_MASK);
2225 if (pcm) {
2226 tmp |= ICH_SE; /* steer enable for multiple SDINs */
2227 tmp |= chip->ac97_sdin[0] << ICH_DI1L_SHIFT;
2228 for (i = 1; i < 4; i++) {
2229 if (pcm->r[0].codec[i]) {
2230 tmp |= chip->ac97_sdin[pcm->r[0].codec[1]->num] << ICH_DI2L_SHIFT;
2231 break;
2232 }
2233 }
2234 } else {
2235 tmp &= ~ICH_SE; /* steer disable */
2236 }
2237 iputbyte(chip, ICHREG(SDM), tmp);
2238 }
2239 if (pbus->pcms[0].r[0].slots & (1 << AC97_SLOT_PCM_SLEFT)) {
2240 chip->multi4 = 1;
2241 if (pbus->pcms[0].r[0].slots & (1 << AC97_SLOT_LFE)) {
2242 chip->multi6 = 1;
2243 if (chip->ac97[0]->flags & AC97_HAS_8CH)
2244 chip->multi8 = 1;
2245 }
2246 }
2247 if (pbus->pcms[0].r[1].rslots[0]) {
2248 chip->dra = 1;
2249 }
2250 if (chip->device_type == DEVICE_INTEL_ICH4) {
2251 if ((igetdword(chip, ICHREG(GLOB_STA)) & ICH_SAMPLE_CAP) == ICH_SAMPLE_16_20)
2252 chip->smp20bit = 1;
2253 }
2254 if (chip->device_type == DEVICE_NFORCE && !spdif_aclink) {
2255 /* 48kHz only */
2256 chip->ichd[chip->spdif_idx].pcm->rates = SNDRV_PCM_RATE_48000;
2257 }
2258 if (chip->device_type == DEVICE_INTEL_ICH4 && !spdif_aclink) {
2259 /* use slot 10/11 for SPDIF */
2260 u32 val;
2261 val = igetdword(chip, ICHREG(GLOB_CNT)) & ~ICH_PCM_SPDIF_MASK;
2262 val |= ICH_PCM_SPDIF_1011;
2263 iputdword(chip, ICHREG(GLOB_CNT), val);
2264 snd_ac97_update_bits(chip->ac97[0], AC97_EXTENDED_STATUS, 0x03 << 4, 0x03 << 4);
2265 }
2266 chip->in_ac97_init = 0;
2267 return 0;
2268
2269 __err:
2270 /* clear the cold-reset bit for the next chance */
2271 if (chip->device_type != DEVICE_ALI)
2272 iputdword(chip, ICHREG(GLOB_CNT),
2273 igetdword(chip, ICHREG(GLOB_CNT)) & ~ICH_AC97COLD);
2274 return err;
2275}
2276
2277
2278/*
2279 *
2280 */
2281
2282static void do_ali_reset(struct intel8x0 *chip)
2283{
2284 iputdword(chip, ICHREG(ALI_SCR), ICH_ALI_SC_RESET);
2285 iputdword(chip, ICHREG(ALI_FIFOCR1), 0x83838383);
2286 iputdword(chip, ICHREG(ALI_FIFOCR2), 0x83838383);
2287 iputdword(chip, ICHREG(ALI_FIFOCR3), 0x83838383);
2288 iputdword(chip, ICHREG(ALI_INTERFACECR),
2289 ICH_ALI_IF_PI|ICH_ALI_IF_PO);
2290 iputdword(chip, ICHREG(ALI_INTERRUPTCR), 0x00000000);
2291 iputdword(chip, ICHREG(ALI_INTERRUPTSR), 0x00000000);
2292}
2293
2294static int snd_intel8x0_ich_chip_init(struct intel8x0 *chip, int probing)
2295{
2296 unsigned long end_time;
2297 unsigned int cnt, status, nstatus;
2298
2299 /* put logic to right state */
2300 /* first clear status bits */
2301 status = ICH_RCS | ICH_MCINT | ICH_POINT | ICH_PIINT;
2302 if (chip->device_type == DEVICE_NFORCE)
2303 status |= ICH_NVSPINT;
2304 cnt = igetdword(chip, ICHREG(GLOB_STA));
2305 iputdword(chip, ICHREG(GLOB_STA), cnt & status);
2306
2307 /* ACLink on, 2 channels */
2308 cnt = igetdword(chip, ICHREG(GLOB_CNT));
2309 cnt &= ~(ICH_ACLINK | ICH_PCM_246_MASK);
2310#ifdef CONFIG_SND_AC97_POWER_SAVE
2311 /* do cold reset - the full ac97 powerdown may leave the controller
2312 * in a warm state but actually it cannot communicate with the codec.
2313 */
2314 iputdword(chip, ICHREG(GLOB_CNT), cnt & ~ICH_AC97COLD);
2315 cnt = igetdword(chip, ICHREG(GLOB_CNT));
2316 udelay(10);
2317 iputdword(chip, ICHREG(GLOB_CNT), cnt | ICH_AC97COLD);
2318 msleep(1);
2319#else
2320 /* finish cold or do warm reset */
2321 cnt |= (cnt & ICH_AC97COLD) == 0 ? ICH_AC97COLD : ICH_AC97WARM;
2322 iputdword(chip, ICHREG(GLOB_CNT), cnt);
2323 end_time = (jiffies + (HZ / 4)) + 1;
2324 do {
2325 if ((igetdword(chip, ICHREG(GLOB_CNT)) & ICH_AC97WARM) == 0)
2326 goto __ok;
2327 schedule_timeout_uninterruptible(1);
2328 } while (time_after_eq(end_time, jiffies));
2329 snd_printk(KERN_ERR "AC'97 warm reset still in progress? [0x%x]\n",
2330 igetdword(chip, ICHREG(GLOB_CNT)));
2331 return -EIO;
2332
2333 __ok:
2334#endif
2335 if (probing) {
2336 /* wait for any codec ready status.
2337 * Once it becomes ready it should remain ready
2338 * as long as we do not disable the ac97 link.
2339 */
2340 end_time = jiffies + HZ;
2341 do {
2342 status = igetdword(chip, ICHREG(GLOB_STA)) &
2343 chip->codec_isr_bits;
2344 if (status)
2345 break;
2346 schedule_timeout_uninterruptible(1);
2347 } while (time_after_eq(end_time, jiffies));
2348 if (! status) {
2349 /* no codec is found */
2350 snd_printk(KERN_ERR "codec_ready: codec is not ready [0x%x]\n",
2351 igetdword(chip, ICHREG(GLOB_STA)));
2352 return -EIO;
2353 }
2354
2355 /* wait for other codecs ready status. */
2356 end_time = jiffies + HZ / 4;
2357 while (status != chip->codec_isr_bits &&
2358 time_after_eq(end_time, jiffies)) {
2359 schedule_timeout_uninterruptible(1);
2360 status |= igetdword(chip, ICHREG(GLOB_STA)) &
2361 chip->codec_isr_bits;
2362 }
2363
2364 } else {
2365 /* resume phase */
2366 int i;
2367 status = 0;
2368 for (i = 0; i < chip->ncodecs; i++)
2369 if (chip->ac97[i])
2370 status |= chip->codec_bit[chip->ac97_sdin[i]];
2371 /* wait until all the probed codecs are ready */
2372 end_time = jiffies + HZ;
2373 do {
2374 nstatus = igetdword(chip, ICHREG(GLOB_STA)) &
2375 chip->codec_isr_bits;
2376 if (status == nstatus)
2377 break;
2378 schedule_timeout_uninterruptible(1);
2379 } while (time_after_eq(end_time, jiffies));
2380 }
2381
2382 if (chip->device_type == DEVICE_SIS) {
2383 /* unmute the output on SIS7012 */
2384 iputword(chip, 0x4c, igetword(chip, 0x4c) | 1);
2385 }
2386 if (chip->device_type == DEVICE_NFORCE && !spdif_aclink) {
2387 /* enable SPDIF interrupt */
2388 unsigned int val;
2389 pci_read_config_dword(chip->pci, 0x4c, &val);
2390 val |= 0x1000000;
2391 pci_write_config_dword(chip->pci, 0x4c, val);
2392 }
2393 return 0;
2394}
2395
2396static int snd_intel8x0_ali_chip_init(struct intel8x0 *chip, int probing)
2397{
2398 u32 reg;
2399 int i = 0;
2400
2401 reg = igetdword(chip, ICHREG(ALI_SCR));
2402 if ((reg & 2) == 0) /* Cold required */
2403 reg |= 2;
2404 else
2405 reg |= 1; /* Warm */
2406 reg &= ~0x80000000; /* ACLink on */
2407 iputdword(chip, ICHREG(ALI_SCR), reg);
2408
2409 for (i = 0; i < HZ / 2; i++) {
2410 if (! (igetdword(chip, ICHREG(ALI_INTERRUPTSR)) & ALI_INT_GPIO))
2411 goto __ok;
2412 schedule_timeout_uninterruptible(1);
2413 }
2414 snd_printk(KERN_ERR "AC'97 reset failed.\n");
2415 if (probing)
2416 return -EIO;
2417
2418 __ok:
2419 for (i = 0; i < HZ / 2; i++) {
2420 reg = igetdword(chip, ICHREG(ALI_RTSR));
2421 if (reg & 0x80) /* primary codec */
2422 break;
2423 iputdword(chip, ICHREG(ALI_RTSR), reg | 0x80);
2424 schedule_timeout_uninterruptible(1);
2425 }
2426
2427 do_ali_reset(chip);
2428 return 0;
2429}
2430
2431static int snd_intel8x0_chip_init(struct intel8x0 *chip, int probing)
2432{
2433 unsigned int i, timeout;
2434 int err;
2435
2436 if (chip->device_type != DEVICE_ALI) {
2437 if ((err = snd_intel8x0_ich_chip_init(chip, probing)) < 0)
2438 return err;
2439 iagetword(chip, 0); /* clear semaphore flag */
2440 } else {
2441 if ((err = snd_intel8x0_ali_chip_init(chip, probing)) < 0)
2442 return err;
2443 }
2444
2445 /* disable interrupts */
2446 for (i = 0; i < chip->bdbars_count; i++)
2447 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, 0x00);
2448 /* reset channels */
2449 for (i = 0; i < chip->bdbars_count; i++)
2450 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, ICH_RESETREGS);
2451 for (i = 0; i < chip->bdbars_count; i++) {
2452 timeout = 100000;
2453 while (--timeout != 0) {
2454 if ((igetbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset) & ICH_RESETREGS) == 0)
2455 break;
2456 }
2457 if (timeout == 0)
2458 printk(KERN_ERR "intel8x0: reset of registers failed?\n");
2459 }
2460 /* initialize Buffer Descriptor Lists */
2461 for (i = 0; i < chip->bdbars_count; i++)
2462 iputdword(chip, ICH_REG_OFF_BDBAR + chip->ichd[i].reg_offset,
2463 chip->ichd[i].bdbar_addr);
2464 return 0;
2465}
2466
2467static int snd_intel8x0_free(struct intel8x0 *chip)
2468{
2469 unsigned int i;
2470
2471 if (chip->irq < 0)
2472 goto __hw_end;
2473 /* disable interrupts */
2474 for (i = 0; i < chip->bdbars_count; i++)
2475 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, 0x00);
2476 /* reset channels */
2477 for (i = 0; i < chip->bdbars_count; i++)
2478 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, ICH_RESETREGS);
2479 if (chip->device_type == DEVICE_NFORCE && !spdif_aclink) {
2480 /* stop the spdif interrupt */
2481 unsigned int val;
2482 pci_read_config_dword(chip->pci, 0x4c, &val);
2483 val &= ~0x1000000;
2484 pci_write_config_dword(chip->pci, 0x4c, val);
2485 }
2486 /* --- */
2487
2488 __hw_end:
2489 if (chip->irq >= 0)
2490 free_irq(chip->irq, chip);
2491 if (chip->bdbars.area) {
2492 if (chip->fix_nocache)
2493 fill_nocache(chip->bdbars.area, chip->bdbars.bytes, 0);
2494 snd_dma_free_pages(&chip->bdbars);
2495 }
2496 if (chip->addr)
2497 pci_iounmap(chip->pci, chip->addr);
2498 if (chip->bmaddr)
2499 pci_iounmap(chip->pci, chip->bmaddr);
2500 pci_release_regions(chip->pci);
2501 pci_disable_device(chip->pci);
2502 kfree(chip);
2503 return 0;
2504}
2505
2506#ifdef CONFIG_PM
2507/*
2508 * power management
2509 */
2510static int intel8x0_suspend(struct pci_dev *pci, pm_message_t state)
2511{
2512 struct snd_card *card = pci_get_drvdata(pci);
2513 struct intel8x0 *chip = card->private_data;
2514 int i;
2515
2516 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
2517 for (i = 0; i < chip->pcm_devs; i++)
2518 snd_pcm_suspend_all(chip->pcm[i]);
2519 /* clear nocache */
2520 if (chip->fix_nocache) {
2521 for (i = 0; i < chip->bdbars_count; i++) {
2522 struct ichdev *ichdev = &chip->ichd[i];
2523 if (ichdev->substream && ichdev->page_attr_changed) {
2524 struct snd_pcm_runtime *runtime = ichdev->substream->runtime;
2525 if (runtime->dma_area)
2526 fill_nocache(runtime->dma_area, runtime->dma_bytes, 0);
2527 }
2528 }
2529 }
2530 for (i = 0; i < chip->ncodecs; i++)
2531 snd_ac97_suspend(chip->ac97[i]);
2532 if (chip->device_type == DEVICE_INTEL_ICH4)
2533 chip->sdm_saved = igetbyte(chip, ICHREG(SDM));
2534
2535 if (chip->irq >= 0) {
2536 free_irq(chip->irq, chip);
2537 chip->irq = -1;
2538 }
2539 pci_disable_device(pci);
2540 pci_save_state(pci);
2541 /* The call below may disable built-in speaker on some laptops
2542 * after S2RAM. So, don't touch it.
2543 */
2544 /* pci_set_power_state(pci, pci_choose_state(pci, state)); */
2545 return 0;
2546}
2547
2548static int intel8x0_resume(struct pci_dev *pci)
2549{
2550 struct snd_card *card = pci_get_drvdata(pci);
2551 struct intel8x0 *chip = card->private_data;
2552 int i;
2553
2554 pci_set_power_state(pci, PCI_D0);
2555 pci_restore_state(pci);
2556 if (pci_enable_device(pci) < 0) {
2557 printk(KERN_ERR "intel8x0: pci_enable_device failed, "
2558 "disabling device\n");
2559 snd_card_disconnect(card);
2560 return -EIO;
2561 }
2562 pci_set_master(pci);
2563 snd_intel8x0_chip_init(chip, 0);
2564 if (request_irq(pci->irq, snd_intel8x0_interrupt,
2565 IRQF_SHARED, card->shortname, chip)) {
2566 printk(KERN_ERR "intel8x0: unable to grab IRQ %d, "
2567 "disabling device\n", pci->irq);
2568 snd_card_disconnect(card);
2569 return -EIO;
2570 }
2571 chip->irq = pci->irq;
2572 synchronize_irq(chip->irq);
2573
2574 /* re-initialize mixer stuff */
2575 if (chip->device_type == DEVICE_INTEL_ICH4 && !spdif_aclink) {
2576 /* enable separate SDINs for ICH4 */
2577 iputbyte(chip, ICHREG(SDM), chip->sdm_saved);
2578 /* use slot 10/11 for SPDIF */
2579 iputdword(chip, ICHREG(GLOB_CNT),
2580 (igetdword(chip, ICHREG(GLOB_CNT)) & ~ICH_PCM_SPDIF_MASK) |
2581 ICH_PCM_SPDIF_1011);
2582 }
2583
2584 /* refill nocache */
2585 if (chip->fix_nocache)
2586 fill_nocache(chip->bdbars.area, chip->bdbars.bytes, 1);
2587
2588 for (i = 0; i < chip->ncodecs; i++)
2589 snd_ac97_resume(chip->ac97[i]);
2590
2591 /* refill nocache */
2592 if (chip->fix_nocache) {
2593 for (i = 0; i < chip->bdbars_count; i++) {
2594 struct ichdev *ichdev = &chip->ichd[i];
2595 if (ichdev->substream && ichdev->page_attr_changed) {
2596 struct snd_pcm_runtime *runtime = ichdev->substream->runtime;
2597 if (runtime->dma_area)
2598 fill_nocache(runtime->dma_area, runtime->dma_bytes, 1);
2599 }
2600 }
2601 }
2602
2603 /* resume status */
2604 for (i = 0; i < chip->bdbars_count; i++) {
2605 struct ichdev *ichdev = &chip->ichd[i];
2606 unsigned long port = ichdev->reg_offset;
2607 if (! ichdev->substream || ! ichdev->suspended)
2608 continue;
2609 if (ichdev->ichd == ICHD_PCMOUT)
2610 snd_intel8x0_setup_pcm_out(chip, ichdev->substream->runtime);
2611 iputdword(chip, port + ICH_REG_OFF_BDBAR, ichdev->bdbar_addr);
2612 iputbyte(chip, port + ICH_REG_OFF_LVI, ichdev->lvi);
2613 iputbyte(chip, port + ICH_REG_OFF_CIV, ichdev->civ);
2614 iputbyte(chip, port + ichdev->roff_sr, ICH_FIFOE | ICH_BCIS | ICH_LVBCI);
2615 }
2616
2617 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
2618 return 0;
2619}
2620#endif /* CONFIG_PM */
2621
2622#define INTEL8X0_TESTBUF_SIZE 32768 /* enough large for one shot */
2623
2624static void __devinit intel8x0_measure_ac97_clock(struct intel8x0 *chip)
2625{
2626 struct snd_pcm_substream *subs;
2627 struct ichdev *ichdev;
2628 unsigned long port;
2629 unsigned long pos, t;
2630 struct timeval start_time, stop_time;
2631
2632 if (chip->ac97_bus->clock != 48000)
2633 return; /* specified in module option */
2634
2635 subs = chip->pcm[0]->streams[0].substream;
2636 if (! subs || subs->dma_buffer.bytes < INTEL8X0_TESTBUF_SIZE) {
2637 snd_printk(KERN_WARNING "no playback buffer allocated - aborting measure ac97 clock\n");
2638 return;
2639 }
2640 ichdev = &chip->ichd[ICHD_PCMOUT];
2641 ichdev->physbuf = subs->dma_buffer.addr;
2642 ichdev->size = chip->ichd[ICHD_PCMOUT].fragsize = INTEL8X0_TESTBUF_SIZE;
2643 ichdev->substream = NULL; /* don't process interrupts */
2644
2645 /* set rate */
2646 if (snd_ac97_set_rate(chip->ac97[0], AC97_PCM_FRONT_DAC_RATE, 48000) < 0) {
2647 snd_printk(KERN_ERR "cannot set ac97 rate: clock = %d\n", chip->ac97_bus->clock);
2648 return;
2649 }
2650 snd_intel8x0_setup_periods(chip, ichdev);
2651 port = ichdev->reg_offset;
2652 spin_lock_irq(&chip->reg_lock);
2653 chip->in_measurement = 1;
2654 /* trigger */
2655 if (chip->device_type != DEVICE_ALI)
2656 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_IOCE | ICH_STARTBM);
2657 else {
2658 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_IOCE);
2659 iputdword(chip, ICHREG(ALI_DMACR), 1 << ichdev->ali_slot);
2660 }
2661 do_gettimeofday(&start_time);
2662 spin_unlock_irq(&chip->reg_lock);
2663 msleep(50);
2664 spin_lock_irq(&chip->reg_lock);
2665 /* check the position */
2666 pos = ichdev->fragsize1;
2667 pos -= igetword(chip, ichdev->reg_offset + ichdev->roff_picb) << ichdev->pos_shift;
2668 pos += ichdev->position;
2669 chip->in_measurement = 0;
2670 do_gettimeofday(&stop_time);
2671 /* stop */
2672 if (chip->device_type == DEVICE_ALI) {
2673 iputdword(chip, ICHREG(ALI_DMACR), 1 << (ichdev->ali_slot + 16));
2674 iputbyte(chip, port + ICH_REG_OFF_CR, 0);
2675 while (igetbyte(chip, port + ICH_REG_OFF_CR))
2676 ;
2677 } else {
2678 iputbyte(chip, port + ICH_REG_OFF_CR, 0);
2679 while (!(igetbyte(chip, port + ichdev->roff_sr) & ICH_DCH))
2680 ;
2681 }
2682 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_RESETREGS);
2683 spin_unlock_irq(&chip->reg_lock);
2684
2685 t = stop_time.tv_sec - start_time.tv_sec;
2686 t *= 1000000;
2687 t += stop_time.tv_usec - start_time.tv_usec;
2688 printk(KERN_INFO "%s: measured %lu usecs\n", __func__, t);
2689 if (t == 0) {
2690 snd_printk(KERN_ERR "?? calculation error..\n");
2691 return;
2692 }
2693 pos = (pos / 4) * 1000;
2694 pos = (pos / t) * 1000 + ((pos % t) * 1000) / t;
2695 if (pos < 40000 || pos >= 60000)
2696 /* abnormal value. hw problem? */
2697 printk(KERN_INFO "intel8x0: measured clock %ld rejected\n", pos);
2698 else if (pos < 47500 || pos > 48500)
2699 /* not 48000Hz, tuning the clock.. */
2700 chip->ac97_bus->clock = (chip->ac97_bus->clock * 48000) / pos;
2701 printk(KERN_INFO "intel8x0: clocking to %d\n", chip->ac97_bus->clock);
2702 snd_ac97_update_power(chip->ac97[0], AC97_PCM_FRONT_DAC_RATE, 0);
2703}
2704
2705static struct snd_pci_quirk intel8x0_clock_list[] __devinitdata = {
2706 SND_PCI_QUIRK(0x0e11, 0x008a, "AD1885", 41000),
2707 SND_PCI_QUIRK(0x1028, 0x00be, "AD1885", 44100),
2708 SND_PCI_QUIRK(0x1028, 0x0177, "AD1980", 48000),
2709 SND_PCI_QUIRK(0x1028, 0x01ad, "AD1981B", 48000),
2710 SND_PCI_QUIRK(0x1043, 0x80f3, "AD1985", 48000),
2711 {0} /* terminator */
2712};
2713
2714static int __devinit intel8x0_in_clock_list(struct intel8x0 *chip)
2715{
2716 struct pci_dev *pci = chip->pci;
2717 const struct snd_pci_quirk *wl;
2718
2719 wl = snd_pci_quirk_lookup(pci, intel8x0_clock_list);
2720 if (!wl)
2721 return 0;
2722 printk(KERN_INFO "intel8x0: white list rate for %04x:%04x is %i\n",
2723 pci->subsystem_vendor, pci->subsystem_device, wl->value);
2724 chip->ac97_bus->clock = wl->value;
2725 return 1;
2726}
2727
2728#ifdef CONFIG_PROC_FS
2729static void snd_intel8x0_proc_read(struct snd_info_entry * entry,
2730 struct snd_info_buffer *buffer)
2731{
2732 struct intel8x0 *chip = entry->private_data;
2733 unsigned int tmp;
2734
2735 snd_iprintf(buffer, "Intel8x0\n\n");
2736 if (chip->device_type == DEVICE_ALI)
2737 return;
2738 tmp = igetdword(chip, ICHREG(GLOB_STA));
2739 snd_iprintf(buffer, "Global control : 0x%08x\n", igetdword(chip, ICHREG(GLOB_CNT)));
2740 snd_iprintf(buffer, "Global status : 0x%08x\n", tmp);
2741 if (chip->device_type == DEVICE_INTEL_ICH4)
2742 snd_iprintf(buffer, "SDM : 0x%08x\n", igetdword(chip, ICHREG(SDM)));
2743 snd_iprintf(buffer, "AC'97 codecs ready :");
2744 if (tmp & chip->codec_isr_bits) {
2745 int i;
2746 static const char *codecs[3] = {
2747 "primary", "secondary", "tertiary"
2748 };
2749 for (i = 0; i < chip->max_codecs; i++)
2750 if (tmp & chip->codec_bit[i])
2751 snd_iprintf(buffer, " %s", codecs[i]);
2752 } else
2753 snd_iprintf(buffer, " none");
2754 snd_iprintf(buffer, "\n");
2755 if (chip->device_type == DEVICE_INTEL_ICH4 ||
2756 chip->device_type == DEVICE_SIS)
2757 snd_iprintf(buffer, "AC'97 codecs SDIN : %i %i %i\n",
2758 chip->ac97_sdin[0],
2759 chip->ac97_sdin[1],
2760 chip->ac97_sdin[2]);
2761}
2762
2763static void __devinit snd_intel8x0_proc_init(struct intel8x0 * chip)
2764{
2765 struct snd_info_entry *entry;
2766
2767 if (! snd_card_proc_new(chip->card, "intel8x0", &entry))
2768 snd_info_set_text_ops(entry, chip, snd_intel8x0_proc_read);
2769}
2770#else
2771#define snd_intel8x0_proc_init(x)
2772#endif
2773
2774static int snd_intel8x0_dev_free(struct snd_device *device)
2775{
2776 struct intel8x0 *chip = device->device_data;
2777 return snd_intel8x0_free(chip);
2778}
2779
2780struct ich_reg_info {
2781 unsigned int int_sta_mask;
2782 unsigned int offset;
2783};
2784
2785static unsigned int ich_codec_bits[3] = {
2786 ICH_PCR, ICH_SCR, ICH_TCR
2787};
2788static unsigned int sis_codec_bits[3] = {
2789 ICH_PCR, ICH_SCR, ICH_SIS_TCR
2790};
2791
2792static int __devinit snd_intel8x0_create(struct snd_card *card,
2793 struct pci_dev *pci,
2794 unsigned long device_type,
2795 struct intel8x0 ** r_intel8x0)
2796{
2797 struct intel8x0 *chip;
2798 int err;
2799 unsigned int i;
2800 unsigned int int_sta_masks;
2801 struct ichdev *ichdev;
2802 static struct snd_device_ops ops = {
2803 .dev_free = snd_intel8x0_dev_free,
2804 };
2805
2806 static unsigned int bdbars[] = {
2807 3, /* DEVICE_INTEL */
2808 6, /* DEVICE_INTEL_ICH4 */
2809 3, /* DEVICE_SIS */
2810 6, /* DEVICE_ALI */
2811 4, /* DEVICE_NFORCE */
2812 };
2813 static struct ich_reg_info intel_regs[6] = {
2814 { ICH_PIINT, 0 },
2815 { ICH_POINT, 0x10 },
2816 { ICH_MCINT, 0x20 },
2817 { ICH_M2INT, 0x40 },
2818 { ICH_P2INT, 0x50 },
2819 { ICH_SPINT, 0x60 },
2820 };
2821 static struct ich_reg_info nforce_regs[4] = {
2822 { ICH_PIINT, 0 },
2823 { ICH_POINT, 0x10 },
2824 { ICH_MCINT, 0x20 },
2825 { ICH_NVSPINT, 0x70 },
2826 };
2827 static struct ich_reg_info ali_regs[6] = {
2828 { ALI_INT_PCMIN, 0x40 },
2829 { ALI_INT_PCMOUT, 0x50 },
2830 { ALI_INT_MICIN, 0x60 },
2831 { ALI_INT_CODECSPDIFOUT, 0x70 },
2832 { ALI_INT_SPDIFIN, 0xa0 },
2833 { ALI_INT_SPDIFOUT, 0xb0 },
2834 };
2835 struct ich_reg_info *tbl;
2836
2837 *r_intel8x0 = NULL;
2838
2839 if ((err = pci_enable_device(pci)) < 0)
2840 return err;
2841
2842 chip = kzalloc(sizeof(*chip), GFP_KERNEL);
2843 if (chip == NULL) {
2844 pci_disable_device(pci);
2845 return -ENOMEM;
2846 }
2847 spin_lock_init(&chip->reg_lock);
2848 chip->device_type = device_type;
2849 chip->card = card;
2850 chip->pci = pci;
2851 chip->irq = -1;
2852
2853 /* module parameters */
2854 chip->buggy_irq = buggy_irq;
2855 chip->buggy_semaphore = buggy_semaphore;
2856 if (xbox)
2857 chip->xbox = 1;
2858
2859 if (pci->vendor == PCI_VENDOR_ID_INTEL &&
2860 pci->device == PCI_DEVICE_ID_INTEL_440MX)
2861 chip->fix_nocache = 1; /* enable workaround */
2862
2863 if ((err = pci_request_regions(pci, card->shortname)) < 0) {
2864 kfree(chip);
2865 pci_disable_device(pci);
2866 return err;
2867 }
2868
2869 if (device_type == DEVICE_ALI) {
2870 /* ALI5455 has no ac97 region */
2871 chip->bmaddr = pci_iomap(pci, 0, 0);
2872 goto port_inited;
2873 }
2874
2875 if (pci_resource_flags(pci, 2) & IORESOURCE_MEM) /* ICH4 and Nforce */
2876 chip->addr = pci_iomap(pci, 2, 0);
2877 else
2878 chip->addr = pci_iomap(pci, 0, 0);
2879 if (!chip->addr) {
2880 snd_printk(KERN_ERR "AC'97 space ioremap problem\n");
2881 snd_intel8x0_free(chip);
2882 return -EIO;
2883 }
2884 if (pci_resource_flags(pci, 3) & IORESOURCE_MEM) /* ICH4 */
2885 chip->bmaddr = pci_iomap(pci, 3, 0);
2886 else
2887 chip->bmaddr = pci_iomap(pci, 1, 0);
2888 if (!chip->bmaddr) {
2889 snd_printk(KERN_ERR "Controller space ioremap problem\n");
2890 snd_intel8x0_free(chip);
2891 return -EIO;
2892 }
2893
2894 port_inited:
2895 chip->bdbars_count = bdbars[device_type];
2896
2897 /* initialize offsets */
2898 switch (device_type) {
2899 case DEVICE_NFORCE:
2900 tbl = nforce_regs;
2901 break;
2902 case DEVICE_ALI:
2903 tbl = ali_regs;
2904 break;
2905 default:
2906 tbl = intel_regs;
2907 break;
2908 }
2909 for (i = 0; i < chip->bdbars_count; i++) {
2910 ichdev = &chip->ichd[i];
2911 ichdev->ichd = i;
2912 ichdev->reg_offset = tbl[i].offset;
2913 ichdev->int_sta_mask = tbl[i].int_sta_mask;
2914 if (device_type == DEVICE_SIS) {
2915 /* SiS 7012 swaps the registers */
2916 ichdev->roff_sr = ICH_REG_OFF_PICB;
2917 ichdev->roff_picb = ICH_REG_OFF_SR;
2918 } else {
2919 ichdev->roff_sr = ICH_REG_OFF_SR;
2920 ichdev->roff_picb = ICH_REG_OFF_PICB;
2921 }
2922 if (device_type == DEVICE_ALI)
2923 ichdev->ali_slot = (ichdev->reg_offset - 0x40) / 0x10;
2924 /* SIS7012 handles the pcm data in bytes, others are in samples */
2925 ichdev->pos_shift = (device_type == DEVICE_SIS) ? 0 : 1;
2926 }
2927
2928 /* allocate buffer descriptor lists */
2929 /* the start of each lists must be aligned to 8 bytes */
2930 if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(pci),
2931 chip->bdbars_count * sizeof(u32) * ICH_MAX_FRAGS * 2,
2932 &chip->bdbars) < 0) {
2933 snd_intel8x0_free(chip);
2934 snd_printk(KERN_ERR "intel8x0: cannot allocate buffer descriptors\n");
2935 return -ENOMEM;
2936 }
2937 /* tables must be aligned to 8 bytes here, but the kernel pages
2938 are much bigger, so we don't care (on i386) */
2939 /* workaround for 440MX */
2940 if (chip->fix_nocache)
2941 fill_nocache(chip->bdbars.area, chip->bdbars.bytes, 1);
2942 int_sta_masks = 0;
2943 for (i = 0; i < chip->bdbars_count; i++) {
2944 ichdev = &chip->ichd[i];
2945 ichdev->bdbar = ((u32 *)chip->bdbars.area) +
2946 (i * ICH_MAX_FRAGS * 2);
2947 ichdev->bdbar_addr = chip->bdbars.addr +
2948 (i * sizeof(u32) * ICH_MAX_FRAGS * 2);
2949 int_sta_masks |= ichdev->int_sta_mask;
2950 }
2951 chip->int_sta_reg = device_type == DEVICE_ALI ?
2952 ICH_REG_ALI_INTERRUPTSR : ICH_REG_GLOB_STA;
2953 chip->int_sta_mask = int_sta_masks;
2954
2955 pci_set_master(pci);
2956
2957 switch(chip->device_type) {
2958 case DEVICE_INTEL_ICH4:
2959 /* ICH4 can have three codecs */
2960 chip->max_codecs = 3;
2961 chip->codec_bit = ich_codec_bits;
2962 chip->codec_ready_bits = ICH_PRI | ICH_SRI | ICH_TRI;
2963 break;
2964 case DEVICE_SIS:
2965 /* recent SIS7012 can have three codecs */
2966 chip->max_codecs = 3;
2967 chip->codec_bit = sis_codec_bits;
2968 chip->codec_ready_bits = ICH_PRI | ICH_SRI | ICH_SIS_TRI;
2969 break;
2970 default:
2971 /* others up to two codecs */
2972 chip->max_codecs = 2;
2973 chip->codec_bit = ich_codec_bits;
2974 chip->codec_ready_bits = ICH_PRI | ICH_SRI;
2975 break;
2976 }
2977 for (i = 0; i < chip->max_codecs; i++)
2978 chip->codec_isr_bits |= chip->codec_bit[i];
2979
2980 if ((err = snd_intel8x0_chip_init(chip, 1)) < 0) {
2981 snd_intel8x0_free(chip);
2982 return err;
2983 }
2984
2985 /* request irq after initializaing int_sta_mask, etc */
2986 if (request_irq(pci->irq, snd_intel8x0_interrupt,
2987 IRQF_SHARED, card->shortname, chip)) {
2988 snd_printk(KERN_ERR "unable to grab IRQ %d\n", pci->irq);
2989 snd_intel8x0_free(chip);
2990 return -EBUSY;
2991 }
2992 chip->irq = pci->irq;
2993
2994 if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) < 0) {
2995 snd_intel8x0_free(chip);
2996 return err;
2997 }
2998
2999 snd_card_set_dev(card, &pci->dev);
3000
3001 *r_intel8x0 = chip;
3002 return 0;
3003}
3004
3005static struct shortname_table {
3006 unsigned int id;
3007 const char *s;
3008} shortnames[] __devinitdata = {
3009 { PCI_DEVICE_ID_INTEL_82801AA_5, "Intel 82801AA-ICH" },
3010 { PCI_DEVICE_ID_INTEL_82801AB_5, "Intel 82901AB-ICH0" },
3011 { PCI_DEVICE_ID_INTEL_82801BA_4, "Intel 82801BA-ICH2" },
3012 { PCI_DEVICE_ID_INTEL_440MX, "Intel 440MX" },
3013 { PCI_DEVICE_ID_INTEL_82801CA_5, "Intel 82801CA-ICH3" },
3014 { PCI_DEVICE_ID_INTEL_82801DB_5, "Intel 82801DB-ICH4" },
3015 { PCI_DEVICE_ID_INTEL_82801EB_5, "Intel ICH5" },
3016 { PCI_DEVICE_ID_INTEL_ESB_5, "Intel 6300ESB" },
3017 { PCI_DEVICE_ID_INTEL_ICH6_18, "Intel ICH6" },
3018 { PCI_DEVICE_ID_INTEL_ICH7_20, "Intel ICH7" },
3019 { PCI_DEVICE_ID_INTEL_ESB2_14, "Intel ESB2" },
3020 { PCI_DEVICE_ID_SI_7012, "SiS SI7012" },
3021 { PCI_DEVICE_ID_NVIDIA_MCP1_AUDIO, "NVidia nForce" },
3022 { PCI_DEVICE_ID_NVIDIA_MCP2_AUDIO, "NVidia nForce2" },
3023 { PCI_DEVICE_ID_NVIDIA_MCP3_AUDIO, "NVidia nForce3" },
3024 { PCI_DEVICE_ID_NVIDIA_CK8S_AUDIO, "NVidia CK8S" },
3025 { PCI_DEVICE_ID_NVIDIA_CK804_AUDIO, "NVidia CK804" },
3026 { PCI_DEVICE_ID_NVIDIA_CK8_AUDIO, "NVidia CK8" },
3027 { 0x003a, "NVidia MCP04" },
3028 { 0x746d, "AMD AMD8111" },
3029 { 0x7445, "AMD AMD768" },
3030 { 0x5455, "ALi M5455" },
3031 { 0, NULL },
3032};
3033
3034static struct snd_pci_quirk spdif_aclink_defaults[] __devinitdata = {
3035 SND_PCI_QUIRK(0x147b, 0x1c1a, "ASUS KN8", 1),
3036 {0} /* end */
3037};
3038
3039/* look up white/black list for SPDIF over ac-link */
3040static int __devinit check_default_spdif_aclink(struct pci_dev *pci)
3041{
3042#ifndef TARGET_OS2
3043 const struct snd_pci_quirk *w;
3044
3045 w = snd_pci_quirk_lookup(pci, spdif_aclink_defaults);
3046 if (w) {
3047 if (w->value)
3048 snd_printdd(KERN_INFO "intel8x0: Using SPDIF over "
3049 "AC-Link for %s\n", w->name);
3050 else
3051 snd_printdd(KERN_INFO "intel8x0: Using integrated "
3052 "SPDIF DMA for %s\n", w->name);
3053 return w->value;
3054 }
3055#endif
3056 return 0;
3057}
3058
3059static int __devinit snd_intel8x0_probe(struct pci_dev *pci,
3060 const struct pci_device_id *pci_id)
3061{
3062 struct snd_card *card;
3063 struct intel8x0 *chip;
3064 int err;
3065 struct shortname_table *name;
3066
3067 err = snd_card_create(index, id, THIS_MODULE, 0, &card);
3068 if (err < 0)
3069 return err;
3070
3071 if (spdif_aclink < 0)
3072 spdif_aclink = check_default_spdif_aclink(pci);
3073
3074 strcpy(card->driver, "ICH");
3075 if (!spdif_aclink) {
3076 switch (pci_id->driver_data) {
3077 case DEVICE_NFORCE:
3078 strcpy(card->driver, "NFORCE");
3079 break;
3080 case DEVICE_INTEL_ICH4:
3081 strcpy(card->driver, "ICH4");
3082 }
3083 }
3084
3085 strcpy(card->shortname, "Intel ICH");
3086 for (name = shortnames; name->id; name++) {
3087 if (pci->device == name->id) {
3088 strcpy(card->shortname, name->s);
3089 break;
3090 }
3091 }
3092
3093 if (buggy_irq < 0) {
3094 /* some Nforce[2] and ICH boards have problems with IRQ handling.
3095 * Needs to return IRQ_HANDLED for unknown irqs.
3096 */
3097 if (pci_id->driver_data == DEVICE_NFORCE)
3098 buggy_irq = 1;
3099 else
3100 buggy_irq = 0;
3101 }
3102
3103 if ((err = snd_intel8x0_create(card, pci, pci_id->driver_data,
3104 &chip)) < 0) {
3105 snd_card_free(card);
3106 return err;
3107 }
3108 card->private_data = chip;
3109
3110 if ((err = snd_intel8x0_mixer(chip, ac97_clock, ac97_quirk)) < 0) {
3111 snd_card_free(card);
3112 return err;
3113 }
3114 if ((err = snd_intel8x0_pcm(chip)) < 0) {
3115 snd_card_free(card);
3116 return err;
3117 }
3118
3119 snd_intel8x0_proc_init(chip);
3120
3121 snprintf(card->longname, sizeof(card->longname),
3122 "%s with %s at irq %i", card->shortname,
3123 snd_ac97_get_short_name(chip->ac97[0]), chip->irq);
3124
3125 if (ac97_clock == 0 || ac97_clock == 1) {
3126 if (ac97_clock == 0) {
3127 if (intel8x0_in_clock_list(chip) == 0)
3128 intel8x0_measure_ac97_clock(chip);
3129 } else {
3130 intel8x0_measure_ac97_clock(chip);
3131 }
3132 }
3133
3134 if ((err = snd_card_register(card)) < 0) {
3135 snd_card_free(card);
3136 return err;
3137 }
3138 pci_set_drvdata(pci, card);
3139 return 0;
3140}
3141
3142static void __devexit snd_intel8x0_remove(struct pci_dev *pci)
3143{
3144 snd_card_free(pci_get_drvdata(pci));
3145 pci_set_drvdata(pci, NULL);
3146}
3147
3148static struct pci_driver driver = {
3149 .name = "Intel ICH",
3150 .id_table = snd_intel8x0_ids,
3151 .probe = snd_intel8x0_probe,
3152 .remove = __devexit_p(snd_intel8x0_remove),
3153#ifdef CONFIG_PM
3154 .suspend = intel8x0_suspend,
3155 .resume = intel8x0_resume,
3156#endif
3157};
3158
3159
3160static int __init alsa_card_intel8x0_init(void)
3161{
3162 return pci_register_driver(&driver);
3163}
3164
3165static void __exit alsa_card_intel8x0_exit(void)
3166{
3167 pci_unregister_driver(&driver);
3168}
3169
3170module_init(alsa_card_intel8x0_init)
3171module_exit(alsa_card_intel8x0_exit)
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