source: GPL/trunk/alsa-kernel/pci/intel8x0.c@ 445

Last change on this file since 445 was 445, checked in by Paul Smedley, 16 years ago

More code tidyups, remove some unnecessary #ifndef TARGET_OS2 by adding some more stub functions
File size: 93.5 KB
Line 
1/*
2 * ALSA driver for Intel ICH (i8x0) chipsets
3 *
4 * Copyright (c) 2000 Jaroslav Kysela <perex@perex.cz>
5 *
6 *
7 * This code also contains alpha support for SiS 735 chipsets provided
8 * by Mike Pieper <mptei@users.sourceforge.net>. We have no datasheet
9 * for SiS735, so the code is not fully functional.
10 *
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
25
26 *
27 */
28
29#include <asm/io.h>
30#include <linux/delay.h>
31#include <linux/interrupt.h>
32#include <linux/init.h>
33#include <linux/pci.h>
34#include <linux/slab.h>
35#include <linux/moduleparam.h>
36#include <sound/core.h>
37#include <sound/pcm.h>
38#include <sound/ac97_codec.h>
39#include <sound/info.h>
40#include <sound/initval.h>
41/* for 440MX workaround */
42#include <asm/pgtable.h>
43#include <asm/cacheflush.h>
44
45MODULE_AUTHOR("Jaroslav Kysela <perex@perex.cz>");
46MODULE_DESCRIPTION("Intel 82801AA,82901AB,i810,i820,i830,i840,i845,MX440; SiS 7012; Ali 5455");
47MODULE_LICENSE("GPL");
48MODULE_SUPPORTED_DEVICE("{{Intel,82801AA-ICH},"
49 "{Intel,82901AB-ICH0},"
50 "{Intel,82801BA-ICH2},"
51 "{Intel,82801CA-ICH3},"
52 "{Intel,82801DB-ICH4},"
53 "{Intel,ICH5},"
54 "{Intel,ICH6},"
55 "{Intel,ICH7},"
56 "{Intel,6300ESB},"
57 "{Intel,ESB2},"
58 "{Intel,MX440},"
59 "{SiS,SI7012},"
60 "{NVidia,nForce Audio},"
61 "{NVidia,nForce2 Audio},"
62 "{NVidia,nForce3 Audio},"
63 "{NVidia,MCP04},"
64 "{NVidia,MCP501},"
65 "{NVidia,CK804},"
66 "{NVidia,CK8},"
67 "{NVidia,CK8S},"
68 "{AMD,AMD768},"
69 "{AMD,AMD8111},"
70 "{ALI,M5455}}");
71
72static int index = SNDRV_DEFAULT_IDX1; /* Index 0-MAX */
73static char *id = SNDRV_DEFAULT_STR1; /* ID for this card */
74static int ac97_clock;
75static char *ac97_quirk;
76static int buggy_semaphore;
77static int buggy_irq = -1; /* auto-check */
78static int xbox;
79static int spdif_aclink = -1;
80
81module_param(index, int, 0444);
82MODULE_PARM_DESC(index, "Index value for Intel i8x0 soundcard.");
83module_param(id, charp, 0444);
84MODULE_PARM_DESC(id, "ID string for Intel i8x0 soundcard.");
85module_param(ac97_clock, int, 0444);
86MODULE_PARM_DESC(ac97_clock, "AC'97 codec clock (0 = whitelist + auto-detect, 1 = force autodetect).");
87module_param(ac97_quirk, charp, 0444);
88MODULE_PARM_DESC(ac97_quirk, "AC'97 workaround for strange hardware.");
89module_param(buggy_semaphore, bool, 0444);
90MODULE_PARM_DESC(buggy_semaphore, "Enable workaround for hardwares with problematic codec semaphores.");
91module_param(buggy_irq, bool, 0444);
92MODULE_PARM_DESC(buggy_irq, "Enable workaround for buggy interrupts on some motherboards.");
93module_param(xbox, bool, 0444);
94MODULE_PARM_DESC(xbox, "Set to 1 for Xbox, if you have problems with the AC'97 codec detection.");
95module_param(spdif_aclink, int, 0444);
96MODULE_PARM_DESC(spdif_aclink, "S/PDIF over AC-link.");
97
98/* just for backward compatibility */
99static int enable;
100module_param(enable, bool, 0444);
101static int joystick;
102module_param(joystick, int, 0444);
103
104/*
105 * Direct registers
106 */
107enum { DEVICE_INTEL, DEVICE_INTEL_ICH4, DEVICE_SIS, DEVICE_ALI, DEVICE_NFORCE };
108
109#define ICHREG(x) ICH_REG_##x
110
111#define DEFINE_REGSET(name,base) \
112enum { \
113 ICH_REG_##name##_BDBAR = base + 0x0, /* dword - buffer descriptor list base address */ \
114 ICH_REG_##name##_CIV = base + 0x04, /* byte - current index value */ \
115 ICH_REG_##name##_LVI = base + 0x05, /* byte - last valid index */ \
116 ICH_REG_##name##_SR = base + 0x06, /* byte - status register */ \
117 ICH_REG_##name##_PICB = base + 0x08, /* word - position in current buffer */ \
118 ICH_REG_##name##_PIV = base + 0x0a, /* byte - prefetched index value */ \
119 ICH_REG_##name##_CR = base + 0x0b, /* byte - control register */ \
120};
121
122/* busmaster blocks */
123DEFINE_REGSET(OFF, 0); /* offset */
124DEFINE_REGSET(PI, 0x00); /* PCM in */
125DEFINE_REGSET(PO, 0x10); /* PCM out */
126DEFINE_REGSET(MC, 0x20); /* Mic in */
127
128/* ICH4 busmaster blocks */
129DEFINE_REGSET(MC2, 0x40); /* Mic in 2 */
130DEFINE_REGSET(PI2, 0x50); /* PCM in 2 */
131DEFINE_REGSET(SP, 0x60); /* SPDIF out */
132
133/* values for each busmaster block */
134
135/* LVI */
136#define ICH_REG_LVI_MASK 0x1f
137
138/* SR */
139#define ICH_FIFOE 0x10 /* FIFO error */
140#define ICH_BCIS 0x08 /* buffer completion interrupt status */
141#define ICH_LVBCI 0x04 /* last valid buffer completion interrupt */
142#define ICH_CELV 0x02 /* current equals last valid */
143#define ICH_DCH 0x01 /* DMA controller halted */
144
145/* PIV */
146#define ICH_REG_PIV_MASK 0x1f /* mask */
147
148/* CR */
149#define ICH_IOCE 0x10 /* interrupt on completion enable */
150#define ICH_FEIE 0x08 /* fifo error interrupt enable */
151#define ICH_LVBIE 0x04 /* last valid buffer interrupt enable */
152#define ICH_RESETREGS 0x02 /* reset busmaster registers */
153#define ICH_STARTBM 0x01 /* start busmaster operation */
154
155
156/* global block */
157#define ICH_REG_GLOB_CNT 0x2c /* dword - global control */
158#define ICH_PCM_SPDIF_MASK 0xc0000000 /* s/pdif pcm slot mask (ICH4) */
159#define ICH_PCM_SPDIF_NONE 0x00000000 /* reserved - undefined */
160#define ICH_PCM_SPDIF_78 0x40000000 /* s/pdif pcm on slots 7&8 */
161#define ICH_PCM_SPDIF_69 0x80000000 /* s/pdif pcm on slots 6&9 */
162#define ICH_PCM_SPDIF_1011 0xc0000000 /* s/pdif pcm on slots 10&11 */
163#define ICH_PCM_20BIT 0x00400000 /* 20-bit samples (ICH4) */
164#define ICH_PCM_246_MASK 0x00300000 /* chan mask (not all chips) */
165#define ICH_PCM_8 0x00300000 /* 8 channels (not all chips) */
166#define ICH_PCM_6 0x00200000 /* 6 channels (not all chips) */
167#define ICH_PCM_4 0x00100000 /* 4 channels (not all chips) */
168#define ICH_PCM_2 0x00000000 /* 2 channels (stereo) */
169#define ICH_SIS_PCM_246_MASK 0x000000c0 /* 6 channels (SIS7012) */
170#define ICH_SIS_PCM_6 0x00000080 /* 6 channels (SIS7012) */
171#define ICH_SIS_PCM_4 0x00000040 /* 4 channels (SIS7012) */
172#define ICH_SIS_PCM_2 0x00000000 /* 2 channels (SIS7012) */
173#define ICH_TRIE 0x00000040 /* tertiary resume interrupt enable */
174#define ICH_SRIE 0x00000020 /* secondary resume interrupt enable */
175#define ICH_PRIE 0x00000010 /* primary resume interrupt enable */
176#define ICH_ACLINK 0x00000008 /* AClink shut off */
177#define ICH_AC97WARM 0x00000004 /* AC'97 warm reset */
178#define ICH_AC97COLD 0x00000002 /* AC'97 cold reset */
179#define ICH_GIE 0x00000001 /* GPI interrupt enable */
180#define ICH_REG_GLOB_STA 0x30 /* dword - global status */
181#define ICH_TRI 0x20000000 /* ICH4: tertiary (AC_SDIN2) resume interrupt */
182#define ICH_TCR 0x10000000 /* ICH4: tertiary (AC_SDIN2) codec ready */
183#define ICH_BCS 0x08000000 /* ICH4: bit clock stopped */
184#define ICH_SPINT 0x04000000 /* ICH4: S/PDIF interrupt */
185#define ICH_P2INT 0x02000000 /* ICH4: PCM2-In interrupt */
186#define ICH_M2INT 0x01000000 /* ICH4: Mic2-In interrupt */
187#define ICH_SAMPLE_CAP 0x00c00000 /* ICH4: sample capability bits (RO) */
188#define ICH_SAMPLE_16_20 0x00400000 /* ICH4: 16- and 20-bit samples */
189#define ICH_MULTICHAN_CAP 0x00300000 /* ICH4: multi-channel capability bits (RO) */
190#define ICH_SIS_TRI 0x00080000 /* SIS: tertiary resume irq */
191#define ICH_SIS_TCR 0x00040000 /* SIS: tertiary codec ready */
192#define ICH_MD3 0x00020000 /* modem power down semaphore */
193#define ICH_AD3 0x00010000 /* audio power down semaphore */
194#define ICH_RCS 0x00008000 /* read completion status */
195#define ICH_BIT3 0x00004000 /* bit 3 slot 12 */
196#define ICH_BIT2 0x00002000 /* bit 2 slot 12 */
197#define ICH_BIT1 0x00001000 /* bit 1 slot 12 */
198#define ICH_SRI 0x00000800 /* secondary (AC_SDIN1) resume interrupt */
199#define ICH_PRI 0x00000400 /* primary (AC_SDIN0) resume interrupt */
200#define ICH_SCR 0x00000200 /* secondary (AC_SDIN1) codec ready */
201#define ICH_PCR 0x00000100 /* primary (AC_SDIN0) codec ready */
202#define ICH_MCINT 0x00000080 /* MIC capture interrupt */
203#define ICH_POINT 0x00000040 /* playback interrupt */
204#define ICH_PIINT 0x00000020 /* capture interrupt */
205#define ICH_NVSPINT 0x00000010 /* nforce spdif interrupt */
206#define ICH_MOINT 0x00000004 /* modem playback interrupt */
207#define ICH_MIINT 0x00000002 /* modem capture interrupt */
208#define ICH_GSCI 0x00000001 /* GPI status change interrupt */
209#define ICH_REG_ACC_SEMA 0x34 /* byte - codec write semaphore */
210#define ICH_CAS 0x01 /* codec access semaphore */
211#define ICH_REG_SDM 0x80
212#define ICH_DI2L_MASK 0x000000c0 /* PCM In 2, Mic In 2 data in line */
213#define ICH_DI2L_SHIFT 6
214#define ICH_DI1L_MASK 0x00000030 /* PCM In 1, Mic In 1 data in line */
215#define ICH_DI1L_SHIFT 4
216#define ICH_SE 0x00000008 /* steer enable */
217#define ICH_LDI_MASK 0x00000003 /* last codec read data input */
218
219#define ICH_MAX_FRAGS 32 /* max hw frags */
220
221
222/*
223 * registers for Ali5455
224 */
225
226/* ALi 5455 busmaster blocks */
227DEFINE_REGSET(AL_PI, 0x40); /* ALi PCM in */
228DEFINE_REGSET(AL_PO, 0x50); /* Ali PCM out */
229DEFINE_REGSET(AL_MC, 0x60); /* Ali Mic in */
230DEFINE_REGSET(AL_CDC_SPO, 0x70); /* Ali Codec SPDIF out */
231DEFINE_REGSET(AL_CENTER, 0x80); /* Ali center out */
232DEFINE_REGSET(AL_LFE, 0x90); /* Ali center out */
233DEFINE_REGSET(AL_CLR_SPI, 0xa0); /* Ali Controller SPDIF in */
234DEFINE_REGSET(AL_CLR_SPO, 0xb0); /* Ali Controller SPDIF out */
235DEFINE_REGSET(AL_I2S, 0xc0); /* Ali I2S in */
236DEFINE_REGSET(AL_PI2, 0xd0); /* Ali PCM2 in */
237DEFINE_REGSET(AL_MC2, 0xe0); /* Ali Mic2 in */
238
239enum {
240 ICH_REG_ALI_SCR = 0x00, /* System Control Register */
241 ICH_REG_ALI_SSR = 0x04, /* System Status Register */
242 ICH_REG_ALI_DMACR = 0x08, /* DMA Control Register */
243 ICH_REG_ALI_FIFOCR1 = 0x0c, /* FIFO Control Register 1 */
244 ICH_REG_ALI_INTERFACECR = 0x10, /* Interface Control Register */
245 ICH_REG_ALI_INTERRUPTCR = 0x14, /* Interrupt control Register */
246 ICH_REG_ALI_INTERRUPTSR = 0x18, /* Interrupt Status Register */
247 ICH_REG_ALI_FIFOCR2 = 0x1c, /* FIFO Control Register 2 */
248 ICH_REG_ALI_CPR = 0x20, /* Command Port Register */
249 ICH_REG_ALI_CPR_ADDR = 0x22, /* ac97 addr write */
250 ICH_REG_ALI_SPR = 0x24, /* Status Port Register */
251 ICH_REG_ALI_SPR_ADDR = 0x26, /* ac97 addr read */
252 ICH_REG_ALI_FIFOCR3 = 0x2c, /* FIFO Control Register 3 */
253 ICH_REG_ALI_TTSR = 0x30, /* Transmit Tag Slot Register */
254 ICH_REG_ALI_RTSR = 0x34, /* Receive Tag Slot Register */
255 ICH_REG_ALI_CSPSR = 0x38, /* Command/Status Port Status Register */
256 ICH_REG_ALI_CAS = 0x3c, /* Codec Write Semaphore Register */
257 ICH_REG_ALI_HWVOL = 0xf0, /* hardware volume control/status */
258 ICH_REG_ALI_I2SCR = 0xf4, /* I2S control/status */
259 ICH_REG_ALI_SPDIFCSR = 0xf8, /* spdif channel status register */
260 ICH_REG_ALI_SPDIFICS = 0xfc, /* spdif interface control/status */
261};
262
263#define ALI_CAS_SEM_BUSY 0x80000000
264#define ALI_CPR_ADDR_SECONDARY 0x100
265#define ALI_CPR_ADDR_READ 0x80
266#define ALI_CSPSR_CODEC_READY 0x08
267#define ALI_CSPSR_READ_OK 0x02
268#define ALI_CSPSR_WRITE_OK 0x01
269
270/* interrupts for the whole chip by interrupt status register finish */
271
272#define ALI_INT_MICIN2 (1<<26)
273#define ALI_INT_PCMIN2 (1<<25)
274#define ALI_INT_I2SIN (1<<24)
275#define ALI_INT_SPDIFOUT (1<<23) /* controller spdif out INTERRUPT */
276#define ALI_INT_SPDIFIN (1<<22)
277#define ALI_INT_LFEOUT (1<<21)
278#define ALI_INT_CENTEROUT (1<<20)
279#define ALI_INT_CODECSPDIFOUT (1<<19)
280#define ALI_INT_MICIN (1<<18)
281#define ALI_INT_PCMOUT (1<<17)
282#define ALI_INT_PCMIN (1<<16)
283#define ALI_INT_CPRAIS (1<<7) /* command port available */
284#define ALI_INT_SPRAIS (1<<5) /* status port available */
285#define ALI_INT_GPIO (1<<1)
286#define ALI_INT_MASK (ALI_INT_SPDIFOUT|ALI_INT_CODECSPDIFOUT|\
287 ALI_INT_MICIN|ALI_INT_PCMOUT|ALI_INT_PCMIN)
288
289#define ICH_ALI_SC_RESET (1<<31) /* master reset */
290#define ICH_ALI_SC_AC97_DBL (1<<30)
291#define ICH_ALI_SC_CODEC_SPDF (3<<20) /* 1=7/8, 2=6/9, 3=10/11 */
292#define ICH_ALI_SC_IN_BITS (3<<18)
293#define ICH_ALI_SC_OUT_BITS (3<<16)
294#define ICH_ALI_SC_6CH_CFG (3<<14)
295#define ICH_ALI_SC_PCM_4 (1<<8)
296#define ICH_ALI_SC_PCM_6 (2<<8)
297#define ICH_ALI_SC_PCM_246_MASK (3<<8)
298
299#define ICH_ALI_SS_SEC_ID (3<<5)
300#define ICH_ALI_SS_PRI_ID (3<<3)
301
302#define ICH_ALI_IF_AC97SP (1<<21)
303#define ICH_ALI_IF_MC (1<<20)
304#define ICH_ALI_IF_PI (1<<19)
305#define ICH_ALI_IF_MC2 (1<<18)
306#define ICH_ALI_IF_PI2 (1<<17)
307#define ICH_ALI_IF_LINE_SRC (1<<15) /* 0/1 = slot 3/6 */
308#define ICH_ALI_IF_MIC_SRC (1<<14) /* 0/1 = slot 3/6 */
309#define ICH_ALI_IF_SPDF_SRC (3<<12) /* 00 = PCM, 01 = AC97-in, 10 = spdif-in, 11 = i2s */
310#define ICH_ALI_IF_AC97_OUT (3<<8) /* 00 = PCM, 10 = spdif-in, 11 = i2s */
311#define ICH_ALI_IF_PO_SPDF (1<<3)
312#define ICH_ALI_IF_PO (1<<1)
313
314/*
315 *
316 */
317
318enum {
319 ICHD_PCMIN,
320 ICHD_PCMOUT,
321 ICHD_MIC,
322 ICHD_MIC2,
323 ICHD_PCM2IN,
324 ICHD_SPBAR,
325 ICHD_LAST = ICHD_SPBAR
326};
327enum {
328 NVD_PCMIN,
329 NVD_PCMOUT,
330 NVD_MIC,
331 NVD_SPBAR,
332 NVD_LAST = NVD_SPBAR
333};
334enum {
335 ALID_PCMIN,
336 ALID_PCMOUT,
337 ALID_MIC,
338 ALID_AC97SPDIFOUT,
339 ALID_SPDIFIN,
340 ALID_SPDIFOUT,
341 ALID_LAST = ALID_SPDIFOUT
342};
343
344#define get_ichdev(substream) (substream->runtime->private_data)
345
346struct ichdev {
347 unsigned int ichd; /* ich device number */
348 unsigned long reg_offset; /* offset to bmaddr */
349 u32 *bdbar; /* CPU address (32bit) */
350 unsigned int bdbar_addr; /* PCI bus address (32bit) */
351 struct snd_pcm_substream *substream;
352 unsigned int physbuf; /* physical address (32bit) */
353 unsigned int size;
354 unsigned int fragsize;
355 unsigned int fragsize1;
356 unsigned int position;
357 unsigned int pos_shift;
358 unsigned int last_pos;
359 unsigned long last_pos_jiffies;
360 unsigned int jiffy_to_bytes;
361 int frags;
362 int lvi;
363 int lvi_frag;
364 int civ;
365 int ack;
366 int ack_reload;
367 unsigned int ack_bit;
368 unsigned int roff_sr;
369 unsigned int roff_picb;
370 unsigned int int_sta_mask; /* interrupt status mask */
371 unsigned int ali_slot; /* ALI DMA slot */
372 struct ac97_pcm *pcm;
373 int pcm_open_flag;
374 unsigned int page_attr_changed: 1;
375 unsigned int suspended: 1;
376};
377
378struct intel8x0 {
379 unsigned int device_type;
380
381 int irq;
382
383 void __iomem *addr;
384 void __iomem *bmaddr;
385
386 struct pci_dev *pci;
387 struct snd_card *card;
388
389 int pcm_devs;
390 struct snd_pcm *pcm[6];
391 struct ichdev ichd[6];
392
393 unsigned multi4: 1,
394 multi6: 1,
395 multi8 :1,
396 dra: 1,
397 smp20bit: 1;
398 unsigned in_ac97_init: 1,
399 in_sdin_init: 1;
400 unsigned in_measurement: 1; /* during ac97 clock measurement */
401 unsigned fix_nocache: 1; /* workaround for 440MX */
402 unsigned buggy_irq: 1; /* workaround for buggy mobos */
403 unsigned xbox: 1; /* workaround for Xbox AC'97 detection */
404 unsigned buggy_semaphore: 1; /* workaround for buggy codec semaphore */
405
406 int spdif_idx; /* SPDIF BAR index; *_SPBAR or -1 if use PCMOUT */
407 unsigned int sdm_saved; /* SDM reg value */
408
409 struct snd_ac97_bus *ac97_bus;
410 struct snd_ac97 *ac97[3];
411 unsigned int ac97_sdin[3];
412 unsigned int max_codecs, ncodecs;
413 unsigned int *codec_bit;
414 unsigned int codec_isr_bits;
415 unsigned int codec_ready_bits;
416
417 spinlock_t reg_lock;
418
419 u32 bdbars_count;
420 struct snd_dma_buffer bdbars;
421 u32 int_sta_reg; /* interrupt status register */
422 u32 int_sta_mask; /* interrupt status mask */
423};
424
425static struct pci_device_id snd_intel8x0_ids[] = {
426 { 0x8086, 0x2415, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* 82801AA */
427 { 0x8086, 0x2425, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* 82901AB */
428 { 0x8086, 0x2445, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* 82801BA */
429 { 0x8086, 0x2485, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* ICH3 */
430 { 0x8086, 0x24c5, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL_ICH4 }, /* ICH4 */
431 { 0x8086, 0x24d5, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL_ICH4 }, /* ICH5 */
432 { 0x8086, 0x25a6, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL_ICH4 }, /* ESB */
433 { 0x8086, 0x266e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL_ICH4 }, /* ICH6 */
434 { 0x8086, 0x27de, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL_ICH4 }, /* ICH7 */
435 { 0x8086, 0x2698, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL_ICH4 }, /* ESB2 */
436 { 0x8086, 0x7195, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* 440MX */
437 { 0x1039, 0x7012, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_SIS }, /* SI7012 */
438 { 0x10de, 0x01b1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE }, /* NFORCE */
439 { 0x10de, 0x003a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE }, /* MCP04 */
440 { 0x10de, 0x006a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE }, /* NFORCE2 */
441 { 0x10de, 0x0059, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE }, /* CK804 */
442 { 0x10de, 0x008a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE }, /* CK8 */
443 { 0x10de, 0x00da, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE }, /* NFORCE3 */
444 { 0x10de, 0x00ea, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE }, /* CK8S */
445 { 0x10de, 0x026b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE }, /* MCP51 */
446 { 0x1022, 0x746d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* AMD8111 */
447 { 0x1022, 0x7445, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* AMD768 */
448 { 0x10b9, 0x5455, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_ALI }, /* Ali5455 */
449 { 0, }
450};
451
452MODULE_DEVICE_TABLE(pci, snd_intel8x0_ids);
453
454/*
455 * Lowlevel I/O - busmaster
456 */
457
458static inline u8 igetbyte(struct intel8x0 *chip, u32 offset)
459{
460 return ioread8(chip->bmaddr + offset);
461}
462
463static inline u16 igetword(struct intel8x0 *chip, u32 offset)
464{
465 return ioread16(chip->bmaddr + offset);
466}
467
468static inline u32 igetdword(struct intel8x0 *chip, u32 offset)
469{
470 return ioread32(chip->bmaddr + offset);
471}
472
473static inline void iputbyte(struct intel8x0 *chip, u32 offset, u8 val)
474{
475 iowrite8(val, chip->bmaddr + offset);
476}
477
478static inline void iputword(struct intel8x0 *chip, u32 offset, u16 val)
479{
480 iowrite16(val, chip->bmaddr + offset);
481}
482
483static inline void iputdword(struct intel8x0 *chip, u32 offset, u32 val)
484{
485 iowrite32(val, chip->bmaddr + offset);
486}
487
488/*
489 * Lowlevel I/O - AC'97 registers
490 */
491
492static inline u16 iagetword(struct intel8x0 *chip, u32 offset)
493{
494 return ioread16(chip->addr + offset);
495}
496
497static inline void iaputword(struct intel8x0 *chip, u32 offset, u16 val)
498{
499 iowrite16(val, chip->addr + offset);
500}
501
502/*
503 * Basic I/O
504 */
505
506/*
507 * access to AC97 codec via normal i/o (for ICH and SIS7012)
508 */
509
510static int snd_intel8x0_codec_semaphore(struct intel8x0 *chip, unsigned int codec)
511{
512 int time;
513
514 if (codec > 2)
515 return -EIO;
516 if (chip->in_sdin_init) {
517 /* we don't know the ready bit assignment at the moment */
518 /* so we check any */
519 codec = chip->codec_isr_bits;
520 } else {
521 codec = chip->codec_bit[chip->ac97_sdin[codec]];
522 }
523
524 /* codec ready ? */
525 if ((igetdword(chip, ICHREG(GLOB_STA)) & codec) == 0)
526 return -EIO;
527
528 if (chip->buggy_semaphore)
529 return 0; /* just ignore ... */
530
531 /* Anyone holding a semaphore for 1 msec should be shot... */
532 time = 100;
533 do {
534 if (!(igetbyte(chip, ICHREG(ACC_SEMA)) & ICH_CAS))
535 return 0;
536 udelay(10);
537 } while (time--);
538
539 /* access to some forbidden (non existant) ac97 registers will not
540 * reset the semaphore. So even if you don't get the semaphore, still
541 * continue the access. We don't need the semaphore anyway. */
542 snd_printk(KERN_ERR "codec_semaphore: semaphore is not ready [0x%x][0x%x]\n",
543 igetbyte(chip, ICHREG(ACC_SEMA)), igetdword(chip, ICHREG(GLOB_STA)));
544 iagetword(chip, 0); /* clear semaphore flag */
545 /* I don't care about the semaphore */
546 return -EBUSY;
547}
548
549static void snd_intel8x0_codec_write(struct snd_ac97 *ac97,
550 unsigned short reg,
551 unsigned short val)
552{
553 struct intel8x0 *chip = ac97->private_data;
554
555 if (snd_intel8x0_codec_semaphore(chip, ac97->num) < 0) {
556 if (! chip->in_ac97_init)
557 snd_printk(KERN_ERR "codec_write %d: semaphore is not ready for register 0x%x\n", ac97->num, reg);
558 }
559 iaputword(chip, reg + ac97->num * 0x80, val);
560}
561
562static unsigned short snd_intel8x0_codec_read(struct snd_ac97 *ac97,
563 unsigned short reg)
564{
565 struct intel8x0 *chip = ac97->private_data;
566 unsigned short res;
567 unsigned int tmp;
568
569 if (snd_intel8x0_codec_semaphore(chip, ac97->num) < 0) {
570 if (! chip->in_ac97_init)
571 snd_printk(KERN_ERR "codec_read %d: semaphore is not ready for register 0x%x\n", ac97->num, reg);
572 res = 0xffff;
573 } else {
574 res = iagetword(chip, reg + ac97->num * 0x80);
575 if ((tmp = igetdword(chip, ICHREG(GLOB_STA))) & ICH_RCS) {
576 /* reset RCS and preserve other R/WC bits */
577 iputdword(chip, ICHREG(GLOB_STA), tmp &
578 ~(chip->codec_ready_bits | ICH_GSCI));
579 if (! chip->in_ac97_init)
580 snd_printk(KERN_ERR "codec_read %d: read timeout for register 0x%x\n", ac97->num, reg);
581 res = 0xffff;
582 }
583 }
584 return res;
585}
586
587static void __devinit snd_intel8x0_codec_read_test(struct intel8x0 *chip,
588 unsigned int codec)
589{
590 unsigned int tmp;
591
592 if (snd_intel8x0_codec_semaphore(chip, codec) >= 0) {
593 iagetword(chip, codec * 0x80);
594 if ((tmp = igetdword(chip, ICHREG(GLOB_STA))) & ICH_RCS) {
595 /* reset RCS and preserve other R/WC bits */
596 iputdword(chip, ICHREG(GLOB_STA), tmp &
597 ~(chip->codec_ready_bits | ICH_GSCI));
598 }
599 }
600}
601
602/*
603 * access to AC97 for Ali5455
604 */
605static int snd_intel8x0_ali_codec_ready(struct intel8x0 *chip, int mask)
606{
607 int count = 0;
608 for (count = 0; count < 0x7f; count++) {
609 int val = igetbyte(chip, ICHREG(ALI_CSPSR));
610 if (val & mask)
611 return 0;
612 }
613 if (! chip->in_ac97_init)
614 snd_printd(KERN_WARNING "intel8x0: AC97 codec ready timeout.\n");
615 return -EBUSY;
616}
617
618static int snd_intel8x0_ali_codec_semaphore(struct intel8x0 *chip)
619{
620 int time = 100;
621 if (chip->buggy_semaphore)
622 return 0; /* just ignore ... */
623 while (--time && (igetdword(chip, ICHREG(ALI_CAS)) & ALI_CAS_SEM_BUSY))
624 udelay(1);
625 if (! time && ! chip->in_ac97_init)
626 snd_printk(KERN_WARNING "ali_codec_semaphore timeout\n");
627 return snd_intel8x0_ali_codec_ready(chip, ALI_CSPSR_CODEC_READY);
628}
629
630static unsigned short snd_intel8x0_ali_codec_read(struct snd_ac97 *ac97, unsigned short reg)
631{
632 struct intel8x0 *chip = ac97->private_data;
633 unsigned short data = 0xffff;
634
635 if (snd_intel8x0_ali_codec_semaphore(chip))
636 goto __err;
637 reg |= ALI_CPR_ADDR_READ;
638 if (ac97->num)
639 reg |= ALI_CPR_ADDR_SECONDARY;
640 iputword(chip, ICHREG(ALI_CPR_ADDR), reg);
641 if (snd_intel8x0_ali_codec_ready(chip, ALI_CSPSR_READ_OK))
642 goto __err;
643 data = igetword(chip, ICHREG(ALI_SPR));
644 __err:
645 return data;
646}
647
648static void snd_intel8x0_ali_codec_write(struct snd_ac97 *ac97, unsigned short reg,
649 unsigned short val)
650{
651 struct intel8x0 *chip = ac97->private_data;
652
653 if (snd_intel8x0_ali_codec_semaphore(chip))
654 return;
655 iputword(chip, ICHREG(ALI_CPR), val);
656 if (ac97->num)
657 reg |= ALI_CPR_ADDR_SECONDARY;
658 iputword(chip, ICHREG(ALI_CPR_ADDR), reg);
659 snd_intel8x0_ali_codec_ready(chip, ALI_CSPSR_WRITE_OK);
660}
661
662
663/*
664 * DMA I/O
665 */
666static void snd_intel8x0_setup_periods(struct intel8x0 *chip, struct ichdev *ichdev)
667{
668 int idx;
669 u32 *bdbar = ichdev->bdbar;
670 unsigned long port = ichdev->reg_offset;
671
672 iputdword(chip, port + ICH_REG_OFF_BDBAR, ichdev->bdbar_addr);
673 if (ichdev->size == ichdev->fragsize) {
674 ichdev->ack_reload = ichdev->ack = 2;
675 ichdev->fragsize1 = ichdev->fragsize >> 1;
676 for (idx = 0; idx < (ICH_REG_LVI_MASK + 1) * 2; idx += 4) {
677 bdbar[idx + 0] = cpu_to_le32(ichdev->physbuf);
678 bdbar[idx + 1] = cpu_to_le32(0x80000000 | /* interrupt on completion */
679 ichdev->fragsize1 >> ichdev->pos_shift);
680 bdbar[idx + 2] = cpu_to_le32(ichdev->physbuf + (ichdev->size >> 1));
681 bdbar[idx + 3] = cpu_to_le32(0x80000000 | /* interrupt on completion */
682 ichdev->fragsize1 >> ichdev->pos_shift);
683 }
684 ichdev->frags = 2;
685 } else {
686 ichdev->ack_reload = ichdev->ack = 1;
687 ichdev->fragsize1 = ichdev->fragsize;
688 for (idx = 0; idx < (ICH_REG_LVI_MASK + 1) * 2; idx += 2) {
689 bdbar[idx + 0] = cpu_to_le32(ichdev->physbuf +
690 (((idx >> 1) * ichdev->fragsize) %
691 ichdev->size));
692 bdbar[idx + 1] = cpu_to_le32(0x80000000 | /* interrupt on completion */
693 ichdev->fragsize >> ichdev->pos_shift);
694#if 0
695 printk(KERN_DEBUG "bdbar[%i] = 0x%x [0x%x]\n",
696 idx + 0, bdbar[idx + 0], bdbar[idx + 1]);
697#endif
698 }
699 ichdev->frags = ichdev->size / ichdev->fragsize;
700 }
701 iputbyte(chip, port + ICH_REG_OFF_LVI, ichdev->lvi = ICH_REG_LVI_MASK);
702 ichdev->civ = 0;
703 iputbyte(chip, port + ICH_REG_OFF_CIV, 0);
704 ichdev->lvi_frag = ICH_REG_LVI_MASK % ichdev->frags;
705 ichdev->position = 0;
706#if 0
707 printk(KERN_DEBUG "lvi_frag = %i, frags = %i, period_size = 0x%x, "
708 "period_size1 = 0x%x\n",
709 ichdev->lvi_frag, ichdev->frags, ichdev->fragsize,
710 ichdev->fragsize1);
711#endif
712 /* clear interrupts */
713 iputbyte(chip, port + ichdev->roff_sr, ICH_FIFOE | ICH_BCIS | ICH_LVBCI);
714}
715
716#ifdef __i386__
717/*
718 * Intel 82443MX running a 100MHz processor system bus has a hardware bug,
719 * which aborts PCI busmaster for audio transfer. A workaround is to set
720 * the pages as non-cached. For details, see the errata in
721 * http://www.intel.com/design/chipsets/specupdt/245051.htm
722 */
723static void fill_nocache(void *buf, int size, int nocache)
724{
725 size = (size + PAGE_SIZE - 1) >> PAGE_SHIFT;
726 if (nocache)
727 set_pages_uc(virt_to_page(buf), size);
728 else
729 set_pages_wb(virt_to_page(buf), size);
730}
731#else
732#define fill_nocache(buf, size, nocache) do { ; } while (0)
733#endif
734
735/*
736 * Interrupt handler
737 */
738
739static inline void snd_intel8x0_update(struct intel8x0 *chip, struct ichdev *ichdev)
740{
741 unsigned long port = ichdev->reg_offset;
742 unsigned long flags;
743 int status, civ, i, step;
744 int ack = 0;
745
746 spin_lock_irqsave(&chip->reg_lock, flags);
747 status = igetbyte(chip, port + ichdev->roff_sr);
748 civ = igetbyte(chip, port + ICH_REG_OFF_CIV);
749 if (!(status & ICH_BCIS)) {
750 step = 0;
751 } else if (civ == ichdev->civ) {
752 // snd_printd("civ same %d\n", civ);
753 step = 1;
754 ichdev->civ++;
755 ichdev->civ &= ICH_REG_LVI_MASK;
756 } else {
757 step = civ - ichdev->civ;
758 if (step < 0)
759 step += ICH_REG_LVI_MASK + 1;
760 // if (step != 1)
761 // snd_printd("step = %d, %d -> %d\n", step, ichdev->civ, civ);
762 ichdev->civ = civ;
763 }
764
765 ichdev->position += step * ichdev->fragsize1;
766 if (! chip->in_measurement)
767 ichdev->position %= ichdev->size;
768 ichdev->lvi += step;
769 ichdev->lvi &= ICH_REG_LVI_MASK;
770 iputbyte(chip, port + ICH_REG_OFF_LVI, ichdev->lvi);
771 for (i = 0; i < step; i++) {
772 ichdev->lvi_frag++;
773 ichdev->lvi_frag %= ichdev->frags;
774 ichdev->bdbar[ichdev->lvi * 2] = cpu_to_le32(ichdev->physbuf + ichdev->lvi_frag * ichdev->fragsize1);
775#if 0
776 printk(KERN_DEBUG "new: bdbar[%i] = 0x%x [0x%x], prefetch = %i, "
777 "all = 0x%x, 0x%x\n",
778 ichdev->lvi * 2, ichdev->bdbar[ichdev->lvi * 2],
779 ichdev->bdbar[ichdev->lvi * 2 + 1], inb(ICH_REG_OFF_PIV + port),
780 inl(port + 4), inb(port + ICH_REG_OFF_CR));
781#endif
782 if (--ichdev->ack == 0) {
783 ichdev->ack = ichdev->ack_reload;
784 ack = 1;
785 }
786 }
787 spin_unlock_irqrestore(&chip->reg_lock, flags);
788 if (ack && ichdev->substream) {
789 snd_pcm_period_elapsed(ichdev->substream);
790 }
791 iputbyte(chip, port + ichdev->roff_sr,
792 status & (ICH_FIFOE | ICH_BCIS | ICH_LVBCI));
793}
794
795static irqreturn_t snd_intel8x0_interrupt(int irq, void *dev_id)
796{
797 struct intel8x0 *chip = dev_id;
798 struct ichdev *ichdev;
799 unsigned int status;
800 unsigned int i;
801
802 status = igetdword(chip, chip->int_sta_reg);
803 if (status == 0xffffffff) /* we are not yet resumed */
804 return IRQ_NONE;
805
806 if ((status & chip->int_sta_mask) == 0) {
807 if (status) {
808 /* ack */
809 iputdword(chip, chip->int_sta_reg, status);
810 if (! chip->buggy_irq)
811 status = 0;
812 }
813 return IRQ_RETVAL(status);
814 }
815
816 for (i = 0; i < chip->bdbars_count; i++) {
817 ichdev = &chip->ichd[i];
818 if (status & ichdev->int_sta_mask)
819 snd_intel8x0_update(chip, ichdev);
820 }
821
822 /* ack them */
823 iputdword(chip, chip->int_sta_reg, status & chip->int_sta_mask);
824
825 return IRQ_HANDLED;
826}
827
828/*
829 * PCM part
830 */
831
832static int snd_intel8x0_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
833{
834 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
835 struct ichdev *ichdev = get_ichdev(substream);
836 unsigned char val = 0;
837 unsigned long port = ichdev->reg_offset;
838
839 switch (cmd) {
840 case SNDRV_PCM_TRIGGER_RESUME:
841 ichdev->suspended = 0;
842 /* fallthru */
843 case SNDRV_PCM_TRIGGER_START:
844 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
845 val = ICH_IOCE | ICH_STARTBM;
846 ichdev->last_pos = ichdev->position;
847 ichdev->last_pos_jiffies = jiffies;
848 break;
849 case SNDRV_PCM_TRIGGER_SUSPEND:
850 ichdev->suspended = 1;
851 /* fallthru */
852 case SNDRV_PCM_TRIGGER_STOP:
853 val = 0;
854 break;
855 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
856 val = ICH_IOCE;
857 break;
858 default:
859 return -EINVAL;
860 }
861 iputbyte(chip, port + ICH_REG_OFF_CR, val);
862 if (cmd == SNDRV_PCM_TRIGGER_STOP) {
863 /* wait until DMA stopped */
864 while (!(igetbyte(chip, port + ichdev->roff_sr) & ICH_DCH)) ;
865 /* reset whole DMA things */
866 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_RESETREGS);
867 }
868 return 0;
869}
870
871static int snd_intel8x0_ali_trigger(struct snd_pcm_substream *substream, int cmd)
872{
873 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
874 struct ichdev *ichdev = get_ichdev(substream);
875 unsigned long port = ichdev->reg_offset;
876 static int fiforeg[] = {
877 ICHREG(ALI_FIFOCR1), ICHREG(ALI_FIFOCR2), ICHREG(ALI_FIFOCR3)
878 };
879 unsigned int val, fifo;
880
881 val = igetdword(chip, ICHREG(ALI_DMACR));
882 switch (cmd) {
883 case SNDRV_PCM_TRIGGER_RESUME:
884 ichdev->suspended = 0;
885 /* fallthru */
886 case SNDRV_PCM_TRIGGER_START:
887 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
888 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
889 /* clear FIFO for synchronization of channels */
890 fifo = igetdword(chip, fiforeg[ichdev->ali_slot / 4]);
891 fifo &= ~(0xff << (ichdev->ali_slot % 4));
892 fifo |= 0x83 << (ichdev->ali_slot % 4);
893 iputdword(chip, fiforeg[ichdev->ali_slot / 4], fifo);
894 }
895 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_IOCE);
896 val &= ~(1 << (ichdev->ali_slot + 16)); /* clear PAUSE flag */
897 /* start DMA */
898 iputdword(chip, ICHREG(ALI_DMACR), val | (1 << ichdev->ali_slot));
899 break;
900 case SNDRV_PCM_TRIGGER_SUSPEND:
901 ichdev->suspended = 1;
902 /* fallthru */
903 case SNDRV_PCM_TRIGGER_STOP:
904 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
905 /* pause */
906 iputdword(chip, ICHREG(ALI_DMACR), val | (1 << (ichdev->ali_slot + 16)));
907 iputbyte(chip, port + ICH_REG_OFF_CR, 0);
908 while (igetbyte(chip, port + ICH_REG_OFF_CR))
909 ;
910 if (cmd == SNDRV_PCM_TRIGGER_PAUSE_PUSH)
911 break;
912 /* reset whole DMA things */
913 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_RESETREGS);
914 /* clear interrupts */
915 iputbyte(chip, port + ICH_REG_OFF_SR,
916 igetbyte(chip, port + ICH_REG_OFF_SR) | 0x1e);
917 iputdword(chip, ICHREG(ALI_INTERRUPTSR),
918 igetdword(chip, ICHREG(ALI_INTERRUPTSR)) & ichdev->int_sta_mask);
919 break;
920 default:
921 return -EINVAL;
922 }
923 return 0;
924}
925
926static int snd_intel8x0_hw_params(struct snd_pcm_substream *substream,
927 struct snd_pcm_hw_params *hw_params)
928{
929 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
930 struct ichdev *ichdev = get_ichdev(substream);
931 struct snd_pcm_runtime *runtime = substream->runtime;
932 int dbl = params_rate(hw_params) > 48000;
933 int err;
934
935 if (chip->fix_nocache && ichdev->page_attr_changed) {
936 fill_nocache(runtime->dma_area, runtime->dma_bytes, 0); /* clear */
937 ichdev->page_attr_changed = 0;
938 }
939 err = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params));
940 if (err < 0)
941 return err;
942 if (chip->fix_nocache) {
943 if (runtime->dma_area && ! ichdev->page_attr_changed) {
944 fill_nocache(runtime->dma_area, runtime->dma_bytes, 1);
945 ichdev->page_attr_changed = 1;
946 }
947 }
948 if (ichdev->pcm_open_flag) {
949 snd_ac97_pcm_close(ichdev->pcm);
950 ichdev->pcm_open_flag = 0;
951 }
952 err = snd_ac97_pcm_open(ichdev->pcm, params_rate(hw_params),
953 params_channels(hw_params),
954 ichdev->pcm->r[dbl].slots);
955 if (err >= 0) {
956 ichdev->pcm_open_flag = 1;
957 /* Force SPDIF setting */
958 if (ichdev->ichd == ICHD_PCMOUT && chip->spdif_idx < 0)
959 snd_ac97_set_rate(ichdev->pcm->r[0].codec[0], AC97_SPDIF,
960 params_rate(hw_params));
961 }
962 return err;
963}
964
965static int snd_intel8x0_hw_free(struct snd_pcm_substream *substream)
966{
967 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
968 struct ichdev *ichdev = get_ichdev(substream);
969
970 if (ichdev->pcm_open_flag) {
971 snd_ac97_pcm_close(ichdev->pcm);
972 ichdev->pcm_open_flag = 0;
973 }
974 if (chip->fix_nocache && ichdev->page_attr_changed) {
975 fill_nocache(substream->runtime->dma_area, substream->runtime->dma_bytes, 0);
976 ichdev->page_attr_changed = 0;
977 }
978 return snd_pcm_lib_free_pages(substream);
979}
980
981static void snd_intel8x0_setup_pcm_out(struct intel8x0 *chip,
982 struct snd_pcm_runtime *runtime)
983{
984 unsigned int cnt;
985 int dbl = runtime->rate > 48000;
986
987 spin_lock_irq(&chip->reg_lock);
988 switch (chip->device_type) {
989 case DEVICE_ALI:
990 cnt = igetdword(chip, ICHREG(ALI_SCR));
991 cnt &= ~ICH_ALI_SC_PCM_246_MASK;
992 if (runtime->channels == 4 || dbl)
993 cnt |= ICH_ALI_SC_PCM_4;
994 else if (runtime->channels == 6)
995 cnt |= ICH_ALI_SC_PCM_6;
996 iputdword(chip, ICHREG(ALI_SCR), cnt);
997 break;
998 case DEVICE_SIS:
999 cnt = igetdword(chip, ICHREG(GLOB_CNT));
1000 cnt &= ~ICH_SIS_PCM_246_MASK;
1001 if (runtime->channels == 4 || dbl)
1002 cnt |= ICH_SIS_PCM_4;
1003 else if (runtime->channels == 6)
1004 cnt |= ICH_SIS_PCM_6;
1005 iputdword(chip, ICHREG(GLOB_CNT), cnt);
1006 break;
1007 default:
1008 cnt = igetdword(chip, ICHREG(GLOB_CNT));
1009 cnt &= ~(ICH_PCM_246_MASK | ICH_PCM_20BIT);
1010 if (runtime->channels == 4 || dbl)
1011 cnt |= ICH_PCM_4;
1012 else if (runtime->channels == 6)
1013 cnt |= ICH_PCM_6;
1014 else if (runtime->channels == 8)
1015 cnt |= ICH_PCM_8;
1016 if (chip->device_type == DEVICE_NFORCE) {
1017 /* reset to 2ch once to keep the 6 channel data in alignment,
1018 * to start from Front Left always
1019 */
1020 if (cnt & ICH_PCM_246_MASK) {
1021 iputdword(chip, ICHREG(GLOB_CNT), cnt & ~ICH_PCM_246_MASK);
1022 spin_unlock_irq(&chip->reg_lock);
1023 msleep(50); /* grrr... */
1024 spin_lock_irq(&chip->reg_lock);
1025 }
1026 } else if (chip->device_type == DEVICE_INTEL_ICH4) {
1027 if (runtime->sample_bits > 16)
1028 cnt |= ICH_PCM_20BIT;
1029 }
1030 iputdword(chip, ICHREG(GLOB_CNT), cnt);
1031 break;
1032 }
1033 spin_unlock_irq(&chip->reg_lock);
1034}
1035
1036static int snd_intel8x0_pcm_prepare(struct snd_pcm_substream *substream)
1037{
1038 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1039 struct snd_pcm_runtime *runtime = substream->runtime;
1040 struct ichdev *ichdev = get_ichdev(substream);
1041
1042 ichdev->physbuf = runtime->dma_addr;
1043 ichdev->size = snd_pcm_lib_buffer_bytes(substream);
1044 ichdev->fragsize = snd_pcm_lib_period_bytes(substream);
1045 if (ichdev->ichd == ICHD_PCMOUT) {
1046 snd_intel8x0_setup_pcm_out(chip, runtime);
1047 if (chip->device_type == DEVICE_INTEL_ICH4)
1048 ichdev->pos_shift = (runtime->sample_bits > 16) ? 2 : 1;
1049 }
1050 snd_intel8x0_setup_periods(chip, ichdev);
1051 ichdev->jiffy_to_bytes = (runtime->rate * 4 * ichdev->pos_shift) / HZ;
1052 return 0;
1053}
1054
1055static snd_pcm_uframes_t snd_intel8x0_pcm_pointer(struct snd_pcm_substream *substream)
1056{
1057 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1058 struct ichdev *ichdev = get_ichdev(substream);
1059 size_t ptr1, ptr;
1060 int civ, timeout = 10;
1061 unsigned int position;
1062
1063 spin_lock(&chip->reg_lock);
1064 do {
1065 civ = igetbyte(chip, ichdev->reg_offset + ICH_REG_OFF_CIV);
1066 ptr1 = igetword(chip, ichdev->reg_offset + ichdev->roff_picb);
1067 position = ichdev->position;
1068 if (ptr1 == 0) {
1069 udelay(10);
1070 continue;
1071 }
1072 if (civ == igetbyte(chip, ichdev->reg_offset + ICH_REG_OFF_CIV) &&
1073 ptr1 == igetword(chip, ichdev->reg_offset + ichdev->roff_picb))
1074 break;
1075 } while (timeout--);
1076 if (ptr1 != 0) {
1077 ptr1 <<= ichdev->pos_shift;
1078 ptr = ichdev->fragsize1 - ptr1;
1079 ptr += position;
1080 ichdev->last_pos = ptr;
1081 ichdev->last_pos_jiffies = jiffies;
1082 } else {
1083 ptr1 = jiffies - ichdev->last_pos_jiffies;
1084 if (ptr1)
1085 ptr1 -= 1;
1086 ptr = ichdev->last_pos + ptr1 * ichdev->jiffy_to_bytes;
1087 ptr %= ichdev->size;
1088 }
1089 spin_unlock(&chip->reg_lock);
1090 if (ptr >= ichdev->size)
1091 return 0;
1092 return bytes_to_frames(substream->runtime, ptr);
1093}
1094
1095static struct snd_pcm_hardware snd_intel8x0_stream =
1096{
1097 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1098 SNDRV_PCM_INFO_BLOCK_TRANSFER |
1099 SNDRV_PCM_INFO_MMAP_VALID |
1100 SNDRV_PCM_INFO_PAUSE |
1101 SNDRV_PCM_INFO_RESUME),
1102 .formats = SNDRV_PCM_FMTBIT_S16_LE,
1103 .rates = SNDRV_PCM_RATE_48000,
1104 .rate_min = 48000,
1105 .rate_max = 48000,
1106 .channels_min = 2,
1107 .channels_max = 2,
1108 .buffer_bytes_max = 128 * 1024,
1109 .period_bytes_min = 32,
1110 .period_bytes_max = 128 * 1024,
1111 .periods_min = 1,
1112 .periods_max = 1024,
1113 .fifo_size = 0,
1114};
1115
1116static unsigned int channels4[] = {
1117 2, 4,
1118};
1119
1120static struct snd_pcm_hw_constraint_list hw_constraints_channels4 = {
1121 .count = ARRAY_SIZE(channels4),
1122 .list = channels4,
1123 .mask = 0,
1124};
1125
1126static unsigned int channels6[] = {
1127 2, 4, 6,
1128};
1129
1130static struct snd_pcm_hw_constraint_list hw_constraints_channels6 = {
1131 .count = ARRAY_SIZE(channels6),
1132 .list = channels6,
1133 .mask = 0,
1134};
1135
1136static unsigned int channels8[] = {
1137 2, 4, 6, 8,
1138};
1139
1140static struct snd_pcm_hw_constraint_list hw_constraints_channels8 = {
1141 .count = ARRAY_SIZE(channels8),
1142 .list = channels8,
1143 .mask = 0,
1144};
1145
1146static int snd_intel8x0_pcm_open(struct snd_pcm_substream *substream, struct ichdev *ichdev)
1147{
1148 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1149 struct snd_pcm_runtime *runtime = substream->runtime;
1150 int err;
1151
1152 ichdev->substream = substream;
1153 runtime->hw = snd_intel8x0_stream;
1154 runtime->hw.rates = ichdev->pcm->rates;
1155 snd_pcm_limit_hw_rates(runtime);
1156 if (chip->device_type == DEVICE_SIS) {
1157 runtime->hw.buffer_bytes_max = 64*1024;
1158 runtime->hw.period_bytes_max = 64*1024;
1159 }
1160 if ((err = snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS)) < 0)
1161 return err;
1162 runtime->private_data = ichdev;
1163 return 0;
1164}
1165
1166static int snd_intel8x0_playback_open(struct snd_pcm_substream *substream)
1167{
1168 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1169 struct snd_pcm_runtime *runtime = substream->runtime;
1170 int err;
1171
1172 err = snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_PCMOUT]);
1173 if (err < 0)
1174 return err;
1175
1176 if (chip->multi8) {
1177 runtime->hw.channels_max = 8;
1178 snd_pcm_hw_constraint_list(runtime, 0,
1179 SNDRV_PCM_HW_PARAM_CHANNELS,
1180 &hw_constraints_channels8);
1181 } else if (chip->multi6) {
1182 runtime->hw.channels_max = 6;
1183 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
1184 &hw_constraints_channels6);
1185 } else if (chip->multi4) {
1186 runtime->hw.channels_max = 4;
1187 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
1188 &hw_constraints_channels4);
1189 }
1190 if (chip->dra) {
1191 snd_ac97_pcm_double_rate_rules(runtime);
1192 }
1193 if (chip->smp20bit) {
1194 runtime->hw.formats |= SNDRV_PCM_FMTBIT_S32_LE;
1195 snd_pcm_hw_constraint_msbits(runtime, 0, 32, 20);
1196 }
1197 return 0;
1198}
1199
1200static int snd_intel8x0_playback_close(struct snd_pcm_substream *substream)
1201{
1202 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1203
1204 chip->ichd[ICHD_PCMOUT].substream = NULL;
1205 return 0;
1206}
1207
1208static int snd_intel8x0_capture_open(struct snd_pcm_substream *substream)
1209{
1210 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1211
1212 return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_PCMIN]);
1213}
1214
1215static int snd_intel8x0_capture_close(struct snd_pcm_substream *substream)
1216{
1217 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1218
1219 chip->ichd[ICHD_PCMIN].substream = NULL;
1220 return 0;
1221}
1222
1223static int snd_intel8x0_mic_open(struct snd_pcm_substream *substream)
1224{
1225 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1226
1227 return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_MIC]);
1228}
1229
1230static int snd_intel8x0_mic_close(struct snd_pcm_substream *substream)
1231{
1232 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1233
1234 chip->ichd[ICHD_MIC].substream = NULL;
1235 return 0;
1236}
1237
1238static int snd_intel8x0_mic2_open(struct snd_pcm_substream *substream)
1239{
1240 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1241
1242 return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_MIC2]);
1243}
1244
1245static int snd_intel8x0_mic2_close(struct snd_pcm_substream *substream)
1246{
1247 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1248
1249 chip->ichd[ICHD_MIC2].substream = NULL;
1250 return 0;
1251}
1252
1253static int snd_intel8x0_capture2_open(struct snd_pcm_substream *substream)
1254{
1255 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1256
1257 return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_PCM2IN]);
1258}
1259
1260static int snd_intel8x0_capture2_close(struct snd_pcm_substream *substream)
1261{
1262 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1263
1264 chip->ichd[ICHD_PCM2IN].substream = NULL;
1265 return 0;
1266}
1267
1268static int snd_intel8x0_spdif_open(struct snd_pcm_substream *substream)
1269{
1270 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1271 int idx = chip->device_type == DEVICE_NFORCE ? NVD_SPBAR : ICHD_SPBAR;
1272
1273 return snd_intel8x0_pcm_open(substream, &chip->ichd[idx]);
1274}
1275
1276static int snd_intel8x0_spdif_close(struct snd_pcm_substream *substream)
1277{
1278 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1279 int idx = chip->device_type == DEVICE_NFORCE ? NVD_SPBAR : ICHD_SPBAR;
1280
1281 chip->ichd[idx].substream = NULL;
1282 return 0;
1283}
1284
1285static int snd_intel8x0_ali_ac97spdifout_open(struct snd_pcm_substream *substream)
1286{
1287 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1288 unsigned int val;
1289
1290 spin_lock_irq(&chip->reg_lock);
1291 val = igetdword(chip, ICHREG(ALI_INTERFACECR));
1292 val |= ICH_ALI_IF_AC97SP;
1293 iputdword(chip, ICHREG(ALI_INTERFACECR), val);
1294 /* also needs to set ALI_SC_CODEC_SPDF correctly */
1295 spin_unlock_irq(&chip->reg_lock);
1296
1297 return snd_intel8x0_pcm_open(substream, &chip->ichd[ALID_AC97SPDIFOUT]);
1298}
1299
1300static int snd_intel8x0_ali_ac97spdifout_close(struct snd_pcm_substream *substream)
1301{
1302 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1303 unsigned int val;
1304
1305 chip->ichd[ALID_AC97SPDIFOUT].substream = NULL;
1306 spin_lock_irq(&chip->reg_lock);
1307 val = igetdword(chip, ICHREG(ALI_INTERFACECR));
1308 val &= ~ICH_ALI_IF_AC97SP;
1309 iputdword(chip, ICHREG(ALI_INTERFACECR), val);
1310 spin_unlock_irq(&chip->reg_lock);
1311
1312 return 0;
1313}
1314
1315#if 0 // NYI
1316static int snd_intel8x0_ali_spdifin_open(struct snd_pcm_substream *substream)
1317{
1318 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1319
1320 return snd_intel8x0_pcm_open(substream, &chip->ichd[ALID_SPDIFIN]);
1321}
1322
1323static int snd_intel8x0_ali_spdifin_close(struct snd_pcm_substream *substream)
1324{
1325 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1326
1327 chip->ichd[ALID_SPDIFIN].substream = NULL;
1328 return 0;
1329}
1330
1331static int snd_intel8x0_ali_spdifout_open(struct snd_pcm_substream *substream)
1332{
1333 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1334
1335 return snd_intel8x0_pcm_open(substream, &chip->ichd[ALID_SPDIFOUT]);
1336}
1337
1338static int snd_intel8x0_ali_spdifout_close(struct snd_pcm_substream *substream)
1339{
1340 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1341
1342 chip->ichd[ALID_SPDIFOUT].substream = NULL;
1343 return 0;
1344}
1345#endif
1346
1347static struct snd_pcm_ops snd_intel8x0_playback_ops = {
1348 .open = snd_intel8x0_playback_open,
1349 .close = snd_intel8x0_playback_close,
1350 .ioctl = snd_pcm_lib_ioctl,
1351 .hw_params = snd_intel8x0_hw_params,
1352 .hw_free = snd_intel8x0_hw_free,
1353 .prepare = snd_intel8x0_pcm_prepare,
1354 .trigger = snd_intel8x0_pcm_trigger,
1355 .pointer = snd_intel8x0_pcm_pointer,
1356};
1357
1358static struct snd_pcm_ops snd_intel8x0_capture_ops = {
1359 .open = snd_intel8x0_capture_open,
1360 .close = snd_intel8x0_capture_close,
1361 .ioctl = snd_pcm_lib_ioctl,
1362 .hw_params = snd_intel8x0_hw_params,
1363 .hw_free = snd_intel8x0_hw_free,
1364 .prepare = snd_intel8x0_pcm_prepare,
1365 .trigger = snd_intel8x0_pcm_trigger,
1366 .pointer = snd_intel8x0_pcm_pointer,
1367};
1368
1369static struct snd_pcm_ops snd_intel8x0_capture_mic_ops = {
1370 .open = snd_intel8x0_mic_open,
1371 .close = snd_intel8x0_mic_close,
1372 .ioctl = snd_pcm_lib_ioctl,
1373 .hw_params = snd_intel8x0_hw_params,
1374 .hw_free = snd_intel8x0_hw_free,
1375 .prepare = snd_intel8x0_pcm_prepare,
1376 .trigger = snd_intel8x0_pcm_trigger,
1377 .pointer = snd_intel8x0_pcm_pointer,
1378};
1379
1380static struct snd_pcm_ops snd_intel8x0_capture_mic2_ops = {
1381 .open = snd_intel8x0_mic2_open,
1382 .close = snd_intel8x0_mic2_close,
1383 .ioctl = snd_pcm_lib_ioctl,
1384 .hw_params = snd_intel8x0_hw_params,
1385 .hw_free = snd_intel8x0_hw_free,
1386 .prepare = snd_intel8x0_pcm_prepare,
1387 .trigger = snd_intel8x0_pcm_trigger,
1388 .pointer = snd_intel8x0_pcm_pointer,
1389};
1390
1391static struct snd_pcm_ops snd_intel8x0_capture2_ops = {
1392 .open = snd_intel8x0_capture2_open,
1393 .close = snd_intel8x0_capture2_close,
1394 .ioctl = snd_pcm_lib_ioctl,
1395 .hw_params = snd_intel8x0_hw_params,
1396 .hw_free = snd_intel8x0_hw_free,
1397 .prepare = snd_intel8x0_pcm_prepare,
1398 .trigger = snd_intel8x0_pcm_trigger,
1399 .pointer = snd_intel8x0_pcm_pointer,
1400};
1401
1402static struct snd_pcm_ops snd_intel8x0_spdif_ops = {
1403 .open = snd_intel8x0_spdif_open,
1404 .close = snd_intel8x0_spdif_close,
1405 .ioctl = snd_pcm_lib_ioctl,
1406 .hw_params = snd_intel8x0_hw_params,
1407 .hw_free = snd_intel8x0_hw_free,
1408 .prepare = snd_intel8x0_pcm_prepare,
1409 .trigger = snd_intel8x0_pcm_trigger,
1410 .pointer = snd_intel8x0_pcm_pointer,
1411};
1412
1413static struct snd_pcm_ops snd_intel8x0_ali_playback_ops = {
1414 .open = snd_intel8x0_playback_open,
1415 .close = snd_intel8x0_playback_close,
1416 .ioctl = snd_pcm_lib_ioctl,
1417 .hw_params = snd_intel8x0_hw_params,
1418 .hw_free = snd_intel8x0_hw_free,
1419 .prepare = snd_intel8x0_pcm_prepare,
1420 .trigger = snd_intel8x0_ali_trigger,
1421 .pointer = snd_intel8x0_pcm_pointer,
1422};
1423
1424static struct snd_pcm_ops snd_intel8x0_ali_capture_ops = {
1425 .open = snd_intel8x0_capture_open,
1426 .close = snd_intel8x0_capture_close,
1427 .ioctl = snd_pcm_lib_ioctl,
1428 .hw_params = snd_intel8x0_hw_params,
1429 .hw_free = snd_intel8x0_hw_free,
1430 .prepare = snd_intel8x0_pcm_prepare,
1431 .trigger = snd_intel8x0_ali_trigger,
1432 .pointer = snd_intel8x0_pcm_pointer,
1433};
1434
1435static struct snd_pcm_ops snd_intel8x0_ali_capture_mic_ops = {
1436 .open = snd_intel8x0_mic_open,
1437 .close = snd_intel8x0_mic_close,
1438 .ioctl = snd_pcm_lib_ioctl,
1439 .hw_params = snd_intel8x0_hw_params,
1440 .hw_free = snd_intel8x0_hw_free,
1441 .prepare = snd_intel8x0_pcm_prepare,
1442 .trigger = snd_intel8x0_ali_trigger,
1443 .pointer = snd_intel8x0_pcm_pointer,
1444};
1445
1446static struct snd_pcm_ops snd_intel8x0_ali_ac97spdifout_ops = {
1447 .open = snd_intel8x0_ali_ac97spdifout_open,
1448 .close = snd_intel8x0_ali_ac97spdifout_close,
1449 .ioctl = snd_pcm_lib_ioctl,
1450 .hw_params = snd_intel8x0_hw_params,
1451 .hw_free = snd_intel8x0_hw_free,
1452 .prepare = snd_intel8x0_pcm_prepare,
1453 .trigger = snd_intel8x0_ali_trigger,
1454 .pointer = snd_intel8x0_pcm_pointer,
1455};
1456
1457#if 0 // NYI
1458static struct snd_pcm_ops snd_intel8x0_ali_spdifin_ops = {
1459 .open = snd_intel8x0_ali_spdifin_open,
1460 .close = snd_intel8x0_ali_spdifin_close,
1461 .ioctl = snd_pcm_lib_ioctl,
1462 .hw_params = snd_intel8x0_hw_params,
1463 .hw_free = snd_intel8x0_hw_free,
1464 .prepare = snd_intel8x0_pcm_prepare,
1465 .trigger = snd_intel8x0_pcm_trigger,
1466 .pointer = snd_intel8x0_pcm_pointer,
1467};
1468
1469static struct snd_pcm_ops snd_intel8x0_ali_spdifout_ops = {
1470 .open = snd_intel8x0_ali_spdifout_open,
1471 .close = snd_intel8x0_ali_spdifout_close,
1472 .ioctl = snd_pcm_lib_ioctl,
1473 .hw_params = snd_intel8x0_hw_params,
1474 .hw_free = snd_intel8x0_hw_free,
1475 .prepare = snd_intel8x0_pcm_prepare,
1476 .trigger = snd_intel8x0_pcm_trigger,
1477 .pointer = snd_intel8x0_pcm_pointer,
1478};
1479#endif // NYI
1480
1481struct ich_pcm_table {
1482 char *suffix;
1483 struct snd_pcm_ops *playback_ops;
1484 struct snd_pcm_ops *capture_ops;
1485 size_t prealloc_size;
1486 size_t prealloc_max_size;
1487 int ac97_idx;
1488};
1489
1490static int __devinit snd_intel8x0_pcm1(struct intel8x0 *chip, int device,
1491 struct ich_pcm_table *rec)
1492{
1493 struct snd_pcm *pcm;
1494 int err;
1495 char name[32];
1496
1497 if (rec->suffix)
1498 sprintf(name, "Intel ICH - %s", rec->suffix);
1499 else
1500 strcpy(name, "Intel ICH");
1501 err = snd_pcm_new(chip->card, name, device,
1502 rec->playback_ops ? 1 : 0,
1503 rec->capture_ops ? 1 : 0, &pcm);
1504 if (err < 0)
1505 return err;
1506
1507 if (rec->playback_ops)
1508 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, rec->playback_ops);
1509 if (rec->capture_ops)
1510 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, rec->capture_ops);
1511
1512 pcm->private_data = chip;
1513 pcm->info_flags = 0;
1514 if (rec->suffix)
1515 sprintf(pcm->name, "%s - %s", chip->card->shortname, rec->suffix);
1516 else
1517 strcpy(pcm->name, chip->card->shortname);
1518 chip->pcm[device] = pcm;
1519
1520 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1521 snd_dma_pci_data(chip->pci),
1522 rec->prealloc_size, rec->prealloc_max_size);
1523
1524 return 0;
1525}
1526
1527static struct ich_pcm_table intel_pcms[] __devinitdata = {
1528 {
1529 .playback_ops = &snd_intel8x0_playback_ops,
1530 .capture_ops = &snd_intel8x0_capture_ops,
1531 .prealloc_size = 64 * 1024,
1532 .prealloc_max_size = 128 * 1024,
1533 },
1534 {
1535 .suffix = "MIC ADC",
1536 .capture_ops = &snd_intel8x0_capture_mic_ops,
1537 .prealloc_size = 0,
1538 .prealloc_max_size = 128 * 1024,
1539 .ac97_idx = ICHD_MIC,
1540 },
1541 {
1542 .suffix = "MIC2 ADC",
1543 .capture_ops = &snd_intel8x0_capture_mic2_ops,
1544 .prealloc_size = 0,
1545 .prealloc_max_size = 128 * 1024,
1546 .ac97_idx = ICHD_MIC2,
1547 },
1548 {
1549 .suffix = "ADC2",
1550 .capture_ops = &snd_intel8x0_capture2_ops,
1551 .prealloc_size = 0,
1552 .prealloc_max_size = 128 * 1024,
1553 .ac97_idx = ICHD_PCM2IN,
1554 },
1555 {
1556 .suffix = "IEC958",
1557 .playback_ops = &snd_intel8x0_spdif_ops,
1558 .prealloc_size = 64 * 1024,
1559 .prealloc_max_size = 128 * 1024,
1560 .ac97_idx = ICHD_SPBAR,
1561 },
1562};
1563
1564static struct ich_pcm_table nforce_pcms[] __devinitdata = {
1565 {
1566 .playback_ops = &snd_intel8x0_playback_ops,
1567 .capture_ops = &snd_intel8x0_capture_ops,
1568 .prealloc_size = 64 * 1024,
1569 .prealloc_max_size = 128 * 1024,
1570 },
1571 {
1572 .suffix = "MIC ADC",
1573 .capture_ops = &snd_intel8x0_capture_mic_ops,
1574 .prealloc_size = 0,
1575 .prealloc_max_size = 128 * 1024,
1576 .ac97_idx = NVD_MIC,
1577 },
1578 {
1579 .suffix = "IEC958",
1580 .playback_ops = &snd_intel8x0_spdif_ops,
1581 .prealloc_size = 64 * 1024,
1582 .prealloc_max_size = 128 * 1024,
1583 .ac97_idx = NVD_SPBAR,
1584 },
1585};
1586
1587static struct ich_pcm_table ali_pcms[] __devinitdata = {
1588 {
1589 .playback_ops = &snd_intel8x0_ali_playback_ops,
1590 .capture_ops = &snd_intel8x0_ali_capture_ops,
1591 .prealloc_size = 64 * 1024,
1592 .prealloc_max_size = 128 * 1024,
1593 },
1594 {
1595 .suffix = "MIC ADC",
1596 .capture_ops = &snd_intel8x0_ali_capture_mic_ops,
1597 .prealloc_size = 0,
1598 .prealloc_max_size = 128 * 1024,
1599 .ac97_idx = ALID_MIC,
1600 },
1601 {
1602 .suffix = "IEC958",
1603 .playback_ops = &snd_intel8x0_ali_ac97spdifout_ops,
1604 /* .capture_ops = &snd_intel8x0_ali_spdifin_ops, */
1605 .prealloc_size = 64 * 1024,
1606 .prealloc_max_size = 128 * 1024,
1607 .ac97_idx = ALID_AC97SPDIFOUT,
1608 },
1609#if 0 // NYI
1610 {
1611 .suffix = "HW IEC958",
1612 .playback_ops = &snd_intel8x0_ali_spdifout_ops,
1613 .prealloc_size = 64 * 1024,
1614 .prealloc_max_size = 128 * 1024,
1615 },
1616#endif
1617};
1618
1619static int __devinit snd_intel8x0_pcm(struct intel8x0 *chip)
1620{
1621 int i, tblsize, device, err;
1622 struct ich_pcm_table *tbl, *rec;
1623
1624 switch (chip->device_type) {
1625 case DEVICE_INTEL_ICH4:
1626 tbl = intel_pcms;
1627 tblsize = ARRAY_SIZE(intel_pcms);
1628 if (spdif_aclink)
1629 tblsize--;
1630 break;
1631 case DEVICE_NFORCE:
1632 tbl = nforce_pcms;
1633 tblsize = ARRAY_SIZE(nforce_pcms);
1634 if (spdif_aclink)
1635 tblsize--;
1636 break;
1637 case DEVICE_ALI:
1638 tbl = ali_pcms;
1639 tblsize = ARRAY_SIZE(ali_pcms);
1640 break;
1641 default:
1642 tbl = intel_pcms;
1643 tblsize = 2;
1644 break;
1645 }
1646
1647 device = 0;
1648 for (i = 0; i < tblsize; i++) {
1649 rec = tbl + i;
1650 if (i > 0 && rec->ac97_idx) {
1651 /* activate PCM only when associated AC'97 codec */
1652 if (! chip->ichd[rec->ac97_idx].pcm)
1653 continue;
1654 }
1655 err = snd_intel8x0_pcm1(chip, device, rec);
1656 if (err < 0)
1657 return err;
1658 device++;
1659 }
1660
1661 chip->pcm_devs = device;
1662 return 0;
1663}
1664
1665
1666/*
1667 * Mixer part
1668 */
1669
1670static void snd_intel8x0_mixer_free_ac97_bus(struct snd_ac97_bus *bus)
1671{
1672 struct intel8x0 *chip = bus->private_data;
1673 chip->ac97_bus = NULL;
1674}
1675
1676static void snd_intel8x0_mixer_free_ac97(struct snd_ac97 *ac97)
1677{
1678 struct intel8x0 *chip = ac97->private_data;
1679 chip->ac97[ac97->num] = NULL;
1680}
1681
1682static struct ac97_pcm ac97_pcm_defs[] __devinitdata = {
1683 /* front PCM */
1684 {
1685 .exclusive = 1,
1686 .r =
1687 {
1688 {
1689 .slots = (1 << AC97_SLOT_PCM_LEFT) |
1690 (1 << AC97_SLOT_PCM_RIGHT) |
1691 (1 << AC97_SLOT_PCM_CENTER) |
1692 (1 << AC97_SLOT_PCM_SLEFT) |
1693 (1 << AC97_SLOT_PCM_SRIGHT) |
1694 (1 << AC97_SLOT_LFE)
1695 },
1696 {
1697 .slots = (1 << AC97_SLOT_PCM_LEFT) |
1698 (1 << AC97_SLOT_PCM_RIGHT) |
1699 (1 << AC97_SLOT_PCM_LEFT_0) |
1700 (1 << AC97_SLOT_PCM_RIGHT_0)
1701 }
1702 }
1703 },
1704 /* PCM IN #1 */
1705 {
1706 .stream = 1,
1707 .exclusive = 1,
1708 .r = { {
1709 .slots = (1 << AC97_SLOT_PCM_LEFT) |
1710 (1 << AC97_SLOT_PCM_RIGHT)
1711 }
1712 }
1713 },
1714 /* MIC IN #1 */
1715 {
1716 .stream = 1,
1717 .exclusive = 1,
1718 .r = { {
1719 .slots = (1 << AC97_SLOT_MIC)
1720 }
1721 }
1722 },
1723 /* S/PDIF PCM */
1724 {
1725 .exclusive = 1,
1726 .spdif = 1,
1727 .r = { {
1728 .slots = (1 << AC97_SLOT_SPDIF_LEFT2) |
1729 (1 << AC97_SLOT_SPDIF_RIGHT2)
1730 }
1731 }
1732 },
1733 /* PCM IN #2 */
1734 {
1735 .stream = 1,
1736 .exclusive = 1,
1737 .r = { {
1738 .slots = (1 << AC97_SLOT_PCM_LEFT) |
1739 (1 << AC97_SLOT_PCM_RIGHT)
1740 }
1741 }
1742 },
1743 /* MIC IN #2 */
1744 {
1745 .stream = 1,
1746 .exclusive = 1,
1747 .r = { {
1748 .slots = (1 << AC97_SLOT_MIC)
1749 }
1750 }
1751 },
1752};
1753
1754static struct ac97_quirk ac97_quirks[] __devinitdata = {
1755 {
1756 .subvendor = 0x0e11,
1757 .subdevice = 0x000e,
1758 .name = "Compaq Deskpro EN", /* AD1885 */
1759 .type = AC97_TUNE_HP_ONLY
1760 },
1761 {
1762 .subvendor = 0x0e11,
1763 .subdevice = 0x008a,
1764 .name = "Compaq Evo W4000", /* AD1885 */
1765 .type = AC97_TUNE_HP_ONLY
1766 },
1767 {
1768 .subvendor = 0x0e11,
1769 .subdevice = 0x00b8,
1770 .name = "Compaq Evo D510C",
1771 .type = AC97_TUNE_HP_ONLY
1772 },
1773 {
1774 .subvendor = 0x0e11,
1775 .subdevice = 0x0860,
1776 .name = "HP/Compaq nx7010",
1777 .type = AC97_TUNE_MUTE_LED
1778 },
1779 {
1780 .subvendor = 0x1014,
1781 .subdevice = 0x1f00,
1782 .name = "MS-9128",
1783 .type = AC97_TUNE_ALC_JACK
1784 },
1785 {
1786 .subvendor = 0x1014,
1787 .subdevice = 0x0267,
1788 .name = "IBM NetVista A30p", /* AD1981B */
1789 .type = AC97_TUNE_HP_ONLY
1790 },
1791 {
1792 .subvendor = 0x1025,
1793 .subdevice = 0x0082,
1794 .name = "Acer Travelmate 2310",
1795 .type = AC97_TUNE_HP_ONLY
1796 },
1797 {
1798 .subvendor = 0x1025,
1799 .subdevice = 0x0083,
1800 .name = "Acer Aspire 3003LCi",
1801 .type = AC97_TUNE_HP_ONLY
1802 },
1803 {
1804 .subvendor = 0x1028,
1805 .subdevice = 0x00d8,
1806 .name = "Dell Precision 530", /* AD1885 */
1807 .type = AC97_TUNE_HP_ONLY
1808 },
1809 {
1810 .subvendor = 0x1028,
1811 .subdevice = 0x010d,
1812 .name = "Dell", /* which model? AD1885 */
1813 .type = AC97_TUNE_HP_ONLY
1814 },
1815 {
1816 .subvendor = 0x1028,
1817 .subdevice = 0x0126,
1818 .name = "Dell Optiplex GX260", /* AD1981A */
1819 .type = AC97_TUNE_HP_ONLY
1820 },
1821 {
1822 .subvendor = 0x1028,
1823 .subdevice = 0x012c,
1824 .name = "Dell Precision 650", /* AD1981A */
1825 .type = AC97_TUNE_HP_ONLY
1826 },
1827 {
1828 .subvendor = 0x1028,
1829 .subdevice = 0x012d,
1830 .name = "Dell Precision 450", /* AD1981B*/
1831 .type = AC97_TUNE_HP_ONLY
1832 },
1833 {
1834 .subvendor = 0x1028,
1835 .subdevice = 0x0147,
1836 .name = "Dell", /* which model? AD1981B*/
1837 .type = AC97_TUNE_HP_ONLY
1838 },
1839 {
1840 .subvendor = 0x1028,
1841 .subdevice = 0x0151,
1842 .name = "Dell Optiplex GX270", /* AD1981B */
1843 .type = AC97_TUNE_HP_ONLY
1844 },
1845 {
1846 .subvendor = 0x1028,
1847 .subdevice = 0x014e,
1848 .name = "Dell D800", /* STAC9750/51 */
1849 .type = AC97_TUNE_HP_ONLY
1850 },
1851 {
1852 .subvendor = 0x1028,
1853 .subdevice = 0x0163,
1854 .name = "Dell Unknown", /* STAC9750/51 */
1855 .type = AC97_TUNE_HP_ONLY
1856 },
1857 {
1858 .subvendor = 0x1028,
1859 .subdevice = 0x016a,
1860 .name = "Dell Inspiron 8600", /* STAC9750/51 */
1861 .type = AC97_TUNE_HP_ONLY
1862 },
1863 {
1864 .subvendor = 0x1028,
1865 .subdevice = 0x0186,
1866 .name = "Dell Latitude D810", /* cf. Malone #41015 */
1867 .type = AC97_TUNE_HP_MUTE_LED
1868 },
1869 {
1870 .subvendor = 0x1028,
1871 .subdevice = 0x0188,
1872 .name = "Dell Inspiron 6000",
1873 .type = AC97_TUNE_HP_MUTE_LED /* cf. Malone #41015 */
1874 },
1875 {
1876 .subvendor = 0x1028,
1877 .subdevice = 0x0191,
1878 .name = "Dell Inspiron 8600",
1879 .type = AC97_TUNE_HP_ONLY
1880 },
1881 {
1882 .subvendor = 0x103c,
1883 .subdevice = 0x006d,
1884 .name = "HP zv5000",
1885 .type = AC97_TUNE_MUTE_LED /*AD1981B*/
1886 },
1887 { /* FIXME: which codec? */
1888 .subvendor = 0x103c,
1889 .subdevice = 0x00c3,
1890 .name = "HP xw6000",
1891 .type = AC97_TUNE_HP_ONLY
1892 },
1893 {
1894 .subvendor = 0x103c,
1895 .subdevice = 0x088c,
1896 .name = "HP nc8000",
1897 .type = AC97_TUNE_HP_MUTE_LED
1898 },
1899 {
1900 .subvendor = 0x103c,
1901 .subdevice = 0x0890,
1902 .name = "HP nc6000",
1903 .type = AC97_TUNE_MUTE_LED
1904 },
1905 {
1906 .subvendor = 0x103c,
1907 .subdevice = 0x129d,
1908 .name = "HP xw8000",
1909 .type = AC97_TUNE_HP_ONLY
1910 },
1911 {
1912 .subvendor = 0x103c,
1913 .subdevice = 0x0938,
1914 .name = "HP nc4200",
1915 .type = AC97_TUNE_HP_MUTE_LED
1916 },
1917 {
1918 .subvendor = 0x103c,
1919 .subdevice = 0x099c,
1920 .name = "HP nx6110/nc6120",
1921 .type = AC97_TUNE_HP_MUTE_LED
1922 },
1923 {
1924 .subvendor = 0x103c,
1925 .subdevice = 0x0944,
1926 .name = "HP nc6220",
1927 .type = AC97_TUNE_HP_MUTE_LED
1928 },
1929 {
1930 .subvendor = 0x103c,
1931 .subdevice = 0x0934,
1932 .name = "HP nc8220",
1933 .type = AC97_TUNE_HP_MUTE_LED
1934 },
1935 {
1936 .subvendor = 0x103c,
1937 .subdevice = 0x12f1,
1938 .name = "HP xw8200", /* AD1981B*/
1939 .type = AC97_TUNE_HP_ONLY
1940 },
1941 {
1942 .subvendor = 0x103c,
1943 .subdevice = 0x12f2,
1944 .name = "HP xw6200",
1945 .type = AC97_TUNE_HP_ONLY
1946 },
1947 {
1948 .subvendor = 0x103c,
1949 .subdevice = 0x3008,
1950 .name = "HP xw4200", /* AD1981B*/
1951 .type = AC97_TUNE_HP_ONLY
1952 },
1953 {
1954 .subvendor = 0x104d,
1955 .subdevice = 0x8197,
1956 .name = "Sony S1XP",
1957 .type = AC97_TUNE_INV_EAPD
1958 },
1959 {
1960 .subvendor = 0x1043,
1961 .subdevice = 0x80f3,
1962 .name = "ASUS ICH5/AD1985",
1963 .type = AC97_TUNE_AD_SHARING
1964 },
1965 {
1966 .subvendor = 0x10cf,
1967 .subdevice = 0x11c3,
1968 .name = "Fujitsu-Siemens E4010",
1969 .type = AC97_TUNE_HP_ONLY
1970 },
1971 {
1972 .subvendor = 0x10cf,
1973 .subdevice = 0x1225,
1974 .name = "Fujitsu-Siemens T3010",
1975 .type = AC97_TUNE_HP_ONLY
1976 },
1977 {
1978 .subvendor = 0x10cf,
1979 .subdevice = 0x1253,
1980 .name = "Fujitsu S6210", /* STAC9750/51 */
1981 .type = AC97_TUNE_HP_ONLY
1982 },
1983 {
1984 .subvendor = 0x10cf,
1985 .subdevice = 0x127d,
1986 .name = "Fujitsu Lifebook P7010",
1987 .type = AC97_TUNE_HP_ONLY
1988 },
1989 {
1990 .subvendor = 0x10cf,
1991 .subdevice = 0x127e,
1992 .name = "Fujitsu Lifebook C1211D",
1993 .type = AC97_TUNE_HP_ONLY
1994 },
1995 {
1996 .subvendor = 0x10cf,
1997 .subdevice = 0x12ec,
1998 .name = "Fujitsu-Siemens 4010",
1999 .type = AC97_TUNE_HP_ONLY
2000 },
2001 {
2002 .subvendor = 0x10cf,
2003 .subdevice = 0x12f2,
2004 .name = "Fujitsu-Siemens Celsius H320",
2005 .type = AC97_TUNE_SWAP_HP
2006 },
2007 {
2008 .subvendor = 0x10f1,
2009 .subdevice = 0x2665,
2010 .name = "Fujitsu-Siemens Celsius", /* AD1981? */
2011 .type = AC97_TUNE_HP_ONLY
2012 },
2013 {
2014 .subvendor = 0x10f1,
2015 .subdevice = 0x2885,
2016 .name = "AMD64 Mobo", /* ALC650 */
2017 .type = AC97_TUNE_HP_ONLY
2018 },
2019 {
2020 .subvendor = 0x10f1,
2021 .subdevice = 0x2895,
2022 .name = "Tyan Thunder K8WE",
2023 .type = AC97_TUNE_HP_ONLY
2024 },
2025 {
2026 .subvendor = 0x10f7,
2027 .subdevice = 0x834c,
2028 .name = "Panasonic CF-R4",
2029 .type = AC97_TUNE_HP_ONLY,
2030 },
2031 {
2032 .subvendor = 0x110a,
2033 .subdevice = 0x0056,
2034 .name = "Fujitsu-Siemens Scenic", /* AD1981? */
2035 .type = AC97_TUNE_HP_ONLY
2036 },
2037 {
2038 .subvendor = 0x11d4,
2039 .subdevice = 0x5375,
2040 .name = "ADI AD1985 (discrete)",
2041 .type = AC97_TUNE_HP_ONLY
2042 },
2043 {
2044 .subvendor = 0x1462,
2045 .subdevice = 0x5470,
2046 .name = "MSI P4 ATX 645 Ultra",
2047 .type = AC97_TUNE_HP_ONLY
2048 },
2049 {
2050 .subvendor = 0x1734,
2051 .subdevice = 0x0088,
2052 .name = "Fujitsu-Siemens D1522", /* AD1981 */
2053 .type = AC97_TUNE_HP_ONLY
2054 },
2055 {
2056 .subvendor = 0x8086,
2057 .subdevice = 0x2000,
2058 .mask = 0xfff0,
2059 .name = "Intel ICH5/AD1985",
2060 .type = AC97_TUNE_AD_SHARING
2061 },
2062 {
2063 .subvendor = 0x8086,
2064 .subdevice = 0x4000,
2065 .mask = 0xfff0,
2066 .name = "Intel ICH5/AD1985",
2067 .type = AC97_TUNE_AD_SHARING
2068 },
2069 {
2070 .subvendor = 0x8086,
2071 .subdevice = 0x4856,
2072 .name = "Intel D845WN (82801BA)",
2073 .type = AC97_TUNE_SWAP_HP
2074 },
2075 {
2076 .subvendor = 0x8086,
2077 .subdevice = 0x4d44,
2078 .name = "Intel D850EMV2", /* AD1885 */
2079 .type = AC97_TUNE_HP_ONLY
2080 },
2081 {
2082 .subvendor = 0x8086,
2083 .subdevice = 0x4d56,
2084 .name = "Intel ICH/AD1885",
2085 .type = AC97_TUNE_HP_ONLY
2086 },
2087 {
2088 .subvendor = 0x8086,
2089 .subdevice = 0x6000,
2090 .mask = 0xfff0,
2091 .name = "Intel ICH5/AD1985",
2092 .type = AC97_TUNE_AD_SHARING
2093 },
2094 {
2095 .subvendor = 0x8086,
2096 .subdevice = 0xe000,
2097 .mask = 0xfff0,
2098 .name = "Intel ICH5/AD1985",
2099 .type = AC97_TUNE_AD_SHARING
2100 },
2101#if 0 /* FIXME: this seems wrong on most boards */
2102 {
2103 .subvendor = 0x8086,
2104 .subdevice = 0xa000,
2105 .mask = 0xfff0,
2106 .name = "Intel ICH5/AD1985",
2107 .type = AC97_TUNE_HP_ONLY
2108 },
2109#endif
2110 {0} /* terminator */
2111};
2112
2113static int __devinit snd_intel8x0_mixer(struct intel8x0 *chip, int ac97_clock,
2114 const char *quirk_override)
2115{
2116 struct snd_ac97_bus *pbus;
2117 struct snd_ac97_template ac97;
2118 int err;
2119 unsigned int i, codecs;
2120 unsigned int glob_sta = 0;
2121 struct snd_ac97_bus_ops *ops;
2122 static struct snd_ac97_bus_ops standard_bus_ops = {
2123 .write = snd_intel8x0_codec_write,
2124 .read = snd_intel8x0_codec_read,
2125 };
2126 static struct snd_ac97_bus_ops ali_bus_ops = {
2127 .write = snd_intel8x0_ali_codec_write,
2128 .read = snd_intel8x0_ali_codec_read,
2129 };
2130
2131 chip->spdif_idx = -1; /* use PCMOUT (or disabled) */
2132 if (!spdif_aclink) {
2133 switch (chip->device_type) {
2134 case DEVICE_NFORCE:
2135 chip->spdif_idx = NVD_SPBAR;
2136 break;
2137 case DEVICE_ALI:
2138 chip->spdif_idx = ALID_AC97SPDIFOUT;
2139 break;
2140 case DEVICE_INTEL_ICH4:
2141 chip->spdif_idx = ICHD_SPBAR;
2142 break;
2143 };
2144 }
2145
2146 chip->in_ac97_init = 1;
2147
2148 memset(&ac97, 0, sizeof(ac97));
2149 ac97.private_data = chip;
2150 ac97.private_free = snd_intel8x0_mixer_free_ac97;
2151 ac97.scaps = AC97_SCAP_SKIP_MODEM | AC97_SCAP_POWER_SAVE;
2152 if (chip->xbox)
2153 ac97.scaps |= AC97_SCAP_DETECT_BY_VENDOR;
2154 if (chip->device_type != DEVICE_ALI) {
2155 glob_sta = igetdword(chip, ICHREG(GLOB_STA));
2156 ops = &standard_bus_ops;
2157 chip->in_sdin_init = 1;
2158 codecs = 0;
2159 for (i = 0; i < chip->max_codecs; i++) {
2160 if (! (glob_sta & chip->codec_bit[i]))
2161 continue;
2162 if (chip->device_type == DEVICE_INTEL_ICH4) {
2163 snd_intel8x0_codec_read_test(chip, codecs);
2164 chip->ac97_sdin[codecs] =
2165 igetbyte(chip, ICHREG(SDM)) & ICH_LDI_MASK;
2166 if (snd_BUG_ON(chip->ac97_sdin[codecs] >= 3))
2167 chip->ac97_sdin[codecs] = 0;
2168 } else
2169 chip->ac97_sdin[codecs] = i;
2170 codecs++;
2171 }
2172 chip->in_sdin_init = 0;
2173 if (! codecs)
2174 codecs = 1;
2175 } else {
2176 ops = &ali_bus_ops;
2177 codecs = 1;
2178 /* detect the secondary codec */
2179 for (i = 0; i < 100; i++) {
2180 unsigned int reg = igetdword(chip, ICHREG(ALI_RTSR));
2181 if (reg & 0x40) {
2182 codecs = 2;
2183 break;
2184 }
2185 iputdword(chip, ICHREG(ALI_RTSR), reg | 0x40);
2186 udelay(1);
2187 }
2188 }
2189 if ((err = snd_ac97_bus(chip->card, 0, ops, chip, &pbus)) < 0)
2190 goto __err;
2191 pbus->private_free = snd_intel8x0_mixer_free_ac97_bus;
2192 if (ac97_clock >= 8000 && ac97_clock <= 48000)
2193 pbus->clock = ac97_clock;
2194 /* FIXME: my test board doesn't work well with VRA... */
2195 if (chip->device_type == DEVICE_ALI)
2196 pbus->no_vra = 1;
2197 else
2198 pbus->dra = 1;
2199 chip->ac97_bus = pbus;
2200 chip->ncodecs = codecs;
2201
2202 ac97.pci = chip->pci;
2203 for (i = 0; i < codecs; i++) {
2204 ac97.num = i;
2205 if ((err = snd_ac97_mixer(pbus, &ac97, &chip->ac97[i])) < 0) {
2206 if (err != -EACCES)
2207 snd_printk(KERN_ERR "Unable to initialize codec #%d\n", i);
2208 if (i == 0)
2209 goto __err;
2210 }
2211 }
2212 /* tune up the primary codec */
2213 snd_ac97_tune_hardware(chip->ac97[0], ac97_quirks, quirk_override);
2214 /* enable separate SDINs for ICH4 */
2215 if (chip->device_type == DEVICE_INTEL_ICH4)
2216 pbus->isdin = 1;
2217 /* find the available PCM streams */
2218 i = ARRAY_SIZE(ac97_pcm_defs);
2219 if (chip->device_type != DEVICE_INTEL_ICH4)
2220 i -= 2; /* do not allocate PCM2IN and MIC2 */
2221 if (chip->spdif_idx < 0)
2222 i--; /* do not allocate S/PDIF */
2223 err = snd_ac97_pcm_assign(pbus, i, ac97_pcm_defs);
2224 if (err < 0)
2225 goto __err;
2226 chip->ichd[ICHD_PCMOUT].pcm = &pbus->pcms[0];
2227 chip->ichd[ICHD_PCMIN].pcm = &pbus->pcms[1];
2228 chip->ichd[ICHD_MIC].pcm = &pbus->pcms[2];
2229 if (chip->spdif_idx >= 0)
2230 chip->ichd[chip->spdif_idx].pcm = &pbus->pcms[3];
2231 if (chip->device_type == DEVICE_INTEL_ICH4) {
2232 chip->ichd[ICHD_PCM2IN].pcm = &pbus->pcms[4];
2233 chip->ichd[ICHD_MIC2].pcm = &pbus->pcms[5];
2234 }
2235 /* enable separate SDINs for ICH4 */
2236 if (chip->device_type == DEVICE_INTEL_ICH4) {
2237 struct ac97_pcm *pcm = chip->ichd[ICHD_PCM2IN].pcm;
2238 u8 tmp = igetbyte(chip, ICHREG(SDM));
2239 tmp &= ~(ICH_DI2L_MASK|ICH_DI1L_MASK);
2240 if (pcm) {
2241 tmp |= ICH_SE; /* steer enable for multiple SDINs */
2242 tmp |= chip->ac97_sdin[0] << ICH_DI1L_SHIFT;
2243 for (i = 1; i < 4; i++) {
2244 if (pcm->r[0].codec[i]) {
2245 tmp |= chip->ac97_sdin[pcm->r[0].codec[1]->num] << ICH_DI2L_SHIFT;
2246 break;
2247 }
2248 }
2249 } else {
2250 tmp &= ~ICH_SE; /* steer disable */
2251 }
2252 iputbyte(chip, ICHREG(SDM), tmp);
2253 }
2254 if (pbus->pcms[0].r[0].slots & (1 << AC97_SLOT_PCM_SLEFT)) {
2255 chip->multi4 = 1;
2256 if (pbus->pcms[0].r[0].slots & (1 << AC97_SLOT_LFE)) {
2257 chip->multi6 = 1;
2258 if (chip->ac97[0]->flags & AC97_HAS_8CH)
2259 chip->multi8 = 1;
2260 }
2261 }
2262 if (pbus->pcms[0].r[1].rslots[0]) {
2263 chip->dra = 1;
2264 }
2265 if (chip->device_type == DEVICE_INTEL_ICH4) {
2266 if ((igetdword(chip, ICHREG(GLOB_STA)) & ICH_SAMPLE_CAP) == ICH_SAMPLE_16_20)
2267 chip->smp20bit = 1;
2268 }
2269 if (chip->device_type == DEVICE_NFORCE && !spdif_aclink) {
2270 /* 48kHz only */
2271 chip->ichd[chip->spdif_idx].pcm->rates = SNDRV_PCM_RATE_48000;
2272 }
2273 if (chip->device_type == DEVICE_INTEL_ICH4 && !spdif_aclink) {
2274 /* use slot 10/11 for SPDIF */
2275 u32 val;
2276 val = igetdword(chip, ICHREG(GLOB_CNT)) & ~ICH_PCM_SPDIF_MASK;
2277 val |= ICH_PCM_SPDIF_1011;
2278 iputdword(chip, ICHREG(GLOB_CNT), val);
2279 snd_ac97_update_bits(chip->ac97[0], AC97_EXTENDED_STATUS, 0x03 << 4, 0x03 << 4);
2280 }
2281 chip->in_ac97_init = 0;
2282 return 0;
2283
2284 __err:
2285 /* clear the cold-reset bit for the next chance */
2286 if (chip->device_type != DEVICE_ALI)
2287 iputdword(chip, ICHREG(GLOB_CNT),
2288 igetdword(chip, ICHREG(GLOB_CNT)) & ~ICH_AC97COLD);
2289 return err;
2290}
2291
2292
2293/*
2294 *
2295 */
2296
2297static void do_ali_reset(struct intel8x0 *chip)
2298{
2299 iputdword(chip, ICHREG(ALI_SCR), ICH_ALI_SC_RESET);
2300 iputdword(chip, ICHREG(ALI_FIFOCR1), 0x83838383);
2301 iputdword(chip, ICHREG(ALI_FIFOCR2), 0x83838383);
2302 iputdword(chip, ICHREG(ALI_FIFOCR3), 0x83838383);
2303 iputdword(chip, ICHREG(ALI_INTERFACECR),
2304 ICH_ALI_IF_PI|ICH_ALI_IF_PO);
2305 iputdword(chip, ICHREG(ALI_INTERRUPTCR), 0x00000000);
2306 iputdword(chip, ICHREG(ALI_INTERRUPTSR), 0x00000000);
2307}
2308
2309#ifdef CONFIG_SND_AC97_POWER_SAVE
2310static struct snd_pci_quirk ich_chip_reset_mode[] = {
2311 SND_PCI_QUIRK(0x1014, 0x051f, "Thinkpad R32", 1),
2312 { } /* end */
2313};
2314
2315static int snd_intel8x0_ich_chip_cold_reset(struct intel8x0 *chip)
2316{
2317 unsigned int cnt;
2318 /* ACLink on, 2 channels */
2319
2320 if (snd_pci_quirk_lookup(chip->pci, ich_chip_reset_mode))
2321 return -EIO;
2322
2323 cnt = igetdword(chip, ICHREG(GLOB_CNT));
2324 cnt &= ~(ICH_ACLINK | ICH_PCM_246_MASK);
2325
2326 /* do cold reset - the full ac97 powerdown may leave the controller
2327 * in a warm state but actually it cannot communicate with the codec.
2328 */
2329 iputdword(chip, ICHREG(GLOB_CNT), cnt & ~ICH_AC97COLD);
2330 cnt = igetdword(chip, ICHREG(GLOB_CNT));
2331 udelay(10);
2332 iputdword(chip, ICHREG(GLOB_CNT), cnt | ICH_AC97COLD);
2333 msleep(1);
2334 return 0;
2335}
2336#define snd_intel8x0_ich_chip_can_cold_reset(chip) \
2337 (!snd_pci_quirk_lookup(chip->pci, ich_chip_reset_mode))
2338#else
2339#define snd_intel8x0_ich_chip_cold_reset(chip) 0
2340#define snd_intel8x0_ich_chip_can_cold_reset(chip) (0)
2341#endif
2342
2343static int snd_intel8x0_ich_chip_reset(struct intel8x0 *chip)
2344{
2345 unsigned long end_time;
2346 unsigned int cnt;
2347 /* ACLink on, 2 channels */
2348 cnt = igetdword(chip, ICHREG(GLOB_CNT));
2349 cnt &= ~(ICH_ACLINK | ICH_PCM_246_MASK);
2350 /* finish cold or do warm reset */
2351 cnt |= (cnt & ICH_AC97COLD) == 0 ? ICH_AC97COLD : ICH_AC97WARM;
2352 iputdword(chip, ICHREG(GLOB_CNT), cnt);
2353 end_time = (jiffies + (HZ / 4)) + 1;
2354 do {
2355 if ((igetdword(chip, ICHREG(GLOB_CNT)) & ICH_AC97WARM) == 0)
2356 return 0;
2357 schedule_timeout_uninterruptible(1);
2358 } while (time_after_eq(end_time, jiffies));
2359 snd_printk(KERN_ERR "AC'97 warm reset still in progress? [0x%x]\n",
2360 igetdword(chip, ICHREG(GLOB_CNT)));
2361 return -EIO;
2362}
2363
2364static int snd_intel8x0_ich_chip_init(struct intel8x0 *chip, int probing)
2365{
2366 unsigned long end_time;
2367 unsigned int status, nstatus;
2368 unsigned int cnt;
2369 int err;
2370
2371 /* put logic to right state */
2372 /* first clear status bits */
2373 status = ICH_RCS | ICH_MCINT | ICH_POINT | ICH_PIINT;
2374 if (chip->device_type == DEVICE_NFORCE)
2375 status |= ICH_NVSPINT;
2376 cnt = igetdword(chip, ICHREG(GLOB_STA));
2377 iputdword(chip, ICHREG(GLOB_STA), cnt & status);
2378
2379 if (snd_intel8x0_ich_chip_can_cold_reset(chip))
2380 err = snd_intel8x0_ich_chip_cold_reset(chip);
2381 else
2382 err = snd_intel8x0_ich_chip_reset(chip);
2383 if (err < 0)
2384 return err;
2385
2386 if (probing) {
2387 /* wait for any codec ready status.
2388 * Once it becomes ready it should remain ready
2389 * as long as we do not disable the ac97 link.
2390 */
2391 end_time = jiffies + HZ;
2392 do {
2393 status = igetdword(chip, ICHREG(GLOB_STA)) &
2394 chip->codec_isr_bits;
2395 if (status)
2396 break;
2397 schedule_timeout_uninterruptible(1);
2398 } while (time_after_eq(end_time, jiffies));
2399 if (! status) {
2400 /* no codec is found */
2401 snd_printk(KERN_ERR "codec_ready: codec is not ready [0x%x]\n",
2402 igetdword(chip, ICHREG(GLOB_STA)));
2403 return -EIO;
2404 }
2405
2406 /* wait for other codecs ready status. */
2407 end_time = jiffies + HZ / 4;
2408 while (status != chip->codec_isr_bits &&
2409 time_after_eq(end_time, jiffies)) {
2410 schedule_timeout_uninterruptible(1);
2411 status |= igetdword(chip, ICHREG(GLOB_STA)) &
2412 chip->codec_isr_bits;
2413 }
2414
2415 } else {
2416 /* resume phase */
2417 int i;
2418 status = 0;
2419 for (i = 0; i < chip->ncodecs; i++)
2420 if (chip->ac97[i])
2421 status |= chip->codec_bit[chip->ac97_sdin[i]];
2422 /* wait until all the probed codecs are ready */
2423 end_time = jiffies + HZ;
2424 do {
2425 nstatus = igetdword(chip, ICHREG(GLOB_STA)) &
2426 chip->codec_isr_bits;
2427 if (status == nstatus)
2428 break;
2429 schedule_timeout_uninterruptible(1);
2430 } while (time_after_eq(end_time, jiffies));
2431 }
2432
2433 if (chip->device_type == DEVICE_SIS) {
2434 /* unmute the output on SIS7012 */
2435 iputword(chip, 0x4c, igetword(chip, 0x4c) | 1);
2436 }
2437 if (chip->device_type == DEVICE_NFORCE && !spdif_aclink) {
2438 /* enable SPDIF interrupt */
2439 unsigned int val;
2440 pci_read_config_dword(chip->pci, 0x4c, &val);
2441 val |= 0x1000000;
2442 pci_write_config_dword(chip->pci, 0x4c, val);
2443 }
2444 return 0;
2445}
2446
2447static int snd_intel8x0_ali_chip_init(struct intel8x0 *chip, int probing)
2448{
2449 u32 reg;
2450 int i = 0;
2451
2452 reg = igetdword(chip, ICHREG(ALI_SCR));
2453 if ((reg & 2) == 0) /* Cold required */
2454 reg |= 2;
2455 else
2456 reg |= 1; /* Warm */
2457 reg &= ~0x80000000; /* ACLink on */
2458 iputdword(chip, ICHREG(ALI_SCR), reg);
2459
2460 for (i = 0; i < HZ / 2; i++) {
2461 if (! (igetdword(chip, ICHREG(ALI_INTERRUPTSR)) & ALI_INT_GPIO))
2462 goto __ok;
2463 schedule_timeout_uninterruptible(1);
2464 }
2465 snd_printk(KERN_ERR "AC'97 reset failed.\n");
2466 if (probing)
2467 return -EIO;
2468
2469 __ok:
2470 for (i = 0; i < HZ / 2; i++) {
2471 reg = igetdword(chip, ICHREG(ALI_RTSR));
2472 if (reg & 0x80) /* primary codec */
2473 break;
2474 iputdword(chip, ICHREG(ALI_RTSR), reg | 0x80);
2475 schedule_timeout_uninterruptible(1);
2476 }
2477
2478 do_ali_reset(chip);
2479 return 0;
2480}
2481
2482static int snd_intel8x0_chip_init(struct intel8x0 *chip, int probing)
2483{
2484 unsigned int i, timeout;
2485 int err;
2486
2487 if (chip->device_type != DEVICE_ALI) {
2488 if ((err = snd_intel8x0_ich_chip_init(chip, probing)) < 0)
2489 return err;
2490 iagetword(chip, 0); /* clear semaphore flag */
2491 } else {
2492 if ((err = snd_intel8x0_ali_chip_init(chip, probing)) < 0)
2493 return err;
2494 }
2495
2496 /* disable interrupts */
2497 for (i = 0; i < chip->bdbars_count; i++)
2498 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, 0x00);
2499 /* reset channels */
2500 for (i = 0; i < chip->bdbars_count; i++)
2501 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, ICH_RESETREGS);
2502 for (i = 0; i < chip->bdbars_count; i++) {
2503 timeout = 100000;
2504 while (--timeout != 0) {
2505 if ((igetbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset) & ICH_RESETREGS) == 0)
2506 break;
2507 }
2508 if (timeout == 0)
2509 printk(KERN_ERR "intel8x0: reset of registers failed?\n");
2510 }
2511 /* initialize Buffer Descriptor Lists */
2512 for (i = 0; i < chip->bdbars_count; i++)
2513 iputdword(chip, ICH_REG_OFF_BDBAR + chip->ichd[i].reg_offset,
2514 chip->ichd[i].bdbar_addr);
2515 return 0;
2516}
2517
2518static int snd_intel8x0_free(struct intel8x0 *chip)
2519{
2520 unsigned int i;
2521
2522 if (chip->irq < 0)
2523 goto __hw_end;
2524 /* disable interrupts */
2525 for (i = 0; i < chip->bdbars_count; i++)
2526 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, 0x00);
2527 /* reset channels */
2528 for (i = 0; i < chip->bdbars_count; i++)
2529 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, ICH_RESETREGS);
2530 if (chip->device_type == DEVICE_NFORCE && !spdif_aclink) {
2531 /* stop the spdif interrupt */
2532 unsigned int val;
2533 pci_read_config_dword(chip->pci, 0x4c, &val);
2534 val &= ~0x1000000;
2535 pci_write_config_dword(chip->pci, 0x4c, val);
2536 }
2537 /* --- */
2538
2539 __hw_end:
2540 if (chip->irq >= 0)
2541 free_irq(chip->irq, chip);
2542 if (chip->bdbars.area) {
2543 if (chip->fix_nocache)
2544 fill_nocache(chip->bdbars.area, chip->bdbars.bytes, 0);
2545 snd_dma_free_pages(&chip->bdbars);
2546 }
2547 if (chip->addr)
2548 pci_iounmap(chip->pci, chip->addr);
2549 if (chip->bmaddr)
2550 pci_iounmap(chip->pci, chip->bmaddr);
2551 pci_release_regions(chip->pci);
2552 pci_disable_device(chip->pci);
2553 kfree(chip);
2554 return 0;
2555}
2556
2557#ifdef CONFIG_PM
2558/*
2559 * power management
2560 */
2561static int intel8x0_suspend(struct pci_dev *pci, pm_message_t state)
2562{
2563 struct snd_card *card = pci_get_drvdata(pci);
2564 struct intel8x0 *chip = card->private_data;
2565 int i;
2566
2567 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
2568 for (i = 0; i < chip->pcm_devs; i++)
2569 snd_pcm_suspend_all(chip->pcm[i]);
2570 /* clear nocache */
2571 if (chip->fix_nocache) {
2572 for (i = 0; i < chip->bdbars_count; i++) {
2573 struct ichdev *ichdev = &chip->ichd[i];
2574 if (ichdev->substream && ichdev->page_attr_changed) {
2575 struct snd_pcm_runtime *runtime = ichdev->substream->runtime;
2576 if (runtime->dma_area)
2577 fill_nocache(runtime->dma_area, runtime->dma_bytes, 0);
2578 }
2579 }
2580 }
2581 for (i = 0; i < chip->ncodecs; i++)
2582 snd_ac97_suspend(chip->ac97[i]);
2583 if (chip->device_type == DEVICE_INTEL_ICH4)
2584 chip->sdm_saved = igetbyte(chip, ICHREG(SDM));
2585
2586 if (chip->irq >= 0) {
2587 free_irq(chip->irq, chip);
2588 chip->irq = -1;
2589 }
2590 pci_disable_device(pci);
2591 pci_save_state(pci);
2592 /* The call below may disable built-in speaker on some laptops
2593 * after S2RAM. So, don't touch it.
2594 */
2595 /* pci_set_power_state(pci, pci_choose_state(pci, state)); */
2596 return 0;
2597}
2598
2599static int intel8x0_resume(struct pci_dev *pci)
2600{
2601 struct snd_card *card = pci_get_drvdata(pci);
2602 struct intel8x0 *chip = card->private_data;
2603 int i;
2604
2605 pci_set_power_state(pci, PCI_D0);
2606 pci_restore_state(pci);
2607 if (pci_enable_device(pci) < 0) {
2608 printk(KERN_ERR "intel8x0: pci_enable_device failed, "
2609 "disabling device\n");
2610 snd_card_disconnect(card);
2611 return -EIO;
2612 }
2613 pci_set_master(pci);
2614 snd_intel8x0_chip_init(chip, 0);
2615 if (request_irq(pci->irq, snd_intel8x0_interrupt,
2616 IRQF_SHARED, card->shortname, chip)) {
2617 printk(KERN_ERR "intel8x0: unable to grab IRQ %d, "
2618 "disabling device\n", pci->irq);
2619 snd_card_disconnect(card);
2620 return -EIO;
2621 }
2622 chip->irq = pci->irq;
2623 synchronize_irq(chip->irq);
2624
2625 /* re-initialize mixer stuff */
2626 if (chip->device_type == DEVICE_INTEL_ICH4 && !spdif_aclink) {
2627 /* enable separate SDINs for ICH4 */
2628 iputbyte(chip, ICHREG(SDM), chip->sdm_saved);
2629 /* use slot 10/11 for SPDIF */
2630 iputdword(chip, ICHREG(GLOB_CNT),
2631 (igetdword(chip, ICHREG(GLOB_CNT)) & ~ICH_PCM_SPDIF_MASK) |
2632 ICH_PCM_SPDIF_1011);
2633 }
2634
2635 /* refill nocache */
2636 if (chip->fix_nocache)
2637 fill_nocache(chip->bdbars.area, chip->bdbars.bytes, 1);
2638
2639 for (i = 0; i < chip->ncodecs; i++)
2640 snd_ac97_resume(chip->ac97[i]);
2641
2642 /* refill nocache */
2643 if (chip->fix_nocache) {
2644 for (i = 0; i < chip->bdbars_count; i++) {
2645 struct ichdev *ichdev = &chip->ichd[i];
2646 if (ichdev->substream && ichdev->page_attr_changed) {
2647 struct snd_pcm_runtime *runtime = ichdev->substream->runtime;
2648 if (runtime->dma_area)
2649 fill_nocache(runtime->dma_area, runtime->dma_bytes, 1);
2650 }
2651 }
2652 }
2653
2654 /* resume status */
2655 for (i = 0; i < chip->bdbars_count; i++) {
2656 struct ichdev *ichdev = &chip->ichd[i];
2657 unsigned long port = ichdev->reg_offset;
2658 if (! ichdev->substream || ! ichdev->suspended)
2659 continue;
2660 if (ichdev->ichd == ICHD_PCMOUT)
2661 snd_intel8x0_setup_pcm_out(chip, ichdev->substream->runtime);
2662 iputdword(chip, port + ICH_REG_OFF_BDBAR, ichdev->bdbar_addr);
2663 iputbyte(chip, port + ICH_REG_OFF_LVI, ichdev->lvi);
2664 iputbyte(chip, port + ICH_REG_OFF_CIV, ichdev->civ);
2665 iputbyte(chip, port + ichdev->roff_sr, ICH_FIFOE | ICH_BCIS | ICH_LVBCI);
2666 }
2667
2668 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
2669 return 0;
2670}
2671#endif /* CONFIG_PM */
2672
2673#define INTEL8X0_TESTBUF_SIZE 32768 /* enough large for one shot */
2674
2675static void __devinit intel8x0_measure_ac97_clock(struct intel8x0 *chip)
2676{
2677 struct snd_pcm_substream *subs;
2678 struct ichdev *ichdev;
2679 unsigned long port;
2680 unsigned long pos, pos1, t;
2681 int civ, timeout = 1000, attempt = 1;
2682 struct timespec start_time, stop_time;
2683
2684 if (chip->ac97_bus->clock != 48000)
2685 return; /* specified in module option */
2686
2687 __again:
2688 subs = chip->pcm[0]->streams[0].substream;
2689 if (! subs || subs->dma_buffer.bytes < INTEL8X0_TESTBUF_SIZE) {
2690 snd_printk(KERN_WARNING "no playback buffer allocated - aborting measure ac97 clock\n");
2691 return;
2692 }
2693 ichdev = &chip->ichd[ICHD_PCMOUT];
2694 ichdev->physbuf = subs->dma_buffer.addr;
2695 ichdev->size = ichdev->fragsize = INTEL8X0_TESTBUF_SIZE;
2696 ichdev->substream = NULL; /* don't process interrupts */
2697
2698 /* set rate */
2699 if (snd_ac97_set_rate(chip->ac97[0], AC97_PCM_FRONT_DAC_RATE, 48000) < 0) {
2700 snd_printk(KERN_ERR "cannot set ac97 rate: clock = %d\n", chip->ac97_bus->clock);
2701 return;
2702 }
2703 snd_intel8x0_setup_periods(chip, ichdev);
2704 port = ichdev->reg_offset;
2705 spin_lock_irq(&chip->reg_lock);
2706 chip->in_measurement = 1;
2707 /* trigger */
2708 if (chip->device_type != DEVICE_ALI)
2709 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_IOCE | ICH_STARTBM);
2710 else {
2711 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_IOCE);
2712 iputdword(chip, ICHREG(ALI_DMACR), 1 << ichdev->ali_slot);
2713 }
2714 do_posix_clock_monotonic_gettime(&start_time);
2715 spin_unlock_irq(&chip->reg_lock);
2716 msleep(50);
2717 spin_lock_irq(&chip->reg_lock);
2718 /* check the position */
2719 do {
2720 civ = igetbyte(chip, ichdev->reg_offset + ICH_REG_OFF_CIV);
2721 pos1 = igetword(chip, ichdev->reg_offset + ichdev->roff_picb);
2722 if (pos1 == 0) {
2723 udelay(10);
2724 continue;
2725 }
2726 if (civ == igetbyte(chip, ichdev->reg_offset + ICH_REG_OFF_CIV) &&
2727 pos1 == igetword(chip, ichdev->reg_offset + ichdev->roff_picb))
2728 break;
2729 } while (timeout--);
2730 if (pos1 == 0) { /* oops, this value is not reliable */
2731 pos = 0;
2732 } else {
2733 pos = ichdev->fragsize1;
2734 pos -= pos1 << ichdev->pos_shift;
2735 pos += ichdev->position;
2736 }
2737 chip->in_measurement = 0;
2738 do_posix_clock_monotonic_gettime(&stop_time);
2739 /* stop */
2740 if (chip->device_type == DEVICE_ALI) {
2741 iputdword(chip, ICHREG(ALI_DMACR), 1 << (ichdev->ali_slot + 16));
2742 iputbyte(chip, port + ICH_REG_OFF_CR, 0);
2743 while (igetbyte(chip, port + ICH_REG_OFF_CR))
2744 ;
2745 } else {
2746 iputbyte(chip, port + ICH_REG_OFF_CR, 0);
2747 while (!(igetbyte(chip, port + ichdev->roff_sr) & ICH_DCH))
2748 ;
2749 }
2750 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_RESETREGS);
2751 spin_unlock_irq(&chip->reg_lock);
2752
2753 if (pos == 0) {
2754 snd_printk(KERN_ERR "intel8x0: measure - unreliable DMA position..\n");
2755 __retry:
2756 if (attempt < 3) {
2757 msleep(300);
2758 attempt++;
2759 goto __again;
2760 }
2761 goto __end;
2762 }
2763
2764 pos /= 4;
2765 t = stop_time.tv_sec - start_time.tv_sec;
2766 t *= 1000000;
2767 t += (stop_time.tv_nsec - start_time.tv_nsec) / 1000;
2768 printk(KERN_INFO "%s: measured %lu usecs (%lu samples)\n", __func__, t, pos);
2769 if (t == 0) {
2770 snd_printk(KERN_ERR "intel8x0: ?? calculation error..\n");
2771 goto __retry;
2772 }
2773 pos *= 1000;
2774 pos = (pos / t) * 1000 + ((pos % t) * 1000) / t;
2775 if (pos < 40000 || pos >= 60000) {
2776 /* abnormal value. hw problem? */
2777 printk(KERN_INFO "intel8x0: measured clock %ld rejected\n", pos);
2778 goto __retry;
2779 } else if (pos > 40500 && pos < 41500)
2780 /* first exception - 41000Hz reference clock */
2781 chip->ac97_bus->clock = 41000;
2782 else if (pos > 43600 && pos < 44600)
2783 /* second exception - 44100HZ reference clock */
2784 chip->ac97_bus->clock = 44100;
2785 else if (pos < 47500 || pos > 48500)
2786 /* not 48000Hz, tuning the clock.. */
2787 chip->ac97_bus->clock = (chip->ac97_bus->clock * 48000) / pos;
2788 __end:
2789 printk(KERN_INFO "intel8x0: clocking to %d\n", chip->ac97_bus->clock);
2790 snd_ac97_update_power(chip->ac97[0], AC97_PCM_FRONT_DAC_RATE, 0);
2791}
2792
2793static struct snd_pci_quirk intel8x0_clock_list[] __devinitdata = {
2794 SND_PCI_QUIRK(0x0e11, 0x008a, "AD1885", 41000),
2795 SND_PCI_QUIRK(0x1028, 0x00be, "AD1885", 44100),
2796 SND_PCI_QUIRK(0x1028, 0x0177, "AD1980", 48000),
2797 SND_PCI_QUIRK(0x1028, 0x01ad, "AD1981B", 48000),
2798 SND_PCI_QUIRK(0x1043, 0x80f3, "AD1985", 48000),
2799 {0} /* terminator */
2800};
2801
2802static int __devinit intel8x0_in_clock_list(struct intel8x0 *chip)
2803{
2804 struct pci_dev *pci = chip->pci;
2805 const struct snd_pci_quirk *wl;
2806
2807 wl = snd_pci_quirk_lookup(pci, intel8x0_clock_list);
2808 if (!wl)
2809 return 0;
2810 printk(KERN_INFO "intel8x0: white list rate for %04x:%04x is %i\n",
2811 pci->subsystem_vendor, pci->subsystem_device, wl->value);
2812 chip->ac97_bus->clock = wl->value;
2813 return 1;
2814}
2815
2816#ifdef CONFIG_PROC_FS
2817static void snd_intel8x0_proc_read(struct snd_info_entry * entry,
2818 struct snd_info_buffer *buffer)
2819{
2820 struct intel8x0 *chip = entry->private_data;
2821 unsigned int tmp;
2822
2823 snd_iprintf(buffer, "Intel8x0\n\n");
2824 if (chip->device_type == DEVICE_ALI)
2825 return;
2826 tmp = igetdword(chip, ICHREG(GLOB_STA));
2827 snd_iprintf(buffer, "Global control : 0x%08x\n", igetdword(chip, ICHREG(GLOB_CNT)));
2828 snd_iprintf(buffer, "Global status : 0x%08x\n", tmp);
2829 if (chip->device_type == DEVICE_INTEL_ICH4)
2830 snd_iprintf(buffer, "SDM : 0x%08x\n", igetdword(chip, ICHREG(SDM)));
2831 snd_iprintf(buffer, "AC'97 codecs ready :");
2832 if (tmp & chip->codec_isr_bits) {
2833 int i;
2834 static const char *codecs[3] = {
2835 "primary", "secondary", "tertiary"
2836 };
2837 for (i = 0; i < chip->max_codecs; i++)
2838 if (tmp & chip->codec_bit[i])
2839 snd_iprintf(buffer, " %s", codecs[i]);
2840 } else
2841 snd_iprintf(buffer, " none");
2842 snd_iprintf(buffer, "\n");
2843 if (chip->device_type == DEVICE_INTEL_ICH4 ||
2844 chip->device_type == DEVICE_SIS)
2845 snd_iprintf(buffer, "AC'97 codecs SDIN : %i %i %i\n",
2846 chip->ac97_sdin[0],
2847 chip->ac97_sdin[1],
2848 chip->ac97_sdin[2]);
2849}
2850
2851static void __devinit snd_intel8x0_proc_init(struct intel8x0 * chip)
2852{
2853 struct snd_info_entry *entry;
2854
2855 if (! snd_card_proc_new(chip->card, "intel8x0", &entry))
2856 snd_info_set_text_ops(entry, chip, snd_intel8x0_proc_read);
2857}
2858#else
2859#define snd_intel8x0_proc_init(x)
2860#endif
2861
2862static int snd_intel8x0_dev_free(struct snd_device *device)
2863{
2864 struct intel8x0 *chip = device->device_data;
2865 return snd_intel8x0_free(chip);
2866}
2867
2868struct ich_reg_info {
2869 unsigned int int_sta_mask;
2870 unsigned int offset;
2871};
2872
2873static unsigned int ich_codec_bits[3] = {
2874 ICH_PCR, ICH_SCR, ICH_TCR
2875};
2876static unsigned int sis_codec_bits[3] = {
2877 ICH_PCR, ICH_SCR, ICH_SIS_TCR
2878};
2879
2880static int __devinit snd_intel8x0_create(struct snd_card *card,
2881 struct pci_dev *pci,
2882 unsigned long device_type,
2883 struct intel8x0 ** r_intel8x0)
2884{
2885 struct intel8x0 *chip;
2886 int err;
2887 unsigned int i;
2888 unsigned int int_sta_masks;
2889 struct ichdev *ichdev;
2890 static struct snd_device_ops ops = {
2891 .dev_free = snd_intel8x0_dev_free,
2892 };
2893
2894 static unsigned int bdbars[] = {
2895 3, /* DEVICE_INTEL */
2896 6, /* DEVICE_INTEL_ICH4 */
2897 3, /* DEVICE_SIS */
2898 6, /* DEVICE_ALI */
2899 4, /* DEVICE_NFORCE */
2900 };
2901 static struct ich_reg_info intel_regs[6] = {
2902 { ICH_PIINT, 0 },
2903 { ICH_POINT, 0x10 },
2904 { ICH_MCINT, 0x20 },
2905 { ICH_M2INT, 0x40 },
2906 { ICH_P2INT, 0x50 },
2907 { ICH_SPINT, 0x60 },
2908 };
2909 static struct ich_reg_info nforce_regs[4] = {
2910 { ICH_PIINT, 0 },
2911 { ICH_POINT, 0x10 },
2912 { ICH_MCINT, 0x20 },
2913 { ICH_NVSPINT, 0x70 },
2914 };
2915 static struct ich_reg_info ali_regs[6] = {
2916 { ALI_INT_PCMIN, 0x40 },
2917 { ALI_INT_PCMOUT, 0x50 },
2918 { ALI_INT_MICIN, 0x60 },
2919 { ALI_INT_CODECSPDIFOUT, 0x70 },
2920 { ALI_INT_SPDIFIN, 0xa0 },
2921 { ALI_INT_SPDIFOUT, 0xb0 },
2922 };
2923 struct ich_reg_info *tbl;
2924
2925 *r_intel8x0 = NULL;
2926
2927 if ((err = pci_enable_device(pci)) < 0)
2928 return err;
2929
2930 chip = kzalloc(sizeof(*chip), GFP_KERNEL);
2931 if (chip == NULL) {
2932 pci_disable_device(pci);
2933 return -ENOMEM;
2934 }
2935 spin_lock_init(&chip->reg_lock);
2936 chip->device_type = device_type;
2937 chip->card = card;
2938 chip->pci = pci;
2939 chip->irq = -1;
2940
2941 /* module parameters */
2942 chip->buggy_irq = buggy_irq;
2943 chip->buggy_semaphore = buggy_semaphore;
2944 if (xbox)
2945 chip->xbox = 1;
2946
2947 if (pci->vendor == PCI_VENDOR_ID_INTEL &&
2948 pci->device == PCI_DEVICE_ID_INTEL_440MX)
2949 chip->fix_nocache = 1; /* enable workaround */
2950
2951 if ((err = pci_request_regions(pci, card->shortname)) < 0) {
2952 kfree(chip);
2953 pci_disable_device(pci);
2954 return err;
2955 }
2956
2957 if (device_type == DEVICE_ALI) {
2958 /* ALI5455 has no ac97 region */
2959 chip->bmaddr = pci_iomap(pci, 0, 0);
2960 goto port_inited;
2961 }
2962
2963 if (pci_resource_flags(pci, 2) & IORESOURCE_MEM) /* ICH4 and Nforce */
2964 chip->addr = pci_iomap(pci, 2, 0);
2965 else
2966 chip->addr = pci_iomap(pci, 0, 0);
2967 if (!chip->addr) {
2968 snd_printk(KERN_ERR "AC'97 space ioremap problem\n");
2969 snd_intel8x0_free(chip);
2970 return -EIO;
2971 }
2972 if (pci_resource_flags(pci, 3) & IORESOURCE_MEM) /* ICH4 */
2973 chip->bmaddr = pci_iomap(pci, 3, 0);
2974 else
2975 chip->bmaddr = pci_iomap(pci, 1, 0);
2976 if (!chip->bmaddr) {
2977 snd_printk(KERN_ERR "Controller space ioremap problem\n");
2978 snd_intel8x0_free(chip);
2979 return -EIO;
2980 }
2981
2982 port_inited:
2983 chip->bdbars_count = bdbars[device_type];
2984
2985 /* initialize offsets */
2986 switch (device_type) {
2987 case DEVICE_NFORCE:
2988 tbl = nforce_regs;
2989 break;
2990 case DEVICE_ALI:
2991 tbl = ali_regs;
2992 break;
2993 default:
2994 tbl = intel_regs;
2995 break;
2996 }
2997 for (i = 0; i < chip->bdbars_count; i++) {
2998 ichdev = &chip->ichd[i];
2999 ichdev->ichd = i;
3000 ichdev->reg_offset = tbl[i].offset;
3001 ichdev->int_sta_mask = tbl[i].int_sta_mask;
3002 if (device_type == DEVICE_SIS) {
3003 /* SiS 7012 swaps the registers */
3004 ichdev->roff_sr = ICH_REG_OFF_PICB;
3005 ichdev->roff_picb = ICH_REG_OFF_SR;
3006 } else {
3007 ichdev->roff_sr = ICH_REG_OFF_SR;
3008 ichdev->roff_picb = ICH_REG_OFF_PICB;
3009 }
3010 if (device_type == DEVICE_ALI)
3011 ichdev->ali_slot = (ichdev->reg_offset - 0x40) / 0x10;
3012 /* SIS7012 handles the pcm data in bytes, others are in samples */
3013 ichdev->pos_shift = (device_type == DEVICE_SIS) ? 0 : 1;
3014 }
3015
3016 /* allocate buffer descriptor lists */
3017 /* the start of each lists must be aligned to 8 bytes */
3018 if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(pci),
3019 chip->bdbars_count * sizeof(u32) * ICH_MAX_FRAGS * 2,
3020 &chip->bdbars) < 0) {
3021 snd_intel8x0_free(chip);
3022 snd_printk(KERN_ERR "intel8x0: cannot allocate buffer descriptors\n");
3023 return -ENOMEM;
3024 }
3025 /* tables must be aligned to 8 bytes here, but the kernel pages
3026 are much bigger, so we don't care (on i386) */
3027 /* workaround for 440MX */
3028 if (chip->fix_nocache)
3029 fill_nocache(chip->bdbars.area, chip->bdbars.bytes, 1);
3030 int_sta_masks = 0;
3031 for (i = 0; i < chip->bdbars_count; i++) {
3032 ichdev = &chip->ichd[i];
3033 ichdev->bdbar = ((u32 *)chip->bdbars.area) +
3034 (i * ICH_MAX_FRAGS * 2);
3035 ichdev->bdbar_addr = chip->bdbars.addr +
3036 (i * sizeof(u32) * ICH_MAX_FRAGS * 2);
3037 int_sta_masks |= ichdev->int_sta_mask;
3038 }
3039 chip->int_sta_reg = device_type == DEVICE_ALI ?
3040 ICH_REG_ALI_INTERRUPTSR : ICH_REG_GLOB_STA;
3041 chip->int_sta_mask = int_sta_masks;
3042
3043 pci_set_master(pci);
3044
3045 switch(chip->device_type) {
3046 case DEVICE_INTEL_ICH4:
3047 /* ICH4 can have three codecs */
3048 chip->max_codecs = 3;
3049 chip->codec_bit = ich_codec_bits;
3050 chip->codec_ready_bits = ICH_PRI | ICH_SRI | ICH_TRI;
3051 break;
3052 case DEVICE_SIS:
3053 /* recent SIS7012 can have three codecs */
3054 chip->max_codecs = 3;
3055 chip->codec_bit = sis_codec_bits;
3056 chip->codec_ready_bits = ICH_PRI | ICH_SRI | ICH_SIS_TRI;
3057 break;
3058 default:
3059 /* others up to two codecs */
3060 chip->max_codecs = 2;
3061 chip->codec_bit = ich_codec_bits;
3062 chip->codec_ready_bits = ICH_PRI | ICH_SRI;
3063 break;
3064 }
3065 for (i = 0; i < chip->max_codecs; i++)
3066 chip->codec_isr_bits |= chip->codec_bit[i];
3067
3068 if ((err = snd_intel8x0_chip_init(chip, 1)) < 0) {
3069 snd_intel8x0_free(chip);
3070 return err;
3071 }
3072
3073 /* request irq after initializaing int_sta_mask, etc */
3074 if (request_irq(pci->irq, snd_intel8x0_interrupt,
3075 IRQF_SHARED, card->shortname, chip)) {
3076 snd_printk(KERN_ERR "unable to grab IRQ %d\n", pci->irq);
3077 snd_intel8x0_free(chip);
3078 return -EBUSY;
3079 }
3080 chip->irq = pci->irq;
3081
3082 if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) < 0) {
3083 snd_intel8x0_free(chip);
3084 return err;
3085 }
3086
3087 snd_card_set_dev(card, &pci->dev);
3088
3089 *r_intel8x0 = chip;
3090 return 0;
3091}
3092
3093static struct shortname_table {
3094 unsigned int id;
3095 const char *s;
3096} shortnames[] __devinitdata = {
3097 { PCI_DEVICE_ID_INTEL_82801AA_5, "Intel 82801AA-ICH" },
3098 { PCI_DEVICE_ID_INTEL_82801AB_5, "Intel 82901AB-ICH0" },
3099 { PCI_DEVICE_ID_INTEL_82801BA_4, "Intel 82801BA-ICH2" },
3100 { PCI_DEVICE_ID_INTEL_440MX, "Intel 440MX" },
3101 { PCI_DEVICE_ID_INTEL_82801CA_5, "Intel 82801CA-ICH3" },
3102 { PCI_DEVICE_ID_INTEL_82801DB_5, "Intel 82801DB-ICH4" },
3103 { PCI_DEVICE_ID_INTEL_82801EB_5, "Intel ICH5" },
3104 { PCI_DEVICE_ID_INTEL_ESB_5, "Intel 6300ESB" },
3105 { PCI_DEVICE_ID_INTEL_ICH6_18, "Intel ICH6" },
3106 { PCI_DEVICE_ID_INTEL_ICH7_20, "Intel ICH7" },
3107 { PCI_DEVICE_ID_INTEL_ESB2_14, "Intel ESB2" },
3108 { PCI_DEVICE_ID_SI_7012, "SiS SI7012" },
3109 { PCI_DEVICE_ID_NVIDIA_MCP1_AUDIO, "NVidia nForce" },
3110 { PCI_DEVICE_ID_NVIDIA_MCP2_AUDIO, "NVidia nForce2" },
3111 { PCI_DEVICE_ID_NVIDIA_MCP3_AUDIO, "NVidia nForce3" },
3112 { PCI_DEVICE_ID_NVIDIA_CK8S_AUDIO, "NVidia CK8S" },
3113 { PCI_DEVICE_ID_NVIDIA_CK804_AUDIO, "NVidia CK804" },
3114 { PCI_DEVICE_ID_NVIDIA_CK8_AUDIO, "NVidia CK8" },
3115 { 0x003a, "NVidia MCP04" },
3116 { 0x746d, "AMD AMD8111" },
3117 { 0x7445, "AMD AMD768" },
3118 { 0x5455, "ALi M5455" },
3119 { 0, NULL },
3120};
3121
3122static struct snd_pci_quirk spdif_aclink_defaults[] __devinitdata = {
3123 SND_PCI_QUIRK(0x147b, 0x1c1a, "ASUS KN8", 1),
3124 {0} /* end */
3125};
3126
3127/* look up white/black list for SPDIF over ac-link */
3128static int __devinit check_default_spdif_aclink(struct pci_dev *pci)
3129{
3130#ifndef TARGET_OS2
3131 const struct snd_pci_quirk *w;
3132
3133 w = snd_pci_quirk_lookup(pci, spdif_aclink_defaults);
3134 if (w) {
3135 if (w->value)
3136 snd_printdd(KERN_INFO "intel8x0: Using SPDIF over "
3137 "AC-Link for %s\n", w->name);
3138 else
3139 snd_printdd(KERN_INFO "intel8x0: Using integrated "
3140 "SPDIF DMA for %s\n", w->name);
3141 return w->value;
3142 }
3143#endif
3144 return 0;
3145}
3146
3147static int __devinit snd_intel8x0_probe(struct pci_dev *pci,
3148 const struct pci_device_id *pci_id)
3149{
3150 struct snd_card *card;
3151 struct intel8x0 *chip;
3152 int err;
3153 struct shortname_table *name;
3154
3155 err = snd_card_create(index, id, THIS_MODULE, 0, &card);
3156 if (err < 0)
3157 return err;
3158
3159 if (spdif_aclink < 0)
3160 spdif_aclink = check_default_spdif_aclink(pci);
3161
3162 strcpy(card->driver, "ICH");
3163 if (!spdif_aclink) {
3164 switch (pci_id->driver_data) {
3165 case DEVICE_NFORCE:
3166 strcpy(card->driver, "NFORCE");
3167 break;
3168 case DEVICE_INTEL_ICH4:
3169 strcpy(card->driver, "ICH4");
3170 }
3171 }
3172
3173 strcpy(card->shortname, "Intel ICH");
3174 for (name = shortnames; name->id; name++) {
3175 if (pci->device == name->id) {
3176 strcpy(card->shortname, name->s);
3177 break;
3178 }
3179 }
3180
3181 if (buggy_irq < 0) {
3182 /* some Nforce[2] and ICH boards have problems with IRQ handling.
3183 * Needs to return IRQ_HANDLED for unknown irqs.
3184 */
3185 if (pci_id->driver_data == DEVICE_NFORCE)
3186 buggy_irq = 1;
3187 else
3188 buggy_irq = 0;
3189 }
3190
3191 if ((err = snd_intel8x0_create(card, pci, pci_id->driver_data,
3192 &chip)) < 0) {
3193 snd_card_free(card);
3194 return err;
3195 }
3196 card->private_data = chip;
3197
3198 if ((err = snd_intel8x0_mixer(chip, ac97_clock, ac97_quirk)) < 0) {
3199 snd_card_free(card);
3200 return err;
3201 }
3202 if ((err = snd_intel8x0_pcm(chip)) < 0) {
3203 snd_card_free(card);
3204 return err;
3205 }
3206
3207 snd_intel8x0_proc_init(chip);
3208
3209 snprintf(card->longname, sizeof(card->longname),
3210 "%s with %s at irq %i", card->shortname,
3211 snd_ac97_get_short_name(chip->ac97[0]), chip->irq);
3212
3213 if (ac97_clock == 0 || ac97_clock == 1) {
3214 if (ac97_clock == 0) {
3215 if (intel8x0_in_clock_list(chip) == 0)
3216 intel8x0_measure_ac97_clock(chip);
3217 } else {
3218 intel8x0_measure_ac97_clock(chip);
3219 }
3220 }
3221
3222 if ((err = snd_card_register(card)) < 0) {
3223 snd_card_free(card);
3224 return err;
3225 }
3226 pci_set_drvdata(pci, card);
3227 return 0;
3228}
3229
3230static void __devexit snd_intel8x0_remove(struct pci_dev *pci)
3231{
3232 snd_card_free(pci_get_drvdata(pci));
3233 pci_set_drvdata(pci, NULL);
3234}
3235
3236static struct pci_driver driver = {
3237 .name = "Intel ICH",
3238 .id_table = snd_intel8x0_ids,
3239 .probe = snd_intel8x0_probe,
3240 .remove = __devexit_p(snd_intel8x0_remove),
3241#ifdef CONFIG_PM
3242 .suspend = intel8x0_suspend,
3243 .resume = intel8x0_resume,
3244#endif
3245};
3246
3247
3248static int __init alsa_card_intel8x0_init(void)
3249{
3250 return pci_register_driver(&driver);
3251}
3252
3253static void __exit alsa_card_intel8x0_exit(void)
3254{
3255 pci_unregister_driver(&driver);
3256}
3257
3258module_init(alsa_card_intel8x0_init)
3259module_exit(alsa_card_intel8x0_exit)
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