source: GPL/trunk/alsa-kernel/pci/cs4281.c@ 695

Last change on this file since 695 was 695, checked in by David Azarewicz, 4 years ago

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1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Driver for Cirrus Logic CS4281 based PCI soundcard
4 * Copyright (c) by Jaroslav Kysela <perex@perex.cz>,
5 */
6
7#include <linux/io.h>
8#include <linux/delay.h>
9#include <linux/interrupt.h>
10#include <linux/init.h>
11#include <linux/pci.h>
12#include <linux/slab.h>
13#include <linux/gameport.h>
14#include <linux/module.h>
15#include <sound/core.h>
16#include <sound/control.h>
17#include <sound/pcm.h>
18#include <sound/rawmidi.h>
19#include <sound/ac97_codec.h>
20#include <sound/tlv.h>
21#include <sound/opl3.h>
22#include <sound/initval.h>
23
24
25#ifdef TARGET_OS2
26#define KBUILD_MODNAME "cs4281"
27#endif
28MODULE_AUTHOR("Jaroslav Kysela <perex@perex.cz>");
29MODULE_DESCRIPTION("Cirrus Logic CS4281");
30MODULE_LICENSE("GPL");
31
32static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
33static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
34static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable switches */
35static bool dual_codec[SNDRV_CARDS]; /* dual codec */
36
37module_param_array(index, int, NULL, 0444);
38MODULE_PARM_DESC(index, "Index value for CS4281 soundcard.");
39module_param_array(id, charp, NULL, 0444);
40MODULE_PARM_DESC(id, "ID string for CS4281 soundcard.");
41module_param_array(enable, bool, NULL, 0444);
42MODULE_PARM_DESC(enable, "Enable CS4281 soundcard.");
43module_param_array(dual_codec, bool, NULL, 0444);
44MODULE_PARM_DESC(dual_codec, "Secondary Codec ID (0 = disabled).");
45
46/*
47 * Direct registers
48 */
49
50#define CS4281_BA0_SIZE 0x1000
51#define CS4281_BA1_SIZE 0x10000
52
53/*
54 * BA0 registers
55 */
56#define BA0_HISR 0x0000 /* Host Interrupt Status Register */
57#define BA0_HISR_INTENA (1<<31) /* Internal Interrupt Enable Bit */
58#define BA0_HISR_MIDI (1<<22) /* MIDI port interrupt */
59#define BA0_HISR_FIFOI (1<<20) /* FIFO polled interrupt */
60#define BA0_HISR_DMAI (1<<18) /* DMA interrupt (half or end) */
61#define BA0_HISR_FIFO(c) (1<<(12+(c))) /* FIFO channel interrupt */
62#define BA0_HISR_DMA(c) (1<<(8+(c))) /* DMA channel interrupt */
63#define BA0_HISR_GPPI (1<<5) /* General Purpose Input (Primary chip) */
64#define BA0_HISR_GPSI (1<<4) /* General Purpose Input (Secondary chip) */
65#define BA0_HISR_GP3I (1<<3) /* GPIO3 pin Interrupt */
66#define BA0_HISR_GP1I (1<<2) /* GPIO1 pin Interrupt */
67#define BA0_HISR_VUPI (1<<1) /* VOLUP pin Interrupt */
68#define BA0_HISR_VDNI (1<<0) /* VOLDN pin Interrupt */
69
70#define BA0_HICR 0x0008 /* Host Interrupt Control Register */
71#define BA0_HICR_CHGM (1<<1) /* INTENA Change Mask */
72#define BA0_HICR_IEV (1<<0) /* INTENA Value */
73#define BA0_HICR_EOI (3<<0) /* End of Interrupt command */
74
75#define BA0_HIMR 0x000c /* Host Interrupt Mask Register */
76 /* Use same contants as for BA0_HISR */
77
78#define BA0_IIER 0x0010 /* ISA Interrupt Enable Register */
79
80#define BA0_HDSR0 0x00f0 /* Host DMA Engine 0 Status Register */
81#define BA0_HDSR1 0x00f4 /* Host DMA Engine 1 Status Register */
82#define BA0_HDSR2 0x00f8 /* Host DMA Engine 2 Status Register */
83#define BA0_HDSR3 0x00fc /* Host DMA Engine 3 Status Register */
84
85#define BA0_HDSR_CH1P (1<<25) /* Channel 1 Pending */
86#define BA0_HDSR_CH2P (1<<24) /* Channel 2 Pending */
87#define BA0_HDSR_DHTC (1<<17) /* DMA Half Terminal Count */
88#define BA0_HDSR_DTC (1<<16) /* DMA Terminal Count */
89#define BA0_HDSR_DRUN (1<<15) /* DMA Running */
90#define BA0_HDSR_RQ (1<<7) /* Pending Request */
91
92#define BA0_DCA0 0x0110 /* Host DMA Engine 0 Current Address */
93#define BA0_DCC0 0x0114 /* Host DMA Engine 0 Current Count */
94#define BA0_DBA0 0x0118 /* Host DMA Engine 0 Base Address */
95#define BA0_DBC0 0x011c /* Host DMA Engine 0 Base Count */
96#define BA0_DCA1 0x0120 /* Host DMA Engine 1 Current Address */
97#define BA0_DCC1 0x0124 /* Host DMA Engine 1 Current Count */
98#define BA0_DBA1 0x0128 /* Host DMA Engine 1 Base Address */
99#define BA0_DBC1 0x012c /* Host DMA Engine 1 Base Count */
100#define BA0_DCA2 0x0130 /* Host DMA Engine 2 Current Address */
101#define BA0_DCC2 0x0134 /* Host DMA Engine 2 Current Count */
102#define BA0_DBA2 0x0138 /* Host DMA Engine 2 Base Address */
103#define BA0_DBC2 0x013c /* Host DMA Engine 2 Base Count */
104#define BA0_DCA3 0x0140 /* Host DMA Engine 3 Current Address */
105#define BA0_DCC3 0x0144 /* Host DMA Engine 3 Current Count */
106#define BA0_DBA3 0x0148 /* Host DMA Engine 3 Base Address */
107#define BA0_DBC3 0x014c /* Host DMA Engine 3 Base Count */
108#define BA0_DMR0 0x0150 /* Host DMA Engine 0 Mode */
109#define BA0_DCR0 0x0154 /* Host DMA Engine 0 Command */
110#define BA0_DMR1 0x0158 /* Host DMA Engine 1 Mode */
111#define BA0_DCR1 0x015c /* Host DMA Engine 1 Command */
112#define BA0_DMR2 0x0160 /* Host DMA Engine 2 Mode */
113#define BA0_DCR2 0x0164 /* Host DMA Engine 2 Command */
114#define BA0_DMR3 0x0168 /* Host DMA Engine 3 Mode */
115#define BA0_DCR3 0x016c /* Host DMA Engine 3 Command */
116
117#define BA0_DMR_DMA (1<<29) /* Enable DMA mode */
118#define BA0_DMR_POLL (1<<28) /* Enable poll mode */
119#define BA0_DMR_TBC (1<<25) /* Transfer By Channel */
120#define BA0_DMR_CBC (1<<24) /* Count By Channel (0 = frame resolution) */
121#define BA0_DMR_SWAPC (1<<22) /* Swap Left/Right Channels */
122#define BA0_DMR_SIZE20 (1<<20) /* Sample is 20-bit */
123#define BA0_DMR_USIGN (1<<19) /* Unsigned */
124#define BA0_DMR_BEND (1<<18) /* Big Endian */
125#define BA0_DMR_MONO (1<<17) /* Mono */
126#define BA0_DMR_SIZE8 (1<<16) /* Sample is 8-bit */
127#define BA0_DMR_TYPE_DEMAND (0<<6)
128#define BA0_DMR_TYPE_SINGLE (1<<6)
129#define BA0_DMR_TYPE_BLOCK (2<<6)
130#define BA0_DMR_TYPE_CASCADE (3<<6) /* Not supported */
131#define BA0_DMR_DEC (1<<5) /* Access Increment (0) or Decrement (1) */
132#define BA0_DMR_AUTO (1<<4) /* Auto-Initialize */
133#define BA0_DMR_TR_VERIFY (0<<2) /* Verify Transfer */
134#define BA0_DMR_TR_WRITE (1<<2) /* Write Transfer */
135#define BA0_DMR_TR_READ (2<<2) /* Read Transfer */
136
137#define BA0_DCR_HTCIE (1<<17) /* Half Terminal Count Interrupt */
138#define BA0_DCR_TCIE (1<<16) /* Terminal Count Interrupt */
139#define BA0_DCR_MSK (1<<0) /* DMA Mask bit */
140
141#define BA0_FCR0 0x0180 /* FIFO Control 0 */
142#define BA0_FCR1 0x0184 /* FIFO Control 1 */
143#define BA0_FCR2 0x0188 /* FIFO Control 2 */
144#define BA0_FCR3 0x018c /* FIFO Control 3 */
145
146#define BA0_FCR_FEN (1<<31) /* FIFO Enable bit */
147#define BA0_FCR_DACZ (1<<30) /* DAC Zero */
148#define BA0_FCR_PSH (1<<29) /* Previous Sample Hold */
149#define BA0_FCR_RS(x) (((x)&0x1f)<<24) /* Right Slot Mapping */
150#define BA0_FCR_LS(x) (((x)&0x1f)<<16) /* Left Slot Mapping */
151#define BA0_FCR_SZ(x) (((x)&0x7f)<<8) /* FIFO buffer size (in samples) */
152#define BA0_FCR_OF(x) (((x)&0x7f)<<0) /* FIFO starting offset (in samples) */
153
154#define BA0_FPDR0 0x0190 /* FIFO Polled Data 0 */
155#define BA0_FPDR1 0x0194 /* FIFO Polled Data 1 */
156#define BA0_FPDR2 0x0198 /* FIFO Polled Data 2 */
157#define BA0_FPDR3 0x019c /* FIFO Polled Data 3 */
158
159#define BA0_FCHS 0x020c /* FIFO Channel Status */
160#define BA0_FCHS_RCO(x) (1<<(7+(((x)&3)<<3))) /* Right Channel Out */
161#define BA0_FCHS_LCO(x) (1<<(6+(((x)&3)<<3))) /* Left Channel Out */
162#define BA0_FCHS_MRP(x) (1<<(5+(((x)&3)<<3))) /* Move Read Pointer */
163#define BA0_FCHS_FE(x) (1<<(4+(((x)&3)<<3))) /* FIFO Empty */
164#define BA0_FCHS_FF(x) (1<<(3+(((x)&3)<<3))) /* FIFO Full */
165#define BA0_FCHS_IOR(x) (1<<(2+(((x)&3)<<3))) /* Internal Overrun Flag */
166#define BA0_FCHS_RCI(x) (1<<(1+(((x)&3)<<3))) /* Right Channel In */
167#define BA0_FCHS_LCI(x) (1<<(0+(((x)&3)<<3))) /* Left Channel In */
168
169#define BA0_FSIC0 0x0210 /* FIFO Status and Interrupt Control 0 */
170#define BA0_FSIC1 0x0214 /* FIFO Status and Interrupt Control 1 */
171#define BA0_FSIC2 0x0218 /* FIFO Status and Interrupt Control 2 */
172#define BA0_FSIC3 0x021c /* FIFO Status and Interrupt Control 3 */
173
174#define BA0_FSIC_FIC(x) (((x)&0x7f)<<24) /* FIFO Interrupt Count */
175#define BA0_FSIC_FORIE (1<<23) /* FIFO OverRun Interrupt Enable */
176#define BA0_FSIC_FURIE (1<<22) /* FIFO UnderRun Interrupt Enable */
177#define BA0_FSIC_FSCIE (1<<16) /* FIFO Sample Count Interrupt Enable */
178#define BA0_FSIC_FSC(x) (((x)&0x7f)<<8) /* FIFO Sample Count */
179#define BA0_FSIC_FOR (1<<7) /* FIFO OverRun */
180#define BA0_FSIC_FUR (1<<6) /* FIFO UnderRun */
181#define BA0_FSIC_FSCR (1<<0) /* FIFO Sample Count Reached */
182
183#define BA0_PMCS 0x0344 /* Power Management Control/Status */
184#define BA0_CWPR 0x03e0 /* Configuration Write Protect */
185
186#define BA0_EPPMC 0x03e4 /* Extended PCI Power Management Control */
187#define BA0_EPPMC_FPDN (1<<14) /* Full Power DowN */
188
189#define BA0_GPIOR 0x03e8 /* GPIO Pin Interface Register */
190
191#define BA0_SPMC 0x03ec /* Serial Port Power Management Control (& ASDIN2 enable) */
192#define BA0_SPMC_GIPPEN (1<<15) /* GP INT Primary PME# Enable */
193#define BA0_SPMC_GISPEN (1<<14) /* GP INT Secondary PME# Enable */
194#define BA0_SPMC_EESPD (1<<9) /* EEPROM Serial Port Disable */
195#define BA0_SPMC_ASDI2E (1<<8) /* ASDIN2 Enable */
196#define BA0_SPMC_ASDO (1<<7) /* Asynchronous ASDOUT Assertion */
197#define BA0_SPMC_WUP2 (1<<3) /* Wakeup for Secondary Input */
198#define BA0_SPMC_WUP1 (1<<2) /* Wakeup for Primary Input */
199#define BA0_SPMC_ASYNC (1<<1) /* Asynchronous ASYNC Assertion */
200#define BA0_SPMC_RSTN (1<<0) /* Reset Not! */
201
202#define BA0_CFLR 0x03f0 /* Configuration Load Register (EEPROM or BIOS) */
203#define BA0_CFLR_DEFAULT 0x00000001 /* CFLR must be in AC97 link mode */
204#define BA0_IISR 0x03f4 /* ISA Interrupt Select */
205#define BA0_TMS 0x03f8 /* Test Register */
206#define BA0_SSVID 0x03fc /* Subsystem ID register */
207
208#define BA0_CLKCR1 0x0400 /* Clock Control Register 1 */
209#define BA0_CLKCR1_CLKON (1<<25) /* Read Only */
210#define BA0_CLKCR1_DLLRDY (1<<24) /* DLL Ready */
211#define BA0_CLKCR1_DLLOS (1<<6) /* DLL Output Select */
212#define BA0_CLKCR1_SWCE (1<<5) /* Clock Enable */
213#define BA0_CLKCR1_DLLP (1<<4) /* DLL PowerUp */
214#define BA0_CLKCR1_DLLSS (((x)&3)<<3) /* DLL Source Select */
215
216#define BA0_FRR 0x0410 /* Feature Reporting Register */
217#define BA0_SLT12O 0x041c /* Slot 12 GPIO Output Register for AC-Link */
218
219#define BA0_SERMC 0x0420 /* Serial Port Master Control */
220#define BA0_SERMC_FCRN (1<<27) /* Force Codec Ready Not */
221#define BA0_SERMC_ODSEN2 (1<<25) /* On-Demand Support Enable ASDIN2 */
222#define BA0_SERMC_ODSEN1 (1<<24) /* On-Demand Support Enable ASDIN1 */
223#define BA0_SERMC_SXLB (1<<21) /* ASDIN2 to ASDOUT Loopback */
224#define BA0_SERMC_SLB (1<<20) /* ASDOUT to ASDIN2 Loopback */
225#define BA0_SERMC_LOVF (1<<19) /* Loopback Output Valid Frame bit */
226#define BA0_SERMC_TCID(x) (((x)&3)<<16) /* Target Secondary Codec ID */
227#define BA0_SERMC_PXLB (5<<1) /* Primary Port External Loopback */
228#define BA0_SERMC_PLB (4<<1) /* Primary Port Internal Loopback */
229#define BA0_SERMC_PTC (7<<1) /* Port Timing Configuration */
230#define BA0_SERMC_PTC_AC97 (1<<1) /* AC97 mode */
231#define BA0_SERMC_MSPE (1<<0) /* Master Serial Port Enable */
232
233#define BA0_SERC1 0x0428 /* Serial Port Configuration 1 */
234#define BA0_SERC1_SO1F(x) (((x)&7)>>1) /* Primary Output Port Format */
235#define BA0_SERC1_AC97 (1<<1)
236#define BA0_SERC1_SO1EN (1<<0) /* Primary Output Port Enable */
237
238#define BA0_SERC2 0x042c /* Serial Port Configuration 2 */
239#define BA0_SERC2_SI1F(x) (((x)&7)>>1) /* Primary Input Port Format */
240#define BA0_SERC2_AC97 (1<<1)
241#define BA0_SERC2_SI1EN (1<<0) /* Primary Input Port Enable */
242
243#define BA0_SLT12M 0x045c /* Slot 12 Monitor Register for Primary AC-Link */
244
245#define BA0_ACCTL 0x0460 /* AC'97 Control */
246#define BA0_ACCTL_TC (1<<6) /* Target Codec */
247#define BA0_ACCTL_CRW (1<<4) /* 0=Write, 1=Read Command */
248#define BA0_ACCTL_DCV (1<<3) /* Dynamic Command Valid */
249#define BA0_ACCTL_VFRM (1<<2) /* Valid Frame */
250#define BA0_ACCTL_ESYN (1<<1) /* Enable Sync */
251
252#define BA0_ACSTS 0x0464 /* AC'97 Status */
253#define BA0_ACSTS_VSTS (1<<1) /* Valid Status */
254#define BA0_ACSTS_CRDY (1<<0) /* Codec Ready */
255
256#define BA0_ACOSV 0x0468 /* AC'97 Output Slot Valid */
257#define BA0_ACOSV_SLV(x) (1<<((x)-3))
258
259#define BA0_ACCAD 0x046c /* AC'97 Command Address */
260#define BA0_ACCDA 0x0470 /* AC'97 Command Data */
261
262#define BA0_ACISV 0x0474 /* AC'97 Input Slot Valid */
263#define BA0_ACISV_SLV(x) (1<<((x)-3))
264
265#define BA0_ACSAD 0x0478 /* AC'97 Status Address */
266#define BA0_ACSDA 0x047c /* AC'97 Status Data */
267#define BA0_JSPT 0x0480 /* Joystick poll/trigger */
268#define BA0_JSCTL 0x0484 /* Joystick control */
269#define BA0_JSC1 0x0488 /* Joystick control */
270#define BA0_JSC2 0x048c /* Joystick control */
271#define BA0_JSIO 0x04a0
272
273#define BA0_MIDCR 0x0490 /* MIDI Control */
274#define BA0_MIDCR_MRST (1<<5) /* Reset MIDI Interface */
275#define BA0_MIDCR_MLB (1<<4) /* MIDI Loop Back Enable */
276#define BA0_MIDCR_TIE (1<<3) /* MIDI Transmuit Interrupt Enable */
277#define BA0_MIDCR_RIE (1<<2) /* MIDI Receive Interrupt Enable */
278#define BA0_MIDCR_RXE (1<<1) /* MIDI Receive Enable */
279#define BA0_MIDCR_TXE (1<<0) /* MIDI Transmit Enable */
280
281#define BA0_MIDCMD 0x0494 /* MIDI Command (wo) */
282
283#define BA0_MIDSR 0x0494 /* MIDI Status (ro) */
284#define BA0_MIDSR_RDA (1<<15) /* Sticky bit (RBE 1->0) */
285#define BA0_MIDSR_TBE (1<<14) /* Sticky bit (TBF 0->1) */
286#define BA0_MIDSR_RBE (1<<7) /* Receive Buffer Empty */
287#define BA0_MIDSR_TBF (1<<6) /* Transmit Buffer Full */
288
289#define BA0_MIDWP 0x0498 /* MIDI Write */
290#define BA0_MIDRP 0x049c /* MIDI Read (ro) */
291
292#define BA0_AODSD1 0x04a8 /* AC'97 On-Demand Slot Disable for primary link (ro) */
293#define BA0_AODSD1_NDS(x) (1<<((x)-3))
294
295#define BA0_AODSD2 0x04ac /* AC'97 On-Demand Slot Disable for secondary link (ro) */
296#define BA0_AODSD2_NDS(x) (1<<((x)-3))
297
298#define BA0_CFGI 0x04b0 /* Configure Interface (EEPROM interface) */
299#define BA0_SLT12M2 0x04dc /* Slot 12 Monitor Register 2 for secondary AC-link */
300#define BA0_ACSTS2 0x04e4 /* AC'97 Status Register 2 */
301#define BA0_ACISV2 0x04f4 /* AC'97 Input Slot Valid Register 2 */
302#define BA0_ACSAD2 0x04f8 /* AC'97 Status Address Register 2 */
303#define BA0_ACSDA2 0x04fc /* AC'97 Status Data Register 2 */
304#define BA0_FMSR 0x0730 /* FM Synthesis Status (ro) */
305#define BA0_B0AP 0x0730 /* FM Bank 0 Address Port (wo) */
306#define BA0_FMDP 0x0734 /* FM Data Port */
307#define BA0_B1AP 0x0738 /* FM Bank 1 Address Port */
308#define BA0_B1DP 0x073c /* FM Bank 1 Data Port */
309
310#define BA0_SSPM 0x0740 /* Sound System Power Management */
311#define BA0_SSPM_MIXEN (1<<6) /* Playback SRC + FM/Wavetable MIX */
312#define BA0_SSPM_CSRCEN (1<<5) /* Capture Sample Rate Converter Enable */
313#define BA0_SSPM_PSRCEN (1<<4) /* Playback Sample Rate Converter Enable */
314#define BA0_SSPM_JSEN (1<<3) /* Joystick Enable */
315#define BA0_SSPM_ACLEN (1<<2) /* Serial Port Engine and AC-Link Enable */
316#define BA0_SSPM_FMEN (1<<1) /* FM Synthesis Block Enable */
317
318#define BA0_DACSR 0x0744 /* DAC Sample Rate - Playback SRC */
319#define BA0_ADCSR 0x0748 /* ADC Sample Rate - Capture SRC */
320
321#define BA0_SSCR 0x074c /* Sound System Control Register */
322#define BA0_SSCR_HVS1 (1<<23) /* Hardwave Volume Step (0=1,1=2) */
323#define BA0_SSCR_MVCS (1<<19) /* Master Volume Codec Select */
324#define BA0_SSCR_MVLD (1<<18) /* Master Volume Line Out Disable */
325#define BA0_SSCR_MVAD (1<<17) /* Master Volume Alternate Out Disable */
326#define BA0_SSCR_MVMD (1<<16) /* Master Volume Mono Out Disable */
327#define BA0_SSCR_XLPSRC (1<<8) /* External SRC Loopback Mode */
328#define BA0_SSCR_LPSRC (1<<7) /* SRC Loopback Mode */
329#define BA0_SSCR_CDTX (1<<5) /* CD Transfer Data */
330#define BA0_SSCR_HVC (1<<3) /* Harware Volume Control Enable */
331
332#define BA0_FMLVC 0x0754 /* FM Synthesis Left Volume Control */
333#define BA0_FMRVC 0x0758 /* FM Synthesis Right Volume Control */
334#define BA0_SRCSA 0x075c /* SRC Slot Assignments */
335#define BA0_PPLVC 0x0760 /* PCM Playback Left Volume Control */
336#define BA0_PPRVC 0x0764 /* PCM Playback Right Volume Control */
337#define BA0_PASR 0x0768 /* playback sample rate */
338#define BA0_CASR 0x076C /* capture sample rate */
339
340/* Source Slot Numbers - Playback */
341#define SRCSLOT_LEFT_PCM_PLAYBACK 0
342#define SRCSLOT_RIGHT_PCM_PLAYBACK 1
343#define SRCSLOT_PHONE_LINE_1_DAC 2
344#define SRCSLOT_CENTER_PCM_PLAYBACK 3
345#define SRCSLOT_LEFT_SURROUND_PCM_PLAYBACK 4
346#define SRCSLOT_RIGHT_SURROUND_PCM_PLAYBACK 5
347#define SRCSLOT_LFE_PCM_PLAYBACK 6
348#define SRCSLOT_PHONE_LINE_2_DAC 7
349#define SRCSLOT_HEADSET_DAC 8
350#define SRCSLOT_LEFT_WT 29 /* invalid for BA0_SRCSA */
351#define SRCSLOT_RIGHT_WT 30 /* invalid for BA0_SRCSA */
352
353/* Source Slot Numbers - Capture */
354#define SRCSLOT_LEFT_PCM_RECORD 10
355#define SRCSLOT_RIGHT_PCM_RECORD 11
356#define SRCSLOT_PHONE_LINE_1_ADC 12
357#define SRCSLOT_MIC_ADC 13
358#define SRCSLOT_PHONE_LINE_2_ADC 17
359#define SRCSLOT_HEADSET_ADC 18
360#define SRCSLOT_SECONDARY_LEFT_PCM_RECORD 20
361#define SRCSLOT_SECONDARY_RIGHT_PCM_RECORD 21
362#define SRCSLOT_SECONDARY_PHONE_LINE_1_ADC 22
363#define SRCSLOT_SECONDARY_MIC_ADC 23
364#define SRCSLOT_SECONDARY_PHONE_LINE_2_ADC 27
365#define SRCSLOT_SECONDARY_HEADSET_ADC 28
366
367/* Source Slot Numbers - Others */
368#define SRCSLOT_POWER_DOWN 31
369
370/* MIDI modes */
371#define CS4281_MODE_OUTPUT (1<<0)
372#define CS4281_MODE_INPUT (1<<1)
373
374/* joystick bits */
375/* Bits for JSPT */
376#define JSPT_CAX 0x00000001
377#define JSPT_CAY 0x00000002
378#define JSPT_CBX 0x00000004
379#define JSPT_CBY 0x00000008
380#define JSPT_BA1 0x00000010
381#define JSPT_BA2 0x00000020
382#define JSPT_BB1 0x00000040
383#define JSPT_BB2 0x00000080
384
385/* Bits for JSCTL */
386#define JSCTL_SP_MASK 0x00000003
387#define JSCTL_SP_SLOW 0x00000000
388#define JSCTL_SP_MEDIUM_SLOW 0x00000001
389#define JSCTL_SP_MEDIUM_FAST 0x00000002
390#define JSCTL_SP_FAST 0x00000003
391#define JSCTL_ARE 0x00000004
392
393/* Data register pairs masks */
394#define JSC1_Y1V_MASK 0x0000FFFF
395#define JSC1_X1V_MASK 0xFFFF0000
396#define JSC1_Y1V_SHIFT 0
397#define JSC1_X1V_SHIFT 16
398#define JSC2_Y2V_MASK 0x0000FFFF
399#define JSC2_X2V_MASK 0xFFFF0000
400#define JSC2_Y2V_SHIFT 0
401#define JSC2_X2V_SHIFT 16
402
403/* JS GPIO */
404#define JSIO_DAX 0x00000001
405#define JSIO_DAY 0x00000002
406#define JSIO_DBX 0x00000004
407#define JSIO_DBY 0x00000008
408#define JSIO_AXOE 0x00000010
409#define JSIO_AYOE 0x00000020
410#define JSIO_BXOE 0x00000040
411#define JSIO_BYOE 0x00000080
412
413/*
414 *
415 */
416
417struct cs4281_dma {
418 struct snd_pcm_substream *substream;
419 unsigned int regDBA; /* offset to DBA register */
420 unsigned int regDCA; /* offset to DCA register */
421 unsigned int regDBC; /* offset to DBC register */
422 unsigned int regDCC; /* offset to DCC register */
423 unsigned int regDMR; /* offset to DMR register */
424 unsigned int regDCR; /* offset to DCR register */
425 unsigned int regHDSR; /* offset to HDSR register */
426 unsigned int regFCR; /* offset to FCR register */
427 unsigned int regFSIC; /* offset to FSIC register */
428 unsigned int valDMR; /* DMA mode */
429 unsigned int valDCR; /* DMA command */
430 unsigned int valFCR; /* FIFO control */
431 unsigned int fifo_offset; /* FIFO offset within BA1 */
432 unsigned char left_slot; /* FIFO left slot */
433 unsigned char right_slot; /* FIFO right slot */
434 int frag; /* period number */
435};
436
437#define SUSPEND_REGISTERS 20
438
439struct cs4281 {
440 int irq;
441
442 void __iomem *ba0; /* virtual (accessible) address */
443 void __iomem *ba1; /* virtual (accessible) address */
444 unsigned long ba0_addr;
445 unsigned long ba1_addr;
446
447 int dual_codec;
448
449 struct snd_ac97_bus *ac97_bus;
450 struct snd_ac97 *ac97;
451 struct snd_ac97 *ac97_secondary;
452
453 struct pci_dev *pci;
454 struct snd_card *card;
455 struct snd_pcm *pcm;
456 struct snd_rawmidi *rmidi;
457 struct snd_rawmidi_substream *midi_input;
458 struct snd_rawmidi_substream *midi_output;
459
460 struct cs4281_dma dma[4];
461
462 unsigned char src_left_play_slot;
463 unsigned char src_right_play_slot;
464 unsigned char src_left_rec_slot;
465 unsigned char src_right_rec_slot;
466
467 unsigned int spurious_dhtc_irq;
468 unsigned int spurious_dtc_irq;
469
470 spinlock_t reg_lock;
471 unsigned int midcr;
472 unsigned int uartm;
473
474 struct gameport *gameport;
475
476#ifdef CONFIG_PM_SLEEP
477 u32 suspend_regs[SUSPEND_REGISTERS];
478#endif
479
480};
481
482static irqreturn_t snd_cs4281_interrupt(int irq, void *dev_id);
483
484static const struct pci_device_id snd_cs4281_ids[] = {
485 { PCI_VDEVICE(CIRRUS, 0x6005), 0, }, /* CS4281 */
486 { 0, }
487};
488
489MODULE_DEVICE_TABLE(pci, snd_cs4281_ids);
490
491/*
492 * constants
493 */
494
495#define CS4281_FIFO_SIZE 32
496
497/*
498 * common I/O routines
499 */
500
501static inline void snd_cs4281_pokeBA0(struct cs4281 *chip, unsigned long offset,
502 unsigned int val)
503{
504 writel(val, chip->ba0 + offset);
505}
506
507static inline unsigned int snd_cs4281_peekBA0(struct cs4281 *chip, unsigned long offset)
508{
509 return readl(chip->ba0 + offset);
510}
511
512static void snd_cs4281_ac97_write(struct snd_ac97 *ac97,
513 unsigned short reg, unsigned short val)
514{
515 /*
516 * 1. Write ACCAD = Command Address Register = 46Ch for AC97 register address
517 * 2. Write ACCDA = Command Data Register = 470h for data to write to AC97
518 * 3. Write ACCTL = Control Register = 460h for initiating the write
519 * 4. Read ACCTL = 460h, DCV should be reset by now and 460h = 07h
520 * 5. if DCV not cleared, break and return error
521 */
522 struct cs4281 *chip = ac97->private_data;
523 int count;
524
525 /*
526 * Setup the AC97 control registers on the CS461x to send the
527 * appropriate command to the AC97 to perform the read.
528 * ACCAD = Command Address Register = 46Ch
529 * ACCDA = Command Data Register = 470h
530 * ACCTL = Control Register = 460h
531 * set DCV - will clear when process completed
532 * reset CRW - Write command
533 * set VFRM - valid frame enabled
534 * set ESYN - ASYNC generation enabled
535 * set RSTN - ARST# inactive, AC97 codec not reset
536 */
537 snd_cs4281_pokeBA0(chip, BA0_ACCAD, reg);
538 snd_cs4281_pokeBA0(chip, BA0_ACCDA, val);
539 snd_cs4281_pokeBA0(chip, BA0_ACCTL, BA0_ACCTL_DCV | BA0_ACCTL_VFRM |
540 BA0_ACCTL_ESYN | (ac97->num ? BA0_ACCTL_TC : 0));
541 for (count = 0; count < 2000; count++) {
542 /*
543 * First, we want to wait for a short time.
544 */
545 udelay(10);
546 /*
547 * Now, check to see if the write has completed.
548 * ACCTL = 460h, DCV should be reset by now and 460h = 07h
549 */
550 if (!(snd_cs4281_peekBA0(chip, BA0_ACCTL) & BA0_ACCTL_DCV)) {
551 return;
552 }
553 }
554 dev_err(chip->card->dev,
555 "AC'97 write problem, reg = 0x%x, val = 0x%x\n", reg, val);
556}
557
558static unsigned short snd_cs4281_ac97_read(struct snd_ac97 *ac97,
559 unsigned short reg)
560{
561 struct cs4281 *chip = ac97->private_data;
562 int count;
563 unsigned short result;
564 // FIXME: volatile is necessary in the following due to a bug of
565 // some gcc versions
566 volatile int ac97_num = ((volatile struct snd_ac97 *)ac97)->num;
567
568 /*
569 * 1. Write ACCAD = Command Address Register = 46Ch for AC97 register address
570 * 2. Write ACCDA = Command Data Register = 470h for data to write to AC97
571 * 3. Write ACCTL = Control Register = 460h for initiating the write
572 * 4. Read ACCTL = 460h, DCV should be reset by now and 460h = 17h
573 * 5. if DCV not cleared, break and return error
574 * 6. Read ACSTS = Status Register = 464h, check VSTS bit
575 */
576
577 snd_cs4281_peekBA0(chip, ac97_num ? BA0_ACSDA2 : BA0_ACSDA);
578
579 /*
580 * Setup the AC97 control registers on the CS461x to send the
581 * appropriate command to the AC97 to perform the read.
582 * ACCAD = Command Address Register = 46Ch
583 * ACCDA = Command Data Register = 470h
584 * ACCTL = Control Register = 460h
585 * set DCV - will clear when process completed
586 * set CRW - Read command
587 * set VFRM - valid frame enabled
588 * set ESYN - ASYNC generation enabled
589 * set RSTN - ARST# inactive, AC97 codec not reset
590 */
591
592 snd_cs4281_pokeBA0(chip, BA0_ACCAD, reg);
593 snd_cs4281_pokeBA0(chip, BA0_ACCDA, 0);
594 snd_cs4281_pokeBA0(chip, BA0_ACCTL, BA0_ACCTL_DCV | BA0_ACCTL_CRW |
595 BA0_ACCTL_VFRM | BA0_ACCTL_ESYN |
596 (ac97_num ? BA0_ACCTL_TC : 0));
597
598
599 /*
600 * Wait for the read to occur.
601 */
602 for (count = 0; count < 500; count++) {
603 /*
604 * First, we want to wait for a short time.
605 */
606 udelay(10);
607 /*
608 * Now, check to see if the read has completed.
609 * ACCTL = 460h, DCV should be reset by now and 460h = 17h
610 */
611 if (!(snd_cs4281_peekBA0(chip, BA0_ACCTL) & BA0_ACCTL_DCV))
612 goto __ok1;
613 }
614
615 dev_err(chip->card->dev,
616 "AC'97 read problem (ACCTL_DCV), reg = 0x%x\n", reg);
617 result = 0xffff;
618 goto __end;
619
620 __ok1:
621 /*
622 * Wait for the valid status bit to go active.
623 */
624 for (count = 0; count < 100; count++) {
625 /*
626 * Read the AC97 status register.
627 * ACSTS = Status Register = 464h
628 * VSTS - Valid Status
629 */
630 if (snd_cs4281_peekBA0(chip, ac97_num ? BA0_ACSTS2 : BA0_ACSTS) & BA0_ACSTS_VSTS)
631 goto __ok2;
632 udelay(10);
633 }
634
635 dev_err(chip->card->dev,
636 "AC'97 read problem (ACSTS_VSTS), reg = 0x%x\n", reg);
637 result = 0xffff;
638 goto __end;
639
640 __ok2:
641 /*
642 * Read the data returned from the AC97 register.
643 * ACSDA = Status Data Register = 474h
644 */
645 result = snd_cs4281_peekBA0(chip, ac97_num ? BA0_ACSDA2 : BA0_ACSDA);
646
647 __end:
648 return result;
649}
650
651/*
652 * PCM part
653 */
654
655static int snd_cs4281_trigger(struct snd_pcm_substream *substream, int cmd)
656{
657 struct cs4281_dma *dma = substream->runtime->private_data;
658 struct cs4281 *chip = snd_pcm_substream_chip(substream);
659
660 spin_lock(&chip->reg_lock);
661 switch (cmd) {
662 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
663 dma->valDCR |= BA0_DCR_MSK;
664 dma->valFCR |= BA0_FCR_FEN;
665 break;
666 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
667 dma->valDCR &= ~BA0_DCR_MSK;
668 dma->valFCR &= ~BA0_FCR_FEN;
669 break;
670 case SNDRV_PCM_TRIGGER_START:
671 case SNDRV_PCM_TRIGGER_RESUME:
672 snd_cs4281_pokeBA0(chip, dma->regDMR, dma->valDMR & ~BA0_DMR_DMA);
673 dma->valDMR |= BA0_DMR_DMA;
674 dma->valDCR &= ~BA0_DCR_MSK;
675 dma->valFCR |= BA0_FCR_FEN;
676 break;
677 case SNDRV_PCM_TRIGGER_STOP:
678 case SNDRV_PCM_TRIGGER_SUSPEND:
679 dma->valDMR &= ~(BA0_DMR_DMA|BA0_DMR_POLL);
680 dma->valDCR |= BA0_DCR_MSK;
681 dma->valFCR &= ~BA0_FCR_FEN;
682 /* Leave wave playback FIFO enabled for FM */
683 if (dma->regFCR != BA0_FCR0)
684 dma->valFCR &= ~BA0_FCR_FEN;
685 break;
686 default:
687 spin_unlock(&chip->reg_lock);
688 return -EINVAL;
689 }
690 snd_cs4281_pokeBA0(chip, dma->regDMR, dma->valDMR);
691 snd_cs4281_pokeBA0(chip, dma->regFCR, dma->valFCR);
692 snd_cs4281_pokeBA0(chip, dma->regDCR, dma->valDCR);
693 spin_unlock(&chip->reg_lock);
694 return 0;
695}
696
697static unsigned int snd_cs4281_rate(unsigned int rate, unsigned int *real_rate)
698{
699 unsigned int val;
700
701 if (real_rate)
702 *real_rate = rate;
703 /* special "hardcoded" rates */
704 switch (rate) {
705 case 8000: return 5;
706 case 11025: return 4;
707 case 16000: return 3;
708 case 22050: return 2;
709 case 44100: return 1;
710 case 48000: return 0;
711 default:
712 break;
713 }
714 val = 1536000 / rate;
715 if (real_rate)
716 *real_rate = 1536000 / val;
717 return val;
718}
719
720static void snd_cs4281_mode(struct cs4281 *chip, struct cs4281_dma *dma,
721 struct snd_pcm_runtime *runtime,
722 int capture, int src)
723{
724 int rec_mono;
725
726 dma->valDMR = BA0_DMR_TYPE_SINGLE | BA0_DMR_AUTO |
727 (capture ? BA0_DMR_TR_WRITE : BA0_DMR_TR_READ);
728 if (runtime->channels == 1)
729 dma->valDMR |= BA0_DMR_MONO;
730 if (snd_pcm_format_unsigned(runtime->format) > 0)
731 dma->valDMR |= BA0_DMR_USIGN;
732 if (snd_pcm_format_big_endian(runtime->format) > 0)
733 dma->valDMR |= BA0_DMR_BEND;
734 switch (snd_pcm_format_width(runtime->format)) {
735 case 8: dma->valDMR |= BA0_DMR_SIZE8;
736 if (runtime->channels == 1)
737 dma->valDMR |= BA0_DMR_SWAPC;
738 break;
739 case 32: dma->valDMR |= BA0_DMR_SIZE20; break;
740 }
741 dma->frag = 0; /* for workaround */
742 dma->valDCR = BA0_DCR_TCIE | BA0_DCR_MSK;
743 if (runtime->buffer_size != runtime->period_size)
744 dma->valDCR |= BA0_DCR_HTCIE;
745 /* Initialize DMA */
746 snd_cs4281_pokeBA0(chip, dma->regDBA, runtime->dma_addr);
747 snd_cs4281_pokeBA0(chip, dma->regDBC, runtime->buffer_size - 1);
748 rec_mono = (chip->dma[1].valDMR & BA0_DMR_MONO) == BA0_DMR_MONO;
749 snd_cs4281_pokeBA0(chip, BA0_SRCSA, (chip->src_left_play_slot << 0) |
750 (chip->src_right_play_slot << 8) |
751 (chip->src_left_rec_slot << 16) |
752 ((rec_mono ? 31 : chip->src_right_rec_slot) << 24));
753 if (!src)
754 goto __skip_src;
755 if (!capture) {
756 if (dma->left_slot == chip->src_left_play_slot) {
757 unsigned int val = snd_cs4281_rate(runtime->rate, NULL);
758 snd_BUG_ON(dma->right_slot != chip->src_right_play_slot);
759 snd_cs4281_pokeBA0(chip, BA0_DACSR, val);
760 }
761 } else {
762 if (dma->left_slot == chip->src_left_rec_slot) {
763 unsigned int val = snd_cs4281_rate(runtime->rate, NULL);
764 snd_BUG_ON(dma->right_slot != chip->src_right_rec_slot);
765 snd_cs4281_pokeBA0(chip, BA0_ADCSR, val);
766 }
767 }
768 __skip_src:
769 /* Deactivate wave playback FIFO before changing slot assignments */
770 if (dma->regFCR == BA0_FCR0)
771 snd_cs4281_pokeBA0(chip, dma->regFCR, snd_cs4281_peekBA0(chip, dma->regFCR) & ~BA0_FCR_FEN);
772 /* Initialize FIFO */
773 dma->valFCR = BA0_FCR_LS(dma->left_slot) |
774 BA0_FCR_RS(capture && (dma->valDMR & BA0_DMR_MONO) ? 31 : dma->right_slot) |
775 BA0_FCR_SZ(CS4281_FIFO_SIZE) |
776 BA0_FCR_OF(dma->fifo_offset);
777 snd_cs4281_pokeBA0(chip, dma->regFCR, dma->valFCR | (capture ? BA0_FCR_PSH : 0));
778 /* Activate FIFO again for FM playback */
779 if (dma->regFCR == BA0_FCR0)
780 snd_cs4281_pokeBA0(chip, dma->regFCR, dma->valFCR | BA0_FCR_FEN);
781 /* Clear FIFO Status and Interrupt Control Register */
782 snd_cs4281_pokeBA0(chip, dma->regFSIC, 0);
783}
784
785static int snd_cs4281_playback_prepare(struct snd_pcm_substream *substream)
786{
787 struct snd_pcm_runtime *runtime = substream->runtime;
788 struct cs4281_dma *dma = runtime->private_data;
789 struct cs4281 *chip = snd_pcm_substream_chip(substream);
790
791 spin_lock_irq(&chip->reg_lock);
792 snd_cs4281_mode(chip, dma, runtime, 0, 1);
793 spin_unlock_irq(&chip->reg_lock);
794 return 0;
795}
796
797static int snd_cs4281_capture_prepare(struct snd_pcm_substream *substream)
798{
799 struct snd_pcm_runtime *runtime = substream->runtime;
800 struct cs4281_dma *dma = runtime->private_data;
801 struct cs4281 *chip = snd_pcm_substream_chip(substream);
802
803 spin_lock_irq(&chip->reg_lock);
804 snd_cs4281_mode(chip, dma, runtime, 1, 1);
805 spin_unlock_irq(&chip->reg_lock);
806 return 0;
807}
808
809static snd_pcm_uframes_t snd_cs4281_pointer(struct snd_pcm_substream *substream)
810{
811 struct snd_pcm_runtime *runtime = substream->runtime;
812 struct cs4281_dma *dma = runtime->private_data;
813 struct cs4281 *chip = snd_pcm_substream_chip(substream);
814
815 /*
816 dev_dbg(chip->card->dev,
817 "DCC = 0x%x, buffer_size = 0x%x, jiffies = %li\n",
818 snd_cs4281_peekBA0(chip, dma->regDCC), runtime->buffer_size,
819 jiffies);
820 */
821 return runtime->buffer_size -
822 snd_cs4281_peekBA0(chip, dma->regDCC) - 1;
823}
824
825static const struct snd_pcm_hardware snd_cs4281_playback =
826{
827 .info = SNDRV_PCM_INFO_MMAP |
828 SNDRV_PCM_INFO_INTERLEAVED |
829 SNDRV_PCM_INFO_MMAP_VALID |
830 SNDRV_PCM_INFO_PAUSE |
831 SNDRV_PCM_INFO_RESUME,
832 .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S8 |
833 SNDRV_PCM_FMTBIT_U16_LE | SNDRV_PCM_FMTBIT_S16_LE |
834 SNDRV_PCM_FMTBIT_U16_BE | SNDRV_PCM_FMTBIT_S16_BE |
835 SNDRV_PCM_FMTBIT_U32_LE | SNDRV_PCM_FMTBIT_S32_LE |
836 SNDRV_PCM_FMTBIT_U32_BE | SNDRV_PCM_FMTBIT_S32_BE,
837 .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
838 .rate_min = 4000,
839 .rate_max = 48000,
840 .channels_min = 1,
841 .channels_max = 2,
842 .buffer_bytes_max = (512*1024),
843 .period_bytes_min = 64,
844 .period_bytes_max = (512*1024),
845 .periods_min = 1,
846 .periods_max = 2,
847 .fifo_size = CS4281_FIFO_SIZE,
848};
849
850static const struct snd_pcm_hardware snd_cs4281_capture =
851{
852 .info = SNDRV_PCM_INFO_MMAP |
853 SNDRV_PCM_INFO_INTERLEAVED |
854 SNDRV_PCM_INFO_MMAP_VALID |
855 SNDRV_PCM_INFO_PAUSE |
856 SNDRV_PCM_INFO_RESUME,
857 .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S8 |
858 SNDRV_PCM_FMTBIT_U16_LE | SNDRV_PCM_FMTBIT_S16_LE |
859 SNDRV_PCM_FMTBIT_U16_BE | SNDRV_PCM_FMTBIT_S16_BE |
860 SNDRV_PCM_FMTBIT_U32_LE | SNDRV_PCM_FMTBIT_S32_LE |
861 SNDRV_PCM_FMTBIT_U32_BE | SNDRV_PCM_FMTBIT_S32_BE,
862 .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
863 .rate_min = 4000,
864 .rate_max = 48000,
865 .channels_min = 1,
866 .channels_max = 2,
867 .buffer_bytes_max = (512*1024),
868 .period_bytes_min = 64,
869 .period_bytes_max = (512*1024),
870 .periods_min = 1,
871 .periods_max = 2,
872 .fifo_size = CS4281_FIFO_SIZE,
873};
874
875static int snd_cs4281_playback_open(struct snd_pcm_substream *substream)
876{
877 struct cs4281 *chip = snd_pcm_substream_chip(substream);
878 struct snd_pcm_runtime *runtime = substream->runtime;
879 struct cs4281_dma *dma;
880
881 dma = &chip->dma[0];
882 dma->substream = substream;
883 dma->left_slot = 0;
884 dma->right_slot = 1;
885 runtime->private_data = dma;
886 runtime->hw = snd_cs4281_playback;
887 /* should be detected from the AC'97 layer, but it seems
888 that although CS4297A rev B reports 18-bit ADC resolution,
889 samples are 20-bit */
890 snd_pcm_hw_constraint_msbits(runtime, 0, 32, 20);
891 return 0;
892}
893
894static int snd_cs4281_capture_open(struct snd_pcm_substream *substream)
895{
896 struct cs4281 *chip = snd_pcm_substream_chip(substream);
897 struct snd_pcm_runtime *runtime = substream->runtime;
898 struct cs4281_dma *dma;
899
900 dma = &chip->dma[1];
901 dma->substream = substream;
902 dma->left_slot = 10;
903 dma->right_slot = 11;
904 runtime->private_data = dma;
905 runtime->hw = snd_cs4281_capture;
906 /* should be detected from the AC'97 layer, but it seems
907 that although CS4297A rev B reports 18-bit ADC resolution,
908 samples are 20-bit */
909 snd_pcm_hw_constraint_msbits(runtime, 0, 32, 20);
910 return 0;
911}
912
913static int snd_cs4281_playback_close(struct snd_pcm_substream *substream)
914{
915 struct cs4281_dma *dma = substream->runtime->private_data;
916
917 dma->substream = NULL;
918 return 0;
919}
920
921static int snd_cs4281_capture_close(struct snd_pcm_substream *substream)
922{
923 struct cs4281_dma *dma = substream->runtime->private_data;
924
925 dma->substream = NULL;
926 return 0;
927}
928
929static const struct snd_pcm_ops snd_cs4281_playback_ops = {
930 .open = snd_cs4281_playback_open,
931 .close = snd_cs4281_playback_close,
932 .prepare = snd_cs4281_playback_prepare,
933 .trigger = snd_cs4281_trigger,
934 .pointer = snd_cs4281_pointer,
935};
936
937static const struct snd_pcm_ops snd_cs4281_capture_ops = {
938 .open = snd_cs4281_capture_open,
939 .close = snd_cs4281_capture_close,
940 .prepare = snd_cs4281_capture_prepare,
941 .trigger = snd_cs4281_trigger,
942 .pointer = snd_cs4281_pointer,
943};
944
945static int snd_cs4281_pcm(struct cs4281 *chip, int device)
946{
947 struct snd_pcm *pcm;
948 int err;
949
950 err = snd_pcm_new(chip->card, "CS4281", device, 1, 1, &pcm);
951 if (err < 0)
952 return err;
953
954 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cs4281_playback_ops);
955 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_cs4281_capture_ops);
956
957 pcm->private_data = chip;
958 pcm->info_flags = 0;
959 strcpy(pcm->name, "CS4281");
960 chip->pcm = pcm;
961
962 snd_pcm_set_managed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV, &chip->pci->dev,
963 64*1024, 512*1024);
964
965 return 0;
966}
967
968/*
969 * Mixer section
970 */
971
972#define CS_VOL_MASK 0x1f
973
974static int snd_cs4281_info_volume(struct snd_kcontrol *kcontrol,
975 struct snd_ctl_elem_info *uinfo)
976{
977 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
978 uinfo->count = 2;
979 uinfo->value.integer.min = 0;
980 uinfo->value.integer.max = CS_VOL_MASK;
981 return 0;
982}
983
984static int snd_cs4281_get_volume(struct snd_kcontrol *kcontrol,
985 struct snd_ctl_elem_value *ucontrol)
986{
987 struct cs4281 *chip = snd_kcontrol_chip(kcontrol);
988 int regL = (kcontrol->private_value >> 16) & 0xffff;
989 int regR = kcontrol->private_value & 0xffff;
990 int volL, volR;
991
992 volL = CS_VOL_MASK - (snd_cs4281_peekBA0(chip, regL) & CS_VOL_MASK);
993 volR = CS_VOL_MASK - (snd_cs4281_peekBA0(chip, regR) & CS_VOL_MASK);
994
995 ucontrol->value.integer.value[0] = volL;
996 ucontrol->value.integer.value[1] = volR;
997 return 0;
998}
999
1000static int snd_cs4281_put_volume(struct snd_kcontrol *kcontrol,
1001 struct snd_ctl_elem_value *ucontrol)
1002{
1003 struct cs4281 *chip = snd_kcontrol_chip(kcontrol);
1004 int change = 0;
1005 int regL = (kcontrol->private_value >> 16) & 0xffff;
1006 int regR = kcontrol->private_value & 0xffff;
1007 int volL, volR;
1008
1009 volL = CS_VOL_MASK - (snd_cs4281_peekBA0(chip, regL) & CS_VOL_MASK);
1010 volR = CS_VOL_MASK - (snd_cs4281_peekBA0(chip, regR) & CS_VOL_MASK);
1011
1012 if (ucontrol->value.integer.value[0] != volL) {
1013 volL = CS_VOL_MASK - (ucontrol->value.integer.value[0] & CS_VOL_MASK);
1014 snd_cs4281_pokeBA0(chip, regL, volL);
1015 change = 1;
1016 }
1017 if (ucontrol->value.integer.value[1] != volR) {
1018 volR = CS_VOL_MASK - (ucontrol->value.integer.value[1] & CS_VOL_MASK);
1019 snd_cs4281_pokeBA0(chip, regR, volR);
1020 change = 1;
1021 }
1022 return change;
1023}
1024
1025static const DECLARE_TLV_DB_SCALE(db_scale_dsp, -4650, 150, 0);
1026
1027static const struct snd_kcontrol_new snd_cs4281_fm_vol =
1028{
1029 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
1030 .name = "Synth Playback Volume",
1031 .info = snd_cs4281_info_volume,
1032 .get = snd_cs4281_get_volume,
1033 .put = snd_cs4281_put_volume,
1034 .private_value = ((BA0_FMLVC << 16) | BA0_FMRVC),
1035 .tlv = { .p = db_scale_dsp },
1036};
1037
1038static const struct snd_kcontrol_new snd_cs4281_pcm_vol =
1039{
1040 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
1041 .name = "PCM Stream Playback Volume",
1042 .info = snd_cs4281_info_volume,
1043 .get = snd_cs4281_get_volume,
1044 .put = snd_cs4281_put_volume,
1045 .private_value = ((BA0_PPLVC << 16) | BA0_PPRVC),
1046 .tlv = { .p = db_scale_dsp },
1047};
1048
1049static void snd_cs4281_mixer_free_ac97_bus(struct snd_ac97_bus *bus)
1050{
1051 struct cs4281 *chip = bus->private_data;
1052 chip->ac97_bus = NULL;
1053}
1054
1055static void snd_cs4281_mixer_free_ac97(struct snd_ac97 *ac97)
1056{
1057 struct cs4281 *chip = ac97->private_data;
1058 if (ac97->num)
1059 chip->ac97_secondary = NULL;
1060 else
1061 chip->ac97 = NULL;
1062}
1063
1064static int snd_cs4281_mixer(struct cs4281 *chip)
1065{
1066 struct snd_card *card = chip->card;
1067 struct snd_ac97_template ac97;
1068 int err;
1069 static const struct snd_ac97_bus_ops ops = {
1070 .write = snd_cs4281_ac97_write,
1071 .read = snd_cs4281_ac97_read,
1072 };
1073
1074 if ((err = snd_ac97_bus(card, 0, &ops, chip, &chip->ac97_bus)) < 0)
1075 return err;
1076 chip->ac97_bus->private_free = snd_cs4281_mixer_free_ac97_bus;
1077
1078 memset(&ac97, 0, sizeof(ac97));
1079 ac97.private_data = chip;
1080 ac97.private_free = snd_cs4281_mixer_free_ac97;
1081 if ((err = snd_ac97_mixer(chip->ac97_bus, &ac97, &chip->ac97)) < 0)
1082 return err;
1083 if (chip->dual_codec) {
1084 ac97.num = 1;
1085 if ((err = snd_ac97_mixer(chip->ac97_bus, &ac97, &chip->ac97_secondary)) < 0)
1086 return err;
1087 }
1088 if ((err = snd_ctl_add(card, snd_ctl_new1(&snd_cs4281_fm_vol, chip))) < 0)
1089 return err;
1090 if ((err = snd_ctl_add(card, snd_ctl_new1(&snd_cs4281_pcm_vol, chip))) < 0)
1091 return err;
1092 return 0;
1093}
1094
1095
1096/*
1097 * proc interface
1098 */
1099
1100static void snd_cs4281_proc_read(struct snd_info_entry *entry,
1101 struct snd_info_buffer *buffer)
1102{
1103 struct cs4281 *chip = entry->private_data;
1104
1105 snd_iprintf(buffer, "Cirrus Logic CS4281\n\n");
1106 snd_iprintf(buffer, "Spurious half IRQs : %u\n", chip->spurious_dhtc_irq);
1107 snd_iprintf(buffer, "Spurious end IRQs : %u\n", chip->spurious_dtc_irq);
1108}
1109
1110static ssize_t snd_cs4281_BA0_read(struct snd_info_entry *entry,
1111 void *file_private_data,
1112 struct file *file, char __user *buf,
1113 size_t count, loff_t pos)
1114{
1115 struct cs4281 *chip = entry->private_data;
1116
1117 if (copy_to_user_fromio(buf, chip->ba0 + pos, count))
1118 return -EFAULT;
1119 return count;
1120}
1121
1122static ssize_t snd_cs4281_BA1_read(struct snd_info_entry *entry,
1123 void *file_private_data,
1124 struct file *file, char __user *buf,
1125 size_t count, loff_t pos)
1126{
1127 struct cs4281 *chip = entry->private_data;
1128
1129 if (copy_to_user_fromio(buf, chip->ba1 + pos, count))
1130 return -EFAULT;
1131 return count;
1132}
1133
1134static const struct snd_info_entry_ops snd_cs4281_proc_ops_BA0 = {
1135 .read = snd_cs4281_BA0_read,
1136};
1137
1138static const struct snd_info_entry_ops snd_cs4281_proc_ops_BA1 = {
1139 .read = snd_cs4281_BA1_read,
1140};
1141
1142static void snd_cs4281_proc_init(struct cs4281 *chip)
1143{
1144 struct snd_info_entry *entry;
1145
1146 snd_card_ro_proc_new(chip->card, "cs4281", chip, snd_cs4281_proc_read);
1147 if (! snd_card_proc_new(chip->card, "cs4281_BA0", &entry)) {
1148 entry->content = SNDRV_INFO_CONTENT_DATA;
1149 entry->private_data = chip;
1150 entry->c.ops = &snd_cs4281_proc_ops_BA0;
1151 entry->size = CS4281_BA0_SIZE;
1152 }
1153 if (! snd_card_proc_new(chip->card, "cs4281_BA1", &entry)) {
1154 entry->content = SNDRV_INFO_CONTENT_DATA;
1155 entry->private_data = chip;
1156 entry->c.ops = &snd_cs4281_proc_ops_BA1;
1157 entry->size = CS4281_BA1_SIZE;
1158 }
1159}
1160
1161/*
1162 * joystick support
1163 */
1164
1165#if IS_REACHABLE(CONFIG_GAMEPORT)
1166
1167static void snd_cs4281_gameport_trigger(struct gameport *gameport)
1168{
1169 struct cs4281 *chip = gameport_get_port_data(gameport);
1170
1171 if (snd_BUG_ON(!chip))
1172 return;
1173 snd_cs4281_pokeBA0(chip, BA0_JSPT, 0xff);
1174}
1175
1176static unsigned char snd_cs4281_gameport_read(struct gameport *gameport)
1177{
1178 struct cs4281 *chip = gameport_get_port_data(gameport);
1179
1180 if (snd_BUG_ON(!chip))
1181 return 0;
1182 return snd_cs4281_peekBA0(chip, BA0_JSPT);
1183}
1184
1185#ifdef COOKED_MODE
1186static int snd_cs4281_gameport_cooked_read(struct gameport *gameport,
1187 int *axes, int *buttons)
1188{
1189 struct cs4281 *chip = gameport_get_port_data(gameport);
1190 unsigned js1, js2, jst;
1191
1192 if (snd_BUG_ON(!chip))
1193 return 0;
1194
1195 js1 = snd_cs4281_peekBA0(chip, BA0_JSC1);
1196 js2 = snd_cs4281_peekBA0(chip, BA0_JSC2);
1197 jst = snd_cs4281_peekBA0(chip, BA0_JSPT);
1198
1199 *buttons = (~jst >> 4) & 0x0F;
1200
1201 axes[0] = ((js1 & JSC1_Y1V_MASK) >> JSC1_Y1V_SHIFT) & 0xFFFF;
1202 axes[1] = ((js1 & JSC1_X1V_MASK) >> JSC1_X1V_SHIFT) & 0xFFFF;
1203 axes[2] = ((js2 & JSC2_Y2V_MASK) >> JSC2_Y2V_SHIFT) & 0xFFFF;
1204 axes[3] = ((js2 & JSC2_X2V_MASK) >> JSC2_X2V_SHIFT) & 0xFFFF;
1205
1206 for (jst = 0; jst < 4; ++jst)
1207 if (axes[jst] == 0xFFFF) axes[jst] = -1;
1208 return 0;
1209}
1210#else
1211#define snd_cs4281_gameport_cooked_read NULL
1212#endif
1213
1214static int snd_cs4281_gameport_open(struct gameport *gameport, int mode)
1215{
1216 switch (mode) {
1217#ifdef COOKED_MODE
1218 case GAMEPORT_MODE_COOKED:
1219 return 0;
1220#endif
1221 case GAMEPORT_MODE_RAW:
1222 return 0;
1223 default:
1224 return -1;
1225 }
1226 return 0;
1227}
1228
1229static int snd_cs4281_create_gameport(struct cs4281 *chip)
1230{
1231 struct gameport *gp;
1232
1233 chip->gameport = gp = gameport_allocate_port();
1234 if (!gp) {
1235 dev_err(chip->card->dev,
1236 "cannot allocate memory for gameport\n");
1237 return -ENOMEM;
1238 }
1239
1240 gameport_set_name(gp, "CS4281 Gameport");
1241 gameport_set_phys(gp, "pci%s/gameport0", pci_name(chip->pci));
1242 gameport_set_dev_parent(gp, &chip->pci->dev);
1243 gp->open = snd_cs4281_gameport_open;
1244 gp->read = snd_cs4281_gameport_read;
1245 gp->trigger = snd_cs4281_gameport_trigger;
1246 gp->cooked_read = snd_cs4281_gameport_cooked_read;
1247 gameport_set_port_data(gp, chip);
1248
1249 snd_cs4281_pokeBA0(chip, BA0_JSIO, 0xFF); // ?
1250 snd_cs4281_pokeBA0(chip, BA0_JSCTL, JSCTL_SP_MEDIUM_SLOW);
1251
1252 gameport_register_port(gp);
1253
1254 return 0;
1255}
1256
1257static void snd_cs4281_free_gameport(struct cs4281 *chip)
1258{
1259 if (chip->gameport) {
1260 gameport_unregister_port(chip->gameport);
1261 chip->gameport = NULL;
1262 }
1263}
1264#else
1265static inline int snd_cs4281_create_gameport(struct cs4281 *chip) { return -ENOSYS; }
1266static inline void snd_cs4281_free_gameport(struct cs4281 *chip) { }
1267#endif /* IS_REACHABLE(CONFIG_GAMEPORT) */
1268
1269static int snd_cs4281_free(struct cs4281 *chip)
1270{
1271 snd_cs4281_free_gameport(chip);
1272
1273 /* Mask interrupts */
1274 snd_cs4281_pokeBA0(chip, BA0_HIMR, 0x7fffffff);
1275 /* Stop the DLL Clock logic. */
1276 snd_cs4281_pokeBA0(chip, BA0_CLKCR1, 0);
1277 /* Sound System Power Management - Turn Everything OFF */
1278 snd_cs4281_pokeBA0(chip, BA0_SSPM, 0);
1279 /* PCI interface - D3 state */
1280 pci_set_power_state(chip->pci, PCI_D3hot);
1281
1282 if (chip->irq >= 0)
1283 free_irq(chip->irq, chip);
1284 iounmap(chip->ba0);
1285 iounmap(chip->ba1);
1286 pci_release_regions(chip->pci);
1287 pci_disable_device(chip->pci);
1288
1289 kfree(chip);
1290 return 0;
1291}
1292
1293static int snd_cs4281_dev_free(struct snd_device *device)
1294{
1295 struct cs4281 *chip = device->device_data;
1296 return snd_cs4281_free(chip);
1297}
1298
1299static int snd_cs4281_chip_init(struct cs4281 *chip); /* defined below */
1300
1301static int snd_cs4281_create(struct snd_card *card,
1302 struct pci_dev *pci,
1303 struct cs4281 **rchip,
1304 int dual_codec)
1305{
1306 struct cs4281 *chip;
1307 unsigned int tmp;
1308 int err;
1309 static const struct snd_device_ops ops = {
1310 .dev_free = snd_cs4281_dev_free,
1311 };
1312
1313 *rchip = NULL;
1314 if ((err = pci_enable_device(pci)) < 0)
1315 return err;
1316 chip = kzalloc(sizeof(*chip), GFP_KERNEL);
1317 if (chip == NULL) {
1318 pci_disable_device(pci);
1319 return -ENOMEM;
1320 }
1321 spin_lock_init(&chip->reg_lock);
1322 chip->card = card;
1323 chip->pci = pci;
1324 chip->irq = -1;
1325 pci_set_master(pci);
1326 if (dual_codec < 0 || dual_codec > 3) {
1327 dev_err(card->dev, "invalid dual_codec option %d\n", dual_codec);
1328 dual_codec = 0;
1329 }
1330 chip->dual_codec = dual_codec;
1331
1332 if ((err = pci_request_regions(pci, "CS4281")) < 0) {
1333 kfree(chip);
1334 pci_disable_device(pci);
1335 return err;
1336 }
1337 chip->ba0_addr = pci_resource_start(pci, 0);
1338 chip->ba1_addr = pci_resource_start(pci, 1);
1339
1340 chip->ba0 = pci_ioremap_bar(pci, 0);
1341 chip->ba1 = pci_ioremap_bar(pci, 1);
1342 if (!chip->ba0 || !chip->ba1) {
1343 snd_cs4281_free(chip);
1344 return -ENOMEM;
1345 }
1346
1347 if (request_irq(pci->irq, snd_cs4281_interrupt, IRQF_SHARED,
1348 KBUILD_MODNAME, chip)) {
1349 dev_err(card->dev, "unable to grab IRQ %d\n", pci->irq);
1350 snd_cs4281_free(chip);
1351 return -ENOMEM;
1352 }
1353 chip->irq = pci->irq;
1354 card->sync_irq = chip->irq;
1355
1356 tmp = snd_cs4281_chip_init(chip);
1357 if (tmp) {
1358 snd_cs4281_free(chip);
1359 return tmp;
1360 }
1361
1362 if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) < 0) {
1363 snd_cs4281_free(chip);
1364 return err;
1365 }
1366
1367 snd_cs4281_proc_init(chip);
1368
1369 *rchip = chip;
1370 return 0;
1371}
1372
1373static int snd_cs4281_chip_init(struct cs4281 *chip)
1374{
1375 unsigned int tmp;
1376 unsigned long end_time;
1377 int retry_count = 2;
1378
1379 /* Having EPPMC.FPDN=1 prevent proper chip initialisation */
1380 tmp = snd_cs4281_peekBA0(chip, BA0_EPPMC);
1381 if (tmp & BA0_EPPMC_FPDN)
1382 snd_cs4281_pokeBA0(chip, BA0_EPPMC, tmp & ~BA0_EPPMC_FPDN);
1383
1384 __retry:
1385 tmp = snd_cs4281_peekBA0(chip, BA0_CFLR);
1386 if (tmp != BA0_CFLR_DEFAULT) {
1387 snd_cs4281_pokeBA0(chip, BA0_CFLR, BA0_CFLR_DEFAULT);
1388 tmp = snd_cs4281_peekBA0(chip, BA0_CFLR);
1389 if (tmp != BA0_CFLR_DEFAULT) {
1390 dev_err(chip->card->dev,
1391 "CFLR setup failed (0x%x)\n", tmp);
1392 return -EIO;
1393 }
1394 }
1395
1396 /* Set the 'Configuration Write Protect' register
1397 * to 4281h. Allows vendor-defined configuration
1398 * space between 0e4h and 0ffh to be written. */
1399 snd_cs4281_pokeBA0(chip, BA0_CWPR, 0x4281);
1400
1401 if ((tmp = snd_cs4281_peekBA0(chip, BA0_SERC1)) != (BA0_SERC1_SO1EN | BA0_SERC1_AC97)) {
1402 dev_err(chip->card->dev,
1403 "SERC1 AC'97 check failed (0x%x)\n", tmp);
1404 return -EIO;
1405 }
1406 if ((tmp = snd_cs4281_peekBA0(chip, BA0_SERC2)) != (BA0_SERC2_SI1EN | BA0_SERC2_AC97)) {
1407 dev_err(chip->card->dev,
1408 "SERC2 AC'97 check failed (0x%x)\n", tmp);
1409 return -EIO;
1410 }
1411
1412 /* Sound System Power Management */
1413 snd_cs4281_pokeBA0(chip, BA0_SSPM, BA0_SSPM_MIXEN | BA0_SSPM_CSRCEN |
1414 BA0_SSPM_PSRCEN | BA0_SSPM_JSEN |
1415 BA0_SSPM_ACLEN | BA0_SSPM_FMEN);
1416
1417 /* Serial Port Power Management */
1418 /* Blast the clock control register to zero so that the
1419 * PLL starts out in a known state, and blast the master serial
1420 * port control register to zero so that the serial ports also
1421 * start out in a known state. */
1422 snd_cs4281_pokeBA0(chip, BA0_CLKCR1, 0);
1423 snd_cs4281_pokeBA0(chip, BA0_SERMC, 0);
1424
1425 /* Make ESYN go to zero to turn off
1426 * the Sync pulse on the AC97 link. */
1427 snd_cs4281_pokeBA0(chip, BA0_ACCTL, 0);
1428 udelay(50);
1429
1430 /* Drive the ARST# pin low for a minimum of 1uS (as defined in the AC97
1431 * spec) and then drive it high. This is done for non AC97 modes since
1432 * there might be logic external to the CS4281 that uses the ARST# line
1433 * for a reset. */
1434 snd_cs4281_pokeBA0(chip, BA0_SPMC, 0);
1435 udelay(50);
1436 snd_cs4281_pokeBA0(chip, BA0_SPMC, BA0_SPMC_RSTN);
1437 msleep(50);
1438
1439 if (chip->dual_codec)
1440 snd_cs4281_pokeBA0(chip, BA0_SPMC, BA0_SPMC_RSTN | BA0_SPMC_ASDI2E);
1441
1442 /*
1443 * Set the serial port timing configuration.
1444 */
1445 snd_cs4281_pokeBA0(chip, BA0_SERMC,
1446 (chip->dual_codec ? BA0_SERMC_TCID(chip->dual_codec) : BA0_SERMC_TCID(1)) |
1447 BA0_SERMC_PTC_AC97 | BA0_SERMC_MSPE);
1448
1449 /*
1450 * Start the DLL Clock logic.
1451 */
1452 snd_cs4281_pokeBA0(chip, BA0_CLKCR1, BA0_CLKCR1_DLLP);
1453 msleep(50);
1454 snd_cs4281_pokeBA0(chip, BA0_CLKCR1, BA0_CLKCR1_SWCE | BA0_CLKCR1_DLLP);
1455
1456 /*
1457 * Wait for the DLL ready signal from the clock logic.
1458 */
1459 end_time = jiffies + HZ;
1460 do {
1461 /*
1462 * Read the AC97 status register to see if we've seen a CODEC
1463 * signal from the AC97 codec.
1464 */
1465 if (snd_cs4281_peekBA0(chip, BA0_CLKCR1) & BA0_CLKCR1_DLLRDY)
1466 goto __ok0;
1467 schedule_timeout_uninterruptible(1);
1468 } while (time_after_eq(end_time, jiffies));
1469
1470 dev_err(chip->card->dev, "DLLRDY not seen\n");
1471 return -EIO;
1472
1473 __ok0:
1474
1475 /*
1476 * The first thing we do here is to enable sync generation. As soon
1477 * as we start receiving bit clock, we'll start producing the SYNC
1478 * signal.
1479 */
1480 snd_cs4281_pokeBA0(chip, BA0_ACCTL, BA0_ACCTL_ESYN);
1481
1482 /*
1483 * Wait for the codec ready signal from the AC97 codec.
1484 */
1485 end_time = jiffies + HZ;
1486 do {
1487 /*
1488 * Read the AC97 status register to see if we've seen a CODEC
1489 * signal from the AC97 codec.
1490 */
1491 if (snd_cs4281_peekBA0(chip, BA0_ACSTS) & BA0_ACSTS_CRDY)
1492 goto __ok1;
1493 schedule_timeout_uninterruptible(1);
1494 } while (time_after_eq(end_time, jiffies));
1495
1496 dev_err(chip->card->dev,
1497 "never read codec ready from AC'97 (0x%x)\n",
1498 snd_cs4281_peekBA0(chip, BA0_ACSTS));
1499 return -EIO;
1500
1501 __ok1:
1502 if (chip->dual_codec) {
1503 end_time = jiffies + HZ;
1504 do {
1505 if (snd_cs4281_peekBA0(chip, BA0_ACSTS2) & BA0_ACSTS_CRDY)
1506 goto __codec2_ok;
1507 schedule_timeout_uninterruptible(1);
1508 } while (time_after_eq(end_time, jiffies));
1509 dev_info(chip->card->dev,
1510 "secondary codec doesn't respond. disable it...\n");
1511 chip->dual_codec = 0;
1512 __codec2_ok: ;
1513 }
1514
1515 /*
1516 * Assert the valid frame signal so that we can start sending commands
1517 * to the AC97 codec.
1518 */
1519
1520 snd_cs4281_pokeBA0(chip, BA0_ACCTL, BA0_ACCTL_VFRM | BA0_ACCTL_ESYN);
1521
1522 /*
1523 * Wait until we've sampled input slots 3 and 4 as valid, meaning that
1524 * the codec is pumping ADC data across the AC-link.
1525 */
1526
1527 end_time = jiffies + HZ;
1528 do {
1529 /*
1530 * Read the input slot valid register and see if input slots 3
1531 * 4 are valid yet.
1532 */
1533 if ((snd_cs4281_peekBA0(chip, BA0_ACISV) & (BA0_ACISV_SLV(3) | BA0_ACISV_SLV(4))) == (BA0_ACISV_SLV(3) | BA0_ACISV_SLV(4)))
1534 goto __ok2;
1535 schedule_timeout_uninterruptible(1);
1536 } while (time_after_eq(end_time, jiffies));
1537
1538 if (--retry_count > 0)
1539 goto __retry;
1540 dev_err(chip->card->dev, "never read ISV3 and ISV4 from AC'97\n");
1541 return -EIO;
1542
1543 __ok2:
1544
1545 /*
1546 * Now, assert valid frame and the slot 3 and 4 valid bits. This will
1547 * commense the transfer of digital audio data to the AC97 codec.
1548 */
1549 snd_cs4281_pokeBA0(chip, BA0_ACOSV, BA0_ACOSV_SLV(3) | BA0_ACOSV_SLV(4));
1550
1551 /*
1552 * Initialize DMA structures
1553 */
1554 for (tmp = 0; tmp < 4; tmp++) {
1555 struct cs4281_dma *dma = &chip->dma[tmp];
1556 dma->regDBA = BA0_DBA0 + (tmp * 0x10);
1557 dma->regDCA = BA0_DCA0 + (tmp * 0x10);
1558 dma->regDBC = BA0_DBC0 + (tmp * 0x10);
1559 dma->regDCC = BA0_DCC0 + (tmp * 0x10);
1560 dma->regDMR = BA0_DMR0 + (tmp * 8);
1561 dma->regDCR = BA0_DCR0 + (tmp * 8);
1562 dma->regHDSR = BA0_HDSR0 + (tmp * 4);
1563 dma->regFCR = BA0_FCR0 + (tmp * 4);
1564 dma->regFSIC = BA0_FSIC0 + (tmp * 4);
1565 dma->fifo_offset = tmp * CS4281_FIFO_SIZE;
1566 snd_cs4281_pokeBA0(chip, dma->regFCR,
1567 BA0_FCR_LS(31) |
1568 BA0_FCR_RS(31) |
1569 BA0_FCR_SZ(CS4281_FIFO_SIZE) |
1570 BA0_FCR_OF(dma->fifo_offset));
1571 }
1572
1573 chip->src_left_play_slot = 0; /* AC'97 left PCM playback (3) */
1574 chip->src_right_play_slot = 1; /* AC'97 right PCM playback (4) */
1575 chip->src_left_rec_slot = 10; /* AC'97 left PCM record (3) */
1576 chip->src_right_rec_slot = 11; /* AC'97 right PCM record (4) */
1577
1578 /* Activate wave playback FIFO for FM playback */
1579 chip->dma[0].valFCR = BA0_FCR_FEN | BA0_FCR_LS(0) |
1580 BA0_FCR_RS(1) |
1581 BA0_FCR_SZ(CS4281_FIFO_SIZE) |
1582 BA0_FCR_OF(chip->dma[0].fifo_offset);
1583 snd_cs4281_pokeBA0(chip, chip->dma[0].regFCR, chip->dma[0].valFCR);
1584 snd_cs4281_pokeBA0(chip, BA0_SRCSA, (chip->src_left_play_slot << 0) |
1585 (chip->src_right_play_slot << 8) |
1586 (chip->src_left_rec_slot << 16) |
1587 (chip->src_right_rec_slot << 24));
1588
1589 /* Initialize digital volume */
1590 snd_cs4281_pokeBA0(chip, BA0_PPLVC, 0);
1591 snd_cs4281_pokeBA0(chip, BA0_PPRVC, 0);
1592
1593 /* Enable IRQs */
1594 snd_cs4281_pokeBA0(chip, BA0_HICR, BA0_HICR_EOI);
1595 /* Unmask interrupts */
1596 snd_cs4281_pokeBA0(chip, BA0_HIMR, 0x7fffffff & ~(
1597 BA0_HISR_MIDI |
1598 BA0_HISR_DMAI |
1599 BA0_HISR_DMA(0) |
1600 BA0_HISR_DMA(1) |
1601 BA0_HISR_DMA(2) |
1602 BA0_HISR_DMA(3)));
1603
1604 return 0;
1605}
1606
1607/*
1608 * MIDI section
1609 */
1610
1611static void snd_cs4281_midi_reset(struct cs4281 *chip)
1612{
1613 snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr | BA0_MIDCR_MRST);
1614 udelay(100);
1615 snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr);
1616}
1617
1618static int snd_cs4281_midi_input_open(struct snd_rawmidi_substream *substream)
1619{
1620 struct cs4281 *chip = substream->rmidi->private_data;
1621
1622 spin_lock_irq(&chip->reg_lock);
1623 chip->midcr |= BA0_MIDCR_RXE;
1624 chip->midi_input = substream;
1625 if (!(chip->uartm & CS4281_MODE_OUTPUT)) {
1626 snd_cs4281_midi_reset(chip);
1627 } else {
1628 snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr);
1629 }
1630 spin_unlock_irq(&chip->reg_lock);
1631 return 0;
1632}
1633
1634static int snd_cs4281_midi_input_close(struct snd_rawmidi_substream *substream)
1635{
1636 struct cs4281 *chip = substream->rmidi->private_data;
1637
1638 spin_lock_irq(&chip->reg_lock);
1639 chip->midcr &= ~(BA0_MIDCR_RXE | BA0_MIDCR_RIE);
1640 chip->midi_input = NULL;
1641 if (!(chip->uartm & CS4281_MODE_OUTPUT)) {
1642 snd_cs4281_midi_reset(chip);
1643 } else {
1644 snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr);
1645 }
1646 chip->uartm &= ~CS4281_MODE_INPUT;
1647 spin_unlock_irq(&chip->reg_lock);
1648 return 0;
1649}
1650
1651static int snd_cs4281_midi_output_open(struct snd_rawmidi_substream *substream)
1652{
1653 struct cs4281 *chip = substream->rmidi->private_data;
1654
1655 spin_lock_irq(&chip->reg_lock);
1656 chip->uartm |= CS4281_MODE_OUTPUT;
1657 chip->midcr |= BA0_MIDCR_TXE;
1658 chip->midi_output = substream;
1659 if (!(chip->uartm & CS4281_MODE_INPUT)) {
1660 snd_cs4281_midi_reset(chip);
1661 } else {
1662 snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr);
1663 }
1664 spin_unlock_irq(&chip->reg_lock);
1665 return 0;
1666}
1667
1668static int snd_cs4281_midi_output_close(struct snd_rawmidi_substream *substream)
1669{
1670 struct cs4281 *chip = substream->rmidi->private_data;
1671
1672 spin_lock_irq(&chip->reg_lock);
1673 chip->midcr &= ~(BA0_MIDCR_TXE | BA0_MIDCR_TIE);
1674 chip->midi_output = NULL;
1675 if (!(chip->uartm & CS4281_MODE_INPUT)) {
1676 snd_cs4281_midi_reset(chip);
1677 } else {
1678 snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr);
1679 }
1680 chip->uartm &= ~CS4281_MODE_OUTPUT;
1681 spin_unlock_irq(&chip->reg_lock);
1682 return 0;
1683}
1684
1685static void snd_cs4281_midi_input_trigger(struct snd_rawmidi_substream *substream, int up)
1686{
1687 unsigned long flags;
1688 struct cs4281 *chip = substream->rmidi->private_data;
1689
1690 spin_lock_irqsave(&chip->reg_lock, flags);
1691 if (up) {
1692 if ((chip->midcr & BA0_MIDCR_RIE) == 0) {
1693 chip->midcr |= BA0_MIDCR_RIE;
1694 snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr);
1695 }
1696 } else {
1697 if (chip->midcr & BA0_MIDCR_RIE) {
1698 chip->midcr &= ~BA0_MIDCR_RIE;
1699 snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr);
1700 }
1701 }
1702 spin_unlock_irqrestore(&chip->reg_lock, flags);
1703}
1704
1705static void snd_cs4281_midi_output_trigger(struct snd_rawmidi_substream *substream, int up)
1706{
1707 unsigned long flags;
1708 struct cs4281 *chip = substream->rmidi->private_data;
1709 unsigned char byte;
1710
1711 spin_lock_irqsave(&chip->reg_lock, flags);
1712 if (up) {
1713 if ((chip->midcr & BA0_MIDCR_TIE) == 0) {
1714 chip->midcr |= BA0_MIDCR_TIE;
1715 /* fill UART FIFO buffer at first, and turn Tx interrupts only if necessary */
1716 while ((chip->midcr & BA0_MIDCR_TIE) &&
1717 (snd_cs4281_peekBA0(chip, BA0_MIDSR) & BA0_MIDSR_TBF) == 0) {
1718 if (snd_rawmidi_transmit(substream, &byte, 1) != 1) {
1719 chip->midcr &= ~BA0_MIDCR_TIE;
1720 } else {
1721 snd_cs4281_pokeBA0(chip, BA0_MIDWP, byte);
1722 }
1723 }
1724 snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr);
1725 }
1726 } else {
1727 if (chip->midcr & BA0_MIDCR_TIE) {
1728 chip->midcr &= ~BA0_MIDCR_TIE;
1729 snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr);
1730 }
1731 }
1732 spin_unlock_irqrestore(&chip->reg_lock, flags);
1733}
1734
1735static const struct snd_rawmidi_ops snd_cs4281_midi_output =
1736{
1737 .open = snd_cs4281_midi_output_open,
1738 .close = snd_cs4281_midi_output_close,
1739 .trigger = snd_cs4281_midi_output_trigger,
1740};
1741
1742static const struct snd_rawmidi_ops snd_cs4281_midi_input =
1743{
1744 .open = snd_cs4281_midi_input_open,
1745 .close = snd_cs4281_midi_input_close,
1746 .trigger = snd_cs4281_midi_input_trigger,
1747};
1748
1749static int snd_cs4281_midi(struct cs4281 *chip, int device)
1750{
1751 struct snd_rawmidi *rmidi;
1752 int err;
1753
1754 if ((err = snd_rawmidi_new(chip->card, "CS4281", device, 1, 1, &rmidi)) < 0)
1755 return err;
1756 strcpy(rmidi->name, "CS4281");
1757 snd_rawmidi_set_ops(rmidi, SNDRV_RAWMIDI_STREAM_OUTPUT, &snd_cs4281_midi_output);
1758 snd_rawmidi_set_ops(rmidi, SNDRV_RAWMIDI_STREAM_INPUT, &snd_cs4281_midi_input);
1759 rmidi->info_flags |= SNDRV_RAWMIDI_INFO_OUTPUT | SNDRV_RAWMIDI_INFO_INPUT | SNDRV_RAWMIDI_INFO_DUPLEX;
1760 rmidi->private_data = chip;
1761 chip->rmidi = rmidi;
1762 return 0;
1763}
1764
1765/*
1766 * Interrupt handler
1767 */
1768
1769static irqreturn_t snd_cs4281_interrupt(int irq, void *dev_id)
1770{
1771 struct cs4281 *chip = dev_id;
1772 unsigned int status, dma, val;
1773 struct cs4281_dma *cdma;
1774
1775 if (chip == NULL)
1776 return IRQ_NONE;
1777 status = snd_cs4281_peekBA0(chip, BA0_HISR);
1778 if ((status & 0x7fffffff) == 0) {
1779 snd_cs4281_pokeBA0(chip, BA0_HICR, BA0_HICR_EOI);
1780 return IRQ_NONE;
1781 }
1782
1783 if (status & (BA0_HISR_DMA(0)|BA0_HISR_DMA(1)|BA0_HISR_DMA(2)|BA0_HISR_DMA(3))) {
1784 for (dma = 0; dma < 4; dma++)
1785 if (status & BA0_HISR_DMA(dma)) {
1786 cdma = &chip->dma[dma];
1787 spin_lock(&chip->reg_lock);
1788 /* ack DMA IRQ */
1789 val = snd_cs4281_peekBA0(chip, cdma->regHDSR);
1790 /* workaround, sometimes CS4281 acknowledges */
1791 /* end or middle transfer position twice */
1792 cdma->frag++;
1793 if ((val & BA0_HDSR_DHTC) && !(cdma->frag & 1)) {
1794 cdma->frag--;
1795 chip->spurious_dhtc_irq++;
1796 spin_unlock(&chip->reg_lock);
1797 continue;
1798 }
1799 if ((val & BA0_HDSR_DTC) && (cdma->frag & 1)) {
1800 cdma->frag--;
1801 chip->spurious_dtc_irq++;
1802 spin_unlock(&chip->reg_lock);
1803 continue;
1804 }
1805 spin_unlock(&chip->reg_lock);
1806 snd_pcm_period_elapsed(cdma->substream);
1807 }
1808 }
1809
1810 if ((status & BA0_HISR_MIDI) && chip->rmidi) {
1811 unsigned char c;
1812
1813 spin_lock(&chip->reg_lock);
1814 while ((snd_cs4281_peekBA0(chip, BA0_MIDSR) & BA0_MIDSR_RBE) == 0) {
1815 c = snd_cs4281_peekBA0(chip, BA0_MIDRP);
1816 if ((chip->midcr & BA0_MIDCR_RIE) == 0)
1817 continue;
1818 snd_rawmidi_receive(chip->midi_input, &c, 1);
1819 }
1820 while ((snd_cs4281_peekBA0(chip, BA0_MIDSR) & BA0_MIDSR_TBF) == 0) {
1821 if ((chip->midcr & BA0_MIDCR_TIE) == 0)
1822 break;
1823 if (snd_rawmidi_transmit(chip->midi_output, &c, 1) != 1) {
1824 chip->midcr &= ~BA0_MIDCR_TIE;
1825 snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr);
1826 break;
1827 }
1828 snd_cs4281_pokeBA0(chip, BA0_MIDWP, c);
1829 }
1830 spin_unlock(&chip->reg_lock);
1831 }
1832
1833 /* EOI to the PCI part... reenables interrupts */
1834 snd_cs4281_pokeBA0(chip, BA0_HICR, BA0_HICR_EOI);
1835
1836 return IRQ_HANDLED;
1837}
1838
1839
1840/*
1841 * OPL3 command
1842 */
1843static void snd_cs4281_opl3_command(struct snd_opl3 *opl3, unsigned short cmd,
1844 unsigned char val)
1845{
1846 unsigned long flags;
1847 struct cs4281 *chip = opl3->private_data;
1848 void __iomem *port;
1849
1850 if (cmd & OPL3_RIGHT)
1851 port = chip->ba0 + BA0_B1AP; /* right port */
1852 else
1853 port = chip->ba0 + BA0_B0AP; /* left port */
1854
1855 spin_lock_irqsave(&opl3->reg_lock, flags);
1856
1857 writel((unsigned int)cmd, port);
1858 udelay(10);
1859
1860 writel((unsigned int)val, port + 4);
1861 udelay(30);
1862
1863 spin_unlock_irqrestore(&opl3->reg_lock, flags);
1864}
1865
1866static int snd_cs4281_probe(struct pci_dev *pci,
1867 const struct pci_device_id *pci_id)
1868{
1869 static int dev;
1870 struct snd_card *card;
1871 struct cs4281 *chip;
1872 struct snd_opl3 *opl3;
1873 int err;
1874
1875 if (dev >= SNDRV_CARDS)
1876 return -ENODEV;
1877 if (!enable[dev]) {
1878 dev++;
1879 return -ENOENT;
1880 }
1881
1882 err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE,
1883 0, &card);
1884 if (err < 0)
1885 return err;
1886
1887 if ((err = snd_cs4281_create(card, pci, &chip, dual_codec[dev])) < 0) {
1888 snd_card_free(card);
1889 return err;
1890 }
1891 card->private_data = chip;
1892
1893 if ((err = snd_cs4281_mixer(chip)) < 0) {
1894 snd_card_free(card);
1895 return err;
1896 }
1897 if ((err = snd_cs4281_pcm(chip, 0)) < 0) {
1898 snd_card_free(card);
1899 return err;
1900 }
1901 if ((err = snd_cs4281_midi(chip, 0)) < 0) {
1902 snd_card_free(card);
1903 return err;
1904 }
1905 if ((err = snd_opl3_new(card, OPL3_HW_OPL3_CS4281, &opl3)) < 0) {
1906 snd_card_free(card);
1907 return err;
1908 }
1909 opl3->private_data = chip;
1910 opl3->command = snd_cs4281_opl3_command;
1911 snd_opl3_init(opl3);
1912 if ((err = snd_opl3_hwdep_new(opl3, 0, 1, NULL)) < 0) {
1913 snd_card_free(card);
1914 return err;
1915 }
1916 snd_cs4281_create_gameport(chip);
1917 strcpy(card->driver, "CS4281");
1918 strcpy(card->shortname, "Cirrus Logic CS4281");
1919 sprintf(card->longname, "%s at 0x%lx, irq %d",
1920 card->shortname,
1921 chip->ba0_addr,
1922 chip->irq);
1923
1924 if ((err = snd_card_register(card)) < 0) {
1925 snd_card_free(card);
1926 return err;
1927 }
1928
1929 pci_set_drvdata(pci, card);
1930 dev++;
1931 return 0;
1932}
1933
1934static void snd_cs4281_remove(struct pci_dev *pci)
1935{
1936 snd_card_free(pci_get_drvdata(pci));
1937}
1938
1939/*
1940 * Power Management
1941 */
1942#ifdef CONFIG_PM_SLEEP
1943
1944static const int saved_regs[SUSPEND_REGISTERS] = {
1945 BA0_JSCTL,
1946 BA0_GPIOR,
1947 BA0_SSCR,
1948 BA0_MIDCR,
1949 BA0_SRCSA,
1950 BA0_PASR,
1951 BA0_CASR,
1952 BA0_DACSR,
1953 BA0_ADCSR,
1954 BA0_FMLVC,
1955 BA0_FMRVC,
1956 BA0_PPLVC,
1957 BA0_PPRVC,
1958};
1959
1960#define CLKCR1_CKRA 0x00010000L
1961
1962static int cs4281_suspend(struct device *dev)
1963{
1964 struct snd_card *card = dev_get_drvdata(dev);
1965 struct cs4281 *chip = card->private_data;
1966 u32 ulCLK;
1967 unsigned int i;
1968
1969 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
1970 snd_ac97_suspend(chip->ac97);
1971 snd_ac97_suspend(chip->ac97_secondary);
1972
1973 ulCLK = snd_cs4281_peekBA0(chip, BA0_CLKCR1);
1974 ulCLK |= CLKCR1_CKRA;
1975 snd_cs4281_pokeBA0(chip, BA0_CLKCR1, ulCLK);
1976
1977 /* Disable interrupts. */
1978 snd_cs4281_pokeBA0(chip, BA0_HICR, BA0_HICR_CHGM);
1979
1980 /* remember the status registers */
1981 for (i = 0; i < ARRAY_SIZE(saved_regs); i++)
1982 if (saved_regs[i])
1983 chip->suspend_regs[i] = snd_cs4281_peekBA0(chip, saved_regs[i]);
1984
1985 /* Turn off the serial ports. */
1986 snd_cs4281_pokeBA0(chip, BA0_SERMC, 0);
1987
1988 /* Power off FM, Joystick, AC link, */
1989 snd_cs4281_pokeBA0(chip, BA0_SSPM, 0);
1990
1991 /* DLL off. */
1992 snd_cs4281_pokeBA0(chip, BA0_CLKCR1, 0);
1993
1994 /* AC link off. */
1995 snd_cs4281_pokeBA0(chip, BA0_SPMC, 0);
1996
1997 ulCLK = snd_cs4281_peekBA0(chip, BA0_CLKCR1);
1998 ulCLK &= ~CLKCR1_CKRA;
1999 snd_cs4281_pokeBA0(chip, BA0_CLKCR1, ulCLK);
2000 return 0;
2001}
2002
2003static int cs4281_resume(struct device *dev)
2004{
2005 struct snd_card *card = dev_get_drvdata(dev);
2006 struct cs4281 *chip = card->private_data;
2007 unsigned int i;
2008 u32 ulCLK;
2009
2010 ulCLK = snd_cs4281_peekBA0(chip, BA0_CLKCR1);
2011 ulCLK |= CLKCR1_CKRA;
2012 snd_cs4281_pokeBA0(chip, BA0_CLKCR1, ulCLK);
2013
2014 snd_cs4281_chip_init(chip);
2015
2016 /* restore the status registers */
2017 for (i = 0; i < ARRAY_SIZE(saved_regs); i++)
2018 if (saved_regs[i])
2019 snd_cs4281_pokeBA0(chip, saved_regs[i], chip->suspend_regs[i]);
2020
2021 snd_ac97_resume(chip->ac97);
2022 snd_ac97_resume(chip->ac97_secondary);
2023
2024 ulCLK = snd_cs4281_peekBA0(chip, BA0_CLKCR1);
2025 ulCLK &= ~CLKCR1_CKRA;
2026 snd_cs4281_pokeBA0(chip, BA0_CLKCR1, ulCLK);
2027
2028 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
2029 return 0;
2030}
2031
2032static SIMPLE_DEV_PM_OPS(cs4281_pm, cs4281_suspend, cs4281_resume);
2033#define CS4281_PM_OPS &cs4281_pm
2034#else
2035#define CS4281_PM_OPS NULL
2036#endif /* CONFIG_PM_SLEEP */
2037
2038static struct pci_driver cs4281_driver = {
2039 .name = KBUILD_MODNAME,
2040 .id_table = snd_cs4281_ids,
2041 .probe = snd_cs4281_probe,
2042 .remove = snd_cs4281_remove,
2043 .driver = {
2044 .pm = CS4281_PM_OPS,
2045 },
2046};
2047
2048module_pci_driver(cs4281_driver);
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