source: GPL/trunk/alsa-kernel/pci/cs4281.c

Last change on this file was 777, checked in by David Azarewicz, 5 months ago

Merge from uniaud32-exp branch
File size: 63.5 KB
Line 
1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Driver for Cirrus Logic CS4281 based PCI soundcard
4 * Copyright (c) by Jaroslav Kysela <perex@perex.cz>,
5 */
6
7#include <linux/io.h>
8#include <linux/delay.h>
9#include <linux/interrupt.h>
10#include <linux/init.h>
11#include <linux/pci.h>
12#include <linux/slab.h>
13#include <linux/gameport.h>
14#include <linux/module.h>
15#include <sound/core.h>
16#include <sound/control.h>
17#include <sound/pcm.h>
18#include <sound/rawmidi.h>
19#include <sound/ac97_codec.h>
20#include <sound/tlv.h>
21#include <sound/opl3.h>
22#include <sound/initval.h>
23
24
25#ifdef TARGET_OS2
26#define KBUILD_MODNAME "cs4281"
27#endif
28MODULE_AUTHOR("Jaroslav Kysela <perex@perex.cz>");
29MODULE_DESCRIPTION("Cirrus Logic CS4281");
30MODULE_LICENSE("GPL");
31
32static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
33static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
34static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable switches */
35static bool dual_codec[SNDRV_CARDS]; /* dual codec */
36
37module_param_array(index, int, NULL, 0444);
38MODULE_PARM_DESC(index, "Index value for CS4281 soundcard.");
39module_param_array(id, charp, NULL, 0444);
40MODULE_PARM_DESC(id, "ID string for CS4281 soundcard.");
41module_param_array(enable, bool, NULL, 0444);
42MODULE_PARM_DESC(enable, "Enable CS4281 soundcard.");
43module_param_array(dual_codec, bool, NULL, 0444);
44MODULE_PARM_DESC(dual_codec, "Secondary Codec ID (0 = disabled).");
45
46/*
47 * Direct registers
48 */
49
50#define CS4281_BA0_SIZE 0x1000
51#define CS4281_BA1_SIZE 0x10000
52
53/*
54 * BA0 registers
55 */
56#define BA0_HISR 0x0000 /* Host Interrupt Status Register */
57#define BA0_HISR_INTENA (1<<31) /* Internal Interrupt Enable Bit */
58#define BA0_HISR_MIDI (1<<22) /* MIDI port interrupt */
59#define BA0_HISR_FIFOI (1<<20) /* FIFO polled interrupt */
60#define BA0_HISR_DMAI (1<<18) /* DMA interrupt (half or end) */
61#define BA0_HISR_FIFO(c) (1<<(12+(c))) /* FIFO channel interrupt */
62#define BA0_HISR_DMA(c) (1<<(8+(c))) /* DMA channel interrupt */
63#define BA0_HISR_GPPI (1<<5) /* General Purpose Input (Primary chip) */
64#define BA0_HISR_GPSI (1<<4) /* General Purpose Input (Secondary chip) */
65#define BA0_HISR_GP3I (1<<3) /* GPIO3 pin Interrupt */
66#define BA0_HISR_GP1I (1<<2) /* GPIO1 pin Interrupt */
67#define BA0_HISR_VUPI (1<<1) /* VOLUP pin Interrupt */
68#define BA0_HISR_VDNI (1<<0) /* VOLDN pin Interrupt */
69
70#define BA0_HICR 0x0008 /* Host Interrupt Control Register */
71#define BA0_HICR_CHGM (1<<1) /* INTENA Change Mask */
72#define BA0_HICR_IEV (1<<0) /* INTENA Value */
73#define BA0_HICR_EOI (3<<0) /* End of Interrupt command */
74
75#define BA0_HIMR 0x000c /* Host Interrupt Mask Register */
76 /* Use same contants as for BA0_HISR */
77
78#define BA0_IIER 0x0010 /* ISA Interrupt Enable Register */
79
80#define BA0_HDSR0 0x00f0 /* Host DMA Engine 0 Status Register */
81#define BA0_HDSR1 0x00f4 /* Host DMA Engine 1 Status Register */
82#define BA0_HDSR2 0x00f8 /* Host DMA Engine 2 Status Register */
83#define BA0_HDSR3 0x00fc /* Host DMA Engine 3 Status Register */
84
85#define BA0_HDSR_CH1P (1<<25) /* Channel 1 Pending */
86#define BA0_HDSR_CH2P (1<<24) /* Channel 2 Pending */
87#define BA0_HDSR_DHTC (1<<17) /* DMA Half Terminal Count */
88#define BA0_HDSR_DTC (1<<16) /* DMA Terminal Count */
89#define BA0_HDSR_DRUN (1<<15) /* DMA Running */
90#define BA0_HDSR_RQ (1<<7) /* Pending Request */
91
92#define BA0_DCA0 0x0110 /* Host DMA Engine 0 Current Address */
93#define BA0_DCC0 0x0114 /* Host DMA Engine 0 Current Count */
94#define BA0_DBA0 0x0118 /* Host DMA Engine 0 Base Address */
95#define BA0_DBC0 0x011c /* Host DMA Engine 0 Base Count */
96#define BA0_DCA1 0x0120 /* Host DMA Engine 1 Current Address */
97#define BA0_DCC1 0x0124 /* Host DMA Engine 1 Current Count */
98#define BA0_DBA1 0x0128 /* Host DMA Engine 1 Base Address */
99#define BA0_DBC1 0x012c /* Host DMA Engine 1 Base Count */
100#define BA0_DCA2 0x0130 /* Host DMA Engine 2 Current Address */
101#define BA0_DCC2 0x0134 /* Host DMA Engine 2 Current Count */
102#define BA0_DBA2 0x0138 /* Host DMA Engine 2 Base Address */
103#define BA0_DBC2 0x013c /* Host DMA Engine 2 Base Count */
104#define BA0_DCA3 0x0140 /* Host DMA Engine 3 Current Address */
105#define BA0_DCC3 0x0144 /* Host DMA Engine 3 Current Count */
106#define BA0_DBA3 0x0148 /* Host DMA Engine 3 Base Address */
107#define BA0_DBC3 0x014c /* Host DMA Engine 3 Base Count */
108#define BA0_DMR0 0x0150 /* Host DMA Engine 0 Mode */
109#define BA0_DCR0 0x0154 /* Host DMA Engine 0 Command */
110#define BA0_DMR1 0x0158 /* Host DMA Engine 1 Mode */
111#define BA0_DCR1 0x015c /* Host DMA Engine 1 Command */
112#define BA0_DMR2 0x0160 /* Host DMA Engine 2 Mode */
113#define BA0_DCR2 0x0164 /* Host DMA Engine 2 Command */
114#define BA0_DMR3 0x0168 /* Host DMA Engine 3 Mode */
115#define BA0_DCR3 0x016c /* Host DMA Engine 3 Command */
116
117#define BA0_DMR_DMA (1<<29) /* Enable DMA mode */
118#define BA0_DMR_POLL (1<<28) /* Enable poll mode */
119#define BA0_DMR_TBC (1<<25) /* Transfer By Channel */
120#define BA0_DMR_CBC (1<<24) /* Count By Channel (0 = frame resolution) */
121#define BA0_DMR_SWAPC (1<<22) /* Swap Left/Right Channels */
122#define BA0_DMR_SIZE20 (1<<20) /* Sample is 20-bit */
123#define BA0_DMR_USIGN (1<<19) /* Unsigned */
124#define BA0_DMR_BEND (1<<18) /* Big Endian */
125#define BA0_DMR_MONO (1<<17) /* Mono */
126#define BA0_DMR_SIZE8 (1<<16) /* Sample is 8-bit */
127#define BA0_DMR_TYPE_DEMAND (0<<6)
128#define BA0_DMR_TYPE_SINGLE (1<<6)
129#define BA0_DMR_TYPE_BLOCK (2<<6)
130#define BA0_DMR_TYPE_CASCADE (3<<6) /* Not supported */
131#define BA0_DMR_DEC (1<<5) /* Access Increment (0) or Decrement (1) */
132#define BA0_DMR_AUTO (1<<4) /* Auto-Initialize */
133#define BA0_DMR_TR_VERIFY (0<<2) /* Verify Transfer */
134#define BA0_DMR_TR_WRITE (1<<2) /* Write Transfer */
135#define BA0_DMR_TR_READ (2<<2) /* Read Transfer */
136
137#define BA0_DCR_HTCIE (1<<17) /* Half Terminal Count Interrupt */
138#define BA0_DCR_TCIE (1<<16) /* Terminal Count Interrupt */
139#define BA0_DCR_MSK (1<<0) /* DMA Mask bit */
140
141#define BA0_FCR0 0x0180 /* FIFO Control 0 */
142#define BA0_FCR1 0x0184 /* FIFO Control 1 */
143#define BA0_FCR2 0x0188 /* FIFO Control 2 */
144#define BA0_FCR3 0x018c /* FIFO Control 3 */
145
146#define BA0_FCR_FEN (1<<31) /* FIFO Enable bit */
147#define BA0_FCR_DACZ (1<<30) /* DAC Zero */
148#define BA0_FCR_PSH (1<<29) /* Previous Sample Hold */
149#define BA0_FCR_RS(x) (((x)&0x1f)<<24) /* Right Slot Mapping */
150#define BA0_FCR_LS(x) (((x)&0x1f)<<16) /* Left Slot Mapping */
151#define BA0_FCR_SZ(x) (((x)&0x7f)<<8) /* FIFO buffer size (in samples) */
152#define BA0_FCR_OF(x) (((x)&0x7f)<<0) /* FIFO starting offset (in samples) */
153
154#define BA0_FPDR0 0x0190 /* FIFO Polled Data 0 */
155#define BA0_FPDR1 0x0194 /* FIFO Polled Data 1 */
156#define BA0_FPDR2 0x0198 /* FIFO Polled Data 2 */
157#define BA0_FPDR3 0x019c /* FIFO Polled Data 3 */
158
159#define BA0_FCHS 0x020c /* FIFO Channel Status */
160#define BA0_FCHS_RCO(x) (1<<(7+(((x)&3)<<3))) /* Right Channel Out */
161#define BA0_FCHS_LCO(x) (1<<(6+(((x)&3)<<3))) /* Left Channel Out */
162#define BA0_FCHS_MRP(x) (1<<(5+(((x)&3)<<3))) /* Move Read Pointer */
163#define BA0_FCHS_FE(x) (1<<(4+(((x)&3)<<3))) /* FIFO Empty */
164#define BA0_FCHS_FF(x) (1<<(3+(((x)&3)<<3))) /* FIFO Full */
165#define BA0_FCHS_IOR(x) (1<<(2+(((x)&3)<<3))) /* Internal Overrun Flag */
166#define BA0_FCHS_RCI(x) (1<<(1+(((x)&3)<<3))) /* Right Channel In */
167#define BA0_FCHS_LCI(x) (1<<(0+(((x)&3)<<3))) /* Left Channel In */
168
169#define BA0_FSIC0 0x0210 /* FIFO Status and Interrupt Control 0 */
170#define BA0_FSIC1 0x0214 /* FIFO Status and Interrupt Control 1 */
171#define BA0_FSIC2 0x0218 /* FIFO Status and Interrupt Control 2 */
172#define BA0_FSIC3 0x021c /* FIFO Status and Interrupt Control 3 */
173
174#define BA0_FSIC_FIC(x) (((x)&0x7f)<<24) /* FIFO Interrupt Count */
175#define BA0_FSIC_FORIE (1<<23) /* FIFO OverRun Interrupt Enable */
176#define BA0_FSIC_FURIE (1<<22) /* FIFO UnderRun Interrupt Enable */
177#define BA0_FSIC_FSCIE (1<<16) /* FIFO Sample Count Interrupt Enable */
178#define BA0_FSIC_FSC(x) (((x)&0x7f)<<8) /* FIFO Sample Count */
179#define BA0_FSIC_FOR (1<<7) /* FIFO OverRun */
180#define BA0_FSIC_FUR (1<<6) /* FIFO UnderRun */
181#define BA0_FSIC_FSCR (1<<0) /* FIFO Sample Count Reached */
182
183#define BA0_PMCS 0x0344 /* Power Management Control/Status */
184#define BA0_CWPR 0x03e0 /* Configuration Write Protect */
185
186#define BA0_EPPMC 0x03e4 /* Extended PCI Power Management Control */
187#define BA0_EPPMC_FPDN (1<<14) /* Full Power DowN */
188
189#define BA0_GPIOR 0x03e8 /* GPIO Pin Interface Register */
190
191#define BA0_SPMC 0x03ec /* Serial Port Power Management Control (& ASDIN2 enable) */
192#define BA0_SPMC_GIPPEN (1<<15) /* GP INT Primary PME# Enable */
193#define BA0_SPMC_GISPEN (1<<14) /* GP INT Secondary PME# Enable */
194#define BA0_SPMC_EESPD (1<<9) /* EEPROM Serial Port Disable */
195#define BA0_SPMC_ASDI2E (1<<8) /* ASDIN2 Enable */
196#define BA0_SPMC_ASDO (1<<7) /* Asynchronous ASDOUT Assertion */
197#define BA0_SPMC_WUP2 (1<<3) /* Wakeup for Secondary Input */
198#define BA0_SPMC_WUP1 (1<<2) /* Wakeup for Primary Input */
199#define BA0_SPMC_ASYNC (1<<1) /* Asynchronous ASYNC Assertion */
200#define BA0_SPMC_RSTN (1<<0) /* Reset Not! */
201
202#define BA0_CFLR 0x03f0 /* Configuration Load Register (EEPROM or BIOS) */
203#define BA0_CFLR_DEFAULT 0x00000001 /* CFLR must be in AC97 link mode */
204#define BA0_IISR 0x03f4 /* ISA Interrupt Select */
205#define BA0_TMS 0x03f8 /* Test Register */
206#define BA0_SSVID 0x03fc /* Subsystem ID register */
207
208#define BA0_CLKCR1 0x0400 /* Clock Control Register 1 */
209#define BA0_CLKCR1_CLKON (1<<25) /* Read Only */
210#define BA0_CLKCR1_DLLRDY (1<<24) /* DLL Ready */
211#define BA0_CLKCR1_DLLOS (1<<6) /* DLL Output Select */
212#define BA0_CLKCR1_SWCE (1<<5) /* Clock Enable */
213#define BA0_CLKCR1_DLLP (1<<4) /* DLL PowerUp */
214#define BA0_CLKCR1_DLLSS (((x)&3)<<3) /* DLL Source Select */
215
216#define BA0_FRR 0x0410 /* Feature Reporting Register */
217#define BA0_SLT12O 0x041c /* Slot 12 GPIO Output Register for AC-Link */
218
219#define BA0_SERMC 0x0420 /* Serial Port Master Control */
220#define BA0_SERMC_FCRN (1<<27) /* Force Codec Ready Not */
221#define BA0_SERMC_ODSEN2 (1<<25) /* On-Demand Support Enable ASDIN2 */
222#define BA0_SERMC_ODSEN1 (1<<24) /* On-Demand Support Enable ASDIN1 */
223#define BA0_SERMC_SXLB (1<<21) /* ASDIN2 to ASDOUT Loopback */
224#define BA0_SERMC_SLB (1<<20) /* ASDOUT to ASDIN2 Loopback */
225#define BA0_SERMC_LOVF (1<<19) /* Loopback Output Valid Frame bit */
226#define BA0_SERMC_TCID(x) (((x)&3)<<16) /* Target Secondary Codec ID */
227#define BA0_SERMC_PXLB (5<<1) /* Primary Port External Loopback */
228#define BA0_SERMC_PLB (4<<1) /* Primary Port Internal Loopback */
229#define BA0_SERMC_PTC (7<<1) /* Port Timing Configuration */
230#define BA0_SERMC_PTC_AC97 (1<<1) /* AC97 mode */
231#define BA0_SERMC_MSPE (1<<0) /* Master Serial Port Enable */
232
233#define BA0_SERC1 0x0428 /* Serial Port Configuration 1 */
234#define BA0_SERC1_SO1F(x) (((x)&7)>>1) /* Primary Output Port Format */
235#define BA0_SERC1_AC97 (1<<1)
236#define BA0_SERC1_SO1EN (1<<0) /* Primary Output Port Enable */
237
238#define BA0_SERC2 0x042c /* Serial Port Configuration 2 */
239#define BA0_SERC2_SI1F(x) (((x)&7)>>1) /* Primary Input Port Format */
240#define BA0_SERC2_AC97 (1<<1)
241#define BA0_SERC2_SI1EN (1<<0) /* Primary Input Port Enable */
242
243#define BA0_SLT12M 0x045c /* Slot 12 Monitor Register for Primary AC-Link */
244
245#define BA0_ACCTL 0x0460 /* AC'97 Control */
246#define BA0_ACCTL_TC (1<<6) /* Target Codec */
247#define BA0_ACCTL_CRW (1<<4) /* 0=Write, 1=Read Command */
248#define BA0_ACCTL_DCV (1<<3) /* Dynamic Command Valid */
249#define BA0_ACCTL_VFRM (1<<2) /* Valid Frame */
250#define BA0_ACCTL_ESYN (1<<1) /* Enable Sync */
251
252#define BA0_ACSTS 0x0464 /* AC'97 Status */
253#define BA0_ACSTS_VSTS (1<<1) /* Valid Status */
254#define BA0_ACSTS_CRDY (1<<0) /* Codec Ready */
255
256#define BA0_ACOSV 0x0468 /* AC'97 Output Slot Valid */
257#define BA0_ACOSV_SLV(x) (1<<((x)-3))
258
259#define BA0_ACCAD 0x046c /* AC'97 Command Address */
260#define BA0_ACCDA 0x0470 /* AC'97 Command Data */
261
262#define BA0_ACISV 0x0474 /* AC'97 Input Slot Valid */
263#define BA0_ACISV_SLV(x) (1<<((x)-3))
264
265#define BA0_ACSAD 0x0478 /* AC'97 Status Address */
266#define BA0_ACSDA 0x047c /* AC'97 Status Data */
267#define BA0_JSPT 0x0480 /* Joystick poll/trigger */
268#define BA0_JSCTL 0x0484 /* Joystick control */
269#define BA0_JSC1 0x0488 /* Joystick control */
270#define BA0_JSC2 0x048c /* Joystick control */
271#define BA0_JSIO 0x04a0
272
273#define BA0_MIDCR 0x0490 /* MIDI Control */
274#define BA0_MIDCR_MRST (1<<5) /* Reset MIDI Interface */
275#define BA0_MIDCR_MLB (1<<4) /* MIDI Loop Back Enable */
276#define BA0_MIDCR_TIE (1<<3) /* MIDI Transmuit Interrupt Enable */
277#define BA0_MIDCR_RIE (1<<2) /* MIDI Receive Interrupt Enable */
278#define BA0_MIDCR_RXE (1<<1) /* MIDI Receive Enable */
279#define BA0_MIDCR_TXE (1<<0) /* MIDI Transmit Enable */
280
281#define BA0_MIDCMD 0x0494 /* MIDI Command (wo) */
282
283#define BA0_MIDSR 0x0494 /* MIDI Status (ro) */
284#define BA0_MIDSR_RDA (1<<15) /* Sticky bit (RBE 1->0) */
285#define BA0_MIDSR_TBE (1<<14) /* Sticky bit (TBF 0->1) */
286#define BA0_MIDSR_RBE (1<<7) /* Receive Buffer Empty */
287#define BA0_MIDSR_TBF (1<<6) /* Transmit Buffer Full */
288
289#define BA0_MIDWP 0x0498 /* MIDI Write */
290#define BA0_MIDRP 0x049c /* MIDI Read (ro) */
291
292#define BA0_AODSD1 0x04a8 /* AC'97 On-Demand Slot Disable for primary link (ro) */
293#define BA0_AODSD1_NDS(x) (1<<((x)-3))
294
295#define BA0_AODSD2 0x04ac /* AC'97 On-Demand Slot Disable for secondary link (ro) */
296#define BA0_AODSD2_NDS(x) (1<<((x)-3))
297
298#define BA0_CFGI 0x04b0 /* Configure Interface (EEPROM interface) */
299#define BA0_SLT12M2 0x04dc /* Slot 12 Monitor Register 2 for secondary AC-link */
300#define BA0_ACSTS2 0x04e4 /* AC'97 Status Register 2 */
301#define BA0_ACISV2 0x04f4 /* AC'97 Input Slot Valid Register 2 */
302#define BA0_ACSAD2 0x04f8 /* AC'97 Status Address Register 2 */
303#define BA0_ACSDA2 0x04fc /* AC'97 Status Data Register 2 */
304#define BA0_FMSR 0x0730 /* FM Synthesis Status (ro) */
305#define BA0_B0AP 0x0730 /* FM Bank 0 Address Port (wo) */
306#define BA0_FMDP 0x0734 /* FM Data Port */
307#define BA0_B1AP 0x0738 /* FM Bank 1 Address Port */
308#define BA0_B1DP 0x073c /* FM Bank 1 Data Port */
309
310#define BA0_SSPM 0x0740 /* Sound System Power Management */
311#define BA0_SSPM_MIXEN (1<<6) /* Playback SRC + FM/Wavetable MIX */
312#define BA0_SSPM_CSRCEN (1<<5) /* Capture Sample Rate Converter Enable */
313#define BA0_SSPM_PSRCEN (1<<4) /* Playback Sample Rate Converter Enable */
314#define BA0_SSPM_JSEN (1<<3) /* Joystick Enable */
315#define BA0_SSPM_ACLEN (1<<2) /* Serial Port Engine and AC-Link Enable */
316#define BA0_SSPM_FMEN (1<<1) /* FM Synthesis Block Enable */
317
318#define BA0_DACSR 0x0744 /* DAC Sample Rate - Playback SRC */
319#define BA0_ADCSR 0x0748 /* ADC Sample Rate - Capture SRC */
320
321#define BA0_SSCR 0x074c /* Sound System Control Register */
322#define BA0_SSCR_HVS1 (1<<23) /* Hardwave Volume Step (0=1,1=2) */
323#define BA0_SSCR_MVCS (1<<19) /* Master Volume Codec Select */
324#define BA0_SSCR_MVLD (1<<18) /* Master Volume Line Out Disable */
325#define BA0_SSCR_MVAD (1<<17) /* Master Volume Alternate Out Disable */
326#define BA0_SSCR_MVMD (1<<16) /* Master Volume Mono Out Disable */
327#define BA0_SSCR_XLPSRC (1<<8) /* External SRC Loopback Mode */
328#define BA0_SSCR_LPSRC (1<<7) /* SRC Loopback Mode */
329#define BA0_SSCR_CDTX (1<<5) /* CD Transfer Data */
330#define BA0_SSCR_HVC (1<<3) /* Harware Volume Control Enable */
331
332#define BA0_FMLVC 0x0754 /* FM Synthesis Left Volume Control */
333#define BA0_FMRVC 0x0758 /* FM Synthesis Right Volume Control */
334#define BA0_SRCSA 0x075c /* SRC Slot Assignments */
335#define BA0_PPLVC 0x0760 /* PCM Playback Left Volume Control */
336#define BA0_PPRVC 0x0764 /* PCM Playback Right Volume Control */
337#define BA0_PASR 0x0768 /* playback sample rate */
338#define BA0_CASR 0x076C /* capture sample rate */
339
340/* Source Slot Numbers - Playback */
341#define SRCSLOT_LEFT_PCM_PLAYBACK 0
342#define SRCSLOT_RIGHT_PCM_PLAYBACK 1
343#define SRCSLOT_PHONE_LINE_1_DAC 2
344#define SRCSLOT_CENTER_PCM_PLAYBACK 3
345#define SRCSLOT_LEFT_SURROUND_PCM_PLAYBACK 4
346#define SRCSLOT_RIGHT_SURROUND_PCM_PLAYBACK 5
347#define SRCSLOT_LFE_PCM_PLAYBACK 6
348#define SRCSLOT_PHONE_LINE_2_DAC 7
349#define SRCSLOT_HEADSET_DAC 8
350#define SRCSLOT_LEFT_WT 29 /* invalid for BA0_SRCSA */
351#define SRCSLOT_RIGHT_WT 30 /* invalid for BA0_SRCSA */
352
353/* Source Slot Numbers - Capture */
354#define SRCSLOT_LEFT_PCM_RECORD 10
355#define SRCSLOT_RIGHT_PCM_RECORD 11
356#define SRCSLOT_PHONE_LINE_1_ADC 12
357#define SRCSLOT_MIC_ADC 13
358#define SRCSLOT_PHONE_LINE_2_ADC 17
359#define SRCSLOT_HEADSET_ADC 18
360#define SRCSLOT_SECONDARY_LEFT_PCM_RECORD 20
361#define SRCSLOT_SECONDARY_RIGHT_PCM_RECORD 21
362#define SRCSLOT_SECONDARY_PHONE_LINE_1_ADC 22
363#define SRCSLOT_SECONDARY_MIC_ADC 23
364#define SRCSLOT_SECONDARY_PHONE_LINE_2_ADC 27
365#define SRCSLOT_SECONDARY_HEADSET_ADC 28
366
367/* Source Slot Numbers - Others */
368#define SRCSLOT_POWER_DOWN 31
369
370/* MIDI modes */
371#define CS4281_MODE_OUTPUT (1<<0)
372#define CS4281_MODE_INPUT (1<<1)
373
374/* joystick bits */
375/* Bits for JSPT */
376#define JSPT_CAX 0x00000001
377#define JSPT_CAY 0x00000002
378#define JSPT_CBX 0x00000004
379#define JSPT_CBY 0x00000008
380#define JSPT_BA1 0x00000010
381#define JSPT_BA2 0x00000020
382#define JSPT_BB1 0x00000040
383#define JSPT_BB2 0x00000080
384
385/* Bits for JSCTL */
386#define JSCTL_SP_MASK 0x00000003
387#define JSCTL_SP_SLOW 0x00000000
388#define JSCTL_SP_MEDIUM_SLOW 0x00000001
389#define JSCTL_SP_MEDIUM_FAST 0x00000002
390#define JSCTL_SP_FAST 0x00000003
391#define JSCTL_ARE 0x00000004
392
393/* Data register pairs masks */
394#define JSC1_Y1V_MASK 0x0000FFFF
395#define JSC1_X1V_MASK 0xFFFF0000
396#define JSC1_Y1V_SHIFT 0
397#define JSC1_X1V_SHIFT 16
398#define JSC2_Y2V_MASK 0x0000FFFF
399#define JSC2_X2V_MASK 0xFFFF0000
400#define JSC2_Y2V_SHIFT 0
401#define JSC2_X2V_SHIFT 16
402
403/* JS GPIO */
404#define JSIO_DAX 0x00000001
405#define JSIO_DAY 0x00000002
406#define JSIO_DBX 0x00000004
407#define JSIO_DBY 0x00000008
408#define JSIO_AXOE 0x00000010
409#define JSIO_AYOE 0x00000020
410#define JSIO_BXOE 0x00000040
411#define JSIO_BYOE 0x00000080
412
413/*
414 *
415 */
416
417struct cs4281_dma {
418 struct snd_pcm_substream *substream;
419 unsigned int regDBA; /* offset to DBA register */
420 unsigned int regDCA; /* offset to DCA register */
421 unsigned int regDBC; /* offset to DBC register */
422 unsigned int regDCC; /* offset to DCC register */
423 unsigned int regDMR; /* offset to DMR register */
424 unsigned int regDCR; /* offset to DCR register */
425 unsigned int regHDSR; /* offset to HDSR register */
426 unsigned int regFCR; /* offset to FCR register */
427 unsigned int regFSIC; /* offset to FSIC register */
428 unsigned int valDMR; /* DMA mode */
429 unsigned int valDCR; /* DMA command */
430 unsigned int valFCR; /* FIFO control */
431 unsigned int fifo_offset; /* FIFO offset within BA1 */
432 unsigned char left_slot; /* FIFO left slot */
433 unsigned char right_slot; /* FIFO right slot */
434 int frag; /* period number */
435};
436
437#define SUSPEND_REGISTERS 20
438
439struct cs4281 {
440 int irq;
441
442 void __iomem *ba0; /* virtual (accessible) address */
443 void __iomem *ba1; /* virtual (accessible) address */
444 unsigned long ba0_addr;
445 unsigned long ba1_addr;
446
447 int dual_codec;
448
449 struct snd_ac97_bus *ac97_bus;
450 struct snd_ac97 *ac97;
451 struct snd_ac97 *ac97_secondary;
452
453 struct pci_dev *pci;
454 struct snd_card *card;
455 struct snd_pcm *pcm;
456 struct snd_rawmidi *rmidi;
457 struct snd_rawmidi_substream *midi_input;
458 struct snd_rawmidi_substream *midi_output;
459
460 struct cs4281_dma dma[4];
461
462 unsigned char src_left_play_slot;
463 unsigned char src_right_play_slot;
464 unsigned char src_left_rec_slot;
465 unsigned char src_right_rec_slot;
466
467 unsigned int spurious_dhtc_irq;
468 unsigned int spurious_dtc_irq;
469
470 spinlock_t reg_lock;
471 unsigned int midcr;
472 unsigned int uartm;
473
474 struct gameport *gameport;
475
476 u32 suspend_regs[SUSPEND_REGISTERS];
477};
478
479static irqreturn_t snd_cs4281_interrupt(int irq, void *dev_id);
480
481static const struct pci_device_id snd_cs4281_ids[] = {
482 { PCI_VDEVICE(CIRRUS, 0x6005), 0, }, /* CS4281 */
483 { 0, }
484};
485
486MODULE_DEVICE_TABLE(pci, snd_cs4281_ids);
487
488/*
489 * constants
490 */
491
492#define CS4281_FIFO_SIZE 32
493
494/*
495 * common I/O routines
496 */
497
498static inline void snd_cs4281_pokeBA0(struct cs4281 *chip, unsigned long offset,
499 unsigned int val)
500{
501 writel(val, chip->ba0 + offset);
502}
503
504static inline unsigned int snd_cs4281_peekBA0(struct cs4281 *chip, unsigned long offset)
505{
506 return readl(chip->ba0 + offset);
507}
508
509static void snd_cs4281_ac97_write(struct snd_ac97 *ac97,
510 unsigned short reg, unsigned short val)
511{
512 /*
513 * 1. Write ACCAD = Command Address Register = 46Ch for AC97 register address
514 * 2. Write ACCDA = Command Data Register = 470h for data to write to AC97
515 * 3. Write ACCTL = Control Register = 460h for initiating the write
516 * 4. Read ACCTL = 460h, DCV should be reset by now and 460h = 07h
517 * 5. if DCV not cleared, break and return error
518 */
519 struct cs4281 *chip = ac97->private_data;
520 int count;
521
522 /*
523 * Setup the AC97 control registers on the CS461x to send the
524 * appropriate command to the AC97 to perform the read.
525 * ACCAD = Command Address Register = 46Ch
526 * ACCDA = Command Data Register = 470h
527 * ACCTL = Control Register = 460h
528 * set DCV - will clear when process completed
529 * reset CRW - Write command
530 * set VFRM - valid frame enabled
531 * set ESYN - ASYNC generation enabled
532 * set RSTN - ARST# inactive, AC97 codec not reset
533 */
534 snd_cs4281_pokeBA0(chip, BA0_ACCAD, reg);
535 snd_cs4281_pokeBA0(chip, BA0_ACCDA, val);
536 snd_cs4281_pokeBA0(chip, BA0_ACCTL, BA0_ACCTL_DCV | BA0_ACCTL_VFRM |
537 BA0_ACCTL_ESYN | (ac97->num ? BA0_ACCTL_TC : 0));
538 for (count = 0; count < 2000; count++) {
539 /*
540 * First, we want to wait for a short time.
541 */
542 udelay(10);
543 /*
544 * Now, check to see if the write has completed.
545 * ACCTL = 460h, DCV should be reset by now and 460h = 07h
546 */
547 if (!(snd_cs4281_peekBA0(chip, BA0_ACCTL) & BA0_ACCTL_DCV)) {
548 return;
549 }
550 }
551 dev_err(chip->card->dev,
552 "AC'97 write problem, reg = 0x%x, val = 0x%x\n", reg, val);
553}
554
555static unsigned short snd_cs4281_ac97_read(struct snd_ac97 *ac97,
556 unsigned short reg)
557{
558 struct cs4281 *chip = ac97->private_data;
559 int count;
560 unsigned short result;
561 // FIXME: volatile is necessary in the following due to a bug of
562 // some gcc versions
563 volatile int ac97_num = ((volatile struct snd_ac97 *)ac97)->num;
564
565 /*
566 * 1. Write ACCAD = Command Address Register = 46Ch for AC97 register address
567 * 2. Write ACCDA = Command Data Register = 470h for data to write to AC97
568 * 3. Write ACCTL = Control Register = 460h for initiating the write
569 * 4. Read ACCTL = 460h, DCV should be reset by now and 460h = 17h
570 * 5. if DCV not cleared, break and return error
571 * 6. Read ACSTS = Status Register = 464h, check VSTS bit
572 */
573
574 snd_cs4281_peekBA0(chip, ac97_num ? BA0_ACSDA2 : BA0_ACSDA);
575
576 /*
577 * Setup the AC97 control registers on the CS461x to send the
578 * appropriate command to the AC97 to perform the read.
579 * ACCAD = Command Address Register = 46Ch
580 * ACCDA = Command Data Register = 470h
581 * ACCTL = Control Register = 460h
582 * set DCV - will clear when process completed
583 * set CRW - Read command
584 * set VFRM - valid frame enabled
585 * set ESYN - ASYNC generation enabled
586 * set RSTN - ARST# inactive, AC97 codec not reset
587 */
588
589 snd_cs4281_pokeBA0(chip, BA0_ACCAD, reg);
590 snd_cs4281_pokeBA0(chip, BA0_ACCDA, 0);
591 snd_cs4281_pokeBA0(chip, BA0_ACCTL, BA0_ACCTL_DCV | BA0_ACCTL_CRW |
592 BA0_ACCTL_VFRM | BA0_ACCTL_ESYN |
593 (ac97_num ? BA0_ACCTL_TC : 0));
594
595
596 /*
597 * Wait for the read to occur.
598 */
599 for (count = 0; count < 500; count++) {
600 /*
601 * First, we want to wait for a short time.
602 */
603 udelay(10);
604 /*
605 * Now, check to see if the read has completed.
606 * ACCTL = 460h, DCV should be reset by now and 460h = 17h
607 */
608 if (!(snd_cs4281_peekBA0(chip, BA0_ACCTL) & BA0_ACCTL_DCV))
609 goto __ok1;
610 }
611
612 dev_err(chip->card->dev,
613 "AC'97 read problem (ACCTL_DCV), reg = 0x%x\n", reg);
614 result = 0xffff;
615 goto __end;
616
617 __ok1:
618 /*
619 * Wait for the valid status bit to go active.
620 */
621 for (count = 0; count < 100; count++) {
622 /*
623 * Read the AC97 status register.
624 * ACSTS = Status Register = 464h
625 * VSTS - Valid Status
626 */
627 if (snd_cs4281_peekBA0(chip, ac97_num ? BA0_ACSTS2 : BA0_ACSTS) & BA0_ACSTS_VSTS)
628 goto __ok2;
629 udelay(10);
630 }
631
632 dev_err(chip->card->dev,
633 "AC'97 read problem (ACSTS_VSTS), reg = 0x%x\n", reg);
634 result = 0xffff;
635 goto __end;
636
637 __ok2:
638 /*
639 * Read the data returned from the AC97 register.
640 * ACSDA = Status Data Register = 474h
641 */
642 result = snd_cs4281_peekBA0(chip, ac97_num ? BA0_ACSDA2 : BA0_ACSDA);
643
644 __end:
645 return result;
646}
647
648/*
649 * PCM part
650 */
651
652static int snd_cs4281_trigger(struct snd_pcm_substream *substream, int cmd)
653{
654 struct cs4281_dma *dma = substream->runtime->private_data;
655 struct cs4281 *chip = snd_pcm_substream_chip(substream);
656
657 spin_lock(&chip->reg_lock);
658 switch (cmd) {
659 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
660 dma->valDCR |= BA0_DCR_MSK;
661 dma->valFCR |= BA0_FCR_FEN;
662 break;
663 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
664 dma->valDCR &= ~BA0_DCR_MSK;
665 dma->valFCR &= ~BA0_FCR_FEN;
666 break;
667 case SNDRV_PCM_TRIGGER_START:
668 case SNDRV_PCM_TRIGGER_RESUME:
669 snd_cs4281_pokeBA0(chip, dma->regDMR, dma->valDMR & ~BA0_DMR_DMA);
670 dma->valDMR |= BA0_DMR_DMA;
671 dma->valDCR &= ~BA0_DCR_MSK;
672 dma->valFCR |= BA0_FCR_FEN;
673 break;
674 case SNDRV_PCM_TRIGGER_STOP:
675 case SNDRV_PCM_TRIGGER_SUSPEND:
676 dma->valDMR &= ~(BA0_DMR_DMA|BA0_DMR_POLL);
677 dma->valDCR |= BA0_DCR_MSK;
678 dma->valFCR &= ~BA0_FCR_FEN;
679 /* Leave wave playback FIFO enabled for FM */
680 if (dma->regFCR != BA0_FCR0)
681 dma->valFCR &= ~BA0_FCR_FEN;
682 break;
683 default:
684 spin_unlock(&chip->reg_lock);
685 return -EINVAL;
686 }
687 snd_cs4281_pokeBA0(chip, dma->regDMR, dma->valDMR);
688 snd_cs4281_pokeBA0(chip, dma->regFCR, dma->valFCR);
689 snd_cs4281_pokeBA0(chip, dma->regDCR, dma->valDCR);
690 spin_unlock(&chip->reg_lock);
691 return 0;
692}
693
694static unsigned int snd_cs4281_rate(unsigned int rate, unsigned int *real_rate)
695{
696 unsigned int val;
697
698 if (real_rate)
699 *real_rate = rate;
700 /* special "hardcoded" rates */
701 switch (rate) {
702 case 8000: return 5;
703 case 11025: return 4;
704 case 16000: return 3;
705 case 22050: return 2;
706 case 44100: return 1;
707 case 48000: return 0;
708 default:
709 break;
710 }
711 val = 1536000 / rate;
712 if (real_rate)
713 *real_rate = 1536000 / val;
714 return val;
715}
716
717static void snd_cs4281_mode(struct cs4281 *chip, struct cs4281_dma *dma,
718 struct snd_pcm_runtime *runtime,
719 int capture, int src)
720{
721 int rec_mono;
722
723 dma->valDMR = BA0_DMR_TYPE_SINGLE | BA0_DMR_AUTO |
724 (capture ? BA0_DMR_TR_WRITE : BA0_DMR_TR_READ);
725 if (runtime->channels == 1)
726 dma->valDMR |= BA0_DMR_MONO;
727 if (snd_pcm_format_unsigned(runtime->format) > 0)
728 dma->valDMR |= BA0_DMR_USIGN;
729 if (snd_pcm_format_big_endian(runtime->format) > 0)
730 dma->valDMR |= BA0_DMR_BEND;
731 switch (snd_pcm_format_width(runtime->format)) {
732 case 8: dma->valDMR |= BA0_DMR_SIZE8;
733 if (runtime->channels == 1)
734 dma->valDMR |= BA0_DMR_SWAPC;
735 break;
736 case 32: dma->valDMR |= BA0_DMR_SIZE20; break;
737 }
738 dma->frag = 0; /* for workaround */
739 dma->valDCR = BA0_DCR_TCIE | BA0_DCR_MSK;
740 if (runtime->buffer_size != runtime->period_size)
741 dma->valDCR |= BA0_DCR_HTCIE;
742 /* Initialize DMA */
743 snd_cs4281_pokeBA0(chip, dma->regDBA, runtime->dma_addr);
744 snd_cs4281_pokeBA0(chip, dma->regDBC, runtime->buffer_size - 1);
745 rec_mono = (chip->dma[1].valDMR & BA0_DMR_MONO) == BA0_DMR_MONO;
746 snd_cs4281_pokeBA0(chip, BA0_SRCSA, (chip->src_left_play_slot << 0) |
747 (chip->src_right_play_slot << 8) |
748 (chip->src_left_rec_slot << 16) |
749 ((rec_mono ? 31 : chip->src_right_rec_slot) << 24));
750 if (!src)
751 goto __skip_src;
752 if (!capture) {
753 if (dma->left_slot == chip->src_left_play_slot) {
754 unsigned int val = snd_cs4281_rate(runtime->rate, NULL);
755 snd_BUG_ON(dma->right_slot != chip->src_right_play_slot);
756 snd_cs4281_pokeBA0(chip, BA0_DACSR, val);
757 }
758 } else {
759 if (dma->left_slot == chip->src_left_rec_slot) {
760 unsigned int val = snd_cs4281_rate(runtime->rate, NULL);
761 snd_BUG_ON(dma->right_slot != chip->src_right_rec_slot);
762 snd_cs4281_pokeBA0(chip, BA0_ADCSR, val);
763 }
764 }
765 __skip_src:
766 /* Deactivate wave playback FIFO before changing slot assignments */
767 if (dma->regFCR == BA0_FCR0)
768 snd_cs4281_pokeBA0(chip, dma->regFCR, snd_cs4281_peekBA0(chip, dma->regFCR) & ~BA0_FCR_FEN);
769 /* Initialize FIFO */
770 dma->valFCR = BA0_FCR_LS(dma->left_slot) |
771 BA0_FCR_RS(capture && (dma->valDMR & BA0_DMR_MONO) ? 31 : dma->right_slot) |
772 BA0_FCR_SZ(CS4281_FIFO_SIZE) |
773 BA0_FCR_OF(dma->fifo_offset);
774 snd_cs4281_pokeBA0(chip, dma->regFCR, dma->valFCR | (capture ? BA0_FCR_PSH : 0));
775 /* Activate FIFO again for FM playback */
776 if (dma->regFCR == BA0_FCR0)
777 snd_cs4281_pokeBA0(chip, dma->regFCR, dma->valFCR | BA0_FCR_FEN);
778 /* Clear FIFO Status and Interrupt Control Register */
779 snd_cs4281_pokeBA0(chip, dma->regFSIC, 0);
780}
781
782static int snd_cs4281_playback_prepare(struct snd_pcm_substream *substream)
783{
784 struct snd_pcm_runtime *runtime = substream->runtime;
785 struct cs4281_dma *dma = runtime->private_data;
786 struct cs4281 *chip = snd_pcm_substream_chip(substream);
787
788 spin_lock_irq(&chip->reg_lock);
789 snd_cs4281_mode(chip, dma, runtime, 0, 1);
790 spin_unlock_irq(&chip->reg_lock);
791 return 0;
792}
793
794static int snd_cs4281_capture_prepare(struct snd_pcm_substream *substream)
795{
796 struct snd_pcm_runtime *runtime = substream->runtime;
797 struct cs4281_dma *dma = runtime->private_data;
798 struct cs4281 *chip = snd_pcm_substream_chip(substream);
799
800 spin_lock_irq(&chip->reg_lock);
801 snd_cs4281_mode(chip, dma, runtime, 1, 1);
802 spin_unlock_irq(&chip->reg_lock);
803 return 0;
804}
805
806static snd_pcm_uframes_t snd_cs4281_pointer(struct snd_pcm_substream *substream)
807{
808 struct snd_pcm_runtime *runtime = substream->runtime;
809 struct cs4281_dma *dma = runtime->private_data;
810 struct cs4281 *chip = snd_pcm_substream_chip(substream);
811
812 /*
813 dev_dbg(chip->card->dev,
814 "DCC = 0x%x, buffer_size = 0x%x, jiffies = %li\n",
815 snd_cs4281_peekBA0(chip, dma->regDCC), runtime->buffer_size,
816 jiffies);
817 */
818 return runtime->buffer_size -
819 snd_cs4281_peekBA0(chip, dma->regDCC) - 1;
820}
821
822static const struct snd_pcm_hardware snd_cs4281_playback =
823{
824 .info = SNDRV_PCM_INFO_MMAP |
825 SNDRV_PCM_INFO_INTERLEAVED |
826 SNDRV_PCM_INFO_MMAP_VALID |
827 SNDRV_PCM_INFO_PAUSE |
828 SNDRV_PCM_INFO_RESUME,
829 .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S8 |
830 SNDRV_PCM_FMTBIT_U16_LE | SNDRV_PCM_FMTBIT_S16_LE |
831 SNDRV_PCM_FMTBIT_U16_BE | SNDRV_PCM_FMTBIT_S16_BE |
832 SNDRV_PCM_FMTBIT_U32_LE | SNDRV_PCM_FMTBIT_S32_LE |
833 SNDRV_PCM_FMTBIT_U32_BE | SNDRV_PCM_FMTBIT_S32_BE,
834 .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
835 .rate_min = 4000,
836 .rate_max = 48000,
837 .channels_min = 1,
838 .channels_max = 2,
839 .buffer_bytes_max = (512*1024),
840 .period_bytes_min = 64,
841 .period_bytes_max = (512*1024),
842 .periods_min = 1,
843 .periods_max = 2,
844 .fifo_size = CS4281_FIFO_SIZE,
845};
846
847static const struct snd_pcm_hardware snd_cs4281_capture =
848{
849 .info = SNDRV_PCM_INFO_MMAP |
850 SNDRV_PCM_INFO_INTERLEAVED |
851 SNDRV_PCM_INFO_MMAP_VALID |
852 SNDRV_PCM_INFO_PAUSE |
853 SNDRV_PCM_INFO_RESUME,
854 .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S8 |
855 SNDRV_PCM_FMTBIT_U16_LE | SNDRV_PCM_FMTBIT_S16_LE |
856 SNDRV_PCM_FMTBIT_U16_BE | SNDRV_PCM_FMTBIT_S16_BE |
857 SNDRV_PCM_FMTBIT_U32_LE | SNDRV_PCM_FMTBIT_S32_LE |
858 SNDRV_PCM_FMTBIT_U32_BE | SNDRV_PCM_FMTBIT_S32_BE,
859 .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
860 .rate_min = 4000,
861 .rate_max = 48000,
862 .channels_min = 1,
863 .channels_max = 2,
864 .buffer_bytes_max = (512*1024),
865 .period_bytes_min = 64,
866 .period_bytes_max = (512*1024),
867 .periods_min = 1,
868 .periods_max = 2,
869 .fifo_size = CS4281_FIFO_SIZE,
870};
871
872static int snd_cs4281_playback_open(struct snd_pcm_substream *substream)
873{
874 struct cs4281 *chip = snd_pcm_substream_chip(substream);
875 struct snd_pcm_runtime *runtime = substream->runtime;
876 struct cs4281_dma *dma;
877
878 dma = &chip->dma[0];
879 dma->substream = substream;
880 dma->left_slot = 0;
881 dma->right_slot = 1;
882 runtime->private_data = dma;
883 runtime->hw = snd_cs4281_playback;
884 /* should be detected from the AC'97 layer, but it seems
885 that although CS4297A rev B reports 18-bit ADC resolution,
886 samples are 20-bit */
887 snd_pcm_hw_constraint_msbits(runtime, 0, 32, 20);
888 return 0;
889}
890
891static int snd_cs4281_capture_open(struct snd_pcm_substream *substream)
892{
893 struct cs4281 *chip = snd_pcm_substream_chip(substream);
894 struct snd_pcm_runtime *runtime = substream->runtime;
895 struct cs4281_dma *dma;
896
897 dma = &chip->dma[1];
898 dma->substream = substream;
899 dma->left_slot = 10;
900 dma->right_slot = 11;
901 runtime->private_data = dma;
902 runtime->hw = snd_cs4281_capture;
903 /* should be detected from the AC'97 layer, but it seems
904 that although CS4297A rev B reports 18-bit ADC resolution,
905 samples are 20-bit */
906 snd_pcm_hw_constraint_msbits(runtime, 0, 32, 20);
907 return 0;
908}
909
910static int snd_cs4281_playback_close(struct snd_pcm_substream *substream)
911{
912 struct cs4281_dma *dma = substream->runtime->private_data;
913
914 dma->substream = NULL;
915 return 0;
916}
917
918static int snd_cs4281_capture_close(struct snd_pcm_substream *substream)
919{
920 struct cs4281_dma *dma = substream->runtime->private_data;
921
922 dma->substream = NULL;
923 return 0;
924}
925
926static const struct snd_pcm_ops snd_cs4281_playback_ops = {
927 .open = snd_cs4281_playback_open,
928 .close = snd_cs4281_playback_close,
929 .prepare = snd_cs4281_playback_prepare,
930 .trigger = snd_cs4281_trigger,
931 .pointer = snd_cs4281_pointer,
932};
933
934static const struct snd_pcm_ops snd_cs4281_capture_ops = {
935 .open = snd_cs4281_capture_open,
936 .close = snd_cs4281_capture_close,
937 .prepare = snd_cs4281_capture_prepare,
938 .trigger = snd_cs4281_trigger,
939 .pointer = snd_cs4281_pointer,
940};
941
942static int snd_cs4281_pcm(struct cs4281 *chip, int device)
943{
944 struct snd_pcm *pcm;
945 int err;
946
947 err = snd_pcm_new(chip->card, "CS4281", device, 1, 1, &pcm);
948 if (err < 0)
949 return err;
950
951 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cs4281_playback_ops);
952 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_cs4281_capture_ops);
953
954 pcm->private_data = chip;
955 pcm->info_flags = 0;
956 strcpy(pcm->name, "CS4281");
957 chip->pcm = pcm;
958
959 snd_pcm_set_managed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV, &chip->pci->dev,
960 64*1024, 512*1024);
961
962 return 0;
963}
964
965/*
966 * Mixer section
967 */
968
969#define CS_VOL_MASK 0x1f
970
971static int snd_cs4281_info_volume(struct snd_kcontrol *kcontrol,
972 struct snd_ctl_elem_info *uinfo)
973{
974 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
975 uinfo->count = 2;
976 uinfo->value.integer.min = 0;
977 uinfo->value.integer.max = CS_VOL_MASK;
978 return 0;
979}
980
981static int snd_cs4281_get_volume(struct snd_kcontrol *kcontrol,
982 struct snd_ctl_elem_value *ucontrol)
983{
984 struct cs4281 *chip = snd_kcontrol_chip(kcontrol);
985 int regL = (kcontrol->private_value >> 16) & 0xffff;
986 int regR = kcontrol->private_value & 0xffff;
987 int volL, volR;
988
989 volL = CS_VOL_MASK - (snd_cs4281_peekBA0(chip, regL) & CS_VOL_MASK);
990 volR = CS_VOL_MASK - (snd_cs4281_peekBA0(chip, regR) & CS_VOL_MASK);
991
992 ucontrol->value.integer.value[0] = volL;
993 ucontrol->value.integer.value[1] = volR;
994 return 0;
995}
996
997static int snd_cs4281_put_volume(struct snd_kcontrol *kcontrol,
998 struct snd_ctl_elem_value *ucontrol)
999{
1000 struct cs4281 *chip = snd_kcontrol_chip(kcontrol);
1001 int change = 0;
1002 int regL = (kcontrol->private_value >> 16) & 0xffff;
1003 int regR = kcontrol->private_value & 0xffff;
1004 int volL, volR;
1005
1006 volL = CS_VOL_MASK - (snd_cs4281_peekBA0(chip, regL) & CS_VOL_MASK);
1007 volR = CS_VOL_MASK - (snd_cs4281_peekBA0(chip, regR) & CS_VOL_MASK);
1008
1009 if (ucontrol->value.integer.value[0] != volL) {
1010 volL = CS_VOL_MASK - (ucontrol->value.integer.value[0] & CS_VOL_MASK);
1011 snd_cs4281_pokeBA0(chip, regL, volL);
1012 change = 1;
1013 }
1014 if (ucontrol->value.integer.value[1] != volR) {
1015 volR = CS_VOL_MASK - (ucontrol->value.integer.value[1] & CS_VOL_MASK);
1016 snd_cs4281_pokeBA0(chip, regR, volR);
1017 change = 1;
1018 }
1019 return change;
1020}
1021
1022static const DECLARE_TLV_DB_SCALE(db_scale_dsp, -4650, 150, 0);
1023
1024static const struct snd_kcontrol_new snd_cs4281_fm_vol =
1025{
1026 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
1027 .name = "Synth Playback Volume",
1028 .info = snd_cs4281_info_volume,
1029 .get = snd_cs4281_get_volume,
1030 .put = snd_cs4281_put_volume,
1031 .private_value = ((BA0_FMLVC << 16) | BA0_FMRVC),
1032 .tlv = { .p = db_scale_dsp },
1033};
1034
1035static const struct snd_kcontrol_new snd_cs4281_pcm_vol =
1036{
1037 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
1038 .name = "PCM Stream Playback Volume",
1039 .info = snd_cs4281_info_volume,
1040 .get = snd_cs4281_get_volume,
1041 .put = snd_cs4281_put_volume,
1042 .private_value = ((BA0_PPLVC << 16) | BA0_PPRVC),
1043 .tlv = { .p = db_scale_dsp },
1044};
1045
1046static void snd_cs4281_mixer_free_ac97_bus(struct snd_ac97_bus *bus)
1047{
1048 struct cs4281 *chip = bus->private_data;
1049 chip->ac97_bus = NULL;
1050}
1051
1052static void snd_cs4281_mixer_free_ac97(struct snd_ac97 *ac97)
1053{
1054 struct cs4281 *chip = ac97->private_data;
1055 if (ac97->num)
1056 chip->ac97_secondary = NULL;
1057 else
1058 chip->ac97 = NULL;
1059}
1060
1061static int snd_cs4281_mixer(struct cs4281 *chip)
1062{
1063 struct snd_card *card = chip->card;
1064 struct snd_ac97_template ac97;
1065 int err;
1066 static const struct snd_ac97_bus_ops ops = {
1067 .write = snd_cs4281_ac97_write,
1068 .read = snd_cs4281_ac97_read,
1069 };
1070
1071 err = snd_ac97_bus(card, 0, &ops, chip, &chip->ac97_bus);
1072 if (err < 0)
1073 return err;
1074 chip->ac97_bus->private_free = snd_cs4281_mixer_free_ac97_bus;
1075
1076 memset(&ac97, 0, sizeof(ac97));
1077 ac97.private_data = chip;
1078 ac97.private_free = snd_cs4281_mixer_free_ac97;
1079 err = snd_ac97_mixer(chip->ac97_bus, &ac97, &chip->ac97);
1080 if (err < 0)
1081 return err;
1082 if (chip->dual_codec) {
1083 ac97.num = 1;
1084 err = snd_ac97_mixer(chip->ac97_bus, &ac97, &chip->ac97_secondary);
1085 if (err < 0)
1086 return err;
1087 }
1088 err = snd_ctl_add(card, snd_ctl_new1(&snd_cs4281_fm_vol, chip));
1089 if (err < 0)
1090 return err;
1091 err = snd_ctl_add(card, snd_ctl_new1(&snd_cs4281_pcm_vol, chip));
1092 if (err < 0)
1093 return err;
1094 return 0;
1095}
1096
1097
1098/*
1099 * proc interface
1100 */
1101
1102static void snd_cs4281_proc_read(struct snd_info_entry *entry,
1103 struct snd_info_buffer *buffer)
1104{
1105 struct cs4281 *chip = entry->private_data;
1106
1107 snd_iprintf(buffer, "Cirrus Logic CS4281\n\n");
1108 snd_iprintf(buffer, "Spurious half IRQs : %u\n", chip->spurious_dhtc_irq);
1109 snd_iprintf(buffer, "Spurious end IRQs : %u\n", chip->spurious_dtc_irq);
1110}
1111
1112static ssize_t snd_cs4281_BA0_read(struct snd_info_entry *entry,
1113 void *file_private_data,
1114 struct file *file, char __user *buf,
1115 size_t count, loff_t pos)
1116{
1117 struct cs4281 *chip = entry->private_data;
1118
1119 if (copy_to_user_fromio(buf, chip->ba0 + pos, count))
1120 return -EFAULT;
1121 return count;
1122}
1123
1124static ssize_t snd_cs4281_BA1_read(struct snd_info_entry *entry,
1125 void *file_private_data,
1126 struct file *file, char __user *buf,
1127 size_t count, loff_t pos)
1128{
1129 struct cs4281 *chip = entry->private_data;
1130
1131 if (copy_to_user_fromio(buf, chip->ba1 + pos, count))
1132 return -EFAULT;
1133 return count;
1134}
1135
1136static const struct snd_info_entry_ops snd_cs4281_proc_ops_BA0 = {
1137 .read = snd_cs4281_BA0_read,
1138};
1139
1140static const struct snd_info_entry_ops snd_cs4281_proc_ops_BA1 = {
1141 .read = snd_cs4281_BA1_read,
1142};
1143
1144static void snd_cs4281_proc_init(struct cs4281 *chip)
1145{
1146 struct snd_info_entry *entry;
1147
1148 snd_card_ro_proc_new(chip->card, "cs4281", chip, snd_cs4281_proc_read);
1149 if (! snd_card_proc_new(chip->card, "cs4281_BA0", &entry)) {
1150 entry->content = SNDRV_INFO_CONTENT_DATA;
1151 entry->private_data = chip;
1152 entry->c.ops = &snd_cs4281_proc_ops_BA0;
1153 entry->size = CS4281_BA0_SIZE;
1154 }
1155 if (! snd_card_proc_new(chip->card, "cs4281_BA1", &entry)) {
1156 entry->content = SNDRV_INFO_CONTENT_DATA;
1157 entry->private_data = chip;
1158 entry->c.ops = &snd_cs4281_proc_ops_BA1;
1159 entry->size = CS4281_BA1_SIZE;
1160 }
1161}
1162
1163/*
1164 * joystick support
1165 */
1166
1167#if IS_REACHABLE(CONFIG_GAMEPORT)
1168
1169static void snd_cs4281_gameport_trigger(struct gameport *gameport)
1170{
1171 struct cs4281 *chip = gameport_get_port_data(gameport);
1172
1173 if (snd_BUG_ON(!chip))
1174 return;
1175 snd_cs4281_pokeBA0(chip, BA0_JSPT, 0xff);
1176}
1177
1178static unsigned char snd_cs4281_gameport_read(struct gameport *gameport)
1179{
1180 struct cs4281 *chip = gameport_get_port_data(gameport);
1181
1182 if (snd_BUG_ON(!chip))
1183 return 0;
1184 return snd_cs4281_peekBA0(chip, BA0_JSPT);
1185}
1186
1187#ifdef COOKED_MODE
1188static int snd_cs4281_gameport_cooked_read(struct gameport *gameport,
1189 int *axes, int *buttons)
1190{
1191 struct cs4281 *chip = gameport_get_port_data(gameport);
1192 unsigned js1, js2, jst;
1193
1194 if (snd_BUG_ON(!chip))
1195 return 0;
1196
1197 js1 = snd_cs4281_peekBA0(chip, BA0_JSC1);
1198 js2 = snd_cs4281_peekBA0(chip, BA0_JSC2);
1199 jst = snd_cs4281_peekBA0(chip, BA0_JSPT);
1200
1201 *buttons = (~jst >> 4) & 0x0F;
1202
1203 axes[0] = ((js1 & JSC1_Y1V_MASK) >> JSC1_Y1V_SHIFT) & 0xFFFF;
1204 axes[1] = ((js1 & JSC1_X1V_MASK) >> JSC1_X1V_SHIFT) & 0xFFFF;
1205 axes[2] = ((js2 & JSC2_Y2V_MASK) >> JSC2_Y2V_SHIFT) & 0xFFFF;
1206 axes[3] = ((js2 & JSC2_X2V_MASK) >> JSC2_X2V_SHIFT) & 0xFFFF;
1207
1208 for (jst = 0; jst < 4; ++jst)
1209 if (axes[jst] == 0xFFFF) axes[jst] = -1;
1210 return 0;
1211}
1212#else
1213#define snd_cs4281_gameport_cooked_read NULL
1214#endif
1215
1216static int snd_cs4281_gameport_open(struct gameport *gameport, int mode)
1217{
1218 switch (mode) {
1219#ifdef COOKED_MODE
1220 case GAMEPORT_MODE_COOKED:
1221 return 0;
1222#endif
1223 case GAMEPORT_MODE_RAW:
1224 return 0;
1225 default:
1226 return -1;
1227 }
1228 return 0;
1229}
1230
1231static int snd_cs4281_create_gameport(struct cs4281 *chip)
1232{
1233 struct gameport *gp;
1234
1235 chip->gameport = gp = gameport_allocate_port();
1236 if (!gp) {
1237 dev_err(chip->card->dev,
1238 "cannot allocate memory for gameport\n");
1239 return -ENOMEM;
1240 }
1241
1242 gameport_set_name(gp, "CS4281 Gameport");
1243 gameport_set_phys(gp, "pci%s/gameport0", pci_name(chip->pci));
1244 gameport_set_dev_parent(gp, &chip->pci->dev);
1245 gp->open = snd_cs4281_gameport_open;
1246 gp->read = snd_cs4281_gameport_read;
1247 gp->trigger = snd_cs4281_gameport_trigger;
1248 gp->cooked_read = snd_cs4281_gameport_cooked_read;
1249 gameport_set_port_data(gp, chip);
1250
1251 snd_cs4281_pokeBA0(chip, BA0_JSIO, 0xFF); // ?
1252 snd_cs4281_pokeBA0(chip, BA0_JSCTL, JSCTL_SP_MEDIUM_SLOW);
1253
1254 gameport_register_port(gp);
1255
1256 return 0;
1257}
1258
1259static void snd_cs4281_free_gameport(struct cs4281 *chip)
1260{
1261 if (chip->gameport) {
1262 gameport_unregister_port(chip->gameport);
1263 chip->gameport = NULL;
1264 }
1265}
1266#else
1267static inline int snd_cs4281_create_gameport(struct cs4281 *chip) { return -ENOSYS; }
1268static inline void snd_cs4281_free_gameport(struct cs4281 *chip) { }
1269#endif /* IS_REACHABLE(CONFIG_GAMEPORT) */
1270
1271static void snd_cs4281_free(struct snd_card *card)
1272{
1273 struct cs4281 *chip = card->private_data;
1274
1275 snd_cs4281_free_gameport(chip);
1276
1277 /* Mask interrupts */
1278 snd_cs4281_pokeBA0(chip, BA0_HIMR, 0x7fffffff);
1279 /* Stop the DLL Clock logic. */
1280 snd_cs4281_pokeBA0(chip, BA0_CLKCR1, 0);
1281 /* Sound System Power Management - Turn Everything OFF */
1282 snd_cs4281_pokeBA0(chip, BA0_SSPM, 0);
1283}
1284
1285static int snd_cs4281_chip_init(struct cs4281 *chip); /* defined below */
1286
1287static int snd_cs4281_create(struct snd_card *card,
1288 struct pci_dev *pci,
1289 int dual_codec)
1290{
1291 struct cs4281 *chip = card->private_data;
1292 int err;
1293
1294 err = pcim_enable_device(pci);
1295 if (err < 0)
1296 return err;
1297 spin_lock_init(&chip->reg_lock);
1298 chip->card = card;
1299 chip->pci = pci;
1300 chip->irq = -1;
1301 pci_set_master(pci);
1302 if (dual_codec < 0 || dual_codec > 3) {
1303 dev_err(card->dev, "invalid dual_codec option %d\n", dual_codec);
1304 dual_codec = 0;
1305 }
1306 chip->dual_codec = dual_codec;
1307
1308 err = pcim_iomap_regions(pci, 0x03, "CS4281"); /* 2 BARs */
1309 if (err < 0)
1310 return err;
1311 chip->ba0_addr = pci_resource_start(pci, 0);
1312 chip->ba1_addr = pci_resource_start(pci, 1);
1313
1314 chip->ba0 = pcim_iomap_table(pci)[0];
1315 chip->ba1 = pcim_iomap_table(pci)[1];
1316 if (devm_request_irq(&pci->dev, pci->irq, snd_cs4281_interrupt,
1317 IRQF_SHARED, KBUILD_MODNAME, chip)) {
1318 dev_err(card->dev, "unable to grab IRQ %d\n", pci->irq);
1319 return -ENOMEM;
1320 }
1321 chip->irq = pci->irq;
1322 card->sync_irq = chip->irq;
1323 card->private_free = snd_cs4281_free;
1324
1325 err = snd_cs4281_chip_init(chip);
1326 if (err)
1327 return err;
1328
1329 snd_cs4281_proc_init(chip);
1330 return 0;
1331}
1332
1333static int snd_cs4281_chip_init(struct cs4281 *chip)
1334{
1335 unsigned int tmp;
1336 unsigned long end_time;
1337 int retry_count = 2;
1338
1339 /* Having EPPMC.FPDN=1 prevent proper chip initialisation */
1340 tmp = snd_cs4281_peekBA0(chip, BA0_EPPMC);
1341 if (tmp & BA0_EPPMC_FPDN)
1342 snd_cs4281_pokeBA0(chip, BA0_EPPMC, tmp & ~BA0_EPPMC_FPDN);
1343
1344 __retry:
1345 tmp = snd_cs4281_peekBA0(chip, BA0_CFLR);
1346 if (tmp != BA0_CFLR_DEFAULT) {
1347 snd_cs4281_pokeBA0(chip, BA0_CFLR, BA0_CFLR_DEFAULT);
1348 tmp = snd_cs4281_peekBA0(chip, BA0_CFLR);
1349 if (tmp != BA0_CFLR_DEFAULT) {
1350 dev_err(chip->card->dev,
1351 "CFLR setup failed (0x%x)\n", tmp);
1352 return -EIO;
1353 }
1354 }
1355
1356 /* Set the 'Configuration Write Protect' register
1357 * to 4281h. Allows vendor-defined configuration
1358 * space between 0e4h and 0ffh to be written. */
1359 snd_cs4281_pokeBA0(chip, BA0_CWPR, 0x4281);
1360
1361 tmp = snd_cs4281_peekBA0(chip, BA0_SERC1);
1362 if (tmp != (BA0_SERC1_SO1EN | BA0_SERC1_AC97)) {
1363 dev_err(chip->card->dev,
1364 "SERC1 AC'97 check failed (0x%x)\n", tmp);
1365 return -EIO;
1366 }
1367 tmp = snd_cs4281_peekBA0(chip, BA0_SERC2);
1368 if (tmp != (BA0_SERC2_SI1EN | BA0_SERC2_AC97)) {
1369 dev_err(chip->card->dev,
1370 "SERC2 AC'97 check failed (0x%x)\n", tmp);
1371 return -EIO;
1372 }
1373
1374 /* Sound System Power Management */
1375 snd_cs4281_pokeBA0(chip, BA0_SSPM, BA0_SSPM_MIXEN | BA0_SSPM_CSRCEN |
1376 BA0_SSPM_PSRCEN | BA0_SSPM_JSEN |
1377 BA0_SSPM_ACLEN | BA0_SSPM_FMEN);
1378
1379 /* Serial Port Power Management */
1380 /* Blast the clock control register to zero so that the
1381 * PLL starts out in a known state, and blast the master serial
1382 * port control register to zero so that the serial ports also
1383 * start out in a known state. */
1384 snd_cs4281_pokeBA0(chip, BA0_CLKCR1, 0);
1385 snd_cs4281_pokeBA0(chip, BA0_SERMC, 0);
1386
1387 /* Make ESYN go to zero to turn off
1388 * the Sync pulse on the AC97 link. */
1389 snd_cs4281_pokeBA0(chip, BA0_ACCTL, 0);
1390 udelay(50);
1391
1392 /* Drive the ARST# pin low for a minimum of 1uS (as defined in the AC97
1393 * spec) and then drive it high. This is done for non AC97 modes since
1394 * there might be logic external to the CS4281 that uses the ARST# line
1395 * for a reset. */
1396 snd_cs4281_pokeBA0(chip, BA0_SPMC, 0);
1397 udelay(50);
1398 snd_cs4281_pokeBA0(chip, BA0_SPMC, BA0_SPMC_RSTN);
1399 msleep(50);
1400
1401 if (chip->dual_codec)
1402 snd_cs4281_pokeBA0(chip, BA0_SPMC, BA0_SPMC_RSTN | BA0_SPMC_ASDI2E);
1403
1404 /*
1405 * Set the serial port timing configuration.
1406 */
1407 snd_cs4281_pokeBA0(chip, BA0_SERMC,
1408 (chip->dual_codec ? BA0_SERMC_TCID(chip->dual_codec) : BA0_SERMC_TCID(1)) |
1409 BA0_SERMC_PTC_AC97 | BA0_SERMC_MSPE);
1410
1411 /*
1412 * Start the DLL Clock logic.
1413 */
1414 snd_cs4281_pokeBA0(chip, BA0_CLKCR1, BA0_CLKCR1_DLLP);
1415 msleep(50);
1416 snd_cs4281_pokeBA0(chip, BA0_CLKCR1, BA0_CLKCR1_SWCE | BA0_CLKCR1_DLLP);
1417
1418 /*
1419 * Wait for the DLL ready signal from the clock logic.
1420 */
1421 end_time = jiffies + HZ;
1422 do {
1423 /*
1424 * Read the AC97 status register to see if we've seen a CODEC
1425 * signal from the AC97 codec.
1426 */
1427 if (snd_cs4281_peekBA0(chip, BA0_CLKCR1) & BA0_CLKCR1_DLLRDY)
1428 goto __ok0;
1429 schedule_timeout_uninterruptible(1);
1430 } while (time_after_eq(end_time, jiffies));
1431
1432 dev_err(chip->card->dev, "DLLRDY not seen\n");
1433 return -EIO;
1434
1435 __ok0:
1436
1437 /*
1438 * The first thing we do here is to enable sync generation. As soon
1439 * as we start receiving bit clock, we'll start producing the SYNC
1440 * signal.
1441 */
1442 snd_cs4281_pokeBA0(chip, BA0_ACCTL, BA0_ACCTL_ESYN);
1443
1444 /*
1445 * Wait for the codec ready signal from the AC97 codec.
1446 */
1447 end_time = jiffies + HZ;
1448 do {
1449 /*
1450 * Read the AC97 status register to see if we've seen a CODEC
1451 * signal from the AC97 codec.
1452 */
1453 if (snd_cs4281_peekBA0(chip, BA0_ACSTS) & BA0_ACSTS_CRDY)
1454 goto __ok1;
1455 schedule_timeout_uninterruptible(1);
1456 } while (time_after_eq(end_time, jiffies));
1457
1458 dev_err(chip->card->dev,
1459 "never read codec ready from AC'97 (0x%x)\n",
1460 snd_cs4281_peekBA0(chip, BA0_ACSTS));
1461 return -EIO;
1462
1463 __ok1:
1464 if (chip->dual_codec) {
1465 end_time = jiffies + HZ;
1466 do {
1467 if (snd_cs4281_peekBA0(chip, BA0_ACSTS2) & BA0_ACSTS_CRDY)
1468 goto __codec2_ok;
1469 schedule_timeout_uninterruptible(1);
1470 } while (time_after_eq(end_time, jiffies));
1471 dev_info(chip->card->dev,
1472 "secondary codec doesn't respond. disable it...\n");
1473 chip->dual_codec = 0;
1474 __codec2_ok: ;
1475 }
1476
1477 /*
1478 * Assert the valid frame signal so that we can start sending commands
1479 * to the AC97 codec.
1480 */
1481
1482 snd_cs4281_pokeBA0(chip, BA0_ACCTL, BA0_ACCTL_VFRM | BA0_ACCTL_ESYN);
1483
1484 /*
1485 * Wait until we've sampled input slots 3 and 4 as valid, meaning that
1486 * the codec is pumping ADC data across the AC-link.
1487 */
1488
1489 end_time = jiffies + HZ;
1490 do {
1491 /*
1492 * Read the input slot valid register and see if input slots 3
1493 * 4 are valid yet.
1494 */
1495 if ((snd_cs4281_peekBA0(chip, BA0_ACISV) & (BA0_ACISV_SLV(3) | BA0_ACISV_SLV(4))) == (BA0_ACISV_SLV(3) | BA0_ACISV_SLV(4)))
1496 goto __ok2;
1497 schedule_timeout_uninterruptible(1);
1498 } while (time_after_eq(end_time, jiffies));
1499
1500 if (--retry_count > 0)
1501 goto __retry;
1502 dev_err(chip->card->dev, "never read ISV3 and ISV4 from AC'97\n");
1503 return -EIO;
1504
1505 __ok2:
1506
1507 /*
1508 * Now, assert valid frame and the slot 3 and 4 valid bits. This will
1509 * commense the transfer of digital audio data to the AC97 codec.
1510 */
1511 snd_cs4281_pokeBA0(chip, BA0_ACOSV, BA0_ACOSV_SLV(3) | BA0_ACOSV_SLV(4));
1512
1513 /*
1514 * Initialize DMA structures
1515 */
1516 for (tmp = 0; tmp < 4; tmp++) {
1517 struct cs4281_dma *dma = &chip->dma[tmp];
1518 dma->regDBA = BA0_DBA0 + (tmp * 0x10);
1519 dma->regDCA = BA0_DCA0 + (tmp * 0x10);
1520 dma->regDBC = BA0_DBC0 + (tmp * 0x10);
1521 dma->regDCC = BA0_DCC0 + (tmp * 0x10);
1522 dma->regDMR = BA0_DMR0 + (tmp * 8);
1523 dma->regDCR = BA0_DCR0 + (tmp * 8);
1524 dma->regHDSR = BA0_HDSR0 + (tmp * 4);
1525 dma->regFCR = BA0_FCR0 + (tmp * 4);
1526 dma->regFSIC = BA0_FSIC0 + (tmp * 4);
1527 dma->fifo_offset = tmp * CS4281_FIFO_SIZE;
1528 snd_cs4281_pokeBA0(chip, dma->regFCR,
1529 BA0_FCR_LS(31) |
1530 BA0_FCR_RS(31) |
1531 BA0_FCR_SZ(CS4281_FIFO_SIZE) |
1532 BA0_FCR_OF(dma->fifo_offset));
1533 }
1534
1535 chip->src_left_play_slot = 0; /* AC'97 left PCM playback (3) */
1536 chip->src_right_play_slot = 1; /* AC'97 right PCM playback (4) */
1537 chip->src_left_rec_slot = 10; /* AC'97 left PCM record (3) */
1538 chip->src_right_rec_slot = 11; /* AC'97 right PCM record (4) */
1539
1540 /* Activate wave playback FIFO for FM playback */
1541 chip->dma[0].valFCR = BA0_FCR_FEN | BA0_FCR_LS(0) |
1542 BA0_FCR_RS(1) |
1543 BA0_FCR_SZ(CS4281_FIFO_SIZE) |
1544 BA0_FCR_OF(chip->dma[0].fifo_offset);
1545 snd_cs4281_pokeBA0(chip, chip->dma[0].regFCR, chip->dma[0].valFCR);
1546 snd_cs4281_pokeBA0(chip, BA0_SRCSA, (chip->src_left_play_slot << 0) |
1547 (chip->src_right_play_slot << 8) |
1548 (chip->src_left_rec_slot << 16) |
1549 (chip->src_right_rec_slot << 24));
1550
1551 /* Initialize digital volume */
1552 snd_cs4281_pokeBA0(chip, BA0_PPLVC, 0);
1553 snd_cs4281_pokeBA0(chip, BA0_PPRVC, 0);
1554
1555 /* Enable IRQs */
1556 snd_cs4281_pokeBA0(chip, BA0_HICR, BA0_HICR_EOI);
1557 /* Unmask interrupts */
1558 snd_cs4281_pokeBA0(chip, BA0_HIMR, 0x7fffffff & ~(
1559 BA0_HISR_MIDI |
1560 BA0_HISR_DMAI |
1561 BA0_HISR_DMA(0) |
1562 BA0_HISR_DMA(1) |
1563 BA0_HISR_DMA(2) |
1564 BA0_HISR_DMA(3)));
1565
1566 return 0;
1567}
1568
1569/*
1570 * MIDI section
1571 */
1572
1573static void snd_cs4281_midi_reset(struct cs4281 *chip)
1574{
1575 snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr | BA0_MIDCR_MRST);
1576 udelay(100);
1577 snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr);
1578}
1579
1580static int snd_cs4281_midi_input_open(struct snd_rawmidi_substream *substream)
1581{
1582 struct cs4281 *chip = substream->rmidi->private_data;
1583
1584 spin_lock_irq(&chip->reg_lock);
1585 chip->midcr |= BA0_MIDCR_RXE;
1586 chip->midi_input = substream;
1587 if (!(chip->uartm & CS4281_MODE_OUTPUT)) {
1588 snd_cs4281_midi_reset(chip);
1589 } else {
1590 snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr);
1591 }
1592 spin_unlock_irq(&chip->reg_lock);
1593 return 0;
1594}
1595
1596static int snd_cs4281_midi_input_close(struct snd_rawmidi_substream *substream)
1597{
1598 struct cs4281 *chip = substream->rmidi->private_data;
1599
1600 spin_lock_irq(&chip->reg_lock);
1601 chip->midcr &= ~(BA0_MIDCR_RXE | BA0_MIDCR_RIE);
1602 chip->midi_input = NULL;
1603 if (!(chip->uartm & CS4281_MODE_OUTPUT)) {
1604 snd_cs4281_midi_reset(chip);
1605 } else {
1606 snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr);
1607 }
1608 chip->uartm &= ~CS4281_MODE_INPUT;
1609 spin_unlock_irq(&chip->reg_lock);
1610 return 0;
1611}
1612
1613static int snd_cs4281_midi_output_open(struct snd_rawmidi_substream *substream)
1614{
1615 struct cs4281 *chip = substream->rmidi->private_data;
1616
1617 spin_lock_irq(&chip->reg_lock);
1618 chip->uartm |= CS4281_MODE_OUTPUT;
1619 chip->midcr |= BA0_MIDCR_TXE;
1620 chip->midi_output = substream;
1621 if (!(chip->uartm & CS4281_MODE_INPUT)) {
1622 snd_cs4281_midi_reset(chip);
1623 } else {
1624 snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr);
1625 }
1626 spin_unlock_irq(&chip->reg_lock);
1627 return 0;
1628}
1629
1630static int snd_cs4281_midi_output_close(struct snd_rawmidi_substream *substream)
1631{
1632 struct cs4281 *chip = substream->rmidi->private_data;
1633
1634 spin_lock_irq(&chip->reg_lock);
1635 chip->midcr &= ~(BA0_MIDCR_TXE | BA0_MIDCR_TIE);
1636 chip->midi_output = NULL;
1637 if (!(chip->uartm & CS4281_MODE_INPUT)) {
1638 snd_cs4281_midi_reset(chip);
1639 } else {
1640 snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr);
1641 }
1642 chip->uartm &= ~CS4281_MODE_OUTPUT;
1643 spin_unlock_irq(&chip->reg_lock);
1644 return 0;
1645}
1646
1647static void snd_cs4281_midi_input_trigger(struct snd_rawmidi_substream *substream, int up)
1648{
1649 unsigned long flags;
1650 struct cs4281 *chip = substream->rmidi->private_data;
1651
1652 spin_lock_irqsave(&chip->reg_lock, flags);
1653 if (up) {
1654 if ((chip->midcr & BA0_MIDCR_RIE) == 0) {
1655 chip->midcr |= BA0_MIDCR_RIE;
1656 snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr);
1657 }
1658 } else {
1659 if (chip->midcr & BA0_MIDCR_RIE) {
1660 chip->midcr &= ~BA0_MIDCR_RIE;
1661 snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr);
1662 }
1663 }
1664 spin_unlock_irqrestore(&chip->reg_lock, flags);
1665}
1666
1667static void snd_cs4281_midi_output_trigger(struct snd_rawmidi_substream *substream, int up)
1668{
1669 unsigned long flags;
1670 struct cs4281 *chip = substream->rmidi->private_data;
1671 unsigned char byte;
1672
1673 spin_lock_irqsave(&chip->reg_lock, flags);
1674 if (up) {
1675 if ((chip->midcr & BA0_MIDCR_TIE) == 0) {
1676 chip->midcr |= BA0_MIDCR_TIE;
1677 /* fill UART FIFO buffer at first, and turn Tx interrupts only if necessary */
1678 while ((chip->midcr & BA0_MIDCR_TIE) &&
1679 (snd_cs4281_peekBA0(chip, BA0_MIDSR) & BA0_MIDSR_TBF) == 0) {
1680 if (snd_rawmidi_transmit(substream, &byte, 1) != 1) {
1681 chip->midcr &= ~BA0_MIDCR_TIE;
1682 } else {
1683 snd_cs4281_pokeBA0(chip, BA0_MIDWP, byte);
1684 }
1685 }
1686 snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr);
1687 }
1688 } else {
1689 if (chip->midcr & BA0_MIDCR_TIE) {
1690 chip->midcr &= ~BA0_MIDCR_TIE;
1691 snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr);
1692 }
1693 }
1694 spin_unlock_irqrestore(&chip->reg_lock, flags);
1695}
1696
1697static const struct snd_rawmidi_ops snd_cs4281_midi_output =
1698{
1699 .open = snd_cs4281_midi_output_open,
1700 .close = snd_cs4281_midi_output_close,
1701 .trigger = snd_cs4281_midi_output_trigger,
1702};
1703
1704static const struct snd_rawmidi_ops snd_cs4281_midi_input =
1705{
1706 .open = snd_cs4281_midi_input_open,
1707 .close = snd_cs4281_midi_input_close,
1708 .trigger = snd_cs4281_midi_input_trigger,
1709};
1710
1711static int snd_cs4281_midi(struct cs4281 *chip, int device)
1712{
1713 struct snd_rawmidi *rmidi;
1714 int err;
1715
1716 err = snd_rawmidi_new(chip->card, "CS4281", device, 1, 1, &rmidi);
1717 if (err < 0)
1718 return err;
1719 strcpy(rmidi->name, "CS4281");
1720 snd_rawmidi_set_ops(rmidi, SNDRV_RAWMIDI_STREAM_OUTPUT, &snd_cs4281_midi_output);
1721 snd_rawmidi_set_ops(rmidi, SNDRV_RAWMIDI_STREAM_INPUT, &snd_cs4281_midi_input);
1722 rmidi->info_flags |= SNDRV_RAWMIDI_INFO_OUTPUT | SNDRV_RAWMIDI_INFO_INPUT | SNDRV_RAWMIDI_INFO_DUPLEX;
1723 rmidi->private_data = chip;
1724 chip->rmidi = rmidi;
1725 return 0;
1726}
1727
1728/*
1729 * Interrupt handler
1730 */
1731
1732static irqreturn_t snd_cs4281_interrupt(int irq, void *dev_id)
1733{
1734 struct cs4281 *chip = dev_id;
1735 unsigned int status, dma, val;
1736 struct cs4281_dma *cdma;
1737
1738 if (chip == NULL)
1739 return IRQ_NONE;
1740 status = snd_cs4281_peekBA0(chip, BA0_HISR);
1741 if ((status & 0x7fffffff) == 0) {
1742 snd_cs4281_pokeBA0(chip, BA0_HICR, BA0_HICR_EOI);
1743 return IRQ_NONE;
1744 }
1745
1746 if (status & (BA0_HISR_DMA(0)|BA0_HISR_DMA(1)|BA0_HISR_DMA(2)|BA0_HISR_DMA(3))) {
1747 for (dma = 0; dma < 4; dma++)
1748 if (status & BA0_HISR_DMA(dma)) {
1749 cdma = &chip->dma[dma];
1750 spin_lock(&chip->reg_lock);
1751 /* ack DMA IRQ */
1752 val = snd_cs4281_peekBA0(chip, cdma->regHDSR);
1753 /* workaround, sometimes CS4281 acknowledges */
1754 /* end or middle transfer position twice */
1755 cdma->frag++;
1756 if ((val & BA0_HDSR_DHTC) && !(cdma->frag & 1)) {
1757 cdma->frag--;
1758 chip->spurious_dhtc_irq++;
1759 spin_unlock(&chip->reg_lock);
1760 continue;
1761 }
1762 if ((val & BA0_HDSR_DTC) && (cdma->frag & 1)) {
1763 cdma->frag--;
1764 chip->spurious_dtc_irq++;
1765 spin_unlock(&chip->reg_lock);
1766 continue;
1767 }
1768 spin_unlock(&chip->reg_lock);
1769 snd_pcm_period_elapsed(cdma->substream);
1770 }
1771 }
1772
1773 if ((status & BA0_HISR_MIDI) && chip->rmidi) {
1774 unsigned char c;
1775
1776 spin_lock(&chip->reg_lock);
1777 while ((snd_cs4281_peekBA0(chip, BA0_MIDSR) & BA0_MIDSR_RBE) == 0) {
1778 c = snd_cs4281_peekBA0(chip, BA0_MIDRP);
1779 if ((chip->midcr & BA0_MIDCR_RIE) == 0)
1780 continue;
1781 snd_rawmidi_receive(chip->midi_input, &c, 1);
1782 }
1783 while ((snd_cs4281_peekBA0(chip, BA0_MIDSR) & BA0_MIDSR_TBF) == 0) {
1784 if ((chip->midcr & BA0_MIDCR_TIE) == 0)
1785 break;
1786 if (snd_rawmidi_transmit(chip->midi_output, &c, 1) != 1) {
1787 chip->midcr &= ~BA0_MIDCR_TIE;
1788 snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr);
1789 break;
1790 }
1791 snd_cs4281_pokeBA0(chip, BA0_MIDWP, c);
1792 }
1793 spin_unlock(&chip->reg_lock);
1794 }
1795
1796 /* EOI to the PCI part... reenables interrupts */
1797 snd_cs4281_pokeBA0(chip, BA0_HICR, BA0_HICR_EOI);
1798
1799 return IRQ_HANDLED;
1800}
1801
1802
1803/*
1804 * OPL3 command
1805 */
1806static void snd_cs4281_opl3_command(struct snd_opl3 *opl3, unsigned short cmd,
1807 unsigned char val)
1808{
1809 unsigned long flags;
1810 struct cs4281 *chip = opl3->private_data;
1811 void __iomem *port;
1812
1813 if (cmd & OPL3_RIGHT)
1814 port = chip->ba0 + BA0_B1AP; /* right port */
1815 else
1816 port = chip->ba0 + BA0_B0AP; /* left port */
1817
1818 spin_lock_irqsave(&opl3->reg_lock, flags);
1819
1820 writel((unsigned int)cmd, port);
1821 udelay(10);
1822
1823 writel((unsigned int)val, port + 4);
1824 udelay(30);
1825
1826 spin_unlock_irqrestore(&opl3->reg_lock, flags);
1827}
1828
1829static int __snd_cs4281_probe(struct pci_dev *pci,
1830 const struct pci_device_id *pci_id)
1831{
1832 static int dev;
1833 struct snd_card *card;
1834 struct cs4281 *chip;
1835 struct snd_opl3 *opl3;
1836 int err;
1837
1838 if (dev >= SNDRV_CARDS)
1839 return -ENODEV;
1840 if (!enable[dev]) {
1841 dev++;
1842 return -ENOENT;
1843 }
1844
1845 err = snd_devm_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE,
1846 sizeof(*chip), &card);
1847 if (err < 0)
1848 return err;
1849 chip = card->private_data;
1850
1851 err = snd_cs4281_create(card, pci, dual_codec[dev]);
1852 if (err < 0)
1853 return err;
1854
1855 err = snd_cs4281_mixer(chip);
1856 if (err < 0)
1857 return err;
1858 err = snd_cs4281_pcm(chip, 0);
1859 if (err < 0)
1860 return err;
1861 err = snd_cs4281_midi(chip, 0);
1862 if (err < 0)
1863 return err;
1864 err = snd_opl3_new(card, OPL3_HW_OPL3_CS4281, &opl3);
1865 if (err < 0)
1866 return err;
1867 opl3->private_data = chip;
1868 opl3->command = snd_cs4281_opl3_command;
1869 snd_opl3_init(opl3);
1870 err = snd_opl3_hwdep_new(opl3, 0, 1, NULL);
1871 if (err < 0)
1872 return err;
1873 snd_cs4281_create_gameport(chip);
1874 strcpy(card->driver, "CS4281");
1875 strcpy(card->shortname, "Cirrus Logic CS4281");
1876 sprintf(card->longname, "%s at 0x%lx, irq %d",
1877 card->shortname,
1878 chip->ba0_addr,
1879 chip->irq);
1880
1881 err = snd_card_register(card);
1882 if (err < 0)
1883 return err;
1884
1885 pci_set_drvdata(pci, card);
1886 dev++;
1887 return 0;
1888}
1889
1890static int snd_cs4281_probe(struct pci_dev *pci,
1891 const struct pci_device_id *pci_id)
1892{
1893 return snd_card_free_on_error(&pci->dev, __snd_cs4281_probe(pci, pci_id));
1894}
1895
1896/*
1897 * Power Management
1898 */
1899static const int saved_regs[SUSPEND_REGISTERS] = {
1900 BA0_JSCTL,
1901 BA0_GPIOR,
1902 BA0_SSCR,
1903 BA0_MIDCR,
1904 BA0_SRCSA,
1905 BA0_PASR,
1906 BA0_CASR,
1907 BA0_DACSR,
1908 BA0_ADCSR,
1909 BA0_FMLVC,
1910 BA0_FMRVC,
1911 BA0_PPLVC,
1912 BA0_PPRVC,
1913};
1914
1915#define CLKCR1_CKRA 0x00010000L
1916
1917static int cs4281_suspend(struct device *dev)
1918{
1919 struct snd_card *card = dev_get_drvdata(dev);
1920 struct cs4281 *chip = card->private_data;
1921 u32 ulCLK;
1922 unsigned int i;
1923
1924 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
1925 snd_ac97_suspend(chip->ac97);
1926 snd_ac97_suspend(chip->ac97_secondary);
1927
1928 ulCLK = snd_cs4281_peekBA0(chip, BA0_CLKCR1);
1929 ulCLK |= CLKCR1_CKRA;
1930 snd_cs4281_pokeBA0(chip, BA0_CLKCR1, ulCLK);
1931
1932 /* Disable interrupts. */
1933 snd_cs4281_pokeBA0(chip, BA0_HICR, BA0_HICR_CHGM);
1934
1935 /* remember the status registers */
1936 for (i = 0; i < ARRAY_SIZE(saved_regs); i++)
1937 if (saved_regs[i])
1938 chip->suspend_regs[i] = snd_cs4281_peekBA0(chip, saved_regs[i]);
1939
1940 /* Turn off the serial ports. */
1941 snd_cs4281_pokeBA0(chip, BA0_SERMC, 0);
1942
1943 /* Power off FM, Joystick, AC link, */
1944 snd_cs4281_pokeBA0(chip, BA0_SSPM, 0);
1945
1946 /* DLL off. */
1947 snd_cs4281_pokeBA0(chip, BA0_CLKCR1, 0);
1948
1949 /* AC link off. */
1950 snd_cs4281_pokeBA0(chip, BA0_SPMC, 0);
1951
1952 ulCLK = snd_cs4281_peekBA0(chip, BA0_CLKCR1);
1953 ulCLK &= ~CLKCR1_CKRA;
1954 snd_cs4281_pokeBA0(chip, BA0_CLKCR1, ulCLK);
1955 return 0;
1956}
1957
1958static int cs4281_resume(struct device *dev)
1959{
1960 struct snd_card *card = dev_get_drvdata(dev);
1961 struct cs4281 *chip = card->private_data;
1962 unsigned int i;
1963 u32 ulCLK;
1964
1965 ulCLK = snd_cs4281_peekBA0(chip, BA0_CLKCR1);
1966 ulCLK |= CLKCR1_CKRA;
1967 snd_cs4281_pokeBA0(chip, BA0_CLKCR1, ulCLK);
1968
1969 snd_cs4281_chip_init(chip);
1970
1971 /* restore the status registers */
1972 for (i = 0; i < ARRAY_SIZE(saved_regs); i++)
1973 if (saved_regs[i])
1974 snd_cs4281_pokeBA0(chip, saved_regs[i], chip->suspend_regs[i]);
1975
1976 snd_ac97_resume(chip->ac97);
1977 snd_ac97_resume(chip->ac97_secondary);
1978
1979 ulCLK = snd_cs4281_peekBA0(chip, BA0_CLKCR1);
1980 ulCLK &= ~CLKCR1_CKRA;
1981 snd_cs4281_pokeBA0(chip, BA0_CLKCR1, ulCLK);
1982
1983 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
1984 return 0;
1985}
1986
1987static DEFINE_SIMPLE_DEV_PM_OPS(cs4281_pm, cs4281_suspend, cs4281_resume);
1988
1989static struct pci_driver cs4281_driver = {
1990 .name = KBUILD_MODNAME,
1991 .id_table = snd_cs4281_ids,
1992 .probe = snd_cs4281_probe,
1993 .driver = {
1994 .pm = &cs4281_pm,
1995 },
1996};
1997
1998module_pci_driver(cs4281_driver);
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