source: GPL/trunk/alsa-kernel/pci/cs4281.c@ 679

Last change on this file since 679 was 679, checked in by David Azarewicz, 4 years ago

Merge changes from Paul's uniaud32next branch.
File size: 64.6 KB
Line 
1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Driver for Cirrus Logic CS4281 based PCI soundcard
4 * Copyright (c) by Jaroslav Kysela <perex@perex.cz>,
5 */
6
7#include <linux/io.h>
8#include <linux/delay.h>
9#include <linux/interrupt.h>
10#include <linux/init.h>
11#include <linux/pci.h>
12#include <linux/slab.h>
13#include <linux/gameport.h>
14#include <linux/module.h>
15#include <sound/core.h>
16#include <sound/control.h>
17#include <sound/pcm.h>
18#include <sound/rawmidi.h>
19#include <sound/ac97_codec.h>
20#include <sound/tlv.h>
21#include <sound/opl3.h>
22#include <sound/initval.h>
23
24
25#ifdef TARGET_OS2
26#define KBUILD_MODNAME "cs4281"
27#endif
28MODULE_AUTHOR("Jaroslav Kysela <perex@perex.cz>");
29MODULE_DESCRIPTION("Cirrus Logic CS4281");
30MODULE_LICENSE("GPL");
31MODULE_SUPPORTED_DEVICE("{{Cirrus Logic,CS4281}}");
32
33static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
34static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
35static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable switches */
36static bool dual_codec[SNDRV_CARDS]; /* dual codec */
37
38module_param_array(index, int, NULL, 0444);
39MODULE_PARM_DESC(index, "Index value for CS4281 soundcard.");
40module_param_array(id, charp, NULL, 0444);
41MODULE_PARM_DESC(id, "ID string for CS4281 soundcard.");
42module_param_array(enable, bool, NULL, 0444);
43MODULE_PARM_DESC(enable, "Enable CS4281 soundcard.");
44module_param_array(dual_codec, bool, NULL, 0444);
45MODULE_PARM_DESC(dual_codec, "Secondary Codec ID (0 = disabled).");
46
47/*
48 * Direct registers
49 */
50
51#define CS4281_BA0_SIZE 0x1000
52#define CS4281_BA1_SIZE 0x10000
53
54/*
55 * BA0 registers
56 */
57#define BA0_HISR 0x0000 /* Host Interrupt Status Register */
58#define BA0_HISR_INTENA (1<<31) /* Internal Interrupt Enable Bit */
59#define BA0_HISR_MIDI (1<<22) /* MIDI port interrupt */
60#define BA0_HISR_FIFOI (1<<20) /* FIFO polled interrupt */
61#define BA0_HISR_DMAI (1<<18) /* DMA interrupt (half or end) */
62#define BA0_HISR_FIFO(c) (1<<(12+(c))) /* FIFO channel interrupt */
63#define BA0_HISR_DMA(c) (1<<(8+(c))) /* DMA channel interrupt */
64#define BA0_HISR_GPPI (1<<5) /* General Purpose Input (Primary chip) */
65#define BA0_HISR_GPSI (1<<4) /* General Purpose Input (Secondary chip) */
66#define BA0_HISR_GP3I (1<<3) /* GPIO3 pin Interrupt */
67#define BA0_HISR_GP1I (1<<2) /* GPIO1 pin Interrupt */
68#define BA0_HISR_VUPI (1<<1) /* VOLUP pin Interrupt */
69#define BA0_HISR_VDNI (1<<0) /* VOLDN pin Interrupt */
70
71#define BA0_HICR 0x0008 /* Host Interrupt Control Register */
72#define BA0_HICR_CHGM (1<<1) /* INTENA Change Mask */
73#define BA0_HICR_IEV (1<<0) /* INTENA Value */
74#define BA0_HICR_EOI (3<<0) /* End of Interrupt command */
75
76#define BA0_HIMR 0x000c /* Host Interrupt Mask Register */
77 /* Use same contants as for BA0_HISR */
78
79#define BA0_IIER 0x0010 /* ISA Interrupt Enable Register */
80
81#define BA0_HDSR0 0x00f0 /* Host DMA Engine 0 Status Register */
82#define BA0_HDSR1 0x00f4 /* Host DMA Engine 1 Status Register */
83#define BA0_HDSR2 0x00f8 /* Host DMA Engine 2 Status Register */
84#define BA0_HDSR3 0x00fc /* Host DMA Engine 3 Status Register */
85
86#define BA0_HDSR_CH1P (1<<25) /* Channel 1 Pending */
87#define BA0_HDSR_CH2P (1<<24) /* Channel 2 Pending */
88#define BA0_HDSR_DHTC (1<<17) /* DMA Half Terminal Count */
89#define BA0_HDSR_DTC (1<<16) /* DMA Terminal Count */
90#define BA0_HDSR_DRUN (1<<15) /* DMA Running */
91#define BA0_HDSR_RQ (1<<7) /* Pending Request */
92
93#define BA0_DCA0 0x0110 /* Host DMA Engine 0 Current Address */
94#define BA0_DCC0 0x0114 /* Host DMA Engine 0 Current Count */
95#define BA0_DBA0 0x0118 /* Host DMA Engine 0 Base Address */
96#define BA0_DBC0 0x011c /* Host DMA Engine 0 Base Count */
97#define BA0_DCA1 0x0120 /* Host DMA Engine 1 Current Address */
98#define BA0_DCC1 0x0124 /* Host DMA Engine 1 Current Count */
99#define BA0_DBA1 0x0128 /* Host DMA Engine 1 Base Address */
100#define BA0_DBC1 0x012c /* Host DMA Engine 1 Base Count */
101#define BA0_DCA2 0x0130 /* Host DMA Engine 2 Current Address */
102#define BA0_DCC2 0x0134 /* Host DMA Engine 2 Current Count */
103#define BA0_DBA2 0x0138 /* Host DMA Engine 2 Base Address */
104#define BA0_DBC2 0x013c /* Host DMA Engine 2 Base Count */
105#define BA0_DCA3 0x0140 /* Host DMA Engine 3 Current Address */
106#define BA0_DCC3 0x0144 /* Host DMA Engine 3 Current Count */
107#define BA0_DBA3 0x0148 /* Host DMA Engine 3 Base Address */
108#define BA0_DBC3 0x014c /* Host DMA Engine 3 Base Count */
109#define BA0_DMR0 0x0150 /* Host DMA Engine 0 Mode */
110#define BA0_DCR0 0x0154 /* Host DMA Engine 0 Command */
111#define BA0_DMR1 0x0158 /* Host DMA Engine 1 Mode */
112#define BA0_DCR1 0x015c /* Host DMA Engine 1 Command */
113#define BA0_DMR2 0x0160 /* Host DMA Engine 2 Mode */
114#define BA0_DCR2 0x0164 /* Host DMA Engine 2 Command */
115#define BA0_DMR3 0x0168 /* Host DMA Engine 3 Mode */
116#define BA0_DCR3 0x016c /* Host DMA Engine 3 Command */
117
118#define BA0_DMR_DMA (1<<29) /* Enable DMA mode */
119#define BA0_DMR_POLL (1<<28) /* Enable poll mode */
120#define BA0_DMR_TBC (1<<25) /* Transfer By Channel */
121#define BA0_DMR_CBC (1<<24) /* Count By Channel (0 = frame resolution) */
122#define BA0_DMR_SWAPC (1<<22) /* Swap Left/Right Channels */
123#define BA0_DMR_SIZE20 (1<<20) /* Sample is 20-bit */
124#define BA0_DMR_USIGN (1<<19) /* Unsigned */
125#define BA0_DMR_BEND (1<<18) /* Big Endian */
126#define BA0_DMR_MONO (1<<17) /* Mono */
127#define BA0_DMR_SIZE8 (1<<16) /* Sample is 8-bit */
128#define BA0_DMR_TYPE_DEMAND (0<<6)
129#define BA0_DMR_TYPE_SINGLE (1<<6)
130#define BA0_DMR_TYPE_BLOCK (2<<6)
131#define BA0_DMR_TYPE_CASCADE (3<<6) /* Not supported */
132#define BA0_DMR_DEC (1<<5) /* Access Increment (0) or Decrement (1) */
133#define BA0_DMR_AUTO (1<<4) /* Auto-Initialize */
134#define BA0_DMR_TR_VERIFY (0<<2) /* Verify Transfer */
135#define BA0_DMR_TR_WRITE (1<<2) /* Write Transfer */
136#define BA0_DMR_TR_READ (2<<2) /* Read Transfer */
137
138#define BA0_DCR_HTCIE (1<<17) /* Half Terminal Count Interrupt */
139#define BA0_DCR_TCIE (1<<16) /* Terminal Count Interrupt */
140#define BA0_DCR_MSK (1<<0) /* DMA Mask bit */
141
142#define BA0_FCR0 0x0180 /* FIFO Control 0 */
143#define BA0_FCR1 0x0184 /* FIFO Control 1 */
144#define BA0_FCR2 0x0188 /* FIFO Control 2 */
145#define BA0_FCR3 0x018c /* FIFO Control 3 */
146
147#define BA0_FCR_FEN (1<<31) /* FIFO Enable bit */
148#define BA0_FCR_DACZ (1<<30) /* DAC Zero */
149#define BA0_FCR_PSH (1<<29) /* Previous Sample Hold */
150#define BA0_FCR_RS(x) (((x)&0x1f)<<24) /* Right Slot Mapping */
151#define BA0_FCR_LS(x) (((x)&0x1f)<<16) /* Left Slot Mapping */
152#define BA0_FCR_SZ(x) (((x)&0x7f)<<8) /* FIFO buffer size (in samples) */
153#define BA0_FCR_OF(x) (((x)&0x7f)<<0) /* FIFO starting offset (in samples) */
154
155#define BA0_FPDR0 0x0190 /* FIFO Polled Data 0 */
156#define BA0_FPDR1 0x0194 /* FIFO Polled Data 1 */
157#define BA0_FPDR2 0x0198 /* FIFO Polled Data 2 */
158#define BA0_FPDR3 0x019c /* FIFO Polled Data 3 */
159
160#define BA0_FCHS 0x020c /* FIFO Channel Status */
161#define BA0_FCHS_RCO(x) (1<<(7+(((x)&3)<<3))) /* Right Channel Out */
162#define BA0_FCHS_LCO(x) (1<<(6+(((x)&3)<<3))) /* Left Channel Out */
163#define BA0_FCHS_MRP(x) (1<<(5+(((x)&3)<<3))) /* Move Read Pointer */
164#define BA0_FCHS_FE(x) (1<<(4+(((x)&3)<<3))) /* FIFO Empty */
165#define BA0_FCHS_FF(x) (1<<(3+(((x)&3)<<3))) /* FIFO Full */
166#define BA0_FCHS_IOR(x) (1<<(2+(((x)&3)<<3))) /* Internal Overrun Flag */
167#define BA0_FCHS_RCI(x) (1<<(1+(((x)&3)<<3))) /* Right Channel In */
168#define BA0_FCHS_LCI(x) (1<<(0+(((x)&3)<<3))) /* Left Channel In */
169
170#define BA0_FSIC0 0x0210 /* FIFO Status and Interrupt Control 0 */
171#define BA0_FSIC1 0x0214 /* FIFO Status and Interrupt Control 1 */
172#define BA0_FSIC2 0x0218 /* FIFO Status and Interrupt Control 2 */
173#define BA0_FSIC3 0x021c /* FIFO Status and Interrupt Control 3 */
174
175#define BA0_FSIC_FIC(x) (((x)&0x7f)<<24) /* FIFO Interrupt Count */
176#define BA0_FSIC_FORIE (1<<23) /* FIFO OverRun Interrupt Enable */
177#define BA0_FSIC_FURIE (1<<22) /* FIFO UnderRun Interrupt Enable */
178#define BA0_FSIC_FSCIE (1<<16) /* FIFO Sample Count Interrupt Enable */
179#define BA0_FSIC_FSC(x) (((x)&0x7f)<<8) /* FIFO Sample Count */
180#define BA0_FSIC_FOR (1<<7) /* FIFO OverRun */
181#define BA0_FSIC_FUR (1<<6) /* FIFO UnderRun */
182#define BA0_FSIC_FSCR (1<<0) /* FIFO Sample Count Reached */
183
184#define BA0_PMCS 0x0344 /* Power Management Control/Status */
185#define BA0_CWPR 0x03e0 /* Configuration Write Protect */
186
187#define BA0_EPPMC 0x03e4 /* Extended PCI Power Management Control */
188#define BA0_EPPMC_FPDN (1<<14) /* Full Power DowN */
189
190#define BA0_GPIOR 0x03e8 /* GPIO Pin Interface Register */
191
192#define BA0_SPMC 0x03ec /* Serial Port Power Management Control (& ASDIN2 enable) */
193#define BA0_SPMC_GIPPEN (1<<15) /* GP INT Primary PME# Enable */
194#define BA0_SPMC_GISPEN (1<<14) /* GP INT Secondary PME# Enable */
195#define BA0_SPMC_EESPD (1<<9) /* EEPROM Serial Port Disable */
196#define BA0_SPMC_ASDI2E (1<<8) /* ASDIN2 Enable */
197#define BA0_SPMC_ASDO (1<<7) /* Asynchronous ASDOUT Assertion */
198#define BA0_SPMC_WUP2 (1<<3) /* Wakeup for Secondary Input */
199#define BA0_SPMC_WUP1 (1<<2) /* Wakeup for Primary Input */
200#define BA0_SPMC_ASYNC (1<<1) /* Asynchronous ASYNC Assertion */
201#define BA0_SPMC_RSTN (1<<0) /* Reset Not! */
202
203#define BA0_CFLR 0x03f0 /* Configuration Load Register (EEPROM or BIOS) */
204#define BA0_CFLR_DEFAULT 0x00000001 /* CFLR must be in AC97 link mode */
205#define BA0_IISR 0x03f4 /* ISA Interrupt Select */
206#define BA0_TMS 0x03f8 /* Test Register */
207#define BA0_SSVID 0x03fc /* Subsystem ID register */
208
209#define BA0_CLKCR1 0x0400 /* Clock Control Register 1 */
210#define BA0_CLKCR1_CLKON (1<<25) /* Read Only */
211#define BA0_CLKCR1_DLLRDY (1<<24) /* DLL Ready */
212#define BA0_CLKCR1_DLLOS (1<<6) /* DLL Output Select */
213#define BA0_CLKCR1_SWCE (1<<5) /* Clock Enable */
214#define BA0_CLKCR1_DLLP (1<<4) /* DLL PowerUp */
215#define BA0_CLKCR1_DLLSS (((x)&3)<<3) /* DLL Source Select */
216
217#define BA0_FRR 0x0410 /* Feature Reporting Register */
218#define BA0_SLT12O 0x041c /* Slot 12 GPIO Output Register for AC-Link */
219
220#define BA0_SERMC 0x0420 /* Serial Port Master Control */
221#define BA0_SERMC_FCRN (1<<27) /* Force Codec Ready Not */
222#define BA0_SERMC_ODSEN2 (1<<25) /* On-Demand Support Enable ASDIN2 */
223#define BA0_SERMC_ODSEN1 (1<<24) /* On-Demand Support Enable ASDIN1 */
224#define BA0_SERMC_SXLB (1<<21) /* ASDIN2 to ASDOUT Loopback */
225#define BA0_SERMC_SLB (1<<20) /* ASDOUT to ASDIN2 Loopback */
226#define BA0_SERMC_LOVF (1<<19) /* Loopback Output Valid Frame bit */
227#define BA0_SERMC_TCID(x) (((x)&3)<<16) /* Target Secondary Codec ID */
228#define BA0_SERMC_PXLB (5<<1) /* Primary Port External Loopback */
229#define BA0_SERMC_PLB (4<<1) /* Primary Port Internal Loopback */
230#define BA0_SERMC_PTC (7<<1) /* Port Timing Configuration */
231#define BA0_SERMC_PTC_AC97 (1<<1) /* AC97 mode */
232#define BA0_SERMC_MSPE (1<<0) /* Master Serial Port Enable */
233
234#define BA0_SERC1 0x0428 /* Serial Port Configuration 1 */
235#define BA0_SERC1_SO1F(x) (((x)&7)>>1) /* Primary Output Port Format */
236#define BA0_SERC1_AC97 (1<<1)
237#define BA0_SERC1_SO1EN (1<<0) /* Primary Output Port Enable */
238
239#define BA0_SERC2 0x042c /* Serial Port Configuration 2 */
240#define BA0_SERC2_SI1F(x) (((x)&7)>>1) /* Primary Input Port Format */
241#define BA0_SERC2_AC97 (1<<1)
242#define BA0_SERC2_SI1EN (1<<0) /* Primary Input Port Enable */
243
244#define BA0_SLT12M 0x045c /* Slot 12 Monitor Register for Primary AC-Link */
245
246#define BA0_ACCTL 0x0460 /* AC'97 Control */
247#define BA0_ACCTL_TC (1<<6) /* Target Codec */
248#define BA0_ACCTL_CRW (1<<4) /* 0=Write, 1=Read Command */
249#define BA0_ACCTL_DCV (1<<3) /* Dynamic Command Valid */
250#define BA0_ACCTL_VFRM (1<<2) /* Valid Frame */
251#define BA0_ACCTL_ESYN (1<<1) /* Enable Sync */
252
253#define BA0_ACSTS 0x0464 /* AC'97 Status */
254#define BA0_ACSTS_VSTS (1<<1) /* Valid Status */
255#define BA0_ACSTS_CRDY (1<<0) /* Codec Ready */
256
257#define BA0_ACOSV 0x0468 /* AC'97 Output Slot Valid */
258#define BA0_ACOSV_SLV(x) (1<<((x)-3))
259
260#define BA0_ACCAD 0x046c /* AC'97 Command Address */
261#define BA0_ACCDA 0x0470 /* AC'97 Command Data */
262
263#define BA0_ACISV 0x0474 /* AC'97 Input Slot Valid */
264#define BA0_ACISV_SLV(x) (1<<((x)-3))
265
266#define BA0_ACSAD 0x0478 /* AC'97 Status Address */
267#define BA0_ACSDA 0x047c /* AC'97 Status Data */
268#define BA0_JSPT 0x0480 /* Joystick poll/trigger */
269#define BA0_JSCTL 0x0484 /* Joystick control */
270#define BA0_JSC1 0x0488 /* Joystick control */
271#define BA0_JSC2 0x048c /* Joystick control */
272#define BA0_JSIO 0x04a0
273
274#define BA0_MIDCR 0x0490 /* MIDI Control */
275#define BA0_MIDCR_MRST (1<<5) /* Reset MIDI Interface */
276#define BA0_MIDCR_MLB (1<<4) /* MIDI Loop Back Enable */
277#define BA0_MIDCR_TIE (1<<3) /* MIDI Transmuit Interrupt Enable */
278#define BA0_MIDCR_RIE (1<<2) /* MIDI Receive Interrupt Enable */
279#define BA0_MIDCR_RXE (1<<1) /* MIDI Receive Enable */
280#define BA0_MIDCR_TXE (1<<0) /* MIDI Transmit Enable */
281
282#define BA0_MIDCMD 0x0494 /* MIDI Command (wo) */
283
284#define BA0_MIDSR 0x0494 /* MIDI Status (ro) */
285#define BA0_MIDSR_RDA (1<<15) /* Sticky bit (RBE 1->0) */
286#define BA0_MIDSR_TBE (1<<14) /* Sticky bit (TBF 0->1) */
287#define BA0_MIDSR_RBE (1<<7) /* Receive Buffer Empty */
288#define BA0_MIDSR_TBF (1<<6) /* Transmit Buffer Full */
289
290#define BA0_MIDWP 0x0498 /* MIDI Write */
291#define BA0_MIDRP 0x049c /* MIDI Read (ro) */
292
293#define BA0_AODSD1 0x04a8 /* AC'97 On-Demand Slot Disable for primary link (ro) */
294#define BA0_AODSD1_NDS(x) (1<<((x)-3))
295
296#define BA0_AODSD2 0x04ac /* AC'97 On-Demand Slot Disable for secondary link (ro) */
297#define BA0_AODSD2_NDS(x) (1<<((x)-3))
298
299#define BA0_CFGI 0x04b0 /* Configure Interface (EEPROM interface) */
300#define BA0_SLT12M2 0x04dc /* Slot 12 Monitor Register 2 for secondary AC-link */
301#define BA0_ACSTS2 0x04e4 /* AC'97 Status Register 2 */
302#define BA0_ACISV2 0x04f4 /* AC'97 Input Slot Valid Register 2 */
303#define BA0_ACSAD2 0x04f8 /* AC'97 Status Address Register 2 */
304#define BA0_ACSDA2 0x04fc /* AC'97 Status Data Register 2 */
305#define BA0_FMSR 0x0730 /* FM Synthesis Status (ro) */
306#define BA0_B0AP 0x0730 /* FM Bank 0 Address Port (wo) */
307#define BA0_FMDP 0x0734 /* FM Data Port */
308#define BA0_B1AP 0x0738 /* FM Bank 1 Address Port */
309#define BA0_B1DP 0x073c /* FM Bank 1 Data Port */
310
311#define BA0_SSPM 0x0740 /* Sound System Power Management */
312#define BA0_SSPM_MIXEN (1<<6) /* Playback SRC + FM/Wavetable MIX */
313#define BA0_SSPM_CSRCEN (1<<5) /* Capture Sample Rate Converter Enable */
314#define BA0_SSPM_PSRCEN (1<<4) /* Playback Sample Rate Converter Enable */
315#define BA0_SSPM_JSEN (1<<3) /* Joystick Enable */
316#define BA0_SSPM_ACLEN (1<<2) /* Serial Port Engine and AC-Link Enable */
317#define BA0_SSPM_FMEN (1<<1) /* FM Synthesis Block Enable */
318
319#define BA0_DACSR 0x0744 /* DAC Sample Rate - Playback SRC */
320#define BA0_ADCSR 0x0748 /* ADC Sample Rate - Capture SRC */
321
322#define BA0_SSCR 0x074c /* Sound System Control Register */
323#define BA0_SSCR_HVS1 (1<<23) /* Hardwave Volume Step (0=1,1=2) */
324#define BA0_SSCR_MVCS (1<<19) /* Master Volume Codec Select */
325#define BA0_SSCR_MVLD (1<<18) /* Master Volume Line Out Disable */
326#define BA0_SSCR_MVAD (1<<17) /* Master Volume Alternate Out Disable */
327#define BA0_SSCR_MVMD (1<<16) /* Master Volume Mono Out Disable */
328#define BA0_SSCR_XLPSRC (1<<8) /* External SRC Loopback Mode */
329#define BA0_SSCR_LPSRC (1<<7) /* SRC Loopback Mode */
330#define BA0_SSCR_CDTX (1<<5) /* CD Transfer Data */
331#define BA0_SSCR_HVC (1<<3) /* Harware Volume Control Enable */
332
333#define BA0_FMLVC 0x0754 /* FM Synthesis Left Volume Control */
334#define BA0_FMRVC 0x0758 /* FM Synthesis Right Volume Control */
335#define BA0_SRCSA 0x075c /* SRC Slot Assignments */
336#define BA0_PPLVC 0x0760 /* PCM Playback Left Volume Control */
337#define BA0_PPRVC 0x0764 /* PCM Playback Right Volume Control */
338#define BA0_PASR 0x0768 /* playback sample rate */
339#define BA0_CASR 0x076C /* capture sample rate */
340
341/* Source Slot Numbers - Playback */
342#define SRCSLOT_LEFT_PCM_PLAYBACK 0
343#define SRCSLOT_RIGHT_PCM_PLAYBACK 1
344#define SRCSLOT_PHONE_LINE_1_DAC 2
345#define SRCSLOT_CENTER_PCM_PLAYBACK 3
346#define SRCSLOT_LEFT_SURROUND_PCM_PLAYBACK 4
347#define SRCSLOT_RIGHT_SURROUND_PCM_PLAYBACK 5
348#define SRCSLOT_LFE_PCM_PLAYBACK 6
349#define SRCSLOT_PHONE_LINE_2_DAC 7
350#define SRCSLOT_HEADSET_DAC 8
351#define SRCSLOT_LEFT_WT 29 /* invalid for BA0_SRCSA */
352#define SRCSLOT_RIGHT_WT 30 /* invalid for BA0_SRCSA */
353
354/* Source Slot Numbers - Capture */
355#define SRCSLOT_LEFT_PCM_RECORD 10
356#define SRCSLOT_RIGHT_PCM_RECORD 11
357#define SRCSLOT_PHONE_LINE_1_ADC 12
358#define SRCSLOT_MIC_ADC 13
359#define SRCSLOT_PHONE_LINE_2_ADC 17
360#define SRCSLOT_HEADSET_ADC 18
361#define SRCSLOT_SECONDARY_LEFT_PCM_RECORD 20
362#define SRCSLOT_SECONDARY_RIGHT_PCM_RECORD 21
363#define SRCSLOT_SECONDARY_PHONE_LINE_1_ADC 22
364#define SRCSLOT_SECONDARY_MIC_ADC 23
365#define SRCSLOT_SECONDARY_PHONE_LINE_2_ADC 27
366#define SRCSLOT_SECONDARY_HEADSET_ADC 28
367
368/* Source Slot Numbers - Others */
369#define SRCSLOT_POWER_DOWN 31
370
371/* MIDI modes */
372#define CS4281_MODE_OUTPUT (1<<0)
373#define CS4281_MODE_INPUT (1<<1)
374
375/* joystick bits */
376/* Bits for JSPT */
377#define JSPT_CAX 0x00000001
378#define JSPT_CAY 0x00000002
379#define JSPT_CBX 0x00000004
380#define JSPT_CBY 0x00000008
381#define JSPT_BA1 0x00000010
382#define JSPT_BA2 0x00000020
383#define JSPT_BB1 0x00000040
384#define JSPT_BB2 0x00000080
385
386/* Bits for JSCTL */
387#define JSCTL_SP_MASK 0x00000003
388#define JSCTL_SP_SLOW 0x00000000
389#define JSCTL_SP_MEDIUM_SLOW 0x00000001
390#define JSCTL_SP_MEDIUM_FAST 0x00000002
391#define JSCTL_SP_FAST 0x00000003
392#define JSCTL_ARE 0x00000004
393
394/* Data register pairs masks */
395#define JSC1_Y1V_MASK 0x0000FFFF
396#define JSC1_X1V_MASK 0xFFFF0000
397#define JSC1_Y1V_SHIFT 0
398#define JSC1_X1V_SHIFT 16
399#define JSC2_Y2V_MASK 0x0000FFFF
400#define JSC2_X2V_MASK 0xFFFF0000
401#define JSC2_Y2V_SHIFT 0
402#define JSC2_X2V_SHIFT 16
403
404/* JS GPIO */
405#define JSIO_DAX 0x00000001
406#define JSIO_DAY 0x00000002
407#define JSIO_DBX 0x00000004
408#define JSIO_DBY 0x00000008
409#define JSIO_AXOE 0x00000010
410#define JSIO_AYOE 0x00000020
411#define JSIO_BXOE 0x00000040
412#define JSIO_BYOE 0x00000080
413
414/*
415 *
416 */
417
418struct cs4281_dma {
419 struct snd_pcm_substream *substream;
420 unsigned int regDBA; /* offset to DBA register */
421 unsigned int regDCA; /* offset to DCA register */
422 unsigned int regDBC; /* offset to DBC register */
423 unsigned int regDCC; /* offset to DCC register */
424 unsigned int regDMR; /* offset to DMR register */
425 unsigned int regDCR; /* offset to DCR register */
426 unsigned int regHDSR; /* offset to HDSR register */
427 unsigned int regFCR; /* offset to FCR register */
428 unsigned int regFSIC; /* offset to FSIC register */
429 unsigned int valDMR; /* DMA mode */
430 unsigned int valDCR; /* DMA command */
431 unsigned int valFCR; /* FIFO control */
432 unsigned int fifo_offset; /* FIFO offset within BA1 */
433 unsigned char left_slot; /* FIFO left slot */
434 unsigned char right_slot; /* FIFO right slot */
435 int frag; /* period number */
436};
437
438#define SUSPEND_REGISTERS 20
439
440struct cs4281 {
441 int irq;
442
443 void __iomem *ba0; /* virtual (accessible) address */
444 void __iomem *ba1; /* virtual (accessible) address */
445 unsigned long ba0_addr;
446 unsigned long ba1_addr;
447
448 int dual_codec;
449
450 struct snd_ac97_bus *ac97_bus;
451 struct snd_ac97 *ac97;
452 struct snd_ac97 *ac97_secondary;
453
454 struct pci_dev *pci;
455 struct snd_card *card;
456 struct snd_pcm *pcm;
457 struct snd_rawmidi *rmidi;
458 struct snd_rawmidi_substream *midi_input;
459 struct snd_rawmidi_substream *midi_output;
460
461 struct cs4281_dma dma[4];
462
463 unsigned char src_left_play_slot;
464 unsigned char src_right_play_slot;
465 unsigned char src_left_rec_slot;
466 unsigned char src_right_rec_slot;
467
468 unsigned int spurious_dhtc_irq;
469 unsigned int spurious_dtc_irq;
470
471 spinlock_t reg_lock;
472 unsigned int midcr;
473 unsigned int uartm;
474
475 struct gameport *gameport;
476
477#ifdef CONFIG_PM_SLEEP
478 u32 suspend_regs[SUSPEND_REGISTERS];
479#endif
480
481};
482
483static irqreturn_t snd_cs4281_interrupt(int irq, void *dev_id);
484
485static const struct pci_device_id snd_cs4281_ids[] = {
486 { PCI_VDEVICE(CIRRUS, 0x6005), 0, }, /* CS4281 */
487 { 0, }
488};
489
490MODULE_DEVICE_TABLE(pci, snd_cs4281_ids);
491
492/*
493 * constants
494 */
495
496#define CS4281_FIFO_SIZE 32
497
498/*
499 * common I/O routines
500 */
501
502static inline void snd_cs4281_pokeBA0(struct cs4281 *chip, unsigned long offset,
503 unsigned int val)
504{
505 writel(val, chip->ba0 + offset);
506}
507
508static inline unsigned int snd_cs4281_peekBA0(struct cs4281 *chip, unsigned long offset)
509{
510 return readl(chip->ba0 + offset);
511}
512
513static void snd_cs4281_ac97_write(struct snd_ac97 *ac97,
514 unsigned short reg, unsigned short val)
515{
516 /*
517 * 1. Write ACCAD = Command Address Register = 46Ch for AC97 register address
518 * 2. Write ACCDA = Command Data Register = 470h for data to write to AC97
519 * 3. Write ACCTL = Control Register = 460h for initiating the write
520 * 4. Read ACCTL = 460h, DCV should be reset by now and 460h = 07h
521 * 5. if DCV not cleared, break and return error
522 */
523 struct cs4281 *chip = ac97->private_data;
524 int count;
525
526 /*
527 * Setup the AC97 control registers on the CS461x to send the
528 * appropriate command to the AC97 to perform the read.
529 * ACCAD = Command Address Register = 46Ch
530 * ACCDA = Command Data Register = 470h
531 * ACCTL = Control Register = 460h
532 * set DCV - will clear when process completed
533 * reset CRW - Write command
534 * set VFRM - valid frame enabled
535 * set ESYN - ASYNC generation enabled
536 * set RSTN - ARST# inactive, AC97 codec not reset
537 */
538 snd_cs4281_pokeBA0(chip, BA0_ACCAD, reg);
539 snd_cs4281_pokeBA0(chip, BA0_ACCDA, val);
540 snd_cs4281_pokeBA0(chip, BA0_ACCTL, BA0_ACCTL_DCV | BA0_ACCTL_VFRM |
541 BA0_ACCTL_ESYN | (ac97->num ? BA0_ACCTL_TC : 0));
542 for (count = 0; count < 2000; count++) {
543 /*
544 * First, we want to wait for a short time.
545 */
546 udelay(10);
547 /*
548 * Now, check to see if the write has completed.
549 * ACCTL = 460h, DCV should be reset by now and 460h = 07h
550 */
551 if (!(snd_cs4281_peekBA0(chip, BA0_ACCTL) & BA0_ACCTL_DCV)) {
552 return;
553 }
554 }
555 dev_err(chip->card->dev,
556 "AC'97 write problem, reg = 0x%x, val = 0x%x\n", reg, val);
557}
558
559static unsigned short snd_cs4281_ac97_read(struct snd_ac97 *ac97,
560 unsigned short reg)
561{
562 struct cs4281 *chip = ac97->private_data;
563 int count;
564 unsigned short result;
565 // FIXME: volatile is necessary in the following due to a bug of
566 // some gcc versions
567 volatile int ac97_num = ((volatile struct snd_ac97 *)ac97)->num;
568
569 /*
570 * 1. Write ACCAD = Command Address Register = 46Ch for AC97 register address
571 * 2. Write ACCDA = Command Data Register = 470h for data to write to AC97
572 * 3. Write ACCTL = Control Register = 460h for initiating the write
573 * 4. Read ACCTL = 460h, DCV should be reset by now and 460h = 17h
574 * 5. if DCV not cleared, break and return error
575 * 6. Read ACSTS = Status Register = 464h, check VSTS bit
576 */
577
578 snd_cs4281_peekBA0(chip, ac97_num ? BA0_ACSDA2 : BA0_ACSDA);
579
580 /*
581 * Setup the AC97 control registers on the CS461x to send the
582 * appropriate command to the AC97 to perform the read.
583 * ACCAD = Command Address Register = 46Ch
584 * ACCDA = Command Data Register = 470h
585 * ACCTL = Control Register = 460h
586 * set DCV - will clear when process completed
587 * set CRW - Read command
588 * set VFRM - valid frame enabled
589 * set ESYN - ASYNC generation enabled
590 * set RSTN - ARST# inactive, AC97 codec not reset
591 */
592
593 snd_cs4281_pokeBA0(chip, BA0_ACCAD, reg);
594 snd_cs4281_pokeBA0(chip, BA0_ACCDA, 0);
595 snd_cs4281_pokeBA0(chip, BA0_ACCTL, BA0_ACCTL_DCV | BA0_ACCTL_CRW |
596 BA0_ACCTL_VFRM | BA0_ACCTL_ESYN |
597 (ac97_num ? BA0_ACCTL_TC : 0));
598
599
600 /*
601 * Wait for the read to occur.
602 */
603 for (count = 0; count < 500; count++) {
604 /*
605 * First, we want to wait for a short time.
606 */
607 udelay(10);
608 /*
609 * Now, check to see if the read has completed.
610 * ACCTL = 460h, DCV should be reset by now and 460h = 17h
611 */
612 if (!(snd_cs4281_peekBA0(chip, BA0_ACCTL) & BA0_ACCTL_DCV))
613 goto __ok1;
614 }
615
616 dev_err(chip->card->dev,
617 "AC'97 read problem (ACCTL_DCV), reg = 0x%x\n", reg);
618 result = 0xffff;
619 goto __end;
620
621 __ok1:
622 /*
623 * Wait for the valid status bit to go active.
624 */
625 for (count = 0; count < 100; count++) {
626 /*
627 * Read the AC97 status register.
628 * ACSTS = Status Register = 464h
629 * VSTS - Valid Status
630 */
631 if (snd_cs4281_peekBA0(chip, ac97_num ? BA0_ACSTS2 : BA0_ACSTS) & BA0_ACSTS_VSTS)
632 goto __ok2;
633 udelay(10);
634 }
635
636 dev_err(chip->card->dev,
637 "AC'97 read problem (ACSTS_VSTS), reg = 0x%x\n", reg);
638 result = 0xffff;
639 goto __end;
640
641 __ok2:
642 /*
643 * Read the data returned from the AC97 register.
644 * ACSDA = Status Data Register = 474h
645 */
646 result = snd_cs4281_peekBA0(chip, ac97_num ? BA0_ACSDA2 : BA0_ACSDA);
647
648 __end:
649 return result;
650}
651
652/*
653 * PCM part
654 */
655
656static int snd_cs4281_trigger(struct snd_pcm_substream *substream, int cmd)
657{
658 struct cs4281_dma *dma = substream->runtime->private_data;
659 struct cs4281 *chip = snd_pcm_substream_chip(substream);
660
661 spin_lock(&chip->reg_lock);
662 switch (cmd) {
663 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
664 dma->valDCR |= BA0_DCR_MSK;
665 dma->valFCR |= BA0_FCR_FEN;
666 break;
667 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
668 dma->valDCR &= ~BA0_DCR_MSK;
669 dma->valFCR &= ~BA0_FCR_FEN;
670 break;
671 case SNDRV_PCM_TRIGGER_START:
672 case SNDRV_PCM_TRIGGER_RESUME:
673 snd_cs4281_pokeBA0(chip, dma->regDMR, dma->valDMR & ~BA0_DMR_DMA);
674 dma->valDMR |= BA0_DMR_DMA;
675 dma->valDCR &= ~BA0_DCR_MSK;
676 dma->valFCR |= BA0_FCR_FEN;
677 break;
678 case SNDRV_PCM_TRIGGER_STOP:
679 case SNDRV_PCM_TRIGGER_SUSPEND:
680 dma->valDMR &= ~(BA0_DMR_DMA|BA0_DMR_POLL);
681 dma->valDCR |= BA0_DCR_MSK;
682 dma->valFCR &= ~BA0_FCR_FEN;
683 /* Leave wave playback FIFO enabled for FM */
684 if (dma->regFCR != BA0_FCR0)
685 dma->valFCR &= ~BA0_FCR_FEN;
686 break;
687 default:
688 spin_unlock(&chip->reg_lock);
689 return -EINVAL;
690 }
691 snd_cs4281_pokeBA0(chip, dma->regDMR, dma->valDMR);
692 snd_cs4281_pokeBA0(chip, dma->regFCR, dma->valFCR);
693 snd_cs4281_pokeBA0(chip, dma->regDCR, dma->valDCR);
694 spin_unlock(&chip->reg_lock);
695 return 0;
696}
697
698static unsigned int snd_cs4281_rate(unsigned int rate, unsigned int *real_rate)
699{
700 unsigned int val;
701
702 if (real_rate)
703 *real_rate = rate;
704 /* special "hardcoded" rates */
705 switch (rate) {
706 case 8000: return 5;
707 case 11025: return 4;
708 case 16000: return 3;
709 case 22050: return 2;
710 case 44100: return 1;
711 case 48000: return 0;
712 default:
713 break;
714 }
715 val = 1536000 / rate;
716 if (real_rate)
717 *real_rate = 1536000 / val;
718 return val;
719}
720
721static void snd_cs4281_mode(struct cs4281 *chip, struct cs4281_dma *dma,
722 struct snd_pcm_runtime *runtime,
723 int capture, int src)
724{
725 int rec_mono;
726
727 dma->valDMR = BA0_DMR_TYPE_SINGLE | BA0_DMR_AUTO |
728 (capture ? BA0_DMR_TR_WRITE : BA0_DMR_TR_READ);
729 if (runtime->channels == 1)
730 dma->valDMR |= BA0_DMR_MONO;
731 if (snd_pcm_format_unsigned(runtime->format) > 0)
732 dma->valDMR |= BA0_DMR_USIGN;
733 if (snd_pcm_format_big_endian(runtime->format) > 0)
734 dma->valDMR |= BA0_DMR_BEND;
735 switch (snd_pcm_format_width(runtime->format)) {
736 case 8: dma->valDMR |= BA0_DMR_SIZE8;
737 if (runtime->channels == 1)
738 dma->valDMR |= BA0_DMR_SWAPC;
739 break;
740 case 32: dma->valDMR |= BA0_DMR_SIZE20; break;
741 }
742 dma->frag = 0; /* for workaround */
743 dma->valDCR = BA0_DCR_TCIE | BA0_DCR_MSK;
744 if (runtime->buffer_size != runtime->period_size)
745 dma->valDCR |= BA0_DCR_HTCIE;
746 /* Initialize DMA */
747 snd_cs4281_pokeBA0(chip, dma->regDBA, runtime->dma_addr);
748 snd_cs4281_pokeBA0(chip, dma->regDBC, runtime->buffer_size - 1);
749 rec_mono = (chip->dma[1].valDMR & BA0_DMR_MONO) == BA0_DMR_MONO;
750 snd_cs4281_pokeBA0(chip, BA0_SRCSA, (chip->src_left_play_slot << 0) |
751 (chip->src_right_play_slot << 8) |
752 (chip->src_left_rec_slot << 16) |
753 ((rec_mono ? 31 : chip->src_right_rec_slot) << 24));
754 if (!src)
755 goto __skip_src;
756 if (!capture) {
757 if (dma->left_slot == chip->src_left_play_slot) {
758 unsigned int val = snd_cs4281_rate(runtime->rate, NULL);
759 snd_BUG_ON(dma->right_slot != chip->src_right_play_slot);
760 snd_cs4281_pokeBA0(chip, BA0_DACSR, val);
761 }
762 } else {
763 if (dma->left_slot == chip->src_left_rec_slot) {
764 unsigned int val = snd_cs4281_rate(runtime->rate, NULL);
765 snd_BUG_ON(dma->right_slot != chip->src_right_rec_slot);
766 snd_cs4281_pokeBA0(chip, BA0_ADCSR, val);
767 }
768 }
769 __skip_src:
770 /* Deactivate wave playback FIFO before changing slot assignments */
771 if (dma->regFCR == BA0_FCR0)
772 snd_cs4281_pokeBA0(chip, dma->regFCR, snd_cs4281_peekBA0(chip, dma->regFCR) & ~BA0_FCR_FEN);
773 /* Initialize FIFO */
774 dma->valFCR = BA0_FCR_LS(dma->left_slot) |
775 BA0_FCR_RS(capture && (dma->valDMR & BA0_DMR_MONO) ? 31 : dma->right_slot) |
776 BA0_FCR_SZ(CS4281_FIFO_SIZE) |
777 BA0_FCR_OF(dma->fifo_offset);
778 snd_cs4281_pokeBA0(chip, dma->regFCR, dma->valFCR | (capture ? BA0_FCR_PSH : 0));
779 /* Activate FIFO again for FM playback */
780 if (dma->regFCR == BA0_FCR0)
781 snd_cs4281_pokeBA0(chip, dma->regFCR, dma->valFCR | BA0_FCR_FEN);
782 /* Clear FIFO Status and Interrupt Control Register */
783 snd_cs4281_pokeBA0(chip, dma->regFSIC, 0);
784}
785
786static int snd_cs4281_playback_prepare(struct snd_pcm_substream *substream)
787{
788 struct snd_pcm_runtime *runtime = substream->runtime;
789 struct cs4281_dma *dma = runtime->private_data;
790 struct cs4281 *chip = snd_pcm_substream_chip(substream);
791
792 spin_lock_irq(&chip->reg_lock);
793 snd_cs4281_mode(chip, dma, runtime, 0, 1);
794 spin_unlock_irq(&chip->reg_lock);
795 return 0;
796}
797
798static int snd_cs4281_capture_prepare(struct snd_pcm_substream *substream)
799{
800 struct snd_pcm_runtime *runtime = substream->runtime;
801 struct cs4281_dma *dma = runtime->private_data;
802 struct cs4281 *chip = snd_pcm_substream_chip(substream);
803
804 spin_lock_irq(&chip->reg_lock);
805 snd_cs4281_mode(chip, dma, runtime, 1, 1);
806 spin_unlock_irq(&chip->reg_lock);
807 return 0;
808}
809
810static snd_pcm_uframes_t snd_cs4281_pointer(struct snd_pcm_substream *substream)
811{
812 struct snd_pcm_runtime *runtime = substream->runtime;
813 struct cs4281_dma *dma = runtime->private_data;
814 struct cs4281 *chip = snd_pcm_substream_chip(substream);
815
816 /*
817 dev_dbg(chip->card->dev,
818 "DCC = 0x%x, buffer_size = 0x%x, jiffies = %li\n",
819 snd_cs4281_peekBA0(chip, dma->regDCC), runtime->buffer_size,
820 jiffies);
821 */
822 return runtime->buffer_size -
823 snd_cs4281_peekBA0(chip, dma->regDCC) - 1;
824}
825
826static const struct snd_pcm_hardware snd_cs4281_playback =
827{
828 .info = SNDRV_PCM_INFO_MMAP |
829 SNDRV_PCM_INFO_INTERLEAVED |
830 SNDRV_PCM_INFO_MMAP_VALID |
831 SNDRV_PCM_INFO_PAUSE |
832 SNDRV_PCM_INFO_RESUME,
833 .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S8 |
834 SNDRV_PCM_FMTBIT_U16_LE | SNDRV_PCM_FMTBIT_S16_LE |
835 SNDRV_PCM_FMTBIT_U16_BE | SNDRV_PCM_FMTBIT_S16_BE |
836 SNDRV_PCM_FMTBIT_U32_LE | SNDRV_PCM_FMTBIT_S32_LE |
837 SNDRV_PCM_FMTBIT_U32_BE | SNDRV_PCM_FMTBIT_S32_BE,
838 .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
839 .rate_min = 4000,
840 .rate_max = 48000,
841 .channels_min = 1,
842 .channels_max = 2,
843 .buffer_bytes_max = (512*1024),
844 .period_bytes_min = 64,
845 .period_bytes_max = (512*1024),
846 .periods_min = 1,
847 .periods_max = 2,
848 .fifo_size = CS4281_FIFO_SIZE,
849};
850
851static const struct snd_pcm_hardware snd_cs4281_capture =
852{
853 .info = SNDRV_PCM_INFO_MMAP |
854 SNDRV_PCM_INFO_INTERLEAVED |
855 SNDRV_PCM_INFO_MMAP_VALID |
856 SNDRV_PCM_INFO_PAUSE |
857 SNDRV_PCM_INFO_RESUME,
858 .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S8 |
859 SNDRV_PCM_FMTBIT_U16_LE | SNDRV_PCM_FMTBIT_S16_LE |
860 SNDRV_PCM_FMTBIT_U16_BE | SNDRV_PCM_FMTBIT_S16_BE |
861 SNDRV_PCM_FMTBIT_U32_LE | SNDRV_PCM_FMTBIT_S32_LE |
862 SNDRV_PCM_FMTBIT_U32_BE | SNDRV_PCM_FMTBIT_S32_BE,
863 .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
864 .rate_min = 4000,
865 .rate_max = 48000,
866 .channels_min = 1,
867 .channels_max = 2,
868 .buffer_bytes_max = (512*1024),
869 .period_bytes_min = 64,
870 .period_bytes_max = (512*1024),
871 .periods_min = 1,
872 .periods_max = 2,
873 .fifo_size = CS4281_FIFO_SIZE,
874};
875
876static int snd_cs4281_playback_open(struct snd_pcm_substream *substream)
877{
878 struct cs4281 *chip = snd_pcm_substream_chip(substream);
879 struct snd_pcm_runtime *runtime = substream->runtime;
880 struct cs4281_dma *dma;
881
882 dma = &chip->dma[0];
883 dma->substream = substream;
884 dma->left_slot = 0;
885 dma->right_slot = 1;
886 runtime->private_data = dma;
887 runtime->hw = snd_cs4281_playback;
888 /* should be detected from the AC'97 layer, but it seems
889 that although CS4297A rev B reports 18-bit ADC resolution,
890 samples are 20-bit */
891 snd_pcm_hw_constraint_msbits(runtime, 0, 32, 20);
892 return 0;
893}
894
895static int snd_cs4281_capture_open(struct snd_pcm_substream *substream)
896{
897 struct cs4281 *chip = snd_pcm_substream_chip(substream);
898 struct snd_pcm_runtime *runtime = substream->runtime;
899 struct cs4281_dma *dma;
900
901 dma = &chip->dma[1];
902 dma->substream = substream;
903 dma->left_slot = 10;
904 dma->right_slot = 11;
905 runtime->private_data = dma;
906 runtime->hw = snd_cs4281_capture;
907 /* should be detected from the AC'97 layer, but it seems
908 that although CS4297A rev B reports 18-bit ADC resolution,
909 samples are 20-bit */
910 snd_pcm_hw_constraint_msbits(runtime, 0, 32, 20);
911 return 0;
912}
913
914static int snd_cs4281_playback_close(struct snd_pcm_substream *substream)
915{
916 struct cs4281_dma *dma = substream->runtime->private_data;
917
918 dma->substream = NULL;
919 return 0;
920}
921
922static int snd_cs4281_capture_close(struct snd_pcm_substream *substream)
923{
924 struct cs4281_dma *dma = substream->runtime->private_data;
925
926 dma->substream = NULL;
927 return 0;
928}
929
930static const struct snd_pcm_ops snd_cs4281_playback_ops = {
931 .open = snd_cs4281_playback_open,
932 .close = snd_cs4281_playback_close,
933 .prepare = snd_cs4281_playback_prepare,
934 .trigger = snd_cs4281_trigger,
935 .pointer = snd_cs4281_pointer,
936};
937
938static const struct snd_pcm_ops snd_cs4281_capture_ops = {
939 .open = snd_cs4281_capture_open,
940 .close = snd_cs4281_capture_close,
941 .prepare = snd_cs4281_capture_prepare,
942 .trigger = snd_cs4281_trigger,
943 .pointer = snd_cs4281_pointer,
944};
945
946static int snd_cs4281_pcm(struct cs4281 *chip, int device)
947{
948 struct snd_pcm *pcm;
949 int err;
950
951 err = snd_pcm_new(chip->card, "CS4281", device, 1, 1, &pcm);
952 if (err < 0)
953 return err;
954
955 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cs4281_playback_ops);
956 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_cs4281_capture_ops);
957
958 pcm->private_data = chip;
959 pcm->info_flags = 0;
960 strcpy(pcm->name, "CS4281");
961 chip->pcm = pcm;
962
963 snd_pcm_set_managed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV, &chip->pci->dev,
964 64*1024, 512*1024);
965
966 return 0;
967}
968
969/*
970 * Mixer section
971 */
972
973#define CS_VOL_MASK 0x1f
974
975static int snd_cs4281_info_volume(struct snd_kcontrol *kcontrol,
976 struct snd_ctl_elem_info *uinfo)
977{
978 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
979 uinfo->count = 2;
980 uinfo->value.integer.min = 0;
981 uinfo->value.integer.max = CS_VOL_MASK;
982 return 0;
983}
984
985static int snd_cs4281_get_volume(struct snd_kcontrol *kcontrol,
986 struct snd_ctl_elem_value *ucontrol)
987{
988 struct cs4281 *chip = snd_kcontrol_chip(kcontrol);
989 int regL = (kcontrol->private_value >> 16) & 0xffff;
990 int regR = kcontrol->private_value & 0xffff;
991 int volL, volR;
992
993 volL = CS_VOL_MASK - (snd_cs4281_peekBA0(chip, regL) & CS_VOL_MASK);
994 volR = CS_VOL_MASK - (snd_cs4281_peekBA0(chip, regR) & CS_VOL_MASK);
995
996 ucontrol->value.integer.value[0] = volL;
997 ucontrol->value.integer.value[1] = volR;
998 return 0;
999}
1000
1001static int snd_cs4281_put_volume(struct snd_kcontrol *kcontrol,
1002 struct snd_ctl_elem_value *ucontrol)
1003{
1004 struct cs4281 *chip = snd_kcontrol_chip(kcontrol);
1005 int change = 0;
1006 int regL = (kcontrol->private_value >> 16) & 0xffff;
1007 int regR = kcontrol->private_value & 0xffff;
1008 int volL, volR;
1009
1010 volL = CS_VOL_MASK - (snd_cs4281_peekBA0(chip, regL) & CS_VOL_MASK);
1011 volR = CS_VOL_MASK - (snd_cs4281_peekBA0(chip, regR) & CS_VOL_MASK);
1012
1013 if (ucontrol->value.integer.value[0] != volL) {
1014 volL = CS_VOL_MASK - (ucontrol->value.integer.value[0] & CS_VOL_MASK);
1015 snd_cs4281_pokeBA0(chip, regL, volL);
1016 change = 1;
1017 }
1018 if (ucontrol->value.integer.value[1] != volR) {
1019 volR = CS_VOL_MASK - (ucontrol->value.integer.value[1] & CS_VOL_MASK);
1020 snd_cs4281_pokeBA0(chip, regR, volR);
1021 change = 1;
1022 }
1023 return change;
1024}
1025
1026static const DECLARE_TLV_DB_SCALE(db_scale_dsp, -4650, 150, 0);
1027
1028static const struct snd_kcontrol_new snd_cs4281_fm_vol =
1029{
1030 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
1031 .name = "Synth Playback Volume",
1032 .info = snd_cs4281_info_volume,
1033 .get = snd_cs4281_get_volume,
1034 .put = snd_cs4281_put_volume,
1035 .private_value = ((BA0_FMLVC << 16) | BA0_FMRVC),
1036 .tlv = { .p = db_scale_dsp },
1037};
1038
1039static const struct snd_kcontrol_new snd_cs4281_pcm_vol =
1040{
1041 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
1042 .name = "PCM Stream Playback Volume",
1043 .info = snd_cs4281_info_volume,
1044 .get = snd_cs4281_get_volume,
1045 .put = snd_cs4281_put_volume,
1046 .private_value = ((BA0_PPLVC << 16) | BA0_PPRVC),
1047 .tlv = { .p = db_scale_dsp },
1048};
1049
1050static void snd_cs4281_mixer_free_ac97_bus(struct snd_ac97_bus *bus)
1051{
1052 struct cs4281 *chip = bus->private_data;
1053 chip->ac97_bus = NULL;
1054}
1055
1056static void snd_cs4281_mixer_free_ac97(struct snd_ac97 *ac97)
1057{
1058 struct cs4281 *chip = ac97->private_data;
1059 if (ac97->num)
1060 chip->ac97_secondary = NULL;
1061 else
1062 chip->ac97 = NULL;
1063}
1064
1065static int snd_cs4281_mixer(struct cs4281 *chip)
1066{
1067 struct snd_card *card = chip->card;
1068 struct snd_ac97_template ac97;
1069 int err;
1070 static const struct snd_ac97_bus_ops ops = {
1071 .write = snd_cs4281_ac97_write,
1072 .read = snd_cs4281_ac97_read,
1073 };
1074
1075 if ((err = snd_ac97_bus(card, 0, &ops, chip, &chip->ac97_bus)) < 0)
1076 return err;
1077 chip->ac97_bus->private_free = snd_cs4281_mixer_free_ac97_bus;
1078
1079 memset(&ac97, 0, sizeof(ac97));
1080 ac97.private_data = chip;
1081 ac97.private_free = snd_cs4281_mixer_free_ac97;
1082 if ((err = snd_ac97_mixer(chip->ac97_bus, &ac97, &chip->ac97)) < 0)
1083 return err;
1084 if (chip->dual_codec) {
1085 ac97.num = 1;
1086 if ((err = snd_ac97_mixer(chip->ac97_bus, &ac97, &chip->ac97_secondary)) < 0)
1087 return err;
1088 }
1089 if ((err = snd_ctl_add(card, snd_ctl_new1(&snd_cs4281_fm_vol, chip))) < 0)
1090 return err;
1091 if ((err = snd_ctl_add(card, snd_ctl_new1(&snd_cs4281_pcm_vol, chip))) < 0)
1092 return err;
1093 return 0;
1094}
1095
1096
1097/*
1098 * proc interface
1099 */
1100
1101static void snd_cs4281_proc_read(struct snd_info_entry *entry,
1102 struct snd_info_buffer *buffer)
1103{
1104 struct cs4281 *chip = entry->private_data;
1105
1106 snd_iprintf(buffer, "Cirrus Logic CS4281\n\n");
1107 snd_iprintf(buffer, "Spurious half IRQs : %u\n", chip->spurious_dhtc_irq);
1108 snd_iprintf(buffer, "Spurious end IRQs : %u\n", chip->spurious_dtc_irq);
1109}
1110
1111static ssize_t snd_cs4281_BA0_read(struct snd_info_entry *entry,
1112 void *file_private_data,
1113 struct file *file, char __user *buf,
1114 size_t count, loff_t pos)
1115{
1116 struct cs4281 *chip = entry->private_data;
1117
1118 if (copy_to_user_fromio(buf, chip->ba0 + pos, count))
1119 return -EFAULT;
1120 return count;
1121}
1122
1123static ssize_t snd_cs4281_BA1_read(struct snd_info_entry *entry,
1124 void *file_private_data,
1125 struct file *file, char __user *buf,
1126 size_t count, loff_t pos)
1127{
1128 struct cs4281 *chip = entry->private_data;
1129
1130 if (copy_to_user_fromio(buf, chip->ba1 + pos, count))
1131 return -EFAULT;
1132 return count;
1133}
1134
1135static const struct snd_info_entry_ops snd_cs4281_proc_ops_BA0 = {
1136 .read = snd_cs4281_BA0_read,
1137};
1138
1139static const struct snd_info_entry_ops snd_cs4281_proc_ops_BA1 = {
1140 .read = snd_cs4281_BA1_read,
1141};
1142
1143static void snd_cs4281_proc_init(struct cs4281 *chip)
1144{
1145 struct snd_info_entry *entry;
1146
1147 snd_card_ro_proc_new(chip->card, "cs4281", chip, snd_cs4281_proc_read);
1148 if (! snd_card_proc_new(chip->card, "cs4281_BA0", &entry)) {
1149 entry->content = SNDRV_INFO_CONTENT_DATA;
1150 entry->private_data = chip;
1151 entry->c.ops = &snd_cs4281_proc_ops_BA0;
1152 entry->size = CS4281_BA0_SIZE;
1153 }
1154 if (! snd_card_proc_new(chip->card, "cs4281_BA1", &entry)) {
1155 entry->content = SNDRV_INFO_CONTENT_DATA;
1156 entry->private_data = chip;
1157 entry->c.ops = &snd_cs4281_proc_ops_BA1;
1158 entry->size = CS4281_BA1_SIZE;
1159 }
1160}
1161
1162/*
1163 * joystick support
1164 */
1165
1166#if IS_REACHABLE(CONFIG_GAMEPORT)
1167
1168static void snd_cs4281_gameport_trigger(struct gameport *gameport)
1169{
1170 struct cs4281 *chip = gameport_get_port_data(gameport);
1171
1172 if (snd_BUG_ON(!chip))
1173 return;
1174 snd_cs4281_pokeBA0(chip, BA0_JSPT, 0xff);
1175}
1176
1177static unsigned char snd_cs4281_gameport_read(struct gameport *gameport)
1178{
1179 struct cs4281 *chip = gameport_get_port_data(gameport);
1180
1181 if (snd_BUG_ON(!chip))
1182 return 0;
1183 return snd_cs4281_peekBA0(chip, BA0_JSPT);
1184}
1185
1186#ifdef COOKED_MODE
1187static int snd_cs4281_gameport_cooked_read(struct gameport *gameport,
1188 int *axes, int *buttons)
1189{
1190 struct cs4281 *chip = gameport_get_port_data(gameport);
1191 unsigned js1, js2, jst;
1192
1193 if (snd_BUG_ON(!chip))
1194 return 0;
1195
1196 js1 = snd_cs4281_peekBA0(chip, BA0_JSC1);
1197 js2 = snd_cs4281_peekBA0(chip, BA0_JSC2);
1198 jst = snd_cs4281_peekBA0(chip, BA0_JSPT);
1199
1200 *buttons = (~jst >> 4) & 0x0F;
1201
1202 axes[0] = ((js1 & JSC1_Y1V_MASK) >> JSC1_Y1V_SHIFT) & 0xFFFF;
1203 axes[1] = ((js1 & JSC1_X1V_MASK) >> JSC1_X1V_SHIFT) & 0xFFFF;
1204 axes[2] = ((js2 & JSC2_Y2V_MASK) >> JSC2_Y2V_SHIFT) & 0xFFFF;
1205 axes[3] = ((js2 & JSC2_X2V_MASK) >> JSC2_X2V_SHIFT) & 0xFFFF;
1206
1207 for (jst = 0; jst < 4; ++jst)
1208 if (axes[jst] == 0xFFFF) axes[jst] = -1;
1209 return 0;
1210}
1211#else
1212#define snd_cs4281_gameport_cooked_read NULL
1213#endif
1214
1215static int snd_cs4281_gameport_open(struct gameport *gameport, int mode)
1216{
1217 switch (mode) {
1218#ifdef COOKED_MODE
1219 case GAMEPORT_MODE_COOKED:
1220 return 0;
1221#endif
1222 case GAMEPORT_MODE_RAW:
1223 return 0;
1224 default:
1225 return -1;
1226 }
1227 return 0;
1228}
1229
1230static int snd_cs4281_create_gameport(struct cs4281 *chip)
1231{
1232 struct gameport *gp;
1233
1234 chip->gameport = gp = gameport_allocate_port();
1235 if (!gp) {
1236 dev_err(chip->card->dev,
1237 "cannot allocate memory for gameport\n");
1238 return -ENOMEM;
1239 }
1240
1241 gameport_set_name(gp, "CS4281 Gameport");
1242 gameport_set_phys(gp, "pci%s/gameport0", pci_name(chip->pci));
1243 gameport_set_dev_parent(gp, &chip->pci->dev);
1244 gp->open = snd_cs4281_gameport_open;
1245 gp->read = snd_cs4281_gameport_read;
1246 gp->trigger = snd_cs4281_gameport_trigger;
1247 gp->cooked_read = snd_cs4281_gameport_cooked_read;
1248 gameport_set_port_data(gp, chip);
1249
1250 snd_cs4281_pokeBA0(chip, BA0_JSIO, 0xFF); // ?
1251 snd_cs4281_pokeBA0(chip, BA0_JSCTL, JSCTL_SP_MEDIUM_SLOW);
1252
1253 gameport_register_port(gp);
1254
1255 return 0;
1256}
1257
1258static void snd_cs4281_free_gameport(struct cs4281 *chip)
1259{
1260 if (chip->gameport) {
1261 gameport_unregister_port(chip->gameport);
1262 chip->gameport = NULL;
1263 }
1264}
1265#else
1266static inline int snd_cs4281_create_gameport(struct cs4281 *chip) { return -ENOSYS; }
1267static inline void snd_cs4281_free_gameport(struct cs4281 *chip) { }
1268#endif /* IS_REACHABLE(CONFIG_GAMEPORT) */
1269
1270static int snd_cs4281_free(struct cs4281 *chip)
1271{
1272 snd_cs4281_free_gameport(chip);
1273
1274 /* Mask interrupts */
1275 snd_cs4281_pokeBA0(chip, BA0_HIMR, 0x7fffffff);
1276 /* Stop the DLL Clock logic. */
1277 snd_cs4281_pokeBA0(chip, BA0_CLKCR1, 0);
1278 /* Sound System Power Management - Turn Everything OFF */
1279 snd_cs4281_pokeBA0(chip, BA0_SSPM, 0);
1280 /* PCI interface - D3 state */
1281 pci_set_power_state(chip->pci, PCI_D3hot);
1282
1283 if (chip->irq >= 0)
1284 free_irq(chip->irq, chip);
1285 iounmap(chip->ba0);
1286 iounmap(chip->ba1);
1287 pci_release_regions(chip->pci);
1288 pci_disable_device(chip->pci);
1289
1290 kfree(chip);
1291 return 0;
1292}
1293
1294static int snd_cs4281_dev_free(struct snd_device *device)
1295{
1296 struct cs4281 *chip = device->device_data;
1297 return snd_cs4281_free(chip);
1298}
1299
1300static int snd_cs4281_chip_init(struct cs4281 *chip); /* defined below */
1301
1302static int snd_cs4281_create(struct snd_card *card,
1303 struct pci_dev *pci,
1304 struct cs4281 **rchip,
1305 int dual_codec)
1306{
1307 struct cs4281 *chip;
1308 unsigned int tmp;
1309 int err;
1310 static const struct snd_device_ops ops = {
1311 .dev_free = snd_cs4281_dev_free,
1312 };
1313
1314 *rchip = NULL;
1315 if ((err = pci_enable_device(pci)) < 0)
1316 return err;
1317 chip = kzalloc(sizeof(*chip), GFP_KERNEL);
1318 if (chip == NULL) {
1319 pci_disable_device(pci);
1320 return -ENOMEM;
1321 }
1322 spin_lock_init(&chip->reg_lock);
1323 chip->card = card;
1324 chip->pci = pci;
1325 chip->irq = -1;
1326 pci_set_master(pci);
1327 if (dual_codec < 0 || dual_codec > 3) {
1328 dev_err(card->dev, "invalid dual_codec option %d\n", dual_codec);
1329 dual_codec = 0;
1330 }
1331 chip->dual_codec = dual_codec;
1332
1333 if ((err = pci_request_regions(pci, "CS4281")) < 0) {
1334 kfree(chip);
1335 pci_disable_device(pci);
1336 return err;
1337 }
1338 chip->ba0_addr = pci_resource_start(pci, 0);
1339 chip->ba1_addr = pci_resource_start(pci, 1);
1340
1341 chip->ba0 = pci_ioremap_bar(pci, 0);
1342 chip->ba1 = pci_ioremap_bar(pci, 1);
1343 if (!chip->ba0 || !chip->ba1) {
1344 snd_cs4281_free(chip);
1345 return -ENOMEM;
1346 }
1347
1348 if (request_irq(pci->irq, snd_cs4281_interrupt, IRQF_SHARED,
1349 KBUILD_MODNAME, chip)) {
1350 dev_err(card->dev, "unable to grab IRQ %d\n", pci->irq);
1351 snd_cs4281_free(chip);
1352 return -ENOMEM;
1353 }
1354 chip->irq = pci->irq;
1355 card->sync_irq = chip->irq;
1356
1357 tmp = snd_cs4281_chip_init(chip);
1358 if (tmp) {
1359 snd_cs4281_free(chip);
1360 return tmp;
1361 }
1362
1363 if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) < 0) {
1364 snd_cs4281_free(chip);
1365 return err;
1366 }
1367
1368 snd_cs4281_proc_init(chip);
1369
1370 *rchip = chip;
1371 return 0;
1372}
1373
1374static int snd_cs4281_chip_init(struct cs4281 *chip)
1375{
1376 unsigned int tmp;
1377 unsigned long end_time;
1378 int retry_count = 2;
1379
1380 /* Having EPPMC.FPDN=1 prevent proper chip initialisation */
1381 tmp = snd_cs4281_peekBA0(chip, BA0_EPPMC);
1382 if (tmp & BA0_EPPMC_FPDN)
1383 snd_cs4281_pokeBA0(chip, BA0_EPPMC, tmp & ~BA0_EPPMC_FPDN);
1384
1385 __retry:
1386 tmp = snd_cs4281_peekBA0(chip, BA0_CFLR);
1387 if (tmp != BA0_CFLR_DEFAULT) {
1388 snd_cs4281_pokeBA0(chip, BA0_CFLR, BA0_CFLR_DEFAULT);
1389 tmp = snd_cs4281_peekBA0(chip, BA0_CFLR);
1390 if (tmp != BA0_CFLR_DEFAULT) {
1391 dev_err(chip->card->dev,
1392 "CFLR setup failed (0x%x)\n", tmp);
1393 return -EIO;
1394 }
1395 }
1396
1397 /* Set the 'Configuration Write Protect' register
1398 * to 4281h. Allows vendor-defined configuration
1399 * space between 0e4h and 0ffh to be written. */
1400 snd_cs4281_pokeBA0(chip, BA0_CWPR, 0x4281);
1401
1402 if ((tmp = snd_cs4281_peekBA0(chip, BA0_SERC1)) != (BA0_SERC1_SO1EN | BA0_SERC1_AC97)) {
1403 dev_err(chip->card->dev,
1404 "SERC1 AC'97 check failed (0x%x)\n", tmp);
1405 return -EIO;
1406 }
1407 if ((tmp = snd_cs4281_peekBA0(chip, BA0_SERC2)) != (BA0_SERC2_SI1EN | BA0_SERC2_AC97)) {
1408 dev_err(chip->card->dev,
1409 "SERC2 AC'97 check failed (0x%x)\n", tmp);
1410 return -EIO;
1411 }
1412
1413 /* Sound System Power Management */
1414 snd_cs4281_pokeBA0(chip, BA0_SSPM, BA0_SSPM_MIXEN | BA0_SSPM_CSRCEN |
1415 BA0_SSPM_PSRCEN | BA0_SSPM_JSEN |
1416 BA0_SSPM_ACLEN | BA0_SSPM_FMEN);
1417
1418 /* Serial Port Power Management */
1419 /* Blast the clock control register to zero so that the
1420 * PLL starts out in a known state, and blast the master serial
1421 * port control register to zero so that the serial ports also
1422 * start out in a known state. */
1423 snd_cs4281_pokeBA0(chip, BA0_CLKCR1, 0);
1424 snd_cs4281_pokeBA0(chip, BA0_SERMC, 0);
1425
1426 /* Make ESYN go to zero to turn off
1427 * the Sync pulse on the AC97 link. */
1428 snd_cs4281_pokeBA0(chip, BA0_ACCTL, 0);
1429 udelay(50);
1430
1431 /* Drive the ARST# pin low for a minimum of 1uS (as defined in the AC97
1432 * spec) and then drive it high. This is done for non AC97 modes since
1433 * there might be logic external to the CS4281 that uses the ARST# line
1434 * for a reset. */
1435 snd_cs4281_pokeBA0(chip, BA0_SPMC, 0);
1436 udelay(50);
1437 snd_cs4281_pokeBA0(chip, BA0_SPMC, BA0_SPMC_RSTN);
1438 msleep(50);
1439
1440 if (chip->dual_codec)
1441 snd_cs4281_pokeBA0(chip, BA0_SPMC, BA0_SPMC_RSTN | BA0_SPMC_ASDI2E);
1442
1443 /*
1444 * Set the serial port timing configuration.
1445 */
1446 snd_cs4281_pokeBA0(chip, BA0_SERMC,
1447 (chip->dual_codec ? BA0_SERMC_TCID(chip->dual_codec) : BA0_SERMC_TCID(1)) |
1448 BA0_SERMC_PTC_AC97 | BA0_SERMC_MSPE);
1449
1450 /*
1451 * Start the DLL Clock logic.
1452 */
1453 snd_cs4281_pokeBA0(chip, BA0_CLKCR1, BA0_CLKCR1_DLLP);
1454 msleep(50);
1455 snd_cs4281_pokeBA0(chip, BA0_CLKCR1, BA0_CLKCR1_SWCE | BA0_CLKCR1_DLLP);
1456
1457 /*
1458 * Wait for the DLL ready signal from the clock logic.
1459 */
1460 end_time = jiffies + HZ;
1461 do {
1462 /*
1463 * Read the AC97 status register to see if we've seen a CODEC
1464 * signal from the AC97 codec.
1465 */
1466 if (snd_cs4281_peekBA0(chip, BA0_CLKCR1) & BA0_CLKCR1_DLLRDY)
1467 goto __ok0;
1468 schedule_timeout_uninterruptible(1);
1469 } while (time_after_eq(end_time, jiffies));
1470
1471 dev_err(chip->card->dev, "DLLRDY not seen\n");
1472 return -EIO;
1473
1474 __ok0:
1475
1476 /*
1477 * The first thing we do here is to enable sync generation. As soon
1478 * as we start receiving bit clock, we'll start producing the SYNC
1479 * signal.
1480 */
1481 snd_cs4281_pokeBA0(chip, BA0_ACCTL, BA0_ACCTL_ESYN);
1482
1483 /*
1484 * Wait for the codec ready signal from the AC97 codec.
1485 */
1486 end_time = jiffies + HZ;
1487 do {
1488 /*
1489 * Read the AC97 status register to see if we've seen a CODEC
1490 * signal from the AC97 codec.
1491 */
1492 if (snd_cs4281_peekBA0(chip, BA0_ACSTS) & BA0_ACSTS_CRDY)
1493 goto __ok1;
1494 schedule_timeout_uninterruptible(1);
1495 } while (time_after_eq(end_time, jiffies));
1496
1497 dev_err(chip->card->dev,
1498 "never read codec ready from AC'97 (0x%x)\n",
1499 snd_cs4281_peekBA0(chip, BA0_ACSTS));
1500 return -EIO;
1501
1502 __ok1:
1503 if (chip->dual_codec) {
1504 end_time = jiffies + HZ;
1505 do {
1506 if (snd_cs4281_peekBA0(chip, BA0_ACSTS2) & BA0_ACSTS_CRDY)
1507 goto __codec2_ok;
1508 schedule_timeout_uninterruptible(1);
1509 } while (time_after_eq(end_time, jiffies));
1510 dev_info(chip->card->dev,
1511 "secondary codec doesn't respond. disable it...\n");
1512 chip->dual_codec = 0;
1513 __codec2_ok: ;
1514 }
1515
1516 /*
1517 * Assert the valid frame signal so that we can start sending commands
1518 * to the AC97 codec.
1519 */
1520
1521 snd_cs4281_pokeBA0(chip, BA0_ACCTL, BA0_ACCTL_VFRM | BA0_ACCTL_ESYN);
1522
1523 /*
1524 * Wait until we've sampled input slots 3 and 4 as valid, meaning that
1525 * the codec is pumping ADC data across the AC-link.
1526 */
1527
1528 end_time = jiffies + HZ;
1529 do {
1530 /*
1531 * Read the input slot valid register and see if input slots 3
1532 * 4 are valid yet.
1533 */
1534 if ((snd_cs4281_peekBA0(chip, BA0_ACISV) & (BA0_ACISV_SLV(3) | BA0_ACISV_SLV(4))) == (BA0_ACISV_SLV(3) | BA0_ACISV_SLV(4)))
1535 goto __ok2;
1536 schedule_timeout_uninterruptible(1);
1537 } while (time_after_eq(end_time, jiffies));
1538
1539 if (--retry_count > 0)
1540 goto __retry;
1541 dev_err(chip->card->dev, "never read ISV3 and ISV4 from AC'97\n");
1542 return -EIO;
1543
1544 __ok2:
1545
1546 /*
1547 * Now, assert valid frame and the slot 3 and 4 valid bits. This will
1548 * commense the transfer of digital audio data to the AC97 codec.
1549 */
1550 snd_cs4281_pokeBA0(chip, BA0_ACOSV, BA0_ACOSV_SLV(3) | BA0_ACOSV_SLV(4));
1551
1552 /*
1553 * Initialize DMA structures
1554 */
1555 for (tmp = 0; tmp < 4; tmp++) {
1556 struct cs4281_dma *dma = &chip->dma[tmp];
1557 dma->regDBA = BA0_DBA0 + (tmp * 0x10);
1558 dma->regDCA = BA0_DCA0 + (tmp * 0x10);
1559 dma->regDBC = BA0_DBC0 + (tmp * 0x10);
1560 dma->regDCC = BA0_DCC0 + (tmp * 0x10);
1561 dma->regDMR = BA0_DMR0 + (tmp * 8);
1562 dma->regDCR = BA0_DCR0 + (tmp * 8);
1563 dma->regHDSR = BA0_HDSR0 + (tmp * 4);
1564 dma->regFCR = BA0_FCR0 + (tmp * 4);
1565 dma->regFSIC = BA0_FSIC0 + (tmp * 4);
1566 dma->fifo_offset = tmp * CS4281_FIFO_SIZE;
1567 snd_cs4281_pokeBA0(chip, dma->regFCR,
1568 BA0_FCR_LS(31) |
1569 BA0_FCR_RS(31) |
1570 BA0_FCR_SZ(CS4281_FIFO_SIZE) |
1571 BA0_FCR_OF(dma->fifo_offset));
1572 }
1573
1574 chip->src_left_play_slot = 0; /* AC'97 left PCM playback (3) */
1575 chip->src_right_play_slot = 1; /* AC'97 right PCM playback (4) */
1576 chip->src_left_rec_slot = 10; /* AC'97 left PCM record (3) */
1577 chip->src_right_rec_slot = 11; /* AC'97 right PCM record (4) */
1578
1579 /* Activate wave playback FIFO for FM playback */
1580 chip->dma[0].valFCR = BA0_FCR_FEN | BA0_FCR_LS(0) |
1581 BA0_FCR_RS(1) |
1582 BA0_FCR_SZ(CS4281_FIFO_SIZE) |
1583 BA0_FCR_OF(chip->dma[0].fifo_offset);
1584 snd_cs4281_pokeBA0(chip, chip->dma[0].regFCR, chip->dma[0].valFCR);
1585 snd_cs4281_pokeBA0(chip, BA0_SRCSA, (chip->src_left_play_slot << 0) |
1586 (chip->src_right_play_slot << 8) |
1587 (chip->src_left_rec_slot << 16) |
1588 (chip->src_right_rec_slot << 24));
1589
1590 /* Initialize digital volume */
1591 snd_cs4281_pokeBA0(chip, BA0_PPLVC, 0);
1592 snd_cs4281_pokeBA0(chip, BA0_PPRVC, 0);
1593
1594 /* Enable IRQs */
1595 snd_cs4281_pokeBA0(chip, BA0_HICR, BA0_HICR_EOI);
1596 /* Unmask interrupts */
1597 snd_cs4281_pokeBA0(chip, BA0_HIMR, 0x7fffffff & ~(
1598 BA0_HISR_MIDI |
1599 BA0_HISR_DMAI |
1600 BA0_HISR_DMA(0) |
1601 BA0_HISR_DMA(1) |
1602 BA0_HISR_DMA(2) |
1603 BA0_HISR_DMA(3)));
1604
1605 return 0;
1606}
1607
1608/*
1609 * MIDI section
1610 */
1611
1612static void snd_cs4281_midi_reset(struct cs4281 *chip)
1613{
1614 snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr | BA0_MIDCR_MRST);
1615 udelay(100);
1616 snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr);
1617}
1618
1619static int snd_cs4281_midi_input_open(struct snd_rawmidi_substream *substream)
1620{
1621 struct cs4281 *chip = substream->rmidi->private_data;
1622
1623 spin_lock_irq(&chip->reg_lock);
1624 chip->midcr |= BA0_MIDCR_RXE;
1625 chip->midi_input = substream;
1626 if (!(chip->uartm & CS4281_MODE_OUTPUT)) {
1627 snd_cs4281_midi_reset(chip);
1628 } else {
1629 snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr);
1630 }
1631 spin_unlock_irq(&chip->reg_lock);
1632 return 0;
1633}
1634
1635static int snd_cs4281_midi_input_close(struct snd_rawmidi_substream *substream)
1636{
1637 struct cs4281 *chip = substream->rmidi->private_data;
1638
1639 spin_lock_irq(&chip->reg_lock);
1640 chip->midcr &= ~(BA0_MIDCR_RXE | BA0_MIDCR_RIE);
1641 chip->midi_input = NULL;
1642 if (!(chip->uartm & CS4281_MODE_OUTPUT)) {
1643 snd_cs4281_midi_reset(chip);
1644 } else {
1645 snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr);
1646 }
1647 chip->uartm &= ~CS4281_MODE_INPUT;
1648 spin_unlock_irq(&chip->reg_lock);
1649 return 0;
1650}
1651
1652static int snd_cs4281_midi_output_open(struct snd_rawmidi_substream *substream)
1653{
1654 struct cs4281 *chip = substream->rmidi->private_data;
1655
1656 spin_lock_irq(&chip->reg_lock);
1657 chip->uartm |= CS4281_MODE_OUTPUT;
1658 chip->midcr |= BA0_MIDCR_TXE;
1659 chip->midi_output = substream;
1660 if (!(chip->uartm & CS4281_MODE_INPUT)) {
1661 snd_cs4281_midi_reset(chip);
1662 } else {
1663 snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr);
1664 }
1665 spin_unlock_irq(&chip->reg_lock);
1666 return 0;
1667}
1668
1669static int snd_cs4281_midi_output_close(struct snd_rawmidi_substream *substream)
1670{
1671 struct cs4281 *chip = substream->rmidi->private_data;
1672
1673 spin_lock_irq(&chip->reg_lock);
1674 chip->midcr &= ~(BA0_MIDCR_TXE | BA0_MIDCR_TIE);
1675 chip->midi_output = NULL;
1676 if (!(chip->uartm & CS4281_MODE_INPUT)) {
1677 snd_cs4281_midi_reset(chip);
1678 } else {
1679 snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr);
1680 }
1681 chip->uartm &= ~CS4281_MODE_OUTPUT;
1682 spin_unlock_irq(&chip->reg_lock);
1683 return 0;
1684}
1685
1686static void snd_cs4281_midi_input_trigger(struct snd_rawmidi_substream *substream, int up)
1687{
1688 unsigned long flags;
1689 struct cs4281 *chip = substream->rmidi->private_data;
1690
1691 spin_lock_irqsave(&chip->reg_lock, flags);
1692 if (up) {
1693 if ((chip->midcr & BA0_MIDCR_RIE) == 0) {
1694 chip->midcr |= BA0_MIDCR_RIE;
1695 snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr);
1696 }
1697 } else {
1698 if (chip->midcr & BA0_MIDCR_RIE) {
1699 chip->midcr &= ~BA0_MIDCR_RIE;
1700 snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr);
1701 }
1702 }
1703 spin_unlock_irqrestore(&chip->reg_lock, flags);
1704}
1705
1706static void snd_cs4281_midi_output_trigger(struct snd_rawmidi_substream *substream, int up)
1707{
1708 unsigned long flags;
1709 struct cs4281 *chip = substream->rmidi->private_data;
1710 unsigned char byte;
1711
1712 spin_lock_irqsave(&chip->reg_lock, flags);
1713 if (up) {
1714 if ((chip->midcr & BA0_MIDCR_TIE) == 0) {
1715 chip->midcr |= BA0_MIDCR_TIE;
1716 /* fill UART FIFO buffer at first, and turn Tx interrupts only if necessary */
1717 while ((chip->midcr & BA0_MIDCR_TIE) &&
1718 (snd_cs4281_peekBA0(chip, BA0_MIDSR) & BA0_MIDSR_TBF) == 0) {
1719 if (snd_rawmidi_transmit(substream, &byte, 1) != 1) {
1720 chip->midcr &= ~BA0_MIDCR_TIE;
1721 } else {
1722 snd_cs4281_pokeBA0(chip, BA0_MIDWP, byte);
1723 }
1724 }
1725 snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr);
1726 }
1727 } else {
1728 if (chip->midcr & BA0_MIDCR_TIE) {
1729 chip->midcr &= ~BA0_MIDCR_TIE;
1730 snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr);
1731 }
1732 }
1733 spin_unlock_irqrestore(&chip->reg_lock, flags);
1734}
1735
1736static const struct snd_rawmidi_ops snd_cs4281_midi_output =
1737{
1738 .open = snd_cs4281_midi_output_open,
1739 .close = snd_cs4281_midi_output_close,
1740 .trigger = snd_cs4281_midi_output_trigger,
1741};
1742
1743static const struct snd_rawmidi_ops snd_cs4281_midi_input =
1744{
1745 .open = snd_cs4281_midi_input_open,
1746 .close = snd_cs4281_midi_input_close,
1747 .trigger = snd_cs4281_midi_input_trigger,
1748};
1749
1750static int snd_cs4281_midi(struct cs4281 *chip, int device)
1751{
1752 struct snd_rawmidi *rmidi;
1753 int err;
1754
1755 if ((err = snd_rawmidi_new(chip->card, "CS4281", device, 1, 1, &rmidi)) < 0)
1756 return err;
1757 strcpy(rmidi->name, "CS4281");
1758 snd_rawmidi_set_ops(rmidi, SNDRV_RAWMIDI_STREAM_OUTPUT, &snd_cs4281_midi_output);
1759 snd_rawmidi_set_ops(rmidi, SNDRV_RAWMIDI_STREAM_INPUT, &snd_cs4281_midi_input);
1760 rmidi->info_flags |= SNDRV_RAWMIDI_INFO_OUTPUT | SNDRV_RAWMIDI_INFO_INPUT | SNDRV_RAWMIDI_INFO_DUPLEX;
1761 rmidi->private_data = chip;
1762 chip->rmidi = rmidi;
1763 return 0;
1764}
1765
1766/*
1767 * Interrupt handler
1768 */
1769
1770static irqreturn_t snd_cs4281_interrupt(int irq, void *dev_id)
1771{
1772 struct cs4281 *chip = dev_id;
1773 unsigned int status, dma, val;
1774 struct cs4281_dma *cdma;
1775
1776 if (chip == NULL)
1777 return IRQ_NONE;
1778 status = snd_cs4281_peekBA0(chip, BA0_HISR);
1779 if ((status & 0x7fffffff) == 0) {
1780 snd_cs4281_pokeBA0(chip, BA0_HICR, BA0_HICR_EOI);
1781 return IRQ_NONE;
1782 }
1783
1784 if (status & (BA0_HISR_DMA(0)|BA0_HISR_DMA(1)|BA0_HISR_DMA(2)|BA0_HISR_DMA(3))) {
1785 for (dma = 0; dma < 4; dma++)
1786 if (status & BA0_HISR_DMA(dma)) {
1787 cdma = &chip->dma[dma];
1788 spin_lock(&chip->reg_lock);
1789 /* ack DMA IRQ */
1790 val = snd_cs4281_peekBA0(chip, cdma->regHDSR);
1791 /* workaround, sometimes CS4281 acknowledges */
1792 /* end or middle transfer position twice */
1793 cdma->frag++;
1794 if ((val & BA0_HDSR_DHTC) && !(cdma->frag & 1)) {
1795 cdma->frag--;
1796 chip->spurious_dhtc_irq++;
1797 spin_unlock(&chip->reg_lock);
1798 continue;
1799 }
1800 if ((val & BA0_HDSR_DTC) && (cdma->frag & 1)) {
1801 cdma->frag--;
1802 chip->spurious_dtc_irq++;
1803 spin_unlock(&chip->reg_lock);
1804 continue;
1805 }
1806 spin_unlock(&chip->reg_lock);
1807 snd_pcm_period_elapsed(cdma->substream);
1808 }
1809 }
1810
1811 if ((status & BA0_HISR_MIDI) && chip->rmidi) {
1812 unsigned char c;
1813
1814 spin_lock(&chip->reg_lock);
1815 while ((snd_cs4281_peekBA0(chip, BA0_MIDSR) & BA0_MIDSR_RBE) == 0) {
1816 c = snd_cs4281_peekBA0(chip, BA0_MIDRP);
1817 if ((chip->midcr & BA0_MIDCR_RIE) == 0)
1818 continue;
1819 snd_rawmidi_receive(chip->midi_input, &c, 1);
1820 }
1821 while ((snd_cs4281_peekBA0(chip, BA0_MIDSR) & BA0_MIDSR_TBF) == 0) {
1822 if ((chip->midcr & BA0_MIDCR_TIE) == 0)
1823 break;
1824 if (snd_rawmidi_transmit(chip->midi_output, &c, 1) != 1) {
1825 chip->midcr &= ~BA0_MIDCR_TIE;
1826 snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr);
1827 break;
1828 }
1829 snd_cs4281_pokeBA0(chip, BA0_MIDWP, c);
1830 }
1831 spin_unlock(&chip->reg_lock);
1832 }
1833
1834 /* EOI to the PCI part... reenables interrupts */
1835 snd_cs4281_pokeBA0(chip, BA0_HICR, BA0_HICR_EOI);
1836
1837 return IRQ_HANDLED;
1838}
1839
1840
1841/*
1842 * OPL3 command
1843 */
1844static void snd_cs4281_opl3_command(struct snd_opl3 *opl3, unsigned short cmd,
1845 unsigned char val)
1846{
1847 unsigned long flags;
1848 struct cs4281 *chip = opl3->private_data;
1849 void __iomem *port;
1850
1851 if (cmd & OPL3_RIGHT)
1852 port = chip->ba0 + BA0_B1AP; /* right port */
1853 else
1854 port = chip->ba0 + BA0_B0AP; /* left port */
1855
1856 spin_lock_irqsave(&opl3->reg_lock, flags);
1857
1858 writel((unsigned int)cmd, port);
1859 udelay(10);
1860
1861 writel((unsigned int)val, port + 4);
1862 udelay(30);
1863
1864 spin_unlock_irqrestore(&opl3->reg_lock, flags);
1865}
1866
1867static int snd_cs4281_probe(struct pci_dev *pci,
1868 const struct pci_device_id *pci_id)
1869{
1870 static int dev;
1871 struct snd_card *card;
1872 struct cs4281 *chip;
1873 struct snd_opl3 *opl3;
1874 int err;
1875
1876 if (dev >= SNDRV_CARDS)
1877 return -ENODEV;
1878 if (!enable[dev]) {
1879 dev++;
1880 return -ENOENT;
1881 }
1882
1883 err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE,
1884 0, &card);
1885 if (err < 0)
1886 return err;
1887
1888 if ((err = snd_cs4281_create(card, pci, &chip, dual_codec[dev])) < 0) {
1889 snd_card_free(card);
1890 return err;
1891 }
1892 card->private_data = chip;
1893
1894 if ((err = snd_cs4281_mixer(chip)) < 0) {
1895 snd_card_free(card);
1896 return err;
1897 }
1898 if ((err = snd_cs4281_pcm(chip, 0)) < 0) {
1899 snd_card_free(card);
1900 return err;
1901 }
1902 if ((err = snd_cs4281_midi(chip, 0)) < 0) {
1903 snd_card_free(card);
1904 return err;
1905 }
1906 if ((err = snd_opl3_new(card, OPL3_HW_OPL3_CS4281, &opl3)) < 0) {
1907 snd_card_free(card);
1908 return err;
1909 }
1910 opl3->private_data = chip;
1911 opl3->command = snd_cs4281_opl3_command;
1912 snd_opl3_init(opl3);
1913 if ((err = snd_opl3_hwdep_new(opl3, 0, 1, NULL)) < 0) {
1914 snd_card_free(card);
1915 return err;
1916 }
1917 snd_cs4281_create_gameport(chip);
1918 strcpy(card->driver, "CS4281");
1919 strcpy(card->shortname, "Cirrus Logic CS4281");
1920 sprintf(card->longname, "%s at 0x%lx, irq %d",
1921 card->shortname,
1922 chip->ba0_addr,
1923 chip->irq);
1924
1925 if ((err = snd_card_register(card)) < 0) {
1926 snd_card_free(card);
1927 return err;
1928 }
1929
1930 pci_set_drvdata(pci, card);
1931 dev++;
1932 return 0;
1933}
1934
1935static void snd_cs4281_remove(struct pci_dev *pci)
1936{
1937 snd_card_free(pci_get_drvdata(pci));
1938}
1939
1940/*
1941 * Power Management
1942 */
1943#ifdef CONFIG_PM_SLEEP
1944
1945static const int saved_regs[SUSPEND_REGISTERS] = {
1946 BA0_JSCTL,
1947 BA0_GPIOR,
1948 BA0_SSCR,
1949 BA0_MIDCR,
1950 BA0_SRCSA,
1951 BA0_PASR,
1952 BA0_CASR,
1953 BA0_DACSR,
1954 BA0_ADCSR,
1955 BA0_FMLVC,
1956 BA0_FMRVC,
1957 BA0_PPLVC,
1958 BA0_PPRVC,
1959};
1960
1961#define CLKCR1_CKRA 0x00010000L
1962
1963static int cs4281_suspend(struct device *dev)
1964{
1965 struct snd_card *card = dev_get_drvdata(dev);
1966 struct cs4281 *chip = card->private_data;
1967 u32 ulCLK;
1968 unsigned int i;
1969
1970 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
1971 snd_ac97_suspend(chip->ac97);
1972 snd_ac97_suspend(chip->ac97_secondary);
1973
1974 ulCLK = snd_cs4281_peekBA0(chip, BA0_CLKCR1);
1975 ulCLK |= CLKCR1_CKRA;
1976 snd_cs4281_pokeBA0(chip, BA0_CLKCR1, ulCLK);
1977
1978 /* Disable interrupts. */
1979 snd_cs4281_pokeBA0(chip, BA0_HICR, BA0_HICR_CHGM);
1980
1981 /* remember the status registers */
1982 for (i = 0; i < ARRAY_SIZE(saved_regs); i++)
1983 if (saved_regs[i])
1984 chip->suspend_regs[i] = snd_cs4281_peekBA0(chip, saved_regs[i]);
1985
1986 /* Turn off the serial ports. */
1987 snd_cs4281_pokeBA0(chip, BA0_SERMC, 0);
1988
1989 /* Power off FM, Joystick, AC link, */
1990 snd_cs4281_pokeBA0(chip, BA0_SSPM, 0);
1991
1992 /* DLL off. */
1993 snd_cs4281_pokeBA0(chip, BA0_CLKCR1, 0);
1994
1995 /* AC link off. */
1996 snd_cs4281_pokeBA0(chip, BA0_SPMC, 0);
1997
1998 ulCLK = snd_cs4281_peekBA0(chip, BA0_CLKCR1);
1999 ulCLK &= ~CLKCR1_CKRA;
2000 snd_cs4281_pokeBA0(chip, BA0_CLKCR1, ulCLK);
2001 return 0;
2002}
2003
2004static int cs4281_resume(struct device *dev)
2005{
2006 struct snd_card *card = dev_get_drvdata(dev);
2007 struct cs4281 *chip = card->private_data;
2008 unsigned int i;
2009 u32 ulCLK;
2010
2011 ulCLK = snd_cs4281_peekBA0(chip, BA0_CLKCR1);
2012 ulCLK |= CLKCR1_CKRA;
2013 snd_cs4281_pokeBA0(chip, BA0_CLKCR1, ulCLK);
2014
2015 snd_cs4281_chip_init(chip);
2016
2017 /* restore the status registers */
2018 for (i = 0; i < ARRAY_SIZE(saved_regs); i++)
2019 if (saved_regs[i])
2020 snd_cs4281_pokeBA0(chip, saved_regs[i], chip->suspend_regs[i]);
2021
2022 snd_ac97_resume(chip->ac97);
2023 snd_ac97_resume(chip->ac97_secondary);
2024
2025 ulCLK = snd_cs4281_peekBA0(chip, BA0_CLKCR1);
2026 ulCLK &= ~CLKCR1_CKRA;
2027 snd_cs4281_pokeBA0(chip, BA0_CLKCR1, ulCLK);
2028
2029 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
2030 return 0;
2031}
2032
2033static SIMPLE_DEV_PM_OPS(cs4281_pm, cs4281_suspend, cs4281_resume);
2034#define CS4281_PM_OPS &cs4281_pm
2035#else
2036#define CS4281_PM_OPS NULL
2037#endif /* CONFIG_PM_SLEEP */
2038
2039static struct pci_driver cs4281_driver = {
2040 .name = KBUILD_MODNAME,
2041 .id_table = snd_cs4281_ids,
2042 .probe = snd_cs4281_probe,
2043 .remove = snd_cs4281_remove,
2044 .driver = {
2045 .pm = CS4281_PM_OPS,
2046 },
2047};
2048
2049module_pci_driver(cs4281_driver);
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