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atiixp.c

Last change on this file was 777, checked in by David Azarewicz, 6 months ago
Merge from uniaud32-exp branch
File size: 44.9 KB

Rev	Line
[679]	1	// SPDX-License-Identifier: GPL-2.0-or-later
[32]	2	/*
	3	* ALSA driver for ATI IXP 150/200/250/300 AC97 controllers
	4	*
	5	* Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
	6	*/
	7
[679]	8	#include <linux/io.h>
[32]	9	#include <linux/delay.h>
	10	#include <linux/interrupt.h>
	11	#include <linux/init.h>
	12	#include <linux/pci.h>
	13	#include <linux/slab.h>
[679]	14	#include <linux/module.h>
[305]	15	#include <linux/mutex.h>
[32]	16	#include <sound/core.h>
	17	#include <sound/pcm.h>
	18	#include <sound/pcm_params.h>
	19	#include <sound/info.h>
	20	#include <sound/ac97_codec.h>
	21	#include <sound/initval.h>
	22
[679]	23	#ifdef TARGET_OS2
	24	#define KBUILD_MODNAME "atiixp"
	25	#endif
	26
[32]	27	MODULE_AUTHOR("Takashi Iwai <tiwai@suse.de>");
	28	MODULE_DESCRIPTION("ATI IXP AC97 controller");
	29	MODULE_LICENSE("GPL");
	30
[70]	31	static int index = SNDRV_DEFAULT_IDX1; /* Index 0-MAX */
	32	static char id = SNDRV_DEFAULT_STR1; / ID for this card */
	33	static int ac97_clock = 48000;
	34	static char *ac97_quirk;
[679]	35	static bool spdif_aclink = 1;
[305]	36	static int ac97_codec = -1;
[32]	37
[305]	38	module_param(index, int, 0444);
[32]	39	MODULE_PARM_DESC(index, "Index value for ATI IXP controller.");
[305]	40	module_param(id, charp, 0444);
[32]	41	MODULE_PARM_DESC(id, "ID string for ATI IXP controller.");
[305]	42	module_param(ac97_clock, int, 0444);
[32]	43	MODULE_PARM_DESC(ac97_clock, "AC'97 codec clock (default 48000Hz).");
[305]	44	module_param(ac97_quirk, charp, 0444);
[32]	45	MODULE_PARM_DESC(ac97_quirk, "AC'97 workaround for strange hardware.");
[305]	46	module_param(ac97_codec, int, 0444);
	47	MODULE_PARM_DESC(ac97_codec, "Specify codec instead of probing.");
	48	module_param(spdif_aclink, bool, 0444);
[32]	49	MODULE_PARM_DESC(spdif_aclink, "S/PDIF over AC-link.");
	50
[70]	51	/* just for backward compatibility */
[679]	52	//static bool enable;
[305]	53	module_param(enable, bool, 0444);
[32]	54
[70]	55
[32]	56	/*
	57	*/
	58
	59	#define ATI_REG_ISR 0x00 /* interrupt source */
	60	#define ATI_REG_ISR_IN_XRUN (1U<<0)
	61	#define ATI_REG_ISR_IN_STATUS (1U<<1)
	62	#define ATI_REG_ISR_OUT_XRUN (1U<<2)
	63	#define ATI_REG_ISR_OUT_STATUS (1U<<3)
	64	#define ATI_REG_ISR_SPDF_XRUN (1U<<4)
	65	#define ATI_REG_ISR_SPDF_STATUS (1U<<5)
	66	#define ATI_REG_ISR_PHYS_INTR (1U<<8)
	67	#define ATI_REG_ISR_PHYS_MISMATCH (1U<<9)
	68	#define ATI_REG_ISR_CODEC0_NOT_READY (1U<<10)
	69	#define ATI_REG_ISR_CODEC1_NOT_READY (1U<<11)
	70	#define ATI_REG_ISR_CODEC2_NOT_READY (1U<<12)
	71	#define ATI_REG_ISR_NEW_FRAME (1U<<13)
	72
	73	#define ATI_REG_IER 0x04 /* interrupt enable */
	74	#define ATI_REG_IER_IN_XRUN_EN (1U<<0)
	75	#define ATI_REG_IER_IO_STATUS_EN (1U<<1)
	76	#define ATI_REG_IER_OUT_XRUN_EN (1U<<2)
	77	#define ATI_REG_IER_OUT_XRUN_COND (1U<<3)
	78	#define ATI_REG_IER_SPDF_XRUN_EN (1U<<4)
	79	#define ATI_REG_IER_SPDF_STATUS_EN (1U<<5)
	80	#define ATI_REG_IER_PHYS_INTR_EN (1U<<8)
	81	#define ATI_REG_IER_PHYS_MISMATCH_EN (1U<<9)
	82	#define ATI_REG_IER_CODEC0_INTR_EN (1U<<10)
	83	#define ATI_REG_IER_CODEC1_INTR_EN (1U<<11)
	84	#define ATI_REG_IER_CODEC2_INTR_EN (1U<<12)
	85	#define ATI_REG_IER_NEW_FRAME_EN (1U<<13) /* (RO */
	86	#define ATI_REG_IER_SET_BUS_BUSY (1U<<14) /* (WO) audio is running */
	87
	88	#define ATI_REG_CMD 0x08 /* command */
	89	#define ATI_REG_CMD_POWERDOWN (1U<<0)
	90	#define ATI_REG_CMD_RECEIVE_EN (1U<<1)
	91	#define ATI_REG_CMD_SEND_EN (1U<<2)
	92	#define ATI_REG_CMD_STATUS_MEM (1U<<3)
	93	#define ATI_REG_CMD_SPDF_OUT_EN (1U<<4)
	94	#define ATI_REG_CMD_SPDF_STATUS_MEM (1U<<5)
	95	#define ATI_REG_CMD_SPDF_THRESHOLD (3U<<6)
	96	#define ATI_REG_CMD_SPDF_THRESHOLD_SHIFT 6
	97	#define ATI_REG_CMD_IN_DMA_EN (1U<<8)
	98	#define ATI_REG_CMD_OUT_DMA_EN (1U<<9)
	99	#define ATI_REG_CMD_SPDF_DMA_EN (1U<<10)
	100	#define ATI_REG_CMD_SPDF_OUT_STOPPED (1U<<11)
	101	#define ATI_REG_CMD_SPDF_CONFIG_MASK (7U<<12)
	102	#define ATI_REG_CMD_SPDF_CONFIG_34 (1U<<12)
	103	#define ATI_REG_CMD_SPDF_CONFIG_78 (2U<<12)
	104	#define ATI_REG_CMD_SPDF_CONFIG_69 (3U<<12)
	105	#define ATI_REG_CMD_SPDF_CONFIG_01 (4U<<12)
	106	#define ATI_REG_CMD_INTERLEAVE_SPDF (1U<<16)
	107	#define ATI_REG_CMD_AUDIO_PRESENT (1U<<20)
	108	#define ATI_REG_CMD_INTERLEAVE_IN (1U<<21)
	109	#define ATI_REG_CMD_INTERLEAVE_OUT (1U<<22)
	110	#define ATI_REG_CMD_LOOPBACK_EN (1U<<23)
	111	#define ATI_REG_CMD_PACKED_DIS (1U<<24)
	112	#define ATI_REG_CMD_BURST_EN (1U<<25)
	113	#define ATI_REG_CMD_PANIC_EN (1U<<26)
	114	#define ATI_REG_CMD_MODEM_PRESENT (1U<<27)
	115	#define ATI_REG_CMD_ACLINK_ACTIVE (1U<<28)
	116	#define ATI_REG_CMD_AC_SOFT_RESET (1U<<29)
	117	#define ATI_REG_CMD_AC_SYNC (1U<<30)
	118	#define ATI_REG_CMD_AC_RESET (1U<<31)
	119
	120	#define ATI_REG_PHYS_OUT_ADDR 0x0c
	121	#define ATI_REG_PHYS_OUT_CODEC_MASK (3U<<0)
	122	#define ATI_REG_PHYS_OUT_RW (1U<<2)
	123	#define ATI_REG_PHYS_OUT_ADDR_EN (1U<<8)
	124	#define ATI_REG_PHYS_OUT_ADDR_SHIFT 9
	125	#define ATI_REG_PHYS_OUT_DATA_SHIFT 16
	126
	127	#define ATI_REG_PHYS_IN_ADDR 0x10
	128	#define ATI_REG_PHYS_IN_READ_FLAG (1U<<8)
	129	#define ATI_REG_PHYS_IN_ADDR_SHIFT 9
	130	#define ATI_REG_PHYS_IN_DATA_SHIFT 16
	131
	132	#define ATI_REG_SLOTREQ 0x14
	133
	134	#define ATI_REG_COUNTER 0x18
	135	#define ATI_REG_COUNTER_SLOT (3U<<0) /* slot # */
	136	#define ATI_REG_COUNTER_BITCLOCK (31U<<8)
	137
	138	#define ATI_REG_IN_FIFO_THRESHOLD 0x1c
	139
	140	#define ATI_REG_IN_DMA_LINKPTR 0x20
	141	#define ATI_REG_IN_DMA_DT_START 0x24 /* RO */
	142	#define ATI_REG_IN_DMA_DT_NEXT 0x28 /* RO */
	143	#define ATI_REG_IN_DMA_DT_CUR 0x2c /* RO */
	144	#define ATI_REG_IN_DMA_DT_SIZE 0x30
	145
	146	#define ATI_REG_OUT_DMA_SLOT 0x34
	147	#define ATI_REG_OUT_DMA_SLOT_BIT(x) (1U << ((x) - 3))
	148	#define ATI_REG_OUT_DMA_SLOT_MASK 0x1ff
	149	#define ATI_REG_OUT_DMA_THRESHOLD_MASK 0xf800
	150	#define ATI_REG_OUT_DMA_THRESHOLD_SHIFT 11
	151
	152	#define ATI_REG_OUT_DMA_LINKPTR 0x38
	153	#define ATI_REG_OUT_DMA_DT_START 0x3c /* RO */
	154	#define ATI_REG_OUT_DMA_DT_NEXT 0x40 /* RO */
	155	#define ATI_REG_OUT_DMA_DT_CUR 0x44 /* RO */
	156	#define ATI_REG_OUT_DMA_DT_SIZE 0x48
	157
	158	#define ATI_REG_SPDF_CMD 0x4c
	159	#define ATI_REG_SPDF_CMD_LFSR (1U<<4)
	160	#define ATI_REG_SPDF_CMD_SINGLE_CH (1U<<5)
	161	#define ATI_REG_SPDF_CMD_LFSR_ACC (0xff<<8) /* RO */
	162
	163	#define ATI_REG_SPDF_DMA_LINKPTR 0x50
	164	#define ATI_REG_SPDF_DMA_DT_START 0x54 /* RO */
	165	#define ATI_REG_SPDF_DMA_DT_NEXT 0x58 /* RO */
	166	#define ATI_REG_SPDF_DMA_DT_CUR 0x5c /* RO */
	167	#define ATI_REG_SPDF_DMA_DT_SIZE 0x60
	168
	169	#define ATI_REG_MODEM_MIRROR 0x7c
	170	#define ATI_REG_AUDIO_MIRROR 0x80
	171
	172	#define ATI_REG_6CH_REORDER 0x84 /* reorder slots for 6ch */
	173	#define ATI_REG_6CH_REORDER_EN (1U<<0) /* 3,4,7,8,6,9 -> 3,4,6,9,7,8 */
	174
	175	#define ATI_REG_FIFO_FLUSH 0x88
	176	#define ATI_REG_FIFO_OUT_FLUSH (1U<<0)
	177	#define ATI_REG_FIFO_IN_FLUSH (1U<<1)
	178
	179	/* LINKPTR */
	180	#define ATI_REG_LINKPTR_EN (1U<<0)
	181
	182	/* [INT\|OUT\|SPDIF]_DMA_DT_SIZE */
	183	#define ATI_REG_DMA_DT_SIZE (0xffffU<<0)
	184	#define ATI_REG_DMA_FIFO_USED (0x1fU<<16)
	185	#define ATI_REG_DMA_FIFO_FREE (0x1fU<<21)
	186	#define ATI_REG_DMA_STATE (7U<<26)
	187
	188
	189	#define ATI_MAX_DESCRIPTORS 256 /* max number of descriptor packets */
	190
	191
[70]	192	struct atiixp;
[32]	193
	194	/*
	195	* DMA packate descriptor
	196	*/
	197
[70]	198	struct atiixp_dma_desc {
[679]	199	__le32 addr; /* DMA buffer address */
[32]	200	u16 status; /* status bits */
	201	u16 size; /* size of the packet in dwords */
[679]	202	__le32 next; /* address of the next packet descriptor */
[70]	203	};
[32]	204
	205	/*
	206	* stream enum
	207	*/
	208	enum { ATI_DMA_PLAYBACK, ATI_DMA_CAPTURE, ATI_DMA_SPDIF, NUM_ATI_DMAS }; /* DMAs */
	209	enum { ATI_PCM_OUT, ATI_PCM_IN, ATI_PCM_SPDIF, NUM_ATI_PCMS }; /* AC97 pcm slots */
	210	enum { ATI_PCMDEV_ANALOG, ATI_PCMDEV_DIGITAL, NUM_ATI_PCMDEVS }; /* pcm devices */
	211
	212	#define NUM_ATI_CODECS 3
	213
	214
	215	/*
	216	* constants and callbacks for each DMA type
	217	*/
[70]	218	struct atiixp_dma_ops {
[32]	219	int type; /* ATI_DMA_XXX */
	220	unsigned int llp_offset; /* LINKPTR offset */
	221	unsigned int dt_cur; /* DT_CUR offset */
[70]	222	/* called from open callback */
	223	void (enable_dma)(struct atiixp chip, int on);
	224	/* called from trigger (START/STOP) */
	225	void (enable_transfer)(struct atiixp chip, int on);
	226	/* called from trigger (STOP only) */
	227	void (flush_dma)(struct atiixp chip);
[32]	228	};
	229
	230	/*
	231	* DMA stream
	232	*/
[70]	233	struct atiixp_dma {
	234	const struct atiixp_dma_ops *ops;
[32]	235	struct snd_dma_buffer desc_buf;
[70]	236	struct snd_pcm_substream substream; / assigned PCM substream */
[32]	237	unsigned int buf_addr, buf_bytes; /* DMA buffer address, bytes */
	238	unsigned int period_bytes, periods;
	239	int opened;
[70]	240	int running;
	241	int suspended;
[32]	242	int pcm_open_flag;
[70]	243	int ac97_pcm_type; /* index # of ac97_pcm to access, -1 = not used */
	244	unsigned int saved_curptr;
[32]	245	};
	246
	247	/*
	248	* ATI IXP chip
	249	*/
[70]	250	struct atiixp {
	251	struct snd_card *card;
[32]	252	struct pci_dev *pci;
	253
	254	unsigned long addr;
	255	void __iomem *remap_addr;
	256	int irq;
[70]	257
	258	struct snd_ac97_bus *ac97_bus;
	259	struct snd_ac97 *ac97[NUM_ATI_CODECS];
[32]	260
	261	spinlock_t reg_lock;
	262
[70]	263	struct atiixp_dma dmas[NUM_ATI_DMAS];
[32]	264	struct ac97_pcm *pcms[NUM_ATI_PCMS];
[70]	265	struct snd_pcm *pcmdevs[NUM_ATI_PCMDEVS];
[32]	266
	267	int max_channels; /* max. channels for PCM out */
	268
	269	unsigned int codec_not_ready_bits; /* for codec detection */
	270
	271	int spdif_over_aclink; /* passed from the module option */
[305]	272	struct mutex open_mutex; /* playback open mutex */
[32]	273	};
	274
	275
	276	/*
	277	*/
[679]	278	static const struct pci_device_id snd_atiixp_ids[] = {
[464]	279	{ PCI_VDEVICE(ATI, 0x4341), 0 }, /* SB200 */
	280	{ PCI_VDEVICE(ATI, 0x4361), 0 }, /* SB300 */
	281	{ PCI_VDEVICE(ATI, 0x4370), 0 }, /* SB400 */
	282	{ PCI_VDEVICE(ATI, 0x4382), 0 }, /* SB600 */
[32]	283	{ 0, }
	284	};
	285
	286	MODULE_DEVICE_TABLE(pci, snd_atiixp_ids);
	287
[679]	288	static const struct snd_pci_quirk atiixp_quirks[] = {
[598]	289	SND_PCI_QUIRK(0x105b, 0x0c81, "Foxconn RC4107MA-RS2", 0),
[305]	290	SND_PCI_QUIRK(0x15bd, 0x3100, "DFI RS482", 0),
	291	{0} /* terminator */
	292	};
[32]	293
	294	/*
	295	* lowlevel functions
	296	*/
	297
	298	/*
	299	* update the bits of the given register.
	300	* return 1 if the bits changed.
	301	*/
[70]	302	static int snd_atiixp_update_bits(struct atiixp *chip, unsigned int reg,
[32]	303	unsigned int mask, unsigned int value)
	304	{
[305]	305	void __iomem *addr = chip->remap_addr + reg;
[32]	306	unsigned int data, old_data;
	307	old_data = data = readl(addr);
	308	data &= ~mask;
	309	data \|= value;
	310	if (old_data == data)
	311	return 0;
	312	writel(data, addr);
	313	return 1;
	314	}
	315
	316	/*
	317	* macros for easy use
	318	*/
	319	#define atiixp_write(chip,reg,value) \
[305]	320	writel(value, chip->remap_addr + ATI_REG_##reg)
[32]	321	#define atiixp_read(chip,reg) \
[305]	322	readl(chip->remap_addr + ATI_REG_##reg)
[32]	323	#define atiixp_update(chip,reg,mask,val) \
	324	snd_atiixp_update_bits(chip, ATI_REG_##reg, mask, val)
	325
	326	/*
	327	* handling DMA packets
	328	*
	329	* we allocate a linear buffer for the DMA, and split it to each packet.
	330	* in a future version, a scatter-gather buffer should be implemented.
	331	*/
	332
	333	#define ATI_DESC_LIST_SIZE \
[70]	334	PAGE_ALIGN(ATI_MAX_DESCRIPTORS * sizeof(struct atiixp_dma_desc))
[32]	335
	336	/*
	337	* build packets ring for the given buffer size.
	338	*
	339	* IXP handles the buffer descriptors, which are connected as a linked
	340	* list. although we can change the list dynamically, in this version,
	341	* a static RING of buffer descriptors is used.
	342	*
[679]	343	* the ring is built in this function, and is set up to the hardware.
[32]	344	*/
[70]	345	static int atiixp_build_dma_packets(struct atiixp chip, struct atiixp_dma dma,
	346	struct snd_pcm_substream *substream,
	347	unsigned int periods,
	348	unsigned int period_bytes)
[32]	349	{
	350	unsigned int i;
	351	u32 addr, desc_addr;
	352	unsigned long flags;
	353
	354	if (periods > ATI_MAX_DESCRIPTORS)
	355	return -ENOMEM;
	356
	357	if (dma->desc_buf.area == NULL) {
[70]	358	if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
[679]	359	&chip->pci->dev,
[70]	360	ATI_DESC_LIST_SIZE,
	361	&dma->desc_buf) < 0)
[32]	362	return -ENOMEM;
	363	dma->period_bytes = dma->periods = 0; /* clear */
	364	}
	365
[598]	366	if (dma->periods == periods && dma->period_bytes == period_bytes) {
[488]	367	writel((u32)dma->desc_buf.addr \| ATI_REG_LINKPTR_EN,
	368	(char*)chip->remap_addr + dma->ops->llp_offset);
[305]	369	return 0;
[488]	370	}
[305]	371
[32]	372	/* reset DMA before changing the descriptor table */
	373	spin_lock_irqsave(&chip->reg_lock, flags);
[305]	374	writel(0, chip->remap_addr + dma->ops->llp_offset);
[32]	375	dma->ops->enable_dma(chip, 0);
	376	dma->ops->enable_dma(chip, 1);
	377	spin_unlock_irqrestore(&chip->reg_lock, flags);
	378
	379	/* fill the entries */
	380	addr = (u32)substream->runtime->dma_addr;
	381	desc_addr = (u32)dma->desc_buf.addr;
	382	for (i = 0; i < periods; i++) {
[70]	383	struct atiixp_dma_desc *desc;
	384	desc = &((struct atiixp_dma_desc *)dma->desc_buf.area)[i];
[32]	385	desc->addr = cpu_to_le32(addr);
	386	desc->status = 0;
	387	desc->size = period_bytes >> 2; /* in dwords */
[70]	388	desc_addr += sizeof(struct atiixp_dma_desc);
[32]	389	if (i == periods - 1)
	390	desc->next = cpu_to_le32((u32)dma->desc_buf.addr);
	391	else
	392	desc->next = cpu_to_le32(desc_addr);
	393	addr += period_bytes;
	394	}
	395
	396	writel((u32)dma->desc_buf.addr \| ATI_REG_LINKPTR_EN,
[305]	397	chip->remap_addr + dma->ops->llp_offset);
[32]	398
	399	dma->period_bytes = period_bytes;
	400	dma->periods = periods;
	401
	402	return 0;
	403	}
	404
	405	/*
	406	* remove the ring buffer and release it if assigned
	407	*/
[70]	408	static void atiixp_clear_dma_packets(struct atiixp chip, struct atiixp_dma dma,
	409	struct snd_pcm_substream *substream)
[32]	410	{
	411	if (dma->desc_buf.area) {
[305]	412	writel(0, chip->remap_addr + dma->ops->llp_offset);
[32]	413	snd_dma_free_pages(&dma->desc_buf);
	414	dma->desc_buf.area = NULL;
	415	}
	416	}
	417
	418	/*
	419	* AC97 interface
	420	*/
[70]	421	static int snd_atiixp_acquire_codec(struct atiixp *chip)
[32]	422	{
	423	int timeout = 1000;
	424
	425	while (atiixp_read(chip, PHYS_OUT_ADDR) & ATI_REG_PHYS_OUT_ADDR_EN) {
	426	if (! timeout--) {
[679]	427	dev_warn(chip->card->dev, "codec acquire timeout\n");
[32]	428	return -EBUSY;
	429	}
	430	udelay(1);
	431	}
	432	return 0;
	433	}
	434
[70]	435	static unsigned short snd_atiixp_codec_read(struct atiixp *chip, unsigned short codec, unsigned short reg)
[32]	436	{
	437	unsigned int data;
	438	int timeout;
	439
	440	if (snd_atiixp_acquire_codec(chip) < 0)
	441	return 0xffff;
	442	data = (reg << ATI_REG_PHYS_OUT_ADDR_SHIFT) \|
	443	ATI_REG_PHYS_OUT_ADDR_EN \|
	444	ATI_REG_PHYS_OUT_RW \|
	445	codec;
	446	atiixp_write(chip, PHYS_OUT_ADDR, data);
	447	if (snd_atiixp_acquire_codec(chip) < 0)
	448	return 0xffff;
	449	timeout = 1000;
	450	do {
	451	data = atiixp_read(chip, PHYS_IN_ADDR);
	452	if (data & ATI_REG_PHYS_IN_READ_FLAG)
	453	return data >> ATI_REG_PHYS_IN_DATA_SHIFT;
	454	udelay(1);
	455	} while (--timeout);
	456	/* time out may happen during reset */
	457	if (reg < 0x7c)
[679]	458	dev_warn(chip->card->dev, "codec read timeout (reg %x)\n", reg);
[32]	459	return 0xffff;
	460	}
	461
	462
[70]	463	static void snd_atiixp_codec_write(struct atiixp *chip, unsigned short codec,
	464	unsigned short reg, unsigned short val)
[32]	465	{
	466	unsigned int data;
[679]	467
[32]	468	if (snd_atiixp_acquire_codec(chip) < 0)
	469	return;
	470	data = ((unsigned int)val << ATI_REG_PHYS_OUT_DATA_SHIFT) \|
	471	((unsigned int)reg << ATI_REG_PHYS_OUT_ADDR_SHIFT) \|
	472	ATI_REG_PHYS_OUT_ADDR_EN \| codec;
	473	atiixp_write(chip, PHYS_OUT_ADDR, data);
	474	}
	475
	476
[70]	477	static unsigned short snd_atiixp_ac97_read(struct snd_ac97 *ac97,
	478	unsigned short reg)
[32]	479	{
[70]	480	struct atiixp *chip = ac97->private_data;
	481	return snd_atiixp_codec_read(chip, ac97->num, reg);
[679]	482
[32]	483	}
	484
[70]	485	static void snd_atiixp_ac97_write(struct snd_ac97 *ac97, unsigned short reg,
	486	unsigned short val)
[32]	487	{
[70]	488	struct atiixp *chip = ac97->private_data;
[32]	489	snd_atiixp_codec_write(chip, ac97->num, reg, val);
	490	}
	491
	492	/*
	493	* reset AC link
	494	*/
[70]	495	static int snd_atiixp_aclink_reset(struct atiixp *chip)
[32]	496	{
	497	int timeout;
	498
	499	/* reset powerdoewn */
	500	if (atiixp_update(chip, CMD, ATI_REG_CMD_POWERDOWN, 0))
	501	udelay(10);
	502
	503	/* perform a software reset */
	504	atiixp_update(chip, CMD, ATI_REG_CMD_AC_SOFT_RESET, ATI_REG_CMD_AC_SOFT_RESET);
[522]	505	#pragma disable_message (302)
[32]	506	atiixp_read(chip, CMD);
	507	udelay(10);
	508	atiixp_update(chip, CMD, ATI_REG_CMD_AC_SOFT_RESET, 0);
[679]	509
[32]	510	timeout = 10;
	511	while (! (atiixp_read(chip, CMD) & ATI_REG_CMD_ACLINK_ACTIVE)) {
	512	/* do a hard reset */
	513	atiixp_update(chip, CMD, ATI_REG_CMD_AC_SYNC\|ATI_REG_CMD_AC_RESET,
	514	ATI_REG_CMD_AC_SYNC);
	515	atiixp_read(chip, CMD);
[70]	516	mdelay(1);
[32]	517	atiixp_update(chip, CMD, ATI_REG_CMD_AC_RESET, ATI_REG_CMD_AC_RESET);
[679]	518	if (!--timeout) {
	519	dev_err(chip->card->dev, "codec reset timeout\n");
[32]	520	break;
	521	}
	522	}
[522]	523	#pragma enable_message (302)
[32]	524
	525	/* deassert RESET and assert SYNC to make sure */
	526	atiixp_update(chip, CMD, ATI_REG_CMD_AC_SYNC\|ATI_REG_CMD_AC_RESET,
	527	ATI_REG_CMD_AC_SYNC\|ATI_REG_CMD_AC_RESET);
	528
	529	return 0;
	530	}
	531
[70]	532	static int snd_atiixp_aclink_down(struct atiixp *chip)
[32]	533	{
	534	// if (atiixp_read(chip, MODEM_MIRROR) & 0x1) /* modem running, too? */
	535	// return -EBUSY;
	536	atiixp_update(chip, CMD,
	537	ATI_REG_CMD_POWERDOWN \| ATI_REG_CMD_AC_RESET,
	538	ATI_REG_CMD_POWERDOWN);
	539	return 0;
	540	}
	541
	542	/*
	543	* auto-detection of codecs
	544	*
	545	* the IXP chip can generate interrupts for the non-existing codecs.
	546	* NEW_FRAME interrupt is used to make sure that the interrupt is generated
	547	* even if all three codecs are connected.
	548	*/
	549
	550	#define ALL_CODEC_NOT_READY \
	551	(ATI_REG_ISR_CODEC0_NOT_READY \|\
	552	ATI_REG_ISR_CODEC1_NOT_READY \|\
	553	ATI_REG_ISR_CODEC2_NOT_READY)
	554	#define CODEC_CHECK_BITS (ALL_CODEC_NOT_READY\|ATI_REG_ISR_NEW_FRAME)
	555
[679]	556	static int ac97_probing_bugs(struct pci_dev *pci)
[32]	557	{
[305]	558	const struct snd_pci_quirk *q;
	559
	560	q = snd_pci_quirk_lookup(pci, atiixp_quirks);
	561	if (q) {
[679]	562	dev_dbg(&pci->dev, "atiixp quirk for %s. Forcing codec %d\n",
	563	snd_pci_quirk_name(q), q->value);
[305]	564	return q->value;
	565	}
	566	/* this hardware doesn't need workarounds. Probe for codec */
	567	return -1;
	568	}
	569
[679]	570	static int snd_atiixp_codec_detect(struct atiixp *chip)
[305]	571	{
[32]	572	int timeout;
	573
	574	chip->codec_not_ready_bits = 0;
[305]	575	if (ac97_codec == -1)
	576	ac97_codec = ac97_probing_bugs(chip->pci);
	577	if (ac97_codec >= 0) {
[488]	578	chip->codec_not_ready_bits \|=
[305]	579	CODEC_CHECK_BITS ^ (1 << (ac97_codec + 10));
	580	return 0;
	581	}
	582
[32]	583	atiixp_write(chip, IER, CODEC_CHECK_BITS);
	584	/* wait for the interrupts */
	585	timeout = 50;
	586	while (timeout-- > 0) {
[70]	587	mdelay(1);
[32]	588	if (chip->codec_not_ready_bits)
	589	break;
	590	}
	591	atiixp_write(chip, IER, 0); /* disable irqs */
	592
	593	if ((chip->codec_not_ready_bits & ALL_CODEC_NOT_READY) == ALL_CODEC_NOT_READY) {
[679]	594	dev_err(chip->card->dev, "no codec detected!\n");
[32]	595	return -ENXIO;
	596	}
	597	return 0;
	598	}
	599
	600
	601	/*
	602	* enable DMA and irqs
	603	*/
[70]	604	static int snd_atiixp_chip_start(struct atiixp *chip)
[32]	605	{
	606	unsigned int reg;
	607
	608	/* set up spdif, enable burst mode */
	609	reg = atiixp_read(chip, CMD);
	610	reg \|= 0x02 << ATI_REG_CMD_SPDF_THRESHOLD_SHIFT;
	611	reg \|= ATI_REG_CMD_BURST_EN;
	612	atiixp_write(chip, CMD, reg);
	613
	614	reg = atiixp_read(chip, SPDF_CMD);
	615	reg &= ~(ATI_REG_SPDF_CMD_LFSR\|ATI_REG_SPDF_CMD_SINGLE_CH);
	616	atiixp_write(chip, SPDF_CMD, reg);
	617
	618	/* clear all interrupt source */
	619	atiixp_write(chip, ISR, 0xffffffff);
	620	/* enable irqs */
	621	atiixp_write(chip, IER,
	622	ATI_REG_IER_IO_STATUS_EN \|
	623	ATI_REG_IER_IN_XRUN_EN \|
	624	ATI_REG_IER_OUT_XRUN_EN \|
	625	ATI_REG_IER_SPDF_XRUN_EN \|
	626	ATI_REG_IER_SPDF_STATUS_EN);
	627	return 0;
	628	}
	629
	630
	631	/*
	632	* disable DMA and IRQs
	633	*/
[70]	634	static int snd_atiixp_chip_stop(struct atiixp *chip)
[32]	635	{
	636	/* clear interrupt source */
	637	atiixp_write(chip, ISR, atiixp_read(chip, ISR));
	638	/* disable irqs */
	639	atiixp_write(chip, IER, 0);
	640	return 0;
	641	}
	642
	643
	644	/*
	645	* PCM section
	646	*/
	647
	648	/*
	649	* pointer callback simplly reads XXX_DMA_DT_CUR register as the current
	650	* position. when SG-buffer is implemented, the offset must be calculated
	651	* correctly...
	652	*/
[70]	653	static snd_pcm_uframes_t snd_atiixp_pcm_pointer(struct snd_pcm_substream *substream)
[32]	654	{
[70]	655	struct atiixp *chip = snd_pcm_substream_chip(substream);
	656	struct snd_pcm_runtime *runtime = substream->runtime;
	657	struct atiixp_dma *dma = runtime->private_data;
	658	unsigned int curptr;
	659	int timeout = 1000;
[32]	660
[70]	661	while (timeout--) {
[305]	662	curptr = readl(chip->remap_addr + dma->ops->dt_cur);
[70]	663	if (curptr < dma->buf_addr)
	664	continue;
	665	curptr -= dma->buf_addr;
	666	if (curptr >= dma->buf_bytes)
	667	continue;
	668	return bytes_to_frames(runtime, curptr);
	669	}
[679]	670	dev_dbg(chip->card->dev, "invalid DMA pointer read 0x%x (buf=%x)\n",
[305]	671	readl(chip->remap_addr + dma->ops->dt_cur), dma->buf_addr);
[70]	672	return 0;
[32]	673	}
	674
	675	/*
	676	* XRUN detected, and stop the PCM substream
	677	*/
[70]	678	static void snd_atiixp_xrun_dma(struct atiixp chip, struct atiixp_dma dma)
[32]	679	{
	680	if (! dma->substream \|\| ! dma->running)
	681	return;
[679]	682	dev_dbg(chip->card->dev, "XRUN detected (DMA %d)\n", dma->ops->type);
	683	snd_pcm_stop_xrun(dma->substream);
[32]	684	}
	685
	686	/*
	687	* the period ack. update the substream.
	688	*/
[70]	689	static void snd_atiixp_update_dma(struct atiixp chip, struct atiixp_dma dma)
[32]	690	{
	691	if (! dma->substream \|\| ! dma->running)
	692	return;
	693	snd_pcm_period_elapsed(dma->substream);
	694	}
	695
	696	/* set BUS_BUSY interrupt bit if any DMA is running */
	697	/* call with spinlock held */
[70]	698	static void snd_atiixp_check_bus_busy(struct atiixp *chip)
[32]	699	{
	700	unsigned int bus_busy;
	701	if (atiixp_read(chip, CMD) & (ATI_REG_CMD_SEND_EN \|
	702	ATI_REG_CMD_RECEIVE_EN \|
	703	ATI_REG_CMD_SPDF_OUT_EN))
	704	bus_busy = ATI_REG_IER_SET_BUS_BUSY;
	705	else
	706	bus_busy = 0;
	707	atiixp_update(chip, IER, ATI_REG_IER_SET_BUS_BUSY, bus_busy);
	708	}
	709
	710	/* common trigger callback
	711	* calling the lowlevel callbacks in it
	712	*/
[70]	713	static int snd_atiixp_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
[32]	714	{
[70]	715	struct atiixp *chip = snd_pcm_substream_chip(substream);
	716	struct atiixp_dma *dma = substream->runtime->private_data;
[32]	717	int err = 0;
	718
[399]	719	if (snd_BUG_ON(!dma->ops->enable_transfer \|\|
	720	!dma->ops->flush_dma))
	721	return -EINVAL;
[32]	722
	723	spin_lock(&chip->reg_lock);
	724	switch (cmd) {
[70]	725	case SNDRV_PCM_TRIGGER_START:
	726	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
	727	case SNDRV_PCM_TRIGGER_RESUME:
[679]	728	if (dma->running && dma->suspended &&
	729	cmd == SNDRV_PCM_TRIGGER_RESUME)
	730	writel(dma->saved_curptr, chip->remap_addr +
	731	dma->ops->dt_cur);
[32]	732	dma->ops->enable_transfer(chip, 1);
[70]	733	dma->running = 1;
	734	dma->suspended = 0;
[32]	735	break;
[70]	736	case SNDRV_PCM_TRIGGER_STOP:
	737	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
	738	case SNDRV_PCM_TRIGGER_SUSPEND:
[679]	739	dma->suspended = cmd == SNDRV_PCM_TRIGGER_SUSPEND;
	740	if (dma->running && dma->suspended)
	741	dma->saved_curptr = readl(chip->remap_addr +
	742	dma->ops->dt_cur);
[32]	743	dma->ops->enable_transfer(chip, 0);
[70]	744	dma->running = 0;
[32]	745	break;
	746	default:
	747	err = -EINVAL;
	748	break;
	749	}
	750	if (! err) {
	751	snd_atiixp_check_bus_busy(chip);
	752	if (cmd == SNDRV_PCM_TRIGGER_STOP) {
	753	dma->ops->flush_dma(chip);
	754	snd_atiixp_check_bus_busy(chip);
	755	}
	756	}
	757	spin_unlock(&chip->reg_lock);
	758	return err;
	759	}
	760
	761
	762	/*
	763	* lowlevel callbacks for each DMA type
	764	*
	765	* every callback is supposed to be called in chip->reg_lock spinlock
	766	*/
	767
	768	/* flush FIFO of analog OUT DMA */
[70]	769	static void atiixp_out_flush_dma(struct atiixp *chip)
[32]	770	{
	771	atiixp_write(chip, FIFO_FLUSH, ATI_REG_FIFO_OUT_FLUSH);
	772	}
	773
	774	/* enable/disable analog OUT DMA */
[70]	775	static void atiixp_out_enable_dma(struct atiixp *chip, int on)
[32]	776	{
	777	unsigned int data;
	778	data = atiixp_read(chip, CMD);
	779	if (on) {
	780	if (data & ATI_REG_CMD_OUT_DMA_EN)
	781	return;
	782	atiixp_out_flush_dma(chip);
	783	data \|= ATI_REG_CMD_OUT_DMA_EN;
	784	} else
	785	data &= ~ATI_REG_CMD_OUT_DMA_EN;
	786	atiixp_write(chip, CMD, data);
	787	}
	788
	789	/* start/stop transfer over OUT DMA */
[70]	790	static void atiixp_out_enable_transfer(struct atiixp *chip, int on)
[32]	791	{
	792	atiixp_update(chip, CMD, ATI_REG_CMD_SEND_EN,
	793	on ? ATI_REG_CMD_SEND_EN : 0);
	794	}
	795
	796	/* enable/disable analog IN DMA */
[70]	797	static void atiixp_in_enable_dma(struct atiixp *chip, int on)
[32]	798	{
	799	atiixp_update(chip, CMD, ATI_REG_CMD_IN_DMA_EN,
	800	on ? ATI_REG_CMD_IN_DMA_EN : 0);
	801	}
	802
	803	/* start/stop analog IN DMA */
[70]	804	static void atiixp_in_enable_transfer(struct atiixp *chip, int on)
[32]	805	{
	806	if (on) {
	807	unsigned int data = atiixp_read(chip, CMD);
	808	if (! (data & ATI_REG_CMD_RECEIVE_EN)) {
	809	data \|= ATI_REG_CMD_RECEIVE_EN;
	810	#if 0 /* FIXME: this causes the endless loop */
	811	/* wait until slot 3/4 are finished */
	812	while ((atiixp_read(chip, COUNTER) &
	813	ATI_REG_COUNTER_SLOT) != 5)
	814	;
	815	#endif
	816	atiixp_write(chip, CMD, data);
	817	}
	818	} else
	819	atiixp_update(chip, CMD, ATI_REG_CMD_RECEIVE_EN, 0);
	820	}
	821
	822	/* flush FIFO of analog IN DMA */
[70]	823	static void atiixp_in_flush_dma(struct atiixp *chip)
[32]	824	{
	825	atiixp_write(chip, FIFO_FLUSH, ATI_REG_FIFO_IN_FLUSH);
	826	}
	827
	828	/* enable/disable SPDIF OUT DMA */
[70]	829	static void atiixp_spdif_enable_dma(struct atiixp *chip, int on)
[32]	830	{
	831	atiixp_update(chip, CMD, ATI_REG_CMD_SPDF_DMA_EN,
	832	on ? ATI_REG_CMD_SPDF_DMA_EN : 0);
	833	}
	834
	835	/* start/stop SPDIF OUT DMA */
[70]	836	static void atiixp_spdif_enable_transfer(struct atiixp *chip, int on)
[32]	837	{
	838	unsigned int data;
	839	data = atiixp_read(chip, CMD);
	840	if (on)
	841	data \|= ATI_REG_CMD_SPDF_OUT_EN;
	842	else
	843	data &= ~ATI_REG_CMD_SPDF_OUT_EN;
	844	atiixp_write(chip, CMD, data);
	845	}
	846
	847	/* flush FIFO of SPDIF OUT DMA */
[70]	848	static void atiixp_spdif_flush_dma(struct atiixp *chip)
[32]	849	{
	850	int timeout;
	851
	852	/* DMA off, transfer on */
	853	atiixp_spdif_enable_dma(chip, 0);
	854	atiixp_spdif_enable_transfer(chip, 1);
[70]	855
[32]	856	timeout = 100;
	857	do {
	858	if (! (atiixp_read(chip, SPDF_DMA_DT_SIZE) & ATI_REG_DMA_FIFO_USED))
	859	break;
	860	udelay(1);
	861	} while (timeout-- > 0);
	862
	863	atiixp_spdif_enable_transfer(chip, 0);
	864	}
	865
	866	/* set up slots and formats for SPDIF OUT */
[70]	867	static int snd_atiixp_spdif_prepare(struct snd_pcm_substream *substream)
[32]	868	{
[70]	869	struct atiixp *chip = snd_pcm_substream_chip(substream);
[32]	870
	871	spin_lock_irq(&chip->reg_lock);
	872	if (chip->spdif_over_aclink) {
	873	unsigned int data;
	874	/* enable slots 10/11 */
	875	atiixp_update(chip, CMD, ATI_REG_CMD_SPDF_CONFIG_MASK,
	876	ATI_REG_CMD_SPDF_CONFIG_01);
	877	data = atiixp_read(chip, OUT_DMA_SLOT) & ~ATI_REG_OUT_DMA_SLOT_MASK;
	878	data \|= ATI_REG_OUT_DMA_SLOT_BIT(10) \|
	879	ATI_REG_OUT_DMA_SLOT_BIT(11);
	880	data \|= 0x04 << ATI_REG_OUT_DMA_THRESHOLD_SHIFT;
	881	atiixp_write(chip, OUT_DMA_SLOT, data);
	882	atiixp_update(chip, CMD, ATI_REG_CMD_INTERLEAVE_OUT,
	883	substream->runtime->format == SNDRV_PCM_FORMAT_S16_LE ?
	884	ATI_REG_CMD_INTERLEAVE_OUT : 0);
	885	} else {
	886	atiixp_update(chip, CMD, ATI_REG_CMD_SPDF_CONFIG_MASK, 0);
	887	atiixp_update(chip, CMD, ATI_REG_CMD_INTERLEAVE_SPDF, 0);
	888	}
	889	spin_unlock_irq(&chip->reg_lock);
	890	return 0;
	891	}
	892
	893	/* set up slots and formats for analog OUT */
[70]	894	static int snd_atiixp_playback_prepare(struct snd_pcm_substream *substream)
[32]	895	{
[70]	896	struct atiixp *chip = snd_pcm_substream_chip(substream);
[32]	897	unsigned int data;
	898
	899	spin_lock_irq(&chip->reg_lock);
	900	data = atiixp_read(chip, OUT_DMA_SLOT) & ~ATI_REG_OUT_DMA_SLOT_MASK;
	901	switch (substream->runtime->channels) {
	902	case 8:
	903	data \|= ATI_REG_OUT_DMA_SLOT_BIT(10) \|
	904	ATI_REG_OUT_DMA_SLOT_BIT(11);
[679]	905	fallthrough;
[32]	906	case 6:
	907	data \|= ATI_REG_OUT_DMA_SLOT_BIT(7) \|
	908	ATI_REG_OUT_DMA_SLOT_BIT(8);
[679]	909	fallthrough;
[32]	910	case 4:
	911	data \|= ATI_REG_OUT_DMA_SLOT_BIT(6) \|
	912	ATI_REG_OUT_DMA_SLOT_BIT(9);
[679]	913	fallthrough;
[32]	914	default:
	915	data \|= ATI_REG_OUT_DMA_SLOT_BIT(3) \|
	916	ATI_REG_OUT_DMA_SLOT_BIT(4);
	917	break;
	918	}
	919
	920	/* set output threshold */
	921	data \|= 0x04 << ATI_REG_OUT_DMA_THRESHOLD_SHIFT;
	922	atiixp_write(chip, OUT_DMA_SLOT, data);
	923
	924	atiixp_update(chip, CMD, ATI_REG_CMD_INTERLEAVE_OUT,
	925	substream->runtime->format == SNDRV_PCM_FORMAT_S16_LE ?
	926	ATI_REG_CMD_INTERLEAVE_OUT : 0);
	927
	928	/*
	929	* enable 6 channel re-ordering bit if needed
	930	*/
	931	atiixp_update(chip, 6CH_REORDER, ATI_REG_6CH_REORDER_EN,
	932	substream->runtime->channels >= 6 ? ATI_REG_6CH_REORDER_EN: 0);
[679]	933
[32]	934	spin_unlock_irq(&chip->reg_lock);
	935	return 0;
	936	}
	937
	938	/* set up slots and formats for analog IN */
[70]	939	static int snd_atiixp_capture_prepare(struct snd_pcm_substream *substream)
[32]	940	{
[70]	941	struct atiixp *chip = snd_pcm_substream_chip(substream);
[32]	942
	943	spin_lock_irq(&chip->reg_lock);
	944	atiixp_update(chip, CMD, ATI_REG_CMD_INTERLEAVE_IN,
	945	substream->runtime->format == SNDRV_PCM_FORMAT_S16_LE ?
	946	ATI_REG_CMD_INTERLEAVE_IN : 0);
	947	spin_unlock_irq(&chip->reg_lock);
	948	return 0;
	949	}
	950
	951	/*
	952	* hw_params - allocate the buffer and set up buffer descriptors
	953	*/
[70]	954	static int snd_atiixp_pcm_hw_params(struct snd_pcm_substream *substream,
	955	struct snd_pcm_hw_params *hw_params)
[32]	956	{
[70]	957	struct atiixp *chip = snd_pcm_substream_chip(substream);
	958	struct atiixp_dma *dma = substream->runtime->private_data;
[32]	959	int err;
	960
	961	dma->buf_addr = substream->runtime->dma_addr;
	962	dma->buf_bytes = params_buffer_bytes(hw_params);
	963
	964	err = atiixp_build_dma_packets(chip, dma, substream,
	965	params_periods(hw_params),
	966	params_period_bytes(hw_params));
	967	if (err < 0)
	968	return err;
	969
	970	if (dma->ac97_pcm_type >= 0) {
	971	struct ac97_pcm *pcm = chip->pcms[dma->ac97_pcm_type];
	972	/* PCM is bound to AC97 codec(s)
	973	* set up the AC97 codecs
	974	*/
	975	if (dma->pcm_open_flag) {
	976	snd_ac97_pcm_close(pcm);
	977	dma->pcm_open_flag = 0;
	978	}
	979	err = snd_ac97_pcm_open(pcm, params_rate(hw_params),
	980	params_channels(hw_params),
	981	pcm->r[0].slots);
	982	if (err >= 0)
	983	dma->pcm_open_flag = 1;
	984	}
	985
	986	return err;
	987	}
	988
[70]	989	static int snd_atiixp_pcm_hw_free(struct snd_pcm_substream *substream)
[32]	990	{
[70]	991	struct atiixp *chip = snd_pcm_substream_chip(substream);
	992	struct atiixp_dma *dma = substream->runtime->private_data;
[32]	993
	994	if (dma->pcm_open_flag) {
	995	struct ac97_pcm *pcm = chip->pcms[dma->ac97_pcm_type];
	996	snd_ac97_pcm_close(pcm);
	997	dma->pcm_open_flag = 0;
	998	}
	999	atiixp_clear_dma_packets(chip, dma, substream);
	1000	return 0;
	1001	}
	1002
	1003
	1004	/*
	1005	* pcm hardware definition, identical for all DMA types
	1006	*/
[679]	1007	static const struct snd_pcm_hardware snd_atiixp_pcm_hw =
[32]	1008	{
[70]	1009	.info = (SNDRV_PCM_INFO_MMAP \| SNDRV_PCM_INFO_INTERLEAVED \|
	1010	SNDRV_PCM_INFO_BLOCK_TRANSFER \|
	1011	SNDRV_PCM_INFO_PAUSE \|
[32]	1012	SNDRV_PCM_INFO_RESUME \|
	1013	SNDRV_PCM_INFO_MMAP_VALID),
[70]	1014	.formats = SNDRV_PCM_FMTBIT_S16_LE \| SNDRV_PCM_FMTBIT_S32_LE,
	1015	.rates = SNDRV_PCM_RATE_48000,
	1016	.rate_min = 48000,
	1017	.rate_max = 48000,
	1018	.channels_min = 2,
	1019	.channels_max = 2,
	1020	.buffer_bytes_max = 256 * 1024,
	1021	.period_bytes_min = 32,
	1022	.period_bytes_max = 128 * 1024,
	1023	.periods_min = 2,
	1024	.periods_max = ATI_MAX_DESCRIPTORS,
[32]	1025	};
	1026
[70]	1027	static int snd_atiixp_pcm_open(struct snd_pcm_substream *substream,
	1028	struct atiixp_dma *dma, int pcm_type)
[32]	1029	{
[70]	1030	struct atiixp *chip = snd_pcm_substream_chip(substream);
	1031	struct snd_pcm_runtime *runtime = substream->runtime;
[32]	1032	int err;
	1033
[399]	1034	if (snd_BUG_ON(!dma->ops \|\| !dma->ops->enable_dma))
	1035	return -EINVAL;
[32]	1036
	1037	if (dma->opened)
	1038	return -EBUSY;
	1039	dma->substream = substream;
	1040	runtime->hw = snd_atiixp_pcm_hw;
	1041	dma->ac97_pcm_type = pcm_type;
	1042	if (pcm_type >= 0) {
	1043	runtime->hw.rates = chip->pcms[pcm_type]->rates;
	1044	snd_pcm_limit_hw_rates(runtime);
	1045	} else {
	1046	/* direct SPDIF */
	1047	runtime->hw.formats = SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE;
	1048	}
[703]	1049	err = snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS);
	1050	if (err < 0)
[32]	1051	return err;
	1052	runtime->private_data = dma;
	1053
	1054	/* enable DMA bits */
	1055	spin_lock_irq(&chip->reg_lock);
	1056	dma->ops->enable_dma(chip, 1);
	1057	spin_unlock_irq(&chip->reg_lock);
	1058	dma->opened = 1;
	1059
	1060	return 0;
	1061	}
	1062
[70]	1063	static int snd_atiixp_pcm_close(struct snd_pcm_substream *substream,
	1064	struct atiixp_dma *dma)
[32]	1065	{
[70]	1066	struct atiixp *chip = snd_pcm_substream_chip(substream);
[32]	1067	/* disable DMA bits */
[399]	1068	if (snd_BUG_ON(!dma->ops \|\| !dma->ops->enable_dma))
	1069	return -EINVAL;
[32]	1070	spin_lock_irq(&chip->reg_lock);
	1071	dma->ops->enable_dma(chip, 0);
	1072	spin_unlock_irq(&chip->reg_lock);
	1073	dma->substream = NULL;
	1074	dma->opened = 0;
	1075	return 0;
	1076	}
	1077
	1078	/*
	1079	*/
[70]	1080	static int snd_atiixp_playback_open(struct snd_pcm_substream *substream)
[32]	1081	{
[70]	1082	struct atiixp *chip = snd_pcm_substream_chip(substream);
[32]	1083	int err;
	1084
[305]	1085	mutex_lock(&chip->open_mutex);
[32]	1086	err = snd_atiixp_pcm_open(substream, &chip->dmas[ATI_DMA_PLAYBACK], 0);
[305]	1087	mutex_unlock(&chip->open_mutex);
[32]	1088	if (err < 0)
	1089	return err;
	1090	substream->runtime->hw.channels_max = chip->max_channels;
	1091	if (chip->max_channels > 2)
	1092	/* channels must be even */
	1093	snd_pcm_hw_constraint_step(substream->runtime, 0,
	1094	SNDRV_PCM_HW_PARAM_CHANNELS, 2);
	1095	return 0;
	1096	}
	1097
[70]	1098	static int snd_atiixp_playback_close(struct snd_pcm_substream *substream)
[32]	1099	{
[70]	1100	struct atiixp *chip = snd_pcm_substream_chip(substream);
[32]	1101	int err;
[305]	1102	mutex_lock(&chip->open_mutex);
[32]	1103	err = snd_atiixp_pcm_close(substream, &chip->dmas[ATI_DMA_PLAYBACK]);
[305]	1104	mutex_unlock(&chip->open_mutex);
[32]	1105	return err;
	1106	}
	1107
[70]	1108	static int snd_atiixp_capture_open(struct snd_pcm_substream *substream)
[32]	1109	{
[70]	1110	struct atiixp *chip = snd_pcm_substream_chip(substream);
[32]	1111	return snd_atiixp_pcm_open(substream, &chip->dmas[ATI_DMA_CAPTURE], 1);
	1112	}
	1113
[70]	1114	static int snd_atiixp_capture_close(struct snd_pcm_substream *substream)
[32]	1115	{
[70]	1116	struct atiixp *chip = snd_pcm_substream_chip(substream);
[32]	1117	return snd_atiixp_pcm_close(substream, &chip->dmas[ATI_DMA_CAPTURE]);
	1118	}
	1119
[70]	1120	static int snd_atiixp_spdif_open(struct snd_pcm_substream *substream)
[32]	1121	{
[70]	1122	struct atiixp *chip = snd_pcm_substream_chip(substream);
[32]	1123	int err;
[305]	1124	mutex_lock(&chip->open_mutex);
[32]	1125	if (chip->spdif_over_aclink) /* share DMA_PLAYBACK */
	1126	err = snd_atiixp_pcm_open(substream, &chip->dmas[ATI_DMA_PLAYBACK], 2);
	1127	else
	1128	err = snd_atiixp_pcm_open(substream, &chip->dmas[ATI_DMA_SPDIF], -1);
[305]	1129	mutex_unlock(&chip->open_mutex);
[32]	1130	return err;
	1131	}
	1132
[70]	1133	static int snd_atiixp_spdif_close(struct snd_pcm_substream *substream)
[32]	1134	{
[70]	1135	struct atiixp *chip = snd_pcm_substream_chip(substream);
[32]	1136	int err;
[305]	1137	mutex_lock(&chip->open_mutex);
[32]	1138	if (chip->spdif_over_aclink)
	1139	err = snd_atiixp_pcm_close(substream, &chip->dmas[ATI_DMA_PLAYBACK]);
	1140	else
	1141	err = snd_atiixp_pcm_close(substream, &chip->dmas[ATI_DMA_SPDIF]);
[305]	1142	mutex_unlock(&chip->open_mutex);
[32]	1143	return err;
	1144	}
	1145
	1146	/* AC97 playback */
[679]	1147	static const struct snd_pcm_ops snd_atiixp_playback_ops = {
[70]	1148	.open = snd_atiixp_playback_open,
	1149	.close = snd_atiixp_playback_close,
	1150	.hw_params = snd_atiixp_pcm_hw_params,
	1151	.hw_free = snd_atiixp_pcm_hw_free,
	1152	.prepare = snd_atiixp_playback_prepare,
	1153	.trigger = snd_atiixp_pcm_trigger,
	1154	.pointer = snd_atiixp_pcm_pointer,
[32]	1155	};
	1156
	1157	/* AC97 capture */
[679]	1158	static const struct snd_pcm_ops snd_atiixp_capture_ops = {
[70]	1159	.open = snd_atiixp_capture_open,
	1160	.close = snd_atiixp_capture_close,
	1161	.hw_params = snd_atiixp_pcm_hw_params,
	1162	.hw_free = snd_atiixp_pcm_hw_free,
	1163	.prepare = snd_atiixp_capture_prepare,
	1164	.trigger = snd_atiixp_pcm_trigger,
	1165	.pointer = snd_atiixp_pcm_pointer,
[32]	1166	};
	1167
	1168	/* SPDIF playback */
[679]	1169	static const struct snd_pcm_ops snd_atiixp_spdif_ops = {
[70]	1170	.open = snd_atiixp_spdif_open,
	1171	.close = snd_atiixp_spdif_close,
	1172	.hw_params = snd_atiixp_pcm_hw_params,
	1173	.hw_free = snd_atiixp_pcm_hw_free,
	1174	.prepare = snd_atiixp_spdif_prepare,
	1175	.trigger = snd_atiixp_pcm_trigger,
	1176	.pointer = snd_atiixp_pcm_pointer,
[32]	1177	};
	1178
[679]	1179	static const struct ac97_pcm atiixp_pcm_defs[] = {
[70]	1180	/* front PCM */
	1181	{
	1182	.exclusive = 1,
	1183	.r = { {
	1184	.slots = (1 << AC97_SLOT_PCM_LEFT) \|
	1185	(1 << AC97_SLOT_PCM_RIGHT) \|
	1186	(1 << AC97_SLOT_PCM_CENTER) \|
	1187	(1 << AC97_SLOT_PCM_SLEFT) \|
	1188	(1 << AC97_SLOT_PCM_SRIGHT) \|
	1189	(1 << AC97_SLOT_LFE)
	1190	}
	1191	}
	1192	},
	1193	/* PCM IN #1 */
	1194	{
	1195	.stream = 1,
	1196	.exclusive = 1,
	1197	.r = { {
	1198	.slots = (1 << AC97_SLOT_PCM_LEFT) \|
	1199	(1 << AC97_SLOT_PCM_RIGHT)
	1200	}
	1201	}
	1202	},
	1203	/* S/PDIF OUT (optional) */
	1204	{
	1205	.exclusive = 1,
	1206	.spdif = 1,
	1207	.r = { {
	1208	.slots = (1 << AC97_SLOT_SPDIF_LEFT2) \|
	1209	(1 << AC97_SLOT_SPDIF_RIGHT2)
	1210	}
	1211	}
	1212	},
[32]	1213	};
	1214
[679]	1215	static const struct atiixp_dma_ops snd_atiixp_playback_dma_ops = {
[70]	1216	.type = ATI_DMA_PLAYBACK,
	1217	.llp_offset = ATI_REG_OUT_DMA_LINKPTR,
	1218	.dt_cur = ATI_REG_OUT_DMA_DT_CUR,
	1219	.enable_dma = atiixp_out_enable_dma,
	1220	.enable_transfer = atiixp_out_enable_transfer,
	1221	.flush_dma = atiixp_out_flush_dma,
[32]	1222	};
[70]	1223
[679]	1224	static const struct atiixp_dma_ops snd_atiixp_capture_dma_ops = {
[70]	1225	.type = ATI_DMA_CAPTURE,
	1226	.llp_offset = ATI_REG_IN_DMA_LINKPTR,
	1227	.dt_cur = ATI_REG_IN_DMA_DT_CUR,
	1228	.enable_dma = atiixp_in_enable_dma,
	1229	.enable_transfer = atiixp_in_enable_transfer,
	1230	.flush_dma = atiixp_in_flush_dma,
[32]	1231	};
[70]	1232
[679]	1233	static const struct atiixp_dma_ops snd_atiixp_spdif_dma_ops = {
[70]	1234	.type = ATI_DMA_SPDIF,
	1235	.llp_offset = ATI_REG_SPDF_DMA_LINKPTR,
	1236	.dt_cur = ATI_REG_SPDF_DMA_DT_CUR,
	1237	.enable_dma = atiixp_spdif_enable_dma,
	1238	.enable_transfer = atiixp_spdif_enable_transfer,
	1239	.flush_dma = atiixp_spdif_flush_dma,
[32]	1240	};
[70]	1241
[32]	1242
[679]	1243	static int snd_atiixp_pcm_new(struct atiixp *chip)
[32]	1244	{
[70]	1245	struct snd_pcm *pcm;
[679]	1246	struct snd_pcm_chmap *chmap;
[70]	1247	struct snd_ac97_bus *pbus = chip->ac97_bus;
[32]	1248	int err, i, num_pcms;
	1249
	1250	/* initialize constants */
	1251	chip->dmas[ATI_DMA_PLAYBACK].ops = &snd_atiixp_playback_dma_ops;
	1252	chip->dmas[ATI_DMA_CAPTURE].ops = &snd_atiixp_capture_dma_ops;
	1253	if (! chip->spdif_over_aclink)
	1254	chip->dmas[ATI_DMA_SPDIF].ops = &snd_atiixp_spdif_dma_ops;
	1255
	1256	/* assign AC97 pcm */
	1257	if (chip->spdif_over_aclink)
	1258	num_pcms = 3;
	1259	else
	1260	num_pcms = 2;
	1261	err = snd_ac97_pcm_assign(pbus, num_pcms, atiixp_pcm_defs);
	1262	if (err < 0)
	1263	return err;
	1264	for (i = 0; i < num_pcms; i++)
	1265	chip->pcms[i] = &pbus->pcms[i];
	1266
	1267	chip->max_channels = 2;
	1268	if (pbus->pcms[ATI_PCM_OUT].r[0].slots & (1 << AC97_SLOT_PCM_SLEFT)) {
	1269	if (pbus->pcms[ATI_PCM_OUT].r[0].slots & (1 << AC97_SLOT_LFE))
	1270	chip->max_channels = 6;
	1271	else
	1272	chip->max_channels = 4;
	1273	}
	1274
	1275	/* PCM #0: analog I/O */
[70]	1276	err = snd_pcm_new(chip->card, "ATI IXP AC97",
	1277	ATI_PCMDEV_ANALOG, 1, 1, &pcm);
[32]	1278	if (err < 0)
	1279	return err;
	1280	snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_atiixp_playback_ops);
	1281	snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_atiixp_capture_ops);
	1282	pcm->private_data = chip;
	1283	strcpy(pcm->name, "ATI IXP AC97");
	1284	chip->pcmdevs[ATI_PCMDEV_ANALOG] = pcm;
	1285
[679]	1286	snd_pcm_set_managed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV,
	1287	&chip->pci->dev, 641024, 1281024);
[32]	1288
[679]	1289	err = snd_pcm_add_chmap_ctls(pcm, SNDRV_PCM_STREAM_PLAYBACK,
	1290	snd_pcm_alt_chmaps, chip->max_channels, 0,
	1291	&chmap);
	1292	if (err < 0)
	1293	return err;
	1294	chmap->channel_mask = SND_PCM_CHMAP_MASK_2468;
	1295	chip->ac97[0]->chmaps[SNDRV_PCM_STREAM_PLAYBACK] = chmap;
	1296
[32]	1297	/* no SPDIF support on codec? */
	1298	if (chip->pcms[ATI_PCM_SPDIF] && ! chip->pcms[ATI_PCM_SPDIF]->rates)
	1299	return 0;
[70]	1300
[32]	1301	/* FIXME: non-48k sample rate doesn't work on my test machine with AD1888 */
	1302	if (chip->pcms[ATI_PCM_SPDIF])
	1303	chip->pcms[ATI_PCM_SPDIF]->rates = SNDRV_PCM_RATE_48000;
	1304
	1305	/* PCM #1: spdif playback */
[70]	1306	err = snd_pcm_new(chip->card, "ATI IXP IEC958",
	1307	ATI_PCMDEV_DIGITAL, 1, 0, &pcm);
[32]	1308	if (err < 0)
	1309	return err;
	1310	snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_atiixp_spdif_ops);
	1311	pcm->private_data = chip;
	1312	if (chip->spdif_over_aclink)
	1313	strcpy(pcm->name, "ATI IXP IEC958 (AC97)");
	1314	else
	1315	strcpy(pcm->name, "ATI IXP IEC958 (Direct)");
	1316	chip->pcmdevs[ATI_PCMDEV_DIGITAL] = pcm;
	1317
[679]	1318	snd_pcm_set_managed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV,
	1319	&chip->pci->dev, 641024, 1281024);
[32]	1320
	1321	/* pre-select AC97 SPDIF slots 10/11 */
	1322	for (i = 0; i < NUM_ATI_CODECS; i++) {
	1323	if (chip->ac97[i])
[70]	1324	snd_ac97_update_bits(chip->ac97[i],
	1325	AC97_EXTENDED_STATUS,
	1326	0x03 << 4, 0x03 << 4);
[32]	1327	}
	1328
	1329	return 0;
	1330	}
	1331
	1332
	1333
	1334	/*
	1335	* interrupt handler
	1336	*/
[305]	1337	static irqreturn_t snd_atiixp_interrupt(int irq, void *dev_id)
[32]	1338	{
[70]	1339	struct atiixp *chip = dev_id;
	1340	unsigned int status;
[32]	1341
	1342	status = atiixp_read(chip, ISR);
	1343
	1344	if (! status)
	1345	return IRQ_NONE;
	1346
	1347	/* process audio DMA */
	1348	if (status & ATI_REG_ISR_OUT_XRUN)
	1349	snd_atiixp_xrun_dma(chip, &chip->dmas[ATI_DMA_PLAYBACK]);
	1350	else if (status & ATI_REG_ISR_OUT_STATUS)
	1351	snd_atiixp_update_dma(chip, &chip->dmas[ATI_DMA_PLAYBACK]);
	1352	if (status & ATI_REG_ISR_IN_XRUN)
	1353	snd_atiixp_xrun_dma(chip, &chip->dmas[ATI_DMA_CAPTURE]);
	1354	else if (status & ATI_REG_ISR_IN_STATUS)
	1355	snd_atiixp_update_dma(chip, &chip->dmas[ATI_DMA_CAPTURE]);
	1356	if (! chip->spdif_over_aclink) {
	1357	if (status & ATI_REG_ISR_SPDF_XRUN)
	1358	snd_atiixp_xrun_dma(chip, &chip->dmas[ATI_DMA_SPDIF]);
	1359	else if (status & ATI_REG_ISR_SPDF_STATUS)
	1360	snd_atiixp_update_dma(chip, &chip->dmas[ATI_DMA_SPDIF]);
	1361	}
	1362
	1363	/* for codec detection */
	1364	if (status & CODEC_CHECK_BITS) {
	1365	unsigned int detected;
	1366	detected = status & CODEC_CHECK_BITS;
	1367	spin_lock(&chip->reg_lock);
	1368	chip->codec_not_ready_bits \|= detected;
	1369	atiixp_update(chip, IER, detected, 0); /* disable the detected irqs */
	1370	spin_unlock(&chip->reg_lock);
	1371	}
	1372
	1373	/* ack */
	1374	atiixp_write(chip, ISR, status);
	1375
	1376	return IRQ_HANDLED;
	1377	}
	1378
	1379
	1380	/*
	1381	* ac97 mixer section
	1382	*/
	1383
[679]	1384	static const struct ac97_quirk ac97_quirks[] = {
[70]	1385	{
	1386	.subvendor = 0x103c,
	1387	.subdevice = 0x006b,
	1388	.name = "HP Pavilion ZV5030US",
	1389	.type = AC97_TUNE_MUTE_LED
	1390	},
	1391	{
	1392	.subvendor = 0x103c,
	1393	.subdevice = 0x308b,
	1394	.name = "HP nx6125",
	1395	.type = AC97_TUNE_MUTE_LED
	1396	},
[426]	1397	{
	1398	.subvendor = 0x103c,
	1399	.subdevice = 0x3091,
	1400	.name = "unknown HP",
	1401	.type = AC97_TUNE_MUTE_LED
	1402	},
[70]	1403	{0} /* terminator */
[32]	1404	};
	1405
[679]	1406	static int snd_atiixp_mixer_new(struct atiixp *chip, int clock,
	1407	const char *quirk_override)
[32]	1408	{
[70]	1409	struct snd_ac97_bus *pbus;
	1410	struct snd_ac97_template ac97;
[32]	1411	int i, err;
	1412	int codec_count;
[679]	1413	static const struct snd_ac97_bus_ops ops = {
[70]	1414	.write = snd_atiixp_ac97_write,
	1415	.read = snd_atiixp_ac97_read,
[32]	1416	};
[679]	1417	static const unsigned int codec_skip[NUM_ATI_CODECS] = {
[32]	1418	ATI_REG_ISR_CODEC0_NOT_READY,
	1419	ATI_REG_ISR_CODEC1_NOT_READY,
	1420	ATI_REG_ISR_CODEC2_NOT_READY,
	1421	};
	1422
	1423	if (snd_atiixp_codec_detect(chip) < 0)
	1424	return -ENXIO;
	1425
[703]	1426	err = snd_ac97_bus(chip->card, 0, &ops, chip, &pbus);
	1427	if (err < 0)
[32]	1428	return err;
	1429	pbus->clock = clock;
	1430	chip->ac97_bus = pbus;
	1431
	1432	codec_count = 0;
	1433	for (i = 0; i < NUM_ATI_CODECS; i++) {
	1434	if (chip->codec_not_ready_bits & codec_skip[i])
	1435	continue;
	1436	memset(&ac97, 0, sizeof(ac97));
	1437	ac97.private_data = chip;
	1438	ac97.pci = chip->pci;
	1439	ac97.num = i;
[305]	1440	ac97.scaps = AC97_SCAP_SKIP_MODEM \| AC97_SCAP_POWER_SAVE;
[70]	1441	if (! chip->spdif_over_aclink)
	1442	ac97.scaps \|= AC97_SCAP_NO_SPDIF;
[703]	1443	err = snd_ac97_mixer(pbus, &ac97, &chip->ac97[i]);
	1444	if (err < 0) {
[32]	1445	chip->ac97[i] = NULL; /* to be sure */
[679]	1446	dev_dbg(chip->card->dev,
	1447	"codec %d not available for audio\n", i);
[32]	1448	continue;
	1449	}
	1450	codec_count++;
	1451	}
	1452
	1453	if (! codec_count) {
[679]	1454	dev_err(chip->card->dev, "no codec available\n");
[32]	1455	return -ENODEV;
	1456	}
	1457
[70]	1458	snd_ac97_tune_hardware(chip->ac97[0], ac97_quirks, quirk_override);
[32]	1459
	1460	return 0;
	1461	}
	1462
	1463
	1464	/*
	1465	* power management
	1466	*/
[679]	1467	static int snd_atiixp_suspend(struct device *dev)
[32]	1468	{
[679]	1469	struct snd_card *card = dev_get_drvdata(dev);
[70]	1470	struct atiixp *chip = card->private_data;
[32]	1471	int i;
	1472
[70]	1473	snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
[32]	1474	for (i = 0; i < NUM_ATI_CODECS; i++)
[70]	1475	snd_ac97_suspend(chip->ac97[i]);
[32]	1476	snd_atiixp_aclink_down(chip);
	1477	snd_atiixp_chip_stop(chip);
	1478	return 0;
	1479	}
	1480
[679]	1481	static int snd_atiixp_resume(struct device *dev)
[32]	1482	{
[679]	1483	struct snd_card *card = dev_get_drvdata(dev);
[70]	1484	struct atiixp *chip = card->private_data;
[32]	1485	int i;
	1486
	1487	snd_atiixp_aclink_reset(chip);
	1488	snd_atiixp_chip_start(chip);
	1489
	1490	for (i = 0; i < NUM_ATI_CODECS; i++)
[70]	1491	snd_ac97_resume(chip->ac97[i]);
[32]	1492
[70]	1493	for (i = 0; i < NUM_ATI_PCMDEVS; i++)
	1494	if (chip->pcmdevs[i]) {
	1495	struct atiixp_dma *dma = &chip->dmas[i];
	1496	if (dma->substream && dma->suspended) {
	1497	dma->ops->enable_dma(chip, 1);
	1498	dma->substream->ops->prepare(dma->substream);
	1499	writel((u32)dma->desc_buf.addr \| ATI_REG_LINKPTR_EN,
[305]	1500	chip->remap_addr + dma->ops->llp_offset);
[70]	1501	}
	1502	}
	1503
	1504	snd_power_change_state(card, SNDRV_CTL_POWER_D0);
	1505	return 0;
[32]	1506	}
	1507
[777]	1508	static DEFINE_SIMPLE_DEV_PM_OPS(snd_atiixp_pm, snd_atiixp_suspend, snd_atiixp_resume);
[32]	1509
	1510	/*
	1511	* proc interface for register dump
	1512	*/
	1513
[70]	1514	static void snd_atiixp_proc_read(struct snd_info_entry *entry,
	1515	struct snd_info_buffer *buffer)
[32]	1516	{
[70]	1517	struct atiixp *chip = entry->private_data;
[32]	1518	int i;
	1519
	1520	for (i = 0; i < 256; i += 4)
[305]	1521	snd_iprintf(buffer, "%02x: %08x\n", i, readl(chip->remap_addr + i));
[32]	1522	}
	1523
[679]	1524	static void snd_atiixp_proc_init(struct atiixp *chip)
[32]	1525	{
[679]	1526	snd_card_ro_proc_new(chip->card, "atiixp", chip, snd_atiixp_proc_read);
[32]	1527	}
	1528
	1529
	1530	/*
	1531	* destructor
	1532	*/
	1533
[717]	1534	static void snd_atiixp_free(struct snd_card *card)
[32]	1535	{
[717]	1536	snd_atiixp_chip_stop(card->private_data);
[32]	1537	}
	1538
	1539	/*
	1540	* constructor for chip instance
	1541	*/
[717]	1542	static int snd_atiixp_init(struct snd_card card, struct pci_dev pci)
[32]	1543	{
[717]	1544	struct atiixp *chip = card->private_data;
[32]	1545	int err;
	1546
[717]	1547	err = pcim_enable_device(pci);
[703]	1548	if (err < 0)
[32]	1549	return err;
	1550
	1551	spin_lock_init(&chip->reg_lock);
[305]	1552	mutex_init(&chip->open_mutex);
[32]	1553	chip->card = card;
	1554	chip->pci = pci;
	1555	chip->irq = -1;
[717]	1556	err = pcim_iomap_regions(pci, 1 << 0, "ATI IXP AC97");
	1557	if (err < 0)
	1558	return err;
[32]	1559	chip->addr = pci_resource_start(pci, 0);
[717]	1560	chip->remap_addr = pcim_iomap_table(pci)[0];
	1561	if (devm_request_irq(&pci->dev, pci->irq, snd_atiixp_interrupt,
	1562	IRQF_SHARED, KBUILD_MODNAME, chip)) {
[679]	1563	dev_err(card->dev, "unable to grab IRQ %d\n", pci->irq);
[32]	1564	return -EBUSY;
	1565	}
	1566	chip->irq = pci->irq;
[679]	1567	card->sync_irq = chip->irq;
[717]	1568	card->private_free = snd_atiixp_free;
[32]	1569	pci_set_master(pci);
	1570
	1571	return 0;
	1572	}
	1573
	1574
[717]	1575	static int __snd_atiixp_probe(struct pci_dev *pci,
	1576	const struct pci_device_id *pci_id)
[32]	1577	{
[70]	1578	struct snd_card *card;
	1579	struct atiixp *chip;
[32]	1580	int err;
	1581
[717]	1582	err = snd_devm_card_new(&pci->dev, index, id, THIS_MODULE,
	1583	sizeof(*chip), &card);
[410]	1584	if (err < 0)
	1585	return err;
[717]	1586	chip = card->private_data;
[32]	1587
[70]	1588	strcpy(card->driver, spdif_aclink ? "ATIIXP" : "ATIIXP-SPDMA");
[32]	1589	strcpy(card->shortname, "ATI IXP");
[717]	1590	err = snd_atiixp_init(card, pci);
[703]	1591	if (err < 0)
[717]	1592	return err;
[32]	1593
[703]	1594	err = snd_atiixp_aclink_reset(chip);
	1595	if (err < 0)
[717]	1596	return err;
[32]	1597
[70]	1598	chip->spdif_over_aclink = spdif_aclink;
[32]	1599
[703]	1600	err = snd_atiixp_mixer_new(chip, ac97_clock, ac97_quirk);
	1601	if (err < 0)
[717]	1602	return err;
[32]	1603
[703]	1604	err = snd_atiixp_pcm_new(chip);
	1605	if (err < 0)
[717]	1606	return err;
[70]	1607
[32]	1608	snd_atiixp_proc_init(chip);
	1609
	1610	snd_atiixp_chip_start(chip);
	1611
[305]	1612	snprintf(card->longname, sizeof(card->longname),
	1613	"%s rev %x with %s at %#lx, irq %i", card->shortname,
	1614	#ifndef TARGET_OS2
	1615	pci->revision,
	1616	#else
	1617	snd_pci_revision(pci),
	1618	#endif
[32]	1619	chip->ac97[0] ? snd_ac97_get_short_name(chip->ac97[0]) : "?",
	1620	chip->addr, chip->irq);
	1621
[703]	1622	err = snd_card_register(card);
	1623	if (err < 0)
[717]	1624	return err;
[32]	1625
	1626	pci_set_drvdata(pci, card);
	1627	return 0;
	1628	}
	1629
[717]	1630	static int snd_atiixp_probe(struct pci_dev *pci,
	1631	const struct pci_device_id *pci_id)
[32]	1632	{
[717]	1633	return snd_card_free_on_error(&pci->dev, __snd_atiixp_probe(pci, pci_id));
[32]	1634	}
	1635
[679]	1636	static struct pci_driver atiixp_driver = {
	1637	.name = KBUILD_MODNAME,
[70]	1638	.id_table = snd_atiixp_ids,
	1639	.probe = snd_atiixp_probe,
[679]	1640	.driver = {
[777]	1641	.pm = &snd_atiixp_pm,
[679]	1642	},
[32]	1643	};
	1644
[679]	1645	module_pci_driver(atiixp_driver);

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source: GPL/trunk/alsa-kernel/pci/atiixp.c

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