source: GPL/trunk/alsa-kernel/pci/atiixp.c@ 772

Last change on this file since 772 was 772, checked in by David Azarewicz, 5 months ago

Merge in changes from 6.6-LTS branch.
Fixed additional 25+ problems.
File size: 45.0 KB
Line 
1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * ALSA driver for ATI IXP 150/200/250/300 AC97 controllers
4 *
5 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
6 */
7
8#include <linux/io.h>
9#include <linux/delay.h>
10#include <linux/interrupt.h>
11#include <linux/init.h>
12#include <linux/pci.h>
13#include <linux/slab.h>
14#include <linux/module.h>
15#include <linux/mutex.h>
16#include <sound/core.h>
17#include <sound/pcm.h>
18#include <sound/pcm_params.h>
19#include <sound/info.h>
20#include <sound/ac97_codec.h>
21#include <sound/initval.h>
22
23#ifdef TARGET_OS2
24#define KBUILD_MODNAME "atiixp"
25#endif
26
27MODULE_AUTHOR("Takashi Iwai <tiwai@suse.de>");
28MODULE_DESCRIPTION("ATI IXP AC97 controller");
29MODULE_LICENSE("GPL");
30
31static int index = SNDRV_DEFAULT_IDX1; /* Index 0-MAX */
32static char *id = SNDRV_DEFAULT_STR1; /* ID for this card */
33static int ac97_clock = 48000;
34static char *ac97_quirk;
35static bool spdif_aclink = 1;
36static int ac97_codec = -1;
37
38module_param(index, int, 0444);
39MODULE_PARM_DESC(index, "Index value for ATI IXP controller.");
40module_param(id, charp, 0444);
41MODULE_PARM_DESC(id, "ID string for ATI IXP controller.");
42module_param(ac97_clock, int, 0444);
43MODULE_PARM_DESC(ac97_clock, "AC'97 codec clock (default 48000Hz).");
44module_param(ac97_quirk, charp, 0444);
45MODULE_PARM_DESC(ac97_quirk, "AC'97 workaround for strange hardware.");
46module_param(ac97_codec, int, 0444);
47MODULE_PARM_DESC(ac97_codec, "Specify codec instead of probing.");
48module_param(spdif_aclink, bool, 0444);
49MODULE_PARM_DESC(spdif_aclink, "S/PDIF over AC-link.");
50
51/* just for backward compatibility */
52//static bool enable;
53module_param(enable, bool, 0444);
54
55
56/*
57 */
58
59#define ATI_REG_ISR 0x00 /* interrupt source */
60#define ATI_REG_ISR_IN_XRUN (1U<<0)
61#define ATI_REG_ISR_IN_STATUS (1U<<1)
62#define ATI_REG_ISR_OUT_XRUN (1U<<2)
63#define ATI_REG_ISR_OUT_STATUS (1U<<3)
64#define ATI_REG_ISR_SPDF_XRUN (1U<<4)
65#define ATI_REG_ISR_SPDF_STATUS (1U<<5)
66#define ATI_REG_ISR_PHYS_INTR (1U<<8)
67#define ATI_REG_ISR_PHYS_MISMATCH (1U<<9)
68#define ATI_REG_ISR_CODEC0_NOT_READY (1U<<10)
69#define ATI_REG_ISR_CODEC1_NOT_READY (1U<<11)
70#define ATI_REG_ISR_CODEC2_NOT_READY (1U<<12)
71#define ATI_REG_ISR_NEW_FRAME (1U<<13)
72
73#define ATI_REG_IER 0x04 /* interrupt enable */
74#define ATI_REG_IER_IN_XRUN_EN (1U<<0)
75#define ATI_REG_IER_IO_STATUS_EN (1U<<1)
76#define ATI_REG_IER_OUT_XRUN_EN (1U<<2)
77#define ATI_REG_IER_OUT_XRUN_COND (1U<<3)
78#define ATI_REG_IER_SPDF_XRUN_EN (1U<<4)
79#define ATI_REG_IER_SPDF_STATUS_EN (1U<<5)
80#define ATI_REG_IER_PHYS_INTR_EN (1U<<8)
81#define ATI_REG_IER_PHYS_MISMATCH_EN (1U<<9)
82#define ATI_REG_IER_CODEC0_INTR_EN (1U<<10)
83#define ATI_REG_IER_CODEC1_INTR_EN (1U<<11)
84#define ATI_REG_IER_CODEC2_INTR_EN (1U<<12)
85#define ATI_REG_IER_NEW_FRAME_EN (1U<<13) /* (RO */
86#define ATI_REG_IER_SET_BUS_BUSY (1U<<14) /* (WO) audio is running */
87
88#define ATI_REG_CMD 0x08 /* command */
89#define ATI_REG_CMD_POWERDOWN (1U<<0)
90#define ATI_REG_CMD_RECEIVE_EN (1U<<1)
91#define ATI_REG_CMD_SEND_EN (1U<<2)
92#define ATI_REG_CMD_STATUS_MEM (1U<<3)
93#define ATI_REG_CMD_SPDF_OUT_EN (1U<<4)
94#define ATI_REG_CMD_SPDF_STATUS_MEM (1U<<5)
95#define ATI_REG_CMD_SPDF_THRESHOLD (3U<<6)
96#define ATI_REG_CMD_SPDF_THRESHOLD_SHIFT 6
97#define ATI_REG_CMD_IN_DMA_EN (1U<<8)
98#define ATI_REG_CMD_OUT_DMA_EN (1U<<9)
99#define ATI_REG_CMD_SPDF_DMA_EN (1U<<10)
100#define ATI_REG_CMD_SPDF_OUT_STOPPED (1U<<11)
101#define ATI_REG_CMD_SPDF_CONFIG_MASK (7U<<12)
102#define ATI_REG_CMD_SPDF_CONFIG_34 (1U<<12)
103#define ATI_REG_CMD_SPDF_CONFIG_78 (2U<<12)
104#define ATI_REG_CMD_SPDF_CONFIG_69 (3U<<12)
105#define ATI_REG_CMD_SPDF_CONFIG_01 (4U<<12)
106#define ATI_REG_CMD_INTERLEAVE_SPDF (1U<<16)
107#define ATI_REG_CMD_AUDIO_PRESENT (1U<<20)
108#define ATI_REG_CMD_INTERLEAVE_IN (1U<<21)
109#define ATI_REG_CMD_INTERLEAVE_OUT (1U<<22)
110#define ATI_REG_CMD_LOOPBACK_EN (1U<<23)
111#define ATI_REG_CMD_PACKED_DIS (1U<<24)
112#define ATI_REG_CMD_BURST_EN (1U<<25)
113#define ATI_REG_CMD_PANIC_EN (1U<<26)
114#define ATI_REG_CMD_MODEM_PRESENT (1U<<27)
115#define ATI_REG_CMD_ACLINK_ACTIVE (1U<<28)
116#define ATI_REG_CMD_AC_SOFT_RESET (1U<<29)
117#define ATI_REG_CMD_AC_SYNC (1U<<30)
118#define ATI_REG_CMD_AC_RESET (1U<<31)
119
120#define ATI_REG_PHYS_OUT_ADDR 0x0c
121#define ATI_REG_PHYS_OUT_CODEC_MASK (3U<<0)
122#define ATI_REG_PHYS_OUT_RW (1U<<2)
123#define ATI_REG_PHYS_OUT_ADDR_EN (1U<<8)
124#define ATI_REG_PHYS_OUT_ADDR_SHIFT 9
125#define ATI_REG_PHYS_OUT_DATA_SHIFT 16
126
127#define ATI_REG_PHYS_IN_ADDR 0x10
128#define ATI_REG_PHYS_IN_READ_FLAG (1U<<8)
129#define ATI_REG_PHYS_IN_ADDR_SHIFT 9
130#define ATI_REG_PHYS_IN_DATA_SHIFT 16
131
132#define ATI_REG_SLOTREQ 0x14
133
134#define ATI_REG_COUNTER 0x18
135#define ATI_REG_COUNTER_SLOT (3U<<0) /* slot # */
136#define ATI_REG_COUNTER_BITCLOCK (31U<<8)
137
138#define ATI_REG_IN_FIFO_THRESHOLD 0x1c
139
140#define ATI_REG_IN_DMA_LINKPTR 0x20
141#define ATI_REG_IN_DMA_DT_START 0x24 /* RO */
142#define ATI_REG_IN_DMA_DT_NEXT 0x28 /* RO */
143#define ATI_REG_IN_DMA_DT_CUR 0x2c /* RO */
144#define ATI_REG_IN_DMA_DT_SIZE 0x30
145
146#define ATI_REG_OUT_DMA_SLOT 0x34
147#define ATI_REG_OUT_DMA_SLOT_BIT(x) (1U << ((x) - 3))
148#define ATI_REG_OUT_DMA_SLOT_MASK 0x1ff
149#define ATI_REG_OUT_DMA_THRESHOLD_MASK 0xf800
150#define ATI_REG_OUT_DMA_THRESHOLD_SHIFT 11
151
152#define ATI_REG_OUT_DMA_LINKPTR 0x38
153#define ATI_REG_OUT_DMA_DT_START 0x3c /* RO */
154#define ATI_REG_OUT_DMA_DT_NEXT 0x40 /* RO */
155#define ATI_REG_OUT_DMA_DT_CUR 0x44 /* RO */
156#define ATI_REG_OUT_DMA_DT_SIZE 0x48
157
158#define ATI_REG_SPDF_CMD 0x4c
159#define ATI_REG_SPDF_CMD_LFSR (1U<<4)
160#define ATI_REG_SPDF_CMD_SINGLE_CH (1U<<5)
161#define ATI_REG_SPDF_CMD_LFSR_ACC (0xff<<8) /* RO */
162
163#define ATI_REG_SPDF_DMA_LINKPTR 0x50
164#define ATI_REG_SPDF_DMA_DT_START 0x54 /* RO */
165#define ATI_REG_SPDF_DMA_DT_NEXT 0x58 /* RO */
166#define ATI_REG_SPDF_DMA_DT_CUR 0x5c /* RO */
167#define ATI_REG_SPDF_DMA_DT_SIZE 0x60
168
169#define ATI_REG_MODEM_MIRROR 0x7c
170#define ATI_REG_AUDIO_MIRROR 0x80
171
172#define ATI_REG_6CH_REORDER 0x84 /* reorder slots for 6ch */
173#define ATI_REG_6CH_REORDER_EN (1U<<0) /* 3,4,7,8,6,9 -> 3,4,6,9,7,8 */
174
175#define ATI_REG_FIFO_FLUSH 0x88
176#define ATI_REG_FIFO_OUT_FLUSH (1U<<0)
177#define ATI_REG_FIFO_IN_FLUSH (1U<<1)
178
179/* LINKPTR */
180#define ATI_REG_LINKPTR_EN (1U<<0)
181
182/* [INT|OUT|SPDIF]_DMA_DT_SIZE */
183#define ATI_REG_DMA_DT_SIZE (0xffffU<<0)
184#define ATI_REG_DMA_FIFO_USED (0x1fU<<16)
185#define ATI_REG_DMA_FIFO_FREE (0x1fU<<21)
186#define ATI_REG_DMA_STATE (7U<<26)
187
188
189#define ATI_MAX_DESCRIPTORS 256 /* max number of descriptor packets */
190
191
192struct atiixp;
193
194/*
195 * DMA packate descriptor
196 */
197
198struct atiixp_dma_desc {
199 __le32 addr; /* DMA buffer address */
200 u16 status; /* status bits */
201 u16 size; /* size of the packet in dwords */
202 __le32 next; /* address of the next packet descriptor */
203};
204
205/*
206 * stream enum
207 */
208enum { ATI_DMA_PLAYBACK, ATI_DMA_CAPTURE, ATI_DMA_SPDIF, NUM_ATI_DMAS }; /* DMAs */
209enum { ATI_PCM_OUT, ATI_PCM_IN, ATI_PCM_SPDIF, NUM_ATI_PCMS }; /* AC97 pcm slots */
210enum { ATI_PCMDEV_ANALOG, ATI_PCMDEV_DIGITAL, NUM_ATI_PCMDEVS }; /* pcm devices */
211
212#define NUM_ATI_CODECS 3
213
214
215/*
216 * constants and callbacks for each DMA type
217 */
218struct atiixp_dma_ops {
219 int type; /* ATI_DMA_XXX */
220 unsigned int llp_offset; /* LINKPTR offset */
221 unsigned int dt_cur; /* DT_CUR offset */
222 /* called from open callback */
223 void (*enable_dma)(struct atiixp *chip, int on);
224 /* called from trigger (START/STOP) */
225 void (*enable_transfer)(struct atiixp *chip, int on);
226 /* called from trigger (STOP only) */
227 void (*flush_dma)(struct atiixp *chip);
228};
229
230/*
231 * DMA stream
232 */
233struct atiixp_dma {
234 const struct atiixp_dma_ops *ops;
235 struct snd_dma_buffer desc_buf;
236 struct snd_pcm_substream *substream; /* assigned PCM substream */
237 unsigned int buf_addr, buf_bytes; /* DMA buffer address, bytes */
238 unsigned int period_bytes, periods;
239 int opened;
240 int running;
241 int suspended;
242 int pcm_open_flag;
243 int ac97_pcm_type; /* index # of ac97_pcm to access, -1 = not used */
244 unsigned int saved_curptr;
245};
246
247/*
248 * ATI IXP chip
249 */
250struct atiixp {
251 struct snd_card *card;
252 struct pci_dev *pci;
253
254 unsigned long addr;
255 void __iomem *remap_addr;
256 int irq;
257
258 struct snd_ac97_bus *ac97_bus;
259 struct snd_ac97 *ac97[NUM_ATI_CODECS];
260
261 spinlock_t reg_lock;
262
263 struct atiixp_dma dmas[NUM_ATI_DMAS];
264 struct ac97_pcm *pcms[NUM_ATI_PCMS];
265 struct snd_pcm *pcmdevs[NUM_ATI_PCMDEVS];
266
267 int max_channels; /* max. channels for PCM out */
268
269 unsigned int codec_not_ready_bits; /* for codec detection */
270
271 int spdif_over_aclink; /* passed from the module option */
272 struct mutex open_mutex; /* playback open mutex */
273};
274
275
276/*
277 */
278static const struct pci_device_id snd_atiixp_ids[] = {
279 { PCI_VDEVICE(ATI, 0x4341), 0 }, /* SB200 */
280 { PCI_VDEVICE(ATI, 0x4361), 0 }, /* SB300 */
281 { PCI_VDEVICE(ATI, 0x4370), 0 }, /* SB400 */
282 { PCI_VDEVICE(ATI, 0x4382), 0 }, /* SB600 */
283 { 0, }
284};
285
286MODULE_DEVICE_TABLE(pci, snd_atiixp_ids);
287
288static const struct snd_pci_quirk atiixp_quirks[] = {
289 SND_PCI_QUIRK(0x105b, 0x0c81, "Foxconn RC4107MA-RS2", 0),
290 SND_PCI_QUIRK(0x15bd, 0x3100, "DFI RS482", 0),
291 {0} /* terminator */
292};
293
294/*
295 * lowlevel functions
296 */
297
298/*
299 * update the bits of the given register.
300 * return 1 if the bits changed.
301 */
302static int snd_atiixp_update_bits(struct atiixp *chip, unsigned int reg,
303 unsigned int mask, unsigned int value)
304{
305 void __iomem *addr = chip->remap_addr + reg;
306 unsigned int data, old_data;
307 old_data = data = readl(addr);
308 data &= ~mask;
309 data |= value;
310 if (old_data == data)
311 return 0;
312 writel(data, addr);
313 return 1;
314}
315
316/*
317 * macros for easy use
318 */
319#define atiixp_write(chip,reg,value) \
320 writel(value, chip->remap_addr + ATI_REG_##reg)
321#define atiixp_read(chip,reg) \
322 readl(chip->remap_addr + ATI_REG_##reg)
323#define atiixp_update(chip,reg,mask,val) \
324 snd_atiixp_update_bits(chip, ATI_REG_##reg, mask, val)
325
326/*
327 * handling DMA packets
328 *
329 * we allocate a linear buffer for the DMA, and split it to each packet.
330 * in a future version, a scatter-gather buffer should be implemented.
331 */
332
333#define ATI_DESC_LIST_SIZE \
334 PAGE_ALIGN(ATI_MAX_DESCRIPTORS * sizeof(struct atiixp_dma_desc))
335
336/*
337 * build packets ring for the given buffer size.
338 *
339 * IXP handles the buffer descriptors, which are connected as a linked
340 * list. although we can change the list dynamically, in this version,
341 * a static RING of buffer descriptors is used.
342 *
343 * the ring is built in this function, and is set up to the hardware.
344 */
345static int atiixp_build_dma_packets(struct atiixp *chip, struct atiixp_dma *dma,
346 struct snd_pcm_substream *substream,
347 unsigned int periods,
348 unsigned int period_bytes)
349{
350 unsigned int i;
351 u32 addr, desc_addr;
352 unsigned long flags;
353
354 if (periods > ATI_MAX_DESCRIPTORS)
355 return -ENOMEM;
356
357 if (dma->desc_buf.area == NULL) {
358 if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
359 &chip->pci->dev,
360 ATI_DESC_LIST_SIZE,
361 &dma->desc_buf) < 0)
362 return -ENOMEM;
363 dma->period_bytes = dma->periods = 0; /* clear */
364 }
365
366 if (dma->periods == periods && dma->period_bytes == period_bytes) {
367 writel((u32)dma->desc_buf.addr | ATI_REG_LINKPTR_EN,
368 (char*)chip->remap_addr + dma->ops->llp_offset);
369 return 0;
370 }
371
372 /* reset DMA before changing the descriptor table */
373 spin_lock_irqsave(&chip->reg_lock, flags);
374 writel(0, chip->remap_addr + dma->ops->llp_offset);
375 dma->ops->enable_dma(chip, 0);
376 dma->ops->enable_dma(chip, 1);
377 spin_unlock_irqrestore(&chip->reg_lock, flags);
378
379 /* fill the entries */
380 addr = (u32)substream->runtime->dma_addr;
381 desc_addr = (u32)dma->desc_buf.addr;
382 for (i = 0; i < periods; i++) {
383 struct atiixp_dma_desc *desc;
384 desc = &((struct atiixp_dma_desc *)dma->desc_buf.area)[i];
385 desc->addr = cpu_to_le32(addr);
386 desc->status = 0;
387 desc->size = period_bytes >> 2; /* in dwords */
388 desc_addr += sizeof(struct atiixp_dma_desc);
389 if (i == periods - 1)
390 desc->next = cpu_to_le32((u32)dma->desc_buf.addr);
391 else
392 desc->next = cpu_to_le32(desc_addr);
393 addr += period_bytes;
394 }
395
396 writel((u32)dma->desc_buf.addr | ATI_REG_LINKPTR_EN,
397 chip->remap_addr + dma->ops->llp_offset);
398
399 dma->period_bytes = period_bytes;
400 dma->periods = periods;
401
402 return 0;
403}
404
405/*
406 * remove the ring buffer and release it if assigned
407 */
408static void atiixp_clear_dma_packets(struct atiixp *chip, struct atiixp_dma *dma,
409 struct snd_pcm_substream *substream)
410{
411 if (dma->desc_buf.area) {
412 writel(0, chip->remap_addr + dma->ops->llp_offset);
413 snd_dma_free_pages(&dma->desc_buf);
414 dma->desc_buf.area = NULL;
415 }
416}
417
418/*
419 * AC97 interface
420 */
421static int snd_atiixp_acquire_codec(struct atiixp *chip)
422{
423 int timeout = 1000;
424
425 while (atiixp_read(chip, PHYS_OUT_ADDR) & ATI_REG_PHYS_OUT_ADDR_EN) {
426 if (! timeout--) {
427 dev_warn(chip->card->dev, "codec acquire timeout\n");
428 return -EBUSY;
429 }
430 udelay(1);
431 }
432 return 0;
433}
434
435static unsigned short snd_atiixp_codec_read(struct atiixp *chip, unsigned short codec, unsigned short reg)
436{
437 unsigned int data;
438 int timeout;
439
440 if (snd_atiixp_acquire_codec(chip) < 0)
441 return 0xffff;
442 data = (reg << ATI_REG_PHYS_OUT_ADDR_SHIFT) |
443 ATI_REG_PHYS_OUT_ADDR_EN |
444 ATI_REG_PHYS_OUT_RW |
445 codec;
446 atiixp_write(chip, PHYS_OUT_ADDR, data);
447 if (snd_atiixp_acquire_codec(chip) < 0)
448 return 0xffff;
449 timeout = 1000;
450 do {
451 data = atiixp_read(chip, PHYS_IN_ADDR);
452 if (data & ATI_REG_PHYS_IN_READ_FLAG)
453 return data >> ATI_REG_PHYS_IN_DATA_SHIFT;
454 udelay(1);
455 } while (--timeout);
456 /* time out may happen during reset */
457 if (reg < 0x7c)
458 dev_warn(chip->card->dev, "codec read timeout (reg %x)\n", reg);
459 return 0xffff;
460}
461
462
463static void snd_atiixp_codec_write(struct atiixp *chip, unsigned short codec,
464 unsigned short reg, unsigned short val)
465{
466 unsigned int data;
467
468 if (snd_atiixp_acquire_codec(chip) < 0)
469 return;
470 data = ((unsigned int)val << ATI_REG_PHYS_OUT_DATA_SHIFT) |
471 ((unsigned int)reg << ATI_REG_PHYS_OUT_ADDR_SHIFT) |
472 ATI_REG_PHYS_OUT_ADDR_EN | codec;
473 atiixp_write(chip, PHYS_OUT_ADDR, data);
474}
475
476
477static unsigned short snd_atiixp_ac97_read(struct snd_ac97 *ac97,
478 unsigned short reg)
479{
480 struct atiixp *chip = ac97->private_data;
481 return snd_atiixp_codec_read(chip, ac97->num, reg);
482
483}
484
485static void snd_atiixp_ac97_write(struct snd_ac97 *ac97, unsigned short reg,
486 unsigned short val)
487{
488 struct atiixp *chip = ac97->private_data;
489 snd_atiixp_codec_write(chip, ac97->num, reg, val);
490}
491
492/*
493 * reset AC link
494 */
495static int snd_atiixp_aclink_reset(struct atiixp *chip)
496{
497 int timeout;
498
499 /* reset powerdoewn */
500 if (atiixp_update(chip, CMD, ATI_REG_CMD_POWERDOWN, 0))
501 udelay(10);
502
503 /* perform a software reset */
504 atiixp_update(chip, CMD, ATI_REG_CMD_AC_SOFT_RESET, ATI_REG_CMD_AC_SOFT_RESET);
505#pragma disable_message (302)
506 atiixp_read(chip, CMD);
507 udelay(10);
508 atiixp_update(chip, CMD, ATI_REG_CMD_AC_SOFT_RESET, 0);
509
510 timeout = 10;
511 while (! (atiixp_read(chip, CMD) & ATI_REG_CMD_ACLINK_ACTIVE)) {
512 /* do a hard reset */
513 atiixp_update(chip, CMD, ATI_REG_CMD_AC_SYNC|ATI_REG_CMD_AC_RESET,
514 ATI_REG_CMD_AC_SYNC);
515 atiixp_read(chip, CMD);
516 mdelay(1);
517 atiixp_update(chip, CMD, ATI_REG_CMD_AC_RESET, ATI_REG_CMD_AC_RESET);
518 if (!--timeout) {
519 dev_err(chip->card->dev, "codec reset timeout\n");
520 break;
521 }
522 }
523#pragma enable_message (302)
524
525 /* deassert RESET and assert SYNC to make sure */
526 atiixp_update(chip, CMD, ATI_REG_CMD_AC_SYNC|ATI_REG_CMD_AC_RESET,
527 ATI_REG_CMD_AC_SYNC|ATI_REG_CMD_AC_RESET);
528
529 return 0;
530}
531
532#ifdef CONFIG_PM_SLEEP
533static int snd_atiixp_aclink_down(struct atiixp *chip)
534{
535 // if (atiixp_read(chip, MODEM_MIRROR) & 0x1) /* modem running, too? */
536 // return -EBUSY;
537 atiixp_update(chip, CMD,
538 ATI_REG_CMD_POWERDOWN | ATI_REG_CMD_AC_RESET,
539 ATI_REG_CMD_POWERDOWN);
540 return 0;
541}
542#endif
543
544/*
545 * auto-detection of codecs
546 *
547 * the IXP chip can generate interrupts for the non-existing codecs.
548 * NEW_FRAME interrupt is used to make sure that the interrupt is generated
549 * even if all three codecs are connected.
550 */
551
552#define ALL_CODEC_NOT_READY \
553 (ATI_REG_ISR_CODEC0_NOT_READY |\
554 ATI_REG_ISR_CODEC1_NOT_READY |\
555 ATI_REG_ISR_CODEC2_NOT_READY)
556#define CODEC_CHECK_BITS (ALL_CODEC_NOT_READY|ATI_REG_ISR_NEW_FRAME)
557
558static int ac97_probing_bugs(struct pci_dev *pci)
559{
560 const struct snd_pci_quirk *q;
561
562 q = snd_pci_quirk_lookup(pci, atiixp_quirks);
563 if (q) {
564 dev_dbg(&pci->dev, "atiixp quirk for %s. Forcing codec %d\n",
565 snd_pci_quirk_name(q), q->value);
566 return q->value;
567 }
568 /* this hardware doesn't need workarounds. Probe for codec */
569 return -1;
570}
571
572static int snd_atiixp_codec_detect(struct atiixp *chip)
573{
574 int timeout;
575
576 chip->codec_not_ready_bits = 0;
577 if (ac97_codec == -1)
578 ac97_codec = ac97_probing_bugs(chip->pci);
579 if (ac97_codec >= 0) {
580 chip->codec_not_ready_bits |=
581 CODEC_CHECK_BITS ^ (1 << (ac97_codec + 10));
582 return 0;
583 }
584
585 atiixp_write(chip, IER, CODEC_CHECK_BITS);
586 /* wait for the interrupts */
587 timeout = 50;
588 while (timeout-- > 0) {
589 mdelay(1);
590 if (chip->codec_not_ready_bits)
591 break;
592 }
593 atiixp_write(chip, IER, 0); /* disable irqs */
594
595 if ((chip->codec_not_ready_bits & ALL_CODEC_NOT_READY) == ALL_CODEC_NOT_READY) {
596 dev_err(chip->card->dev, "no codec detected!\n");
597 return -ENXIO;
598 }
599 return 0;
600}
601
602
603/*
604 * enable DMA and irqs
605 */
606static int snd_atiixp_chip_start(struct atiixp *chip)
607{
608 unsigned int reg;
609
610 /* set up spdif, enable burst mode */
611 reg = atiixp_read(chip, CMD);
612 reg |= 0x02 << ATI_REG_CMD_SPDF_THRESHOLD_SHIFT;
613 reg |= ATI_REG_CMD_BURST_EN;
614 atiixp_write(chip, CMD, reg);
615
616 reg = atiixp_read(chip, SPDF_CMD);
617 reg &= ~(ATI_REG_SPDF_CMD_LFSR|ATI_REG_SPDF_CMD_SINGLE_CH);
618 atiixp_write(chip, SPDF_CMD, reg);
619
620 /* clear all interrupt source */
621 atiixp_write(chip, ISR, 0xffffffff);
622 /* enable irqs */
623 atiixp_write(chip, IER,
624 ATI_REG_IER_IO_STATUS_EN |
625 ATI_REG_IER_IN_XRUN_EN |
626 ATI_REG_IER_OUT_XRUN_EN |
627 ATI_REG_IER_SPDF_XRUN_EN |
628 ATI_REG_IER_SPDF_STATUS_EN);
629 return 0;
630}
631
632
633/*
634 * disable DMA and IRQs
635 */
636static int snd_atiixp_chip_stop(struct atiixp *chip)
637{
638 /* clear interrupt source */
639 atiixp_write(chip, ISR, atiixp_read(chip, ISR));
640 /* disable irqs */
641 atiixp_write(chip, IER, 0);
642 return 0;
643}
644
645
646/*
647 * PCM section
648 */
649
650/*
651 * pointer callback simplly reads XXX_DMA_DT_CUR register as the current
652 * position. when SG-buffer is implemented, the offset must be calculated
653 * correctly...
654 */
655static snd_pcm_uframes_t snd_atiixp_pcm_pointer(struct snd_pcm_substream *substream)
656{
657 struct atiixp *chip = snd_pcm_substream_chip(substream);
658 struct snd_pcm_runtime *runtime = substream->runtime;
659 struct atiixp_dma *dma = runtime->private_data;
660 unsigned int curptr;
661 int timeout = 1000;
662
663 while (timeout--) {
664 curptr = readl(chip->remap_addr + dma->ops->dt_cur);
665 if (curptr < dma->buf_addr)
666 continue;
667 curptr -= dma->buf_addr;
668 if (curptr >= dma->buf_bytes)
669 continue;
670 return bytes_to_frames(runtime, curptr);
671 }
672 dev_dbg(chip->card->dev, "invalid DMA pointer read 0x%x (buf=%x)\n",
673 readl(chip->remap_addr + dma->ops->dt_cur), dma->buf_addr);
674 return 0;
675}
676
677/*
678 * XRUN detected, and stop the PCM substream
679 */
680static void snd_atiixp_xrun_dma(struct atiixp *chip, struct atiixp_dma *dma)
681{
682 if (! dma->substream || ! dma->running)
683 return;
684 dev_dbg(chip->card->dev, "XRUN detected (DMA %d)\n", dma->ops->type);
685 snd_pcm_stop_xrun(dma->substream);
686}
687
688/*
689 * the period ack. update the substream.
690 */
691static void snd_atiixp_update_dma(struct atiixp *chip, struct atiixp_dma *dma)
692{
693 if (! dma->substream || ! dma->running)
694 return;
695 snd_pcm_period_elapsed(dma->substream);
696}
697
698/* set BUS_BUSY interrupt bit if any DMA is running */
699/* call with spinlock held */
700static void snd_atiixp_check_bus_busy(struct atiixp *chip)
701{
702 unsigned int bus_busy;
703 if (atiixp_read(chip, CMD) & (ATI_REG_CMD_SEND_EN |
704 ATI_REG_CMD_RECEIVE_EN |
705 ATI_REG_CMD_SPDF_OUT_EN))
706 bus_busy = ATI_REG_IER_SET_BUS_BUSY;
707 else
708 bus_busy = 0;
709 atiixp_update(chip, IER, ATI_REG_IER_SET_BUS_BUSY, bus_busy);
710}
711
712/* common trigger callback
713 * calling the lowlevel callbacks in it
714 */
715static int snd_atiixp_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
716{
717 struct atiixp *chip = snd_pcm_substream_chip(substream);
718 struct atiixp_dma *dma = substream->runtime->private_data;
719 int err = 0;
720
721 if (snd_BUG_ON(!dma->ops->enable_transfer ||
722 !dma->ops->flush_dma))
723 return -EINVAL;
724
725 spin_lock(&chip->reg_lock);
726 switch (cmd) {
727 case SNDRV_PCM_TRIGGER_START:
728 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
729 case SNDRV_PCM_TRIGGER_RESUME:
730 if (dma->running && dma->suspended &&
731 cmd == SNDRV_PCM_TRIGGER_RESUME)
732 writel(dma->saved_curptr, chip->remap_addr +
733 dma->ops->dt_cur);
734 dma->ops->enable_transfer(chip, 1);
735 dma->running = 1;
736 dma->suspended = 0;
737 break;
738 case SNDRV_PCM_TRIGGER_STOP:
739 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
740 case SNDRV_PCM_TRIGGER_SUSPEND:
741 dma->suspended = cmd == SNDRV_PCM_TRIGGER_SUSPEND;
742 if (dma->running && dma->suspended)
743 dma->saved_curptr = readl(chip->remap_addr +
744 dma->ops->dt_cur);
745 dma->ops->enable_transfer(chip, 0);
746 dma->running = 0;
747 break;
748 default:
749 err = -EINVAL;
750 break;
751 }
752 if (! err) {
753 snd_atiixp_check_bus_busy(chip);
754 if (cmd == SNDRV_PCM_TRIGGER_STOP) {
755 dma->ops->flush_dma(chip);
756 snd_atiixp_check_bus_busy(chip);
757 }
758 }
759 spin_unlock(&chip->reg_lock);
760 return err;
761}
762
763
764/*
765 * lowlevel callbacks for each DMA type
766 *
767 * every callback is supposed to be called in chip->reg_lock spinlock
768 */
769
770/* flush FIFO of analog OUT DMA */
771static void atiixp_out_flush_dma(struct atiixp *chip)
772{
773 atiixp_write(chip, FIFO_FLUSH, ATI_REG_FIFO_OUT_FLUSH);
774}
775
776/* enable/disable analog OUT DMA */
777static void atiixp_out_enable_dma(struct atiixp *chip, int on)
778{
779 unsigned int data;
780 data = atiixp_read(chip, CMD);
781 if (on) {
782 if (data & ATI_REG_CMD_OUT_DMA_EN)
783 return;
784 atiixp_out_flush_dma(chip);
785 data |= ATI_REG_CMD_OUT_DMA_EN;
786 } else
787 data &= ~ATI_REG_CMD_OUT_DMA_EN;
788 atiixp_write(chip, CMD, data);
789}
790
791/* start/stop transfer over OUT DMA */
792static void atiixp_out_enable_transfer(struct atiixp *chip, int on)
793{
794 atiixp_update(chip, CMD, ATI_REG_CMD_SEND_EN,
795 on ? ATI_REG_CMD_SEND_EN : 0);
796}
797
798/* enable/disable analog IN DMA */
799static void atiixp_in_enable_dma(struct atiixp *chip, int on)
800{
801 atiixp_update(chip, CMD, ATI_REG_CMD_IN_DMA_EN,
802 on ? ATI_REG_CMD_IN_DMA_EN : 0);
803}
804
805/* start/stop analog IN DMA */
806static void atiixp_in_enable_transfer(struct atiixp *chip, int on)
807{
808 if (on) {
809 unsigned int data = atiixp_read(chip, CMD);
810 if (! (data & ATI_REG_CMD_RECEIVE_EN)) {
811 data |= ATI_REG_CMD_RECEIVE_EN;
812#if 0 /* FIXME: this causes the endless loop */
813 /* wait until slot 3/4 are finished */
814 while ((atiixp_read(chip, COUNTER) &
815 ATI_REG_COUNTER_SLOT) != 5)
816 ;
817#endif
818 atiixp_write(chip, CMD, data);
819 }
820 } else
821 atiixp_update(chip, CMD, ATI_REG_CMD_RECEIVE_EN, 0);
822}
823
824/* flush FIFO of analog IN DMA */
825static void atiixp_in_flush_dma(struct atiixp *chip)
826{
827 atiixp_write(chip, FIFO_FLUSH, ATI_REG_FIFO_IN_FLUSH);
828}
829
830/* enable/disable SPDIF OUT DMA */
831static void atiixp_spdif_enable_dma(struct atiixp *chip, int on)
832{
833 atiixp_update(chip, CMD, ATI_REG_CMD_SPDF_DMA_EN,
834 on ? ATI_REG_CMD_SPDF_DMA_EN : 0);
835}
836
837/* start/stop SPDIF OUT DMA */
838static void atiixp_spdif_enable_transfer(struct atiixp *chip, int on)
839{
840 unsigned int data;
841 data = atiixp_read(chip, CMD);
842 if (on)
843 data |= ATI_REG_CMD_SPDF_OUT_EN;
844 else
845 data &= ~ATI_REG_CMD_SPDF_OUT_EN;
846 atiixp_write(chip, CMD, data);
847}
848
849/* flush FIFO of SPDIF OUT DMA */
850static void atiixp_spdif_flush_dma(struct atiixp *chip)
851{
852 int timeout;
853
854 /* DMA off, transfer on */
855 atiixp_spdif_enable_dma(chip, 0);
856 atiixp_spdif_enable_transfer(chip, 1);
857
858 timeout = 100;
859 do {
860 if (! (atiixp_read(chip, SPDF_DMA_DT_SIZE) & ATI_REG_DMA_FIFO_USED))
861 break;
862 udelay(1);
863 } while (timeout-- > 0);
864
865 atiixp_spdif_enable_transfer(chip, 0);
866}
867
868/* set up slots and formats for SPDIF OUT */
869static int snd_atiixp_spdif_prepare(struct snd_pcm_substream *substream)
870{
871 struct atiixp *chip = snd_pcm_substream_chip(substream);
872
873 spin_lock_irq(&chip->reg_lock);
874 if (chip->spdif_over_aclink) {
875 unsigned int data;
876 /* enable slots 10/11 */
877 atiixp_update(chip, CMD, ATI_REG_CMD_SPDF_CONFIG_MASK,
878 ATI_REG_CMD_SPDF_CONFIG_01);
879 data = atiixp_read(chip, OUT_DMA_SLOT) & ~ATI_REG_OUT_DMA_SLOT_MASK;
880 data |= ATI_REG_OUT_DMA_SLOT_BIT(10) |
881 ATI_REG_OUT_DMA_SLOT_BIT(11);
882 data |= 0x04 << ATI_REG_OUT_DMA_THRESHOLD_SHIFT;
883 atiixp_write(chip, OUT_DMA_SLOT, data);
884 atiixp_update(chip, CMD, ATI_REG_CMD_INTERLEAVE_OUT,
885 substream->runtime->format == SNDRV_PCM_FORMAT_S16_LE ?
886 ATI_REG_CMD_INTERLEAVE_OUT : 0);
887 } else {
888 atiixp_update(chip, CMD, ATI_REG_CMD_SPDF_CONFIG_MASK, 0);
889 atiixp_update(chip, CMD, ATI_REG_CMD_INTERLEAVE_SPDF, 0);
890 }
891 spin_unlock_irq(&chip->reg_lock);
892 return 0;
893}
894
895/* set up slots and formats for analog OUT */
896static int snd_atiixp_playback_prepare(struct snd_pcm_substream *substream)
897{
898 struct atiixp *chip = snd_pcm_substream_chip(substream);
899 unsigned int data;
900
901 spin_lock_irq(&chip->reg_lock);
902 data = atiixp_read(chip, OUT_DMA_SLOT) & ~ATI_REG_OUT_DMA_SLOT_MASK;
903 switch (substream->runtime->channels) {
904 case 8:
905 data |= ATI_REG_OUT_DMA_SLOT_BIT(10) |
906 ATI_REG_OUT_DMA_SLOT_BIT(11);
907 fallthrough;
908 case 6:
909 data |= ATI_REG_OUT_DMA_SLOT_BIT(7) |
910 ATI_REG_OUT_DMA_SLOT_BIT(8);
911 fallthrough;
912 case 4:
913 data |= ATI_REG_OUT_DMA_SLOT_BIT(6) |
914 ATI_REG_OUT_DMA_SLOT_BIT(9);
915 fallthrough;
916 default:
917 data |= ATI_REG_OUT_DMA_SLOT_BIT(3) |
918 ATI_REG_OUT_DMA_SLOT_BIT(4);
919 break;
920 }
921
922 /* set output threshold */
923 data |= 0x04 << ATI_REG_OUT_DMA_THRESHOLD_SHIFT;
924 atiixp_write(chip, OUT_DMA_SLOT, data);
925
926 atiixp_update(chip, CMD, ATI_REG_CMD_INTERLEAVE_OUT,
927 substream->runtime->format == SNDRV_PCM_FORMAT_S16_LE ?
928 ATI_REG_CMD_INTERLEAVE_OUT : 0);
929
930 /*
931 * enable 6 channel re-ordering bit if needed
932 */
933 atiixp_update(chip, 6CH_REORDER, ATI_REG_6CH_REORDER_EN,
934 substream->runtime->channels >= 6 ? ATI_REG_6CH_REORDER_EN: 0);
935
936 spin_unlock_irq(&chip->reg_lock);
937 return 0;
938}
939
940/* set up slots and formats for analog IN */
941static int snd_atiixp_capture_prepare(struct snd_pcm_substream *substream)
942{
943 struct atiixp *chip = snd_pcm_substream_chip(substream);
944
945 spin_lock_irq(&chip->reg_lock);
946 atiixp_update(chip, CMD, ATI_REG_CMD_INTERLEAVE_IN,
947 substream->runtime->format == SNDRV_PCM_FORMAT_S16_LE ?
948 ATI_REG_CMD_INTERLEAVE_IN : 0);
949 spin_unlock_irq(&chip->reg_lock);
950 return 0;
951}
952
953/*
954 * hw_params - allocate the buffer and set up buffer descriptors
955 */
956static int snd_atiixp_pcm_hw_params(struct snd_pcm_substream *substream,
957 struct snd_pcm_hw_params *hw_params)
958{
959 struct atiixp *chip = snd_pcm_substream_chip(substream);
960 struct atiixp_dma *dma = substream->runtime->private_data;
961 int err;
962
963 dma->buf_addr = substream->runtime->dma_addr;
964 dma->buf_bytes = params_buffer_bytes(hw_params);
965
966 err = atiixp_build_dma_packets(chip, dma, substream,
967 params_periods(hw_params),
968 params_period_bytes(hw_params));
969 if (err < 0)
970 return err;
971
972 if (dma->ac97_pcm_type >= 0) {
973 struct ac97_pcm *pcm = chip->pcms[dma->ac97_pcm_type];
974 /* PCM is bound to AC97 codec(s)
975 * set up the AC97 codecs
976 */
977 if (dma->pcm_open_flag) {
978 snd_ac97_pcm_close(pcm);
979 dma->pcm_open_flag = 0;
980 }
981 err = snd_ac97_pcm_open(pcm, params_rate(hw_params),
982 params_channels(hw_params),
983 pcm->r[0].slots);
984 if (err >= 0)
985 dma->pcm_open_flag = 1;
986 }
987
988 return err;
989}
990
991static int snd_atiixp_pcm_hw_free(struct snd_pcm_substream *substream)
992{
993 struct atiixp *chip = snd_pcm_substream_chip(substream);
994 struct atiixp_dma *dma = substream->runtime->private_data;
995
996 if (dma->pcm_open_flag) {
997 struct ac97_pcm *pcm = chip->pcms[dma->ac97_pcm_type];
998 snd_ac97_pcm_close(pcm);
999 dma->pcm_open_flag = 0;
1000 }
1001 atiixp_clear_dma_packets(chip, dma, substream);
1002 return 0;
1003}
1004
1005
1006/*
1007 * pcm hardware definition, identical for all DMA types
1008 */
1009static const struct snd_pcm_hardware snd_atiixp_pcm_hw =
1010{
1011 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1012 SNDRV_PCM_INFO_BLOCK_TRANSFER |
1013 SNDRV_PCM_INFO_PAUSE |
1014 SNDRV_PCM_INFO_RESUME |
1015 SNDRV_PCM_INFO_MMAP_VALID),
1016 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE,
1017 .rates = SNDRV_PCM_RATE_48000,
1018 .rate_min = 48000,
1019 .rate_max = 48000,
1020 .channels_min = 2,
1021 .channels_max = 2,
1022 .buffer_bytes_max = 256 * 1024,
1023 .period_bytes_min = 32,
1024 .period_bytes_max = 128 * 1024,
1025 .periods_min = 2,
1026 .periods_max = ATI_MAX_DESCRIPTORS,
1027};
1028
1029static int snd_atiixp_pcm_open(struct snd_pcm_substream *substream,
1030 struct atiixp_dma *dma, int pcm_type)
1031{
1032 struct atiixp *chip = snd_pcm_substream_chip(substream);
1033 struct snd_pcm_runtime *runtime = substream->runtime;
1034 int err;
1035
1036 if (snd_BUG_ON(!dma->ops || !dma->ops->enable_dma))
1037 return -EINVAL;
1038
1039 if (dma->opened)
1040 return -EBUSY;
1041 dma->substream = substream;
1042 runtime->hw = snd_atiixp_pcm_hw;
1043 dma->ac97_pcm_type = pcm_type;
1044 if (pcm_type >= 0) {
1045 runtime->hw.rates = chip->pcms[pcm_type]->rates;
1046 snd_pcm_limit_hw_rates(runtime);
1047 } else {
1048 /* direct SPDIF */
1049 runtime->hw.formats = SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE;
1050 }
1051 err = snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS);
1052 if (err < 0)
1053 return err;
1054 runtime->private_data = dma;
1055
1056 /* enable DMA bits */
1057 spin_lock_irq(&chip->reg_lock);
1058 dma->ops->enable_dma(chip, 1);
1059 spin_unlock_irq(&chip->reg_lock);
1060 dma->opened = 1;
1061
1062 return 0;
1063}
1064
1065static int snd_atiixp_pcm_close(struct snd_pcm_substream *substream,
1066 struct atiixp_dma *dma)
1067{
1068 struct atiixp *chip = snd_pcm_substream_chip(substream);
1069 /* disable DMA bits */
1070 if (snd_BUG_ON(!dma->ops || !dma->ops->enable_dma))
1071 return -EINVAL;
1072 spin_lock_irq(&chip->reg_lock);
1073 dma->ops->enable_dma(chip, 0);
1074 spin_unlock_irq(&chip->reg_lock);
1075 dma->substream = NULL;
1076 dma->opened = 0;
1077 return 0;
1078}
1079
1080/*
1081 */
1082static int snd_atiixp_playback_open(struct snd_pcm_substream *substream)
1083{
1084 struct atiixp *chip = snd_pcm_substream_chip(substream);
1085 int err;
1086
1087 mutex_lock(&chip->open_mutex);
1088 err = snd_atiixp_pcm_open(substream, &chip->dmas[ATI_DMA_PLAYBACK], 0);
1089 mutex_unlock(&chip->open_mutex);
1090 if (err < 0)
1091 return err;
1092 substream->runtime->hw.channels_max = chip->max_channels;
1093 if (chip->max_channels > 2)
1094 /* channels must be even */
1095 snd_pcm_hw_constraint_step(substream->runtime, 0,
1096 SNDRV_PCM_HW_PARAM_CHANNELS, 2);
1097 return 0;
1098}
1099
1100static int snd_atiixp_playback_close(struct snd_pcm_substream *substream)
1101{
1102 struct atiixp *chip = snd_pcm_substream_chip(substream);
1103 int err;
1104 mutex_lock(&chip->open_mutex);
1105 err = snd_atiixp_pcm_close(substream, &chip->dmas[ATI_DMA_PLAYBACK]);
1106 mutex_unlock(&chip->open_mutex);
1107 return err;
1108}
1109
1110static int snd_atiixp_capture_open(struct snd_pcm_substream *substream)
1111{
1112 struct atiixp *chip = snd_pcm_substream_chip(substream);
1113 return snd_atiixp_pcm_open(substream, &chip->dmas[ATI_DMA_CAPTURE], 1);
1114}
1115
1116static int snd_atiixp_capture_close(struct snd_pcm_substream *substream)
1117{
1118 struct atiixp *chip = snd_pcm_substream_chip(substream);
1119 return snd_atiixp_pcm_close(substream, &chip->dmas[ATI_DMA_CAPTURE]);
1120}
1121
1122static int snd_atiixp_spdif_open(struct snd_pcm_substream *substream)
1123{
1124 struct atiixp *chip = snd_pcm_substream_chip(substream);
1125 int err;
1126 mutex_lock(&chip->open_mutex);
1127 if (chip->spdif_over_aclink) /* share DMA_PLAYBACK */
1128 err = snd_atiixp_pcm_open(substream, &chip->dmas[ATI_DMA_PLAYBACK], 2);
1129 else
1130 err = snd_atiixp_pcm_open(substream, &chip->dmas[ATI_DMA_SPDIF], -1);
1131 mutex_unlock(&chip->open_mutex);
1132 return err;
1133}
1134
1135static int snd_atiixp_spdif_close(struct snd_pcm_substream *substream)
1136{
1137 struct atiixp *chip = snd_pcm_substream_chip(substream);
1138 int err;
1139 mutex_lock(&chip->open_mutex);
1140 if (chip->spdif_over_aclink)
1141 err = snd_atiixp_pcm_close(substream, &chip->dmas[ATI_DMA_PLAYBACK]);
1142 else
1143 err = snd_atiixp_pcm_close(substream, &chip->dmas[ATI_DMA_SPDIF]);
1144 mutex_unlock(&chip->open_mutex);
1145 return err;
1146}
1147
1148/* AC97 playback */
1149static const struct snd_pcm_ops snd_atiixp_playback_ops = {
1150 .open = snd_atiixp_playback_open,
1151 .close = snd_atiixp_playback_close,
1152 .hw_params = snd_atiixp_pcm_hw_params,
1153 .hw_free = snd_atiixp_pcm_hw_free,
1154 .prepare = snd_atiixp_playback_prepare,
1155 .trigger = snd_atiixp_pcm_trigger,
1156 .pointer = snd_atiixp_pcm_pointer,
1157};
1158
1159/* AC97 capture */
1160static const struct snd_pcm_ops snd_atiixp_capture_ops = {
1161 .open = snd_atiixp_capture_open,
1162 .close = snd_atiixp_capture_close,
1163 .hw_params = snd_atiixp_pcm_hw_params,
1164 .hw_free = snd_atiixp_pcm_hw_free,
1165 .prepare = snd_atiixp_capture_prepare,
1166 .trigger = snd_atiixp_pcm_trigger,
1167 .pointer = snd_atiixp_pcm_pointer,
1168};
1169
1170/* SPDIF playback */
1171static const struct snd_pcm_ops snd_atiixp_spdif_ops = {
1172 .open = snd_atiixp_spdif_open,
1173 .close = snd_atiixp_spdif_close,
1174 .hw_params = snd_atiixp_pcm_hw_params,
1175 .hw_free = snd_atiixp_pcm_hw_free,
1176 .prepare = snd_atiixp_spdif_prepare,
1177 .trigger = snd_atiixp_pcm_trigger,
1178 .pointer = snd_atiixp_pcm_pointer,
1179};
1180
1181static const struct ac97_pcm atiixp_pcm_defs[] = {
1182 /* front PCM */
1183 {
1184 .exclusive = 1,
1185 .r = { {
1186 .slots = (1 << AC97_SLOT_PCM_LEFT) |
1187 (1 << AC97_SLOT_PCM_RIGHT) |
1188 (1 << AC97_SLOT_PCM_CENTER) |
1189 (1 << AC97_SLOT_PCM_SLEFT) |
1190 (1 << AC97_SLOT_PCM_SRIGHT) |
1191 (1 << AC97_SLOT_LFE)
1192 }
1193 }
1194 },
1195 /* PCM IN #1 */
1196 {
1197 .stream = 1,
1198 .exclusive = 1,
1199 .r = { {
1200 .slots = (1 << AC97_SLOT_PCM_LEFT) |
1201 (1 << AC97_SLOT_PCM_RIGHT)
1202 }
1203 }
1204 },
1205 /* S/PDIF OUT (optional) */
1206 {
1207 .exclusive = 1,
1208 .spdif = 1,
1209 .r = { {
1210 .slots = (1 << AC97_SLOT_SPDIF_LEFT2) |
1211 (1 << AC97_SLOT_SPDIF_RIGHT2)
1212 }
1213 }
1214 },
1215};
1216
1217static const struct atiixp_dma_ops snd_atiixp_playback_dma_ops = {
1218 .type = ATI_DMA_PLAYBACK,
1219 .llp_offset = ATI_REG_OUT_DMA_LINKPTR,
1220 .dt_cur = ATI_REG_OUT_DMA_DT_CUR,
1221 .enable_dma = atiixp_out_enable_dma,
1222 .enable_transfer = atiixp_out_enable_transfer,
1223 .flush_dma = atiixp_out_flush_dma,
1224};
1225
1226static const struct atiixp_dma_ops snd_atiixp_capture_dma_ops = {
1227 .type = ATI_DMA_CAPTURE,
1228 .llp_offset = ATI_REG_IN_DMA_LINKPTR,
1229 .dt_cur = ATI_REG_IN_DMA_DT_CUR,
1230 .enable_dma = atiixp_in_enable_dma,
1231 .enable_transfer = atiixp_in_enable_transfer,
1232 .flush_dma = atiixp_in_flush_dma,
1233};
1234
1235static const struct atiixp_dma_ops snd_atiixp_spdif_dma_ops = {
1236 .type = ATI_DMA_SPDIF,
1237 .llp_offset = ATI_REG_SPDF_DMA_LINKPTR,
1238 .dt_cur = ATI_REG_SPDF_DMA_DT_CUR,
1239 .enable_dma = atiixp_spdif_enable_dma,
1240 .enable_transfer = atiixp_spdif_enable_transfer,
1241 .flush_dma = atiixp_spdif_flush_dma,
1242};
1243
1244
1245static int snd_atiixp_pcm_new(struct atiixp *chip)
1246{
1247 struct snd_pcm *pcm;
1248 struct snd_pcm_chmap *chmap;
1249 struct snd_ac97_bus *pbus = chip->ac97_bus;
1250 int err, i, num_pcms;
1251
1252 /* initialize constants */
1253 chip->dmas[ATI_DMA_PLAYBACK].ops = &snd_atiixp_playback_dma_ops;
1254 chip->dmas[ATI_DMA_CAPTURE].ops = &snd_atiixp_capture_dma_ops;
1255 if (! chip->spdif_over_aclink)
1256 chip->dmas[ATI_DMA_SPDIF].ops = &snd_atiixp_spdif_dma_ops;
1257
1258 /* assign AC97 pcm */
1259 if (chip->spdif_over_aclink)
1260 num_pcms = 3;
1261 else
1262 num_pcms = 2;
1263 err = snd_ac97_pcm_assign(pbus, num_pcms, atiixp_pcm_defs);
1264 if (err < 0)
1265 return err;
1266 for (i = 0; i < num_pcms; i++)
1267 chip->pcms[i] = &pbus->pcms[i];
1268
1269 chip->max_channels = 2;
1270 if (pbus->pcms[ATI_PCM_OUT].r[0].slots & (1 << AC97_SLOT_PCM_SLEFT)) {
1271 if (pbus->pcms[ATI_PCM_OUT].r[0].slots & (1 << AC97_SLOT_LFE))
1272 chip->max_channels = 6;
1273 else
1274 chip->max_channels = 4;
1275 }
1276
1277 /* PCM #0: analog I/O */
1278 err = snd_pcm_new(chip->card, "ATI IXP AC97",
1279 ATI_PCMDEV_ANALOG, 1, 1, &pcm);
1280 if (err < 0)
1281 return err;
1282 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_atiixp_playback_ops);
1283 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_atiixp_capture_ops);
1284 pcm->private_data = chip;
1285 strcpy(pcm->name, "ATI IXP AC97");
1286 chip->pcmdevs[ATI_PCMDEV_ANALOG] = pcm;
1287
1288 snd_pcm_set_managed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV,
1289 &chip->pci->dev, 64*1024, 128*1024);
1290
1291 err = snd_pcm_add_chmap_ctls(pcm, SNDRV_PCM_STREAM_PLAYBACK,
1292 snd_pcm_alt_chmaps, chip->max_channels, 0,
1293 &chmap);
1294 if (err < 0)
1295 return err;
1296 chmap->channel_mask = SND_PCM_CHMAP_MASK_2468;
1297 chip->ac97[0]->chmaps[SNDRV_PCM_STREAM_PLAYBACK] = chmap;
1298
1299 /* no SPDIF support on codec? */
1300 if (chip->pcms[ATI_PCM_SPDIF] && ! chip->pcms[ATI_PCM_SPDIF]->rates)
1301 return 0;
1302
1303 /* FIXME: non-48k sample rate doesn't work on my test machine with AD1888 */
1304 if (chip->pcms[ATI_PCM_SPDIF])
1305 chip->pcms[ATI_PCM_SPDIF]->rates = SNDRV_PCM_RATE_48000;
1306
1307 /* PCM #1: spdif playback */
1308 err = snd_pcm_new(chip->card, "ATI IXP IEC958",
1309 ATI_PCMDEV_DIGITAL, 1, 0, &pcm);
1310 if (err < 0)
1311 return err;
1312 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_atiixp_spdif_ops);
1313 pcm->private_data = chip;
1314 if (chip->spdif_over_aclink)
1315 strcpy(pcm->name, "ATI IXP IEC958 (AC97)");
1316 else
1317 strcpy(pcm->name, "ATI IXP IEC958 (Direct)");
1318 chip->pcmdevs[ATI_PCMDEV_DIGITAL] = pcm;
1319
1320 snd_pcm_set_managed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV,
1321 &chip->pci->dev, 64*1024, 128*1024);
1322
1323 /* pre-select AC97 SPDIF slots 10/11 */
1324 for (i = 0; i < NUM_ATI_CODECS; i++) {
1325 if (chip->ac97[i])
1326 snd_ac97_update_bits(chip->ac97[i],
1327 AC97_EXTENDED_STATUS,
1328 0x03 << 4, 0x03 << 4);
1329 }
1330
1331 return 0;
1332}
1333
1334
1335
1336/*
1337 * interrupt handler
1338 */
1339static irqreturn_t snd_atiixp_interrupt(int irq, void *dev_id)
1340{
1341 struct atiixp *chip = dev_id;
1342 unsigned int status;
1343
1344 status = atiixp_read(chip, ISR);
1345
1346 if (! status)
1347 return IRQ_NONE;
1348
1349 /* process audio DMA */
1350 if (status & ATI_REG_ISR_OUT_XRUN)
1351 snd_atiixp_xrun_dma(chip, &chip->dmas[ATI_DMA_PLAYBACK]);
1352 else if (status & ATI_REG_ISR_OUT_STATUS)
1353 snd_atiixp_update_dma(chip, &chip->dmas[ATI_DMA_PLAYBACK]);
1354 if (status & ATI_REG_ISR_IN_XRUN)
1355 snd_atiixp_xrun_dma(chip, &chip->dmas[ATI_DMA_CAPTURE]);
1356 else if (status & ATI_REG_ISR_IN_STATUS)
1357 snd_atiixp_update_dma(chip, &chip->dmas[ATI_DMA_CAPTURE]);
1358 if (! chip->spdif_over_aclink) {
1359 if (status & ATI_REG_ISR_SPDF_XRUN)
1360 snd_atiixp_xrun_dma(chip, &chip->dmas[ATI_DMA_SPDIF]);
1361 else if (status & ATI_REG_ISR_SPDF_STATUS)
1362 snd_atiixp_update_dma(chip, &chip->dmas[ATI_DMA_SPDIF]);
1363 }
1364
1365 /* for codec detection */
1366 if (status & CODEC_CHECK_BITS) {
1367 unsigned int detected;
1368 detected = status & CODEC_CHECK_BITS;
1369 spin_lock(&chip->reg_lock);
1370 chip->codec_not_ready_bits |= detected;
1371 atiixp_update(chip, IER, detected, 0); /* disable the detected irqs */
1372 spin_unlock(&chip->reg_lock);
1373 }
1374
1375 /* ack */
1376 atiixp_write(chip, ISR, status);
1377
1378 return IRQ_HANDLED;
1379}
1380
1381
1382/*
1383 * ac97 mixer section
1384 */
1385
1386static const struct ac97_quirk ac97_quirks[] = {
1387 {
1388 .subvendor = 0x103c,
1389 .subdevice = 0x006b,
1390 .name = "HP Pavilion ZV5030US",
1391 .type = AC97_TUNE_MUTE_LED
1392 },
1393 {
1394 .subvendor = 0x103c,
1395 .subdevice = 0x308b,
1396 .name = "HP nx6125",
1397 .type = AC97_TUNE_MUTE_LED
1398 },
1399 {
1400 .subvendor = 0x103c,
1401 .subdevice = 0x3091,
1402 .name = "unknown HP",
1403 .type = AC97_TUNE_MUTE_LED
1404 },
1405 {0} /* terminator */
1406};
1407
1408static int snd_atiixp_mixer_new(struct atiixp *chip, int clock,
1409 const char *quirk_override)
1410{
1411 struct snd_ac97_bus *pbus;
1412 struct snd_ac97_template ac97;
1413 int i, err;
1414 int codec_count;
1415 static const struct snd_ac97_bus_ops ops = {
1416 .write = snd_atiixp_ac97_write,
1417 .read = snd_atiixp_ac97_read,
1418 };
1419 static const unsigned int codec_skip[NUM_ATI_CODECS] = {
1420 ATI_REG_ISR_CODEC0_NOT_READY,
1421 ATI_REG_ISR_CODEC1_NOT_READY,
1422 ATI_REG_ISR_CODEC2_NOT_READY,
1423 };
1424
1425 if (snd_atiixp_codec_detect(chip) < 0)
1426 return -ENXIO;
1427
1428 err = snd_ac97_bus(chip->card, 0, &ops, chip, &pbus);
1429 if (err < 0)
1430 return err;
1431 pbus->clock = clock;
1432 chip->ac97_bus = pbus;
1433
1434 codec_count = 0;
1435 for (i = 0; i < NUM_ATI_CODECS; i++) {
1436 if (chip->codec_not_ready_bits & codec_skip[i])
1437 continue;
1438 memset(&ac97, 0, sizeof(ac97));
1439 ac97.private_data = chip;
1440 ac97.pci = chip->pci;
1441 ac97.num = i;
1442 ac97.scaps = AC97_SCAP_SKIP_MODEM | AC97_SCAP_POWER_SAVE;
1443 if (! chip->spdif_over_aclink)
1444 ac97.scaps |= AC97_SCAP_NO_SPDIF;
1445 err = snd_ac97_mixer(pbus, &ac97, &chip->ac97[i]);
1446 if (err < 0) {
1447 chip->ac97[i] = NULL; /* to be sure */
1448 dev_dbg(chip->card->dev,
1449 "codec %d not available for audio\n", i);
1450 continue;
1451 }
1452 codec_count++;
1453 }
1454
1455 if (! codec_count) {
1456 dev_err(chip->card->dev, "no codec available\n");
1457 return -ENODEV;
1458 }
1459
1460 snd_ac97_tune_hardware(chip->ac97[0], ac97_quirks, quirk_override);
1461
1462 return 0;
1463}
1464
1465
1466#ifdef CONFIG_PM_SLEEP
1467/*
1468 * power management
1469 */
1470static int snd_atiixp_suspend(struct device *dev)
1471{
1472 struct snd_card *card = dev_get_drvdata(dev);
1473 struct atiixp *chip = card->private_data;
1474 int i;
1475
1476 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
1477 for (i = 0; i < NUM_ATI_CODECS; i++)
1478 snd_ac97_suspend(chip->ac97[i]);
1479 snd_atiixp_aclink_down(chip);
1480 snd_atiixp_chip_stop(chip);
1481 return 0;
1482}
1483
1484static int snd_atiixp_resume(struct device *dev)
1485{
1486 struct snd_card *card = dev_get_drvdata(dev);
1487 struct atiixp *chip = card->private_data;
1488 int i;
1489
1490 snd_atiixp_aclink_reset(chip);
1491 snd_atiixp_chip_start(chip);
1492
1493 for (i = 0; i < NUM_ATI_CODECS; i++)
1494 snd_ac97_resume(chip->ac97[i]);
1495
1496 for (i = 0; i < NUM_ATI_PCMDEVS; i++)
1497 if (chip->pcmdevs[i]) {
1498 struct atiixp_dma *dma = &chip->dmas[i];
1499 if (dma->substream && dma->suspended) {
1500 dma->ops->enable_dma(chip, 1);
1501 dma->substream->ops->prepare(dma->substream);
1502 writel((u32)dma->desc_buf.addr | ATI_REG_LINKPTR_EN,
1503 chip->remap_addr + dma->ops->llp_offset);
1504 }
1505 }
1506
1507 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
1508 return 0;
1509}
1510
1511static SIMPLE_DEV_PM_OPS(snd_atiixp_pm, snd_atiixp_suspend, snd_atiixp_resume);
1512#define SND_ATIIXP_PM_OPS &snd_atiixp_pm
1513#else
1514#define SND_ATIIXP_PM_OPS NULL
1515#endif /* CONFIG_PM_SLEEP */
1516
1517
1518/*
1519 * proc interface for register dump
1520 */
1521
1522static void snd_atiixp_proc_read(struct snd_info_entry *entry,
1523 struct snd_info_buffer *buffer)
1524{
1525 struct atiixp *chip = entry->private_data;
1526 int i;
1527
1528 for (i = 0; i < 256; i += 4)
1529 snd_iprintf(buffer, "%02x: %08x\n", i, readl(chip->remap_addr + i));
1530}
1531
1532static void snd_atiixp_proc_init(struct atiixp *chip)
1533{
1534 snd_card_ro_proc_new(chip->card, "atiixp", chip, snd_atiixp_proc_read);
1535}
1536
1537
1538/*
1539 * destructor
1540 */
1541
1542static void snd_atiixp_free(struct snd_card *card)
1543{
1544 snd_atiixp_chip_stop(card->private_data);
1545}
1546
1547/*
1548 * constructor for chip instance
1549 */
1550static int snd_atiixp_init(struct snd_card *card, struct pci_dev *pci)
1551{
1552 struct atiixp *chip = card->private_data;
1553 int err;
1554
1555 err = pcim_enable_device(pci);
1556 if (err < 0)
1557 return err;
1558
1559 spin_lock_init(&chip->reg_lock);
1560 mutex_init(&chip->open_mutex);
1561 chip->card = card;
1562 chip->pci = pci;
1563 chip->irq = -1;
1564 err = pcim_iomap_regions(pci, 1 << 0, "ATI IXP AC97");
1565 if (err < 0)
1566 return err;
1567 chip->addr = pci_resource_start(pci, 0);
1568 chip->remap_addr = pcim_iomap_table(pci)[0];
1569 if (devm_request_irq(&pci->dev, pci->irq, snd_atiixp_interrupt,
1570 IRQF_SHARED, KBUILD_MODNAME, chip)) {
1571 dev_err(card->dev, "unable to grab IRQ %d\n", pci->irq);
1572 return -EBUSY;
1573 }
1574 chip->irq = pci->irq;
1575 card->sync_irq = chip->irq;
1576 card->private_free = snd_atiixp_free;
1577 pci_set_master(pci);
1578
1579 return 0;
1580}
1581
1582
1583static int __snd_atiixp_probe(struct pci_dev *pci,
1584 const struct pci_device_id *pci_id)
1585{
1586 struct snd_card *card;
1587 struct atiixp *chip;
1588 int err;
1589
1590 err = snd_devm_card_new(&pci->dev, index, id, THIS_MODULE,
1591 sizeof(*chip), &card);
1592 if (err < 0)
1593 return err;
1594 chip = card->private_data;
1595
1596 strcpy(card->driver, spdif_aclink ? "ATIIXP" : "ATIIXP-SPDMA");
1597 strcpy(card->shortname, "ATI IXP");
1598 err = snd_atiixp_init(card, pci);
1599 if (err < 0)
1600 return err;
1601
1602 err = snd_atiixp_aclink_reset(chip);
1603 if (err < 0)
1604 return err;
1605
1606 chip->spdif_over_aclink = spdif_aclink;
1607
1608 err = snd_atiixp_mixer_new(chip, ac97_clock, ac97_quirk);
1609 if (err < 0)
1610 return err;
1611
1612 err = snd_atiixp_pcm_new(chip);
1613 if (err < 0)
1614 return err;
1615
1616 snd_atiixp_proc_init(chip);
1617
1618 snd_atiixp_chip_start(chip);
1619
1620 snprintf(card->longname, sizeof(card->longname),
1621 "%s rev %x with %s at %#lx, irq %i", card->shortname,
1622#ifndef TARGET_OS2
1623 pci->revision,
1624#else
1625 snd_pci_revision(pci),
1626#endif
1627 chip->ac97[0] ? snd_ac97_get_short_name(chip->ac97[0]) : "?",
1628 chip->addr, chip->irq);
1629
1630 err = snd_card_register(card);
1631 if (err < 0)
1632 return err;
1633
1634 pci_set_drvdata(pci, card);
1635 return 0;
1636}
1637
1638static int snd_atiixp_probe(struct pci_dev *pci,
1639 const struct pci_device_id *pci_id)
1640{
1641 return snd_card_free_on_error(&pci->dev, __snd_atiixp_probe(pci, pci_id));
1642}
1643
1644static struct pci_driver atiixp_driver = {
1645 .name = KBUILD_MODNAME,
1646 .id_table = snd_atiixp_ids,
1647 .probe = snd_atiixp_probe,
1648 .driver = {
1649 .pm = SND_ATIIXP_PM_OPS,
1650 },
1651};
1652
1653module_pci_driver(atiixp_driver);
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