Changeset 160 for trunk/src/os2ahci/ahci.c
- Timestamp:
- May 31, 2013, 2:03:41 AM (12 years ago)
- File:
-
- 1 edited
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- Unmodified
- Added
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trunk/src/os2ahci/ahci.c
r157 r160 162 162 163 163 /* print AHCI register debug information */ 164 #ifdef DEBUG 164 165 if (debug) { 165 printf("AHCI global controller registers:\n");166 aprintf("AHCI global controller registers:\n"); 166 167 for (i = 0; i <= HOST_CAP2 / sizeof(u32); i++) { 167 168 u32 val = ai->bios_config[i]; 168 printf(" %02x: %08lx", i, val);169 aprintf(" %02x: %08lx", i, val); 169 170 170 171 if (i == HOST_CAP) { 171 printf_nts(" -");172 if (val & HOST_CAP_64) printf_nts(" 64bit");173 if (val & HOST_CAP_NCQ) printf_nts(" ncq");174 if (val & HOST_CAP_SNTF) printf_nts(" sntf");175 if (val & HOST_CAP_MPS) printf_nts(" mps");176 if (val & HOST_CAP_SSS) printf_nts(" sss");177 if (val & HOST_CAP_ALPM) printf_nts(" alpm");178 if (val & HOST_CAP_LED) printf_nts(" led");179 if (val & HOST_CAP_CLO) printf_nts(" clo");180 if (val & HOST_CAP_ONLY) printf_nts(" ahci_only");181 if (val & HOST_CAP_PMP) printf_nts(" pmp");182 if (val & HOST_CAP_FBS) printf_nts(" fbs");183 if (val & HOST_CAP_PIO_MULTI) printf_nts(" pio_multi");184 if (val & HOST_CAP_SSC) printf_nts(" ssc");185 if (val & HOST_CAP_PART) printf_nts(" part");186 if (val & HOST_CAP_CCC) printf_nts(" ccc");187 if (val & HOST_CAP_EMS) printf_nts(" ems");188 if (val & HOST_CAP_SXS) printf_nts(" sxs");189 printf_nts(" cmd_slots:%d", (u16) ((val >> 8) & 0x1f) + 1);190 printf_nts(" ports:%d", (u16) (val & 0x1f) + 1);172 ntprintf(" -"); 173 if (val & HOST_CAP_64) ntprintf(" 64bit"); 174 if (val & HOST_CAP_NCQ) ntprintf(" ncq"); 175 if (val & HOST_CAP_SNTF) ntprintf(" sntf"); 176 if (val & HOST_CAP_MPS) ntprintf(" mps"); 177 if (val & HOST_CAP_SSS) ntprintf(" sss"); 178 if (val & HOST_CAP_ALPM) ntprintf(" alpm"); 179 if (val & HOST_CAP_LED) ntprintf(" led"); 180 if (val & HOST_CAP_CLO) ntprintf(" clo"); 181 if (val & HOST_CAP_ONLY) ntprintf(" ahci_only"); 182 if (val & HOST_CAP_PMP) ntprintf(" pmp"); 183 if (val & HOST_CAP_FBS) ntprintf(" fbs"); 184 if (val & HOST_CAP_PIO_MULTI) ntprintf(" pio_multi"); 185 if (val & HOST_CAP_SSC) ntprintf(" ssc"); 186 if (val & HOST_CAP_PART) ntprintf(" part"); 187 if (val & HOST_CAP_CCC) ntprintf(" ccc"); 188 if (val & HOST_CAP_EMS) ntprintf(" ems"); 189 if (val & HOST_CAP_SXS) ntprintf(" sxs"); 190 ntprintf(" cmd_slots:%d", (u16) ((val >> 8) & 0x1f) + 1); 191 ntprintf(" ports:%d", (u16) (val & 0x1f) + 1); 191 192 192 193 } else if (i == HOST_CTL) { 193 printf_nts(" -");194 if (val & HOST_AHCI_EN) printf_nts(" ahci_enabled");195 if (val & HOST_IRQ_EN) printf_nts(" irq_enabled");196 if (val & HOST_RESET) printf_nts(" resetting");194 ntprintf(" -"); 195 if (val & HOST_AHCI_EN) ntprintf(" ahci_enabled"); 196 if (val & HOST_IRQ_EN) ntprintf(" irq_enabled"); 197 if (val & HOST_RESET) ntprintf(" resetting"); 197 198 198 199 } else if (i == HOST_CAP2) { 199 printf_nts(" -");200 if (val & HOST_CAP2_BOH) printf_nts(" boh");201 if (val & HOST_CAP2_NVMHCI) printf_nts(" nvmhci");202 if (val & HOST_CAP2_APST) printf_nts(" apst");200 ntprintf(" -"); 201 if (val & HOST_CAP2_BOH) ntprintf(" boh"); 202 if (val & HOST_CAP2_NVMHCI) ntprintf(" nvmhci"); 203 if (val & HOST_CAP2_APST) ntprintf(" apst"); 203 204 } 204 printf_nts("\n"); 205 } 206 } 205 ntprintf("\n"); 206 } 207 } 208 #endif 207 209 208 210 /* Save working copies of CAP, CAP2 and port_map and remove broken feature … … 337 339 } 338 340 } 339 340 /* Wait some time to give the COMRESET a chance to complete (usually, at341 * least hard disks complete the reset within a few milliseonds)342 */343 msleep(20);344 341 } 345 342 … … 456 453 } 457 454 458 int ahci_reset_controller(AD_INFO *ai)459 {460 u32 tmp;461 TIMER Timer;462 463 dprintf("controller reset starting on adapter %d\n", ad_no(ai));464 /* we must be in AHCI mode, before using anything465 * AHCI-specific, such as HOST_RESET.466 */467 ahci_enable_ahci(ai);468 469 /* global controller reset */470 tmp = readl(ai->mmio + HOST_CTL);471 if ((tmp & HOST_RESET) == 0) {472 writel(ai->mmio + HOST_CTL, tmp | HOST_RESET);473 readl(ai->mmio + HOST_CTL); /* flush */474 }475 476 /*477 * to perform host reset, OS should set HOST_RESET478 * and poll until this bit is read to be "0".479 * reset must complete within 1 second, or480 * the hardware should be considered fried.481 */482 timer_init(&Timer, 1000);483 while (((tmp = readl(ai->mmio + HOST_CTL)) & HOST_RESET) != 0) {484 if (timer_check_and_block(&Timer)) {485 dprintf("controller reset failed (0x%lx)\n", tmp);486 return(-1);487 }488 }489 490 /* turn on AHCI mode */491 ahci_enable_ahci(ai);492 493 /* Some registers might be cleared on reset. Restore494 * initial values.495 */496 ahci_restore_initial_config(ai);497 498 if (ai->pci->vendor == PCI_VENDOR_ID_INTEL) {499 u32 tmp16 = 0;500 501 ddprintf("ahci_reset_controller: intel detected\n");502 /* configure PCS */503 pci_read_conf(ai->bus, ai->dev_func, 0x92, sizeof(u16), &tmp16);504 if ((tmp16 & ai->port_map) != ai->port_map) {505 ddprintf("ahci_reset_controller: updating PCS %x/%x\n", (u16)tmp16, ai->port_map);506 tmp16 |= ai->port_map;507 pci_write_conf(ai->bus, ai->dev_func, 0x92, sizeof(u16), tmp16);508 }509 }510 511 return 0;512 }513 514 455 /****************************************************************************** 515 456 * Scan all ports for connected devices and fill in the corresponding device … … 547 488 ahci_save_bios_config(ai); 548 489 } 549 550 ahci_reset_controller(ai);551 490 552 491 if (ahci_enable_ahci(ai)) { … … 723 662 dprintf("ahci_reset_port: resetting port %d.%d\n", ad_no(ai), p); 724 663 if (debug > 1) { 725 printf(" PORT_CMD = 0x%lx\n", readl(port_mmio + PORT_CMD));726 printf("ahci_reset_port: command engine status:\n");727 printf(" PORT_SCR_ACT = 0x%lx\n", readl(port_mmio + PORT_SCR_ACT));728 printf(" PORT_CMD_ISSUE = 0x%lx\n", readl(port_mmio + PORT_CMD_ISSUE));729 printf("link/device status:\n");730 printf(" PORT_SCR_STAT = 0x%lx\n", readl(port_mmio + PORT_SCR_STAT));731 printf(" PORT_SCR_CTL = 0x%lx\n", readl(port_mmio + PORT_SCR_CTL));732 printf(" PORT_SCR_ERR = 0x%lx\n", readl(port_mmio + PORT_SCR_ERR));733 printf(" PORT_TFDATA = 0x%lx\n", readl(port_mmio + PORT_TFDATA));734 printf("interrupt status:\n");735 printf(" PORT_IRQ_STAT = 0x%lx\n", readl(port_mmio + PORT_IRQ_STAT));736 printf(" PORT_IRQ_MASK = 0x%lx\n", readl(port_mmio + PORT_IRQ_MASK));737 printf(" HOST_IRQ_STAT = 0x%lx\n", readl(ai->mmio + HOST_IRQ_STAT));664 aprintf(" PORT_CMD = 0x%lx\n", readl(port_mmio + PORT_CMD)); 665 aprintf("ahci_reset_port: command engine status:\n"); 666 aprintf(" PORT_SCR_ACT = 0x%lx\n", readl(port_mmio + PORT_SCR_ACT)); 667 aprintf(" PORT_CMD_ISSUE = 0x%lx\n", readl(port_mmio + PORT_CMD_ISSUE)); 668 aprintf("link/device status:\n"); 669 aprintf(" PORT_SCR_STAT = 0x%lx\n", readl(port_mmio + PORT_SCR_STAT)); 670 aprintf(" PORT_SCR_CTL = 0x%lx\n", readl(port_mmio + PORT_SCR_CTL)); 671 aprintf(" PORT_SCR_ERR = 0x%lx\n", readl(port_mmio + PORT_SCR_ERR)); 672 aprintf(" PORT_TFDATA = 0x%lx\n", readl(port_mmio + PORT_TFDATA)); 673 aprintf("interrupt status:\n"); 674 aprintf(" PORT_IRQ_STAT = 0x%lx\n", readl(port_mmio + PORT_IRQ_STAT)); 675 aprintf(" PORT_IRQ_MASK = 0x%lx\n", readl(port_mmio + PORT_IRQ_MASK)); 676 aprintf(" HOST_IRQ_STAT = 0x%lx\n", readl(ai->mmio + HOST_IRQ_STAT)); 738 677 } 739 678 … … 1565 1504 */ 1566 1505 if (irq_stat & PORT_IRQ_UNK_FIS) { 1506 #ifdef DEBUG 1567 1507 u32 _far *unk = (u32 _far *) (port_dma_base(ai, p)->rx_fis + RX_FIS_UNK); 1568 dprintf("warning: unknown FIS %08lx %08lx %08lx %08lx\n", 1569 unk[0], unk[1], unk[2], unk[3]);1508 dprintf("warning: unknown FIS %08lx %08lx %08lx %08lx\n", unk[0], unk[1], unk[2], unk[3]); 1509 #endif 1570 1510 reset_port = 1; 1571 1511 } … … 1688 1628 void ahci_execute_ata(IORBH _far *iorb) 1689 1629 { 1630 #ifdef DEBUG 1690 1631 int a = iorb_unit_adapter(iorb); 1691 1632 int p = iorb_unit_port(iorb); 1692 1633 int d = iorb_unit_device(iorb); 1634 #endif 1693 1635 1694 1636 dphex(((IORB_ADAPTER_PASSTHRU _far *) iorb)->pControllerCmd,
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