Changeset 157 for trunk/src/os2ahci/ahci.c

Timestamp:

May 8, 2013, 5:10:33 PM (12 years ago)

Author:

David Azarewicz

Message:

Fixed up timer functions

File:

• trunk/src/os2ahci/ahci.c (modified) (21 diffs)

trunk/src/os2ahci/ahci.c

@@ -331 +331 @@
 
         /* spec says "leave reset bit on for at least 1ms"; make it 2ms */
-        mdelay(2);
+        udelay(2000);
 
         writel(port_mmio + PORT_SCR_CTL, tmp);
@@ -341 +341 @@
      * least hard disks complete the reset within a few milliseonds)
      */
-    mdelay(20);
+    msleep(20);
   }
 
@@ -448 +448 @@
       return(0);
     }
-    mdelay(10);
+    msleep(10);
   }
 
@@ -459 +459 @@
 {
     u32 tmp;
-    int timeout = 1000;
+    TIMER Timer;
 
     dprintf("controller reset starting on adapter %d\n", ad_no(ai));
@@ -480 +480 @@
      * the hardware should be considered fried.
      */
-    while (((tmp = readl(ai->mmio + HOST_CTL)) & HOST_RESET) == HOST_RESET) {
-        mdelay(10);
-        timeout -= 10;
-        if (timeout <= 0) {
-          dprintf("controller reset failed (0x%lx)\n", tmp);
-          return(-1);
-        }
+    timer_init(&Timer, 1000);
+    while (((tmp = readl(ai->mmio + HOST_CTL)) & HOST_RESET) != 0) {
+      if (timer_check_and_block(&Timer)) {
+        dprintf("controller reset failed (0x%lx)\n", tmp);
+        return(-1);
+      }
     }
 
@@ -497 +496 @@
     ahci_restore_initial_config(ai);
 
-        if (ai->pci->vendor == PCI_VENDOR_ID_INTEL) {
-                u32 tmp16 = 0;
-
-        ddprintf("ahci_reset_controller: intel detected\n");
-                /* configure PCS */
-                pci_read_conf(ai->bus, ai->dev_func, 0x92, sizeof(u16), &tmp16);
-                if ((tmp16 & ai->port_map) != ai->port_map) {
-            ddprintf("ahci_reset_controller: updating PCS %x/%x\n", (u16)tmp16, ai->port_map);
-                        tmp16 |= ai->port_map;
-                        pci_write_conf(ai->bus, ai->dev_func, 0x92, sizeof(u16), tmp16);
-                }
-        }
+    if (ai->pci->vendor == PCI_VENDOR_ID_INTEL) {
+      u32 tmp16 = 0;
+
+      ddprintf("ahci_reset_controller: intel detected\n");
+      /* configure PCS */
+      pci_read_conf(ai->bus, ai->dev_func, 0x92, sizeof(u16), &tmp16);
+      if ((tmp16 & ai->port_map) != ai->port_map) {
+        ddprintf("ahci_reset_controller: updating PCS %x/%x\n", (u16)tmp16, ai->port_map);
+        tmp16 |= ai->port_map;
+        pci_write_conf(ai->bus, ai->dev_func, 0x92, sizeof(u16), tmp16);
+      }
+    }
 
     return 0;
@@ -538 +537 @@
   int p;
   int i;
+  TIMER Timer;
 
   if ((id_buf = malloc(ATA_ID_WORDS * sizeof(u16))) == NULL) {
@@ -561 +561 @@
       ddprintf("ahci_scan_ports: Wait till not busy on port %d\n", p);
       /* wait until all active commands have completed on this port */
+      timer_init(&Timer, 250);
       while (ahci_port_busy(ai, p)) {
-        msleep(250);
+        if (timer_check_and_block(&Timer)) break;
       }
 
@@ -718 +719 @@
   u8 _far *port_mmio = port_base(ai, p);
   u32 tmp;
-  int timeout;
+  TIMER Timer;
 
   dprintf("ahci_reset_port: resetting port %d.%d\n", ad_no(ai), p);
@@ -762 +763 @@
 
   /* spec says "leave reset bit on for at least 1ms"; make it 2ms */
-  mdelay(2);
+  udelay(2000);
 
   writel(port_mmio + PORT_SCR_CTL, tmp);
@@ -768 +769 @@
 
   /* wait for communication to be re-established after port reset */
-  timeout = 5000;
+  dprintf("Wait for communication...\n");
+  timer_init(&Timer, 500);
   while (((tmp = readl(port_mmio + PORT_SCR_STAT)) & 3) != 3) {
-    mdelay(10);
-    timeout -= 10;
-    if (timeout <= 0) {
-      dprintf("no device present after resetting port #%d "
-              "(PORT_SCR_STAT = 0x%lx)\n", p, tmp);
+    if (timer_check_and_block(&Timer)) {
+      dprintf("no device present after resetting port #%d (PORT_SCR_STAT = 0x%lx)\n", p, tmp);
       return(-1);
     }
@@ -788 +787 @@
 
   /* wait for device to be ready ((PxTFD & (BSY | DRQ | ERR)) == 0) */
-  timeout = 5000;
+  timer_init(&Timer, 1000);
   while (((tmp = readl(port_mmio + PORT_TFDATA)) & 0x89) != 0) {
-    mdelay(10);
-    timeout -= 10;
-    if (timeout <= 0) {
-      dprintf("device not ready on port #%d "
-              "(PORT_TFDATA = 0x%lx)\n", p, tmp);
+    if (timer_check_and_block(&Timer)) {
+      dprintf("device not ready on port #%d (PORT_TFDATA = 0x%lx)\n", p, tmp);
       ahci_stop_port(ai, p);
       return(-1);
     }
   }
-  ddprintf("ahci_reset_port: PORT_TFDATA   = 0x%lx\n", readl(port_mmio + PORT_TFDATA));
+  ddprintf("ahci_reset_port: PORT_TFDATA = 0x%lx\n", readl(port_mmio + PORT_TFDATA));
 
   return(0);
@@ -949 +945 @@
 {
   u8 _far *port_mmio = port_base(ai, p);
-  int timeout = 1000;
+  TIMER Timer;
   u32 tmp;
+  int status;
 
   /* disable FIS reception */
@@ -958 +955 @@
 
   /* wait for completion, spec says 500ms, give it 1000ms */
-  while (timeout > 0 && (readl(port_mmio + PORT_CMD) & PORT_CMD_FIS_ON)) {
-    mdelay(10);
-    timeout -= 10;
-  }
-
-  return((timeout <= 0) ? -1 : 0);
+  status = 0;
+  timer_init(&Timer, 1000);
+  while (readl(port_mmio + PORT_CMD) & PORT_CMD_FIS_ON) {
+    status = timer_check_and_block(&Timer);
+    if (status) break;
+  }
+
+  return(status ? -1 : 0);
 }
 
@@ -976 +975 @@
 {
   u8 _far *port_mmio = port_base(ai, p);
-  int timeout = 500;
+  TIMER Timer;
+  int status;
   u32 tmp;
 
@@ -991 +991 @@
 
   /* wait for engine to stop. This could be as long as 500 msec */
-  while (timeout > 0 && (readl(port_mmio + PORT_CMD) & PORT_CMD_LIST_ON)) {
-    mdelay(10);
-    timeout -= 10;
-  }
-
-  return((timeout <= 0) ? -1 : 0);
+  status = 0;
+  timer_init(&Timer, 500);
+  while (readl(port_mmio + PORT_CMD) & PORT_CMD_LIST_ON) {
+    status = timer_check_and_block(&Timer);
+    if (status) break;
+  }
+
+  return(status ? -1 : 0);
 }
 
@@ -1162 +1164 @@
   int p = iorb_unit_port(iorb);
   u8 _far *port_mmio = port_base(ai, p);
+  TIMER Timer;
+  int rc;
 
   /* enable AHCI mode */
@@ -1204 +1208 @@
     ddprintf("executing polled cmd on slot 0...");
     writel(port_mmio + PORT_CMD_ISSUE, 1);
-    timeout /= 10;
-    while (timeout > 0 && (readl(port_mmio + PORT_CMD_ISSUE) & 1)) {
-      mdelay(10);
-      timeout--;
-    }
-    ddprintf(" done (time left = %ld)\n", timeout * 10);
-
-    if (timeout == 0) {
+    timer_init(&Timer, timeout);
+    while (readl(port_mmio + PORT_CMD_ISSUE) & 1) {
+      rc = timer_check_and_block(&Timer);
+      if (rc) break;
+    }
+
+    if (rc) {
       dprintf("timeout for IORB %Fp\n", iorb);
       iorb_seterr(iorb, IOERR_ADAPTER_TIMEOUT);
-
     } else if (readl(port_mmio + PORT_SCR_ERR) != 0 ||
                readl(port_mmio + PORT_TFDATA) & 0x89) {
@@ -1220 +1222 @@
       iorb_seterr(iorb, IOERR_DEVICE_NONSPECIFIC);
       ahci_reset_port(ai, iorb_unit_port(iorb), 0);
-
     } else {
       /* successfully executed command */
@@ -1259 +1260 @@
   u32 tmp;
   int rc;
+  TIMER Timer;
 
   /* verify that command slot 0 is idle */
@@ -1277 +1279 @@
 
   /* wait until command has completed */
-  while (timeout > 0 && (readl(port_mmio + PORT_CMD_ISSUE) & 1)) {
-    mdelay(10);
-    timeout -= 10;
-  }
-  ddprintf(" done (time left = %d)\n", timeout);
+  timer_init(&Timer, timeout);
+  rc = 0;
+  while (readl(port_mmio + PORT_CMD_ISSUE) & 1) {
+    rc = timer_check_and_block(&Timer);
+    if (rc) break;
+  }
 
   /* check error condition */
   if ((tmp = readl(port_mmio + PORT_SCR_ERR)) != 0) {
     dprintf("SERR = 0x%08lx\n", tmp);
-    timeout = 0;
+    rc = 1;
   }
   if (((tmp = readl(port_mmio + PORT_TFDATA)) & 0x89) != 0) {
     dprintf("TFDATA = 0x%08lx\n", tmp);
-    timeout = 0;
-  }
-
-  if (timeout <= 0) {
+    rc = 1;
+  }
+
+  if (rc) {
     ahci_reset_port(ai, p, 0);
     return(-1);