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source: trunk/src/os2ahci/os2ahci.h@ 160

Last change on this file since 160 was 160, checked in by David Azarewicz, 12 years ago
fixed trap dump kernel exit, some work on suspend/resume routines
File size: 29.6 KB

Line
1	/******************************************************************************
2	* os2ahci.h - main header file for os2ahci driver
3	*
4	* Copyright (c) 2011 thi.guten Software Development
5	* Copyright (c) 2011 Mensys B.V.
6	*
7	* Authors: Christian Mueller, Markus Thielen
8	*
9	* Parts copied from/inspired by the Linux AHCI driver;
10	* those parts are (c) Linux AHCI/ATA maintainers
11	*
12	* This program is free software; you can redistribute it and/or modify
13	* it under the terms of the GNU General Public License as published by
14	* the Free Software Foundation; either version 2 of the License, or
15	* (at your option) any later version.
16	*
17	* This program is distributed in the hope that it will be useful,
18	* but WITHOUT ANY WARRANTY; without even the implied warranty of
19	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20	* GNU General Public License for more details.
21	*
22	* You should have received a copy of the GNU General Public License
23	* along with this program; if not, write to the Free Software
24	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
25	*/
26
27	/* ----------------------------- include files ----------------------------- */
28
29	/* IMPORTANT NOTE: The DDK headers require tight structure packing and this
30	* is controlled via compiler parameters. Thus, all stuctures in os2ahci.add
31	* are expected to be byte-aligned without the need of explicit pragma pack()
32	* directives. Where possible, the structures are laid out such that words
33	* and dwords are aligned at least on 2-byte boundaries.
34	*/
35
36	#define DEBUG
37	#define INCL_NOPMAPI
38	#define INCL_DOSINFOSEG
39	#define INCL_NO_SCB
40	#define INCL_DOSERRORS
41	#include <os2.h>
42	#include <dos.h>
43	#include <bseerr.h>
44	#include <dskinit.h>
45	#include <scb.h>
46
47	#include <devhdr.h>
48	#include <iorb.h>
49	#include <strat2.h>
50	#include <reqpkt.h>
51
52	/* NOTE: (Rousseau)
53	* The regular dhcalls.h from $(DDK)\base\h also works.
54	* The devhelp.h from $(DDK)\base\h produces inline assembler errors.
55	* The modified devhelp.h from ..\include works OK and is used because it
56	* generates a slightly smaller driver image.
57	*/
58	#ifdef __WATCOMC__
59	/* include WATCOM specific DEVHELP stubs */
60	#include <devhelp.h>
61	#else
62	#include <dhcalls.h>
63	#endif
64
65	#include <addcalls.h>
66	#include <rmcalls.h>
67	#include <devclass.h>
68	#include <devcmd.h>
69	#include <rmbase.h>
70
71	#include "ahci.h"
72	#include "ahci-idc.h"
73
74	/* -------------------------- macros and constants ------------------------- */
75
76	#define MAX_AD 8 /* maximum number of adapters */
77
78	/* Timer pool size. In theory, we need one timer per outstanding command plus
79	* a few miscellaneous timers but it's unlikely we'll ever have outstanding
80	* commands on all devices on all ports on all apapters -- this would be
81	* 8 * 32 * 32 = 8192 outstanding commands on a maximum of 8 * 32 * 15 = 3840
82	* devices and that's a bit of an exaggeration. It should be more than enough
83	* to have 128 timers.
84	*/
85	#define TIMER_COUNT 128
86	#define TIMER_POOL_SIZE (sizeof(ADD_TIMER_POOL) + \
87	TIMER_COUNT * sizeof(ADD_TIMER_DATA))
88
89	/* default command timeout (can be overwritten in the IORB) */
90	#define DEFAULT_TIMEOUT 30000
91
92	/* Maximum number of retries for commands in the restart/reset context hooks.
93	*
94	* Please note that the corresponding variable in the ADD workspace is a bit
95	* field, thus increasing this value means increasing the size of the bit
96	* field. At the time of writing this comment the 'retries' variable was 2
97	* bits wide (i.e. a maximum number of 3 retries) and there was exactly one
98	* bit left before the ADD workspace structure would become too large...
99	*/
100	#define MAX_RETRIES 3
101
102	/* max/min macros */
103	#define max(a, b) (a) > (b) ? (a) : (b)
104	#define min(a, b) (a) < (b) ? (a) : (b)
105
106	/* debug output macros */
107	#ifdef DEBUG
108	#define dprintf if (debug > 0) printf
109	#define dphex if (debug > 0) phex
110	#define ddprintf if (debug > 1) printf
111	#define ddphex if (debug > 1) phex
112	#define dddprintf if (debug > 2) printf
113	#define dddphex if (debug > 2) phex
114	#define ntprintf printf_nts
115	#define aprintf printf
116	#else
117	#define dprintf(a,...)
118	#define dphex(a,b,c,...)
119	#define ddprintf(a,...)
120	#define ddphex(a,b,c,...)
121	#define dddprintf(a,...)
122	#define dddphex(a,b,c,...)
123	#define ntprintf(a,...)
124	#define aprintf(a,...)
125	#endif
126
127	/* verbosity console print macros
128	* (we use 'i' in ciprintf here to avoid name clash
129	* with vprintf-like funcs)
130	*/
131	#define ciprintf if (verbosity > 0) cprintf
132	#define ciiprintf if (verbosity > 1) cprintf
133
134	/* TRACE macros (for our internal ring buffer trace) */
135	#define AHCI_TRACE_BUF_SIZE 0x8000U /* 32k */
136	#define AHCI_INFO_BUF_SIZE 0x1000U /* 4k */
137	#define TRACE_ACTIVE (debug > 0 && com_base == 0)
138
139	/* adapter number from AD_INFO pointer; mainly for dprintf() purposes */
140	#define ad_no(ai) (((u16) ai - (u16) ad_infos) / sizeof(*ai))
141
142	/* Convert far function address into NPFN (the DDK needs this all over the
143	* place and just casting to NPFN will produce a "segment lost in conversion"
144	* warning. Since casting to a u32 is a bit nasty for function pointers and
145	* might have to be revised for different compilers, we'll use a central
146	* macro for this crap.
147	*/
148	#define mk_NPFN(func) (NPFN) (u32) (func)
149
150	/* stdarg.h macros with explicit far pointers
151	*
152	* NOTE: The compiler pushes fixed arguments with 16 bits minimum, thus
153	* the last fixed argument (i.e. the one passed to va_start) must
154	* have at least 16 bits. Otherwise, the address calculation in
155	* va_start() will fail.
156	*/
157	typedef char _far *va_list;
158	#define va_start(va, last) va = (va_list) (&last + 1)
159	#define va_arg(va, type) ((type _far *) (va += sizeof(type)))[-1]
160	#define va_end(va) va = 0
161
162	/* ctype macros */
163	#define isupper(ch) ((ch) >= 'A' && (ch) <= 'Z')
164	#define tolower(ch) (isupper(ch) ? (ch) + ('a' - 'A') : (ch))
165
166	/* stddef macros */
167	#define offsetof(s, e) ((u16) &((s *) 0)->e)
168
169	/* SMP spinlock compatibility macros for older DDKs using CLI/STI */
170	#ifndef OS2AHCI_SMP
171	#define DevHelp_CreateSpinLock(p_sph) *(p_sph) = 0
172	#define DevHelp_FreeSpinLock(sph) 0
173
174	#define DevHelp_AcquireSpinLock(sph) if ((sph) != 0) \
175	panic("recursive spinlock"); \
176	(sph) = disable()
177
178	#define DevHelp_ReleaseSpinLock(sph) if (sph) { \
179	(sph) = 0; \
180	enable(); \
181	}
182	#endif
183
184	/* shortcut macros */
185	#define spin_lock(sl) DevHelp_AcquireSpinLock(sl)
186	#define spin_unlock(sl) DevHelp_ReleaseSpinLock(sl)
187
188	/* Get AHCI port MMIO base from AD_INFO and port number. For the time being,
189	* MMIO addresses are assumed to be valid 16:16 pointers which implies
190	* that one GDT selector is allocated per adapter.
191	*/
192	#define port_base(ai, p) ((u8 _far ) (ai)->mmio + 0x100 + (p) 0x80)
193
194	/* Get address of port-specific DMA scratch buffer. The total size of all DMA
195	* buffers required for 32 ports exceeds 65536 bytes, thus we need multiple
196	* GDT selectors to access all port DMA scratch buffers and some logic to map
197	* a port number to the corresponding DMA scratch buffer address.
198	*/
199	#define PORT_DMA_BUFS_PER_SEG ((size_t) (65536UL / AHCI_PORT_PRIV_DMA_SZ))
200	#define PORT_DMA_BUF_SEGS ((AHCI_MAX_PORTS + PORT_DMA_BUFS_PER_SEG - 1) \
201	/ PORT_DMA_BUFS_PER_SEG)
202	#define PORT_DMA_SEG_SIZE ((u32) PORT_DMA_BUFS_PER_SEG * \
203	(u32) AHCI_PORT_PRIV_DMA_SZ)
204
205	#define port_dma_base(ai, p) \
206	((AHCI_PORT_DMA _far *) ((ai)->dma_buf[(p) / PORT_DMA_BUFS_PER_SEG] + \
207	((p) % PORT_DMA_BUFS_PER_SEG) * AHCI_PORT_PRIV_DMA_SZ))
208
209	#define port_dma_base_phys(ai, p) \
210	((ai)->dma_buf_phys + (u32) (p) * AHCI_PORT_PRIV_DMA_SZ)
211
212	/* Convert an SATA adapter/port/device address into a 16-bit IORB unit handle
213	* (and the other way round). The mapping looks like this:
214	*
215	* mapping comment
216	* -----------------------------------------------------------------------
217	* 4 bits for the adapter current max is 8 adapters
218	* 4 bits for the port AHCI spec defines up to 32 ports
219	* 4 bits for the device SATA spec defines up to 15 devices behind PMP
220	*/
221	#define iorb_unit(a, p, d) ((((u16) (a) & 0x0fU) << 8) \| \
222	(((u16) (p) & 0x0fU) << 4) \| \
223	(((u16) (d) & 0x0fU)))
224	#define iorb_unit_adapter(iorb) (((u16) (iorb)->UnitHandle >> 8) & 0x07U)
225	#define iorb_unit_port(iorb) (((u16) (iorb)->UnitHandle >> 4) & 0x0fU)
226	#define iorb_unit_device(iorb) ((u16) (iorb)->UnitHandle & 0x0fU)
227
228	/*******************************************************************************
229	* Convenience macros for IORB processing functions
230	*/
231	/* is this IORB on driver or port level? */
232	#define iorb_driver_level(iorb) ((iorb)->CommandCode == IOCC_CONFIGURATION)
233
234	/* is this IORB to be inserted at the beginnig of the IORB queue? */
235	#define iorb_priority(iorb) ((iorb)->CommandCode == IOCC_DEVICE_CONTROL && \
236	(iorb)->CommandModifier == IOCM_ABORT))
237
238	/* access IORB ADD workspace */
239	#define add_workspace(iorb) ((ADD_WORKSPACE _far *) &(iorb)->ADDWorkSpace)
240
241
242
243	/******************************************************************************
244	* PCI generic IDs and macros
245	*/
246	#define PCI_ANY_ID 0xffffU
247	#define PCI_VDEVICE(vendor, device) PCI_VENDOR_ID_##vendor, (device), \
248	PCI_ANY_ID, PCI_ANY_ID, 0, 0
249
250	/******************************************************************************
251	* PCI vendor IDs for AHCI adapters known to this driver (copied from Linux
252	* pci_ids.h)
253	*/
254	#define PCI_VENDOR_ID_AL 0x10b9
255	#define PCI_VENDOR_ID_AMD 0x1022
256	#define PCI_VENDOR_ID_AT 0x1259
257	#define PCI_VENDOR_ID_ATI 0x1002
258	#define PCI_VENDOR_ID_ATT 0x11c1
259	#define PCI_VENDOR_ID_CMD 0x1095
260	#define PCI_VENDOR_ID_CT 0x102c
261	#define PCI_VENDOR_ID_INTEL 0x8086
262	#define PCI_VENDOR_ID_INITIO 0x1101
263	#define PCI_VENDOR_ID_JMICRON 0x197B
264	#define PCI_VENDOR_ID_MARVELL 0x11ab
265	#define PCI_VENDOR_ID_NVIDIA 0x10de
266	#define PCI_VENDOR_ID_PROMISE 0x105a
267	#define PCI_VENDOR_ID_SI 0x1039
268	#define PCI_VENDOR_ID_VIA 0x1106
269
270	/******************************************************************************
271	* PCI class IDs we're interested in (copied from Linux pci_ids.h)
272	*/
273	#define PCI_BASE_CLASS_STORAGE 0x01
274	#define PCI_CLASS_STORAGE_SCSI 0x0100
275	#define PCI_CLASS_STORAGE_IDE 0x0101
276	#define PCI_CLASS_STORAGE_FLOPPY 0x0102
277	#define PCI_CLASS_STORAGE_IPI 0x0103
278	#define PCI_CLASS_STORAGE_RAID 0x0104
279	#define PCI_CLASS_STORAGE_SATA 0x0106
280	#define PCI_CLASS_STORAGE_SATA_AHCI 0x010601
281	#define PCI_CLASS_STORAGE_SAS 0x0107
282	#define PCI_CLASS_STORAGE_OTHER 0x0180
283
284	/******************************************************************************
285	* ANSI color code constants
286	*/
287	#define ANSI_CLR_BRIGHT "\x1b[1m"
288	#define ANSI_CLR_RED "\x1b[31m"
289	#define ANSI_CLR_GREEN "\x1b[32m"
290	#define ANSI_CLR_BLUE "\x1b[34m"
291	#define ANSI_CLR_CYAN "\x1b[36m"
292	#define ANSI_CLR_WHITE "\x1b[37m"
293	#define ANSI_RESET "\x1b[0m"
294
295
296	/* ------------------------ typedefs and structures ------------------------ */
297
298	typedef unsigned int size_t;
299
300	typedef struct {
301	u32 Start;
302	u32 End;
303	} TIMER;
304
305	/* PCI device information structure; this is used both for scanning and for
306	* identification purposes in 'AD_INFO'; based on the Linux pci_device_id
307	* structure but hard-wired to use board_* constants for 'driver_data'
308	*/
309	typedef struct {
310	u16 vendor; /* PCI device vendor/manufacturer */
311	u16 device; /* PCI device ID inside vendor scope */
312	u16 subvendor; /* subsystem vendor (unused so far) */
313	u16 subdevice; /* subsystem device (unused so far) */
314	u32 class; /* PCI device class */
315	u32 class_mask; /* bits to match when scanning for 'class' */
316	u32 board; /* AHCI controller board type (board_* constants) */
317	char chipname; / human readable chip ID string */
318	} PCI_ID;
319
320	/* IORB queue; since IORB queues are updated at interrupt time, the
321	* corresponding pointers (not the data they point to) need to be volatile.
322	*/
323	typedef struct {
324	IORBH _far volatile root; / root of request list */
325	IORBH _far volatile tail; / tail of request list */
326	} IORB_QUEUE;
327
328	/* port information structure */
329	typedef struct {
330	IORB_QUEUE iorb_queue; /* IORB queue for this port */
331	unsigned dev_max : 4; /* maximum device number on this port (0-15) */
332	unsigned cmd_slot : 5; /* current command slot index (using round-
333	* robin indexes to prevent starvation) */
334
335	volatile u32 ncq_cmds; /* bitmap for NCQ commands issued */
336	volatile u32 reg_cmds; /* bitmap for regular commands issued */
337
338	struct {
339	unsigned allocated : 1; /* if != 0, device is allocated */
340	unsigned present : 1; /* if != 0, device is present */
341	unsigned lba48 : 1; /* if != 0, device supports 48-bit LBA */
342	unsigned atapi : 1; /* if != 0, this is an ATAPI device */
343	unsigned atapi_16 : 1; /* if != 0, device suports 16-byte cmds */
344	unsigned removable : 1; /* if != 0, device has removable media */
345	unsigned dev_type : 5; /* device type (UIB_TYPE_* in iorb.h) */
346	unsigned ncq_max : 5; /* maximum tag number for queued commands */
347	UNITINFO _far unit_info; / pointer to modified unit info */
348	} devs[15];
349	} P_INFO;
350
351	/* adapter information structure */
352	typedef struct {
353	PCI_ID pci; / pointer to corresponding PCI ID */
354
355	unsigned port_max : 5; /* maximum port number (0-31) */
356	unsigned cmd_max : 5; /* maximum cmd slot number (0-31) */
357	unsigned port_scan_done : 1; /* if != 0, port scan already done */
358	unsigned busy : 1; /* if != 0, adapter is busy */
359
360	u32 port_map; /* bitmap of active ports */
361
362	/* initial adapter configuration from BIOS */
363	u32 bios_config[HOST_CAP2 / sizeof(u32) + 1];
364
365	u32 cap; /* working copy of CAP register */
366	u32 cap2; /* working copy of CAP2 register */
367	u32 flags; /* adapter flags */
368
369	HRESOURCE rm_adh; /* resource handle for adapter */
370	HRESOURCE rm_bars[6]; /* resource handle for MMIO and I/O BARs */
371	HRESOURCE rm_irq; /* resource handle for IRQ */
372
373	u8 bus; /* PCI bus number */
374	u8 dev_func; /* PCI device and function number */
375	u16 irq; /* interrupt number */
376
377	u32 mmio_phys; /* physical address of MMIO region */
378	u32 mmio_size; /* size of MMIO region */
379	u8 _far mmio; / pointer to this adapter's MMIO region */
380
381	u32 dma_buf_phys; /* physical address of DMA scratch buffer */
382	u8 _far dma_buf[PORT_DMA_BUF_SEGS]; / DMA scatch buffer */
383
384	P_INFO ports[AHCI_MAX_PORTS]; /* SATA ports on this adapter */
385	} AD_INFO;
386
387	/* ADD workspace in IORB (must not exceed 16 bytes) */
388	typedef struct {
389	void (ppfunc)(IORBH _far iorb); /* post-processing function */
390	void buf; / response buffer (e.g. for identify cmds) */
391	ULONG timer; /* timer for timeout procesing */
392	USHORT blocks; /* number of blocks to be transferred */
393	unsigned processing : 1; /* IORB is being processd */
394	unsigned idempotent : 1; /* IORB is idempotent (can be retried) */
395	unsigned queued_hw : 1; /* IORB has been queued to hardware */
396	unsigned no_ncq : 1; /* must not use native command queuing */
397	unsigned is_ncq : 1; /* should use native command queueing */
398	unsigned complete : 1; /* IORB has completed processing */
399	unsigned unaligned : 1; /* unaligned S/G; need to use transfer buffer */
400	unsigned retries : 2; /* number of retries for this command */
401	unsigned cmd_slot : 5; /* AHCI command slot for this IORB */
402	} ADD_WORKSPACE;
403
404	/* sg_memcpy() direction */
405	typedef enum {
406	SG_TO_BUF, /* copy from S/G list to buffer */
407	BUF_TO_SG /* copy from buffer to S/G list */
408	} SG_MEMCPY_DIRECTION;
409
410	/* Define the size of a disk name. Disk Names are user defined names given to physical disk drives in the system. */
411	#define DLA_TABLE_SIGNATURE1 0x424D5202L
412	#define DLA_TABLE_SIGNATURE2 0x44464D50L
413	#define DISK_NAME_SIZE 20
414
415	typedef struct _DLA_Table_Sector { /* DTS */
416	ULONG DLA_Signature1; /* The magic signature (part 1) of a Drive Letter Assignment Table. */
417	ULONG DLA_Signature2; /* The magic signature (part 2) of a Drive Letter Assignment Table. */
418	ULONG DLA_CRC; /* The 32 bit CRC for this sector. Calculated assuming that this field and all unused space in the sector is 0. */
419	ULONG Disk_Serial_Number; /* The serial number assigned to this disk. */
420	ULONG Boot_Disk_Serial_Number;/* The serial number of the disk used to boot the system. This is for conflict resolution when multiple volumes
421	want the same drive letter. Since LVM.EXE will not let this situation happen, the only way to get this situation
422	is for the disk to have been altered by something other than LVM.EXE, or if a disk drive has been moved from one
423	machine to another. If the drive has been moved, then it should have a different Boot_Disk_Serial_Number. Thus,
424	we can tell which disk drive is the "foreign" drive and therefore reject its claim for the drive letter in question.
425	If we find that all of the claimaints have the same Boot_Disk_Serial_Number, then we must assign drive letters on
426	a first come, first serve basis. */
427	ULONG Install_Flags; /* Used by the Install program. */
428	ULONG Cylinders;
429	ULONG Heads_Per_Cylinder;
430	ULONG Sectors_Per_Track;
431	char Disk_Name[DISK_NAME_SIZE]; /* The name assigned to the disk containing this sector. */
432	UCHAR Reboot; /* For use by Install. Used to keep track of reboots initiated by install. */
433	BYTE Reserved[3]; /* Alignment. */
434	/* These are the four entries which correspond to the entries in the partition table. */
435	} DLA_Table_Sector, *PDLA_Table_Sector;
436
437	/* -------------------------- function prototypes -------------------------- */
438
439	/* init.asm */
440	extern u32 _cdecl readl (void _far *addr);
441	extern u32 _cdecl writel (void _far *addr, u32 val);
442	extern void _far * _cdecl memcpy (void _far v_dst, void _far v_src, int len);
443	extern void _far * _cdecl memset (void _far *p, int ch, size_t len);
444	extern void _cdecl _far restart_hook (void);
445	extern void _cdecl _far reset_hook (void);
446	extern void _cdecl _far engine_hook (void);
447	extern void _cdecl _far asm_krnl_exit (void);
448	extern void _cdecl udelay (u16 microseconds);
449
450	/* os2ahci.c */
451	extern USHORT init_drv (RPINITIN _far *req);
452	extern USHORT gen_ioctl (RP_GENIOCTL _far *ioctl);
453	extern USHORT char_dev_input (RP_RWV _far *rwrb);
454	extern USHORT exit_drv (int func);
455	extern USHORT sr_drv (int func);
456	extern void _cdecl _far _loadds add_entry (IORBH _far *iorb);
457	extern void trigger_engine (void);
458	extern int trigger_engine_1 (void);
459	extern void send_iorb (IORBH _far *iorb);
460	extern void iocc_configuration (IORBH _far *iorb);
461	extern void iocc_device_control (IORBH _far *iorb);
462	extern void iocc_unit_control (IORBH _far *iorb);
463	extern void iocm_device_table (IORBH _far *iorb);
464	extern void iocc_geometry (IORBH _far *iorb);
465	extern void iocc_execute_io (IORBH _far *iorb);
466	extern void iocc_unit_status (IORBH _far *iorb);
467	extern void iocc_adapter_passthru (IORBH _far *iorb);
468	extern void iorb_queue_add (IORB_QUEUE _far queue, IORBH _far iorb);
469	extern int iorb_queue_del (IORB_QUEUE _far queue, IORBH _far iorb);
470	extern void iorb_seterr (IORBH _far *iorb, USHORT error_code);
471	extern void iorb_done (IORBH _far *iorb);
472	extern void iorb_complete (IORBH _far *iorb);
473	extern void iorb_requeue (IORBH _far *iorb);
474	extern void aws_free (ADD_WORKSPACE _far *aws);
475	extern void lock_adapter (AD_INFO *ai);
476	extern void unlock_adapter (AD_INFO *ai);
477	extern void _cdecl _far timeout_callback (ULONG timer_handle, ULONG p1, ULONG p2);
478	extern void _cdecl _far reset_watchdog (ULONG timer_handle, ULONG p1, ULONG p2);
479
480	/* ahci.c */
481	extern int ahci_save_bios_config (AD_INFO *ai);
482	extern int ahci_restore_bios_config (AD_INFO *ai);
483	extern int ahci_restore_initial_config (AD_INFO *ai);
484	extern AHCI_PORT_CFG ahci_save_port_config (AD_INFO ai, int p);
485	extern void ahci_restore_port_config (AD_INFO *ai, int p,
486	AHCI_PORT_CFG *pc);
487	extern int ahci_enable_ahci (AD_INFO *ai);
488	extern int ahci_scan_ports (AD_INFO *ai);
489	extern int ahci_complete_init (AD_INFO *ai);
490	extern int ahci_reset_port (AD_INFO *ai, int p, int ei);
491	extern int ahci_start_port (AD_INFO *ai, int p, int ei);
492	extern void ahci_start_fis_rx (AD_INFO *ai, int p);
493	extern void ahci_start_engine (AD_INFO *ai, int p);
494	extern int ahci_stop_port (AD_INFO *ai, int p);
495	extern int ahci_stop_fis_rx (AD_INFO *ai, int p);
496	extern int ahci_stop_engine (AD_INFO *ai, int p);
497	extern int ahci_port_busy (AD_INFO *ai, int p);
498	extern void ahci_exec_iorb (IORBH _far *iorb, int ncq_capable,
499	int (func)(IORBH _far , int));
500	extern void ahci_exec_polled_iorb (IORBH _far *iorb,
501	int (func)(IORBH _far , int),
502	ULONG timeout);
503	extern int ahci_exec_polled_cmd (AD_INFO *ai, int p, int d,
504	int timeout, int cmd, ...);
505	extern int ahci_set_dev_idle (AD_INFO *ai, int p, int d, int idle);
506	extern int ahci_flush_cache (AD_INFO *ai, int p, int d);
507
508	extern int ahci_intr (u16 irq);
509	extern void ahci_port_intr (AD_INFO *ai, int p);
510	extern void ahci_error_intr (AD_INFO *ai, int p, u32 irq_stat);
511
512	extern void ahci_get_geometry (IORBH _far *iorb);
513	extern void ahci_unit_ready (IORBH _far *iorb);
514	extern void ahci_read (IORBH _far *iorb);
515	extern void ahci_verify (IORBH _far *iorb);
516	extern void ahci_write (IORBH _far *iorb);
517	extern void ahci_execute_cdb (IORBH _far *iorb);
518	extern void ahci_execute_ata (IORBH _far *iorb);
519
520	/* libc.c */
521	extern void init_libc (void);
522	extern void init_com (long BaudRate);
523	extern int vsprintf (char _far buf, const char fmt, va_list va);
524	extern int sprintf (char _far buf, const char fmt, ...);
525	extern void vfprintf (const char *fmt, va_list va);
526	extern void _cdecl printf (const char *fmt, ...);
527	extern void _cdecl printf_nts (const char *fmt, ...);
528	extern void cprintf (const char *fmt, ...);
529	extern void phex (const void _far p, int len, const char fmt, ...);
530	extern size_t strlen (const char _far *s);
531	extern char _far strcpy (char _far dst, const char _far *src);
532	extern int memcmp (void _far p1, void _far p2, size_t len);
533	extern void sg_memcpy (SCATGATENTRY _far *sg_list, USHORT sg_cnt,
534	ULONG sg_off, void _far *buf, USHORT len,
535	SG_MEMCPY_DIRECTION dir);
536	extern long strtol (const char _far *buf,
537	const char _far * _far *ep, int base);
538	extern void *malloc (size_t len);
539	extern void free (void *ptr);
540	extern ULONG virt_to_phys (void _far *ptr);
541	//NOT_USED extern void mdelay_cal (void);
542	//NOT_USED extern void mdelay (u32 millies);
543	extern void msleep (u32 millies);
544	extern void panic (char *msg);
545	extern int disable (void);
546	extern void enable (void);
547	extern void timer_init(TIMER far *pTimer, u32 Milliseconds);
548	extern int timer_check_and_block(TIMER far *pTimer);
549
550	/* trace.c */
551	extern void trace_init (u16);
552	extern void trace_exit (void);
553	extern void trace_write (u8 _far *s, int len);
554	extern u16 trace_read (u8 _far *buf, u16 cb_buf);
555	extern u16 trace_char_dev(RP_RWV _far *rwrb);
556	extern void build_user_info(void);
557
558	/* pci.c */
559	extern int add_pci_id (u16 vendor, u16 device);
560	extern void scan_pci_bus (void);
561	extern int pci_enable_int (UCHAR bus, UCHAR dev_func);
562	extern void pci_hack_virtualbox(void);
563	extern char *vendor_from_id (u16 vendor);
564	extern char *device_from_id (u16 device);
565	UCHAR pci_read_conf (UCHAR bus, UCHAR dev_func, UCHAR indx,
566	UCHAR size, ULONG _far *val);
567	UCHAR pci_write_conf (UCHAR bus, UCHAR dev_func, UCHAR indx, UCHAR size,
568	ULONG val);
569
570	/* ctxhook.c */
571	extern void _cdecl restart_ctxhook (ULONG parm);
572	extern void _cdecl reset_ctxhook (ULONG parm);
573	extern void _cdecl engine_ctxhook (ULONG parm);
574
575	/* apm.c */
576	extern void apm_init (void);
577	extern void suspend (void);
578	extern void resume (void);
579
580	/* ioctl.c */
581	extern USHORT ioctl_get_devlist (RP_GENIOCTL _far *ioctl);
582	extern USHORT ioctl_passthrough (RP_GENIOCTL _far *ioctl);
583	extern USHORT ioctl_gen_dsk (RP_GENIOCTL _far *ioctl);
584	extern USHORT ioctl_smart (RP_GENIOCTL _far *ioctl);
585
586
587	/* ---------------------------- global variables --------------------------- */
588
589	extern char _cdecl end_of_data; /* label at the end of all data segments */
590	extern void _cdecl _near end_of_code(); /* label at the end of all code segments */
591
592	extern int debug; /* if != 0, print debug messages to COM1 */
593	extern int thorough_scan; /* if != 0, perform thorough PCI scan */
594	extern int init_reset; /* if != 0, reset ports during init */
595	extern int force_write_cache; /* if != 0, force write cache */
596	extern int verbosity; /* if != 0, show some info during boot */
597	extern int use_lvm_info;
598	extern int wrap_trace_buffer;
599
600	extern HDRIVER rm_drvh; /* resource manager driver handle */
601	extern USHORT add_handle; /* adapter device driver handle */
602	extern UCHAR timer_pool[]; /* timer pool */
603	extern char drv_name[]; /* driver name as string ("OS2AHCI") */
604
605	extern PCI_ID pci_ids[]; /* SATA adapter PCI IDs */
606	extern ULONG drv_lock; /* driver-level spinlock */
607	extern ULONG com_lock; /* debug log spinlock */
608	extern IORB_QUEUE driver_queue; /* driver-level IORB queue */
609	extern AD_INFO ad_infos[]; /* adapter information list */
610	extern int ad_info_cnt; /* number of entries in ad_infos[] */
611	extern u16 ad_ignore; /* bitmap with adapters to be ignored */
612	extern int init_complete; /* if != 0, initialization has completed */
613	extern int suspended; /* indicates if the driver is suspended */
614
615	extern u16 com_base; /* debug COM port base address */
616
617	/* port restart context hook and input data */
618	extern ULONG restart_ctxhook_h;
619	extern volatile u32 ports_to_restart[MAX_AD];
620
621	/* port reset context hook and input data */
622	extern ULONG reset_ctxhook_h;
623	extern ULONG th_reset_watchdog;
624	extern volatile u32 ports_to_reset[MAX_AD];
625	extern IORB_QUEUE abort_queue;
626
627	/* trigger engine context hook and input data */
628	extern ULONG engine_ctxhook_h;
629
630	/* apapter/port-specific options saved when parsing the command line */
631	extern u8 emulate_scsi[MAX_AD][AHCI_MAX_PORTS];
632	extern u8 enable_ncq[MAX_AD][AHCI_MAX_PORTS];
633	extern u8 link_speed[MAX_AD][AHCI_MAX_PORTS];
634	extern u8 link_power[MAX_AD][AHCI_MAX_PORTS];
635	extern u8 track_size[MAX_AD][AHCI_MAX_PORTS];
636

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