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source: trunk/src/os2ahci/os2ahci.h@ 157

Last change on this file since 157 was 157, checked in by David Azarewicz, 12 years ago
Fixed up timer functions
File size: 29.3 KB

Line
1	/******************************************************************************
2	* os2ahci.h - main header file for os2ahci driver
3	*
4	* Copyright (c) 2011 thi.guten Software Development
5	* Copyright (c) 2011 Mensys B.V.
6	*
7	* Authors: Christian Mueller, Markus Thielen
8	*
9	* Parts copied from/inspired by the Linux AHCI driver;
10	* those parts are (c) Linux AHCI/ATA maintainers
11	*
12	* This program is free software; you can redistribute it and/or modify
13	* it under the terms of the GNU General Public License as published by
14	* the Free Software Foundation; either version 2 of the License, or
15	* (at your option) any later version.
16	*
17	* This program is distributed in the hope that it will be useful,
18	* but WITHOUT ANY WARRANTY; without even the implied warranty of
19	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20	* GNU General Public License for more details.
21	*
22	* You should have received a copy of the GNU General Public License
23	* along with this program; if not, write to the Free Software
24	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
25	*/
26
27	/* ----------------------------- include files ----------------------------- */
28
29	/* IMPORTANT NOTE: The DDK headers require tight structure packing and this
30	* is controlled via compiler parameters. Thus, all stuctures in os2ahci.add
31	* are expected to be byte-aligned without the need of explicit pragma pack()
32	* directives. Where possible, the structures are laid out such that words
33	* and dwords are aligned at least on 2-byte boundaries.
34	*/
35
36	#define INCL_NOPMAPI
37	#define INCL_DOSINFOSEG
38	#define INCL_NO_SCB
39	#define INCL_DOSERRORS
40	#include <os2.h>
41	#include <dos.h>
42	#include <bseerr.h>
43	#include <dskinit.h>
44	#include <scb.h>
45
46	#include <devhdr.h>
47	#include <iorb.h>
48	#include <strat2.h>
49	#include <reqpkt.h>
50
51	/* NOTE: (Rousseau)
52	* The regular dhcalls.h from $(DDK)\base\h also works.
53	* The devhelp.h from $(DDK)\base\h produces inline assembler errors.
54	* The modified devhelp.h from ..\include works OK and is used because it
55	* generates a slightly smaller driver image.
56	*/
57	#ifdef __WATCOMC__
58	/* include WATCOM specific DEVHELP stubs */
59	#include <devhelp.h>
60	#else
61	#include <dhcalls.h>
62	#endif
63
64	#include <addcalls.h>
65	#include <rmcalls.h>
66	#include <devclass.h>
67	#include <devcmd.h>
68	#include <rmbase.h>
69
70	#include "ahci.h"
71	#include "ahci-idc.h"
72
73	/* -------------------------- macros and constants ------------------------- */
74
75	#define MAX_AD 8 /* maximum number of adapters */
76
77	/* Timer pool size. In theory, we need one timer per outstanding command plus
78	* a few miscellaneous timers but it's unlikely we'll ever have outstanding
79	* commands on all devices on all ports on all apapters -- this would be
80	* 8 * 32 * 32 = 8192 outstanding commands on a maximum of 8 * 32 * 15 = 3840
81	* devices and that's a bit of an exaggeration. It should be more than enough
82	* to have 128 timers.
83	*/
84	#define TIMER_COUNT 128
85	#define TIMER_POOL_SIZE (sizeof(ADD_TIMER_POOL) + \
86	TIMER_COUNT * sizeof(ADD_TIMER_DATA))
87
88	/* default command timeout (can be overwritten in the IORB) */
89	#define DEFAULT_TIMEOUT 30000
90
91	/* Maximum number of retries for commands in the restart/reset context hooks.
92	*
93	* Please note that the corresponding variable in the ADD workspace is a bit
94	* field, thus increasing this value means increasing the size of the bit
95	* field. At the time of writing this comment the 'retries' variable was 2
96	* bits wide (i.e. a maximum number of 3 retries) and there was exactly one
97	* bit left before the ADD workspace structure would become too large...
98	*/
99	#define MAX_RETRIES 3
100
101	/* max/min macros */
102	#define max(a, b) (a) > (b) ? (a) : (b)
103	#define min(a, b) (a) < (b) ? (a) : (b)
104
105	/* debug output macros */
106	#define dprintf if (debug > 0) printf
107	#define dphex if (debug > 0) phex
108	#define ddprintf if (debug > 1) printf
109	#define ddphex if (debug > 1) phex
110	#define dddprintf if (debug > 2) printf
111	#define dddphex if (debug > 2) phex
112
113	/* verbosity console print macros
114	* (we use 'i' in ciprintf here to avoid name clash
115	* with vprintf-like funcs)
116	*/
117	#define ciprintf if (verbosity > 0) cprintf
118	#define ciiprintf if (verbosity > 1) cprintf
119
120	/* TRACE macros (for our internal ring buffer trace) */
121	#define AHCI_TRACE_BUF_SIZE 0x8000U /* 32k */
122	#define AHCI_INFO_BUF_SIZE 0x1000U /* 4k */
123	#define TRACE_ACTIVE (debug > 0 && com_base == 0)
124
125	/* adapter number from AD_INFO pointer; mainly for dprintf() purposes */
126	#define ad_no(ai) (((u16) ai - (u16) ad_infos) / sizeof(*ai))
127
128	/* Convert far function address into NPFN (the DDK needs this all over the
129	* place and just casting to NPFN will produce a "segment lost in conversion"
130	* warning. Since casting to a u32 is a bit nasty for function pointers and
131	* might have to be revised for different compilers, we'll use a central
132	* macro for this crap.
133	*/
134	#define mk_NPFN(func) (NPFN) (u32) (func)
135
136	/* stdarg.h macros with explicit far pointers
137	*
138	* NOTE: The compiler pushes fixed arguments with 16 bits minimum, thus
139	* the last fixed argument (i.e. the one passed to va_start) must
140	* have at least 16 bits. Otherwise, the address calculation in
141	* va_start() will fail.
142	*/
143	typedef char _far *va_list;
144	#define va_start(va, last) va = (va_list) (&last + 1)
145	#define va_arg(va, type) ((type _far *) (va += sizeof(type)))[-1]
146	#define va_end(va) va = 0
147
148	/* ctype macros */
149	#define isupper(ch) ((ch) >= 'A' && (ch) <= 'Z')
150	#define tolower(ch) (isupper(ch) ? (ch) + ('a' - 'A') : (ch))
151
152	/* stddef macros */
153	#define offsetof(s, e) ((u16) &((s *) 0)->e)
154
155	/* SMP spinlock compatibility macros for older DDKs using CLI/STI */
156	#ifndef OS2AHCI_SMP
157	#define DevHelp_CreateSpinLock(p_sph) *(p_sph) = 0
158	#define DevHelp_FreeSpinLock(sph) 0
159
160	#define DevHelp_AcquireSpinLock(sph) if ((sph) != 0) \
161	panic("recursive spinlock"); \
162	(sph) = disable()
163
164	#define DevHelp_ReleaseSpinLock(sph) if (sph) { \
165	(sph) = 0; \
166	enable(); \
167	}
168	#endif
169
170	/* shortcut macros */
171	#define spin_lock(sl) DevHelp_AcquireSpinLock(sl)
172	#define spin_unlock(sl) DevHelp_ReleaseSpinLock(sl)
173
174	/* Get AHCI port MMIO base from AD_INFO and port number. For the time being,
175	* MMIO addresses are assumed to be valid 16:16 pointers which implies
176	* that one GDT selector is allocated per adapter.
177	*/
178	#define port_base(ai, p) ((u8 _far ) (ai)->mmio + 0x100 + (p) 0x80)
179
180	/* Get address of port-specific DMA scratch buffer. The total size of all DMA
181	* buffers required for 32 ports exceeds 65536 bytes, thus we need multiple
182	* GDT selectors to access all port DMA scratch buffers and some logic to map
183	* a port number to the corresponding DMA scratch buffer address.
184	*/
185	#define PORT_DMA_BUFS_PER_SEG ((size_t) (65536UL / AHCI_PORT_PRIV_DMA_SZ))
186	#define PORT_DMA_BUF_SEGS ((AHCI_MAX_PORTS + PORT_DMA_BUFS_PER_SEG - 1) \
187	/ PORT_DMA_BUFS_PER_SEG)
188	#define PORT_DMA_SEG_SIZE ((u32) PORT_DMA_BUFS_PER_SEG * \
189	(u32) AHCI_PORT_PRIV_DMA_SZ)
190
191	#define port_dma_base(ai, p) \
192	((AHCI_PORT_DMA _far *) ((ai)->dma_buf[(p) / PORT_DMA_BUFS_PER_SEG] + \
193	((p) % PORT_DMA_BUFS_PER_SEG) * AHCI_PORT_PRIV_DMA_SZ))
194
195	#define port_dma_base_phys(ai, p) \
196	((ai)->dma_buf_phys + (u32) (p) * AHCI_PORT_PRIV_DMA_SZ)
197
198	/* Convert an SATA adapter/port/device address into a 16-bit IORB unit handle
199	* (and the other way round). The mapping looks like this:
200	*
201	* mapping comment
202	* -----------------------------------------------------------------------
203	* 4 bits for the adapter current max is 8 adapters
204	* 4 bits for the port AHCI spec defines up to 32 ports
205	* 4 bits for the device SATA spec defines up to 15 devices behind PMP
206	*/
207	#define iorb_unit(a, p, d) ((((u16) (a) & 0x0fU) << 8) \| \
208	(((u16) (p) & 0x0fU) << 4) \| \
209	(((u16) (d) & 0x0fU)))
210	#define iorb_unit_adapter(iorb) (((u16) (iorb)->UnitHandle >> 8) & 0x07U)
211	#define iorb_unit_port(iorb) (((u16) (iorb)->UnitHandle >> 4) & 0x0fU)
212	#define iorb_unit_device(iorb) ((u16) (iorb)->UnitHandle & 0x0fU)
213
214	/*******************************************************************************
215	* Convenience macros for IORB processing functions
216	*/
217	/* is this IORB on driver or port level? */
218	#define iorb_driver_level(iorb) ((iorb)->CommandCode == IOCC_CONFIGURATION)
219
220	/* is this IORB to be inserted at the beginnig of the IORB queue? */
221	#define iorb_priority(iorb) ((iorb)->CommandCode == IOCC_DEVICE_CONTROL && \
222	(iorb)->CommandModifier == IOCM_ABORT))
223
224	/* access IORB ADD workspace */
225	#define add_workspace(iorb) ((ADD_WORKSPACE _far *) &(iorb)->ADDWorkSpace)
226
227
228
229	/******************************************************************************
230	* PCI generic IDs and macros
231	*/
232	#define PCI_ANY_ID 0xffffU
233	#define PCI_VDEVICE(vendor, device) PCI_VENDOR_ID_##vendor, (device), \
234	PCI_ANY_ID, PCI_ANY_ID, 0, 0
235
236	/******************************************************************************
237	* PCI vendor IDs for AHCI adapters known to this driver (copied from Linux
238	* pci_ids.h)
239	*/
240	#define PCI_VENDOR_ID_AL 0x10b9
241	#define PCI_VENDOR_ID_AMD 0x1022
242	#define PCI_VENDOR_ID_AT 0x1259
243	#define PCI_VENDOR_ID_ATI 0x1002
244	#define PCI_VENDOR_ID_ATT 0x11c1
245	#define PCI_VENDOR_ID_CMD 0x1095
246	#define PCI_VENDOR_ID_CT 0x102c
247	#define PCI_VENDOR_ID_INTEL 0x8086
248	#define PCI_VENDOR_ID_INITIO 0x1101
249	#define PCI_VENDOR_ID_JMICRON 0x197B
250	#define PCI_VENDOR_ID_MARVELL 0x11ab
251	#define PCI_VENDOR_ID_NVIDIA 0x10de
252	#define PCI_VENDOR_ID_PROMISE 0x105a
253	#define PCI_VENDOR_ID_SI 0x1039
254	#define PCI_VENDOR_ID_VIA 0x1106
255
256	/******************************************************************************
257	* PCI class IDs we're interested in (copied from Linux pci_ids.h)
258	*/
259	#define PCI_BASE_CLASS_STORAGE 0x01
260	#define PCI_CLASS_STORAGE_SCSI 0x0100
261	#define PCI_CLASS_STORAGE_IDE 0x0101
262	#define PCI_CLASS_STORAGE_FLOPPY 0x0102
263	#define PCI_CLASS_STORAGE_IPI 0x0103
264	#define PCI_CLASS_STORAGE_RAID 0x0104
265	#define PCI_CLASS_STORAGE_SATA 0x0106
266	#define PCI_CLASS_STORAGE_SATA_AHCI 0x010601
267	#define PCI_CLASS_STORAGE_SAS 0x0107
268	#define PCI_CLASS_STORAGE_OTHER 0x0180
269
270	/******************************************************************************
271	* ANSI color code constants
272	*/
273	#define ANSI_CLR_BRIGHT "\x1b[1m"
274	#define ANSI_CLR_RED "\x1b[31m"
275	#define ANSI_CLR_GREEN "\x1b[32m"
276	#define ANSI_CLR_BLUE "\x1b[34m"
277	#define ANSI_CLR_CYAN "\x1b[36m"
278	#define ANSI_CLR_WHITE "\x1b[37m"
279	#define ANSI_RESET "\x1b[0m"
280
281
282	/* ------------------------ typedefs and structures ------------------------ */
283
284	typedef unsigned int size_t;
285
286	typedef struct {
287	u32 Start;
288	u32 End;
289	} TIMER;
290
291	/* PCI device information structure; this is used both for scanning and for
292	* identification purposes in 'AD_INFO'; based on the Linux pci_device_id
293	* structure but hard-wired to use board_* constants for 'driver_data'
294	*/
295	typedef struct {
296	u16 vendor; /* PCI device vendor/manufacturer */
297	u16 device; /* PCI device ID inside vendor scope */
298	u16 subvendor; /* subsystem vendor (unused so far) */
299	u16 subdevice; /* subsystem device (unused so far) */
300	u32 class; /* PCI device class */
301	u32 class_mask; /* bits to match when scanning for 'class' */
302	u32 board; /* AHCI controller board type (board_* constants) */
303	char chipname; / human readable chip ID string */
304	} PCI_ID;
305
306	/* IORB queue; since IORB queues are updated at interrupt time, the
307	* corresponding pointers (not the data they point to) need to be volatile.
308	*/
309	typedef struct {
310	IORBH _far volatile root; / root of request list */
311	IORBH _far volatile tail; / tail of request list */
312	} IORB_QUEUE;
313
314	/* port information structure */
315	typedef struct {
316	IORB_QUEUE iorb_queue; /* IORB queue for this port */
317	unsigned dev_max : 4; /* maximum device number on this port (0-15) */
318	unsigned cmd_slot : 5; /* current command slot index (using round-
319	* robin indexes to prevent starvation) */
320
321	volatile u32 ncq_cmds; /* bitmap for NCQ commands issued */
322	volatile u32 reg_cmds; /* bitmap for regular commands issued */
323
324	struct {
325	unsigned allocated : 1; /* if != 0, device is allocated */
326	unsigned present : 1; /* if != 0, device is present */
327	unsigned lba48 : 1; /* if != 0, device supports 48-bit LBA */
328	unsigned atapi : 1; /* if != 0, this is an ATAPI device */
329	unsigned atapi_16 : 1; /* if != 0, device suports 16-byte cmds */
330	unsigned removable : 1; /* if != 0, device has removable media */
331	unsigned dev_type : 5; /* device type (UIB_TYPE_* in iorb.h) */
332	unsigned ncq_max : 5; /* maximum tag number for queued commands */
333	UNITINFO _far unit_info; / pointer to modified unit info */
334	} devs[15];
335	} P_INFO;
336
337	/* adapter information structure */
338	typedef struct {
339	PCI_ID pci; / pointer to corresponding PCI ID */
340
341	unsigned port_max : 5; /* maximum port number (0-31) */
342	unsigned cmd_max : 5; /* maximum cmd slot number (0-31) */
343	unsigned port_scan_done : 1; /* if != 0, port scan already done */
344	unsigned busy : 1; /* if != 0, adapter is busy */
345
346	u32 port_map; /* bitmap of active ports */
347
348	/* initial adapter configuration from BIOS */
349	u32 bios_config[HOST_CAP2 / sizeof(u32) + 1];
350
351	u32 cap; /* working copy of CAP register */
352	u32 cap2; /* working copy of CAP2 register */
353	u32 flags; /* adapter flags */
354
355	HRESOURCE rm_adh; /* resource handle for adapter */
356	HRESOURCE rm_bars[6]; /* resource handle for MMIO and I/O BARs */
357	HRESOURCE rm_irq; /* resource handle for IRQ */
358
359	u8 bus; /* PCI bus number */
360	u8 dev_func; /* PCI device and function number */
361	u16 irq; /* interrupt number */
362
363	u32 mmio_phys; /* physical address of MMIO region */
364	u32 mmio_size; /* size of MMIO region */
365	u8 _far mmio; / pointer to this adapter's MMIO region */
366
367	u32 dma_buf_phys; /* physical address of DMA scratch buffer */
368	u8 _far dma_buf[PORT_DMA_BUF_SEGS]; / DMA scatch buffer */
369
370	P_INFO ports[AHCI_MAX_PORTS]; /* SATA ports on this adapter */
371	} AD_INFO;
372
373	/* ADD workspace in IORB (must not exceed 16 bytes) */
374	typedef struct {
375	void (ppfunc)(IORBH _far iorb); /* post-processing function */
376	void buf; / response buffer (e.g. for identify cmds) */
377	ULONG timer; /* timer for timeout procesing */
378	USHORT blocks; /* number of blocks to be transferred */
379	unsigned processing : 1; /* IORB is being processd */
380	unsigned idempotent : 1; /* IORB is idempotent (can be retried) */
381	unsigned queued_hw : 1; /* IORB has been queued to hardware */
382	unsigned no_ncq : 1; /* must not use native command queuing */
383	unsigned is_ncq : 1; /* should use native command queueing */
384	unsigned complete : 1; /* IORB has completed processing */
385	unsigned unaligned : 1; /* unaligned S/G; need to use transfer buffer */
386	unsigned retries : 2; /* number of retries for this command */
387	unsigned cmd_slot : 5; /* AHCI command slot for this IORB */
388	} ADD_WORKSPACE;
389
390	/* sg_memcpy() direction */
391	typedef enum {
392	SG_TO_BUF, /* copy from S/G list to buffer */
393	BUF_TO_SG /* copy from buffer to S/G list */
394	} SG_MEMCPY_DIRECTION;
395
396	/* Define the size of a disk name. Disk Names are user defined names given to physical disk drives in the system. */
397	#define DLA_TABLE_SIGNATURE1 0x424D5202L
398	#define DLA_TABLE_SIGNATURE2 0x44464D50L
399	#define DISK_NAME_SIZE 20
400
401	typedef struct _DLA_Table_Sector { /* DTS */
402	ULONG DLA_Signature1; /* The magic signature (part 1) of a Drive Letter Assignment Table. */
403	ULONG DLA_Signature2; /* The magic signature (part 2) of a Drive Letter Assignment Table. */
404	ULONG DLA_CRC; /* The 32 bit CRC for this sector. Calculated assuming that this field and all unused space in the sector is 0. */
405	ULONG Disk_Serial_Number; /* The serial number assigned to this disk. */
406	ULONG Boot_Disk_Serial_Number;/* The serial number of the disk used to boot the system. This is for conflict resolution when multiple volumes
407	want the same drive letter. Since LVM.EXE will not let this situation happen, the only way to get this situation
408	is for the disk to have been altered by something other than LVM.EXE, or if a disk drive has been moved from one
409	machine to another. If the drive has been moved, then it should have a different Boot_Disk_Serial_Number. Thus,
410	we can tell which disk drive is the "foreign" drive and therefore reject its claim for the drive letter in question.
411	If we find that all of the claimaints have the same Boot_Disk_Serial_Number, then we must assign drive letters on
412	a first come, first serve basis. */
413	ULONG Install_Flags; /* Used by the Install program. */
414	ULONG Cylinders;
415	ULONG Heads_Per_Cylinder;
416	ULONG Sectors_Per_Track;
417	char Disk_Name[DISK_NAME_SIZE]; /* The name assigned to the disk containing this sector. */
418	UCHAR Reboot; /* For use by Install. Used to keep track of reboots initiated by install. */
419	BYTE Reserved[3]; /* Alignment. */
420	/* These are the four entries which correspond to the entries in the partition table. */
421	} DLA_Table_Sector, *PDLA_Table_Sector;
422
423	/* -------------------------- function prototypes -------------------------- */
424
425	/* init.asm */
426	extern u32 _cdecl readl (void _far *addr);
427	extern u32 _cdecl writel (void _far *addr, u32 val);
428	extern void _far * _cdecl memcpy (void _far v_dst, void _far v_src, int len);
429	extern void _far * _cdecl memset (void _far *p, int ch, size_t len);
430	extern void _cdecl _far restart_hook (void);
431	extern void _cdecl _far reset_hook (void);
432	extern void _cdecl _far engine_hook (void);
433	extern void _cdecl _far asm_krnl_exit (void);
434	extern void _cdecl udelay (u16 microseconds);
435
436	/* os2ahci.c */
437	extern USHORT init_drv (RPINITIN _far *req);
438	extern USHORT gen_ioctl (RP_GENIOCTL _far *ioctl);
439	extern USHORT char_dev_input (RP_RWV _far *rwrb);
440	extern USHORT exit_drv (int func);
441	extern USHORT sr_drv (int func);
442	extern void _cdecl _far _loadds add_entry (IORBH _far *iorb);
443	extern void trigger_engine (void);
444	extern int trigger_engine_1 (void);
445	extern void send_iorb (IORBH _far *iorb);
446	extern void iocc_configuration (IORBH _far *iorb);
447	extern void iocc_device_control (IORBH _far *iorb);
448	extern void iocc_unit_control (IORBH _far *iorb);
449	extern void iocm_device_table (IORBH _far *iorb);
450	extern void iocc_geometry (IORBH _far *iorb);
451	extern void iocc_execute_io (IORBH _far *iorb);
452	extern void iocc_unit_status (IORBH _far *iorb);
453	extern void iocc_adapter_passthru (IORBH _far *iorb);
454	extern void iorb_queue_add (IORB_QUEUE _far queue, IORBH _far iorb);
455	extern int iorb_queue_del (IORB_QUEUE _far queue, IORBH _far iorb);
456	extern void iorb_seterr (IORBH _far *iorb, USHORT error_code);
457	extern void iorb_done (IORBH _far *iorb);
458	extern void iorb_complete (IORBH _far *iorb);
459	extern void iorb_requeue (IORBH _far *iorb);
460	extern void aws_free (ADD_WORKSPACE _far *aws);
461	extern void lock_adapter (AD_INFO *ai);
462	extern void unlock_adapter (AD_INFO *ai);
463	extern void _cdecl _far timeout_callback (ULONG timer_handle, ULONG p1, ULONG p2);
464	extern void _cdecl _far reset_watchdog (ULONG timer_handle, ULONG p1, ULONG p2);
465
466	/* ahci.c */
467	extern int ahci_save_bios_config (AD_INFO *ai);
468	extern int ahci_restore_bios_config (AD_INFO *ai);
469	extern int ahci_restore_initial_config (AD_INFO *ai);
470	extern AHCI_PORT_CFG ahci_save_port_config (AD_INFO ai, int p);
471	extern void ahci_restore_port_config (AD_INFO *ai, int p,
472	AHCI_PORT_CFG *pc);
473	extern int ahci_enable_ahci (AD_INFO *ai);
474	extern int ahci_scan_ports (AD_INFO *ai);
475	extern int ahci_complete_init (AD_INFO *ai);
476	extern int ahci_reset_port (AD_INFO *ai, int p, int ei);
477	extern int ahci_start_port (AD_INFO *ai, int p, int ei);
478	extern void ahci_start_fis_rx (AD_INFO *ai, int p);
479	extern void ahci_start_engine (AD_INFO *ai, int p);
480	extern int ahci_stop_port (AD_INFO *ai, int p);
481	extern int ahci_stop_fis_rx (AD_INFO *ai, int p);
482	extern int ahci_stop_engine (AD_INFO *ai, int p);
483	extern int ahci_port_busy (AD_INFO *ai, int p);
484	extern void ahci_exec_iorb (IORBH _far *iorb, int ncq_capable,
485	int (func)(IORBH _far , int));
486	extern void ahci_exec_polled_iorb (IORBH _far *iorb,
487	int (func)(IORBH _far , int),
488	ULONG timeout);
489	extern int ahci_exec_polled_cmd (AD_INFO *ai, int p, int d,
490	int timeout, int cmd, ...);
491	extern int ahci_set_dev_idle (AD_INFO *ai, int p, int d, int idle);
492	extern int ahci_flush_cache (AD_INFO *ai, int p, int d);
493
494	extern int ahci_intr (u16 irq);
495	extern void ahci_port_intr (AD_INFO *ai, int p);
496	extern void ahci_error_intr (AD_INFO *ai, int p, u32 irq_stat);
497
498	extern void ahci_get_geometry (IORBH _far *iorb);
499	extern void ahci_unit_ready (IORBH _far *iorb);
500	extern void ahci_read (IORBH _far *iorb);
501	extern void ahci_verify (IORBH _far *iorb);
502	extern void ahci_write (IORBH _far *iorb);
503	extern void ahci_execute_cdb (IORBH _far *iorb);
504	extern void ahci_execute_ata (IORBH _far *iorb);
505
506	/* libc.c */
507	extern void init_libc (void);
508	extern void init_com (long BaudRate);
509	extern int vsprintf (char _far buf, const char fmt, va_list va);
510	extern int sprintf (char _far buf, const char fmt, ...);
511	extern void vfprintf (const char *fmt, va_list va);
512	extern void _cdecl printf (const char *fmt, ...);
513	extern void _cdecl printf_nts (const char *fmt, ...);
514	extern void cprintf (const char *fmt, ...);
515	extern void phex (const void _far p, int len, const char fmt, ...);
516	extern size_t strlen (const char _far *s);
517	extern char _far strcpy (char _far dst, const char _far *src);
518	extern int memcmp (void _far p1, void _far p2, size_t len);
519	extern void sg_memcpy (SCATGATENTRY _far *sg_list, USHORT sg_cnt,
520	ULONG sg_off, void _far *buf, USHORT len,
521	SG_MEMCPY_DIRECTION dir);
522	extern long strtol (const char _far *buf,
523	const char _far * _far *ep, int base);
524	extern void *malloc (size_t len);
525	extern void free (void *ptr);
526	extern ULONG virt_to_phys (void _far *ptr);
527	//NOT_USED extern void mdelay_cal (void);
528	//NOT_USED extern void mdelay (u32 millies);
529	extern void msleep (u32 millies);
530	extern void panic (char *msg);
531	extern int disable (void);
532	extern void enable (void);
533	extern void timer_init(TIMER far *pTimer, u32 Milliseconds);
534	extern int timer_check_and_block(TIMER far *pTimer);
535
536	/* trace.c */
537	extern void trace_init (u16);
538	extern void trace_exit (void);
539	extern void trace_write (u8 _far *s, int len);
540	extern u16 trace_read (u8 _far *buf, u16 cb_buf);
541	extern u16 trace_char_dev(RP_RWV _far *rwrb);
542	extern void build_user_info(void);
543
544	/* pci.c */
545	extern int add_pci_id (u16 vendor, u16 device);
546	extern void scan_pci_bus (void);
547	extern int pci_enable_int (UCHAR bus, UCHAR dev_func);
548	extern void pci_hack_virtualbox(void);
549	extern char *vendor_from_id (u16 vendor);
550	extern char *device_from_id (u16 device);
551	UCHAR pci_read_conf (UCHAR bus, UCHAR dev_func, UCHAR indx,
552	UCHAR size, ULONG _far *val);
553	UCHAR pci_write_conf (UCHAR bus, UCHAR dev_func, UCHAR indx, UCHAR size,
554	ULONG val);
555
556	/* ctxhook.c */
557	extern void _cdecl restart_ctxhook (ULONG parm);
558	extern void _cdecl reset_ctxhook (ULONG parm);
559	extern void _cdecl engine_ctxhook (ULONG parm);
560
561	/* apm.c */
562	extern void apm_init (void);
563	extern void apm_suspend (void);
564	extern void apm_resume (void);
565
566	/* ioctl.c */
567	extern USHORT ioctl_get_devlist (RP_GENIOCTL _far *ioctl);
568	extern USHORT ioctl_passthrough (RP_GENIOCTL _far *ioctl);
569	extern USHORT ioctl_gen_dsk (RP_GENIOCTL _far *ioctl);
570	extern USHORT ioctl_smart (RP_GENIOCTL _far *ioctl);
571
572
573	/* ---------------------------- global variables --------------------------- */
574
575	extern char _cdecl end_of_data; /* label at the end of all data segments */
576	extern void _cdecl _near end_of_code(); /* label at the end of all code segments */
577
578	extern int debug; /* if != 0, print debug messages to COM1 */
579	extern int thorough_scan; /* if != 0, perform thorough PCI scan */
580	extern int init_reset; /* if != 0, reset ports during init */
581	extern int force_write_cache; /* if != 0, force write cache */
582	extern int verbosity; /* if != 0, show some info during boot */
583	extern int use_lvm_info;
584	extern int wrap_trace_buffer;
585
586	extern HDRIVER rm_drvh; /* resource manager driver handle */
587	extern USHORT add_handle; /* adapter device driver handle */
588	extern UCHAR timer_pool[]; /* timer pool */
589	extern char drv_name[]; /* driver name as string ("OS2AHCI") */
590
591	extern PCI_ID pci_ids[]; /* SATA adapter PCI IDs */
592	extern ULONG drv_lock; /* driver-level spinlock */
593	extern ULONG com_lock; /* debug log spinlock */
594	extern IORB_QUEUE driver_queue; /* driver-level IORB queue */
595	extern AD_INFO ad_infos[]; /* adapter information list */
596	extern int ad_info_cnt; /* number of entries in ad_infos[] */
597	extern u16 ad_ignore; /* bitmap with adapters to be ignored */
598	extern int init_complete; /* if != 0, initialization has completed */
599	extern int suspended; /* indicates if the driver is suspended */
600
601	extern u16 com_base; /* debug COM port base address */
602
603	/* port restart context hook and input data */
604	extern ULONG restart_ctxhook_h;
605	extern volatile u32 ports_to_restart[MAX_AD];
606
607	/* port reset context hook and input data */
608	extern ULONG reset_ctxhook_h;
609	extern ULONG th_reset_watchdog;
610	extern volatile u32 ports_to_reset[MAX_AD];
611	extern IORB_QUEUE abort_queue;
612
613	/* trigger engine context hook and input data */
614	extern ULONG engine_ctxhook_h;
615
616	/* apapter/port-specific options saved when parsing the command line */
617	extern u8 emulate_scsi[MAX_AD][AHCI_MAX_PORTS];
618	extern u8 enable_ncq[MAX_AD][AHCI_MAX_PORTS];
619	extern u8 link_speed[MAX_AD][AHCI_MAX_PORTS];
620	extern u8 link_power[MAX_AD][AHCI_MAX_PORTS];
621	extern u8 track_size[MAX_AD][AHCI_MAX_PORTS];
622

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