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source: trunk/src/os2ahci/os2ahci.h@ 161

Last change on this file since 161 was 161, checked in by David Azarewicz, 12 years ago
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1	/******************************************************************************
2	* os2ahci.h - main header file for os2ahci driver
3	*
4	* Copyright (c) 2011 thi.guten Software Development
5	* Copyright (c) 2011 Mensys B.V.
6	*
7	* Authors: Christian Mueller, Markus Thielen
8	*
9	* Parts copied from/inspired by the Linux AHCI driver;
10	* those parts are (c) Linux AHCI/ATA maintainers
11	*
12	* This program is free software; you can redistribute it and/or modify
13	* it under the terms of the GNU General Public License as published by
14	* the Free Software Foundation; either version 2 of the License, or
15	* (at your option) any later version.
16	*
17	* This program is distributed in the hope that it will be useful,
18	* but WITHOUT ANY WARRANTY; without even the implied warranty of
19	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20	* GNU General Public License for more details.
21	*
22	* You should have received a copy of the GNU General Public License
23	* along with this program; if not, write to the Free Software
24	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
25	*/
26
27	/* ----------------------------- include files ----------------------------- */
28
29	/* IMPORTANT NOTE: The DDK headers require tight structure packing and this
30	* is controlled via compiler parameters. Thus, all stuctures in os2ahci.add
31	* are expected to be byte-aligned without the need of explicit pragma pack()
32	* directives. Where possible, the structures are laid out such that words
33	* and dwords are aligned at least on 2-byte boundaries.
34	*/
35
36	/* Global feature defines
37	* DEBUG = enable debug logging routines to be compled in.
38	* LEGACY_APM = enable the legacy APM interface to be compiled in.
39	* Legacy APM support is not needed on eCS systems with ACPI and is more reliable without it enabled.
40	*/
41	#define DEBUG
42	//#define LEGACY_APM
43
44	#define INCL_NOPMAPI
45	#define INCL_DOSINFOSEG
46	#define INCL_NO_SCB
47	#define INCL_DOSERRORS
48	#include <os2.h>
49	#include <dos.h>
50	#include <bseerr.h>
51	#include <dskinit.h>
52	#include <scb.h>
53
54	#include <devhdr.h>
55	#include <iorb.h>
56	#include <strat2.h>
57	#include <reqpkt.h>
58
59	/* NOTE: (Rousseau)
60	* The regular dhcalls.h from $(DDK)\base\h also works.
61	* The devhelp.h from $(DDK)\base\h produces inline assembler errors.
62	* The modified devhelp.h from ..\include works OK and is used because it
63	* generates a slightly smaller driver image.
64	*/
65	#ifdef __WATCOMC__
66	/* include WATCOM specific DEVHELP stubs */
67	#include <devhelp.h>
68	#else
69	#include <dhcalls.h>
70	#endif
71
72	#include <addcalls.h>
73	#include <rmcalls.h>
74	#include <devclass.h>
75	#include <devcmd.h>
76	#include <rmbase.h>
77
78	#include "ahci.h"
79	#include "ahci-idc.h"
80
81	/* -------------------------- macros and constants ------------------------- */
82
83	#define MAX_AD 8 /* maximum number of adapters */
84
85	/* Timer pool size. In theory, we need one timer per outstanding command plus
86	* a few miscellaneous timers but it's unlikely we'll ever have outstanding
87	* commands on all devices on all ports on all apapters -- this would be
88	* 8 * 32 * 32 = 8192 outstanding commands on a maximum of 8 * 32 * 15 = 3840
89	* devices and that's a bit of an exaggeration. It should be more than enough
90	* to have 128 timers.
91	*/
92	#define TIMER_COUNT 128
93	#define TIMER_POOL_SIZE (sizeof(ADD_TIMER_POOL) + \
94	TIMER_COUNT * sizeof(ADD_TIMER_DATA))
95
96	/* default command timeout (can be overwritten in the IORB) */
97	#define DEFAULT_TIMEOUT 30000
98
99	/* Maximum number of retries for commands in the restart/reset context hooks.
100	*
101	* Please note that the corresponding variable in the ADD workspace is a bit
102	* field, thus increasing this value means increasing the size of the bit
103	* field. At the time of writing this comment the 'retries' variable was 2
104	* bits wide (i.e. a maximum number of 3 retries) and there was exactly one
105	* bit left before the ADD workspace structure would become too large...
106	*/
107	#define MAX_RETRIES 3
108
109	/* max/min macros */
110	#define max(a, b) (a) > (b) ? (a) : (b)
111	#define min(a, b) (a) < (b) ? (a) : (b)
112
113	/* debug output macros */
114	#ifdef DEBUG
115	#define dprintf if (debug > 0) printf
116	#define dphex if (debug > 0) phex
117	#define ddprintf if (debug > 1) printf
118	#define ddphex if (debug > 1) phex
119	#define dddprintf if (debug > 2) printf
120	#define dddphex if (debug > 2) phex
121	#define ntprintf printf_nts
122	#define aprintf printf
123	#else
124	#define dprintf(a,...)
125	#define dphex(a,b,c,...)
126	#define ddprintf(a,...)
127	#define ddphex(a,b,c,...)
128	#define dddprintf(a,...)
129	#define dddphex(a,b,c,...)
130	#define ntprintf(a,...)
131	#define aprintf(a,...)
132	#endif
133
134	/* verbosity console print macros
135	* (we use 'i' in ciprintf here to avoid name clash
136	* with vprintf-like funcs)
137	*/
138	#define ciprintf if (verbosity > 0) cprintf
139	#define ciiprintf if (verbosity > 1) cprintf
140
141	/* TRACE macros (for our internal ring buffer trace) */
142	#define AHCI_TRACE_BUF_SIZE 0x8000U /* 32k */
143	#define AHCI_INFO_BUF_SIZE 0x1000U /* 4k */
144	#define TRACE_ACTIVE (debug > 0 && com_base == 0)
145
146	/* adapter number from AD_INFO pointer; mainly for dprintf() purposes */
147	#define ad_no(ai) (((u16) ai - (u16) ad_infos) / sizeof(*ai))
148
149	/* Convert far function address into NPFN (the DDK needs this all over the
150	* place and just casting to NPFN will produce a "segment lost in conversion"
151	* warning. Since casting to a u32 is a bit nasty for function pointers and
152	* might have to be revised for different compilers, we'll use a central
153	* macro for this crap.
154	*/
155	#define mk_NPFN(func) (NPFN) (u32) (func)
156
157	/* stdarg.h macros with explicit far pointers
158	*
159	* NOTE: The compiler pushes fixed arguments with 16 bits minimum, thus
160	* the last fixed argument (i.e. the one passed to va_start) must
161	* have at least 16 bits. Otherwise, the address calculation in
162	* va_start() will fail.
163	*/
164	typedef char _far *va_list;
165	#define va_start(va, last) va = (va_list) (&last + 1)
166	#define va_arg(va, type) ((type _far *) (va += sizeof(type)))[-1]
167	#define va_end(va) va = 0
168
169	/* ctype macros */
170	#define isupper(ch) ((ch) >= 'A' && (ch) <= 'Z')
171	#define tolower(ch) (isupper(ch) ? (ch) + ('a' - 'A') : (ch))
172
173	/* stddef macros */
174	#define offsetof(s, e) ((u16) &((s *) 0)->e)
175
176	/* SMP spinlock compatibility macros for older DDKs using CLI/STI */
177	#ifndef OS2AHCI_SMP
178	#define DevHelp_CreateSpinLock(p_sph) *(p_sph) = 0
179	#define DevHelp_FreeSpinLock(sph) 0
180
181	#define DevHelp_AcquireSpinLock(sph) if ((sph) != 0) \
182	panic("recursive spinlock"); \
183	(sph) = disable()
184
185	#define DevHelp_ReleaseSpinLock(sph) if (sph) { \
186	(sph) = 0; \
187	enable(); \
188	}
189	#endif
190
191	/* shortcut macros */
192	#define spin_lock(sl) DevHelp_AcquireSpinLock(sl)
193	#define spin_unlock(sl) DevHelp_ReleaseSpinLock(sl)
194
195	/* Get AHCI port MMIO base from AD_INFO and port number. For the time being,
196	* MMIO addresses are assumed to be valid 16:16 pointers which implies
197	* that one GDT selector is allocated per adapter.
198	*/
199	#define port_base(ai, p) ((u8 _far ) (ai)->mmio + 0x100 + (p) 0x80)
200
201	/* Get address of port-specific DMA scratch buffer. The total size of all DMA
202	* buffers required for 32 ports exceeds 65536 bytes, thus we need multiple
203	* GDT selectors to access all port DMA scratch buffers and some logic to map
204	* a port number to the corresponding DMA scratch buffer address.
205	*/
206	#define PORT_DMA_BUFS_PER_SEG ((size_t) (65536UL / AHCI_PORT_PRIV_DMA_SZ))
207	#define PORT_DMA_BUF_SEGS ((AHCI_MAX_PORTS + PORT_DMA_BUFS_PER_SEG - 1) \
208	/ PORT_DMA_BUFS_PER_SEG)
209	#define PORT_DMA_SEG_SIZE ((u32) PORT_DMA_BUFS_PER_SEG * \
210	(u32) AHCI_PORT_PRIV_DMA_SZ)
211
212	#define port_dma_base(ai, p) \
213	((AHCI_PORT_DMA _far *) ((ai)->dma_buf[(p) / PORT_DMA_BUFS_PER_SEG] + \
214	((p) % PORT_DMA_BUFS_PER_SEG) * AHCI_PORT_PRIV_DMA_SZ))
215
216	#define port_dma_base_phys(ai, p) \
217	((ai)->dma_buf_phys + (u32) (p) * AHCI_PORT_PRIV_DMA_SZ)
218
219	/* Convert an SATA adapter/port/device address into a 16-bit IORB unit handle
220	* (and the other way round). The mapping looks like this:
221	*
222	* mapping comment
223	* -----------------------------------------------------------------------
224	* 4 bits for the adapter current max is 8 adapters
225	* 4 bits for the port AHCI spec defines up to 32 ports
226	* 4 bits for the device SATA spec defines up to 15 devices behind PMP
227	*/
228	#define iorb_unit(a, p, d) ((((u16) (a) & 0x0fU) << 8) \| \
229	(((u16) (p) & 0x0fU) << 4) \| \
230	(((u16) (d) & 0x0fU)))
231	#define iorb_unit_adapter(iorb) (((u16) (iorb)->UnitHandle >> 8) & 0x07U)
232	#define iorb_unit_port(iorb) (((u16) (iorb)->UnitHandle >> 4) & 0x0fU)
233	#define iorb_unit_device(iorb) ((u16) (iorb)->UnitHandle & 0x0fU)
234
235	/*******************************************************************************
236	* Convenience macros for IORB processing functions
237	*/
238	/* is this IORB on driver or port level? */
239	#define iorb_driver_level(iorb) ((iorb)->CommandCode == IOCC_CONFIGURATION)
240
241	/* is this IORB to be inserted at the beginnig of the IORB queue? */
242	#define iorb_priority(iorb) ((iorb)->CommandCode == IOCC_DEVICE_CONTROL && \
243	(iorb)->CommandModifier == IOCM_ABORT))
244
245	/* access IORB ADD workspace */
246	#define add_workspace(iorb) ((ADD_WORKSPACE _far *) &(iorb)->ADDWorkSpace)
247
248
249
250	/******************************************************************************
251	* PCI generic IDs and macros
252	*/
253	#define PCI_ANY_ID 0xffffU
254	#define PCI_VDEVICE(vendor, device) PCI_VENDOR_ID_##vendor, (device), \
255	PCI_ANY_ID, PCI_ANY_ID, 0, 0
256
257	/******************************************************************************
258	* PCI vendor IDs for AHCI adapters known to this driver (copied from Linux
259	* pci_ids.h)
260	*/
261	#define PCI_VENDOR_ID_AL 0x10b9
262	#define PCI_VENDOR_ID_AMD 0x1022
263	#define PCI_VENDOR_ID_AT 0x1259
264	#define PCI_VENDOR_ID_ATI 0x1002
265	#define PCI_VENDOR_ID_ATT 0x11c1
266	#define PCI_VENDOR_ID_CMD 0x1095
267	#define PCI_VENDOR_ID_CT 0x102c
268	#define PCI_VENDOR_ID_INTEL 0x8086
269	#define PCI_VENDOR_ID_INITIO 0x1101
270	#define PCI_VENDOR_ID_JMICRON 0x197B
271	#define PCI_VENDOR_ID_MARVELL 0x11ab
272	#define PCI_VENDOR_ID_NVIDIA 0x10de
273	#define PCI_VENDOR_ID_PROMISE 0x105a
274	#define PCI_VENDOR_ID_SI 0x1039
275	#define PCI_VENDOR_ID_VIA 0x1106
276
277	/******************************************************************************
278	* PCI class IDs we're interested in (copied from Linux pci_ids.h)
279	*/
280	#define PCI_BASE_CLASS_STORAGE 0x01
281	#define PCI_CLASS_STORAGE_SCSI 0x0100
282	#define PCI_CLASS_STORAGE_IDE 0x0101
283	#define PCI_CLASS_STORAGE_FLOPPY 0x0102
284	#define PCI_CLASS_STORAGE_IPI 0x0103
285	#define PCI_CLASS_STORAGE_RAID 0x0104
286	#define PCI_CLASS_STORAGE_SATA 0x0106
287	#define PCI_CLASS_STORAGE_SATA_AHCI 0x010601
288	#define PCI_CLASS_STORAGE_SAS 0x0107
289	#define PCI_CLASS_STORAGE_OTHER 0x0180
290
291	/******************************************************************************
292	* ANSI color code constants
293	*/
294	#define ANSI_CLR_BRIGHT "\x1b[1m"
295	#define ANSI_CLR_RED "\x1b[31m"
296	#define ANSI_CLR_GREEN "\x1b[32m"
297	#define ANSI_CLR_BLUE "\x1b[34m"
298	#define ANSI_CLR_CYAN "\x1b[36m"
299	#define ANSI_CLR_WHITE "\x1b[37m"
300	#define ANSI_RESET "\x1b[0m"
301
302
303	/* ------------------------ typedefs and structures ------------------------ */
304
305	typedef unsigned int size_t;
306
307	typedef struct {
308	u32 Start;
309	u32 End;
310	} TIMER;
311
312	/* PCI device information structure; this is used both for scanning and for
313	* identification purposes in 'AD_INFO'; based on the Linux pci_device_id
314	* structure but hard-wired to use board_* constants for 'driver_data'
315	*/
316	typedef struct {
317	u16 vendor; /* PCI device vendor/manufacturer */
318	u16 device; /* PCI device ID inside vendor scope */
319	u16 subvendor; /* subsystem vendor (unused so far) */
320	u16 subdevice; /* subsystem device (unused so far) */
321	u32 class; /* PCI device class */
322	u32 class_mask; /* bits to match when scanning for 'class' */
323	u32 board; /* AHCI controller board type (board_* constants) */
324	char chipname; / human readable chip ID string */
325	} PCI_ID;
326
327	/* IORB queue; since IORB queues are updated at interrupt time, the
328	* corresponding pointers (not the data they point to) need to be volatile.
329	*/
330	typedef struct {
331	IORBH _far volatile root; / root of request list */
332	IORBH _far volatile tail; / tail of request list */
333	} IORB_QUEUE;
334
335	/* port information structure */
336	typedef struct {
337	IORB_QUEUE iorb_queue; /* IORB queue for this port */
338	unsigned dev_max : 4; /* maximum device number on this port (0-15) */
339	unsigned cmd_slot : 5; /* current command slot index (using round-
340	* robin indexes to prevent starvation) */
341
342	volatile u32 ncq_cmds; /* bitmap for NCQ commands issued */
343	volatile u32 reg_cmds; /* bitmap for regular commands issued */
344
345	struct {
346	unsigned allocated : 1; /* if != 0, device is allocated */
347	unsigned present : 1; /* if != 0, device is present */
348	unsigned lba48 : 1; /* if != 0, device supports 48-bit LBA */
349	unsigned atapi : 1; /* if != 0, this is an ATAPI device */
350	unsigned atapi_16 : 1; /* if != 0, device suports 16-byte cmds */
351	unsigned removable : 1; /* if != 0, device has removable media */
352	unsigned dev_type : 5; /* device type (UIB_TYPE_* in iorb.h) */
353	unsigned ncq_max : 5; /* maximum tag number for queued commands */
354	UNITINFO _far unit_info; / pointer to modified unit info */
355	} devs[15];
356	} P_INFO;
357
358	/* adapter information structure */
359	typedef struct {
360	PCI_ID pci; / pointer to corresponding PCI ID */
361
362	unsigned port_max : 5; /* maximum port number (0-31) */
363	unsigned cmd_max : 5; /* maximum cmd slot number (0-31) */
364	unsigned port_scan_done : 1; /* if != 0, port scan already done */
365	unsigned busy : 1; /* if != 0, adapter is busy */
366
367	u32 port_map; /* bitmap of active ports */
368
369	/* initial adapter configuration from BIOS */
370	u32 bios_config[HOST_CAP2 / sizeof(u32) + 1];
371
372	u32 cap; /* working copy of CAP register */
373	u32 cap2; /* working copy of CAP2 register */
374	u32 flags; /* adapter flags */
375
376	HRESOURCE rm_adh; /* resource handle for adapter */
377	HRESOURCE rm_bars[6]; /* resource handle for MMIO and I/O BARs */
378	HRESOURCE rm_irq; /* resource handle for IRQ */
379
380	u8 bus; /* PCI bus number */
381	u8 dev_func; /* PCI device and function number */
382	u16 irq; /* interrupt number */
383
384	u32 mmio_phys; /* physical address of MMIO region */
385	u32 mmio_size; /* size of MMIO region */
386	u8 _far mmio; / pointer to this adapter's MMIO region */
387
388	u32 dma_buf_phys; /* physical address of DMA scratch buffer */
389	u8 _far dma_buf[PORT_DMA_BUF_SEGS]; / DMA scatch buffer */
390
391	P_INFO ports[AHCI_MAX_PORTS]; /* SATA ports on this adapter */
392	} AD_INFO;
393
394	/* ADD workspace in IORB (must not exceed 16 bytes) */
395	typedef struct {
396	void (ppfunc)(IORBH _far iorb); /* post-processing function */
397	void buf; / response buffer (e.g. for identify cmds) */
398	ULONG timer; /* timer for timeout procesing */
399	USHORT blocks; /* number of blocks to be transferred */
400	unsigned processing : 1; /* IORB is being processd */
401	unsigned idempotent : 1; /* IORB is idempotent (can be retried) */
402	unsigned queued_hw : 1; /* IORB has been queued to hardware */
403	unsigned no_ncq : 1; /* must not use native command queuing */
404	unsigned is_ncq : 1; /* should use native command queueing */
405	unsigned complete : 1; /* IORB has completed processing */
406	unsigned unaligned : 1; /* unaligned S/G; need to use transfer buffer */
407	unsigned retries : 2; /* number of retries for this command */
408	unsigned cmd_slot : 5; /* AHCI command slot for this IORB */
409	} ADD_WORKSPACE;
410
411	/* sg_memcpy() direction */
412	typedef enum {
413	SG_TO_BUF, /* copy from S/G list to buffer */
414	BUF_TO_SG /* copy from buffer to S/G list */
415	} SG_MEMCPY_DIRECTION;
416
417	/* Define the size of a disk name. Disk Names are user defined names given to physical disk drives in the system. */
418	#define DLA_TABLE_SIGNATURE1 0x424D5202L
419	#define DLA_TABLE_SIGNATURE2 0x44464D50L
420	#define DISK_NAME_SIZE 20
421
422	typedef struct _DLA_Table_Sector { /* DTS */
423	ULONG DLA_Signature1; /* The magic signature (part 1) of a Drive Letter Assignment Table. */
424	ULONG DLA_Signature2; /* The magic signature (part 2) of a Drive Letter Assignment Table. */
425	ULONG DLA_CRC; /* The 32 bit CRC for this sector. Calculated assuming that this field and all unused space in the sector is 0. */
426	ULONG Disk_Serial_Number; /* The serial number assigned to this disk. */
427	ULONG Boot_Disk_Serial_Number;/* The serial number of the disk used to boot the system. This is for conflict resolution when multiple volumes
428	want the same drive letter. Since LVM.EXE will not let this situation happen, the only way to get this situation
429	is for the disk to have been altered by something other than LVM.EXE, or if a disk drive has been moved from one
430	machine to another. If the drive has been moved, then it should have a different Boot_Disk_Serial_Number. Thus,
431	we can tell which disk drive is the "foreign" drive and therefore reject its claim for the drive letter in question.
432	If we find that all of the claimaints have the same Boot_Disk_Serial_Number, then we must assign drive letters on
433	a first come, first serve basis. */
434	ULONG Install_Flags; /* Used by the Install program. */
435	ULONG Cylinders;
436	ULONG Heads_Per_Cylinder;
437	ULONG Sectors_Per_Track;
438	char Disk_Name[DISK_NAME_SIZE]; /* The name assigned to the disk containing this sector. */
439	UCHAR Reboot; /* For use by Install. Used to keep track of reboots initiated by install. */
440	BYTE Reserved[3]; /* Alignment. */
441	/* These are the four entries which correspond to the entries in the partition table. */
442	} DLA_Table_Sector, *PDLA_Table_Sector;
443
444	/* -------------------------- function prototypes -------------------------- */
445
446	/* init.asm */
447	extern u32 _cdecl readl (void _far *addr);
448	extern u32 _cdecl writel (void _far *addr, u32 val);
449	extern void _far * _cdecl memcpy (void _far v_dst, void _far v_src, int len);
450	extern void _far * _cdecl memset (void _far *p, int ch, size_t len);
451	extern void _cdecl _far restart_hook (void);
452	extern void _cdecl _far reset_hook (void);
453	extern void _cdecl _far engine_hook (void);
454	extern void _cdecl _far asm_krnl_exit (void);
455	extern void _cdecl udelay (u16 microseconds);
456
457	/* os2ahci.c */
458	extern USHORT init_drv (RPINITIN _far *req);
459	extern USHORT gen_ioctl (RP_GENIOCTL _far *ioctl);
460	extern USHORT char_dev_input (RP_RWV _far *rwrb);
461	extern USHORT exit_drv (int func);
462	extern USHORT sr_drv (int func);
463	extern void _cdecl _far _loadds add_entry (IORBH _far *iorb);
464	extern void trigger_engine (void);
465	extern int trigger_engine_1 (void);
466	extern void send_iorb (IORBH _far *iorb);
467	extern void iocc_configuration (IORBH _far *iorb);
468	extern void iocc_device_control (IORBH _far *iorb);
469	extern void iocc_unit_control (IORBH _far *iorb);
470	extern void iocm_device_table (IORBH _far *iorb);
471	extern void iocc_geometry (IORBH _far *iorb);
472	extern void iocc_execute_io (IORBH _far *iorb);
473	extern void iocc_unit_status (IORBH _far *iorb);
474	extern void iocc_adapter_passthru (IORBH _far *iorb);
475	extern void iorb_queue_add (IORB_QUEUE _far queue, IORBH _far iorb);
476	extern int iorb_queue_del (IORB_QUEUE _far queue, IORBH _far iorb);
477	extern void iorb_seterr (IORBH _far *iorb, USHORT error_code);
478	extern void iorb_done (IORBH _far *iorb);
479	extern void iorb_complete (IORBH _far *iorb);
480	extern void iorb_requeue (IORBH _far *iorb);
481	extern void aws_free (ADD_WORKSPACE _far *aws);
482	extern void lock_adapter (AD_INFO *ai);
483	extern void unlock_adapter (AD_INFO *ai);
484	extern void _cdecl _far timeout_callback (ULONG timer_handle, ULONG p1, ULONG p2);
485	extern void _cdecl _far reset_watchdog (ULONG timer_handle, ULONG p1, ULONG p2);
486
487	/* ahci.c */
488	extern int ahci_save_bios_config (AD_INFO *ai);
489	extern int ahci_restore_bios_config (AD_INFO *ai);
490	extern int ahci_restore_initial_config (AD_INFO *ai);
491	extern AHCI_PORT_CFG ahci_save_port_config (AD_INFO ai, int p);
492	extern void ahci_restore_port_config (AD_INFO *ai, int p,
493	AHCI_PORT_CFG *pc);
494	extern int ahci_enable_ahci (AD_INFO *ai);
495	extern int ahci_scan_ports (AD_INFO *ai);
496	extern int ahci_complete_init (AD_INFO *ai);
497	extern int ahci_reset_port (AD_INFO *ai, int p, int ei);
498	extern int ahci_start_port (AD_INFO *ai, int p, int ei);
499	extern void ahci_start_fis_rx (AD_INFO *ai, int p);
500	extern void ahci_start_engine (AD_INFO *ai, int p);
501	extern int ahci_stop_port (AD_INFO *ai, int p);
502	extern int ahci_stop_fis_rx (AD_INFO *ai, int p);
503	extern int ahci_stop_engine (AD_INFO *ai, int p);
504	extern int ahci_port_busy (AD_INFO *ai, int p);
505	extern void ahci_exec_iorb (IORBH _far *iorb, int ncq_capable,
506	int (func)(IORBH _far , int));
507	extern void ahci_exec_polled_iorb (IORBH _far *iorb,
508	int (func)(IORBH _far , int),
509	ULONG timeout);
510	extern int ahci_exec_polled_cmd (AD_INFO *ai, int p, int d,
511	int timeout, int cmd, ...);
512	extern int ahci_set_dev_idle (AD_INFO *ai, int p, int d, int idle);
513	extern int ahci_flush_cache (AD_INFO *ai, int p, int d);
514
515	extern int ahci_intr (u16 irq);
516	extern void ahci_port_intr (AD_INFO *ai, int p);
517	extern void ahci_error_intr (AD_INFO *ai, int p, u32 irq_stat);
518
519	extern void ahci_get_geometry (IORBH _far *iorb);
520	extern void ahci_unit_ready (IORBH _far *iorb);
521	extern void ahci_read (IORBH _far *iorb);
522	extern void ahci_verify (IORBH _far *iorb);
523	extern void ahci_write (IORBH _far *iorb);
524	extern void ahci_execute_cdb (IORBH _far *iorb);
525	extern void ahci_execute_ata (IORBH _far *iorb);
526	extern void ahci_dump_host_regs(AD_INFO *ai, int bios_regs);
527	extern void ahci_dump_port_regs(AD_INFO *ai, int p);
528	extern int ahci_reset_controller(AD_INFO *ai);
529
530	/* libc.c */
531	extern void init_libc (void);
532	extern void init_com (long BaudRate);
533	extern int vsprintf (char _far buf, const char fmt, va_list va);
534	extern int sprintf (char _far buf, const char fmt, ...);
535	extern void vfprintf (const char *fmt, va_list va);
536	extern void _cdecl printf (const char *fmt, ...);
537	extern void _cdecl printf_nts (const char *fmt, ...);
538	extern void cprintf (const char *fmt, ...);
539	extern void phex (const void _far p, int len, const char fmt, ...);
540	extern size_t strlen (const char _far *s);
541	extern char _far strcpy (char _far dst, const char _far *src);
542	extern int memcmp (void _far p1, void _far p2, size_t len);
543	extern void sg_memcpy (SCATGATENTRY _far *sg_list, USHORT sg_cnt,
544	ULONG sg_off, void _far *buf, USHORT len,
545	SG_MEMCPY_DIRECTION dir);
546	extern long strtol (const char _far *buf,
547	const char _far * _far *ep, int base);
548	extern void *malloc (size_t len);
549	extern void free (void *ptr);
550	extern ULONG virt_to_phys (void _far *ptr);
551	//NOT_USED extern void mdelay_cal (void);
552	//NOT_USED extern void mdelay (u32 millies);
553	extern void msleep (u32 millies);
554	extern void panic (char *msg);
555	extern int disable (void);
556	extern void enable (void);
557	extern void timer_init(TIMER far *pTimer, u32 Milliseconds);
558	extern int timer_check_and_block(TIMER far *pTimer);
559
560	/* trace.c */
561	extern void trace_init (u16);
562	extern void trace_exit (void);
563	extern void trace_write (u8 _far *s, int len);
564	extern u16 trace_read (u8 _far *buf, u16 cb_buf);
565	extern u16 trace_char_dev(RP_RWV _far *rwrb);
566	extern void build_user_info(void);
567
568	/* pci.c */
569	extern int add_pci_id (u16 vendor, u16 device);
570	extern void scan_pci_bus (void);
571	extern int pci_enable_int (UCHAR bus, UCHAR dev_func);
572	extern void pci_hack_virtualbox(void);
573	extern char *vendor_from_id (u16 vendor);
574	extern char *device_from_id (u16 device);
575	UCHAR pci_read_conf (UCHAR bus, UCHAR dev_func, UCHAR indx,
576	UCHAR size, ULONG _far *val);
577	UCHAR pci_write_conf (UCHAR bus, UCHAR dev_func, UCHAR indx, UCHAR size,
578	ULONG val);
579
580	/* ctxhook.c */
581	extern void _cdecl restart_ctxhook (ULONG parm);
582	extern void _cdecl reset_ctxhook (ULONG parm);
583	extern void _cdecl engine_ctxhook (ULONG parm);
584
585	/* apm.c */
586	extern void apm_init (void);
587	extern void suspend (void);
588	extern void resume (void);
589
590	/* ioctl.c */
591	extern USHORT ioctl_get_devlist (RP_GENIOCTL _far *ioctl);
592	extern USHORT ioctl_passthrough (RP_GENIOCTL _far *ioctl);
593	extern USHORT ioctl_gen_dsk (RP_GENIOCTL _far *ioctl);
594	extern USHORT ioctl_smart (RP_GENIOCTL _far *ioctl);
595
596
597	/* ---------------------------- global variables --------------------------- */
598
599	extern char _cdecl end_of_data; /* label at the end of all data segments */
600	extern void _cdecl _near end_of_code(); /* label at the end of all code segments */
601
602	extern int debug; /* if != 0, print debug messages to COM1 */
603	extern int thorough_scan; /* if != 0, perform thorough PCI scan */
604	extern int init_reset; /* if != 0, reset ports during init */
605	extern int force_write_cache; /* if != 0, force write cache */
606	extern int verbosity; /* if != 0, show some info during boot */
607	extern int use_lvm_info;
608	extern int wrap_trace_buffer;
609
610	extern HDRIVER rm_drvh; /* resource manager driver handle */
611	extern USHORT add_handle; /* adapter device driver handle */
612	extern UCHAR timer_pool[]; /* timer pool */
613	extern char drv_name[]; /* driver name as string ("OS2AHCI") */
614
615	extern PCI_ID pci_ids[]; /* SATA adapter PCI IDs */
616	extern ULONG drv_lock; /* driver-level spinlock */
617	extern ULONG com_lock; /* debug log spinlock */
618	extern IORB_QUEUE driver_queue; /* driver-level IORB queue */
619	extern AD_INFO ad_infos[]; /* adapter information list */
620	extern int ad_info_cnt; /* number of entries in ad_infos[] */
621	extern u16 ad_ignore; /* bitmap with adapters to be ignored */
622	extern int init_complete; /* if != 0, initialization has completed */
623	extern int suspended; /* indicates if the driver is suspended */
624	extern int resume_sleep_flag;
625
626	extern u16 com_base; /* debug COM port base address */
627
628	/* port restart context hook and input data */
629	extern ULONG restart_ctxhook_h;
630	extern volatile u32 ports_to_restart[MAX_AD];
631
632	/* port reset context hook and input data */
633	extern ULONG reset_ctxhook_h;
634	extern ULONG th_reset_watchdog;
635	extern volatile u32 ports_to_reset[MAX_AD];
636	extern IORB_QUEUE abort_queue;
637
638	/* trigger engine context hook and input data */
639	extern ULONG engine_ctxhook_h;
640
641	/* apapter/port-specific options saved when parsing the command line */
642	extern u8 emulate_scsi[MAX_AD][AHCI_MAX_PORTS];
643	extern u8 enable_ncq[MAX_AD][AHCI_MAX_PORTS];
644	extern u8 link_speed[MAX_AD][AHCI_MAX_PORTS];
645	extern u8 link_power[MAX_AD][AHCI_MAX_PORTS];
646	extern u8 track_size[MAX_AD][AHCI_MAX_PORTS];
647

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