Article

Active leakage power optimization for FPGAs

Authors:

Jason H. Anderson,

Tim TuanAuthors Info & Claims

FPGA '04: Proceedings of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arrays

Pages 33 - 41

https://doi.org/10.1145/968280.968287

Published: 22 February 2004 Publication History

Abstract

We consider active leakage power dissipation in FPGAs and present a "no cost" approach for active leakage reduction. It is well-known that the leakage power consumed by a digital CMOS circuit depends strongly on the state of its inputs. Our leakage reduction technique leverages a fundamental property of basic FPGA logic elements (look-up-tables) that allows a logic signal in an FPGA design to be interchanged with its complemented form without any area or delay penalty. We apply this property to select polarities for logic signals so that FPGA hardware structures spend the majority of time in low leakage states. In an experimental study, we optimize active leakage power in circuits mapped into a state-of-the-art 90nm commercial FPGA. Results show that the proposed approach reduces active leakage by 25%, on average.

References

[1]

A. Abdollahi, F. Fallah, and M. Pedram. Runtime mechanisms for leakage current reduction in CMOS VLSI circuits. In International Symposium on Low-Power Electronics and Design, pages 213--218, 2002.

Digital Library

[2]

M. Anis, S. Areibi, M. Mahmoud, and M. Elmasry. Dynamic and leakage power reduction in MTCMOS circuits using an automated efficient gate clustering technique. In ACM/IEEE Design Automation Conference, pages 480--485, 2002.

Digital Library

[3]

M.A. Cirit. Estimating dynamic power consumption of CMOS circuits. In IEEE International Conference on Computer-Aided Design, pages 534--537, 1987.

[4]

V. George and J. Rabaey. Low-Energy FPGAs: Architecture and Design. Kluwer Academic Publishers, Boston, MA, 2001.

Digital Library

[5]

R.S. Guindi and F.N. Najm. Design techniques for gate-leakage reduction in CMOS circuits. In IEEE International Symposium on Quality Electronic Design, pages 61--65, 2003.

Digital Library

[6]

J.P. Halter and F.N. Najm. A gate level leakage power reduction method for ultra-low-power CMOS circuits. In IEEE Custom Integrated Circuits Conference, pages 475--478, 1997.

[7]

M.C. Johnson, D. Somasekhar, L.-Y. Choiu, and K. Roy. Leakage control with efficient use of transistor stacks in single threshold CMOS. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 10(1):1--5, February 2002.

Digital Library

[8]

J. Kao, S. Narendra, and A. Chandrakasan. Subthreshold leakage modeling and reduction techniques. In IEEE International Conference on Computer-Aided Design, pages 141--148, 2002.

Digital Library

[9]

A. Keshavarzi, S. Ma, et. al. Effectiveness of reverse body bias for leakage control in scaled dual Vt CMOS ICs. In ACM/IEEE International Symposium on Low Power Electronics and Design, pages 207--211, 2001.

Digital Library

[10]

C.H. Kim, J.-J. Kim, S. Mukhopadhyay, and K. Roy. A forward body-biased low-leakage SRAM cache: Device and architecture considerations. In ACM/IEEE International Symposium on Low-Power Electronics and Design, pages 6--9, 2003.

Digital Library

[11]

C.H. Kim and K. Roy. Dynamic Vth scaling scheme for active leakage power reduction. In IEEE Design, Automation and Test in Europe Conference, pages 163--167, 2002.

Digital Library

[12]

G. Lemieux. Design of interconnection networks for programmable logic devices. In Ph.D. Thesis. Department of Electrical and Computer Engineering, University of Toronto, 2003.

[13]

G. Lemieux and D. Lewis. Circuit design of routing switches. In ACM/SIGDA International Symposium on Field Programmable Gate Arrays, pages 19--28, 2002.

Digital Library

[14]

D. Lewis, V. Betz, D. Jefferson, A. Lee, C. Lane, P. Leventis, et. al. The Stratix routing and logic architecture. In ACM/SIGDA International Symposium on Field Programmable Gate Arrays, pages 12--20, 2003.

Digital Library

[15]

S.M. Martin, K. Flautner, T. Mudge, and D. Blaauw. Combined dynamic voltage scaling and adaptive body biasing for lower power microprocessors under dynamic workloads. In IEEE International Conference on Computer-Aided Design, pages 721--725, 2002.

Digital Library

[16]

S. Narendra, S. Borkar, V. De, D. Antoniadis, and A. Chandrakasan. Scaling of stack effect and its application for leakage reduction. In IEEE International Symposium on Low-Power Electronics and Design, pages 195--200, 2001.

Digital Library

[17]

M. Nemani and F. N. Najm. High-level area and power estimation for VLSI circuits. IEEE Transactions on Computer Aided Design, 18(6):697--713, June 1999.

Digital Library

[18]

K.W. Poon, A. Yan, and S. J. E. Wilton. A flexible power model for FPGAs. In International Conference on Field-Programmable Logic and Applications, pages 312--321, 2002.

Digital Library

[19]

K. Roy, S. Mukhopadhyay, and H. Mahmoodi-Meimand. Leakage current mechanisms and leakage reduction techniques in deep-submicrometer CMOS circuits. In Proceedings of the IEEE, pages 305--327, February 2003.

[20]

T. Sakurai. Minimizing power across multiple technology and design levels. In IEEE International Conference on Computer-Aided Design, pages 24--27, 2002.

Digital Library

[21]

L. Shang, A. Kaviani, and K. Bathala. Dynamic power consumption the Virtex-II FPGA family. In ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, pages 157--164, 2002.

Digital Library

[22]

S. Sirichotiyakul, T. Edwards, C. Oh, R. Panda, and D. Blaauw. Duet: An accurate leakage estimation and optimization tool for dual-Vt circuits. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 10(2):79--90, April 2002.

Digital Library

[23]

T. Tuan and B. Lai. Leakage power analysis of a 90nm FPGA. In IEEE Custom Integrated Circuits Conference, pages 57--60, 2003.

[24]

K. Usami, N. Kawabe, M. Koizumi, K. Seta, and T. Furusawa. Automated selective multi-threshold design for ultra-low standby applications. In IEEE International Conference on Low-Power Electronics and Design, pages 202--206, 2002.

Digital Library

[25]

Xilinx, Inc., San Jose, CA. Spartan-3 FPGA Data Sheet, 2003.

[26]

Xilinx, Inc., San Jose, CA. Virtex II PRO FPGA Data Sheet, 2003.

[27]

G. Yeap. Practical Low Power Digital VLSI Design. Kluwer Academic Publishers, Boston, MA, 1998.

Digital Library

Cited By

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Firdous ARajan B(2014)Comparative analysis of LUT design In FPGAInternational Conference on Information Communication and Embedded Systems (ICICES2014)10.1109/ICICES.2014.7034160(1-3)Online publication date: Feb-2014
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Index Terms

Active leakage power optimization for FPGAs
1. Hardware
  1. Electronic design automation
    1. Physical design (EDA)

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cover image ACM Conferences

FPGA '04: Proceedings of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arrays

February 2004

266 pages

ISBN:1581138296

DOI:10.1145/968280

General Chair:
Russ Tessier
University of Massachusetts -- Amherst
,
Program Chair:
Herman Schmit
Everychip, Inc.

Copyright © 2004 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Publication History

Published: 22 February 2004

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FPGA04

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FPGA04: ACM/SIGDA International Symposium on Field Programmable Gate Arrays 2004

February 22 - 24, 2004

California, Monterey, USA

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Overall Acceptance Rate 125 of 627 submissions, 20%

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Gong JLi M(2023)Design of Multi-circuit Motor Control System based on Fabric Defect Detection DeviceFrontiers in Computing and Intelligent Systems10.54097/fcis.v4i2.102104:2(78-80)Online publication date: 26-Jun-2023
https://doi.org/10.54097/fcis.v4i2.10210
Firdous ARajan B(2014)Comparative analysis of LUT design In FPGAInternational Conference on Information Communication and Embedded Systems (ICICES2014)10.1109/ICICES.2014.7034160(1-3)Online publication date: Feb-2014
https://doi.org/10.1109/ICICES.2014.7034160
Qin JWang WXiao CLu YLin XWang H(2013)Asymmetric signature schemes for efficient exact edit similarity query processingACM Transactions on Database Systems10.1145/2508020.250802338:3(1-44)Online publication date: 5-Sep-2013
https://dl.acm.org/doi/10.1145/2508020.2508023
Colazzo DGhelli GPardini LSartiani C(2013)Almost-linear inclusion for XML regular expression typesACM Transactions on Database Systems10.1145/2508020.250802238:3(1-45)Online publication date: 5-Sep-2013
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Bonifati AGoodfellow MManolescu ISileo D(2013)Algebraic incremental maintenance of XML viewsACM Transactions on Database Systems10.1145/2508020.250802138:3(1-45)Online publication date: 5-Sep-2013
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Karvounarakis GGreen TIves ZTannen V(2013)Collaborative data sharing via update exchange and provenanceACM Transactions on Database Systems10.1145/250012738:3(1-42)Online publication date: 5-Sep-2013
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Manorama Khandelwal SAkashe S(2013)Design of a FinFET based inverter using MTCMOS and SVL leakage reduction technique2013 Students Conference on Engineering and Systems (SCES)10.1109/SCES.2013.6547489(1-6)Online publication date: Apr-2013
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Marconi TBertels KGaydadjiev G(2013)A novel productivity-driven logic element for field-programmable devicesInternational Journal of Electronics10.1080/00207217.2013.794489101:6(731-762)Online publication date: 9-Jul-2013
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Bsoul ADueck SWilton S(2012)Runtime-Controlled Energy Reduction Techniques for FPGAsGreen Communications10.1201/b13083-3(3-27)Online publication date: 8-Nov-2012
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