research-article

Duet: an accurate leakage estimation and optimization tool for dual-V_t circuits

Authors:

Supamas Sirichotiyakul,

Rajendran Panda,

David BlaauwAuthors Info & Claims

IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Volume 10, Issue 2

Pages 79 - 90

https://doi.org/10.1109/92.994980

Published: 22 April 2002 Publication History

Abstract

We present a new approach for the estimation and optimization of standby power dissipation in large MOS digital circuits. We first introduce a new approach for accurate and efficient calculation of the average standby or leakage current in large digital circuits by introducing the concepts of "dominant leakage states" and the use of state probabilities. Combined with graph reduction techniques and simplified nonlinear simulation, our method achieves speedups of three to four orders of magnitude over exhaustive SPICE simulations while maintaining very good accuracy. The leakage current calculation is then utilized in a new leakage and performance optimization algorithm for circuits using dual V_t processes. Our approach is the first to consider the assignment of both the V_t and the width of a transitor, simultaneously. Our optimization approach was able to obtain 81-100% of the performance achievable with all low V_t transistors, but with 1/3 to 1/6 the standby current. We also show that knowledge of the standby state of the device enhances the leakage/performance tradeoff.

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Cited By

Bajpai PPandey NGupta KPanda J(2019)LECTOR incorporated differential cascode voltage swing logic (L-DCVSL)Analog Integrated Circuits and Signal Processing10.1007/s10470-019-01466-2100:1(221-234)Online publication date: 1-Jul-2019
https://dl.acm.org/doi/10.1007/s10470-019-01466-2
Lorenzo RChaudhury S(2017)LCNT-an approach to minimize leakage power in CMOS integrated circuitsMicrosystem Technologies10.1007/s00542-016-2996-y23:9(4245-4253)Online publication date: 1-Sep-2017
https://dl.acm.org/doi/10.1007/s00542-016-2996-y
Wang NZhong WHao CChen SYoshimura TZhu Y(2016)Leakage-Power-Aware Scheduling With Dual-Threshold Voltage DesignIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2016.253522124:10(3067-3079)Online publication date: 1-Oct-2016
https://dl.acm.org/doi/10.1109/TVLSI.2016.2535221
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Index Terms

Duet: an accurate leakage estimation and optimization tool for dual-V_t circuits
1. Hardware
  1. Hardware validation
  2. Integrated circuits

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cover image IEEE Transactions on Very Large Scale Integration (VLSI) Systems

IEEE Transactions on Very Large Scale Integration (VLSI) Systems Volume 10, Issue 2

April 2002

122 pages

ISSN:1063-8210

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Copyright © 2002.

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IEEE Educational Activities Department

United States

Publication History

Published: 22 April 2002

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Cited By

Bajpai PPandey NGupta KPanda J(2019)LECTOR incorporated differential cascode voltage swing logic (L-DCVSL)Analog Integrated Circuits and Signal Processing10.1007/s10470-019-01466-2100:1(221-234)Online publication date: 1-Jul-2019
https://dl.acm.org/doi/10.1007/s10470-019-01466-2
Lorenzo RChaudhury S(2017)LCNT-an approach to minimize leakage power in CMOS integrated circuitsMicrosystem Technologies10.1007/s00542-016-2996-y23:9(4245-4253)Online publication date: 1-Sep-2017
https://dl.acm.org/doi/10.1007/s00542-016-2996-y
Wang NZhong WHao CChen SYoshimura TZhu Y(2016)Leakage-Power-Aware Scheduling With Dual-Threshold Voltage DesignIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2016.253522124:10(3067-3079)Online publication date: 1-Oct-2016
https://dl.acm.org/doi/10.1109/TVLSI.2016.2535221
Puri RChoudhury MQian HZiegler MXie YKarnik TKhellah MMehra R(2014)Bridging high performance and low power in processor designProceedings of the 2014 international symposium on Low power electronics and design10.1145/2627369.2631642(183-188)Online publication date: 11-Aug-2014
https://dl.acm.org/doi/10.1145/2627369.2631642
Mok SLee JGupta P(2013)Discrete sizing for leakage power optimization in physical designACM Transactions on Design Automation of Electronic Systems10.1145/2390191.239020618:1(1-11)Online publication date: 16-Jan-2013
https://dl.acm.org/doi/10.1145/2390191.2390206
Gupta TKhare K(2013)Lector with Footed-Diode InverterCircuits, Systems, and Signal Processing10.1007/s00034-013-9615-232:6(2707-2722)Online publication date: 1-Dec-2013
https://dl.acm.org/doi/10.1007/s00034-013-9615-2
Rahman MSechen CRosenstiel WMacii E(2012)Post-synthesis leakage power minimizationProceedings of the Conference on Design, Automation and Test in Europe10.5555/2492708.2492732(99-104)Online publication date: 12-Mar-2012
https://dl.acm.org/doi/10.5555/2492708.2492732
Kahng AKang SHu JKoh C(2012)Construction of realistic gate sizing benchmarks with known optimal solutionsProceedings of the 2012 ACM international symposium on International Symposium on Physical Design10.1145/2160916.2160949(153-160)Online publication date: 25-Mar-2012
https://dl.acm.org/doi/10.1145/2160916.2160949
Kahng AKang SKumar RSartori JLin Y(2010)Slack redistribution for graceful degradation under voltage overscalingProceedings of the 2010 Asia and South Pacific Design Automation Conference10.5555/1899721.1899911(825-831)Online publication date: 18-Jan-2010
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Kahng AKang SKumar RSartori JSapatnekar S(2010)Recovery-driven designProceedings of the 47th Design Automation Conference10.1145/1837274.1837481(825-830)Online publication date: 13-Jun-2010
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