Guest editorial: low-power electronics and design
First Page of the Article
Energy-efficient noise-tolerant dynamic styles for scaled-down CMOS and MTCMOS technologies
A new high-speed Domino circuit, called HS-Domino has been developed. HS-Domino resolves the tradeoff between performance and reliability in conventional CD-Dominion logic while dissipating low dynamic power with minimal area overhead. HS-Domino, ...
Duet: an accurate leakage estimation and optimization tool for dual-Vt circuits
We present a new approach for the estimation and optimization of standby power dissipation in large MOS digital circuits. We first introduce a new approach for accurate and efficient calculation of the average standby or leakage current in large digital ...
Analysis of dual-Vt SRAM cells with full-swing single-ended bit line sensing for on-chip cache
- Faith Hamzaoglu,
- Yibin Ye,
- Ali Keshavarzi,
- Kevin Zhang,
- Siva Narendra,
- Shekhar Borkar,
- Mircea Stan,
- Vivek De
This paper compares different high-Vt and dual Vt design choices for a large on-chip cache with single-ended sensing in a 0.13 technology generation. The analysis shows that the best design is the one using a dual-Vt cell, with minimum channel length ...
Layout-driven memory synthesis for embedded systems-on-chip
Memory-processor integration offers new opportunities for reducing the energy of a system. In the case of embedded systems, where memory access patterns can typically be profiled at design time, one solution consists of mapping the most frequently ...
Memory power models for multilevel power estimation and optimization
Storage cost is a major factor in the total power consumption of digital signal processing circuits. Power models for on-chip memories are consequently an important ingredient in power aware design flows for estimation and optimization. Unfortunately, ...
Power-optimal encoding for a DRAM address bus
This paper presents an irredundant encoding technique to minimize the switching activity on a multiplexed Dynamic RAM (DRAM) address bus. The DRAM switching activity can be classified either as external (between two consecutive addresses) or internal (...
Power-aware operating systems for interactive systems
Many portable systems deploy operating systems (OS) to support versatile functionality and to manage resources, including power. This paper presents a new approach for using OS to reduce the power consumption of IO devices in interactive systems. Low-...
Energy scalable system design
We introduce the notion of energy-scalable system design. The principal idea is to maximize computational quality for a given energy constraint at all levels of the system hierarchy. The desirable energy-quality (E-Q) characteristics of systems are ...
Cycle-accurate energy measurement and characterization with a case study of the ARM7TDMI
Energy characterization is the basis for high-level energy reduction. Measurement-based characterization is accurate and independent of model availability and is thus suitable for commercial off-the-shelf (COTS) components, but conventional measurement ...
Power estimation methods for analog circuits for architectural exploration of integrated systems
This paper describes methods for analog-power estimation and practically applies them to two different classes of analog circuits. Such power estimators, that return a power estimate given only a block's specification values without knowing its detailed ...
A low-power high-speed class-AB buffer amplifier for flat-panel-display application
A low-power, high-speed, but with a large input dynamic range and output swing class-AB output buffer circuit, which is suitable for the flat-panel display application, is proposed. The circuit employs an elegant comparator to sense the transients of ...
On the design of low-voltage, low-power CMOS analog multipliers for RF applications
Novel low-voltage, low-power techniques in the design of portable wireless communication systems are required. Two system examples of low-power analog multipliers operating from a 1.2 V supply are presented. These proposed structures achieve the ...
Guest editorial - system-level interconnect prediction
First Page of the Article
Toward better wireload models in the presence of obstacles
Wirelength estimation techniques typically contain a site density function that enumerates all possible path sites for each wirelength in an architecture and an occupation probability function that assigns a probability to each of these paths to be ...
