Article

NoCIC: a spice-based interconnect planning tool emphasizing aggressive on-chip interconnect circuit methods

Authors:

Vishak Venkatraman,

Andrew Laffely,

Hempraveen Kukkamalla,

Wayne BurlesonAuthors Info & Claims

SLIP '04: Proceedings of the 2004 international workshop on System level interconnect prediction

Pages 69 - 75

https://doi.org/10.1145/966747.966762

Published: 14 February 2004 Publication History

Abstract

Performance and power of on-chip interconnects in the nanometer realm have been an increasing source of concern to designers. Network-on-Chip (NoC)structures have been proposed as a solution to achieve efficient and reliable communication. Even with the regularity of NoC structures, it is important for designers to acknowledge the physical layer interconnect issues to plan and quantify achievable performance. In this paper we present a spice-based tool: No-CIC: Network-on-Chip Interconnect Calculator, which enables NoC designers to assess the impact of interconnect circuit designs and understand the tradeoffs involved to achieve better a priori planning. NoCIC determines the interconnect performance and power based on select NoC and circuit parameters. The effects of each parameter on the interconnect performance and power are expressed through various two-dimensional and three-dimensional plots.

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Cited By

Viswanathan KMurugan P(2013)Analysis of multilayer and multifunctional circuit in processorInternational Conference on Advanced Nanomaterials & Emerging Engineering Technologies10.1109/ICANMEET.2013.6609316(485-487)Online publication date: Jul-2013
https://doi.org/10.1109/ICANMEET.2013.6609316
English TPopovici EMarculescu RKishinevsky MGinosar RChatha K(2011)Interconnect physical analyser (IPAA) applied to the design of scalable Network-on-Chip interconnect for cryptographic acceleratorsProceedings of the Fifth ACM/IEEE International Symposium on Networks-on-Chip10.1145/1999946.1999982(225-232)Online publication date: 1-May-2011
https://dl.acm.org/doi/10.1145/1999946.1999982
Atghiaee AMasoumi N(2011)A Predictive and Accurate Interconnect Density FunctionIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2010.205394619:9(1704-1717)Online publication date: 1-Sep-2011
https://dl.acm.org/doi/10.1109/TVLSI.2010.2053946
Show More Cited By

Index Terms

NoCIC: a spice-based interconnect planning tool emphasizing aggressive on-chip interconnect circuit methods
1. Hardware
  1. Integrated circuits

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cover image ACM Conferences

SLIP '04: Proceedings of the 2004 international workshop on System level interconnect prediction

February 2004

111 pages

ISBN:1581138180

DOI:10.1145/966747

General Chair:
Lou Scheffer
Cadence, USA
,
Program Chair:
Igor Markov
University of Michigan, USA

Copyright © 2004 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Publication History

Published: 14 February 2004

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SLIP04: International Workshop on System Level Interconnect Prediction

February 14 - 15, 2004

Paris, France

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Overall Acceptance Rate 6 of 8 submissions, 75%

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Cited By

Viswanathan KMurugan P(2013)Analysis of multilayer and multifunctional circuit in processorInternational Conference on Advanced Nanomaterials & Emerging Engineering Technologies10.1109/ICANMEET.2013.6609316(485-487)Online publication date: Jul-2013
https://doi.org/10.1109/ICANMEET.2013.6609316
English TPopovici EMarculescu RKishinevsky MGinosar RChatha K(2011)Interconnect physical analyser (IPAA) applied to the design of scalable Network-on-Chip interconnect for cryptographic acceleratorsProceedings of the Fifth ACM/IEEE International Symposium on Networks-on-Chip10.1145/1999946.1999982(225-232)Online publication date: 1-May-2011
https://dl.acm.org/doi/10.1145/1999946.1999982
Atghiaee AMasoumi N(2011)A Predictive and Accurate Interconnect Density FunctionIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2010.205394619:9(1704-1717)Online publication date: 1-Sep-2011
https://dl.acm.org/doi/10.1109/TVLSI.2010.2053946
Kornaros G(2010)NCXplore: a design space exploration framework of temporal encoding for on-chip serial interconnectsInternational Journal of High Performance Systems Architecture10.1504/IJHPSA.2010.0345392:3/4(177-186)Online publication date: 1-Aug-2010
https://dl.acm.org/doi/10.1504/IJHPSA.2010.034539
Liang XCanal RWei GBrooks D(2007)Process Variation Tolerant 3T1D-Based Cache ArchitecturesProceedings of the 40th Annual IEEE/ACM International Symposium on Microarchitecture10.1109/MICRO.2007.33(15-26)Online publication date: 1-Dec-2007
https://dl.acm.org/doi/10.1109/MICRO.2007.33
Cornelius CBohn HTimmermann D(2006)Service-oriented Approaches for the Operation of large on-chip Networks2006 NORCHIP10.1109/NORCHP.2006.329206(183-186)Online publication date: Nov-2006
https://doi.org/10.1109/NORCHP.2006.329206
Xu SVenkatraman VBurleson W(2006)Energy-Aware Differential Current Sensing for Global On-Chip Interconnects2006 49th IEEE International Midwest Symposium on Circuits and Systems10.1109/MWSCAS.2006.382163(718-722)Online publication date: Aug-2006
https://doi.org/10.1109/MWSCAS.2006.382163
Ost LMello APalma JMoraes FCalazans NTang T(2005)MAIAProceedings of the 2005 Asia and South Pacific Design Automation Conference10.1145/1120725.1120741(49-52)Online publication date: 18-Jan-2005
https://dl.acm.org/doi/10.1145/1120725.1120741
Burleson WXu S(2005)Digital Systems Design with ASIC and FPGAProceedings of the 2005 IEEE International Conference on Microelectronic Systems Education10.1109/MSE.2005.27(3-4)Online publication date: 12-Jun-2005
https://dl.acm.org/doi/10.1109/MSE.2005.27
Ost LMello APalma JMoraes FCalazans N(2005)MAIA - a framework for networks on chip generation and verificationProceedings of the ASP-DAC 2005. Asia and South Pacific Design Automation Conference, 2005.10.1109/ASPDAC.2005.1466128(49-52)Online publication date: 2005
https://doi.org/10.1109/ASPDAC.2005.1466128

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