article

iDEAL: Inter-router Dual-Function Energy and Area-Efficient Links for Network-on-Chip (NoC) Architectures

Authors:

Avinash Karanth Kodi,

Ashwini Sarathy,

Ahmed LouriAuthors Info & Claims

ACM SIGARCH Computer Architecture News, Volume 36, Issue 3

Pages 241 - 250

https://doi.org/10.1145/1394608.1382142

Published: 01 June 2008 Publication History

Abstract

Network-on-Chip (NoC) architectures have been adopted by a growing number of multi-core designs as a flexible and scalable solution to the increasing wire delay constraints in the deep sub-micron regime. However, the shrinking feature size limits the performance of NoCs due to power and area constraints. Research into the optimization of NoCs has shown that a reduction in the number of buffers in the NoC routers reduces the power and area overhead but degrades the network performance. In this paper, we propose iDEAL, a low-power area-efficient NoC architecture by reducing the number of buffers within the router. To overcome the performance degradation caused by the reduced buffer size, we propose to use adaptive dual-function links capable of data transmission as well as data storage when required. Simulation results for the proposed architecture show that reducing the router buffer size in half and using the adaptive dual-function links achieves nearly 40% savings in buffer power, 30% savings in overall network power and about 41% savings in the router area, with only a marginal 1-3% drop in performance. Moreover, the performance in iDEAL can be further improved by aggressive and speculative flow control techniques.

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iDEAL: Inter-router Dual-Function Energy and Area-Efficient Links for Network-on-Chip (NoC) Architectures

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Information

Published In

cover image ACM SIGARCH Computer Architecture News

ACM SIGARCH Computer Architecture News Volume 36, Issue 3

June 2008

449 pages

ISSN:0163-5964

DOI:10.1145/1394608

Issue’s Table of Contents

ISCA '08: Proceedings of the 35th Annual International Symposium on Computer Architecture
June 2008
449 pages
ISBN:9780769531748

Copyright © 2008 Authors.

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 01 June 2008

Published in SIGARCH Volume 36, Issue 3

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https://doi.org/10.1109/ICCD58817.2023.00033
Delgado-Gallardo VSandoval-Arechiga RParra-Michel R(2023)A Top-Down Modeling Approach for Networks-on-Chip Components Design: A Switch as Case StudyIEEE Access10.1109/ACCESS.2023.323527611(4412-4433)Online publication date: 2023
https://doi.org/10.1109/ACCESS.2023.3235276
Khan KPasricha SKim RSavidis ISasan AThapliyal HDeMara R(2022)RACE: A Reinforcement Learning Framework for Improved Adaptive Control of NoC Channel BuffersProceedings of the Great Lakes Symposium on VLSI 202210.1145/3526241.3530335(205-210)Online publication date: 6-Jun-2022
https://dl.acm.org/doi/10.1145/3526241.3530335
Wang KZheng HLi YLouri A(2022)SecureNoC: A Learning-Enabled, High-Performance, Energy-Efficient, and Secure On-Chip Communication Framework DesignIEEE Transactions on Sustainable Computing10.1109/TSUSC.2021.31382797:3(709-723)Online publication date: 1-Jul-2022
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Alazemi FChen LBose B(2022)Routerless networks-on-chipPower-Efficient Network-on-Chips: Design and Evaluation10.1016/bs.adcom.2021.11.002(81-116)Online publication date: 2022
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Zheng HWang KLouri ALi Z(2020)A versatile and flexible chiplet-based system design for heterogeneous manycore architecturesProceedings of the 57th ACM/EDAC/IEEE Design Automation Conference10.5555/3437539.3437654(1-6)Online publication date: 20-Jul-2020
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