research-article

Performance Analysis of Buffering Schemes in Wormhole Routers

Authors:

Younes M. Boura,

Chita R. DasAuthors Info & Claims

IEEE Transactions on Computers, Volume 46, Issue 6

Pages 687 - 694

https://doi.org/10.1109/12.600826

Published: 01 June 1997 Publication History

Abstract

Wormhole switched input-buffered and middle-buffered routers with virtual channels are analyzed in this paper. Middle buffering refers to the placement of virtual channels between the demultiplexors and multiplexors of a crossbar switch. An analytical model for multistage interconnection networks using middle-buffered switches is developed. In addition, extensive simulation is conducted to assess the performance of the two buffering techniques in different network topologies. The study demonstrates that middle buffering with virtual channels provides better performance than input buffering with virtual channels in multistage interconnection networks, two-dimensional meshes, and hypercubes.

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Cited By

Yan JWang MQin YYu Z(2023)CRAFT: Common Router Architecture for Throughput OptimizationAlgorithms and Architectures for Parallel Processing10.1007/978-981-97-0798-0_13(212-229)Online publication date: 20-Oct-2023
https://dl.acm.org/doi/10.1007/978-981-97-0798-0_13
Kodi ASarathy ALouri AWang JWakabayashi K(2009)Adaptive inter-router links for low-power, area-efficient and reliable Network-on-Chip (NoC) architecturesProceedings of the 2009 Asia and South Pacific Design Automation Conference10.5555/1509633.1509638(1-6)Online publication date: 19-Jan-2009
https://dl.acm.org/doi/10.5555/1509633.1509638
Neishaburi MZilic ZLombardi FBhanja SMassoud YBahar R(2009)Reliability aware NoC router architecture using input channel buffer sharingProceedings of the 19th ACM Great Lakes symposium on VLSI10.1145/1531542.1531658(511-516)Online publication date: 10-May-2009
https://dl.acm.org/doi/10.1145/1531542.1531658
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Index Terms

Performance Analysis of Buffering Schemes in Wormhole Routers
1. Computer systems organization
  1. Architectures
    1. Parallel architectures
      1. Interconnection architectures
2. Hardware
  1. Integrated circuits
    1. Interconnect

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Published In

cover image IEEE Transactions on Computers

IEEE Transactions on Computers Volume 46, Issue 6

June 1997

95 pages

ISSN:0018-9340

Editor:
Jane W.S. Liu
Univ. of Illinois, Urbana

Issue’s Table of Contents

Copyright © Copyright © 1997 IEEE. All Rights Reserved.

Publisher

IEEE Computer Society

United States

Publication History

Published: 01 June 1997

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Cited By

Yan JWang MQin YYu Z(2023)CRAFT: Common Router Architecture for Throughput OptimizationAlgorithms and Architectures for Parallel Processing10.1007/978-981-97-0798-0_13(212-229)Online publication date: 20-Oct-2023
https://dl.acm.org/doi/10.1007/978-981-97-0798-0_13
Kodi ASarathy ALouri AWang JWakabayashi K(2009)Adaptive inter-router links for low-power, area-efficient and reliable Network-on-Chip (NoC) architecturesProceedings of the 2009 Asia and South Pacific Design Automation Conference10.5555/1509633.1509638(1-6)Online publication date: 19-Jan-2009
https://dl.acm.org/doi/10.5555/1509633.1509638
Neishaburi MZilic ZLombardi FBhanja SMassoud YBahar R(2009)Reliability aware NoC router architecture using input channel buffer sharingProceedings of the 19th ACM Great Lakes symposium on VLSI10.1145/1531542.1531658(511-516)Online publication date: 10-May-2009
https://dl.acm.org/doi/10.1145/1531542.1531658
Javadi BAkbari MAbawajy J(2009)Multi-cluster computing interconnection network performance modeling and analysisFuture Generation Computer Systems10.1016/j.future.2008.07.01025:7(737-746)Online publication date: 1-Jul-2009
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Kodi ASarathy ALouri A(2008)iDEALACM SIGARCH Computer Architecture News10.1145/1394608.138214236:3(241-250)Online publication date: 1-Jun-2008
https://dl.acm.org/doi/10.1145/1394608.1382142
Kodi ASarathy ALouri A(2008)iDEALProceedings of the 35th Annual International Symposium on Computer Architecture10.1109/ISCA.2008.14(241-250)Online publication date: 21-Jun-2008
https://dl.acm.org/doi/10.1109/ISCA.2008.14
Javadi BAbawajy JAkbari MNahavandi S(2007)Communication network analysis of the enterprise grid systemsProceedings of the fifth Australasian symposium on ACSW frontiers - Volume 6810.5555/1274531.1274537(33-40)Online publication date: 30-Jan-2007
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Javadi BAkbari MAbawajy J(2007)Analytical communication networks model for enterprise Grid computingFuture Generation Computer Systems10.1016/j.future.2006.11.00223:6(737-747)Online publication date: 1-Jul-2007
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Javadi BAbawajy JAkbari M(2007)Analytical modeling of interconnection networks in heterogeneous multi-cluster systemsThe Journal of Supercomputing10.1007/s11227-006-0011-640:1(29-47)Online publication date: 1-Apr-2007
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Nicopoulos CPark DKim JVijaykrishnan NYousif MDas C(2006)ViChaRProceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture10.1109/MICRO.2006.50(333-346)Online publication date: 9-Dec-2006
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