Article

Static timing analysis of dynamically sensitizable paths

Authors:

S. Perremans,

L. Claesen,

H. De ManAuthors Info & Claims

DAC '89: Proceedings of the 26th ACM/IEEE Design Automation Conference

Pages 568 - 573

https://doi.org/10.1145/74382.74477

Published: 01 June 1989 Publication History

Abstract

This paper describes a new method for solving the false path problem in static timing analysis of acyclic, combinational circuits. The conditions under which a path is false are accurately defined. The fact that these conditions explicitly take into account the dynamic behaviour of the circuit, constitutes the main contribution of the paper. An algorithm for computing the longest dynamically sensitizable paths in an acyclic, combinational circuit is presented.

Cited By

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Chen YDong XShih WZhuo C(2023)Invited Paper: Unleashing the Potential of Machine Learning: Harnessing the Dynamics of Supply Noise for Timing Sign-Off2023 IEEE/ACM International Conference on Computer Aided Design (ICCAD)10.1109/ICCAD57390.2023.10324001(1-6)Online publication date: 28-Oct-2023
https://doi.org/10.1109/ICCAD57390.2023.10324001
Madhavan SPhadke RN B(2021)Physical Design and Implementation of Lakshya -Sub-system of Built in Self Test System2021 International Conference on Circuits, Controls and Communications (CCUBE)10.1109/CCUBE53681.2021.9702732(1-6)Online publication date: 23-Dec-2021
https://doi.org/10.1109/CCUBE53681.2021.9702732
Ganesh Prasad JKarbari SAmmikkallingal SBellal S(2018)Analysis, Physical Design and Power Optimization of Design Block at Lower Technology Node2018 3rd IEEE International Conference on Recent Trends in Electronics, Information & Communication Technology (RTEICT)10.1109/RTEICT42901.2018.9012556(732-737)Online publication date: May-2018
https://doi.org/10.1109/RTEICT42901.2018.9012556
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Index Terms

Static timing analysis of dynamically sensitizable paths
1. Hardware
  1. Integrated circuits
    1. Logic circuits
      1. Combinational circuits
  2. Very large scale integration design
2. Mathematics of computing
  1. Discrete mathematics
    1. Graph theory

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Timing verification using statically sensitizable paths

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Transient faults have become increasingly observable in combinational logic. This is due to the weakening of some inherent protective mechanisms that logic traditionally holds against such flawed spurious events. One of the aforementioned mechanisms ...
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Published In

DAC '89: Proceedings of the 26th ACM/IEEE Design Automation Conference

June 1989

839 pages

ISBN:0897913108

DOI:10.1145/74382

Chairman:
Donald E. Thomas
Carnegie Mellon Univ., Pittsburgh, PA

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 01 June 1989

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DAC89

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IEEE-CS\TCDA
SIGDA

DAC89: The 26th ACM/IEEE-CS Design Automation Conference

June 25 - 28, 1989

Nevada, Las Vegas, USA

Acceptance Rates

DAC '89 Paper Acceptance Rate 156 of 465 submissions, 34%;

Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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DAC '25

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sigda

62nd ACM/IEEE Design Automation Conference

June 22 - 26, 2025

San Francisco , CA , USA

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Cited By

View all

Chen YDong XShih WZhuo C(2023)Invited Paper: Unleashing the Potential of Machine Learning: Harnessing the Dynamics of Supply Noise for Timing Sign-Off2023 IEEE/ACM International Conference on Computer Aided Design (ICCAD)10.1109/ICCAD57390.2023.10324001(1-6)Online publication date: 28-Oct-2023
https://doi.org/10.1109/ICCAD57390.2023.10324001
Madhavan SPhadke RN B(2021)Physical Design and Implementation of Lakshya -Sub-system of Built in Self Test System2021 International Conference on Circuits, Controls and Communications (CCUBE)10.1109/CCUBE53681.2021.9702732(1-6)Online publication date: 23-Dec-2021
https://doi.org/10.1109/CCUBE53681.2021.9702732
Ganesh Prasad JKarbari SAmmikkallingal SBellal S(2018)Analysis, Physical Design and Power Optimization of Design Block at Lower Technology Node2018 3rd IEEE International Conference on Recent Trends in Electronics, Information & Communication Technology (RTEICT)10.1109/RTEICT42901.2018.9012556(732-737)Online publication date: May-2018
https://doi.org/10.1109/RTEICT42901.2018.9012556
Tsai CWang CHuang CChen YHenkel J(2013)Sensitization criterion for threshold logic circuits and its applicationProceedings of the International Conference on Computer-Aided Design10.5555/2561828.2561874(226-233)Online publication date: 18-Nov-2013
https://dl.acm.org/doi/10.5555/2561828.2561874
Tsai CWang CHuang CChen Y(2013)Sensitization criterion for threshold logic circuits and its application2013 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)10.1109/ICCAD.2013.6691123(226-233)Online publication date: Nov-2013
https://doi.org/10.1109/ICCAD.2013.6691123
Jung JKim T(2012)Variation-Aware False Path Analysis Based on Statistical Dynamic Timing AnalysisIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2012.220239231:11(1684-1697)Online publication date: 1-Nov-2012
https://dl.acm.org/doi/10.1109/TCAD.2012.2202392
Marques FMartinello ORibas RReis AMartino JAraújo GOrailoglu AKlein F(2010)Improvements on the detection of false paths by using unateness and satisfiabilityProceedings of the 23rd symposium on Integrated circuits and system design10.1145/1854153.1854201(192-197)Online publication date: 6-Sep-2010
https://dl.acm.org/doi/10.1145/1854153.1854201
Cheng LChen DWong MHutton MGovig JGielen G(2007)Timing constraint-driven technology mapping for FPGAs considering false paths and multi-clock domainsProceedings of the 2007 IEEE/ACM international conference on Computer-aided design10.5555/1326073.1326149(370-375)Online publication date: 5-Nov-2007
https://dl.acm.org/doi/10.5555/1326073.1326149
Lei Cheng Deming Chen Wong MHutton MGovig J(2007)Timing constraint-driven technology mapping for FPGAs considering false paths and multi-clock domains2007 IEEE/ACM International Conference on Computer-Aided Design10.1109/ICCAD.2007.4397292(370-375)Online publication date: Nov-2007
https://doi.org/10.1109/ICCAD.2007.4397292
Hsieh CLin JChang S(2006)Vectorless Estimation of Maximum Instantaneous Current for Sequential CircuitsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2006.87389425:11(2341-2352)Online publication date: Nov-2006
https://doi.org/10.1109/TCAD.2006.873894
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Timing verification using statically sensitizable paths

Propagation of Transients Along Sensitizable Paths

Static timing analysis with false paths and combinational loops

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Timing verification using statically sensitizable paths

Propagation of Transients Along Sensitizable Paths

Static timing analysis with false paths and combinational loops

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