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Partition-driven standard cell thermal placement

Published: 06 April 2003 Publication History

Abstract

The thermal problem has been emerged as one of the key issues for next-generation IC design. In this paper, we propose a scheme to achieve better thermal distribution for partition-driven standard cell placement. The proposed heuristic uses a multigrid-like method that simplifies the thermal equation at each level of partitioning and makes it possible to incorporate temperature considerations directly as placement constraints, thus leading to better thermal distribution. Our experimental results verify the effectiveness of our scheme. We also describe an algorithm to derive a compact thermal model with a complexity of O(mn + m2), where m is the number of the mesh nodes on the substrate surface and $n$ is the number of all internal mesh nodes.

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cover image ACM Conferences
ISPD '03: Proceedings of the 2003 international symposium on Physical design
April 2003
218 pages
ISBN:1581136501
DOI:10.1145/640000
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Publication History

Published: 06 April 2003

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Author Tags

  1. VLSI
  2. partition
  3. placement
  4. standard cell
  5. temperature
  6. thermal model

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ISPD03
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ISPD03: International Symposium on Physical Design
April 6 - 9, 2003
CA, Monterey, USA

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Overall Acceptance Rate 62 of 172 submissions, 36%

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  • (2018)Optimal Thermal Placement and Loss Estimation for Power Electronic ModulesIEEE Transactions on Components, Packaging and Manufacturing Technology10.1109/TCPMT.2017.27812828:2(236-243)Online publication date: Feb-2018
  • (2015)Three-Dimensional Thermal Modeling: Tools and MethodologiesThree-Dimensional Design Methodologies for Tree-based FPGA Architecture10.1007/978-3-319-19174-4_7(147-168)Online publication date: 26-Jun-2015
  • (2014)Fast Thermal Aware Placement With Accurate Thermal Analysis Based on Green FunctionIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2013.226858222:6(1404-1415)Online publication date: Jun-2014
  • (2013)A network-flow based algorithm for power density mitigation at post-placement stageProceedings of the Conference on Design, Automation and Test in Europe10.5555/2485288.2485691(1707-1710)Online publication date: 18-Mar-2013
  • (2013)3D thermal-aware floorplanner using a MOEA approximationIntegration, the VLSI Journal10.1016/j.vlsi.2012.04.00346:1(10-21)Online publication date: 1-Jan-2013
  • (2012)On the Construction of a Generalized Voronoi Inverse of a Rectangular TessellationProceedings of the 2012 Ninth International Symposium on Voronoi Diagrams in Science and Engineering10.1109/ISVD.2012.24(132-137)Online publication date: 27-Jun-2012
  • (2012)Thermal aware modern VLSI floorplanning2012 International Conference on Devices, Circuits and Systems (ICDCS)10.1109/ICDCSyst.2012.6188701(187-190)Online publication date: Mar-2012
  • (2012)A fast thermal aware placement with accurate thermal analysis based on Green function17th Asia and South Pacific Design Automation Conference10.1109/ASPDAC.2012.6164986(425-430)Online publication date: Jan-2012
  • (2012)Full Length ArticleMicroprocessors & Microsystems10.1016/j.micpro.2012.02.01236:5(344-354)Online publication date: 1-Jul-2012
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