skip to main content
10.1145/1278480.1278637acmconferencesArticle/Chapter ViewAbstractPublication PagesdacConference Proceedingsconference-collections
Article

Placement of 3D ICs with thermal and interlayer via considerations

Published: 04 June 2007 Publication History

Abstract

Thermal problems and limitations on interlayer via densities are important design constraints on three-dimensional integrated circuits (3D ICs), and need to be considered during global and detailed placement. Analytical and partitioning-based techniques are developed to explore the tradeoff between wirelength, interlayer via counts, and thermal effects. This method allows wirelengths to be minimized for any desired interlayer via density and temperatures to be reduced while minimizing deleterious effects on wirelength and interlayer via counts. Wirelength reductions within 2% of the optimal can be achieved using 46% fewer interlayer vias. Temperatures can be reduced by about 20% with only 1% higher wirelengths and 10% more interlayer vias.

References

[1]
T. Tanprasert, "An Analytical 3-D Placement that Reserves Routing Space," ISCAS '00, 69--72.
[2]
B. Goplen and S. S. Sapatnekar, "Efficient Thermal Placement of Standard Cells in 3D ICs using a Force Directed Approach," ICCAD '03, 86--89.
[3]
I. Kaya, M. Olbrich, and E. Barke, "3-D Placement Considering Vertical Interconnects," Proc. IEEE Int. SOC Conf. '03, 257--258.
[4]
R. Hentschke, G. Flach, F. Pinto, and R. Reis, "Quadratic Placement for 3D Circuits Using z-Cell Shifting, 3D Iterative Refinement and Simulated Annealing," Proa Symp. on Integrated Circuits and Syst. Des. '06, 220--225.
[5]
Y. Deng and W. Maly, "Interconnect Characteristics of 2.5-D System Integration Scheme," ISPD '01, 171--175.
[6]
S. Das, A. Chandrakasan, and R. Reif, "Design Tools for 3-D Integrated Circuits," ASP-DAC '03, 53--56.
[7]
C. N. Chu and D. F. Wong, "A Matrix Synthesis Approach to Thermal Placement," ISPD '97, 163--168.
[8]
B. Obermeier and F. M. Johannes, "Temperature-Aware Global Placement," ASP-DAC '04, 143--148.
[9]
C. H. Tsai and S. M. Kang, "Cell-Level Placement for Improving Substrate Thermal Distribution," TCAD, 2000, 19(2), 253--266.
[10]
G. Chen and S. S. Sapatnekar, "Partition-Driven Standard Cell Thernal Placement," ISPD '03, pp. 75--80.
[11]
A. E. Dunlop and B. W. Kermghan, "A Procedure for Placement of Standard Cell VLSI Circuits," TCAD, 1985, 4(1), 92--98.
[12]
C.-C. Chang, J. Cong, M. Romesis, and M. Xie, "Optimality and Scalability Study of Existing Placement Algorithms," TCAD, 2004, 23(4), 537--549.
[13]
N. Viswanathan and C. Chu, "FastPlace: Efficient Analytical Placement using Cell Shifting, Iterative Local Refinement and a Hybrid Net Model," ISPD '04, 26--33.
[14]
M. Pan, N. Viswanathan, and C. Chu, "An Efficient and Effective Detailed Placement Algorithm," ICCAD '05, 48--55.
[15]
G. Karypis, R. Aggarwal, V. Kumar, and S. Shekhar, "Multilevel Hypergraph Partitioning: Applications in VLSI Domain," IEEE Trans, on VLSI Syst., 1999, 7(1), 69--79.
[16]
http://er.cs.ucla.edu/benchmarks/ibm-place/
[17]
J. Burns, L. McIlrath, C. Keast, C. Lewis, A. Loomis, K. Warner, and P. Wyatt, "Three-Dimensional Integrated Circuits for Low-Power, High-Bandwidth Systems on a Chip," ISSCC Digest of Technical Papers, 2001, 268--269.
[18]
K. Warner, J. Burns, C. Keast, R. Kunz, D. Lennon, A. Loomis, W. Mowers, and D. Yost, "Low-Temperature Oxide-Bonded Three-Dimensional Integrated Circuits," IEEE International SOI Conference Proceedings, 2002, 123--124.
[19]
J. Cong, "Challenges and Opportunities for Design Innovations in Nanometer Technologies," Invited SRC Design Sciences Concept Paper, 1998, 1--15.

Cited By

View all
  • (2024)Analytical Die-to-Die 3-D Placement With Bistratal Wirelength Model and GPU AccelerationIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2023.334729343:6(1624-1637)Online publication date: Jun-2024
  • (2022)BBF: A Bloom Filter Using B Sequences for Multi-set Membership QueryACM Transactions on Knowledge Discovery from Data10.1145/350273516:5(1-26)Online publication date: 9-Mar-2022
  • (2022)Online Learning Bipartite Matching with Non-stationary DistributionsACM Transactions on Knowledge Discovery from Data10.1145/350273416:5(1-22)Online publication date: 9-Mar-2022
  • Show More Cited By

Index Terms

  1. Placement of 3D ICs with thermal and interlayer via considerations

        Recommendations

        Comments

        Information & Contributors

        Information

        Published In

        cover image ACM Conferences
        DAC '07: Proceedings of the 44th annual Design Automation Conference
        June 2007
        1016 pages
        ISBN:9781595936271
        DOI:10.1145/1278480
        Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

        Sponsors

        Publisher

        Association for Computing Machinery

        New York, NY, United States

        Publication History

        Published: 04 June 2007

        Permissions

        Request permissions for this article.

        Check for updates

        Author Tags

        1. 3-D 1C
        2. 3-D VLSI
        3. interlayer vias
        4. placement
        5. temperature
        6. thermal optimization

        Qualifiers

        • Article

        Conference

        DAC07
        Sponsor:

        Acceptance Rates

        DAC '07 Paper Acceptance Rate 152 of 659 submissions, 23%;
        Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

        Upcoming Conference

        DAC '25
        62nd ACM/IEEE Design Automation Conference
        June 22 - 26, 2025
        San Francisco , CA , USA

        Contributors

        Other Metrics

        Bibliometrics & Citations

        Bibliometrics

        Article Metrics

        • Downloads (Last 12 months)12
        • Downloads (Last 6 weeks)1
        Reflects downloads up to 15 Sep 2024

        Other Metrics

        Citations

        Cited By

        View all
        • (2024)Analytical Die-to-Die 3-D Placement With Bistratal Wirelength Model and GPU AccelerationIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2023.334729343:6(1624-1637)Online publication date: Jun-2024
        • (2022)BBF: A Bloom Filter Using B Sequences for Multi-set Membership QueryACM Transactions on Knowledge Discovery from Data10.1145/350273516:5(1-26)Online publication date: 9-Mar-2022
        • (2022)Online Learning Bipartite Matching with Non-stationary DistributionsACM Transactions on Knowledge Discovery from Data10.1145/350273416:5(1-22)Online publication date: 9-Mar-2022
        • (2022)Constant Time Graph Neural NetworksACM Transactions on Knowledge Discovery from Data10.1145/350273316:5(1-31)Online publication date: 9-Mar-2022
        • (2022)Evidence Transfer: Learning Improved Representations According to External Heterogeneous Task OutcomesACM Transactions on Knowledge Discovery from Data10.1145/350273216:5(1-22)Online publication date: 9-Mar-2022
        • (2021)Toward Responsible AI: An Overview of Federated Learning for User-centered Privacy-preserving ComputingACM Transactions on Interactive Intelligent Systems10.1145/348587511:3-4(1-22)Online publication date: 25-Oct-2021
        • (2021)Synthesizing Brain-network-inspired Interconnections for Large-scale Network-on-chipsACM Transactions on Design Automation of Electronic Systems10.1145/348096127:1(1-30)Online publication date: 15-Oct-2021
        • (2021)Design Automation and Test Solutions for Monolithic 3D ICsACM Journal on Emerging Technologies in Computing Systems10.1145/347346218:1(1-49)Online publication date: 16-Nov-2021
        • (2021)A Design Methodology for Energy-Aware Processing in Unmanned Aerial VehiclesACM Transactions on Design Automation of Electronic Systems10.1145/347045127:1(1-20)Online publication date: 13-Sep-2021
        • (2021)FastCFI: Real-time Control-Flow Integrity Using FPGA without Code InstrumentationACM Transactions on Design Automation of Electronic Systems10.1145/345847126:5(1-39)Online publication date: 5-Jun-2021
        • Show More Cited By

        View Options

        Get Access

        Login options

        View options

        PDF

        View or Download as a PDF file.

        PDF

        eReader

        View online with eReader.

        eReader

        Media

        Figures

        Other

        Tables

        Share

        Share

        Share this Publication link

        Share on social media