Article

Free access

Simultaneous placement and module optimization of analog IC's

Authors:

Edoardo Charbon,

Enrico Malavasi,

Davide Pandini,

Alberto Sangiovanni-VincentelliAuthors Info & Claims

DAC '94: Proceedings of the 31st annual Design Automation Conference

Pages 31 - 35

https://doi.org/10.1145/196244.196261

Published: 06 June 1994 Publication History

PDF eReader

References

[1]

J. Rijmenants, J. B. Litsios, T. R. Schwarz and M. G. R. Degrauwe, "ILAC: An Automated Layout Tool for Analog CMOS Circuits", IEEE Journal of Solid State Circuits, vol. 24, n. 2, pp. 417-425,April 1989.

Crossref

Google Scholar

[2]

M. Kayal, S. Piguet, M. Declercq and B. Hochet, "SALIM: A Layout Generator Tool for Analog ICs", in Proc. IEEE Custom Integrated Circuits Conference, pp. 751-754, May 1988.

Crossref

Google Scholar

[3]

J.M. Cohn, D. J. Garrod, R. A. Rutenbar and L. R. Carley, "KOAN/ANAGRAM II: New Tools for Device-Level Analog Placement and Routing", IEEE Journal of Solid State Circuits, vol. 26, n. 3, pp. 330-342, March 1991.

Crossref

Google Scholar

[4]

U. Choudhury and A. Sangiovanni-Vincentelli, "Constraint Generation for Routing Analog Circuits", in Proc. Design Automation Conference, pp. 561-566,June 1990.

Digital Library

Google Scholar

[5]

E. Malavasi, H. Chang, A. Sangiovanni-Vincentelli, E. Charbon, U. Choudhury, E. Felt, G. Jusuf, E. Liu and R. Neff, "A Top-down, Constraint-Driven Design Methodology for Analog Integrated Circuits", in Analog Circuit Design, pp. 285- 324. J. H. Huijsing, R. J. van der Plassche and W. Sansen Ed., Kluwer Academic Press, 1993.

Crossref

Google Scholar

[6]

E. Charbon, E. Malavasi, U. Choudhury, A. Casotto and A. Sangiovanni-Vincentelli, "A Constraint-Driven Placement Methodology for Analog Integrated Circuits", in P1vc. IEEE Custom Integrated Circuits Conference, pp. 2821-2824,May 1992.

Google Scholar

[7]

S. Kirkpatrick, C. Gelatt and M. Vecchi, "Optimization by simulated annealing", Science, vol. 220, n. 4598, pp. 671-680,May 1983.

Crossref

Google Scholar

[8]

E. Malavasi, D. Pandini and V. Liberali, "Optimum Stacked Layout for Analog CMOS ICs", in P1vc. IEEE Custom Integrated Circuits Conference, pp. 1711-1714, May 1993.

Crossref

Google Scholar

[9]

M.R. Garey and D. S. Johnson, Computers and lntractability. A Guide to the Theory ofNP-Completeness, W. H. Freeman & Co., New York, NY, 1979.

Digital Library

Google Scholar

[10]

C. Bron and J. Kerbosch, "Algorithm 457 - Finding all cliques of an undirected graph", Comm. ACM, vol. 16, n. 9, pp. 575-577, September 1973.

Digital Library

Google Scholar

[11]

F. Romeo, "Simulated Annealing: Theory and Applications to Layout Problems. PhD Thesis", MemorandumUCB/ERL M89/29, University of California at Berkeley, March 1989.

Google Scholar

[12]

E. Charbon, E. Malavasi and A. Sangiovanni-Vincentelli, "Generalized Constraint Generation for Analog Circuit Design", in P~vc. IEEE ICCAD, pp. 408-414, November 1993.

Digital Library

Google Scholar

[13]

E. Charbon, E. Malavasi, D. Pandini and A. Sangiovanni-Vincentelli, "Imposing Tight Specifications on Analog IC's through Simultaneous Placement and Module Optimization", in Proc. IEEE Custom Integrated Circuits Conference, May 1994.

Crossref

Google Scholar

[14]

U. Choudhury and A. Sangiovanni-Vincentelli, "An Analytical-Model Generator for Interconnect Capacitances", in Proc. IEEE Custom Integrated Circuits Conference, pp. 861-864,May 1991.

Crossref

Google Scholar

Cited By

View all

Matsuoka JNakashima YOno S(2017)A preliminary study on designing a benchmark problem for analysis of sparsely-synchronized heterogeneous coevolution2017 IEEE Symposium Series on Computational Intelligence (SSCI)10.1109/SSCI.2017.8285405(1-8)Online publication date: Nov-2017
https://doi.org/10.1109/SSCI.2017.8285405
Charbon EGharpurey RMeyer RSangiovanni-Vincentelli A(2006)Substrate optimization based on semi-analytical techniquesIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/43.74372718:2(172-190)Online publication date: 1-Nov-2006
https://dl.acm.org/doi/10.1109/43.743727
Malavasi ECharbon EFelt ESangiovanni-Vincentelli A(2006)Automation of IC layout with analog constraintsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/43.51157215:8(923-942)Online publication date: 1-Nov-2006
https://dl.acm.org/doi/10.1109/43.511572
Show More Cited By

Index Terms

Simultaneous placement and module optimization of analog IC's

Recommendations

Analog placement based on hierarchical module clustering
DAC '08: Proceedings of the 45th annual Design Automation Conference

In analog layout design, it is very important to reduce the parasitic coupling effects and improve the circuit performance. Consequently, the most important device-level placement constraints are matching, symmetry, and proximity. However, many previous ...
A Performance-Driven Placement Algorithm with Simultaneous Place&Route Optimization for Analog IC's
EDTC '97: Proceedings of the 1997 European conference on Design and Test

This paper presents a performance-driven placement algorithm for automatic layout generation of analog IC's. The main innovations of our approach are essentially: (i) an integrated Place&Route optimization algorithm which is able to provide a realistic ...
Simultaneous analog placement and routing with current flow and current density considerations
DAC '13: Proceedings of the 50th Annual Design Automation Conference

Current-flow and current-density are two major considerations for placement and routing of analog layout synthesis. The current-flow constraints are specified to the critical nets with monotonic current/signal paths to reduce parasitic impacts. The ...

Comments

Information & Contributors

Information

Published In

DAC '94: Proceedings of the 31st annual Design Automation Conference

June 1994

739 pages

ISBN:0897916530

DOI:10.1145/196244

Chairman:
Michael Lorenzetti
Mentor Graphics Corp., Wilsonville, OR

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 06 June 1994

Permissions

Request permissions for this article.

Request Permissions

Check for updates

Qualifiers

Article

Conference

DAC94

Sponsor:

EDAC
SIGDA
IEEE-CAS

DAC94: The 31st ACM/IEEE-CAS/EDAC Design Automation Conference

June 6 - 10, 1994

California, San Diego, USA

Acceptance Rates

DAC '94 Paper Acceptance Rate 100 of 260 submissions, 38%;

Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

Upcoming Conference

DAC '25

Sponsor:
sigda

62nd ACM/IEEE Design Automation Conference

June 22 - 26, 2025

San Francisco , CA , USA

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

11
Total Citations
View Citations
266
Total Downloads

Downloads (Last 12 months)38
Downloads (Last 6 weeks)12

Reflects downloads up to 15 Sep 2024

Other Metrics

View Author Metrics

Citations

Cited By

View all

Matsuoka JNakashima YOno S(2017)A preliminary study on designing a benchmark problem for analysis of sparsely-synchronized heterogeneous coevolution2017 IEEE Symposium Series on Computational Intelligence (SSCI)10.1109/SSCI.2017.8285405(1-8)Online publication date: Nov-2017
https://doi.org/10.1109/SSCI.2017.8285405
Charbon EGharpurey RMeyer RSangiovanni-Vincentelli A(2006)Substrate optimization based on semi-analytical techniquesIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/43.74372718:2(172-190)Online publication date: 1-Nov-2006
https://dl.acm.org/doi/10.1109/43.743727
Malavasi ECharbon EFelt ESangiovanni-Vincentelli A(2006)Automation of IC layout with analog constraintsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/43.51157215:8(923-942)Online publication date: 1-Nov-2006
https://dl.acm.org/doi/10.1109/43.511572
Malavasi EPandini D(2006)Optimum CMOS stack generation with analog constraintsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/43.36312014:1(107-122)Online publication date: 1-Nov-2006
https://dl.acm.org/doi/10.1109/43.363120
Rutenbar RCohn JWiesel MHill D(2000)Layout tools for analog ICs and mixed-signal SoCsProceedings of the 2000 international symposium on Physical design10.1145/332357.332378(76-83)Online publication date: 1-May-2000
https://dl.acm.org/doi/10.1145/332357.332378
Prieto JRueda AQuintana JHuertas J(1997)A Performance-Driven Placement Algorithm with Simultaneous Place&Route Optimization for Analog IC'sProceedings of the 1997 European conference on Design and Test10.5555/787260.787695Online publication date: 17-Mar-1997
https://dl.acm.org/doi/10.5555/787260.787695
Prieto JRueda AQuintana JHuertas J(1997)A performance-driven placement algorithm with simultaneous Place&Route optimization for analog ICsProceedings European Design and Test Conference. ED & TC 9710.1109/EDTC.1997.582389(389-394)Online publication date: 1997
https://doi.org/10.1109/EDTC.1997.582389
Miliozzi PVassiliou ICharbon EMalavasi EPennino TYoffa E(1996)Use of sensitivities and generalized substrate models in mixed-signal IC designProceedings of the 33rd annual Design Automation Conference10.1145/240518.240560(227-232)Online publication date: 1-Jun-1996
https://dl.acm.org/doi/10.1145/240518.240560
Basaran BRutenbar RPennino TYoffa E(1996)An O(n) algorithm for transistor stacking with performance constraintsProceedings of the 33rd annual Design Automation Conference10.1145/240518.240559(221-226)Online publication date: 1-Jun-1996
https://dl.acm.org/doi/10.1145/240518.240559
Miliozzi PVassiliou ICharbon EMalavasi ESangiovanni-Vincentel A(1996)Use of sensitivities and generalized substrate models in mixed-signal IC design33rd Design Automation Conference Proceedings, 199610.1109/DAC.1996.545577(227-232)Online publication date: 1996
https://doi.org/10.1109/DAC.1996.545577
Show More Cited By

View Options

View options

PDF

View or Download as a PDF file.

PDF

eReader

View online with eReader.

eReader

Get Access

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Cited By

Index Terms

Recommendations

Analog placement based on hierarchical module clustering

A Performance-Driven Placement Algorithm with Simultaneous Place&Route Optimization for Analog IC's

Simultaneous analog placement and routing with current flow and current density considerations

Comments

Published In

Sponsors

Publisher

Publication History

Permissions

Check for updates

Qualifiers

Conference

Acceptance Rates

Upcoming Conference

Other Metrics

Article Metrics

Other Metrics

Cited By

PDF

eReader

Login options

Full Access

References

Cited By

Index Terms

Recommendations

Analog placement based on hierarchical module clustering

A Performance-Driven Placement Algorithm with Simultaneous Place&Route Optimization for Analog IC's

Simultaneous analog placement and routing with current flow and current density considerations

Comments

Information

Published In

Sponsors

Publisher

Publication History

Permissions

Check for updates

Qualifiers

Conference

Acceptance Rates

Upcoming Conference

Contributors

Other Metrics

Bibliometrics

Article Metrics

Other Metrics

Citations

Cited By

View options

PDF

eReader

Get Access

Login options

Full Access

Figures

Other

Share

Share this Publication link

Share on social media

Affiliations