Changeset 777 for GPL/trunk/alsa-kernel/pci/emu10k1/io.c

Timestamp:

Apr 21, 2025, 7:17:25 PM (4 months ago)

Author:

David Azarewicz

Message:

Merge from uniaud32-exp branch

Location:

GPL/trunk

Files:

• . (modified) (1 prop)
• alsa-kernel/pci/emu10k1/io.c (modified) (5 diffs)

GPL/trunk/alsa-kernel/pci/emu10k1/io.c

@@ -291 +291 @@
 void snd_emu1010_fpga_write(struct snd_emu10k1 *emu, u32 reg, u32 value)
 {
-        unsigned long flags;
-
-        spin_lock_irqsave(&emu->emu_lock, flags);
+#ifndef TARGET_OS2
+        if (snd_BUG_ON(!mutex_is_locked(&emu->emu1010.lock)))
+                return;
+#endif
         snd_emu1010_fpga_write_locked(emu, reg, value);
-        spin_unlock_irqrestore(&emu->emu_lock, flags);
-}
-
-static void snd_emu1010_fpga_read_locked(struct snd_emu10k1 *emu, u32 reg, u32 *value)
+}
+
+void snd_emu1010_fpga_write_lock(struct snd_emu10k1 *emu, u32 reg, u32 value)
+{
+        snd_emu1010_fpga_lock(emu);
+        snd_emu1010_fpga_write_locked(emu, reg, value);
+        snd_emu1010_fpga_unlock(emu);
+}
+
+void snd_emu1010_fpga_read(struct snd_emu10k1 *emu, u32 reg, u32 *value)
 {
         // The higest input pin is used as the designated interrupt trigger,
@@ -305 +312 @@
         // so using this function often causes an IRQ as a side effect.
         u32 mask = emu->card_capabilities->ca0108_chip ? 0x1f : 0x7f;
+
+#ifndef TARGET_OS2
+        if (snd_BUG_ON(!mutex_is_locked(&emu->emu1010.lock)))
+                return;
+#endif
         if (snd_BUG_ON(reg > 0x3f))
                 return;
@@ -315 +327 @@
 }
 
-void snd_emu1010_fpga_read(struct snd_emu10k1 *emu, u32 reg, u32 *value)
-{
-        unsigned long flags;
-
-        spin_lock_irqsave(&emu->emu_lock, flags);
-        snd_emu1010_fpga_read_locked(emu, reg, value);
-        spin_unlock_irqrestore(&emu->emu_lock, flags);
-}
-
 /* Each Destination has one and only one Source,
  * but one Source can feed any number of Destinations simultaneously.
@@ -329 +332 @@
 void snd_emu1010_fpga_link_dst_src_write(struct snd_emu10k1 *emu, u32 dst, u32 src)
 {
-        unsigned long flags;
-
         if (snd_BUG_ON(dst & ~0x71f))
                 return;
         if (snd_BUG_ON(src & ~0x71f))
                 return;
-        spin_lock_irqsave(&emu->emu_lock, flags);
-        snd_emu1010_fpga_write_locked(emu, EMU_HANA_DESTHI, dst >> 8);
-        snd_emu1010_fpga_write_locked(emu, EMU_HANA_DESTLO, dst & 0x1f);
-        snd_emu1010_fpga_write_locked(emu, EMU_HANA_SRCHI, src >> 8);
-        snd_emu1010_fpga_write_locked(emu, EMU_HANA_SRCLO, src & 0x1f);
-        spin_unlock_irqrestore(&emu->emu_lock, flags);
+        snd_emu1010_fpga_write(emu, EMU_HANA_DESTHI, dst >> 8);
+        snd_emu1010_fpga_write(emu, EMU_HANA_DESTLO, dst & 0x1f);
+        snd_emu1010_fpga_write(emu, EMU_HANA_SRCHI, src >> 8);
+        snd_emu1010_fpga_write(emu, EMU_HANA_SRCLO, src & 0x1f);
 }
 
 u32 snd_emu1010_fpga_link_dst_src_read(struct snd_emu10k1 *emu, u32 dst)
 {
-        unsigned long flags;
         u32 hi, lo;
 
         if (snd_BUG_ON(dst & ~0x71f))
                 return 0;
-        spin_lock_irqsave(&emu->emu_lock, flags);
-        snd_emu1010_fpga_write_locked(emu, EMU_HANA_DESTHI, dst >> 8);
-        snd_emu1010_fpga_write_locked(emu, EMU_HANA_DESTLO, dst & 0x1f);
-        snd_emu1010_fpga_read_locked(emu, EMU_HANA_SRCHI, &hi);
-        snd_emu1010_fpga_read_locked(emu, EMU_HANA_SRCLO, &lo);
-        spin_unlock_irqrestore(&emu->emu_lock, flags);
+        snd_emu1010_fpga_write(emu, EMU_HANA_DESTHI, dst >> 8);
+        snd_emu1010_fpga_write(emu, EMU_HANA_DESTLO, dst & 0x1f);
+        snd_emu1010_fpga_read(emu, EMU_HANA_SRCHI, &hi);
+        snd_emu1010_fpga_read(emu, EMU_HANA_SRCLO, &lo);
         return (hi << 8) | lo;
 }
@@ -429 +425 @@
 
         snd_emu1010_fpga_write(emu, EMU_HANA_DOCK_LEDS_2, leds);
+}
+
+void snd_emu1010_load_firmware_entry(struct snd_emu10k1 *emu, int dock,
+                                     const struct firmware *fw_entry)
+{
+        __always_unused u16 write_post;
+
+        // On E-MU 1010 rev1 the FPGA is a Xilinx Spartan IIE XC2S50E.
+        // On E-MU 0404b it is a Xilinx Spartan III XC3S50.
+        // The wiring is as follows:
+        // GPO7 -> FPGA input & 1K resistor -> FPGA /PGMN <- FPGA output
+        //   In normal operation, the active low reset line is held up by
+        //   an FPGA output, while the GPO pin performs its duty as control
+        //   register access strobe signal. Writing the respective bit to
+        //   EMU_HANA_FPGA_CONFIG puts the FPGA output into high-Z mode, at
+        //   which point the GPO pin can control the reset line through the
+        //   resistor.
+        // GPO6 -> FPGA CCLK & FPGA input
+        // GPO5 -> FPGA DIN (dual function)
+
+        // If the FPGA is already programmed, return it to programming mode
+        snd_emu1010_fpga_write(emu, EMU_HANA_FPGA_CONFIG,
+                               dock ? EMU_HANA_FPGA_CONFIG_AUDIODOCK :
+                                      EMU_HANA_FPGA_CONFIG_HANA);
+
+        // Assert reset line for 100uS
+        outw(0x00, emu->port + A_GPIO);
+        write_post = inw(emu->port + A_GPIO);
+        udelay(100);
+        outw(0x80, emu->port + A_GPIO);
+        write_post = inw(emu->port + A_GPIO);
+        udelay(100);  // Allow FPGA memory to clean
+
+        // Upload the netlist. Keep reset line high!
+        for (int n = 0; n < fw_entry->size; n++) {
+                u8 value = fw_entry->data[n];
+                for (int i = 0; i < 8; i++) {
+                        u16 reg = 0x80;
+                        if (value & 1)
+                                reg |= 0x20;
+                        value >>= 1;
+                        outw(reg, emu->port + A_GPIO);
+                        write_post = inw(emu->port + A_GPIO);
+                        outw(reg | 0x40, emu->port + A_GPIO);
+                        write_post = inw(emu->port + A_GPIO);
+                }
+        }
+
+        // After programming, set GPIO bit 4 high again.
+        // This appears to be a config word that the rev1 Hana
+        // firmware reads; weird things happen without this.
+        outw(0x10, emu->port + A_GPIO);
+        write_post = inw(emu->port + A_GPIO);
 }