Changeset 772 for GPL/trunk/alsa-kernel/pci/emu10k1/emumixer.c
- Timestamp:
- Apr 19, 2025, 8:08:37 PM (7 months ago)
- Location:
- GPL/trunk
- Files:
-
- 2 edited
-
. (modified) (1 prop)
-
alsa-kernel/pci/emu10k1/emumixer.c (modified) (73 diffs)
Legend:
- Unmodified
- Added
- Removed
-
GPL/trunk
- Property svn:mergeinfo changed
/GPL/branches/uniaud32-6.6-LTS (added) merged: 765,768-769 /GPL/branches/uniaud32-exp (added) merged: 735-741,743-744,748-751,753-760,762-764 /GPL/branches/uniaud32-next merged: 718-734
- Property svn:mergeinfo changed
-
GPL/trunk/alsa-kernel/pci/emu10k1/emumixer.c
r703 r772 3 3 * Copyright (c) by Jaroslav Kysela <perex@perex.cz>, 4 4 * Takashi Iwai <tiwai@suse.de> 5 * Lee Revell <rlrevell@joe-job.com> 6 * James Courtier-Dutton <James@superbug.co.uk> 7 * Oswald Buddenhagen <oswald.buddenhagen@gmx.de> 5 8 * Creative Labs, Inc. 9 * 6 10 * Routines for control of EMU10K1 chips / mixer routines 7 * Multichannel PCM support Copyright (c) Lee Revell <rlrevell@joe-job.com>8 *9 * Copyright (c) by James Courtier-Dutton <James@superbug.co.uk>10 * Added EMU 1010 support.11 *12 * BUGS:13 * --14 *15 * TODO:16 * --17 11 */ 18 12 … … 30 24 static const DECLARE_TLV_DB_SCALE(snd_audigy_db_scale2, -10350, 50, 1); /* WM8775 gain scale */ 31 25 26 27 static int add_ctls(struct snd_emu10k1 *emu, const struct snd_kcontrol_new *tpl, 28 const char * const *ctls, unsigned nctls) 29 { 30 struct snd_kcontrol_new kctl = *tpl; 31 int err; 32 33 for (unsigned i = 0; i < nctls; i++) { 34 kctl.name = ctls[i]; 35 kctl.private_value = i; 36 err = snd_ctl_add(emu->card, snd_ctl_new1(&kctl, emu)); 37 if (err < 0) 38 return err; 39 } 40 return 0; 41 } 42 43 32 44 static int snd_emu10k1_spdif_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) 33 45 { … … 42 54 struct snd_emu10k1 *emu = snd_kcontrol_chip(kcontrol); 43 55 unsigned int idx = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id); 44 unsigned long flags;45 56 46 57 /* Limit: emu->spdif_bits */ 47 58 if (idx >= 3) 48 59 return -EINVAL; 49 spin_lock_irqsave(&emu->reg_lock, flags);50 60 ucontrol->value.iec958.status[0] = (emu->spdif_bits[idx] >> 0) & 0xff; 51 61 ucontrol->value.iec958.status[1] = (emu->spdif_bits[idx] >> 8) & 0xff; 52 62 ucontrol->value.iec958.status[2] = (emu->spdif_bits[idx] >> 16) & 0xff; 53 63 ucontrol->value.iec958.status[3] = (emu->spdif_bits[idx] >> 24) & 0xff; 54 spin_unlock_irqrestore(&emu->reg_lock, flags);55 64 return 0; 56 65 } … … 66 75 } 67 76 68 /* 69 * Items labels in enum mixer controls assigning source data to 70 * each destination 71 */ 72 static const char * const emu1010_src_texts[] = { 73 "Silence", 74 "Dock Mic A", 75 "Dock Mic B", 76 "Dock ADC1 Left", 77 "Dock ADC1 Right", 78 "Dock ADC2 Left", 79 "Dock ADC2 Right", 80 "Dock ADC3 Left", 81 "Dock ADC3 Right", 82 "0202 ADC Left", 83 "0202 ADC Right", 84 "0202 SPDIF Left", 85 "0202 SPDIF Right", 86 "ADAT 0", 87 "ADAT 1", 88 "ADAT 2", 89 "ADAT 3", 90 "ADAT 4", 91 "ADAT 5", 92 "ADAT 6", 93 "ADAT 7", 94 "DSP 0", 95 "DSP 1", 96 "DSP 2", 97 "DSP 3", 98 "DSP 4", 99 "DSP 5", 100 "DSP 6", 101 "DSP 7", 102 "DSP 8", 103 "DSP 9", 104 "DSP 10", 105 "DSP 11", 106 "DSP 12", 107 "DSP 13", 108 "DSP 14", 109 "DSP 15", 110 "DSP 16", 111 "DSP 17", 112 "DSP 18", 113 "DSP 19", 114 "DSP 20", 115 "DSP 21", 116 "DSP 22", 117 "DSP 23", 118 "DSP 24", 119 "DSP 25", 120 "DSP 26", 121 "DSP 27", 122 "DSP 28", 123 "DSP 29", 124 "DSP 30", 125 "DSP 31", 126 }; 127 128 /* 1616(m) cardbus */ 129 130 static const char * const emu1616_src_texts[] = { 131 "Silence", 132 "Dock Mic A", 133 "Dock Mic B", 134 "Dock ADC1 Left", 135 "Dock ADC1 Right", 136 "Dock ADC2 Left", 137 "Dock ADC2 Right", 138 "Dock SPDIF Left", 139 "Dock SPDIF Right", 140 "ADAT 0", 141 "ADAT 1", 142 "ADAT 2", 143 "ADAT 3", 144 "ADAT 4", 145 "ADAT 5", 146 "ADAT 6", 147 "ADAT 7", 148 "DSP 0", 149 "DSP 1", 150 "DSP 2", 151 "DSP 3", 152 "DSP 4", 153 "DSP 5", 154 "DSP 6", 155 "DSP 7", 156 "DSP 8", 157 "DSP 9", 158 "DSP 10", 159 "DSP 11", 160 "DSP 12", 161 "DSP 13", 162 "DSP 14", 163 "DSP 15", 164 "DSP 16", 165 "DSP 17", 166 "DSP 18", 167 "DSP 19", 168 "DSP 20", 169 "DSP 21", 170 "DSP 22", 171 "DSP 23", 172 "DSP 24", 173 "DSP 25", 174 "DSP 26", 175 "DSP 27", 176 "DSP 28", 177 "DSP 29", 178 "DSP 30", 179 "DSP 31", 180 }; 181 77 #define PAIR_PS(base, one, two, sfx) base " " one sfx, base " " two sfx 78 #define LR_PS(base, sfx) PAIR_PS(base, "Left", "Right", sfx) 79 80 #define ADAT_PS(pfx, sfx) \ 81 pfx "ADAT 0" sfx, pfx "ADAT 1" sfx, pfx "ADAT 2" sfx, pfx "ADAT 3" sfx, \ 82 pfx "ADAT 4" sfx, pfx "ADAT 5" sfx, pfx "ADAT 6" sfx, pfx "ADAT 7" sfx 83 84 #define PAIR_REGS(base, one, two) \ 85 base ## one ## 1, \ 86 base ## two ## 1 87 88 #define LR_REGS(base) PAIR_REGS(base, _LEFT, _RIGHT) 89 90 #define ADAT_REGS(base) \ 91 base+0, base+1, base+2, base+3, base+4, base+5, base+6, base+7 182 92 183 93 /* 184 94 * List of data sources available for each destination 185 95 */ 186 static const unsigned int emu1010_src_regs[] = { 187 EMU_SRC_SILENCE,/* 0 */ 188 EMU_SRC_DOCK_MIC_A1, /* 1 */ 189 EMU_SRC_DOCK_MIC_B1, /* 2 */ 190 EMU_SRC_DOCK_ADC1_LEFT1, /* 3 */ 191 EMU_SRC_DOCK_ADC1_RIGHT1, /* 4 */ 192 EMU_SRC_DOCK_ADC2_LEFT1, /* 5 */ 193 EMU_SRC_DOCK_ADC2_RIGHT1, /* 6 */ 194 EMU_SRC_DOCK_ADC3_LEFT1, /* 7 */ 195 EMU_SRC_DOCK_ADC3_RIGHT1, /* 8 */ 196 EMU_SRC_HAMOA_ADC_LEFT1, /* 9 */ 197 EMU_SRC_HAMOA_ADC_RIGHT1, /* 10 */ 198 EMU_SRC_HANA_SPDIF_LEFT1, /* 11 */ 199 EMU_SRC_HANA_SPDIF_RIGHT1, /* 12 */ 200 EMU_SRC_HANA_ADAT, /* 13 */ 201 EMU_SRC_HANA_ADAT+1, /* 14 */ 202 EMU_SRC_HANA_ADAT+2, /* 15 */ 203 EMU_SRC_HANA_ADAT+3, /* 16 */ 204 EMU_SRC_HANA_ADAT+4, /* 17 */ 205 EMU_SRC_HANA_ADAT+5, /* 18 */ 206 EMU_SRC_HANA_ADAT+6, /* 19 */ 207 EMU_SRC_HANA_ADAT+7, /* 20 */ 208 EMU_SRC_ALICE_EMU32A, /* 21 */ 209 EMU_SRC_ALICE_EMU32A+1, /* 22 */ 210 EMU_SRC_ALICE_EMU32A+2, /* 23 */ 211 EMU_SRC_ALICE_EMU32A+3, /* 24 */ 212 EMU_SRC_ALICE_EMU32A+4, /* 25 */ 213 EMU_SRC_ALICE_EMU32A+5, /* 26 */ 214 EMU_SRC_ALICE_EMU32A+6, /* 27 */ 215 EMU_SRC_ALICE_EMU32A+7, /* 28 */ 216 EMU_SRC_ALICE_EMU32A+8, /* 29 */ 217 EMU_SRC_ALICE_EMU32A+9, /* 30 */ 218 EMU_SRC_ALICE_EMU32A+0xa, /* 31 */ 219 EMU_SRC_ALICE_EMU32A+0xb, /* 32 */ 220 EMU_SRC_ALICE_EMU32A+0xc, /* 33 */ 221 EMU_SRC_ALICE_EMU32A+0xd, /* 34 */ 222 EMU_SRC_ALICE_EMU32A+0xe, /* 35 */ 223 EMU_SRC_ALICE_EMU32A+0xf, /* 36 */ 224 EMU_SRC_ALICE_EMU32B, /* 37 */ 225 EMU_SRC_ALICE_EMU32B+1, /* 38 */ 226 EMU_SRC_ALICE_EMU32B+2, /* 39 */ 227 EMU_SRC_ALICE_EMU32B+3, /* 40 */ 228 EMU_SRC_ALICE_EMU32B+4, /* 41 */ 229 EMU_SRC_ALICE_EMU32B+5, /* 42 */ 230 EMU_SRC_ALICE_EMU32B+6, /* 43 */ 231 EMU_SRC_ALICE_EMU32B+7, /* 44 */ 232 EMU_SRC_ALICE_EMU32B+8, /* 45 */ 233 EMU_SRC_ALICE_EMU32B+9, /* 46 */ 234 EMU_SRC_ALICE_EMU32B+0xa, /* 47 */ 235 EMU_SRC_ALICE_EMU32B+0xb, /* 48 */ 236 EMU_SRC_ALICE_EMU32B+0xc, /* 49 */ 237 EMU_SRC_ALICE_EMU32B+0xd, /* 50 */ 238 EMU_SRC_ALICE_EMU32B+0xe, /* 51 */ 239 EMU_SRC_ALICE_EMU32B+0xf, /* 52 */ 240 }; 96 97 #define DSP_TEXTS \ 98 "DSP 0", "DSP 1", "DSP 2", "DSP 3", "DSP 4", "DSP 5", "DSP 6", "DSP 7", \ 99 "DSP 8", "DSP 9", "DSP 10", "DSP 11", "DSP 12", "DSP 13", "DSP 14", "DSP 15", \ 100 "DSP 16", "DSP 17", "DSP 18", "DSP 19", "DSP 20", "DSP 21", "DSP 22", "DSP 23", \ 101 "DSP 24", "DSP 25", "DSP 26", "DSP 27", "DSP 28", "DSP 29", "DSP 30", "DSP 31" 102 103 #define PAIR_TEXTS(base, one, two) PAIR_PS(base, one, two, "") 104 #define LR_TEXTS(base) LR_PS(base, "") 105 #define ADAT_TEXTS(pfx) ADAT_PS(pfx, "") 106 107 #define EMU32_SRC_REGS \ 108 EMU_SRC_ALICE_EMU32A, \ 109 EMU_SRC_ALICE_EMU32A+1, \ 110 EMU_SRC_ALICE_EMU32A+2, \ 111 EMU_SRC_ALICE_EMU32A+3, \ 112 EMU_SRC_ALICE_EMU32A+4, \ 113 EMU_SRC_ALICE_EMU32A+5, \ 114 EMU_SRC_ALICE_EMU32A+6, \ 115 EMU_SRC_ALICE_EMU32A+7, \ 116 EMU_SRC_ALICE_EMU32A+8, \ 117 EMU_SRC_ALICE_EMU32A+9, \ 118 EMU_SRC_ALICE_EMU32A+0xa, \ 119 EMU_SRC_ALICE_EMU32A+0xb, \ 120 EMU_SRC_ALICE_EMU32A+0xc, \ 121 EMU_SRC_ALICE_EMU32A+0xd, \ 122 EMU_SRC_ALICE_EMU32A+0xe, \ 123 EMU_SRC_ALICE_EMU32A+0xf, \ 124 EMU_SRC_ALICE_EMU32B, \ 125 EMU_SRC_ALICE_EMU32B+1, \ 126 EMU_SRC_ALICE_EMU32B+2, \ 127 EMU_SRC_ALICE_EMU32B+3, \ 128 EMU_SRC_ALICE_EMU32B+4, \ 129 EMU_SRC_ALICE_EMU32B+5, \ 130 EMU_SRC_ALICE_EMU32B+6, \ 131 EMU_SRC_ALICE_EMU32B+7, \ 132 EMU_SRC_ALICE_EMU32B+8, \ 133 EMU_SRC_ALICE_EMU32B+9, \ 134 EMU_SRC_ALICE_EMU32B+0xa, \ 135 EMU_SRC_ALICE_EMU32B+0xb, \ 136 EMU_SRC_ALICE_EMU32B+0xc, \ 137 EMU_SRC_ALICE_EMU32B+0xd, \ 138 EMU_SRC_ALICE_EMU32B+0xe, \ 139 EMU_SRC_ALICE_EMU32B+0xf 140 141 /* 1010 rev1 */ 142 143 #define EMU1010_COMMON_TEXTS \ 144 "Silence", \ 145 PAIR_TEXTS("Dock Mic", "A", "B"), \ 146 LR_TEXTS("Dock ADC1"), \ 147 LR_TEXTS("Dock ADC2"), \ 148 LR_TEXTS("Dock ADC3"), \ 149 LR_TEXTS("0202 ADC"), \ 150 LR_TEXTS("1010 SPDIF"), \ 151 ADAT_TEXTS("1010 ") 152 153 static const char * const emu1010_src_texts[] = { 154 EMU1010_COMMON_TEXTS, 155 DSP_TEXTS, 156 }; 157 158 static const unsigned short emu1010_src_regs[] = { 159 EMU_SRC_SILENCE, 160 PAIR_REGS(EMU_SRC_DOCK_MIC, _A, _B), 161 LR_REGS(EMU_SRC_DOCK_ADC1), 162 LR_REGS(EMU_SRC_DOCK_ADC2), 163 LR_REGS(EMU_SRC_DOCK_ADC3), 164 LR_REGS(EMU_SRC_HAMOA_ADC), 165 LR_REGS(EMU_SRC_HANA_SPDIF), 166 ADAT_REGS(EMU_SRC_HANA_ADAT), 167 EMU32_SRC_REGS, 168 }; 169 //static_assert(ARRAY_SIZE(emu1010_src_regs) == ARRAY_SIZE(emu1010_src_texts)); 170 171 /* 1010 rev2 */ 172 173 #define EMU1010b_COMMON_TEXTS \ 174 "Silence", \ 175 PAIR_TEXTS("Dock Mic", "A", "B"), \ 176 LR_TEXTS("Dock ADC1"), \ 177 LR_TEXTS("Dock ADC2"), \ 178 LR_TEXTS("0202 ADC"), \ 179 LR_TEXTS("Dock SPDIF"), \ 180 LR_TEXTS("1010 SPDIF"), \ 181 ADAT_TEXTS("Dock "), \ 182 ADAT_TEXTS("1010 ") 183 184 static const char * const emu1010b_src_texts[] = { 185 EMU1010b_COMMON_TEXTS, 186 DSP_TEXTS, 187 }; 188 189 static const unsigned short emu1010b_src_regs[] = { 190 EMU_SRC_SILENCE, 191 PAIR_REGS(EMU_SRC_DOCK_MIC, _A, _B), 192 LR_REGS(EMU_SRC_DOCK_ADC1), 193 LR_REGS(EMU_SRC_DOCK_ADC2), 194 LR_REGS(EMU_SRC_HAMOA_ADC), 195 LR_REGS(EMU_SRC_MDOCK_SPDIF), 196 LR_REGS(EMU_SRC_HANA_SPDIF), 197 ADAT_REGS(EMU_SRC_MDOCK_ADAT), 198 ADAT_REGS(EMU_SRC_HANA_ADAT), 199 EMU32_SRC_REGS, 200 }; 201 //static_assert(ARRAY_SIZE(emu1010b_src_regs) == ARRAY_SIZE(emu1010b_src_texts)); 241 202 242 203 /* 1616(m) cardbus */ 243 static const unsigned int emu1616_src_regs[] = { 204 205 #define EMU1616_COMMON_TEXTS \ 206 "Silence", \ 207 PAIR_TEXTS("Mic", "A", "B"), \ 208 LR_TEXTS("ADC1"), \ 209 LR_TEXTS("ADC2"), \ 210 LR_TEXTS("SPDIF"), \ 211 ADAT_TEXTS("") 212 213 static const char * const emu1616_src_texts[] = { 214 EMU1616_COMMON_TEXTS, 215 DSP_TEXTS, 216 }; 217 218 static const unsigned short emu1616_src_regs[] = { 244 219 EMU_SRC_SILENCE, 245 EMU_SRC_DOCK_MIC_A1, 246 EMU_SRC_DOCK_MIC_B1, 247 EMU_SRC_DOCK_ADC1_LEFT1, 248 EMU_SRC_DOCK_ADC1_RIGHT1, 249 EMU_SRC_DOCK_ADC2_LEFT1, 250 EMU_SRC_DOCK_ADC2_RIGHT1, 251 EMU_SRC_MDOCK_SPDIF_LEFT1, 252 EMU_SRC_MDOCK_SPDIF_RIGHT1, 253 EMU_SRC_MDOCK_ADAT, 254 EMU_SRC_MDOCK_ADAT+1, 255 EMU_SRC_MDOCK_ADAT+2, 256 EMU_SRC_MDOCK_ADAT+3, 257 EMU_SRC_MDOCK_ADAT+4, 258 EMU_SRC_MDOCK_ADAT+5, 259 EMU_SRC_MDOCK_ADAT+6, 260 EMU_SRC_MDOCK_ADAT+7, 261 EMU_SRC_ALICE_EMU32A, 262 EMU_SRC_ALICE_EMU32A+1, 263 EMU_SRC_ALICE_EMU32A+2, 264 EMU_SRC_ALICE_EMU32A+3, 265 EMU_SRC_ALICE_EMU32A+4, 266 EMU_SRC_ALICE_EMU32A+5, 267 EMU_SRC_ALICE_EMU32A+6, 268 EMU_SRC_ALICE_EMU32A+7, 269 EMU_SRC_ALICE_EMU32A+8, 270 EMU_SRC_ALICE_EMU32A+9, 271 EMU_SRC_ALICE_EMU32A+0xa, 272 EMU_SRC_ALICE_EMU32A+0xb, 273 EMU_SRC_ALICE_EMU32A+0xc, 274 EMU_SRC_ALICE_EMU32A+0xd, 275 EMU_SRC_ALICE_EMU32A+0xe, 276 EMU_SRC_ALICE_EMU32A+0xf, 277 EMU_SRC_ALICE_EMU32B, 278 EMU_SRC_ALICE_EMU32B+1, 279 EMU_SRC_ALICE_EMU32B+2, 280 EMU_SRC_ALICE_EMU32B+3, 281 EMU_SRC_ALICE_EMU32B+4, 282 EMU_SRC_ALICE_EMU32B+5, 283 EMU_SRC_ALICE_EMU32B+6, 284 EMU_SRC_ALICE_EMU32B+7, 285 EMU_SRC_ALICE_EMU32B+8, 286 EMU_SRC_ALICE_EMU32B+9, 287 EMU_SRC_ALICE_EMU32B+0xa, 288 EMU_SRC_ALICE_EMU32B+0xb, 289 EMU_SRC_ALICE_EMU32B+0xc, 290 EMU_SRC_ALICE_EMU32B+0xd, 291 EMU_SRC_ALICE_EMU32B+0xe, 292 EMU_SRC_ALICE_EMU32B+0xf, 293 }; 220 PAIR_REGS(EMU_SRC_DOCK_MIC, _A, _B), 221 LR_REGS(EMU_SRC_DOCK_ADC1), 222 LR_REGS(EMU_SRC_DOCK_ADC2), 223 LR_REGS(EMU_SRC_MDOCK_SPDIF), 224 ADAT_REGS(EMU_SRC_MDOCK_ADAT), 225 EMU32_SRC_REGS, 226 }; 227 //static_assert(ARRAY_SIZE(emu1616_src_regs) == ARRAY_SIZE(emu1616_src_texts)); 228 229 /* 0404 rev1 & rev2 */ 230 231 #define EMU0404_COMMON_TEXTS \ 232 "Silence", \ 233 LR_TEXTS("ADC"), \ 234 LR_TEXTS("SPDIF") 235 236 static const char * const emu0404_src_texts[] = { 237 EMU0404_COMMON_TEXTS, 238 DSP_TEXTS, 239 }; 240 241 static const unsigned short emu0404_src_regs[] = { 242 EMU_SRC_SILENCE, 243 LR_REGS(EMU_SRC_HAMOA_ADC), 244 LR_REGS(EMU_SRC_HANA_SPDIF), 245 EMU32_SRC_REGS, 246 }; 247 //static_assert(ARRAY_SIZE(emu0404_src_regs) == ARRAY_SIZE(emu0404_src_texts)); 294 248 295 249 /* … … 297 251 * Each destination has an enum mixer control to choose a data source 298 252 */ 299 static const unsigned int emu1010_output_dst[] = { 300 EMU_DST_DOCK_DAC1_LEFT1, /* 0 */ 301 EMU_DST_DOCK_DAC1_RIGHT1, /* 1 */ 302 EMU_DST_DOCK_DAC2_LEFT1, /* 2 */ 303 EMU_DST_DOCK_DAC2_RIGHT1, /* 3 */ 304 EMU_DST_DOCK_DAC3_LEFT1, /* 4 */ 305 EMU_DST_DOCK_DAC3_RIGHT1, /* 5 */ 306 EMU_DST_DOCK_DAC4_LEFT1, /* 6 */ 307 EMU_DST_DOCK_DAC4_RIGHT1, /* 7 */ 308 EMU_DST_DOCK_PHONES_LEFT1, /* 8 */ 309 EMU_DST_DOCK_PHONES_RIGHT1, /* 9 */ 310 EMU_DST_DOCK_SPDIF_LEFT1, /* 10 */ 311 EMU_DST_DOCK_SPDIF_RIGHT1, /* 11 */ 312 EMU_DST_HANA_SPDIF_LEFT1, /* 12 */ 313 EMU_DST_HANA_SPDIF_RIGHT1, /* 13 */ 314 EMU_DST_HAMOA_DAC_LEFT1, /* 14 */ 315 EMU_DST_HAMOA_DAC_RIGHT1, /* 15 */ 316 EMU_DST_HANA_ADAT, /* 16 */ 317 EMU_DST_HANA_ADAT+1, /* 17 */ 318 EMU_DST_HANA_ADAT+2, /* 18 */ 319 EMU_DST_HANA_ADAT+3, /* 19 */ 320 EMU_DST_HANA_ADAT+4, /* 20 */ 321 EMU_DST_HANA_ADAT+5, /* 21 */ 322 EMU_DST_HANA_ADAT+6, /* 22 */ 323 EMU_DST_HANA_ADAT+7, /* 23 */ 253 254 #define LR_CTLS(base) LR_PS(base, " Playback Enum") 255 #define ADAT_CTLS(pfx) ADAT_PS(pfx, " Playback Enum") 256 257 /* 1010 rev1 */ 258 259 static const char * const emu1010_output_texts[] = { 260 LR_CTLS("Dock DAC1"), 261 LR_CTLS("Dock DAC2"), 262 LR_CTLS("Dock DAC3"), 263 LR_CTLS("Dock DAC4"), 264 LR_CTLS("Dock Phones"), 265 LR_CTLS("Dock SPDIF"), 266 LR_CTLS("0202 DAC"), 267 LR_CTLS("1010 SPDIF"), 268 ADAT_CTLS("1010 "), 269 }; 270 //static_assert(ARRAY_SIZE(emu1010_output_texts) <= NUM_OUTPUT_DESTS); 271 272 static const unsigned short emu1010_output_dst[] = { 273 LR_REGS(EMU_DST_DOCK_DAC1), 274 LR_REGS(EMU_DST_DOCK_DAC2), 275 LR_REGS(EMU_DST_DOCK_DAC3), 276 LR_REGS(EMU_DST_DOCK_DAC4), 277 LR_REGS(EMU_DST_DOCK_PHONES), 278 LR_REGS(EMU_DST_DOCK_SPDIF), 279 LR_REGS(EMU_DST_HAMOA_DAC), 280 LR_REGS(EMU_DST_HANA_SPDIF), 281 ADAT_REGS(EMU_DST_HANA_ADAT), 282 }; 283 //static_assert(ARRAY_SIZE(emu1010_output_dst) == ARRAY_SIZE(emu1010_output_texts)); 284 285 static const unsigned short emu1010_output_dflt[] = { 286 EMU_SRC_ALICE_EMU32A+0, EMU_SRC_ALICE_EMU32A+1, 287 EMU_SRC_ALICE_EMU32A+2, EMU_SRC_ALICE_EMU32A+3, 288 EMU_SRC_ALICE_EMU32A+4, EMU_SRC_ALICE_EMU32A+5, 289 EMU_SRC_ALICE_EMU32A+6, EMU_SRC_ALICE_EMU32A+7, 290 EMU_SRC_ALICE_EMU32A+0, EMU_SRC_ALICE_EMU32A+1, 291 EMU_SRC_ALICE_EMU32A+0, EMU_SRC_ALICE_EMU32A+1, 292 EMU_SRC_ALICE_EMU32A+0, EMU_SRC_ALICE_EMU32A+1, 293 EMU_SRC_ALICE_EMU32A+0, EMU_SRC_ALICE_EMU32A+1, 294 EMU_SRC_ALICE_EMU32A+0, EMU_SRC_ALICE_EMU32A+1, EMU_SRC_ALICE_EMU32A+2, EMU_SRC_ALICE_EMU32A+3, 295 EMU_SRC_ALICE_EMU32A+4, EMU_SRC_ALICE_EMU32A+5, EMU_SRC_ALICE_EMU32A+6, EMU_SRC_ALICE_EMU32A+7, 296 }; 297 //static_assert(ARRAY_SIZE(emu1010_output_dflt) == ARRAY_SIZE(emu1010_output_dst)); 298 299 /* 1010 rev2 */ 300 301 static const char * const snd_emu1010b_output_texts[] = { 302 LR_CTLS("Dock DAC1"), 303 LR_CTLS("Dock DAC2"), 304 LR_CTLS("Dock DAC3"), 305 LR_CTLS("Dock SPDIF"), 306 ADAT_CTLS("Dock "), 307 LR_CTLS("0202 DAC"), 308 LR_CTLS("1010 SPDIF"), 309 ADAT_CTLS("1010 "), 310 }; 311 //static_assert(ARRAY_SIZE(snd_emu1010b_output_texts) <= NUM_OUTPUT_DESTS); 312 313 static const unsigned short emu1010b_output_dst[] = { 314 LR_REGS(EMU_DST_DOCK_DAC1), 315 LR_REGS(EMU_DST_DOCK_DAC2), 316 LR_REGS(EMU_DST_DOCK_DAC3), 317 LR_REGS(EMU_DST_MDOCK_SPDIF), 318 ADAT_REGS(EMU_DST_MDOCK_ADAT), 319 LR_REGS(EMU_DST_HAMOA_DAC), 320 LR_REGS(EMU_DST_HANA_SPDIF), 321 ADAT_REGS(EMU_DST_HANA_ADAT), 322 }; 323 //static_assert(ARRAY_SIZE(emu1010b_output_dst) == ARRAY_SIZE(snd_emu1010b_output_texts)); 324 325 static const unsigned short emu1010b_output_dflt[] = { 326 EMU_SRC_ALICE_EMU32A+0, EMU_SRC_ALICE_EMU32A+1, 327 EMU_SRC_ALICE_EMU32A+2, EMU_SRC_ALICE_EMU32A+3, 328 EMU_SRC_ALICE_EMU32A+4, EMU_SRC_ALICE_EMU32A+5, 329 EMU_SRC_ALICE_EMU32A+0, EMU_SRC_ALICE_EMU32A+1, 330 EMU_SRC_ALICE_EMU32A+0, EMU_SRC_ALICE_EMU32A+1, EMU_SRC_ALICE_EMU32A+2, EMU_SRC_ALICE_EMU32A+3, 331 EMU_SRC_ALICE_EMU32A+4, EMU_SRC_ALICE_EMU32A+5, EMU_SRC_ALICE_EMU32A+6, EMU_SRC_ALICE_EMU32A+7, 332 EMU_SRC_ALICE_EMU32A+0, EMU_SRC_ALICE_EMU32A+1, 333 EMU_SRC_ALICE_EMU32A+0, EMU_SRC_ALICE_EMU32A+1, 334 EMU_SRC_ALICE_EMU32A+0, EMU_SRC_ALICE_EMU32A+1, EMU_SRC_ALICE_EMU32A+2, EMU_SRC_ALICE_EMU32A+3, 335 EMU_SRC_ALICE_EMU32A+4, EMU_SRC_ALICE_EMU32A+5, EMU_SRC_ALICE_EMU32A+6, EMU_SRC_ALICE_EMU32A+7, 324 336 }; 325 337 326 338 /* 1616(m) cardbus */ 327 static const unsigned int emu1616_output_dst[] = { 328 EMU_DST_DOCK_DAC1_LEFT1, 329 EMU_DST_DOCK_DAC1_RIGHT1, 330 EMU_DST_DOCK_DAC2_LEFT1, 331 EMU_DST_DOCK_DAC2_RIGHT1, 332 EMU_DST_DOCK_DAC3_LEFT1, 333 EMU_DST_DOCK_DAC3_RIGHT1, 334 EMU_DST_MDOCK_SPDIF_LEFT1, 335 EMU_DST_MDOCK_SPDIF_RIGHT1, 336 EMU_DST_MDOCK_ADAT, 337 EMU_DST_MDOCK_ADAT+1, 338 EMU_DST_MDOCK_ADAT+2, 339 EMU_DST_MDOCK_ADAT+3, 340 EMU_DST_MDOCK_ADAT+4, 341 EMU_DST_MDOCK_ADAT+5, 342 EMU_DST_MDOCK_ADAT+6, 343 EMU_DST_MDOCK_ADAT+7, 344 EMU_DST_MANA_DAC_LEFT, 345 EMU_DST_MANA_DAC_RIGHT, 346 }; 339 340 static const char * const snd_emu1616_output_texts[] = { 341 LR_CTLS("Dock DAC1"), 342 LR_CTLS("Dock DAC2"), 343 LR_CTLS("Dock DAC3"), 344 LR_CTLS("Dock SPDIF"), 345 ADAT_CTLS("Dock "), 346 LR_CTLS("Mana DAC"), 347 }; 348 //static_assert(ARRAY_SIZE(snd_emu1616_output_texts) <= NUM_OUTPUT_DESTS); 349 350 static const unsigned short emu1616_output_dst[] = { 351 LR_REGS(EMU_DST_DOCK_DAC1), 352 LR_REGS(EMU_DST_DOCK_DAC2), 353 LR_REGS(EMU_DST_DOCK_DAC3), 354 LR_REGS(EMU_DST_MDOCK_SPDIF), 355 ADAT_REGS(EMU_DST_MDOCK_ADAT), 356 EMU_DST_MANA_DAC_LEFT, EMU_DST_MANA_DAC_RIGHT, 357 }; 358 //static_assert(ARRAY_SIZE(emu1616_output_dst) == ARRAY_SIZE(snd_emu1616_output_texts)); 359 360 static const unsigned short emu1616_output_dflt[] = { 361 EMU_SRC_ALICE_EMU32A+0, EMU_SRC_ALICE_EMU32A+1, 362 EMU_SRC_ALICE_EMU32A+2, EMU_SRC_ALICE_EMU32A+3, 363 EMU_SRC_ALICE_EMU32A+4, EMU_SRC_ALICE_EMU32A+5, 364 EMU_SRC_ALICE_EMU32A+0, EMU_SRC_ALICE_EMU32A+1, 365 EMU_SRC_ALICE_EMU32A+0, EMU_SRC_ALICE_EMU32A+1, EMU_SRC_ALICE_EMU32A+2, EMU_SRC_ALICE_EMU32A+3, 366 EMU_SRC_ALICE_EMU32A+4, EMU_SRC_ALICE_EMU32A+5, EMU_SRC_ALICE_EMU32A+6, EMU_SRC_ALICE_EMU32A+7, 367 EMU_SRC_ALICE_EMU32A+0, EMU_SRC_ALICE_EMU32A+1, 368 }; 369 //static_assert(ARRAY_SIZE(emu1616_output_dflt) == ARRAY_SIZE(emu1616_output_dst)); 370 371 /* 0404 rev1 & rev2 */ 372 373 static const char * const snd_emu0404_output_texts[] = { 374 LR_CTLS("DAC"), 375 LR_CTLS("SPDIF"), 376 }; 377 //static_assert(ARRAY_SIZE(snd_emu0404_output_texts) <= NUM_OUTPUT_DESTS); 378 379 static const unsigned short emu0404_output_dst[] = { 380 LR_REGS(EMU_DST_HAMOA_DAC), 381 LR_REGS(EMU_DST_HANA_SPDIF), 382 }; 383 //static_assert(ARRAY_SIZE(emu0404_output_dst) == ARRAY_SIZE(snd_emu0404_output_texts)); 384 385 static const unsigned short emu0404_output_dflt[] = { 386 EMU_SRC_ALICE_EMU32A+0, EMU_SRC_ALICE_EMU32A+1, 387 EMU_SRC_ALICE_EMU32A+0, EMU_SRC_ALICE_EMU32A+1, 388 }; 389 //static_assert(ARRAY_SIZE(emu0404_output_dflt) == ARRAY_SIZE(emu0404_output_dst)); 347 390 348 391 /* 349 * Data destinations - HANA outputs going to Alice2 (audigy) for392 * Data destinations - FPGA outputs going to Alice2 (Audigy) for 350 393 * capture (EMU32 + I2S links) 351 394 * Each destination has an enum mixer control to choose a data source 352 395 */ 353 static const unsigned int emu1010_input_dst[] = { 396 397 static const char * const emu1010_input_texts[] = { 398 "DSP 0 Capture Enum", 399 "DSP 1 Capture Enum", 400 "DSP 2 Capture Enum", 401 "DSP 3 Capture Enum", 402 "DSP 4 Capture Enum", 403 "DSP 5 Capture Enum", 404 "DSP 6 Capture Enum", 405 "DSP 7 Capture Enum", 406 "DSP 8 Capture Enum", 407 "DSP 9 Capture Enum", 408 "DSP A Capture Enum", 409 "DSP B Capture Enum", 410 "DSP C Capture Enum", 411 "DSP D Capture Enum", 412 "DSP E Capture Enum", 413 "DSP F Capture Enum", 414 /* These exist only on rev1 EMU1010 cards. */ 415 "DSP 10 Capture Enum", 416 "DSP 11 Capture Enum", 417 "DSP 12 Capture Enum", 418 "DSP 13 Capture Enum", 419 "DSP 14 Capture Enum", 420 "DSP 15 Capture Enum", 421 }; 422 //static_assert(ARRAY_SIZE(emu1010_input_texts) <= NUM_INPUT_DESTS); 423 424 static const unsigned short emu1010_input_dst[] = { 354 425 EMU_DST_ALICE2_EMU32_0, 355 426 EMU_DST_ALICE2_EMU32_1, … … 368 439 EMU_DST_ALICE2_EMU32_E, 369 440 EMU_DST_ALICE2_EMU32_F, 441 /* These exist only on rev1 EMU1010 cards. */ 370 442 EMU_DST_ALICE_I2S0_LEFT, 371 443 EMU_DST_ALICE_I2S0_RIGHT, … … 375 447 EMU_DST_ALICE_I2S2_RIGHT, 376 448 }; 449 //static_assert(ARRAY_SIZE(emu1010_input_dst) == ARRAY_SIZE(emu1010_input_texts)); 450 451 static const unsigned short emu1010_input_dflt[] = { 452 EMU_SRC_DOCK_MIC_A1, 453 EMU_SRC_DOCK_MIC_B1, 454 EMU_SRC_HAMOA_ADC_LEFT1, 455 EMU_SRC_HAMOA_ADC_RIGHT1, 456 EMU_SRC_DOCK_ADC1_LEFT1, 457 EMU_SRC_DOCK_ADC1_RIGHT1, 458 EMU_SRC_DOCK_ADC2_LEFT1, 459 EMU_SRC_DOCK_ADC2_RIGHT1, 460 /* Pavel Hofman - setting defaults for all capture channels. 461 * Defaults only, users will set their own values anyways, let's 462 * just copy/paste. */ 463 EMU_SRC_DOCK_MIC_A1, 464 EMU_SRC_DOCK_MIC_B1, 465 EMU_SRC_HAMOA_ADC_LEFT1, 466 EMU_SRC_HAMOA_ADC_RIGHT1, 467 EMU_SRC_DOCK_ADC1_LEFT1, 468 EMU_SRC_DOCK_ADC1_RIGHT1, 469 EMU_SRC_DOCK_ADC2_LEFT1, 470 EMU_SRC_DOCK_ADC2_RIGHT1, 471 472 EMU_SRC_DOCK_ADC1_LEFT1, 473 EMU_SRC_DOCK_ADC1_RIGHT1, 474 EMU_SRC_DOCK_ADC2_LEFT1, 475 EMU_SRC_DOCK_ADC2_RIGHT1, 476 EMU_SRC_DOCK_ADC3_LEFT1, 477 EMU_SRC_DOCK_ADC3_RIGHT1, 478 }; 479 //static_assert(ARRAY_SIZE(emu1010_input_dflt) == ARRAY_SIZE(emu1010_input_dst)); 480 481 static const unsigned short emu0404_input_dflt[] = { 482 EMU_SRC_HAMOA_ADC_LEFT1, 483 EMU_SRC_HAMOA_ADC_RIGHT1, 484 EMU_SRC_SILENCE, 485 EMU_SRC_SILENCE, 486 EMU_SRC_SILENCE, 487 EMU_SRC_SILENCE, 488 EMU_SRC_SILENCE, 489 EMU_SRC_SILENCE, 490 EMU_SRC_HANA_SPDIF_LEFT1, 491 EMU_SRC_HANA_SPDIF_RIGHT1, 492 EMU_SRC_SILENCE, 493 EMU_SRC_SILENCE, 494 EMU_SRC_SILENCE, 495 EMU_SRC_SILENCE, 496 EMU_SRC_SILENCE, 497 EMU_SRC_SILENCE, 498 }; 499 500 struct snd_emu1010_routing_info { 501 const char * const *src_texts; 502 const char * const *out_texts; 503 const unsigned short *src_regs; 504 const unsigned short *out_regs; 505 const unsigned short *in_regs; 506 const unsigned short *out_dflts; 507 const unsigned short *in_dflts; 508 unsigned n_srcs; 509 unsigned n_outs; 510 unsigned n_ins; 511 }; 512 513 static const struct snd_emu1010_routing_info emu1010_routing_info[] = { 514 { 515 /* rev1 1010 */ 516 .src_regs = emu1010_src_regs, 517 .src_texts = emu1010_src_texts, 518 .n_srcs = ARRAY_SIZE(emu1010_src_texts), 519 520 .out_dflts = emu1010_output_dflt, 521 .out_regs = emu1010_output_dst, 522 .out_texts = emu1010_output_texts, 523 .n_outs = ARRAY_SIZE(emu1010_output_dst), 524 525 .in_dflts = emu1010_input_dflt, 526 .in_regs = emu1010_input_dst, 527 .n_ins = ARRAY_SIZE(emu1010_input_dst), 528 }, 529 { 530 /* rev2 1010 */ 531 .src_regs = emu1010b_src_regs, 532 .src_texts = emu1010b_src_texts, 533 .n_srcs = ARRAY_SIZE(emu1010b_src_texts), 534 535 .out_dflts = emu1010b_output_dflt, 536 .out_regs = emu1010b_output_dst, 537 .out_texts = snd_emu1010b_output_texts, 538 .n_outs = ARRAY_SIZE(emu1010b_output_dst), 539 540 .in_dflts = emu1010_input_dflt, 541 .in_regs = emu1010_input_dst, 542 .n_ins = ARRAY_SIZE(emu1010_input_dst) - 6, 543 }, 544 { 545 /* 1616(m) cardbus */ 546 .src_regs = emu1616_src_regs, 547 .src_texts = emu1616_src_texts, 548 .n_srcs = ARRAY_SIZE(emu1616_src_texts), 549 550 .out_dflts = emu1616_output_dflt, 551 .out_regs = emu1616_output_dst, 552 .out_texts = snd_emu1616_output_texts, 553 .n_outs = ARRAY_SIZE(emu1616_output_dst), 554 555 .in_dflts = emu1010_input_dflt, 556 .in_regs = emu1010_input_dst, 557 .n_ins = ARRAY_SIZE(emu1010_input_dst) - 6, 558 }, 559 { 560 /* 0404 */ 561 .src_regs = emu0404_src_regs, 562 .src_texts = emu0404_src_texts, 563 .n_srcs = ARRAY_SIZE(emu0404_src_texts), 564 565 .out_dflts = emu0404_output_dflt, 566 .out_regs = emu0404_output_dst, 567 .out_texts = snd_emu0404_output_texts, 568 .n_outs = ARRAY_SIZE(emu0404_output_dflt), 569 570 .in_dflts = emu0404_input_dflt, 571 .in_regs = emu1010_input_dst, 572 .n_ins = ARRAY_SIZE(emu1010_input_dst) - 6, 573 }, 574 }; 575 576 static unsigned emu1010_idx(struct snd_emu10k1 *emu) 577 { 578 return emu->card_capabilities->emu_model - 1; 579 } 580 581 static void snd_emu1010_output_source_apply(struct snd_emu10k1 *emu, 582 int channel, int src) 583 { 584 const struct snd_emu1010_routing_info *emu_ri = 585 &emu1010_routing_info[emu1010_idx(emu)]; 586 587 snd_emu1010_fpga_link_dst_src_write(emu, 588 emu_ri->out_regs[channel], emu_ri->src_regs[src]); 589 } 590 591 static void snd_emu1010_input_source_apply(struct snd_emu10k1 *emu, 592 int channel, int src) 593 { 594 const struct snd_emu1010_routing_info *emu_ri = 595 &emu1010_routing_info[emu1010_idx(emu)]; 596 597 snd_emu1010_fpga_link_dst_src_write(emu, 598 emu_ri->in_regs[channel], emu_ri->src_regs[src]); 599 } 600 601 static void snd_emu1010_apply_sources(struct snd_emu10k1 *emu) 602 { 603 const struct snd_emu1010_routing_info *emu_ri = 604 &emu1010_routing_info[emu1010_idx(emu)]; 605 606 for (unsigned i = 0; i < emu_ri->n_outs; i++) 607 snd_emu1010_output_source_apply( 608 emu, i, emu->emu1010.output_source[i]); 609 for (unsigned i = 0; i < emu_ri->n_ins; i++) 610 snd_emu1010_input_source_apply( 611 emu, i, emu->emu1010.input_source[i]); 612 } 613 614 static u8 emu1010_map_source(const struct snd_emu1010_routing_info *emu_ri, 615 unsigned val) 616 { 617 for (unsigned i = 0; i < emu_ri->n_srcs; i++) 618 if (val == emu_ri->src_regs[i]) 619 return i; 620 return 0; 621 } 377 622 378 623 static int snd_emu1010_input_output_source_info(struct snd_kcontrol *kcontrol, … … 380 625 { 381 626 struct snd_emu10k1 *emu = snd_kcontrol_chip(kcontrol); 382 383 if (emu->card_capabilities->emu_model == EMU_MODEL_EMU1616) 384 return snd_ctl_enum_info(uinfo, 1, 49, emu1616_src_texts); 385 else 386 return snd_ctl_enum_info(uinfo, 1, 53, emu1010_src_texts); 627 const struct snd_emu1010_routing_info *emu_ri = 628 &emu1010_routing_info[emu1010_idx(emu)]; 629 630 return snd_ctl_enum_info(uinfo, 1, emu_ri->n_srcs, emu_ri->src_texts); 387 631 } 388 632 … … 391 635 { 392 636 struct snd_emu10k1 *emu = snd_kcontrol_chip(kcontrol); 393 unsigned int channel; 394 395 channel = (kcontrol->private_value) & 0xff; 396 /* Limit: emu1010_output_dst, emu->emu1010.output_source */ 397 if (channel >= 24 || 398 (emu->card_capabilities->emu_model == EMU_MODEL_EMU1616 && 399 channel >= 18)) 637 const struct snd_emu1010_routing_info *emu_ri = 638 &emu1010_routing_info[emu1010_idx(emu)]; 639 unsigned channel = kcontrol->private_value; 640 641 if (channel >= emu_ri->n_outs) 400 642 return -EINVAL; 401 643 ucontrol->value.enumerated.item[0] = emu->emu1010.output_source[channel]; … … 407 649 { 408 650 struct snd_emu10k1 *emu = snd_kcontrol_chip(kcontrol); 409 unsigned int val;410 unsigned int channel;411 412 val = ucontrol->value.enumerated.item[0];413 i f (val >= 53 ||414 (emu->card_capabilities->emu_model == EMU_MODEL_EMU1616 && 415 val >= 49))651 const struct snd_emu1010_routing_info *emu_ri = 652 &emu1010_routing_info[emu1010_idx(emu)]; 653 unsigned val = ucontrol->value.enumerated.item[0]; 654 unsigned channel = kcontrol->private_value; 655 int change; 656 657 if (val >= emu_ri->n_srcs) 416 658 return -EINVAL; 417 channel = (kcontrol->private_value) & 0xff; 418 /* Limit: emu1010_output_dst, emu->emu1010.output_source */ 419 if (channel >= 24 || 420 (emu->card_capabilities->emu_model == EMU_MODEL_EMU1616 && 421 channel >= 18)) 659 if (channel >= emu_ri->n_outs) 422 660 return -EINVAL; 423 if (emu->emu1010.output_source[channel] == val) 424 return 0; 425 emu->emu1010.output_source[channel] = val; 426 if (emu->card_capabilities->emu_model == EMU_MODEL_EMU1616) 427 snd_emu1010_fpga_link_dst_src_write(emu, 428 emu1616_output_dst[channel], emu1616_src_regs[val]); 429 else 430 snd_emu1010_fpga_link_dst_src_write(emu, 431 emu1010_output_dst[channel], emu1010_src_regs[val]); 432 return 1; 433 } 661 change = (emu->emu1010.output_source[channel] != val); 662 if (change) { 663 emu->emu1010.output_source[channel] = val; 664 snd_emu1010_output_source_apply(emu, channel, val); 665 } 666 return change; 667 } 668 669 static const struct snd_kcontrol_new emu1010_output_source_ctl = { 670 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, 671 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE, 672 .info = snd_emu1010_input_output_source_info, 673 .get = snd_emu1010_output_source_get, 674 .put = snd_emu1010_output_source_put 675 }; 434 676 435 677 static int snd_emu1010_input_source_get(struct snd_kcontrol *kcontrol, … … 437 679 { 438 680 struct snd_emu10k1 *emu = snd_kcontrol_chip(kcontrol); 439 unsigned int channel;440 441 channel = (kcontrol->private_value) & 0xff;442 /* Limit: emu1010_input_dst, emu->emu1010.input_source */ 443 if (channel >= 22)681 const struct snd_emu1010_routing_info *emu_ri = 682 &emu1010_routing_info[emu1010_idx(emu)]; 683 unsigned channel = kcontrol->private_value; 684 685 if (channel >= emu_ri->n_ins) 444 686 return -EINVAL; 445 687 ucontrol->value.enumerated.item[0] = emu->emu1010.input_source[channel]; … … 451 693 { 452 694 struct snd_emu10k1 *emu = snd_kcontrol_chip(kcontrol); 453 unsigned int val;454 unsigned int channel;455 456 val = ucontrol->value.enumerated.item[0];457 i f (val >= 53 ||458 (emu->card_capabilities->emu_model == EMU_MODEL_EMU1616 && 459 val >= 49))695 const struct snd_emu1010_routing_info *emu_ri = 696 &emu1010_routing_info[emu1010_idx(emu)]; 697 unsigned val = ucontrol->value.enumerated.item[0]; 698 unsigned channel = kcontrol->private_value; 699 int change; 700 701 if (val >= emu_ri->n_srcs) 460 702 return -EINVAL; 461 channel = (kcontrol->private_value) & 0xff; 462 /* Limit: emu1010_input_dst, emu->emu1010.input_source */ 463 if (channel >= 22) 703 if (channel >= emu_ri->n_ins) 464 704 return -EINVAL; 465 if (emu->emu1010.input_source[channel] == val) 466 return 0; 467 emu->emu1010.input_source[channel] = val; 468 if (emu->card_capabilities->emu_model == EMU_MODEL_EMU1616) 469 snd_emu1010_fpga_link_dst_src_write(emu, 470 emu1010_input_dst[channel], emu1616_src_regs[val]); 471 else 472 snd_emu1010_fpga_link_dst_src_write(emu, 473 emu1010_input_dst[channel], emu1010_src_regs[val]); 474 return 1; 475 } 476 477 #define EMU1010_SOURCE_OUTPUT(xname,chid) \ 478 { \ 479 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ 480 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE, \ 481 .info = snd_emu1010_input_output_source_info, \ 482 .get = snd_emu1010_output_source_get, \ 483 .put = snd_emu1010_output_source_put, \ 484 .private_value = chid \ 485 } 486 487 static const struct snd_kcontrol_new snd_emu1010_output_enum_ctls[] = { 488 EMU1010_SOURCE_OUTPUT("Dock DAC1 Left Playback Enum", 0), 489 EMU1010_SOURCE_OUTPUT("Dock DAC1 Right Playback Enum", 1), 490 EMU1010_SOURCE_OUTPUT("Dock DAC2 Left Playback Enum", 2), 491 EMU1010_SOURCE_OUTPUT("Dock DAC2 Right Playback Enum", 3), 492 EMU1010_SOURCE_OUTPUT("Dock DAC3 Left Playback Enum", 4), 493 EMU1010_SOURCE_OUTPUT("Dock DAC3 Right Playback Enum", 5), 494 EMU1010_SOURCE_OUTPUT("Dock DAC4 Left Playback Enum", 6), 495 EMU1010_SOURCE_OUTPUT("Dock DAC4 Right Playback Enum", 7), 496 EMU1010_SOURCE_OUTPUT("Dock Phones Left Playback Enum", 8), 497 EMU1010_SOURCE_OUTPUT("Dock Phones Right Playback Enum", 9), 498 EMU1010_SOURCE_OUTPUT("Dock SPDIF Left Playback Enum", 0xa), 499 EMU1010_SOURCE_OUTPUT("Dock SPDIF Right Playback Enum", 0xb), 500 EMU1010_SOURCE_OUTPUT("1010 SPDIF Left Playback Enum", 0xc), 501 EMU1010_SOURCE_OUTPUT("1010 SPDIF Right Playback Enum", 0xd), 502 EMU1010_SOURCE_OUTPUT("0202 DAC Left Playback Enum", 0xe), 503 EMU1010_SOURCE_OUTPUT("0202 DAC Right Playback Enum", 0xf), 504 EMU1010_SOURCE_OUTPUT("1010 ADAT 0 Playback Enum", 0x10), 505 EMU1010_SOURCE_OUTPUT("1010 ADAT 1 Playback Enum", 0x11), 506 EMU1010_SOURCE_OUTPUT("1010 ADAT 2 Playback Enum", 0x12), 507 EMU1010_SOURCE_OUTPUT("1010 ADAT 3 Playback Enum", 0x13), 508 EMU1010_SOURCE_OUTPUT("1010 ADAT 4 Playback Enum", 0x14), 509 EMU1010_SOURCE_OUTPUT("1010 ADAT 5 Playback Enum", 0x15), 510 EMU1010_SOURCE_OUTPUT("1010 ADAT 6 Playback Enum", 0x16), 511 EMU1010_SOURCE_OUTPUT("1010 ADAT 7 Playback Enum", 0x17), 512 }; 513 514 515 /* 1616(m) cardbus */ 516 static const struct snd_kcontrol_new snd_emu1616_output_enum_ctls[] = { 517 EMU1010_SOURCE_OUTPUT("Dock DAC1 Left Playback Enum", 0), 518 EMU1010_SOURCE_OUTPUT("Dock DAC1 Right Playback Enum", 1), 519 EMU1010_SOURCE_OUTPUT("Dock DAC2 Left Playback Enum", 2), 520 EMU1010_SOURCE_OUTPUT("Dock DAC2 Right Playback Enum", 3), 521 EMU1010_SOURCE_OUTPUT("Dock DAC3 Left Playback Enum", 4), 522 EMU1010_SOURCE_OUTPUT("Dock DAC3 Right Playback Enum", 5), 523 EMU1010_SOURCE_OUTPUT("Dock SPDIF Left Playback Enum", 6), 524 EMU1010_SOURCE_OUTPUT("Dock SPDIF Right Playback Enum", 7), 525 EMU1010_SOURCE_OUTPUT("Dock ADAT 0 Playback Enum", 8), 526 EMU1010_SOURCE_OUTPUT("Dock ADAT 1 Playback Enum", 9), 527 EMU1010_SOURCE_OUTPUT("Dock ADAT 2 Playback Enum", 0xa), 528 EMU1010_SOURCE_OUTPUT("Dock ADAT 3 Playback Enum", 0xb), 529 EMU1010_SOURCE_OUTPUT("Dock ADAT 4 Playback Enum", 0xc), 530 EMU1010_SOURCE_OUTPUT("Dock ADAT 5 Playback Enum", 0xd), 531 EMU1010_SOURCE_OUTPUT("Dock ADAT 6 Playback Enum", 0xe), 532 EMU1010_SOURCE_OUTPUT("Dock ADAT 7 Playback Enum", 0xf), 533 EMU1010_SOURCE_OUTPUT("Mana DAC Left Playback Enum", 0x10), 534 EMU1010_SOURCE_OUTPUT("Mana DAC Right Playback Enum", 0x11), 535 }; 536 537 538 #define EMU1010_SOURCE_INPUT(xname,chid) \ 539 { \ 540 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ 541 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE, \ 542 .info = snd_emu1010_input_output_source_info, \ 543 .get = snd_emu1010_input_source_get, \ 544 .put = snd_emu1010_input_source_put, \ 545 .private_value = chid \ 546 } 547 548 static const struct snd_kcontrol_new snd_emu1010_input_enum_ctls[] = { 549 EMU1010_SOURCE_INPUT("DSP 0 Capture Enum", 0), 550 EMU1010_SOURCE_INPUT("DSP 1 Capture Enum", 1), 551 EMU1010_SOURCE_INPUT("DSP 2 Capture Enum", 2), 552 EMU1010_SOURCE_INPUT("DSP 3 Capture Enum", 3), 553 EMU1010_SOURCE_INPUT("DSP 4 Capture Enum", 4), 554 EMU1010_SOURCE_INPUT("DSP 5 Capture Enum", 5), 555 EMU1010_SOURCE_INPUT("DSP 6 Capture Enum", 6), 556 EMU1010_SOURCE_INPUT("DSP 7 Capture Enum", 7), 557 EMU1010_SOURCE_INPUT("DSP 8 Capture Enum", 8), 558 EMU1010_SOURCE_INPUT("DSP 9 Capture Enum", 9), 559 EMU1010_SOURCE_INPUT("DSP A Capture Enum", 0xa), 560 EMU1010_SOURCE_INPUT("DSP B Capture Enum", 0xb), 561 EMU1010_SOURCE_INPUT("DSP C Capture Enum", 0xc), 562 EMU1010_SOURCE_INPUT("DSP D Capture Enum", 0xd), 563 EMU1010_SOURCE_INPUT("DSP E Capture Enum", 0xe), 564 EMU1010_SOURCE_INPUT("DSP F Capture Enum", 0xf), 565 EMU1010_SOURCE_INPUT("DSP 10 Capture Enum", 0x10), 566 EMU1010_SOURCE_INPUT("DSP 11 Capture Enum", 0x11), 567 EMU1010_SOURCE_INPUT("DSP 12 Capture Enum", 0x12), 568 EMU1010_SOURCE_INPUT("DSP 13 Capture Enum", 0x13), 569 EMU1010_SOURCE_INPUT("DSP 14 Capture Enum", 0x14), 570 EMU1010_SOURCE_INPUT("DSP 15 Capture Enum", 0x15), 571 }; 572 573 705 change = (emu->emu1010.input_source[channel] != val); 706 if (change) { 707 emu->emu1010.input_source[channel] = val; 708 snd_emu1010_input_source_apply(emu, channel, val); 709 } 710 return change; 711 } 712 713 static const struct snd_kcontrol_new emu1010_input_source_ctl = { 714 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, 715 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE, 716 .info = snd_emu1010_input_output_source_info, 717 .get = snd_emu1010_input_source_get, 718 .put = snd_emu1010_input_source_put 719 }; 720 721 static int add_emu1010_source_mixers(struct snd_emu10k1 *emu) 722 { 723 const struct snd_emu1010_routing_info *emu_ri = 724 &emu1010_routing_info[emu1010_idx(emu)]; 725 int err; 726 727 err = add_ctls(emu, &emu1010_output_source_ctl, 728 emu_ri->out_texts, emu_ri->n_outs); 729 if (err < 0) 730 return err; 731 err = add_ctls(emu, &emu1010_input_source_ctl, 732 emu1010_input_texts, emu_ri->n_ins); 733 return err; 734 } 735 736 737 static const char * const snd_emu1010_adc_pads[] = { 738 "ADC1 14dB PAD 0202 Capture Switch", 739 "ADC1 14dB PAD Audio Dock Capture Switch", 740 "ADC2 14dB PAD Audio Dock Capture Switch", 741 "ADC3 14dB PAD Audio Dock Capture Switch", 742 }; 743 744 static const unsigned short snd_emu1010_adc_pad_regs[] = { 745 EMU_HANA_0202_ADC_PAD1, 746 EMU_HANA_DOCK_ADC_PAD1, 747 EMU_HANA_DOCK_ADC_PAD2, 748 EMU_HANA_DOCK_ADC_PAD3, 749 }; 574 750 575 751 #define snd_emu1010_adc_pads_info snd_ctl_boolean_mono_info … … 578 754 { 579 755 struct snd_emu10k1 *emu = snd_kcontrol_chip(kcontrol); 580 unsigned int mask = kcontrol->private_value & 0xff; 756 unsigned int mask = snd_emu1010_adc_pad_regs[kcontrol->private_value]; 757 581 758 ucontrol->value.integer.value[0] = (emu->emu1010.adc_pads & mask) ? 1 : 0; 582 759 return 0; … … 586 763 { 587 764 struct snd_emu10k1 *emu = snd_kcontrol_chip(kcontrol); 588 unsigned int mask = kcontrol->private_value & 0xff;765 unsigned int mask = snd_emu1010_adc_pad_regs[kcontrol->private_value]; 589 766 unsigned int val, cache; 767 int change; 768 590 769 val = ucontrol->value.integer.value[0]; 591 770 cache = emu->emu1010.adc_pads; … … 594 773 else 595 774 cache = cache & ~mask; 596 if (cache != emu->emu1010.adc_pads) { 775 change = (cache != emu->emu1010.adc_pads); 776 if (change) { 597 777 snd_emu1010_fpga_write(emu, EMU_HANA_ADC_PADS, cache ); 598 778 emu->emu1010.adc_pads = cache; 599 779 } 600 780 601 return 0; 602 } 603 604 605 606 #define EMU1010_ADC_PADS(xname,chid) \ 607 { \ 608 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ 609 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE, \ 610 .info = snd_emu1010_adc_pads_info, \ 611 .get = snd_emu1010_adc_pads_get, \ 612 .put = snd_emu1010_adc_pads_put, \ 613 .private_value = chid \ 614 } 615 616 static const struct snd_kcontrol_new snd_emu1010_adc_pads[] = { 617 EMU1010_ADC_PADS("ADC1 14dB PAD Audio Dock Capture Switch", EMU_HANA_DOCK_ADC_PAD1), 618 EMU1010_ADC_PADS("ADC2 14dB PAD Audio Dock Capture Switch", EMU_HANA_DOCK_ADC_PAD2), 619 EMU1010_ADC_PADS("ADC3 14dB PAD Audio Dock Capture Switch", EMU_HANA_DOCK_ADC_PAD3), 620 EMU1010_ADC_PADS("ADC1 14dB PAD 0202 Capture Switch", EMU_HANA_0202_ADC_PAD1), 781 return change; 782 } 783 784 static const struct snd_kcontrol_new emu1010_adc_pads_ctl = { 785 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, 786 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE, 787 .info = snd_emu1010_adc_pads_info, 788 .get = snd_emu1010_adc_pads_get, 789 .put = snd_emu1010_adc_pads_put 790 }; 791 792 793 static const char * const snd_emu1010_dac_pads[] = { 794 "DAC1 0202 14dB PAD Playback Switch", 795 "DAC1 Audio Dock 14dB PAD Playback Switch", 796 "DAC2 Audio Dock 14dB PAD Playback Switch", 797 "DAC3 Audio Dock 14dB PAD Playback Switch", 798 "DAC4 Audio Dock 14dB PAD Playback Switch", 799 }; 800 801 static const unsigned short snd_emu1010_dac_regs[] = { 802 EMU_HANA_0202_DAC_PAD1, 803 EMU_HANA_DOCK_DAC_PAD1, 804 EMU_HANA_DOCK_DAC_PAD2, 805 EMU_HANA_DOCK_DAC_PAD3, 806 EMU_HANA_DOCK_DAC_PAD4, 621 807 }; 622 808 … … 626 812 { 627 813 struct snd_emu10k1 *emu = snd_kcontrol_chip(kcontrol); 628 unsigned int mask = kcontrol->private_value & 0xff; 814 unsigned int mask = snd_emu1010_dac_regs[kcontrol->private_value]; 815 629 816 ucontrol->value.integer.value[0] = (emu->emu1010.dac_pads & mask) ? 1 : 0; 630 817 return 0; … … 634 821 { 635 822 struct snd_emu10k1 *emu = snd_kcontrol_chip(kcontrol); 636 unsigned int mask = kcontrol->private_value & 0xff;823 unsigned int mask = snd_emu1010_dac_regs[kcontrol->private_value]; 637 824 unsigned int val, cache; 825 int change; 826 638 827 val = ucontrol->value.integer.value[0]; 639 828 cache = emu->emu1010.dac_pads; … … 642 831 else 643 832 cache = cache & ~mask; 644 if (cache != emu->emu1010.dac_pads) { 833 change = (cache != emu->emu1010.dac_pads); 834 if (change) { 645 835 snd_emu1010_fpga_write(emu, EMU_HANA_DAC_PADS, cache ); 646 836 emu->emu1010.dac_pads = cache; 647 837 } 648 838 649 return 0; 650 } 651 652 653 654 #define EMU1010_DAC_PADS(xname,chid) \ 655 { \ 656 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ 657 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE, \ 658 .info = snd_emu1010_dac_pads_info, \ 659 .get = snd_emu1010_dac_pads_get, \ 660 .put = snd_emu1010_dac_pads_put, \ 661 .private_value = chid \ 662 } 663 664 static const struct snd_kcontrol_new snd_emu1010_dac_pads[] = { 665 EMU1010_DAC_PADS("DAC1 Audio Dock 14dB PAD Playback Switch", EMU_HANA_DOCK_DAC_PAD1), 666 EMU1010_DAC_PADS("DAC2 Audio Dock 14dB PAD Playback Switch", EMU_HANA_DOCK_DAC_PAD2), 667 EMU1010_DAC_PADS("DAC3 Audio Dock 14dB PAD Playback Switch", EMU_HANA_DOCK_DAC_PAD3), 668 EMU1010_DAC_PADS("DAC4 Audio Dock 14dB PAD Playback Switch", EMU_HANA_DOCK_DAC_PAD4), 669 EMU1010_DAC_PADS("DAC1 0202 14dB PAD Playback Switch", EMU_HANA_0202_DAC_PAD1), 670 }; 671 672 673 static int snd_emu1010_internal_clock_info(struct snd_kcontrol *kcontrol, 839 return change; 840 } 841 842 static const struct snd_kcontrol_new emu1010_dac_pads_ctl = { 843 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, 844 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE, 845 .info = snd_emu1010_dac_pads_info, 846 .get = snd_emu1010_dac_pads_get, 847 .put = snd_emu1010_dac_pads_put 848 }; 849 850 851 struct snd_emu1010_pads_info { 852 const char * const *adc_ctls, * const *dac_ctls; 853 unsigned n_adc_ctls, n_dac_ctls; 854 }; 855 856 static const struct snd_emu1010_pads_info emu1010_pads_info[] = { 857 { 858 /* rev1 1010 */ 859 .adc_ctls = snd_emu1010_adc_pads, 860 .n_adc_ctls = ARRAY_SIZE(snd_emu1010_adc_pads), 861 .dac_ctls = snd_emu1010_dac_pads, 862 .n_dac_ctls = ARRAY_SIZE(snd_emu1010_dac_pads), 863 }, 864 { 865 /* rev2 1010 */ 866 .adc_ctls = snd_emu1010_adc_pads, 867 .n_adc_ctls = ARRAY_SIZE(snd_emu1010_adc_pads) - 1, 868 .dac_ctls = snd_emu1010_dac_pads, 869 .n_dac_ctls = ARRAY_SIZE(snd_emu1010_dac_pads) - 1, 870 }, 871 { 872 /* 1616(m) cardbus */ 873 .adc_ctls = snd_emu1010_adc_pads + 1, 874 .n_adc_ctls = ARRAY_SIZE(snd_emu1010_adc_pads) - 2, 875 .dac_ctls = snd_emu1010_dac_pads + 1, 876 .n_dac_ctls = ARRAY_SIZE(snd_emu1010_dac_pads) - 2, 877 }, 878 { 879 /* 0404 */ 880 .adc_ctls = NULL, 881 .n_adc_ctls = 0, 882 .dac_ctls = NULL, 883 .n_dac_ctls = 0, 884 }, 885 }; 886 887 static const char * const emu1010_clock_texts[] = { 888 "44100", "48000", "SPDIF", "ADAT", "Dock", "BNC" 889 }; 890 891 static const u8 emu1010_clock_vals[] = { 892 EMU_HANA_WCLOCK_INT_44_1K, 893 EMU_HANA_WCLOCK_INT_48K, 894 EMU_HANA_WCLOCK_HANA_SPDIF_IN, 895 EMU_HANA_WCLOCK_HANA_ADAT_IN, 896 EMU_HANA_WCLOCK_2ND_HANA, 897 EMU_HANA_WCLOCK_SYNC_BNC, 898 }; 899 900 static const char * const emu0404_clock_texts[] = { 901 "44100", "48000", "SPDIF", "BNC" 902 }; 903 904 static const u8 emu0404_clock_vals[] = { 905 EMU_HANA_WCLOCK_INT_44_1K, 906 EMU_HANA_WCLOCK_INT_48K, 907 EMU_HANA_WCLOCK_HANA_SPDIF_IN, 908 EMU_HANA_WCLOCK_SYNC_BNC, 909 }; 910 911 struct snd_emu1010_clock_info { 912 const char * const *texts; 913 const u8 *vals; 914 unsigned num; 915 }; 916 917 static const struct snd_emu1010_clock_info emu1010_clock_info[] = { 918 { 919 // rev1 1010 920 .texts = emu1010_clock_texts, 921 .vals = emu1010_clock_vals, 922 .num = ARRAY_SIZE(emu1010_clock_vals), 923 }, 924 { 925 // rev2 1010 926 .texts = emu1010_clock_texts, 927 .vals = emu1010_clock_vals, 928 .num = ARRAY_SIZE(emu1010_clock_vals) - 1, 929 }, 930 { 931 // 1616(m) CardBus 932 .texts = emu1010_clock_texts, 933 // TODO: determine what is actually available. 934 // Pedantically, *every* source comes from the 2nd FPGA, as the 935 // card itself has no own (digital) audio ports. The user manual 936 // claims that ADAT and S/PDIF clock sources are separate, which 937 // can mean two things: either E-MU mapped the dock's sources to 938 // the primary ones, or they determine the meaning of the "Dock" 939 // source depending on how the ports are actually configured 940 // (which the 2nd FPGA must be doing anyway). 941 .vals = emu1010_clock_vals, 942 .num = ARRAY_SIZE(emu1010_clock_vals), 943 }, 944 { 945 // 0404 946 .texts = emu0404_clock_texts, 947 .vals = emu0404_clock_vals, 948 .num = ARRAY_SIZE(emu0404_clock_vals), 949 }, 950 }; 951 952 static int snd_emu1010_clock_source_info(struct snd_kcontrol *kcontrol, 674 953 struct snd_ctl_elem_info *uinfo) 675 954 { 676 st atic const char * const texts[4] = {677 "44100", "48000", "SPDIF", "ADAT"678 };955 struct snd_emu10k1 *emu = snd_kcontrol_chip(kcontrol); 956 const struct snd_emu1010_clock_info *emu_ci = 957 &emu1010_clock_info[emu1010_idx(emu)]; 679 958 680 return snd_ctl_enum_info(uinfo, 1, 4,texts);681 } 682 683 static int snd_emu1010_ internal_clock_get(struct snd_kcontrol *kcontrol,959 return snd_ctl_enum_info(uinfo, 1, emu_ci->num, emu_ci->texts); 960 } 961 962 static int snd_emu1010_clock_source_get(struct snd_kcontrol *kcontrol, 684 963 struct snd_ctl_elem_value *ucontrol) 685 964 { 686 965 struct snd_emu10k1 *emu = snd_kcontrol_chip(kcontrol); 687 966 688 ucontrol->value.enumerated.item[0] = emu->emu1010. internal_clock;689 return 0; 690 } 691 692 static int snd_emu1010_ internal_clock_put(struct snd_kcontrol *kcontrol,967 ucontrol->value.enumerated.item[0] = emu->emu1010.clock_source; 968 return 0; 969 } 970 971 static int snd_emu1010_clock_source_put(struct snd_kcontrol *kcontrol, 693 972 struct snd_ctl_elem_value *ucontrol) 694 973 { 695 974 struct snd_emu10k1 *emu = snd_kcontrol_chip(kcontrol); 975 const struct snd_emu1010_clock_info *emu_ci = 976 &emu1010_clock_info[emu1010_idx(emu)]; 696 977 unsigned int val; 697 978 int change = 0; 698 979 699 980 val = ucontrol->value.enumerated.item[0] ; 700 /* Limit: uinfo->value.enumerated.items = 4; */ 701 if (val >= 4) 981 if (val >= emu_ci->num) 702 982 return -EINVAL; 703 change = (emu->emu1010.internal_clock != val); 983 spin_lock_irq(&emu->reg_lock); 984 change = (emu->emu1010.clock_source != val); 704 985 if (change) { 705 emu->emu1010.internal_clock = val; 706 switch (val) { 707 case 0: 708 /* 44100 */ 709 /* Mute all */ 710 snd_emu1010_fpga_write(emu, EMU_HANA_UNMUTE, EMU_MUTE ); 711 /* Default fallback clock 48kHz */ 712 snd_emu1010_fpga_write(emu, EMU_HANA_DEFCLOCK, EMU_HANA_DEFCLOCK_44_1K ); 713 /* Word Clock source, Internal 44.1kHz x1 */ 714 snd_emu1010_fpga_write(emu, EMU_HANA_WCLOCK, 715 EMU_HANA_WCLOCK_INT_44_1K | EMU_HANA_WCLOCK_1X ); 716 /* Set LEDs on Audio Dock */ 717 snd_emu1010_fpga_write(emu, EMU_HANA_DOCK_LEDS_2, 718 EMU_HANA_DOCK_LEDS_2_44K | EMU_HANA_DOCK_LEDS_2_LOCK ); 719 /* Allow DLL to settle */ 720 msleep(10); 721 /* Unmute all */ 722 snd_emu1010_fpga_write(emu, EMU_HANA_UNMUTE, EMU_UNMUTE ); 723 break; 724 case 1: 725 /* 48000 */ 726 /* Mute all */ 727 snd_emu1010_fpga_write(emu, EMU_HANA_UNMUTE, EMU_MUTE ); 728 /* Default fallback clock 48kHz */ 729 snd_emu1010_fpga_write(emu, EMU_HANA_DEFCLOCK, EMU_HANA_DEFCLOCK_48K ); 730 /* Word Clock source, Internal 48kHz x1 */ 731 snd_emu1010_fpga_write(emu, EMU_HANA_WCLOCK, 732 EMU_HANA_WCLOCK_INT_48K | EMU_HANA_WCLOCK_1X ); 733 /* Set LEDs on Audio Dock */ 734 snd_emu1010_fpga_write(emu, EMU_HANA_DOCK_LEDS_2, 735 EMU_HANA_DOCK_LEDS_2_48K | EMU_HANA_DOCK_LEDS_2_LOCK ); 736 /* Allow DLL to settle */ 737 msleep(10); 738 /* Unmute all */ 739 snd_emu1010_fpga_write(emu, EMU_HANA_UNMUTE, EMU_UNMUTE ); 740 break; 741 742 case 2: /* Take clock from S/PDIF IN */ 743 /* Mute all */ 744 snd_emu1010_fpga_write(emu, EMU_HANA_UNMUTE, EMU_MUTE ); 745 /* Default fallback clock 48kHz */ 746 snd_emu1010_fpga_write(emu, EMU_HANA_DEFCLOCK, EMU_HANA_DEFCLOCK_48K ); 747 /* Word Clock source, sync to S/PDIF input */ 748 snd_emu1010_fpga_write(emu, EMU_HANA_WCLOCK, 749 EMU_HANA_WCLOCK_HANA_SPDIF_IN | EMU_HANA_WCLOCK_1X ); 750 /* Set LEDs on Audio Dock */ 751 snd_emu1010_fpga_write(emu, EMU_HANA_DOCK_LEDS_2, 752 EMU_HANA_DOCK_LEDS_2_EXT | EMU_HANA_DOCK_LEDS_2_LOCK ); 753 /* FIXME: We should set EMU_HANA_DOCK_LEDS_2_LOCK only when clock signal is present and valid */ 754 /* Allow DLL to settle */ 755 msleep(10); 756 /* Unmute all */ 757 snd_emu1010_fpga_write(emu, EMU_HANA_UNMUTE, EMU_UNMUTE ); 758 break; 759 760 case 3: 761 /* Take clock from ADAT IN */ 762 /* Mute all */ 763 snd_emu1010_fpga_write(emu, EMU_HANA_UNMUTE, EMU_MUTE ); 764 /* Default fallback clock 48kHz */ 765 snd_emu1010_fpga_write(emu, EMU_HANA_DEFCLOCK, EMU_HANA_DEFCLOCK_48K ); 766 /* Word Clock source, sync to ADAT input */ 767 snd_emu1010_fpga_write(emu, EMU_HANA_WCLOCK, 768 EMU_HANA_WCLOCK_HANA_ADAT_IN | EMU_HANA_WCLOCK_1X ); 769 /* Set LEDs on Audio Dock */ 770 snd_emu1010_fpga_write(emu, EMU_HANA_DOCK_LEDS_2, EMU_HANA_DOCK_LEDS_2_EXT | EMU_HANA_DOCK_LEDS_2_LOCK ); 771 /* FIXME: We should set EMU_HANA_DOCK_LEDS_2_LOCK only when clock signal is present and valid */ 772 /* Allow DLL to settle */ 773 msleep(10); 774 /* Unmute all */ 775 snd_emu1010_fpga_write(emu, EMU_HANA_UNMUTE, EMU_UNMUTE ); 776 777 778 break; 779 } 780 } 781 return change; 782 } 783 784 static const struct snd_kcontrol_new snd_emu1010_internal_clock = 785 { 786 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE, 787 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, 788 .name = "Clock Internal Rate", 789 .count = 1, 790 .info = snd_emu1010_internal_clock_info, 791 .get = snd_emu1010_internal_clock_get, 792 .put = snd_emu1010_internal_clock_put 986 emu->emu1010.clock_source = val; 987 emu->emu1010.wclock = emu_ci->vals[val]; 988 snd_emu1010_update_clock(emu); 989 990 snd_emu1010_fpga_write(emu, EMU_HANA_UNMUTE, EMU_MUTE); 991 snd_emu1010_fpga_write(emu, EMU_HANA_WCLOCK, emu->emu1010.wclock); 992 spin_unlock_irq(&emu->reg_lock); 993 994 msleep(10); // Allow DLL to settle 995 snd_emu1010_fpga_write(emu, EMU_HANA_UNMUTE, EMU_UNMUTE); 996 } else { 997 spin_unlock_irq(&emu->reg_lock); 998 } 999 return change; 1000 } 1001 1002 static const struct snd_kcontrol_new snd_emu1010_clock_source = 1003 { 1004 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE, 1005 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, 1006 .name = "Clock Source", 1007 .count = 1, 1008 .info = snd_emu1010_clock_source_info, 1009 .get = snd_emu1010_clock_source_get, 1010 .put = snd_emu1010_clock_source_put 1011 }; 1012 1013 static int snd_emu1010_clock_fallback_info(struct snd_kcontrol *kcontrol, 1014 struct snd_ctl_elem_info *uinfo) 1015 { 1016 static const char * const texts[2] = { 1017 "44100", "48000" 1018 }; 1019 1020 return snd_ctl_enum_info(uinfo, 1, 2, texts); 1021 } 1022 1023 static int snd_emu1010_clock_fallback_get(struct snd_kcontrol *kcontrol, 1024 struct snd_ctl_elem_value *ucontrol) 1025 { 1026 struct snd_emu10k1 *emu = snd_kcontrol_chip(kcontrol); 1027 1028 ucontrol->value.enumerated.item[0] = emu->emu1010.clock_fallback; 1029 return 0; 1030 } 1031 1032 static int snd_emu1010_clock_fallback_put(struct snd_kcontrol *kcontrol, 1033 struct snd_ctl_elem_value *ucontrol) 1034 { 1035 struct snd_emu10k1 *emu = snd_kcontrol_chip(kcontrol); 1036 unsigned int val = ucontrol->value.enumerated.item[0]; 1037 int change; 1038 1039 if (val >= 2) 1040 return -EINVAL; 1041 change = (emu->emu1010.clock_fallback != val); 1042 if (change) { 1043 emu->emu1010.clock_fallback = val; 1044 snd_emu1010_fpga_write(emu, EMU_HANA_DEFCLOCK, 1 - val); 1045 } 1046 return change; 1047 } 1048 1049 static const struct snd_kcontrol_new snd_emu1010_clock_fallback = 1050 { 1051 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE, 1052 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, 1053 .name = "Clock Fallback", 1054 .count = 1, 1055 .info = snd_emu1010_clock_fallback_info, 1056 .get = snd_emu1010_clock_fallback_get, 1057 .put = snd_emu1010_clock_fallback_put 793 1058 }; 794 1059 … … 827 1092 if (change) { 828 1093 emu->emu1010.optical_out = val; 829 tmp = (emu->emu1010.optical_in ? EMU_HANA_OPTICAL_IN_ADAT : 0) |830 (emu->emu1010.optical_out ? EMU_HANA_OPTICAL_OUT_ADAT : 0);1094 tmp = (emu->emu1010.optical_in ? EMU_HANA_OPTICAL_IN_ADAT : EMU_HANA_OPTICAL_IN_SPDIF) | 1095 (emu->emu1010.optical_out ? EMU_HANA_OPTICAL_OUT_ADAT : EMU_HANA_OPTICAL_OUT_SPDIF); 831 1096 snd_emu1010_fpga_write(emu, EMU_HANA_OPTICAL_TYPE, tmp); 832 1097 } … … 878 1143 if (change) { 879 1144 emu->emu1010.optical_in = val; 880 tmp = (emu->emu1010.optical_in ? EMU_HANA_OPTICAL_IN_ADAT : 0) |881 (emu->emu1010.optical_out ? EMU_HANA_OPTICAL_OUT_ADAT : 0);1145 tmp = (emu->emu1010.optical_in ? EMU_HANA_OPTICAL_IN_ADAT : EMU_HANA_OPTICAL_IN_SPDIF) | 1146 (emu->emu1010.optical_out ? EMU_HANA_OPTICAL_OUT_ADAT : EMU_HANA_OPTICAL_OUT_SPDIF); 882 1147 snd_emu1010_fpga_write(emu, EMU_HANA_OPTICAL_TYPE, tmp); 883 1148 } … … 925 1190 unsigned int source_id; 926 1191 unsigned int ngain, ogain; 927 u 32gpio;1192 u16 gpio; 928 1193 int change = 0; 929 unsigned long flags;930 1194 u32 source; 931 1195 /* If the capture source has changed, … … 941 1205 if (change) { 942 1206 snd_emu10k1_i2c_write(emu, ADC_MUX, 0); /* Mute input */ 943 spin_lock_irq save(&emu->emu_lock, flags);944 gpio = in l(emu->port + A_IOCFG);1207 spin_lock_irq(&emu->emu_lock); 1208 gpio = inw(emu->port + A_IOCFG); 945 1209 if (source_id==0) 946 out l(gpio | 0x4, emu->port + A_IOCFG);1210 outw(gpio | 0x4, emu->port + A_IOCFG); 947 1211 else 948 out l(gpio & ~0x4, emu->port + A_IOCFG);949 spin_unlock_irq restore(&emu->emu_lock, flags);1212 outw(gpio & ~0x4, emu->port + A_IOCFG); 1213 spin_unlock_irq(&emu->emu_lock); 950 1214 951 1215 ngain = emu->i2c_capture_volume[source_id][0]; /* Left */ … … 1006 1270 struct snd_emu10k1 *emu = snd_kcontrol_chip(kcontrol); 1007 1271 unsigned int ogain; 1008 unsigned int ngain ;1272 unsigned int ngain0, ngain1; 1009 1273 unsigned int source_id; 1010 1274 int change = 0; … … 1015 1279 if (source_id >= 2) 1016 1280 return -EINVAL; 1281 ngain0 = ucontrol->value.integer.value[0]; 1282 ngain1 = ucontrol->value.integer.value[1]; 1283 if (ngain0 > 0xff) 1284 return -EINVAL; 1285 if (ngain1 > 0xff) 1286 return -EINVAL; 1017 1287 ogain = emu->i2c_capture_volume[source_id][0]; /* Left */ 1018 ngain = ucontrol->value.integer.value[0]; 1019 if (ngain > 0xff) 1020 return 0; 1021 if (ogain != ngain) { 1288 if (ogain != ngain0) { 1022 1289 if (emu->i2c_capture_source == source_id) 1023 snd_emu10k1_i2c_write(emu, ADC_ATTEN_ADCL, ((ngain) & 0xff));1024 emu->i2c_capture_volume[source_id][0] = ngain ;1290 snd_emu10k1_i2c_write(emu, ADC_ATTEN_ADCL, ngain0); 1291 emu->i2c_capture_volume[source_id][0] = ngain0; 1025 1292 change = 1; 1026 1293 } 1027 1294 ogain = emu->i2c_capture_volume[source_id][1]; /* Right */ 1028 ngain = ucontrol->value.integer.value[1]; 1029 if (ngain > 0xff) 1030 return 0; 1031 if (ogain != ngain) { 1295 if (ogain != ngain1) { 1032 1296 if (emu->i2c_capture_source == source_id) 1033 snd_emu10k1_i2c_write(emu, ADC_ATTEN_ADCR, ((ngain) & 0xff));1034 emu->i2c_capture_volume[source_id][1] = ngain ;1297 snd_emu10k1_i2c_write(emu, ADC_ATTEN_ADCR, ngain1); 1298 emu->i2c_capture_volume[source_id][1] = ngain1; 1035 1299 change = 1; 1036 1300 } … … 1039 1303 } 1040 1304 1041 #define I2C_VOLUME(xname,chid) \ 1042 { \ 1043 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ 1044 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | \ 1045 SNDRV_CTL_ELEM_ACCESS_TLV_READ, \ 1046 .info = snd_audigy_i2c_volume_info, \ 1047 .get = snd_audigy_i2c_volume_get, \ 1048 .put = snd_audigy_i2c_volume_put, \ 1049 .tlv = { .p = snd_audigy_db_scale2 }, \ 1050 .private_value = chid \ 1051 } 1052 1053 1054 static const struct snd_kcontrol_new snd_audigy_i2c_volume_ctls[] = { 1055 I2C_VOLUME("Mic Capture Volume", 0), 1056 I2C_VOLUME("Line Capture Volume", 0) 1305 static const struct snd_kcontrol_new i2c_volume_ctl = { 1306 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, 1307 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | 1308 SNDRV_CTL_ELEM_ACCESS_TLV_READ, 1309 .info = snd_audigy_i2c_volume_info, 1310 .get = snd_audigy_i2c_volume_get, 1311 .put = snd_audigy_i2c_volume_put, 1312 .tlv = { .p = snd_audigy_db_scale2 } 1313 }; 1314 1315 static const char * const snd_audigy_i2c_volume_ctls[] = { 1316 "Mic Capture Volume", 1317 "Line Capture Volume", 1057 1318 }; 1058 1319 … … 1070 1331 struct snd_emu10k1 *emu = snd_kcontrol_chip(kcontrol); 1071 1332 unsigned int tmp; 1072 unsigned long flags; 1073 1074 1075 spin_lock_irqsave(&emu->reg_lock, flags); 1333 1076 1334 tmp = snd_emu10k1_ptr_read(emu, A_SPDIF_SAMPLERATE, 0); 1077 1335 switch (tmp & A_SPDIF_RATE_MASK) { … … 1088 1346 ucontrol->value.enumerated.item[0] = 1; 1089 1347 } 1090 spin_unlock_irqrestore(&emu->reg_lock, flags);1091 1348 return 0; 1092 1349 } … … 1098 1355 int change; 1099 1356 unsigned int reg, val, tmp; 1100 unsigned long flags;1101 1357 1102 1358 switch(ucontrol->value.enumerated.item[0]) { … … 1116 1372 1117 1373 1118 spin_lock_irq save(&emu->reg_lock, flags);1374 spin_lock_irq(&emu->reg_lock); 1119 1375 reg = snd_emu10k1_ptr_read(emu, A_SPDIF_SAMPLERATE, 0); 1120 1376 tmp = reg & ~A_SPDIF_RATE_MASK; … … 1123 1379 if (change) 1124 1380 snd_emu10k1_ptr_write(emu, A_SPDIF_SAMPLERATE, 0, tmp); 1125 spin_unlock_irq restore(&emu->reg_lock, flags);1381 spin_unlock_irq(&emu->reg_lock); 1126 1382 return change; 1127 1383 } … … 1146 1402 int change; 1147 1403 unsigned int val; 1148 unsigned long flags;1149 1404 1150 1405 /* Limit: emu->spdif_bits */ … … 1155 1410 (ucontrol->value.iec958.status[2] << 16) | 1156 1411 (ucontrol->value.iec958.status[3] << 24); 1157 spin_lock_irqsave(&emu->reg_lock, flags);1158 1412 change = val != emu->spdif_bits[idx]; 1159 1413 if (change) { … … 1161 1415 emu->spdif_bits[idx] = val; 1162 1416 } 1163 spin_unlock_irqrestore(&emu->reg_lock, flags);1164 1417 return change; 1165 1418 } … … 1189 1442 { 1190 1443 if (emu->audigy) { 1191 snd_emu10k1_ptr_write (emu, A_FXRT1, voice,1192 snd_emu10k1_compose_audigy_fxrt1(route));1193 snd_emu10k1_ptr_write(emu, A_FXRT2, voice,1194 snd_emu10k1_compose_audigy_fxrt2(route));1444 snd_emu10k1_ptr_write_multiple(emu, voice, 1445 A_FXRT1, snd_emu10k1_compose_audigy_fxrt1(route), 1446 A_FXRT2, snd_emu10k1_compose_audigy_fxrt2(route), 1447 REGLIST_END); 1195 1448 } else { 1196 1449 snd_emu10k1_ptr_write(emu, FXRT, voice, … … 1206 1459 snd_emu10k1_ptr_write(emu, DSL_FXSENDAMOUNT_D, voice, volume[3]); 1207 1460 if (emu->audigy) { 1208 unsigned int val = ((unsigned int)volume[4] << 24) | 1209 ((unsigned int)volume[5] << 16) | 1210 ((unsigned int)volume[6] << 8) | 1211 (unsigned int)volume[7]; 1212 snd_emu10k1_ptr_write(emu, A_SENDAMOUNTS, voice, val); 1461 snd_emu10k1_ptr_write(emu, A_SENDAMOUNTS, voice, 1462 snd_emu10k1_compose_audigy_sendamounts(volume)); 1213 1463 } 1214 1464 } … … 1229 1479 struct snd_ctl_elem_value *ucontrol) 1230 1480 { 1231 unsigned long flags;1232 1481 struct snd_emu10k1 *emu = snd_kcontrol_chip(kcontrol); 1233 1482 struct snd_emu10k1_pcm_mixer *mix = … … 1237 1486 int mask = emu->audigy ? 0x3f : 0x0f; 1238 1487 1239 spin_lock_irqsave(&emu->reg_lock, flags);1240 1488 for (voice = 0; voice < 3; voice++) 1241 1489 for (idx = 0; idx < num_efx; idx++) 1242 1490 ucontrol->value.integer.value[(voice * num_efx) + idx] = 1243 1491 mix->send_routing[voice][idx] & mask; 1244 spin_unlock_irqrestore(&emu->reg_lock, flags);1245 1492 return 0; 1246 1493 } … … 1249 1496 struct snd_ctl_elem_value *ucontrol) 1250 1497 { 1251 unsigned long flags;1252 1498 struct snd_emu10k1 *emu = snd_kcontrol_chip(kcontrol); 1253 1499 struct snd_emu10k1_pcm_mixer *mix = … … 1257 1503 int mask = emu->audigy ? 0x3f : 0x0f; 1258 1504 1259 spin_lock_irq save(&emu->reg_lock, flags);1505 spin_lock_irq(&emu->reg_lock); 1260 1506 for (voice = 0; voice < 3; voice++) 1261 1507 for (idx = 0; idx < num_efx; idx++) { … … 1266 1512 } 1267 1513 } 1268 if (change && mix->epcm ) {1269 if ( mix->epcm->voices[0] && mix->epcm->voices[1]) {1514 if (change && mix->epcm && mix->epcm->voices[0]) { 1515 if (!mix->epcm->voices[0]->last) { 1270 1516 update_emu10k1_fxrt(emu, mix->epcm->voices[0]->number, 1271 1517 &mix->send_routing[1][0]); 1272 update_emu10k1_fxrt(emu, mix->epcm->voices[ 1]->number,1518 update_emu10k1_fxrt(emu, mix->epcm->voices[0]->number + 1, 1273 1519 &mix->send_routing[2][0]); 1274 } else if (mix->epcm->voices[0]){1520 } else { 1275 1521 update_emu10k1_fxrt(emu, mix->epcm->voices[0]->number, 1276 1522 &mix->send_routing[0][0]); 1277 1523 } 1278 1524 } 1279 spin_unlock_irq restore(&emu->reg_lock, flags);1525 spin_unlock_irq(&emu->reg_lock); 1280 1526 return change; 1281 1527 } … … 1305 1551 struct snd_ctl_elem_value *ucontrol) 1306 1552 { 1307 unsigned long flags;1308 1553 struct snd_emu10k1 *emu = snd_kcontrol_chip(kcontrol); 1309 1554 struct snd_emu10k1_pcm_mixer *mix = … … 1312 1557 int num_efx = emu->audigy ? 8 : 4; 1313 1558 1314 spin_lock_irqsave(&emu->reg_lock, flags);1315 1559 for (idx = 0; idx < 3*num_efx; idx++) 1316 1560 ucontrol->value.integer.value[idx] = mix->send_volume[idx/num_efx][idx%num_efx]; 1317 spin_unlock_irqrestore(&emu->reg_lock, flags);1318 1561 return 0; 1319 1562 } … … 1322 1565 struct snd_ctl_elem_value *ucontrol) 1323 1566 { 1324 unsigned long flags;1325 1567 struct snd_emu10k1 *emu = snd_kcontrol_chip(kcontrol); 1326 1568 struct snd_emu10k1_pcm_mixer *mix = … … 1329 1571 int num_efx = emu->audigy ? 8 : 4; 1330 1572 1331 spin_lock_irq save(&emu->reg_lock, flags);1573 spin_lock_irq(&emu->reg_lock); 1332 1574 for (idx = 0; idx < 3*num_efx; idx++) { 1333 1575 val = ucontrol->value.integer.value[idx] & 255; … … 1337 1579 } 1338 1580 } 1339 if (change && mix->epcm ) {1340 if ( mix->epcm->voices[0] && mix->epcm->voices[1]) {1581 if (change && mix->epcm && mix->epcm->voices[0]) { 1582 if (!mix->epcm->voices[0]->last) { 1341 1583 update_emu10k1_send_volume(emu, mix->epcm->voices[0]->number, 1342 1584 &mix->send_volume[1][0]); 1343 update_emu10k1_send_volume(emu, mix->epcm->voices[ 1]->number,1585 update_emu10k1_send_volume(emu, mix->epcm->voices[0]->number + 1, 1344 1586 &mix->send_volume[2][0]); 1345 } else if (mix->epcm->voices[0]){1587 } else { 1346 1588 update_emu10k1_send_volume(emu, mix->epcm->voices[0]->number, 1347 1589 &mix->send_volume[0][0]); 1348 1590 } 1349 1591 } 1350 spin_unlock_irq restore(&emu->reg_lock, flags);1592 spin_unlock_irq(&emu->reg_lock); 1351 1593 return change; 1352 1594 } … … 1368 1610 uinfo->count = 3; 1369 1611 uinfo->value.integer.min = 0; 1370 uinfo->value.integer.max = 0x ffff;1612 uinfo->value.integer.max = 0x1fffd; 1371 1613 return 0; 1372 1614 } … … 1378 1620 struct snd_emu10k1_pcm_mixer *mix = 1379 1621 &emu->pcm_mixer[snd_ctl_get_ioffidx(kcontrol, &ucontrol->id)]; 1380 unsigned long flags;1381 1622 int idx; 1382 1623 1383 spin_lock_irqsave(&emu->reg_lock, flags);1384 1624 for (idx = 0; idx < 3; idx++) 1385 ucontrol->value.integer.value[idx] = mix->attn[idx]; 1386 spin_unlock_irqrestore(&emu->reg_lock, flags); 1625 ucontrol->value.integer.value[idx] = mix->attn[idx] * 0xffffU / 0x8000U; 1387 1626 return 0; 1388 1627 } … … 1391 1630 struct snd_ctl_elem_value *ucontrol) 1392 1631 { 1393 unsigned long flags;1394 1632 struct snd_emu10k1 *emu = snd_kcontrol_chip(kcontrol); 1395 1633 struct snd_emu10k1_pcm_mixer *mix = … … 1397 1635 int change = 0, idx, val; 1398 1636 1399 spin_lock_irq save(&emu->reg_lock, flags);1637 spin_lock_irq(&emu->reg_lock); 1400 1638 for (idx = 0; idx < 3; idx++) { 1401 val = ucontrol->value.integer.value[idx] & 0xffff; 1639 unsigned uval = ucontrol->value.integer.value[idx] & 0x1ffff; 1640 val = uval * 0x8000U / 0xffffU; 1402 1641 if (mix->attn[idx] != val) { 1403 1642 mix->attn[idx] = val; … … 1405 1644 } 1406 1645 } 1407 if (change && mix->epcm ) {1408 if ( mix->epcm->voices[0] && mix->epcm->voices[1]) {1646 if (change && mix->epcm && mix->epcm->voices[0]) { 1647 if (!mix->epcm->voices[0]->last) { 1409 1648 snd_emu10k1_ptr_write(emu, VTFT_VOLUMETARGET, mix->epcm->voices[0]->number, mix->attn[1]); 1410 snd_emu10k1_ptr_write(emu, VTFT_VOLUMETARGET, mix->epcm->voices[ 1]->number, mix->attn[2]);1411 } else if (mix->epcm->voices[0]){1649 snd_emu10k1_ptr_write(emu, VTFT_VOLUMETARGET, mix->epcm->voices[0]->number + 1, mix->attn[2]); 1650 } else { 1412 1651 snd_emu10k1_ptr_write(emu, VTFT_VOLUMETARGET, mix->epcm->voices[0]->number, mix->attn[0]); 1413 1652 } 1414 1653 } 1415 spin_unlock_irq restore(&emu->reg_lock, flags);1654 spin_unlock_irq(&emu->reg_lock); 1416 1655 return change; 1417 1656 } … … 1443 1682 struct snd_ctl_elem_value *ucontrol) 1444 1683 { 1445 unsigned long flags;1446 1684 struct snd_emu10k1 *emu = snd_kcontrol_chip(kcontrol); 1447 1685 struct snd_emu10k1_pcm_mixer *mix = … … 1451 1689 int mask = emu->audigy ? 0x3f : 0x0f; 1452 1690 1453 spin_lock_irqsave(&emu->reg_lock, flags);1454 1691 for (idx = 0; idx < num_efx; idx++) 1455 1692 ucontrol->value.integer.value[idx] = 1456 1693 mix->send_routing[0][idx] & mask; 1457 spin_unlock_irqrestore(&emu->reg_lock, flags);1458 1694 return 0; 1459 1695 } … … 1462 1698 struct snd_ctl_elem_value *ucontrol) 1463 1699 { 1464 unsigned long flags;1465 1700 struct snd_emu10k1 *emu = snd_kcontrol_chip(kcontrol); 1466 1701 int ch = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id); … … 1470 1705 int mask = emu->audigy ? 0x3f : 0x0f; 1471 1706 1472 spin_lock_irq save(&emu->reg_lock, flags);1707 spin_lock_irq(&emu->reg_lock); 1473 1708 for (idx = 0; idx < num_efx; idx++) { 1474 1709 val = ucontrol->value.integer.value[idx] & mask; … … 1485 1720 } 1486 1721 } 1487 spin_unlock_irq restore(&emu->reg_lock, flags);1722 spin_unlock_irq(&emu->reg_lock); 1488 1723 return change; 1489 1724 } … … 1513 1748 struct snd_ctl_elem_value *ucontrol) 1514 1749 { 1515 unsigned long flags;1516 1750 struct snd_emu10k1 *emu = snd_kcontrol_chip(kcontrol); 1517 1751 struct snd_emu10k1_pcm_mixer *mix = … … 1520 1754 int num_efx = emu->audigy ? 8 : 4; 1521 1755 1522 spin_lock_irqsave(&emu->reg_lock, flags);1523 1756 for (idx = 0; idx < num_efx; idx++) 1524 1757 ucontrol->value.integer.value[idx] = mix->send_volume[0][idx]; 1525 spin_unlock_irqrestore(&emu->reg_lock, flags);1526 1758 return 0; 1527 1759 } … … 1530 1762 struct snd_ctl_elem_value *ucontrol) 1531 1763 { 1532 unsigned long flags;1533 1764 struct snd_emu10k1 *emu = snd_kcontrol_chip(kcontrol); 1534 1765 int ch = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id); … … 1537 1768 int num_efx = emu->audigy ? 8 : 4; 1538 1769 1539 spin_lock_irq save(&emu->reg_lock, flags);1770 spin_lock_irq(&emu->reg_lock); 1540 1771 for (idx = 0; idx < num_efx; idx++) { 1541 1772 val = ucontrol->value.integer.value[idx] & 255; … … 1551 1782 } 1552 1783 } 1553 spin_unlock_irq restore(&emu->reg_lock, flags);1784 spin_unlock_irq(&emu->reg_lock); 1554 1785 return change; 1555 1786 } … … 1572 1803 uinfo->count = 1; 1573 1804 uinfo->value.integer.min = 0; 1574 uinfo->value.integer.max = 0x ffff;1805 uinfo->value.integer.max = 0x1fffd; 1575 1806 return 0; 1576 1807 } … … 1582 1813 struct snd_emu10k1_pcm_mixer *mix = 1583 1814 &emu->efx_pcm_mixer[snd_ctl_get_ioffidx(kcontrol, &ucontrol->id)]; 1584 unsigned long flags; 1585 1586 spin_lock_irqsave(&emu->reg_lock, flags); 1587 ucontrol->value.integer.value[0] = mix->attn[0]; 1588 spin_unlock_irqrestore(&emu->reg_lock, flags); 1815 1816 ucontrol->value.integer.value[0] = mix->attn[0] * 0xffffU / 0x8000U; 1589 1817 return 0; 1590 1818 } … … 1593 1821 struct snd_ctl_elem_value *ucontrol) 1594 1822 { 1595 unsigned long flags;1596 1823 struct snd_emu10k1 *emu = snd_kcontrol_chip(kcontrol); 1597 1824 int ch = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id); 1598 1825 struct snd_emu10k1_pcm_mixer *mix = &emu->efx_pcm_mixer[ch]; 1599 1826 int change = 0, val; 1600 1601 spin_lock_irqsave(&emu->reg_lock, flags); 1602 val = ucontrol->value.integer.value[0] & 0xffff; 1827 unsigned uval; 1828 1829 spin_lock_irq(&emu->reg_lock); 1830 uval = ucontrol->value.integer.value[0] & 0x1ffff; 1831 val = uval * 0x8000U / 0xffffU; 1603 1832 if (mix->attn[0] != val) { 1604 1833 mix->attn[0] = val; … … 1610 1839 } 1611 1840 } 1612 spin_unlock_irq restore(&emu->reg_lock, flags);1841 spin_unlock_irq(&emu->reg_lock); 1613 1842 return change; 1614 1843 } … … 1633 1862 1634 1863 if (emu->audigy) 1635 ucontrol->value.integer.value[0] = in l(emu->port + A_IOCFG) & A_IOCFG_GPOUT0 ? 1 : 0;1864 ucontrol->value.integer.value[0] = inw(emu->port + A_IOCFG) & A_IOCFG_GPOUT0 ? 1 : 0; 1636 1865 else 1637 1866 ucontrol->value.integer.value[0] = inl(emu->port + HCFG) & HCFG_GPOUT0 ? 1 : 0; … … 1646 1875 struct snd_ctl_elem_value *ucontrol) 1647 1876 { 1648 unsigned long flags;1649 1877 struct snd_emu10k1 *emu = snd_kcontrol_chip(kcontrol); 1650 1878 unsigned int reg, val, sw; … … 1654 1882 if (emu->card_capabilities->invert_shared_spdif) 1655 1883 sw = !sw; 1656 spin_lock_irq save(&emu->reg_lock, flags);1884 spin_lock_irq(&emu->emu_lock); 1657 1885 if ( emu->card_capabilities->i2c_adc) { 1658 1886 /* Do nothing for Audigy 2 ZS Notebook */ 1659 1887 } else if (emu->audigy) { 1660 reg = in l(emu->port + A_IOCFG);1888 reg = inw(emu->port + A_IOCFG); 1661 1889 val = sw ? A_IOCFG_GPOUT0 : 0; 1662 1890 change = (reg & A_IOCFG_GPOUT0) != val; … … 1664 1892 reg &= ~A_IOCFG_GPOUT0; 1665 1893 reg |= val; 1666 out l(reg | val, emu->port + A_IOCFG);1894 outw(reg | val, emu->port + A_IOCFG); 1667 1895 } 1668 1896 } … … 1675 1903 outl(reg | val, emu->port + HCFG); 1676 1904 } 1677 spin_unlock_irq restore(&emu->reg_lock, flags);1905 spin_unlock_irq(&emu->emu_lock); 1678 1906 return change; 1679 1907 } … … 1755 1983 } 1756 1984 1757 static struct snd_kcontrol *ctl_find(struct snd_card *card, const char *name)1758 {1759 struct snd_ctl_elem_id sid;1760 memset(&sid, 0, sizeof(sid));1761 strcpy(sid.name, name);1762 sid.iface = SNDRV_CTL_ELEM_IFACE_MIXER;1763 return snd_ctl_find_id(card, &sid);1764 }1765 1766 1985 static int rename_ctl(struct snd_card *card, const char *src, const char *dst) 1767 1986 { 1768 struct snd_kcontrol *kctl = ctl_find(card, src);1987 struct snd_kcontrol *kctl = snd_ctl_find_id_mixer(card, src); 1769 1988 if (kctl) { 1770 s trcpy(kctl->id.name, dst);1989 snd_ctl_rename(card, kctl, dst); 1771 1990 return 0; 1772 1991 } … … 1777 1996 int pcm_device, int multi_device) 1778 1997 { 1779 int err , pcm;1998 int err; 1780 1999 struct snd_kcontrol *kctl; 1781 2000 struct snd_card *card = emu->card; … … 2041 2260 return err; 2042 2261 2043 /* initialize the routing and volume table for each pcm playback stream */ 2044 for (pcm = 0; pcm < 32; pcm++) { 2045 struct snd_emu10k1_pcm_mixer *mix; 2046 int v; 2047 2048 mix = &emu->pcm_mixer[pcm]; 2049 mix->epcm = NULL; 2050 2051 for (v = 0; v < 4; v++) 2052 mix->send_routing[0][v] = 2053 mix->send_routing[1][v] = 2054 mix->send_routing[2][v] = v; 2055 2056 memset(&mix->send_volume, 0, sizeof(mix->send_volume)); 2057 mix->send_volume[0][0] = mix->send_volume[0][1] = 2058 mix->send_volume[1][0] = mix->send_volume[2][1] = 255; 2059 2060 mix->attn[0] = mix->attn[1] = mix->attn[2] = 0xffff; 2061 } 2062 2063 /* initialize the routing and volume table for the multichannel playback stream */ 2064 for (pcm = 0; pcm < NUM_EFX_PLAYBACK; pcm++) { 2065 struct snd_emu10k1_pcm_mixer *mix; 2066 int v; 2067 2068 mix = &emu->efx_pcm_mixer[pcm]; 2069 mix->epcm = NULL; 2070 2071 mix->send_routing[0][0] = pcm; 2072 mix->send_routing[0][1] = (pcm == 0) ? 1 : 0; 2073 for (v = 0; v < 2; v++) 2074 mix->send_routing[0][2+v] = 13+v; 2075 if (emu->audigy) 2076 for (v = 0; v < 4; v++) 2077 mix->send_routing[0][4+v] = 60+v; 2078 2079 memset(&mix->send_volume, 0, sizeof(mix->send_volume)); 2080 mix->send_volume[0][0] = 255; 2081 2082 mix->attn[0] = 0xffff; 2083 } 2084 2085 if (! emu->card_capabilities->ecard) { /* FIXME: APS has these controls? */ 2262 if (!emu->card_capabilities->ecard && !emu->card_capabilities->emu_model) { 2086 2263 /* sb live! and audigy */ 2087 2264 kctl = snd_ctl_new1(&snd_emu10k1_spdif_mask_control, emu); … … 2135 2312 } 2136 2313 2137 if (emu->card_capabilities->emu_model == EMU_MODEL_EMU1616) { 2138 /* 1616(m) cardbus */ 2139 int i; 2140 2141 for (i = 0; i < ARRAY_SIZE(snd_emu1616_output_enum_ctls); i++) { 2314 if (emu->card_capabilities->emu_model) { 2315 unsigned i, emu_idx = emu1010_idx(emu); 2316 const struct snd_emu1010_routing_info *emu_ri = 2317 &emu1010_routing_info[emu_idx]; 2318 const struct snd_emu1010_pads_info *emu_pi = &emu1010_pads_info[emu_idx]; 2319 2320 for (i = 0; i < emu_ri->n_ins; i++) 2321 emu->emu1010.input_source[i] = 2322 emu1010_map_source(emu_ri, emu_ri->in_dflts[i]); 2323 for (i = 0; i < emu_ri->n_outs; i++) 2324 emu->emu1010.output_source[i] = 2325 emu1010_map_source(emu_ri, emu_ri->out_dflts[i]); 2326 snd_emu1010_apply_sources(emu); 2327 2328 kctl = emu->ctl_clock_source = snd_ctl_new1(&snd_emu1010_clock_source, emu); 2329 err = snd_ctl_add(card, kctl); 2330 if (err < 0) 2331 return err; 2332 err = snd_ctl_add(card, 2333 snd_ctl_new1(&snd_emu1010_clock_fallback, emu)); 2334 if (err < 0) 2335 return err; 2336 2337 err = add_ctls(emu, &emu1010_adc_pads_ctl, 2338 emu_pi->adc_ctls, emu_pi->n_adc_ctls); 2339 if (err < 0) 2340 return err; 2341 err = add_ctls(emu, &emu1010_dac_pads_ctl, 2342 emu_pi->dac_ctls, emu_pi->n_dac_ctls); 2343 if (err < 0) 2344 return err; 2345 2346 if (!emu->card_capabilities->no_adat) { 2142 2347 err = snd_ctl_add(card, 2143 snd_ctl_new1(&snd_emu1616_output_enum_ctls[i], 2144 emu)); 2348 snd_ctl_new1(&snd_emu1010_optical_out, emu)); 2349 if (err < 0) 2350 return err; 2351 err = snd_ctl_add(card, 2352 snd_ctl_new1(&snd_emu1010_optical_in, emu)); 2145 2353 if (err < 0) 2146 2354 return err; 2147 2355 } 2148 for (i = 0; i < ARRAY_SIZE(snd_emu1010_input_enum_ctls); i++) { 2149 err = snd_ctl_add(card, 2150 snd_ctl_new1(&snd_emu1010_input_enum_ctls[i], 2151 emu)); 2152 if (err < 0) 2153 return err; 2154 } 2155 for (i = 0; i < ARRAY_SIZE(snd_emu1010_adc_pads) - 2; i++) { 2156 err = snd_ctl_add(card, 2157 snd_ctl_new1(&snd_emu1010_adc_pads[i], emu)); 2158 if (err < 0) 2159 return err; 2160 } 2161 for (i = 0; i < ARRAY_SIZE(snd_emu1010_dac_pads) - 2; i++) { 2162 err = snd_ctl_add(card, 2163 snd_ctl_new1(&snd_emu1010_dac_pads[i], emu)); 2164 if (err < 0) 2165 return err; 2166 } 2167 err = snd_ctl_add(card, 2168 snd_ctl_new1(&snd_emu1010_internal_clock, emu)); 2356 2357 err = add_emu1010_source_mixers(emu); 2169 2358 if (err < 0) 2170 2359 return err; 2171 err = snd_ctl_add(card,2172 snd_ctl_new1(&snd_emu1010_optical_out, emu));2173 if (err < 0)2174 return err;2175 err = snd_ctl_add(card,2176 snd_ctl_new1(&snd_emu1010_optical_in, emu));2177 if (err < 0)2178 return err;2179 2180 } else if (emu->card_capabilities->emu_model) {2181 /* all other e-mu cards for now */2182 int i;2183 2184 for (i = 0; i < ARRAY_SIZE(snd_emu1010_output_enum_ctls); i++) {2185 err = snd_ctl_add(card,2186 snd_ctl_new1(&snd_emu1010_output_enum_ctls[i],2187 emu));2188 if (err < 0)2189 return err;2190 }2191 for (i = 0; i < ARRAY_SIZE(snd_emu1010_input_enum_ctls); i++) {2192 err = snd_ctl_add(card,2193 snd_ctl_new1(&snd_emu1010_input_enum_ctls[i],2194 emu));2195 if (err < 0)2196 return err;2197 }2198 for (i = 0; i < ARRAY_SIZE(snd_emu1010_adc_pads); i++) {2199 err = snd_ctl_add(card,2200 snd_ctl_new1(&snd_emu1010_adc_pads[i], emu));2201 if (err < 0)2202 return err;2203 }2204 for (i = 0; i < ARRAY_SIZE(snd_emu1010_dac_pads); i++) {2205 err = snd_ctl_add(card,2206 snd_ctl_new1(&snd_emu1010_dac_pads[i], emu));2207 if (err < 0)2208 return err;2209 }2210 err = snd_ctl_add(card,2211 snd_ctl_new1(&snd_emu1010_internal_clock, emu));2212 if (err < 0)2213 return err;2214 err = snd_ctl_add(card,2215 snd_ctl_new1(&snd_emu1010_optical_out, emu));2216 if (err < 0)2217 return err;2218 err = snd_ctl_add(card,2219 snd_ctl_new1(&snd_emu1010_optical_in, emu));2220 if (err < 0)2221 return err;2222 2360 } 2223 2361 2224 2362 if ( emu->card_capabilities->i2c_adc) { 2225 int i;2226 2227 2363 err = snd_ctl_add(card, snd_ctl_new1(&snd_audigy_i2c_capture_source, emu)); 2228 2364 if (err < 0) 2229 2365 return err; 2230 2366 2231 for (i = 0; i < ARRAY_SIZE(snd_audigy_i2c_volume_ctls); i++) {2232 err = snd_ctl_add(card, snd_ctl_new1(&snd_audigy_i2c_volume_ctls[i], emu));2233 if (err < 0)2234 return err;2235 }2367 err = add_ctls(emu, &i2c_volume_ctl, 2368 snd_audigy_i2c_volume_ctls, 2369 ARRAY_SIZE(snd_audigy_i2c_volume_ctls)); 2370 if (err < 0) 2371 return err; 2236 2372 } 2237 2373
Note:
See TracChangeset
for help on using the changeset viewer.
