Changeset 772 for GPL/trunk/alsa-kernel/pci/emu10k1
- Timestamp:
- Apr 19, 2025, 8:08:37 PM (6 months ago)
- Location:
- GPL/trunk
- Files:
-
- 19 edited
-
. (modified) (1 prop)
-
alsa-kernel/pci/emu10k1/emu10k1.c (modified) (8 diffs)
-
alsa-kernel/pci/emu10k1/emu10k1_callback.c (modified) (13 diffs)
-
alsa-kernel/pci/emu10k1/emu10k1_main.c (modified) (45 diffs)
-
alsa-kernel/pci/emu10k1/emu10k1_synth.c (modified) (5 diffs)
-
alsa-kernel/pci/emu10k1/emufx.c (modified) (48 diffs)
-
alsa-kernel/pci/emu10k1/emumixer.c (modified) (73 diffs)
-
alsa-kernel/pci/emu10k1/emumpu401.c (modified) (14 diffs)
-
alsa-kernel/pci/emu10k1/emupcm.c (modified) (49 diffs)
-
alsa-kernel/pci/emu10k1/emuproc.c (modified) (18 diffs)
-
alsa-kernel/pci/emu10k1/io.c (modified) (22 diffs)
-
alsa-kernel/pci/emu10k1/irq.c (modified) (7 diffs)
-
alsa-kernel/pci/emu10k1/memory.c (modified) (2 diffs)
-
alsa-kernel/pci/emu10k1/p16v.c (modified) (18 diffs)
-
alsa-kernel/pci/emu10k1/p16v.h (modified) (2 diffs)
-
alsa-kernel/pci/emu10k1/p17v.h (modified) (1 diff)
-
alsa-kernel/pci/emu10k1/timer.c (modified) (6 diffs)
-
alsa-kernel/pci/emu10k1/tina2.h (modified) (1 diff)
-
alsa-kernel/pci/emu10k1/voice.c (modified) (4 diffs)
Legend:
- Unmodified
- Added
- Removed
-
GPL/trunk
- Property svn:mergeinfo changed
/GPL/branches/uniaud32-6.6-LTS (added) merged: 765,768-769 /GPL/branches/uniaud32-exp (added) merged: 735-741,743-744,748-751,753-760,762-764 /GPL/branches/uniaud32-next merged: 718-734
- Property svn:mergeinfo changed
-
GPL/trunk/alsa-kernel/pci/emu10k1/emu10k1.c
r717 r772 3 3 * The driver for the EMU10K1 (SB Live!) based soundcards 4 4 * Copyright (c) by Jaroslav Kysela <perex@perex.cz> 5 * 6 * Copyright (c) by James Courtier-Dutton <James@superbug.demon.co.uk> 7 * Added support for Audigy 2 Value. 5 * James Courtier-Dutton <James@superbug.co.uk> 8 6 */ 9 7 … … 45 43 static bool enable_ir[SNDRV_CARDS]; 46 44 static uint subsystem[SNDRV_CARDS]; /* Force card subsystem model */ 47 #ifndef TARGET_OS248 static uint delay_pcm_irq[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = 2};49 #else50 static uint delay_pcm_irq[SNDRV_CARDS] = {2,2,2,2,2,2,2,2};51 #endif52 45 53 46 module_param_array(index, int, NULL, 0444); … … 71 64 module_param_array(subsystem, uint, NULL, 0444); 72 65 MODULE_PARM_DESC(subsystem, "Force card subsystem model."); 73 module_param_array(delay_pcm_irq, uint, NULL, 0444);74 MODULE_PARM_DESC(delay_pcm_irq, "Delay PCM interrupt by specified number of samples (default 0).");75 66 /* 76 67 * Class 0401: 1102:0008 (rev 00) Subsystem: 1102:1001 -> Audigy2 Value Model:SB0400 … … 83 74 }; 84 75 85 /*86 * Audigy 2 Value notes:87 * A_IOCFG Input (GPIO)88 * 0x400 = Front analog jack plugged in. (Green socket)89 * 0x1000 = Read analog jack plugged in. (Black socket)90 * 0x2000 = Center/LFE analog jack plugged in. (Orange socket)91 * A_IOCFG Output (GPIO)92 * 0x60 = Sound out of front Left.93 * Win sets it to 0xXX6194 */95 96 76 MODULE_DEVICE_TABLE(pci, snd_emu10k1_ids); 97 77 … … 129 109 if (err < 0) 130 110 return err; 131 emu->delay_pcm_irq = delay_pcm_irq[dev] & 0x1f;132 111 err = snd_emu10k1_pcm(emu, 0); 133 112 if (err < 0) 134 113 return err; 135 err = snd_emu10k1_pcm_mic(emu, 1); 136 if (err < 0) 137 return err; 114 if (emu->card_capabilities->ac97_chip) { 115 err = snd_emu10k1_pcm_mic(emu, 1); 116 if (err < 0) 117 return err; 118 } 138 119 err = snd_emu10k1_pcm_efx(emu, 2); 139 120 if (err < 0) … … 203 184 return err; 204 185 205 if (emu->card_capabilities->emu_model)206 schedule_delayed_work(&emu->emu1010.firmware_work, 0);207 208 186 pci_set_drvdata(pci, card); 209 187 dev++; … … 221 199 emu->suspend = 1; 222 200 223 cancel_ delayed_work_sync(&emu->emu1010.firmware_work);201 cancel_work_sync(&emu->emu1010.work); 224 202 225 203 snd_ac97_suspend(emu->ac97); … … 250 228 251 229 snd_power_change_state(card, SNDRV_CTL_POWER_D0); 252 253 if (emu->card_capabilities->emu_model)254 schedule_delayed_work(&emu->emu1010.firmware_work, 0);255 230 256 231 return 0; -
GPL/trunk/alsa-kernel/pci/emu10k1/emu10k1_callback.c
r703 r772 34 34 static void terminate_voice(struct snd_emux_voice *vp); 35 35 static void free_voice(struct snd_emux_voice *vp); 36 static void set_fmmod(struct snd_emu10k1 *hw,struct snd_emux_voice *vp);37 static void set_fm2frq2(struct snd_emu10k1 *hw,struct snd_emux_voice *vp);38 static void set_filterQ(struct snd_emu10k1 *hw, struct snd_emux_voice *vp);36 static u32 make_fmmod(struct snd_emux_voice *vp); 37 static u32 make_fm2frq2(struct snd_emux_voice *vp); 38 static int get_pitch_shift(struct snd_emux *emu); 39 39 40 40 /* … … 60 60 .sample_new = snd_emu10k1_sample_new, 61 61 .sample_free = snd_emu10k1_sample_free, 62 .get_pitch_shift = get_pitch_shift, 62 63 }; 63 64 … … 117 118 release_voice(struct snd_emux_voice *vp) 118 119 { 119 int dcysusv;120 120 struct snd_emu10k1 *hw; 121 121 122 122 hw = vp->hw; 123 dcysusv = 0x8000 | (unsigned char)vp->reg.parm.modrelease;124 snd_emu10k1_ptr_write(hw, DCYSUSM, vp->ch, dcysusv);125 dcysusv = 0x8000 | (unsigned char)vp->reg.parm.volrelease | DCYSUSV_CHANNELENABLE_MASK;126 snd_emu10k1_ptr_write(hw, DCYSUSV, vp->ch, dcysusv);123 snd_emu10k1_ptr_write_multiple(hw, vp->ch, 124 DCYSUSM, (unsigned char)vp->reg.parm.modrelease | DCYSUSM_PHASE1_MASK, 125 DCYSUSV, (unsigned char)vp->reg.parm.volrelease | DCYSUSV_PHASE1_MASK | DCYSUSV_CHANNELENABLE_MASK, 126 REGLIST_END); 127 127 } 128 128 … … 139 139 return; 140 140 hw = vp->hw; 141 snd_emu10k1_ptr_write(hw, DCYSUSV, vp->ch, 0x807f | DCYSUSV_CHANNELENABLE_MASK); 141 snd_emu10k1_ptr_write_multiple(hw, vp->ch, 142 DCYSUSV, 0, 143 VTFT, VTFT_FILTERTARGET_MASK, 144 CVCF, CVCF_CURRENTFILTER_MASK, 145 PTRX, 0, 146 CPF, 0, 147 REGLIST_END); 142 148 if (vp->block) { 143 149 struct snd_emu10k1_memblk *emem; … … 162 168 /* on the Audigy 2 ZS Notebook. */ 163 169 if (hw && (vp->ch >= 0)) { 164 snd_emu10k1_ptr_write(hw, IFATN, vp->ch, 0xff00);165 snd_emu10k1_ptr_write(hw, DCYSUSV, vp->ch, 0x807f | DCYSUSV_CHANNELENABLE_MASK);166 // snd_emu10k1_ptr_write(hw, DCYSUSV, vp->ch, 0);167 snd_emu10k1_ptr_write(hw, VTFT, vp->ch, 0xffff);168 snd_emu10k1_ptr_write(hw, CVCF, vp->ch, 0xffff);169 170 snd_emu10k1_voice_free(hw, &hw->voices[vp->ch]); 170 171 vp->emu->num_voices--; … … 192 193 } 193 194 if (update & SNDRV_EMUX_UPDATE_FMMOD) 194 s et_fmmod(hw, vp);195 snd_emu10k1_ptr_write(hw, FMMOD, vp->ch, make_fmmod(vp)); 195 196 if (update & SNDRV_EMUX_UPDATE_TREMFREQ) 196 197 snd_emu10k1_ptr_write(hw, TREMFRQ, vp->ch, vp->reg.parm.tremfrq); 197 198 if (update & SNDRV_EMUX_UPDATE_FM2FRQ2) 198 s et_fm2frq2(hw, vp);199 snd_emu10k1_ptr_write(hw, FM2FRQ2, vp->ch, make_fm2frq2(vp)); 199 200 if (update & SNDRV_EMUX_UPDATE_Q) 200 s et_filterQ(hw, vp);201 snd_emu10k1_ptr_write(hw, CCCA_RESONANCE, vp->ch, vp->reg.parm.filterQ); 201 202 } 202 203 … … 289 290 /* allocate a voice */ 290 291 struct snd_emu10k1_voice *hwvoice; 291 if (snd_emu10k1_voice_alloc(hw, EMU10K1_SYNTH, 1, &hwvoice) < 0 || hwvoice == NULL)292 if (snd_emu10k1_voice_alloc(hw, EMU10K1_SYNTH, 1, 1, NULL, &hwvoice) < 0) 292 293 continue; 293 294 vp->ch = hwvoice->number; … … 310 311 unsigned int temp; 311 312 int ch; 313 u32 psst, dsl, map, ccca, vtarget; 312 314 unsigned int addr, mapped_offset; 313 315 struct snd_midi_channel *chan; … … 347 349 } 348 350 349 /* channel to be silent and idle */350 snd_emu10k1_ptr_write(hw, DCYSUSV, ch, 0x0000);351 snd_emu10k1_ptr_write(hw, VTFT, ch, 0x0000FFFF);352 snd_emu10k1_ptr_write(hw, CVCF, ch, 0x0000FFFF);353 snd_emu10k1_ptr_write(hw, PTRX, ch, 0);354 snd_emu10k1_ptr_write(hw, CPF, ch, 0);355 356 /* set pitch offset */357 snd_emu10k1_ptr_write(hw, IP, vp->ch, vp->apitch);358 359 /* set envelope parameters */360 snd_emu10k1_ptr_write(hw, ENVVAL, ch, vp->reg.parm.moddelay);361 snd_emu10k1_ptr_write(hw, ATKHLDM, ch, vp->reg.parm.modatkhld);362 snd_emu10k1_ptr_write(hw, DCYSUSM, ch, vp->reg.parm.moddcysus);363 snd_emu10k1_ptr_write(hw, ENVVOL, ch, vp->reg.parm.voldelay);364 snd_emu10k1_ptr_write(hw, ATKHLDV, ch, vp->reg.parm.volatkhld);365 /* decay/sustain parameter for volume envelope is used366 for triggerg the voice */367 368 /* cutoff and volume */369 temp = (unsigned int)vp->acutoff << 8 | (unsigned char)vp->avol;370 snd_emu10k1_ptr_write(hw, IFATN, vp->ch, temp);371 372 /* modulation envelope heights */373 snd_emu10k1_ptr_write(hw, PEFE, ch, vp->reg.parm.pefe);374 375 /* lfo1/2 delay */376 snd_emu10k1_ptr_write(hw, LFOVAL1, ch, vp->reg.parm.lfo1delay);377 snd_emu10k1_ptr_write(hw, LFOVAL2, ch, vp->reg.parm.lfo2delay);378 379 /* lfo1 pitch & cutoff shift */380 set_fmmod(hw, vp);381 /* lfo1 volume & freq */382 snd_emu10k1_ptr_write(hw, TREMFRQ, vp->ch, vp->reg.parm.tremfrq);383 /* lfo2 pitch & freq */384 set_fm2frq2(hw, vp);385 386 /* reverb and loop start (reverb 8bit, MSB) */387 351 temp = vp->reg.parm.reverb; 388 352 temp += (int)vp->chan->control[MIDI_CTL_E1_REVERB_DEPTH] * 9 / 10; 389 353 LIMITMAX(temp, 255); 390 354 addr = vp->reg.loopstart; 391 snd_emu10k1_ptr_write(hw, PSST, vp->ch, (temp << 24) | addr); 392 393 /* chorus & loop end (chorus 8bit, MSB) */ 355 psst = (temp << 24) | addr; 356 394 357 addr = vp->reg.loopend; 395 358 temp = vp->reg.parm.chorus; 396 359 temp += (int)chan->control[MIDI_CTL_E3_CHORUS_DEPTH] * 9 / 10; 397 360 LIMITMAX(temp, 255); 398 temp = (temp <<24) | addr; 399 snd_emu10k1_ptr_write(hw, DSL, ch, temp); 400 401 /* clear filter delay memory */ 402 snd_emu10k1_ptr_write(hw, Z1, ch, 0); 403 snd_emu10k1_ptr_write(hw, Z2, ch, 0); 404 405 /* invalidate maps */ 406 temp = (hw->silent_page.addr << hw->address_mode) | (hw->address_mode ? MAP_PTI_MASK1 : MAP_PTI_MASK0); 407 snd_emu10k1_ptr_write(hw, MAPA, ch, temp); 408 snd_emu10k1_ptr_write(hw, MAPB, ch, temp); 409 #if 0 410 /* cache */ 411 { 412 unsigned int val, sample; 413 val = 32; 414 if (vp->reg.sample_mode & SNDRV_SFNT_SAMPLE_8BITS) 415 sample = 0x80808080; 416 else { 417 sample = 0; 418 val *= 2; 419 } 420 421 /* cache */ 422 snd_emu10k1_ptr_write(hw, CCR, ch, 0x1c << 16); 423 snd_emu10k1_ptr_write(hw, CDE, ch, sample); 424 snd_emu10k1_ptr_write(hw, CDF, ch, sample); 425 426 /* invalidate maps */ 427 temp = ((unsigned int)hw->silent_page.addr << hw_address_mode) | (hw->address_mode ? MAP_PTI_MASK1 : MAP_PTI_MASK0); 428 snd_emu10k1_ptr_write(hw, MAPA, ch, temp); 429 snd_emu10k1_ptr_write(hw, MAPB, ch, temp); 430 431 /* fill cache */ 432 val -= 4; 433 val <<= 25; 434 val |= 0x1c << 16; 435 snd_emu10k1_ptr_write(hw, CCR, ch, val); 436 } 437 #endif 438 439 /* Q & current address (Q 4bit value, MSB) */ 361 dsl = (temp << 24) | addr; 362 363 map = (hw->silent_page.addr << hw->address_mode) | (hw->address_mode ? MAP_PTI_MASK1 : MAP_PTI_MASK0); 364 440 365 addr = vp->reg.start; 441 366 temp = vp->reg.parm.filterQ; 442 temp = (temp<<28) | addr;367 ccca = (temp << 28) | addr; 443 368 if (vp->apitch < 0xe400) 444 temp|= CCCA_INTERPROM_0;369 ccca |= CCCA_INTERPROM_0; 445 370 else { 446 371 unsigned int shift = (vp->apitch - 0xe000) >> 10; 447 temp|= shift << 25;372 ccca |= shift << 25; 448 373 } 449 374 if (vp->reg.sample_mode & SNDRV_SFNT_SAMPLE_8BITS) 450 temp |= CCCA_8BITSELECT; 451 snd_emu10k1_ptr_write(hw, CCCA, ch, temp); 452 453 /* reset volume */ 454 temp = (unsigned int)vp->vtarget << 16; 455 snd_emu10k1_ptr_write(hw, VTFT, ch, temp | vp->ftarget); 456 snd_emu10k1_ptr_write(hw, CVCF, ch, temp | 0xff00); 375 ccca |= CCCA_8BITSELECT; 376 377 vtarget = (unsigned int)vp->vtarget << 16; 378 379 snd_emu10k1_ptr_write_multiple(hw, ch, 380 /* channel to be silent and idle */ 381 DCYSUSV, 0, 382 VTFT, VTFT_FILTERTARGET_MASK, 383 CVCF, CVCF_CURRENTFILTER_MASK, 384 PTRX, 0, 385 CPF, 0, 386 387 /* set pitch offset */ 388 IP, vp->apitch, 389 390 /* set envelope parameters */ 391 ENVVAL, vp->reg.parm.moddelay, 392 ATKHLDM, vp->reg.parm.modatkhld, 393 DCYSUSM, vp->reg.parm.moddcysus, 394 ENVVOL, vp->reg.parm.voldelay, 395 ATKHLDV, vp->reg.parm.volatkhld, 396 /* decay/sustain parameter for volume envelope is used 397 for triggerg the voice */ 398 399 /* cutoff and volume */ 400 IFATN, (unsigned int)vp->acutoff << 8 | (unsigned char)vp->avol, 401 402 /* modulation envelope heights */ 403 PEFE, vp->reg.parm.pefe, 404 405 /* lfo1/2 delay */ 406 LFOVAL1, vp->reg.parm.lfo1delay, 407 LFOVAL2, vp->reg.parm.lfo2delay, 408 409 /* lfo1 pitch & cutoff shift */ 410 FMMOD, make_fmmod(vp), 411 /* lfo1 volume & freq */ 412 TREMFRQ, vp->reg.parm.tremfrq, 413 /* lfo2 pitch & freq */ 414 FM2FRQ2, make_fm2frq2(vp), 415 416 /* reverb and loop start (reverb 8bit, MSB) */ 417 PSST, psst, 418 419 /* chorus & loop end (chorus 8bit, MSB) */ 420 DSL, dsl, 421 422 /* clear filter delay memory */ 423 Z1, 0, 424 Z2, 0, 425 426 /* invalidate maps */ 427 MAPA, map, 428 MAPB, map, 429 430 /* Q & current address (Q 4bit value, MSB) */ 431 CCCA, ccca, 432 433 /* reset volume */ 434 VTFT, vtarget | vp->ftarget, 435 CVCF, vtarget | CVCF_CURRENTFILTER_MASK, 436 437 REGLIST_END); 438 439 hw->voices[ch].dirty = 1; 457 440 return 0; 458 441 } … … 464 447 trigger_voice(struct snd_emux_voice *vp) 465 448 { 466 unsigned int temp,ptarget;449 unsigned int ptarget; 467 450 struct snd_emu10k1 *hw; 468 451 struct snd_emu10k1_memblk *emem; … … 479 462 ptarget = IP_TO_CP(vp->apitch); 480 463 #endif 481 /* set pitch target and pan (volume) */ 482 temp = ptarget | (vp->apan << 8) | vp->aaux; 483 snd_emu10k1_ptr_write(hw, PTRX, vp->ch, temp); 484 485 /* pitch target */ 486 snd_emu10k1_ptr_write(hw, CPF, vp->ch, ptarget); 487 488 /* trigger voice */ 489 snd_emu10k1_ptr_write(hw, DCYSUSV, vp->ch, vp->reg.parm.voldcysus|DCYSUSV_CHANNELENABLE_MASK); 464 snd_emu10k1_ptr_write_multiple(hw, vp->ch, 465 /* set pitch target and pan (volume) */ 466 PTRX, ptarget | (vp->apan << 8) | vp->aaux, 467 468 /* current pitch and fractional address */ 469 CPF, ptarget, 470 471 /* enable envelope engine */ 472 DCYSUSV, vp->reg.parm.voldcysus | DCYSUSV_CHANNELENABLE_MASK, 473 474 REGLIST_END); 490 475 } 491 476 492 477 #define MOD_SENSE 18 493 478 494 /* set lfo1 modulation height and cutoff */ 495 static void 496 set_fmmod(struct snd_emu10k1 *hw, struct snd_emux_voice *vp) 497 { 498 unsigned short fmmod; 479 /* calculate lfo1 modulation height and cutoff register */ 480 static u32 481 make_fmmod(struct snd_emux_voice *vp) 482 { 499 483 short pitch; 500 484 unsigned char cutoff; … … 506 490 pitch += (MOD_SENSE * modulation) / 1200; 507 491 LIMITVALUE(pitch, -128, 127); 508 fmmod = ((unsigned char)pitch<<8) | cutoff; 509 snd_emu10k1_ptr_write(hw, FMMOD, vp->ch, fmmod); 510 } 511 512 /* set lfo2 pitch & frequency */ 513 static void 514 set_fm2frq2(struct snd_emu10k1 *hw, struct snd_emux_voice *vp) 515 { 516 unsigned short fm2frq2; 492 return ((unsigned char)pitch << 8) | cutoff; 493 } 494 495 /* calculate set lfo2 pitch & frequency register */ 496 static u32 497 make_fm2frq2(struct snd_emux_voice *vp) 498 { 517 499 short pitch; 518 500 unsigned char freq; … … 524 506 pitch += (MOD_SENSE * modulation) / 1200; 525 507 LIMITVALUE(pitch, -128, 127); 526 fm2frq2 = ((unsigned char)pitch<<8) | freq; 527 snd_emu10k1_ptr_write(hw, FM2FRQ2, vp->ch, fm2frq2); 528 } 529 530 /* set filterQ */ 531 static void 532 set_filterQ(struct snd_emu10k1 *hw, struct snd_emux_voice *vp) 533 { 534 unsigned int val; 535 val = snd_emu10k1_ptr_read(hw, CCCA, vp->ch) & ~CCCA_RESONANCE; 536 val |= (vp->reg.parm.filterQ << 28); 537 snd_emu10k1_ptr_write(hw, CCCA, vp->ch, val); 538 } 508 return ((unsigned char)pitch << 8) | freq; 509 } 510 511 static int get_pitch_shift(struct snd_emux *emu) 512 { 513 struct snd_emu10k1 *hw = emu->hw; 514 515 return (hw->card_capabilities->emu_model && 516 hw->emu1010.word_clock == 44100) ? 0 : -501; 517 } -
GPL/trunk/alsa-kernel/pci/emu10k1/emu10k1_main.c
r717 r772 2 2 /* 3 3 * Copyright (c) by Jaroslav Kysela <perex@perex.cz> 4 * James Courtier-Dutton <James@superbug.co.uk> 5 * Oswald Buddenhagen <oswald.buddenhagen@gmx.de> 4 6 * Creative Labs, Inc. 7 * 5 8 * Routines for control of EMU10K1 chips 6 *7 * Copyright (c) by James Courtier-Dutton <James@superbug.co.uk>8 * Added support for Audigy 2 Value.9 * Added EMU 1010 support.10 * General bug fixes and enhancements.11 *12 * BUGS:13 * --14 *15 * TODO:16 * --17 9 */ 18 10 … … 66 58 void snd_emu10k1_voice_init(struct snd_emu10k1 *emu, int ch) 67 59 { 68 snd_emu10k1_ptr_write(emu, DCYSUSV, ch, 0); 69 snd_emu10k1_ptr_write(emu, IP, ch, 0); 70 snd_emu10k1_ptr_write(emu, VTFT, ch, 0xffff); 71 snd_emu10k1_ptr_write(emu, CVCF, ch, 0xffff); 72 snd_emu10k1_ptr_write(emu, PTRX, ch, 0); 73 snd_emu10k1_ptr_write(emu, CPF, ch, 0); 74 snd_emu10k1_ptr_write(emu, CCR, ch, 0); 75 76 snd_emu10k1_ptr_write(emu, PSST, ch, 0); 77 snd_emu10k1_ptr_write(emu, DSL, ch, 0x10); 78 snd_emu10k1_ptr_write(emu, CCCA, ch, 0); 79 snd_emu10k1_ptr_write(emu, Z1, ch, 0); 80 snd_emu10k1_ptr_write(emu, Z2, ch, 0); 81 snd_emu10k1_ptr_write(emu, FXRT, ch, 0x32100000); 82 83 snd_emu10k1_ptr_write(emu, ATKHLDM, ch, 0); 84 snd_emu10k1_ptr_write(emu, DCYSUSM, ch, 0); 85 snd_emu10k1_ptr_write(emu, IFATN, ch, 0xffff); 86 snd_emu10k1_ptr_write(emu, PEFE, ch, 0); 87 snd_emu10k1_ptr_write(emu, FMMOD, ch, 0); 88 snd_emu10k1_ptr_write(emu, TREMFRQ, ch, 24); /* 1 Hz */ 89 snd_emu10k1_ptr_write(emu, FM2FRQ2, ch, 24); /* 1 Hz */ 90 snd_emu10k1_ptr_write(emu, TEMPENV, ch, 0); 91 92 /*** these are last so OFF prevents writing ***/ 93 snd_emu10k1_ptr_write(emu, LFOVAL2, ch, 0); 94 snd_emu10k1_ptr_write(emu, LFOVAL1, ch, 0); 95 snd_emu10k1_ptr_write(emu, ATKHLDV, ch, 0); 96 snd_emu10k1_ptr_write(emu, ENVVOL, ch, 0); 97 snd_emu10k1_ptr_write(emu, ENVVAL, ch, 0); 60 snd_emu10k1_ptr_write_multiple(emu, ch, 61 DCYSUSV, 0, 62 VTFT, VTFT_FILTERTARGET_MASK, 63 CVCF, CVCF_CURRENTFILTER_MASK, 64 PTRX, 0, 65 CPF, 0, 66 CCR, 0, 67 68 PSST, 0, 69 DSL, 0x10, 70 CCCA, 0, 71 Z1, 0, 72 Z2, 0, 73 FXRT, 0x32100000, 74 75 // The rest is meaningless as long as DCYSUSV_CHANNELENABLE_MASK is zero 76 DCYSUSM, 0, 77 ATKHLDV, 0, 78 ATKHLDM, 0, 79 IP, 0, 80 IFATN, IFATN_FILTERCUTOFF_MASK | IFATN_ATTENUATION_MASK, 81 PEFE, 0, 82 FMMOD, 0, 83 TREMFRQ, 24, /* 1 Hz */ 84 FM2FRQ2, 24, /* 1 Hz */ 85 LFOVAL2, 0, 86 LFOVAL1, 0, 87 ENVVOL, 0, 88 ENVVAL, 0, 89 90 REGLIST_END); 98 91 99 92 /* Audigy extra stuffs */ 100 93 if (emu->audigy) { 101 snd_emu10k1_ptr_write(emu, 0x4c, ch, 0); /* ?? */ 102 snd_emu10k1_ptr_write(emu, 0x4d, ch, 0); /* ?? */ 103 snd_emu10k1_ptr_write(emu, 0x4e, ch, 0); /* ?? */ 104 snd_emu10k1_ptr_write(emu, 0x4f, ch, 0); /* ?? */ 105 snd_emu10k1_ptr_write(emu, A_FXRT1, ch, 0x03020100); 106 snd_emu10k1_ptr_write(emu, A_FXRT2, ch, 0x3f3f3f3f); 107 snd_emu10k1_ptr_write(emu, A_SENDAMOUNTS, ch, 0); 94 snd_emu10k1_ptr_write_multiple(emu, ch, 95 A_CSBA, 0, 96 A_CSDC, 0, 97 A_CSFE, 0, 98 A_CSHG, 0, 99 A_FXRT1, 0x03020100, 100 A_FXRT2, 0x07060504, 101 A_SENDAMOUNTS, 0, 102 REGLIST_END); 108 103 } 109 104 } … … 149 144 }; 150 145 151 static int snd_emu10k1_init(struct snd_emu10k1 *emu, int enable_ir , int resume)146 static int snd_emu10k1_init(struct snd_emu10k1 *emu, int enable_ir) 152 147 { 153 148 unsigned int silent_page; … … 159 154 HCFG_MUTEBUTTONENABLE, emu->port + HCFG); 160 155 161 /* reset recording buffers */162 snd_emu10k1_ptr_write(emu, MICBS, 0, ADCBS_BUFSIZE_NONE);163 snd_emu10k1_ptr_write(emu, MICBA, 0, 0);164 snd_emu10k1_ptr_write(emu, FXBS, 0, ADCBS_BUFSIZE_NONE);165 snd_emu10k1_ptr_write(emu, FXBA, 0, 0);166 snd_emu10k1_ptr_write(emu, ADCBS, 0, ADCBS_BUFSIZE_NONE);167 snd_emu10k1_ptr_write(emu, ADCBA, 0, 0);168 169 /* disable channel interrupt */170 156 outl(0, emu->port + INTE); 171 snd_emu10k1_ptr_write(emu, CLIEL, 0, 0); 172 snd_emu10k1_ptr_write(emu, CLIEH, 0, 0); 173 snd_emu10k1_ptr_write(emu, SOLEL, 0, 0); 174 snd_emu10k1_ptr_write(emu, SOLEH, 0, 0); 157 158 snd_emu10k1_ptr_write_multiple(emu, 0, 159 /* reset recording buffers */ 160 MICBS, ADCBS_BUFSIZE_NONE, 161 MICBA, 0, 162 FXBS, ADCBS_BUFSIZE_NONE, 163 FXBA, 0, 164 ADCBS, ADCBS_BUFSIZE_NONE, 165 ADCBA, 0, 166 167 /* disable channel interrupt */ 168 CLIEL, 0, 169 CLIEH, 0, 170 171 /* disable stop on loop end */ 172 SOLEL, 0, 173 SOLEH, 0, 174 175 REGLIST_END); 175 176 176 177 if (emu->audigy) { … … 186 187 snd_emu10k1_voice_init(emu, ch); 187 188 188 snd_emu10k1_ptr_write(emu, SPCS0, 0, emu->spdif_bits[0]); 189 snd_emu10k1_ptr_write(emu, SPCS1, 0, emu->spdif_bits[1]); 190 snd_emu10k1_ptr_write(emu, SPCS2, 0, emu->spdif_bits[2]); 191 192 if (emu->card_capabilities->ca0151_chip) { /* audigy2 */ 189 snd_emu10k1_ptr_write_multiple(emu, 0, 190 SPCS0, emu->spdif_bits[0], 191 SPCS1, emu->spdif_bits[1], 192 SPCS2, emu->spdif_bits[2], 193 REGLIST_END); 194 195 if (emu->card_capabilities->emu_model) { 196 } else if (emu->card_capabilities->ca0151_chip) { /* audigy2 */ 193 197 /* Hacks for Alice3 to work independent of haP16V driver */ 194 198 /* Setup SRCMulti_I2S SamplingRate */ 199 #ifndef TARGET_OS2 200 snd_emu10k1_ptr_write(emu, A_I2S_CAPTURE_RATE, 0, A_I2S_CAPTURE_96000); 201 #else 195 202 tmp = snd_emu10k1_ptr_read(emu, A_SPDIF_SAMPLERATE, 0); 196 203 tmp &= 0xfffff1ff; 197 204 tmp |= (0x2<<9); 198 205 snd_emu10k1_ptr_write(emu, A_SPDIF_SAMPLERATE, 0, tmp); 199 206 #endif 200 207 /* Setup SRCSel (Enable Spdif,I2S SRCMulti) */ 201 208 snd_emu10k1_ptr20_write(emu, SRCSel, 0, 0x14); … … 208 215 /* Set playback routing. */ 209 216 snd_emu10k1_ptr20_write(emu, CAPTURE_P16V_SOURCE, 0, 0x78e4); 210 } 211 if (emu->card_capabilities->ca0108_chip) { /* audigy2 Value */ 217 } else if (emu->card_capabilities->ca0108_chip) { /* audigy2 Value */ 212 218 /* Hacks for Alice3 to work independent of haP16V driver */ 213 219 dev_info(emu->card->dev, "Audigy2 value: Special config.\n"); 214 220 /* Setup SRCMulti_I2S SamplingRate */ 221 #ifndef TARGET_OS2 222 snd_emu10k1_ptr_write(emu, A_I2S_CAPTURE_RATE, 0, A_I2S_CAPTURE_96000); 223 #else 215 224 tmp = snd_emu10k1_ptr_read(emu, A_SPDIF_SAMPLERATE, 0); 216 225 tmp &= 0xfffff1ff; 217 226 tmp |= (0x2<<9); 218 227 snd_emu10k1_ptr_write(emu, A_SPDIF_SAMPLERATE, 0, tmp); 219 228 #endif 220 229 /* Setup SRCSel (Enable Spdif,I2S SRCMulti) */ 221 outl(0x600000, emu->port + 0x20); 222 outl(0x14, emu->port + 0x24); 230 snd_emu10k1_ptr20_write(emu, P17V_SRCSel, 0, 0x14); 223 231 224 232 /* Setup SRCMulti Input Audio Enable */ 225 outl(0x7b0000, emu->port + 0x20); 226 outl(0xFF000000, emu->port + 0x24); 233 snd_emu10k1_ptr20_write(emu, P17V_MIXER_I2S_ENABLE, 0, 0xFF000000); 227 234 228 235 /* Setup SPDIF Out Audio Enable */ … … 230 237 * so no need for a mixer switch 231 238 */ 232 outl(0x7a0000, emu->port + 0x20);233 outl(0xFF000000, emu->port + 0x24); 234 tmp = in l(emu->port + A_IOCFG) & ~0x8; /* Clear bit 3 */235 out l(tmp, emu->port + A_IOCFG);239 snd_emu10k1_ptr20_write(emu, P17V_MIXER_SPDIF_ENABLE, 0, 0xFF000000); 240 241 tmp = inw(emu->port + A_IOCFG) & ~0x8; /* Clear bit 3 */ 242 outw(tmp, emu->port + A_IOCFG); 236 243 } 237 244 if (emu->card_capabilities->spi_dac) { /* Audigy 2 ZS Notebook with DAC Wolfson WM8768/WM8568 */ … … 253 260 * GPIO7: Unknown 254 261 */ 255 out l(0x76, emu->port + A_IOCFG); /* Windows uses 0x3f76 */262 outw(0x76, emu->port + A_IOCFG); /* Windows uses 0x3f76 */ 256 263 } 257 264 if (emu->card_capabilities->i2c_adc) { /* Audigy 2 ZS Notebook with ADC Wolfson WM8775 */ … … 259 266 260 267 snd_emu10k1_ptr20_write(emu, P17V_I2S_SRC_SEL, 0, 0x2020205f); 261 tmp = in l(emu->port + A_IOCFG);262 out l(tmp | 0x4, emu->port + A_IOCFG); /* Set bit 2 for mic input */263 tmp = in l(emu->port + A_IOCFG);268 tmp = inw(emu->port + A_IOCFG); 269 outw(tmp | 0x4, emu->port + A_IOCFG); /* Set bit 2 for mic input */ 270 tmp = inw(emu->port + A_IOCFG); 264 271 size = ARRAY_SIZE(i2c_adc_init); 265 272 for (n = 0; n < size; n++) … … 274 281 snd_emu10k1_ptr_write(emu, PTB, 0, emu->ptb_pages.addr); 275 282 snd_emu10k1_ptr_write(emu, TCB, 0, 0); /* taken from original driver */ 276 snd_emu10k1_ptr_write(emu, TCBS, 0, 4); /* taken from original driver */283 snd_emu10k1_ptr_write(emu, TCBS, 0, TCBS_BUFFSIZE_256K); /* taken from original driver */ 277 284 278 285 silent_page = (emu->silent_page.addr << emu->address_mode) | (emu->address_mode ? MAP_PTI_MASK1 : MAP_PTI_MASK0); … … 317 324 ; /* Disable A_IOCFG for Audigy 2 ZS Notebook */ 318 325 } else if (emu->audigy) { 319 u nsigned int reg = inl(emu->port + A_IOCFG);320 out l(reg | A_IOCFG_GPOUT2, emu->port + A_IOCFG);326 u16 reg = inw(emu->port + A_IOCFG); 327 outw(reg | A_IOCFG_GPOUT2, emu->port + A_IOCFG); 321 328 udelay(500); 322 out l(reg | A_IOCFG_GPOUT1 | A_IOCFG_GPOUT2, emu->port + A_IOCFG);329 outw(reg | A_IOCFG_GPOUT1 | A_IOCFG_GPOUT2, emu->port + A_IOCFG); 323 330 udelay(100); 324 out l(reg, emu->port + A_IOCFG);331 outw(reg, emu->port + A_IOCFG); 325 332 } else { 326 333 unsigned int reg = inl(emu->port + HCFG); … … 338 345 ; /* Disable A_IOCFG for Audigy 2 ZS Notebook */ 339 346 } else if (emu->audigy) { /* enable analog output */ 340 u nsigned int reg = inl(emu->port + A_IOCFG);341 out l(reg | A_IOCFG_GPOUT0, emu->port + A_IOCFG);347 u16 reg = inw(emu->port + A_IOCFG); 348 outw(reg | A_IOCFG_GPOUT0, emu->port + A_IOCFG); 342 349 } 343 350 … … 363 370 ; /* Disable A_IOCFG for Audigy 2 ZS Notebook */ 364 371 } else if (emu->audigy) { 365 out l(inl(emu->port + A_IOCFG) & ~0x44, emu->port + A_IOCFG);372 outw(inw(emu->port + A_IOCFG) & ~0x44, emu->port + A_IOCFG); 366 373 367 374 if (emu->card_capabilities->ca0151_chip) { /* audigy2 */ … … 369 376 * This has to be done after init ALice3 I2SOut beyond 48KHz. 370 377 * So, sequence is important. */ 371 out l(inl(emu->port + A_IOCFG) | 0x0040, emu->port + A_IOCFG);378 outw(inw(emu->port + A_IOCFG) | 0x0040, emu->port + A_IOCFG); 372 379 } else if (emu->card_capabilities->ca0108_chip) { /* audigy2 value */ 373 380 /* Unmute Analog now. */ 374 out l(inl(emu->port + A_IOCFG) | 0x0060, emu->port + A_IOCFG);381 outw(inw(emu->port + A_IOCFG) | 0x0060, emu->port + A_IOCFG); 375 382 } else { 376 383 /* Disable routing from AC97 line out to Front speakers */ 377 out l(inl(emu->port + A_IOCFG) | 0x0080, emu->port + A_IOCFG);384 outw(inw(emu->port + A_IOCFG) | 0x0080, emu->port + A_IOCFG); 378 385 } 379 386 } … … 397 404 #endif 398 405 399 snd_emu10k1_intr_enable(emu, INTE_PCIERRORENABLE); 406 if (emu->card_capabilities->emu_model) 407 snd_emu10k1_intr_enable(emu, INTE_PCIERRORENABLE | INTE_A_GPIOENABLE); 408 else 409 snd_emu10k1_intr_enable(emu, INTE_PCIERRORENABLE); 400 410 } 401 411 … … 407 417 408 418 /* 409 * Shutdown the chip419 * Shutdown the voices 410 420 */ 411 for (ch = 0; ch < NUM_G; ch++)412 snd_emu10k1_ptr_write(emu, DCYSUSV, ch, 0);413 421 for (ch = 0; ch < NUM_G; ch++) { 414 snd_emu10k1_ptr_write(emu, VTFT, ch, 0); 415 snd_emu10k1_ptr_write(emu, CVCF, ch, 0); 416 snd_emu10k1_ptr_write(emu, PTRX, ch, 0); 417 snd_emu10k1_ptr_write(emu, CPF, ch, 0); 418 } 419 420 /* reset recording buffers */ 421 snd_emu10k1_ptr_write(emu, MICBS, 0, 0); 422 snd_emu10k1_ptr_write(emu, MICBA, 0, 0); 423 snd_emu10k1_ptr_write(emu, FXBS, 0, 0); 424 snd_emu10k1_ptr_write(emu, FXBA, 0, 0); 425 snd_emu10k1_ptr_write(emu, FXWC, 0, 0); 426 snd_emu10k1_ptr_write(emu, ADCBS, 0, ADCBS_BUFSIZE_NONE); 427 snd_emu10k1_ptr_write(emu, ADCBA, 0, 0); 428 snd_emu10k1_ptr_write(emu, TCBS, 0, TCBS_BUFFSIZE_16K); 429 snd_emu10k1_ptr_write(emu, TCB, 0, 0); 422 snd_emu10k1_ptr_write_multiple(emu, ch, 423 DCYSUSV, 0, 424 VTFT, 0, 425 CVCF, 0, 426 PTRX, 0, 427 CPF, 0, 428 REGLIST_END); 429 } 430 431 // stop the DSP 430 432 if (emu->audigy) 431 433 snd_emu10k1_ptr_write(emu, A_DBG, 0, A_DBG_SINGLE_STEP); … … 433 435 snd_emu10k1_ptr_write(emu, DBG, 0, EMU10K1_DBG_SINGLE_STEP); 434 436 435 /* disable channel interrupt */ 436 snd_emu10k1_ptr_write(emu, CLIEL, 0, 0); 437 snd_emu10k1_ptr_write(emu, CLIEH, 0, 0); 438 snd_emu10k1_ptr_write(emu, SOLEL, 0, 0); 439 snd_emu10k1_ptr_write(emu, SOLEH, 0, 0); 437 snd_emu10k1_ptr_write_multiple(emu, 0, 438 /* reset recording buffers */ 439 MICBS, 0, 440 MICBA, 0, 441 FXBS, 0, 442 FXBA, 0, 443 FXWC, 0, 444 ADCBS, ADCBS_BUFSIZE_NONE, 445 ADCBA, 0, 446 TCBS, TCBS_BUFFSIZE_16K, 447 TCB, 0, 448 449 /* disable channel interrupt */ 450 CLIEL, 0, 451 CLIEH, 0, 452 SOLEL, 0, 453 SOLEH, 0, 454 455 PTB, 0, 456 457 REGLIST_END); 440 458 441 459 /* disable audio and lock cache */ 442 460 outl(HCFG_LOCKSOUNDCACHE | HCFG_LOCKTANKCACHE_MASK | HCFG_MUTEBUTTONENABLE, emu->port + HCFG); 443 snd_emu10k1_ptr_write(emu, PTB, 0, 0);444 461 445 462 return 0; … … 660 677 { 661 678 int n, i; 662 int reg; 663 int value; 664 __always_unused unsigned int write_post; 665 unsigned long flags; 679 u16 reg; 680 u8 value; 681 __always_unused u16 write_post; 666 682 667 683 if (!fw_entry) … … 669 685 670 686 /* The FPGA is a Xilinx Spartan IIE XC2S50E */ 687 /* On E-MU 0404b it is a Xilinx Spartan III XC3S50 */ 671 688 /* GPIO7 -> FPGA PGMN 672 689 * GPIO6 -> FPGA CCLK … … 674 691 * FPGA CONFIG OFF -> FPGA PGMN 675 692 */ 676 spin_lock_irq save(&emu->emu_lock, flags);677 out l(0x00, emu->port + A_IOCFG); /* Set PGMN low for 1uS. */678 write_post = in l(emu->port + A_IOCFG);693 spin_lock_irq(&emu->emu_lock); 694 outw(0x00, emu->port + A_GPIO); /* Set PGMN low for 100uS. */ 695 write_post = inw(emu->port + A_GPIO); 679 696 udelay(100); 680 out l(0x80, emu->port + A_IOCFG); /* Leave bit 7 set during netlist setup. */681 write_post = in l(emu->port + A_IOCFG);697 outw(0x80, emu->port + A_GPIO); /* Leave bit 7 set during netlist setup. */ 698 write_post = inw(emu->port + A_GPIO); 682 699 udelay(100); /* Allow FPGA memory to clean */ 683 700 for (n = 0; n < fw_entry->size; n++) { … … 688 705 reg = reg | 0x20; 689 706 value = value >> 1; 690 out l(reg, emu->port + A_IOCFG);691 write_post = in l(emu->port + A_IOCFG);692 out l(reg | 0x40, emu->port + A_IOCFG);693 write_post = in l(emu->port + A_IOCFG);707 outw(reg, emu->port + A_GPIO); 708 write_post = inw(emu->port + A_GPIO); 709 outw(reg | 0x40, emu->port + A_GPIO); 710 write_post = inw(emu->port + A_GPIO); 694 711 } 695 712 } 696 713 /* After programming, set GPIO bit 4 high again. */ 697 out l(0x10, emu->port + A_IOCFG);698 write_post = in l(emu->port + A_IOCFG);699 spin_unlock_irq restore(&emu->emu_lock, flags);714 outw(0x10, emu->port + A_GPIO); 715 write_post = inw(emu->port + A_GPIO); 716 spin_unlock_irq(&emu->emu_lock); 700 717 701 718 return 0; … … 736 753 } 737 754 738 static void emu1010_firmware_work(struct work_struct *work) 755 static void snd_emu1010_load_dock_firmware(struct snd_emu10k1 *emu) 756 { 757 u32 tmp, tmp2; 758 int err; 759 760 // The docking events clearly arrive prematurely - while the 761 // Dock's FPGA seems to be successfully programmed, the Dock 762 // fails to initialize subsequently if we don't give it some 763 // time to "warm up" here. 764 msleep(200); 765 766 dev_info(emu->card->dev, "emu1010: Loading Audio Dock Firmware\n"); 767 /* Return to Audio Dock programming mode */ 768 snd_emu1010_fpga_write(emu, EMU_HANA_FPGA_CONFIG, 769 EMU_HANA_FPGA_CONFIG_AUDIODOCK); 770 err = snd_emu1010_load_firmware(emu, 1, &emu->dock_fw); 771 if (err < 0) 772 return; 773 snd_emu1010_fpga_write(emu, EMU_HANA_FPGA_CONFIG, 0); 774 775 snd_emu1010_fpga_read(emu, EMU_HANA_ID, &tmp); 776 dev_dbg(emu->card->dev, "emu1010: EMU_HANA+DOCK_ID = 0x%x\n", tmp); 777 if ((tmp & 0x1f) != 0x15) { 778 /* FPGA failed to be programmed */ 779 dev_err(emu->card->dev, 780 "emu1010: Loading Audio Dock Firmware failed, reg = 0x%x\n", 781 tmp); 782 return; 783 } 784 dev_info(emu->card->dev, "emu1010: Audio Dock Firmware loaded\n"); 785 786 snd_emu1010_fpga_read(emu, EMU_DOCK_MAJOR_REV, &tmp); 787 snd_emu1010_fpga_read(emu, EMU_DOCK_MINOR_REV, &tmp2); 788 dev_info(emu->card->dev, "Audio Dock ver: %u.%u\n", tmp, tmp2); 789 790 /* Allow DLL to settle, to sync clocking between 1010 and Dock */ 791 msleep(10); 792 } 793 794 static void emu1010_dock_event(struct snd_emu10k1 *emu) 795 { 796 u32 reg; 797 798 snd_emu1010_fpga_read(emu, EMU_HANA_OPTION_CARDS, ®); /* OPTIONS: Which cards are attached to the EMU */ 799 if (reg & EMU_HANA_OPTION_DOCK_OFFLINE) { 800 /* Audio Dock attached */ 801 snd_emu1010_load_dock_firmware(emu); 802 /* Unmute all. Default is muted after a firmware load */ 803 snd_emu1010_fpga_write(emu, EMU_HANA_UNMUTE, EMU_UNMUTE); 804 } else if (!(reg & EMU_HANA_OPTION_DOCK_ONLINE)) { 805 /* Audio Dock removed */ 806 dev_info(emu->card->dev, "emu1010: Audio Dock detached\n"); 807 /* The hardware auto-mutes all, so we unmute again */ 808 snd_emu1010_fpga_write(emu, EMU_HANA_UNMUTE, EMU_UNMUTE); 809 } 810 } 811 812 static void emu1010_clock_event(struct snd_emu10k1 *emu) 813 { 814 struct snd_ctl_elem_id id; 815 816 spin_lock_irq(&emu->reg_lock); 817 // This is the only thing that can actually happen. 818 emu->emu1010.clock_source = emu->emu1010.clock_fallback; 819 emu->emu1010.wclock = 1 - emu->emu1010.clock_source; 820 snd_emu1010_update_clock(emu); 821 spin_unlock_irq(&emu->reg_lock); 822 snd_ctl_build_ioff(&id, emu->ctl_clock_source, 0); 823 snd_ctl_notify(emu->card, SNDRV_CTL_EVENT_MASK_VALUE, &id); 824 } 825 826 static void emu1010_work(struct work_struct *work) 739 827 { 740 828 struct snd_emu10k1 *emu; 741 u32 tmp, tmp2, reg; 742 int err; 743 744 emu = container_of(work, struct snd_emu10k1, 745 emu1010.firmware_work.work); 829 u32 sts; 830 831 emu = container_of(work, struct snd_emu10k1, emu1010.work); 746 832 if (emu->card->shutdown) 747 833 return; … … 750 836 return; 751 837 #endif 752 snd_emu1010_fpga_read(emu, EMU_HANA_IRQ_STATUS, &tmp); /* IRQ Status */ 753 snd_emu1010_fpga_read(emu, EMU_HANA_OPTION_CARDS, ®); /* OPTIONS: Which cards are attached to the EMU */ 754 if (reg & EMU_HANA_OPTION_DOCK_OFFLINE) { 755 /* Audio Dock attached */ 756 /* Return to Audio Dock programming mode */ 757 dev_info(emu->card->dev, 758 "emu1010: Loading Audio Dock Firmware\n"); 759 snd_emu1010_fpga_write(emu, EMU_HANA_FPGA_CONFIG, 760 EMU_HANA_FPGA_CONFIG_AUDIODOCK); 761 err = snd_emu1010_load_firmware(emu, 1, &emu->dock_fw); 762 if (err < 0) 763 goto next; 764 765 snd_emu1010_fpga_write(emu, EMU_HANA_FPGA_CONFIG, 0); 766 snd_emu1010_fpga_read(emu, EMU_HANA_IRQ_STATUS, &tmp); 767 dev_info(emu->card->dev, 768 "emu1010: EMU_HANA+DOCK_IRQ_STATUS = 0x%x\n", tmp); 769 /* ID, should read & 0x7f = 0x55 when FPGA programmed. */ 770 snd_emu1010_fpga_read(emu, EMU_HANA_ID, &tmp); 771 dev_info(emu->card->dev, 772 "emu1010: EMU_HANA+DOCK_ID = 0x%x\n", tmp); 773 if ((tmp & 0x1f) != 0x15) { 774 /* FPGA failed to be programmed */ 775 dev_info(emu->card->dev, 776 "emu1010: Loading Audio Dock Firmware file failed, reg = 0x%x\n", 777 tmp); 778 goto next; 779 } 780 dev_info(emu->card->dev, 781 "emu1010: Audio Dock Firmware loaded\n"); 782 snd_emu1010_fpga_read(emu, EMU_DOCK_MAJOR_REV, &tmp); 783 snd_emu1010_fpga_read(emu, EMU_DOCK_MINOR_REV, &tmp2); 784 dev_info(emu->card->dev, "Audio Dock ver: %u.%u\n", tmp, tmp2); 785 /* Sync clocking between 1010 and Dock */ 786 /* Allow DLL to settle */ 787 msleep(10); 788 /* Unmute all. Default is muted after a firmware load */ 789 snd_emu1010_fpga_write(emu, EMU_HANA_UNMUTE, EMU_UNMUTE); 790 } else if (!reg && emu->emu1010.last_reg) { 791 /* Audio Dock removed */ 792 dev_info(emu->card->dev, "emu1010: Audio Dock detached\n"); 793 /* Unmute all */ 794 snd_emu1010_fpga_write(emu, EMU_HANA_UNMUTE, EMU_UNMUTE); 795 } 796 797 next: 798 emu->emu1010.last_reg = reg; 799 if (!emu->card->shutdown) 800 schedule_delayed_work(&emu->emu1010.firmware_work, 801 msecs_to_jiffies(1000)); 838 839 snd_emu1010_fpga_read(emu, EMU_HANA_IRQ_STATUS, &sts); 840 841 // The distinction of the IRQ status bits is unreliable, 842 // so we dispatch later based on option card status. 843 if (sts & (EMU_HANA_IRQ_DOCK | EMU_HANA_IRQ_DOCK_LOST)) 844 emu1010_dock_event(emu); 845 846 if (sts & EMU_HANA_IRQ_WCLK_CHANGED) 847 emu1010_clock_event(emu); 848 } 849 850 static void emu1010_interrupt(struct snd_emu10k1 *emu) 851 { 852 // We get an interrupt on each GPIO input pin change, but we 853 // care only about the ones triggered by the dedicated pin. 854 u16 sts = inw(emu->port + A_GPIO); 855 u16 bit = emu->card_capabilities->ca0108_chip ? 0x2000 : 0x8000; 856 if (!(sts & bit)) 857 return; 858 859 schedule_work(&emu->emu1010.work); 802 860 } 803 861 //#endif 804 862 805 863 /* 806 * EMU-1010 - details found out from this driver, official MS Win drivers,807 * testing the card:808 *809 * Audigy2 (aka Alice2):810 * ---------------------811 * * communication over PCI812 * * conversion of 32-bit data coming over EMU32 links from HANA FPGA813 * to 2 x 16-bit, using internal DSP instructions814 * * slave mode, clock supplied by HANA815 * * linked to HANA using:816 * 32 x 32-bit serial EMU32 output channels817 * 16 x EMU32 input channels818 * (?) x I2S I/O channels (?)819 *820 * FPGA (aka HANA):821 * ---------------822 * * provides all (?) physical inputs and outputs of the card823 * (ADC, DAC, SPDIF I/O, ADAT I/O, etc.)824 * * provides clock signal for the card and Alice2825 * * two crystals - for 44.1kHz and 48kHz multiples826 * * provides internal routing of signal sources to signal destinations827 * * inputs/outputs to Alice2 - see above828 *829 864 * Current status of the driver: 830 865 * ---------------------------- … … 836 871 static int snd_emu10k1_emu1010_init(struct snd_emu10k1 *emu) 837 872 { 838 unsigned int i;839 873 u32 tmp, tmp2, reg; 840 874 int err; 841 875 842 876 dev_info(emu->card->dev, "emu1010: Special config.\n"); 843 /* AC97 2.1, Any 16Meg of 4Gig address, Auto-Mute, EMU32 Slave, 844 * Lock Sound Memory Cache, Lock Tank Memory Cache, 845 * Mute all codecs. 846 */ 847 outl(0x0005a00c, emu->port + HCFG); 848 /* AC97 2.1, Any 16Meg of 4Gig address, Auto-Mute, EMU32 Slave, 849 * Lock Tank Memory Cache, 850 * Mute all codecs. 851 */ 852 outl(0x0005a004, emu->port + HCFG); 853 /* AC97 2.1, Any 16Meg of 4Gig address, Auto-Mute, EMU32 Slave, 854 * Mute all codecs. 855 */ 856 outl(0x0005a000, emu->port + HCFG); 857 /* AC97 2.1, Any 16Meg of 4Gig address, Auto-Mute, EMU32 Slave, 858 * Mute all codecs. 859 */ 860 outl(0x0005a000, emu->port + HCFG); 877 878 /* Mute, and disable audio and lock cache, just in case. 879 * Proper init follows in snd_emu10k1_init(). */ 880 outl(HCFG_LOCKSOUNDCACHE | HCFG_LOCKTANKCACHE_MASK, emu->port + HCFG); 861 881 862 882 /* Disable 48Volt power to Audio Dock */ … … 870 890 /* Return to programming mode */ 871 891 872 snd_emu1010_fpga_write(emu, EMU_HANA_FPGA_CONFIG, 0x02);892 snd_emu1010_fpga_write(emu, EMU_HANA_FPGA_CONFIG, EMU_HANA_FPGA_CONFIG_HANA); 873 893 } 874 894 snd_emu1010_fpga_read(emu, EMU_HANA_ID, ®); … … 907 927 snd_emu1010_fpga_read(emu, EMU_HANA_OPTION_CARDS, ®); 908 928 dev_info(emu->card->dev, "emu1010: Card options = 0x%x\n", reg); 909 snd_emu1010_fpga_read(emu, EMU_HANA_OPTION_CARDS, ®);910 dev_info(emu->card->dev, "emu1010: Card options = 0x%x\n", reg);911 snd_emu1010_fpga_read(emu, EMU_HANA_OPTICAL_TYPE, &tmp);912 /* Optical -> ADAT I/O*/913 /* 0 : SPDIF914 * 1 : ADAT915 */916 emu->emu1010.optical_in = 1; /* IN_ADAT */917 emu->emu1010.optical_out = 1; /* IN_ADAT */918 tmp = 0;919 tmp = (emu->emu1010.optical_in ? EMU_HANA_OPTICAL_IN_ADAT : 0) |920 (emu->emu1010.optical_out ? EMU_HANA_OPTICAL_OUT_ADAT : 0);929 if (reg & EMU_HANA_OPTION_DOCK_OFFLINE) 930 snd_emu1010_load_dock_firmware(emu); 931 if (emu->card_capabilities->no_adat) { 932 emu->emu1010.optical_in = 0; /* IN_SPDIF */ 933 emu->emu1010.optical_out = 0; /* OUT_SPDIF */ 934 } else { 935 /* Optical -> ADAT I/O */ 936 emu->emu1010.optical_in = 1; /* IN_ADAT */ 937 emu->emu1010.optical_out = 1; /* OUT_ADAT */ 938 } 939 tmp = (emu->emu1010.optical_in ? EMU_HANA_OPTICAL_IN_ADAT : EMU_HANA_OPTICAL_IN_SPDIF) | 940 (emu->emu1010.optical_out ? EMU_HANA_OPTICAL_OUT_ADAT : EMU_HANA_OPTICAL_OUT_SPDIF); 921 941 snd_emu1010_fpga_write(emu, EMU_HANA_OPTICAL_TYPE, tmp); 922 snd_emu1010_fpga_read(emu, EMU_HANA_ADC_PADS, &tmp);923 942 /* Set no attenuation on Audio Dock pads. */ 924 snd_emu1010_fpga_write(emu, EMU_HANA_ADC_PADS, 0x00);925 943 emu->emu1010.adc_pads = 0x00; 926 snd_emu1010_fpga_ read(emu, EMU_HANA_DOCK_MISC, &tmp);944 snd_emu1010_fpga_write(emu, EMU_HANA_ADC_PADS, emu->emu1010.adc_pads); 927 945 /* Unmute Audio dock DACs, Headphone source DAC-4. */ 928 snd_emu1010_fpga_write(emu, EMU_HANA_DOCK_MISC, 0x30); 929 snd_emu1010_fpga_write(emu, EMU_HANA_DOCK_LEDS_2, 0x12); 930 snd_emu1010_fpga_read(emu, EMU_HANA_DAC_PADS, &tmp); 946 snd_emu1010_fpga_write(emu, EMU_HANA_DOCK_MISC, EMU_HANA_DOCK_PHONES_192_DAC4); 931 947 /* DAC PADs. */ 932 snd_emu1010_fpga_write(emu, EMU_HANA_DAC_PADS, 0x0f); 933 emu->emu1010.dac_pads = 0x0f; 934 snd_emu1010_fpga_read(emu, EMU_HANA_DOCK_MISC, &tmp); 935 snd_emu1010_fpga_write(emu, EMU_HANA_DOCK_MISC, 0x30); 936 snd_emu1010_fpga_read(emu, EMU_HANA_SPDIF_MODE, &tmp); 948 emu->emu1010.dac_pads = EMU_HANA_DOCK_DAC_PAD1 | EMU_HANA_DOCK_DAC_PAD2 | 949 EMU_HANA_DOCK_DAC_PAD3 | EMU_HANA_DOCK_DAC_PAD4; 950 snd_emu1010_fpga_write(emu, EMU_HANA_DAC_PADS, emu->emu1010.dac_pads); 937 951 /* SPDIF Format. Set Consumer mode, 24bit, copy enable */ 938 snd_emu1010_fpga_write(emu, EMU_HANA_SPDIF_MODE, 0x10);952 snd_emu1010_fpga_write(emu, EMU_HANA_SPDIF_MODE, EMU_HANA_SPDIF_MODE_RX_INVALID); 939 953 /* MIDI routing */ 940 snd_emu1010_fpga_write(emu, EMU_HANA_MIDI_IN, 0x19); 941 /* Unknown. */ 942 snd_emu1010_fpga_write(emu, EMU_HANA_MIDI_OUT, 0x0c); 943 /* IRQ Enable: All on */ 944 /* snd_emu1010_fpga_write(emu, 0x09, 0x0f ); */ 945 /* IRQ Enable: All off */ 946 snd_emu1010_fpga_write(emu, EMU_HANA_IRQ_ENABLE, 0x00); 947 948 snd_emu1010_fpga_read(emu, EMU_HANA_OPTION_CARDS, ®); 949 dev_info(emu->card->dev, "emu1010: Card options3 = 0x%x\n", reg); 954 snd_emu1010_fpga_write(emu, EMU_HANA_MIDI_IN, EMU_HANA_MIDI_INA_FROM_HAMOA | EMU_HANA_MIDI_INB_FROM_DOCK2); 955 snd_emu1010_fpga_write(emu, EMU_HANA_MIDI_OUT, EMU_HANA_MIDI_OUT_DOCK2 | EMU_HANA_MIDI_OUT_SYNC2); 956 957 emu->gpio_interrupt = emu1010_interrupt; 958 // Note: The Audigy INTE is set later 959 snd_emu1010_fpga_write(emu, EMU_HANA_IRQ_ENABLE, 960 EMU_HANA_IRQ_DOCK | EMU_HANA_IRQ_DOCK_LOST | EMU_HANA_IRQ_WCLK_CHANGED); 961 snd_emu1010_fpga_read(emu, EMU_HANA_IRQ_STATUS, ®); // Clear pending IRQs 962 963 emu->emu1010.clock_source = 1; /* 48000 */ 964 emu->emu1010.clock_fallback = 1; /* 48000 */ 950 965 /* Default WCLK set to 48kHz. */ 951 snd_emu1010_fpga_write(emu, EMU_HANA_DEFCLOCK, 0x00);966 snd_emu1010_fpga_write(emu, EMU_HANA_DEFCLOCK, EMU_HANA_DEFCLOCK_48K); 952 967 /* Word Clock source, Internal 48kHz x1 */ 968 emu->emu1010.wclock = EMU_HANA_WCLOCK_INT_48K; 953 969 snd_emu1010_fpga_write(emu, EMU_HANA_WCLOCK, EMU_HANA_WCLOCK_INT_48K); 954 970 /* snd_emu1010_fpga_write(emu, EMU_HANA_WCLOCK, EMU_HANA_WCLOCK_INT_48K | EMU_HANA_WCLOCK_4X); */ 955 /* Audio Dock LEDs. */ 956 snd_emu1010_fpga_write(emu, EMU_HANA_DOCK_LEDS_2, 0x12); 957 958 #if 0 959 /* For 96kHz */ 960 snd_emu1010_fpga_link_dst_src_write(emu, 961 EMU_DST_ALICE2_EMU32_0, EMU_SRC_HAMOA_ADC_LEFT1); 962 snd_emu1010_fpga_link_dst_src_write(emu, 963 EMU_DST_ALICE2_EMU32_1, EMU_SRC_HAMOA_ADC_RIGHT1); 964 snd_emu1010_fpga_link_dst_src_write(emu, 965 EMU_DST_ALICE2_EMU32_4, EMU_SRC_HAMOA_ADC_LEFT2); 966 snd_emu1010_fpga_link_dst_src_write(emu, 967 EMU_DST_ALICE2_EMU32_5, EMU_SRC_HAMOA_ADC_RIGHT2); 968 #endif 969 #if 0 970 /* For 192kHz */ 971 snd_emu1010_fpga_link_dst_src_write(emu, 972 EMU_DST_ALICE2_EMU32_0, EMU_SRC_HAMOA_ADC_LEFT1); 973 snd_emu1010_fpga_link_dst_src_write(emu, 974 EMU_DST_ALICE2_EMU32_1, EMU_SRC_HAMOA_ADC_RIGHT1); 975 snd_emu1010_fpga_link_dst_src_write(emu, 976 EMU_DST_ALICE2_EMU32_2, EMU_SRC_HAMOA_ADC_LEFT2); 977 snd_emu1010_fpga_link_dst_src_write(emu, 978 EMU_DST_ALICE2_EMU32_3, EMU_SRC_HAMOA_ADC_RIGHT2); 979 snd_emu1010_fpga_link_dst_src_write(emu, 980 EMU_DST_ALICE2_EMU32_4, EMU_SRC_HAMOA_ADC_LEFT3); 981 snd_emu1010_fpga_link_dst_src_write(emu, 982 EMU_DST_ALICE2_EMU32_5, EMU_SRC_HAMOA_ADC_RIGHT3); 983 snd_emu1010_fpga_link_dst_src_write(emu, 984 EMU_DST_ALICE2_EMU32_6, EMU_SRC_HAMOA_ADC_LEFT4); 985 snd_emu1010_fpga_link_dst_src_write(emu, 986 EMU_DST_ALICE2_EMU32_7, EMU_SRC_HAMOA_ADC_RIGHT4); 987 #endif 988 #if 1 989 /* For 48kHz */ 990 snd_emu1010_fpga_link_dst_src_write(emu, 991 EMU_DST_ALICE2_EMU32_0, EMU_SRC_DOCK_MIC_A1); 992 snd_emu1010_fpga_link_dst_src_write(emu, 993 EMU_DST_ALICE2_EMU32_1, EMU_SRC_DOCK_MIC_B1); 994 snd_emu1010_fpga_link_dst_src_write(emu, 995 EMU_DST_ALICE2_EMU32_2, EMU_SRC_HAMOA_ADC_LEFT2); 996 snd_emu1010_fpga_link_dst_src_write(emu, 997 EMU_DST_ALICE2_EMU32_3, EMU_SRC_HAMOA_ADC_LEFT2); 998 snd_emu1010_fpga_link_dst_src_write(emu, 999 EMU_DST_ALICE2_EMU32_4, EMU_SRC_DOCK_ADC1_LEFT1); 1000 snd_emu1010_fpga_link_dst_src_write(emu, 1001 EMU_DST_ALICE2_EMU32_5, EMU_SRC_DOCK_ADC1_RIGHT1); 1002 snd_emu1010_fpga_link_dst_src_write(emu, 1003 EMU_DST_ALICE2_EMU32_6, EMU_SRC_DOCK_ADC2_LEFT1); 1004 snd_emu1010_fpga_link_dst_src_write(emu, 1005 EMU_DST_ALICE2_EMU32_7, EMU_SRC_DOCK_ADC2_RIGHT1); 1006 /* Pavel Hofman - setting defaults for 8 more capture channels 1007 * Defaults only, users will set their own values anyways, let's 1008 * just copy/paste. 1009 */ 1010 1011 snd_emu1010_fpga_link_dst_src_write(emu, 1012 EMU_DST_ALICE2_EMU32_8, EMU_SRC_DOCK_MIC_A1); 1013 snd_emu1010_fpga_link_dst_src_write(emu, 1014 EMU_DST_ALICE2_EMU32_9, EMU_SRC_DOCK_MIC_B1); 1015 snd_emu1010_fpga_link_dst_src_write(emu, 1016 EMU_DST_ALICE2_EMU32_A, EMU_SRC_HAMOA_ADC_LEFT2); 1017 snd_emu1010_fpga_link_dst_src_write(emu, 1018 EMU_DST_ALICE2_EMU32_B, EMU_SRC_HAMOA_ADC_LEFT2); 1019 snd_emu1010_fpga_link_dst_src_write(emu, 1020 EMU_DST_ALICE2_EMU32_C, EMU_SRC_DOCK_ADC1_LEFT1); 1021 snd_emu1010_fpga_link_dst_src_write(emu, 1022 EMU_DST_ALICE2_EMU32_D, EMU_SRC_DOCK_ADC1_RIGHT1); 1023 snd_emu1010_fpga_link_dst_src_write(emu, 1024 EMU_DST_ALICE2_EMU32_E, EMU_SRC_DOCK_ADC2_LEFT1); 1025 snd_emu1010_fpga_link_dst_src_write(emu, 1026 EMU_DST_ALICE2_EMU32_F, EMU_SRC_DOCK_ADC2_RIGHT1); 1027 #endif 1028 #if 0 1029 /* Original */ 1030 snd_emu1010_fpga_link_dst_src_write(emu, 1031 EMU_DST_ALICE2_EMU32_4, EMU_SRC_HANA_ADAT); 1032 snd_emu1010_fpga_link_dst_src_write(emu, 1033 EMU_DST_ALICE2_EMU32_5, EMU_SRC_HANA_ADAT + 1); 1034 snd_emu1010_fpga_link_dst_src_write(emu, 1035 EMU_DST_ALICE2_EMU32_6, EMU_SRC_HANA_ADAT + 2); 1036 snd_emu1010_fpga_link_dst_src_write(emu, 1037 EMU_DST_ALICE2_EMU32_7, EMU_SRC_HANA_ADAT + 3); 1038 snd_emu1010_fpga_link_dst_src_write(emu, 1039 EMU_DST_ALICE2_EMU32_8, EMU_SRC_HANA_ADAT + 4); 1040 snd_emu1010_fpga_link_dst_src_write(emu, 1041 EMU_DST_ALICE2_EMU32_9, EMU_SRC_HANA_ADAT + 5); 1042 snd_emu1010_fpga_link_dst_src_write(emu, 1043 EMU_DST_ALICE2_EMU32_A, EMU_SRC_HANA_ADAT + 6); 1044 snd_emu1010_fpga_link_dst_src_write(emu, 1045 EMU_DST_ALICE2_EMU32_B, EMU_SRC_HANA_ADAT + 7); 1046 snd_emu1010_fpga_link_dst_src_write(emu, 1047 EMU_DST_ALICE2_EMU32_C, EMU_SRC_DOCK_MIC_A1); 1048 snd_emu1010_fpga_link_dst_src_write(emu, 1049 EMU_DST_ALICE2_EMU32_D, EMU_SRC_DOCK_MIC_B1); 1050 snd_emu1010_fpga_link_dst_src_write(emu, 1051 EMU_DST_ALICE2_EMU32_E, EMU_SRC_HAMOA_ADC_LEFT2); 1052 snd_emu1010_fpga_link_dst_src_write(emu, 1053 EMU_DST_ALICE2_EMU32_F, EMU_SRC_HAMOA_ADC_LEFT2); 1054 #endif 1055 for (i = 0; i < 0x20; i++) { 1056 /* AudioDock Elink <- Silence */ 1057 snd_emu1010_fpga_link_dst_src_write(emu, 0x0100 + i, EMU_SRC_SILENCE); 1058 } 1059 for (i = 0; i < 4; i++) { 1060 /* Hana SPDIF Out <- Silence */ 1061 snd_emu1010_fpga_link_dst_src_write(emu, 0x0200 + i, EMU_SRC_SILENCE); 1062 } 1063 for (i = 0; i < 7; i++) { 1064 /* Hamoa DAC <- Silence */ 1065 snd_emu1010_fpga_link_dst_src_write(emu, 0x0300 + i, EMU_SRC_SILENCE); 1066 } 1067 for (i = 0; i < 7; i++) { 1068 /* Hana ADAT Out <- Silence */ 1069 snd_emu1010_fpga_link_dst_src_write(emu, EMU_DST_HANA_ADAT + i, EMU_SRC_SILENCE); 1070 } 1071 snd_emu1010_fpga_link_dst_src_write(emu, 1072 EMU_DST_ALICE_I2S0_LEFT, EMU_SRC_DOCK_ADC1_LEFT1); 1073 snd_emu1010_fpga_link_dst_src_write(emu, 1074 EMU_DST_ALICE_I2S0_RIGHT, EMU_SRC_DOCK_ADC1_RIGHT1); 1075 snd_emu1010_fpga_link_dst_src_write(emu, 1076 EMU_DST_ALICE_I2S1_LEFT, EMU_SRC_DOCK_ADC2_LEFT1); 1077 snd_emu1010_fpga_link_dst_src_write(emu, 1078 EMU_DST_ALICE_I2S1_RIGHT, EMU_SRC_DOCK_ADC2_RIGHT1); 1079 snd_emu1010_fpga_link_dst_src_write(emu, 1080 EMU_DST_ALICE_I2S2_LEFT, EMU_SRC_DOCK_ADC3_LEFT1); 1081 snd_emu1010_fpga_link_dst_src_write(emu, 1082 EMU_DST_ALICE_I2S2_RIGHT, EMU_SRC_DOCK_ADC3_RIGHT1); 1083 snd_emu1010_fpga_write(emu, EMU_HANA_UNMUTE, 0x01); /* Unmute all */ 1084 1085 snd_emu1010_fpga_read(emu, EMU_HANA_OPTION_CARDS, &tmp); 1086 1087 /* AC97 1.03, Any 32Meg of 2Gig address, Auto-Mute, EMU32 Slave, 1088 * Lock Sound Memory Cache, Lock Tank Memory Cache, 1089 * Mute all codecs. 1090 */ 1091 outl(0x0000a000, emu->port + HCFG); 1092 /* AC97 1.03, Any 32Meg of 2Gig address, Auto-Mute, EMU32 Slave, 1093 * Lock Sound Memory Cache, Lock Tank Memory Cache, 1094 * Un-Mute all codecs. 1095 */ 1096 outl(0x0000a001, emu->port + HCFG); 1097 1098 /* Initial boot complete. Now patches */ 1099 1100 snd_emu1010_fpga_read(emu, EMU_HANA_OPTION_CARDS, &tmp); 1101 snd_emu1010_fpga_write(emu, EMU_HANA_MIDI_IN, 0x19); /* MIDI Route */ 1102 snd_emu1010_fpga_write(emu, EMU_HANA_MIDI_OUT, 0x0c); /* Unknown */ 1103 snd_emu1010_fpga_write(emu, EMU_HANA_MIDI_IN, 0x19); /* MIDI Route */ 1104 snd_emu1010_fpga_write(emu, EMU_HANA_MIDI_OUT, 0x0c); /* Unknown */ 1105 snd_emu1010_fpga_read(emu, EMU_HANA_SPDIF_MODE, &tmp); 1106 snd_emu1010_fpga_write(emu, EMU_HANA_SPDIF_MODE, 0x10); /* SPDIF Format spdif (or 0x11 for aes/ebu) */ 1107 1108 #if 0 1109 snd_emu1010_fpga_link_dst_src_write(emu, 1110 EMU_DST_HAMOA_DAC_LEFT1, EMU_SRC_ALICE_EMU32B + 2); /* ALICE2 bus 0xa2 */ 1111 snd_emu1010_fpga_link_dst_src_write(emu, 1112 EMU_DST_HAMOA_DAC_RIGHT1, EMU_SRC_ALICE_EMU32B + 3); /* ALICE2 bus 0xa3 */ 1113 snd_emu1010_fpga_link_dst_src_write(emu, 1114 EMU_DST_HANA_SPDIF_LEFT1, EMU_SRC_ALICE_EMU32A + 2); /* ALICE2 bus 0xb2 */ 1115 snd_emu1010_fpga_link_dst_src_write(emu, 1116 EMU_DST_HANA_SPDIF_RIGHT1, EMU_SRC_ALICE_EMU32A + 3); /* ALICE2 bus 0xb3 */ 1117 #endif 1118 /* Default outputs */ 1119 if (emu->card_capabilities->emu_model == EMU_MODEL_EMU1616) { 1120 /* 1616(M) cardbus default outputs */ 1121 /* ALICE2 bus 0xa0 */ 1122 snd_emu1010_fpga_link_dst_src_write(emu, 1123 EMU_DST_DOCK_DAC1_LEFT1, EMU_SRC_ALICE_EMU32A + 0); 1124 emu->emu1010.output_source[0] = 17; 1125 snd_emu1010_fpga_link_dst_src_write(emu, 1126 EMU_DST_DOCK_DAC1_RIGHT1, EMU_SRC_ALICE_EMU32A + 1); 1127 emu->emu1010.output_source[1] = 18; 1128 snd_emu1010_fpga_link_dst_src_write(emu, 1129 EMU_DST_DOCK_DAC2_LEFT1, EMU_SRC_ALICE_EMU32A + 2); 1130 emu->emu1010.output_source[2] = 19; 1131 snd_emu1010_fpga_link_dst_src_write(emu, 1132 EMU_DST_DOCK_DAC2_RIGHT1, EMU_SRC_ALICE_EMU32A + 3); 1133 emu->emu1010.output_source[3] = 20; 1134 snd_emu1010_fpga_link_dst_src_write(emu, 1135 EMU_DST_DOCK_DAC3_LEFT1, EMU_SRC_ALICE_EMU32A + 4); 1136 emu->emu1010.output_source[4] = 21; 1137 snd_emu1010_fpga_link_dst_src_write(emu, 1138 EMU_DST_DOCK_DAC3_RIGHT1, EMU_SRC_ALICE_EMU32A + 5); 1139 emu->emu1010.output_source[5] = 22; 1140 /* ALICE2 bus 0xa0 */ 1141 snd_emu1010_fpga_link_dst_src_write(emu, 1142 EMU_DST_MANA_DAC_LEFT, EMU_SRC_ALICE_EMU32A + 0); 1143 emu->emu1010.output_source[16] = 17; 1144 snd_emu1010_fpga_link_dst_src_write(emu, 1145 EMU_DST_MANA_DAC_RIGHT, EMU_SRC_ALICE_EMU32A + 1); 1146 emu->emu1010.output_source[17] = 18; 1147 } else { 1148 /* ALICE2 bus 0xa0 */ 1149 snd_emu1010_fpga_link_dst_src_write(emu, 1150 EMU_DST_DOCK_DAC1_LEFT1, EMU_SRC_ALICE_EMU32A + 0); 1151 emu->emu1010.output_source[0] = 21; 1152 snd_emu1010_fpga_link_dst_src_write(emu, 1153 EMU_DST_DOCK_DAC1_RIGHT1, EMU_SRC_ALICE_EMU32A + 1); 1154 emu->emu1010.output_source[1] = 22; 1155 snd_emu1010_fpga_link_dst_src_write(emu, 1156 EMU_DST_DOCK_DAC2_LEFT1, EMU_SRC_ALICE_EMU32A + 2); 1157 emu->emu1010.output_source[2] = 23; 1158 snd_emu1010_fpga_link_dst_src_write(emu, 1159 EMU_DST_DOCK_DAC2_RIGHT1, EMU_SRC_ALICE_EMU32A + 3); 1160 emu->emu1010.output_source[3] = 24; 1161 snd_emu1010_fpga_link_dst_src_write(emu, 1162 EMU_DST_DOCK_DAC3_LEFT1, EMU_SRC_ALICE_EMU32A + 4); 1163 emu->emu1010.output_source[4] = 25; 1164 snd_emu1010_fpga_link_dst_src_write(emu, 1165 EMU_DST_DOCK_DAC3_RIGHT1, EMU_SRC_ALICE_EMU32A + 5); 1166 emu->emu1010.output_source[5] = 26; 1167 snd_emu1010_fpga_link_dst_src_write(emu, 1168 EMU_DST_DOCK_DAC4_LEFT1, EMU_SRC_ALICE_EMU32A + 6); 1169 emu->emu1010.output_source[6] = 27; 1170 snd_emu1010_fpga_link_dst_src_write(emu, 1171 EMU_DST_DOCK_DAC4_RIGHT1, EMU_SRC_ALICE_EMU32A + 7); 1172 emu->emu1010.output_source[7] = 28; 1173 /* ALICE2 bus 0xa0 */ 1174 snd_emu1010_fpga_link_dst_src_write(emu, 1175 EMU_DST_DOCK_PHONES_LEFT1, EMU_SRC_ALICE_EMU32A + 0); 1176 emu->emu1010.output_source[8] = 21; 1177 snd_emu1010_fpga_link_dst_src_write(emu, 1178 EMU_DST_DOCK_PHONES_RIGHT1, EMU_SRC_ALICE_EMU32A + 1); 1179 emu->emu1010.output_source[9] = 22; 1180 /* ALICE2 bus 0xa0 */ 1181 snd_emu1010_fpga_link_dst_src_write(emu, 1182 EMU_DST_DOCK_SPDIF_LEFT1, EMU_SRC_ALICE_EMU32A + 0); 1183 emu->emu1010.output_source[10] = 21; 1184 snd_emu1010_fpga_link_dst_src_write(emu, 1185 EMU_DST_DOCK_SPDIF_RIGHT1, EMU_SRC_ALICE_EMU32A + 1); 1186 emu->emu1010.output_source[11] = 22; 1187 /* ALICE2 bus 0xa0 */ 1188 snd_emu1010_fpga_link_dst_src_write(emu, 1189 EMU_DST_HANA_SPDIF_LEFT1, EMU_SRC_ALICE_EMU32A + 0); 1190 emu->emu1010.output_source[12] = 21; 1191 snd_emu1010_fpga_link_dst_src_write(emu, 1192 EMU_DST_HANA_SPDIF_RIGHT1, EMU_SRC_ALICE_EMU32A + 1); 1193 emu->emu1010.output_source[13] = 22; 1194 /* ALICE2 bus 0xa0 */ 1195 snd_emu1010_fpga_link_dst_src_write(emu, 1196 EMU_DST_HAMOA_DAC_LEFT1, EMU_SRC_ALICE_EMU32A + 0); 1197 emu->emu1010.output_source[14] = 21; 1198 snd_emu1010_fpga_link_dst_src_write(emu, 1199 EMU_DST_HAMOA_DAC_RIGHT1, EMU_SRC_ALICE_EMU32A + 1); 1200 emu->emu1010.output_source[15] = 22; 1201 /* ALICE2 bus 0xa0 */ 1202 snd_emu1010_fpga_link_dst_src_write(emu, 1203 EMU_DST_HANA_ADAT, EMU_SRC_ALICE_EMU32A + 0); 1204 emu->emu1010.output_source[16] = 21; 1205 snd_emu1010_fpga_link_dst_src_write(emu, 1206 EMU_DST_HANA_ADAT + 1, EMU_SRC_ALICE_EMU32A + 1); 1207 emu->emu1010.output_source[17] = 22; 1208 snd_emu1010_fpga_link_dst_src_write(emu, 1209 EMU_DST_HANA_ADAT + 2, EMU_SRC_ALICE_EMU32A + 2); 1210 emu->emu1010.output_source[18] = 23; 1211 snd_emu1010_fpga_link_dst_src_write(emu, 1212 EMU_DST_HANA_ADAT + 3, EMU_SRC_ALICE_EMU32A + 3); 1213 emu->emu1010.output_source[19] = 24; 1214 snd_emu1010_fpga_link_dst_src_write(emu, 1215 EMU_DST_HANA_ADAT + 4, EMU_SRC_ALICE_EMU32A + 4); 1216 emu->emu1010.output_source[20] = 25; 1217 snd_emu1010_fpga_link_dst_src_write(emu, 1218 EMU_DST_HANA_ADAT + 5, EMU_SRC_ALICE_EMU32A + 5); 1219 emu->emu1010.output_source[21] = 26; 1220 snd_emu1010_fpga_link_dst_src_write(emu, 1221 EMU_DST_HANA_ADAT + 6, EMU_SRC_ALICE_EMU32A + 6); 1222 emu->emu1010.output_source[22] = 27; 1223 snd_emu1010_fpga_link_dst_src_write(emu, 1224 EMU_DST_HANA_ADAT + 7, EMU_SRC_ALICE_EMU32A + 7); 1225 emu->emu1010.output_source[23] = 28; 1226 } 1227 /* TEMP: Select SPDIF in/out */ 1228 /* snd_emu1010_fpga_write(emu, EMU_HANA_OPTICAL_TYPE, 0x0); */ /* Output spdif */ 1229 1230 /* TEMP: Select 48kHz SPDIF out */ 1231 snd_emu1010_fpga_write(emu, EMU_HANA_UNMUTE, 0x0); /* Mute all */ 1232 snd_emu1010_fpga_write(emu, EMU_HANA_DEFCLOCK, 0x0); /* Default fallback clock 48kHz */ 1233 /* Word Clock source, Internal 48kHz x1 */ 1234 snd_emu1010_fpga_write(emu, EMU_HANA_WCLOCK, EMU_HANA_WCLOCK_INT_48K); 1235 /* snd_emu1010_fpga_write(emu, EMU_HANA_WCLOCK, EMU_HANA_WCLOCK_INT_48K | EMU_HANA_WCLOCK_4X); */ 1236 emu->emu1010.internal_clock = 1; /* 48000 */ 1237 snd_emu1010_fpga_write(emu, EMU_HANA_DOCK_LEDS_2, 0x12); /* Set LEDs on Audio Dock */ 1238 snd_emu1010_fpga_write(emu, EMU_HANA_UNMUTE, 0x1); /* Unmute all */ 1239 /* snd_emu1010_fpga_write(emu, 0x7, 0x0); */ /* Mute all */ 1240 /* snd_emu1010_fpga_write(emu, 0x7, 0x1); */ /* Unmute all */ 1241 /* snd_emu1010_fpga_write(emu, 0xe, 0x12); */ /* Set LEDs on Audio Dock */ 971 snd_emu1010_update_clock(emu); 972 973 // The routes are all set to EMU_SRC_SILENCE due to the reset, 974 // so it is safe to simply enable the outputs. 975 snd_emu1010_fpga_write(emu, EMU_HANA_UNMUTE, EMU_UNMUTE); 1242 976 1243 977 return 0; … … 1265 999 snd_emu1010_fpga_write(emu, EMU_HANA_DOCK_PWR, 0); 1266 1000 } 1267 cancel_ delayed_work_sync(&emu->emu1010.firmware_work);1001 cancel_work_sync(&emu->emu1010.work); 1268 1002 release_firmware(emu->firmware); 1269 1003 release_firmware(emu->dock_fw); … … 1353 1087 * CA0151: None 1354 1088 */ 1089 /* 1090 * A_IOCFG Input (GPIO) 1091 * 0x400 = Front analog jack plugged in. (Green socket) 1092 * 0x1000 = Rear analog jack plugged in. (Black socket) 1093 * 0x2000 = Center/LFE analog jack plugged in. (Orange socket) 1094 * A_IOCFG Output (GPIO) 1095 * 0x60 = Sound out of front Left. 1096 * Win sets it to 0xXX61 1097 */ 1355 1098 {.vendor = 0x1102, .device = 0x0008, .subsystem = 0x10011102, 1356 1099 .driver = "Audigy2", .name = "SB Audigy 2 Value [SB0400]", … … 1401 1144 .i2c_adc = 1, 1402 1145 .spk71 = 1} , 1146 /* This is MAEM8950 "Mana" */ 1147 /* Attach MicroDock[M] to make it an E-MU 1616[m]. */ 1148 /* Does NOT support sync daughter card (obviously). */ 1403 1149 /* Tested by James@superbug.co.uk 4th Nov 2007. */ 1404 1150 {.vendor = 0x1102, .device = 0x0008, .subsystem = 0x42011102, 1405 .driver = "Audigy2", .name = "E- mu 1010 Notebook[MAEM8950]",1151 .driver = "Audigy2", .name = "E-MU 02 CardBus [MAEM8950]", 1406 1152 .id = "EMU1010", 1407 1153 .emu10k2_chip = 1, … … 1411 1157 .emu_model = EMU_MODEL_EMU1616}, 1412 1158 /* Tested by James@superbug.co.uk 4th Nov 2007. */ 1413 /* This is MAEM8960, 0202 is MAEM 8980 */ 1159 /* This is MAEM8960 "Hana3", 0202 is MAEM8980 */ 1160 /* Attach 0202 daughter card to make it an E-MU 1212m, OR a 1161 * MicroDock[M] to make it an E-MU 1616[m]. */ 1162 /* Does NOT support sync daughter card. */ 1414 1163 {.vendor = 0x1102, .device = 0x0008, .subsystem = 0x40041102, 1415 .driver = "Audigy2", .name = "E- mu1010b PCI [MAEM8960]",1164 .driver = "Audigy2", .name = "E-MU 1010b PCI [MAEM8960]", 1416 1165 .id = "EMU1010", 1417 1166 .emu10k2_chip = 1, … … 1421 1170 /* Tested by Maxim Kachur <mcdebugger@duganet.ru> 17th Oct 2012. */ 1422 1171 /* This is MAEM8986, 0202 is MAEM8980 */ 1172 /* Attach 0202 daughter card to make it an E-MU 1212m, OR a 1173 * MicroDockM to make it an E-MU 1616m. The non-m 1174 * version was never sold with this card, but should 1175 * still work. */ 1176 /* Does NOT support sync daughter card. */ 1423 1177 {.vendor = 0x1102, .device = 0x0008, .subsystem = 0x40071102, 1424 .driver = "Audigy2", .name = "E- mu1010 PCIe [MAEM8986]",1178 .driver = "Audigy2", .name = "E-MU 1010 PCIe [MAEM8986]", 1425 1179 .id = "EMU1010", 1426 1180 .emu10k2_chip = 1, … … 1429 1183 .emu_model = EMU_MODEL_EMU1010B}, /* EMU 1010 PCIe */ 1430 1184 /* Tested by James@superbug.co.uk 8th July 2005. */ 1431 /* This is MAEM8810, 0202 is MAEM8820 */ 1185 /* This is MAEM8810 "Hana", 0202 is MAEM8820 "Hamoa" */ 1186 /* Attach 0202 daughter card to make it an E-MU 1212m, OR an 1187 * AudioDock[M] to make it an E-MU 1820[m]. */ 1188 /* Supports sync daughter card. */ 1432 1189 {.vendor = 0x1102, .device = 0x0004, .subsystem = 0x40011102, 1433 .driver = "Audigy2", .name = "E- mu1010 [MAEM8810]",1190 .driver = "Audigy2", .name = "E-MU 1010 [MAEM8810]", 1434 1191 .id = "EMU1010", 1435 1192 .emu10k2_chip = 1, … … 1437 1194 .spk71 = 1, 1438 1195 .emu_model = EMU_MODEL_EMU1010}, /* EMU 1010 old revision */ 1439 /* EMU0404b */ 1196 /* This is MAEM8852 "HanaLiteLite" */ 1197 /* Supports sync daughter card. */ 1198 /* Tested by oswald.buddenhagen@gmx.de Mar 2023. */ 1440 1199 {.vendor = 0x1102, .device = 0x0008, .subsystem = 0x40021102, 1441 .driver = "Audigy2", .name = "E- mu0404b PCI [MAEM8852]",1200 .driver = "Audigy2", .name = "E-MU 0404b PCI [MAEM8852]", 1442 1201 .id = "EMU0404", 1443 1202 .emu10k2_chip = 1, 1444 1203 .ca0108_chip = 1, 1445 .spk71 = 1, 1204 .spk20 = 1, 1205 .no_adat = 1, 1446 1206 .emu_model = EMU_MODEL_EMU0404}, /* EMU 0404 new revision */ 1207 /* This is MAEM8850 "HanaLite" */ 1208 /* Supports sync daughter card. */ 1447 1209 /* Tested by James@superbug.co.uk 20-3-2007. */ 1448 1210 {.vendor = 0x1102, .device = 0x0004, .subsystem = 0x40021102, 1449 .driver = "Audigy2", .name = "E- mu0404 [MAEM8850]",1211 .driver = "Audigy2", .name = "E-MU 0404 [MAEM8850]", 1450 1212 .id = "EMU0404", 1451 1213 .emu10k2_chip = 1, 1452 1214 .ca0102_chip = 1, 1453 .spk71 = 1, 1215 .spk20 = 1, 1216 .no_adat = 1, 1454 1217 .emu_model = EMU_MODEL_EMU0404}, /* EMU 0404 */ 1455 1218 /* EMU0404 PCIe */ 1219 /* Does NOT support sync daughter card. */ 1456 1220 {.vendor = 0x1102, .device = 0x0008, .subsystem = 0x40051102, 1457 .driver = "Audigy2", .name = "E- mu0404 PCIe [MAEM8984]",1221 .driver = "Audigy2", .name = "E-MU 0404 PCIe [MAEM8984]", 1458 1222 .id = "EMU0404", 1459 1223 .emu10k2_chip = 1, 1460 1224 .ca0108_chip = 1, 1461 .spk71 = 1, 1225 .spk20 = 1, 1226 .no_adat = 1, 1462 1227 .emu_model = EMU_MODEL_EMU0404}, /* EMU 0404 PCIe ver_03 */ 1463 /* Note that all E-mu cards require kernel 2.6 or newer. */1464 1228 {.vendor = 0x1102, .device = 0x0008, 1465 1229 .driver = "Audigy2", .name = "SB Audigy 2 Value [Unknown]", … … 1542 1306 .adc_1361t = 1, /* 24 bit capture instead of 16bit */ 1543 1307 .ac97_chip = 1} , 1308 /* Audigy 2 Platinum EX */ 1309 /* Win driver sets A_IOCFG output to 0x1c00 */ 1544 1310 {.vendor = 0x1102, .device = 0x0004, .subsystem = 0x10051102, 1545 1311 .driver = "Audigy2", .name = "Audigy 2 Platinum EX [SB0280]", … … 1562 1328 .invert_shared_spdif = 1, /* digital/analog switch swapped */ 1563 1329 .ac97_chip = 1} , 1330 /* Audigy 2 Platinum */ 1331 /* Win driver sets A_IOCFG output to 0xa00 */ 1564 1332 {.vendor = 0x1102, .device = 0x0004, .subsystem = 0x10021102, 1565 1333 .driver = "Audigy2", .name = "SB Audigy 2 Platinum [SB0240P]", … … 1667 1435 .ac97_chip = 1, 1668 1436 .sblive51 = 1} , 1437 /* SB Live! Platinum */ 1438 /* Win driver sets A_IOCFG output to 0 */ 1439 /* Tested by Jonathan Dowland <jon@dow.land> Apr 2023. */ 1669 1440 {.vendor = 0x1102, .device = 0x0002, .subsystem = 0x80401102, 1670 1441 .driver = "EMU10K1", .name = "SB Live! Platinum [CT4760P]", … … 1716 1487 .sblive51 = 1} , 1717 1488 {.vendor = 0x1102, .device = 0x0002, .subsystem = 0x40011102, 1718 .driver = "EMU10K1", .name = "E- muAPS [PC545]",1489 .driver = "EMU10K1", .name = "E-MU APS [PC545]", 1719 1490 .id = "APS", 1720 1491 .emu10k1_chip = 1, … … 1761 1532 emu->iommu_workaround = false; 1762 1533 1763 if (!iommu_present(emu->card->dev->bus))1764 return;1765 1766 1534 domain = iommu_get_domain_for_dev(emu->card->dev); 1767 if ( domain &&domain->type == IOMMU_DOMAIN_IDENTITY)1535 if (!domain || domain->type == IOMMU_DOMAIN_IDENTITY) 1768 1536 return; 1769 1537 … … 1810 1578 emu->synth = NULL; 1811 1579 emu->get_synth_voice = NULL; 1812 INIT_ DELAYED_WORK(&emu->emu1010.firmware_work, emu1010_firmware_work);1580 INIT_WORK(&emu->emu1010.work, emu1010_work); 1813 1581 /* read revision & serial */ 1814 1582 #ifndef TARGET_OS2 … … 1925 1693 pci_set_master(pci); 1926 1694 1927 emu->fx8010.fxbus_mask = 0x303f; 1695 // The masks are not used for Audigy. 1696 // FIXME: these should come from the card_capabilites table. 1928 1697 if (extin_mask == 0) 1929 extin_mask = 0x3fcf; 1698 extin_mask = 0x3fcf; // EXTIN_* 1930 1699 if (extout_mask == 0) 1931 extout_mask = 0x7fff; 1700 extout_mask = 0x7fff; // EXTOUT_* 1932 1701 emu->fx8010.extin_mask = extin_mask; 1933 1702 emu->fx8010.extout_mask = extout_mask; … … 1994 1763 1995 1764 /* set up voice indices */ 1996 for (idx = 0; idx < NUM_G; idx++) { 1997 emu->voices[idx].emu = emu; 1765 for (idx = 0; idx < NUM_G; idx++) 1998 1766 emu->voices[idx].number = idx; 1999 } 2000 2001 err = snd_emu10k1_init(emu, enable_ir, 0); 1767 1768 err = snd_emu10k1_init(emu, enable_ir); 2002 1769 if (err < 0) 2003 1770 return err; … … 2031 1798 }; 2032 1799 static const unsigned char saved_regs_audigy[] = { 2033 A_ADCIDX, A_MICIDX, A_FXWC1, A_FXWC2, A_ SAMPLE_RATE,1800 A_ADCIDX, A_MICIDX, A_FXWC1, A_FXWC2, A_EHC, 2034 1801 A_FXRT2, A_SENDAMOUNTS, A_FXRT1, 2035 1802 0xff /* end */ … … 2082 1849 } 2083 1850 if (emu->audigy) 2084 emu->saved_a_iocfg = in l(emu->port + A_IOCFG);1851 emu->saved_a_iocfg = inw(emu->port + A_IOCFG); 2085 1852 emu->saved_hcfg = inl(emu->port + HCFG); 2086 1853 } … … 2096 1863 else 2097 1864 snd_emu10k1_ptr_write(emu, AC97SLOT, 0, AC97SLOT_CNTR|AC97SLOT_LFE); 2098 snd_emu10k1_init(emu, emu->enable_ir , 1);1865 snd_emu10k1_init(emu, emu->enable_ir); 2099 1866 } 2100 1867 … … 2109 1876 /* resore for spdif */ 2110 1877 if (emu->audigy) 2111 out l(emu->saved_a_iocfg, emu->port + A_IOCFG);1878 outw(emu->saved_a_iocfg, emu->port + A_IOCFG); 2112 1879 outl(emu->saved_hcfg, emu->port + HCFG); 2113 1880 -
GPL/trunk/alsa-kernel/pci/emu10k1/emu10k1_synth.c
r679 r772 27 27 struct snd_emu10k1 *hw; 28 28 struct snd_emu10k1_synth_arg *arg; 29 unsigned long flags;30 29 31 30 arg = SNDRV_SEQ_DEVICE_ARGPTR(dev); … … 48 47 emux->max_voices = arg->max_voices; 49 48 emux->num_ports = arg->seq_ports; 50 emux->pitch_shift = -501;51 49 emux->memhdr = hw->memhdr; 52 50 /* maximum two ports */ … … 62 60 } 63 61 64 spin_lock_irq save(&hw->voice_lock, flags);62 spin_lock_irq(&hw->voice_lock); 65 63 hw->synth = emux; 66 64 hw->get_synth_voice = snd_emu10k1_synth_get_voice; 67 spin_unlock_irq restore(&hw->voice_lock, flags);65 spin_unlock_irq(&hw->voice_lock); 68 66 69 67 dev->driver_data = emux; … … 77 75 struct snd_emux *emux; 78 76 struct snd_emu10k1 *hw; 79 unsigned long flags;80 77 81 78 if (dev->driver_data == NULL) … … 85 82 86 83 hw = emux->hw; 87 spin_lock_irq save(&hw->voice_lock, flags);84 spin_lock_irq(&hw->voice_lock); 88 85 hw->synth = NULL; 89 86 hw->get_synth_voice = NULL; 90 spin_unlock_irq restore(&hw->voice_lock, flags);87 spin_unlock_irq(&hw->voice_lock); 91 88 92 89 snd_emux_free(emux); -
GPL/trunk/alsa-kernel/pci/emu10k1/emufx.c
r703 r772 2 2 /* 3 3 * Copyright (c) by Jaroslav Kysela <perex@perex.cz> 4 * James Courtier-Dutton <James@superbug.co.uk> 5 * Oswald Buddenhagen <oswald.buddenhagen@gmx.de> 4 6 * Creative Labs, Inc. 7 * 5 8 * Routines for effect processor FX8010 6 *7 * Copyright (c) by James Courtier-Dutton <James@superbug.co.uk>8 * Added EMU 1010 support.9 *10 * BUGS:11 * --12 *13 * TODO:14 * --15 9 */ 16 10 … … 48 42 */ 49 43 50 static const char * const fxbuses[16] = { 44 // Playback channel labels; corresponds with the public FXBUS_* defines. 45 // Unlike the tables below, this is not determined by the hardware. 46 const char * const snd_emu10k1_fxbus[32] = { 51 47 /* 0x00 */ "PCM Left", 52 48 /* 0x01 */ "PCM Right", 53 /* 0x02 */ "PCM SurroundLeft",54 /* 0x03 */ "PCM SurroundRight",49 /* 0x02 */ "PCM Rear Left", 50 /* 0x03 */ "PCM Rear Right", 55 51 /* 0x04 */ "MIDI Left", 56 52 /* 0x05 */ "MIDI Right", 57 /* 0x06 */ " Center",58 /* 0x07 */ " LFE",59 /* 0x08 */ NULL,60 /* 0x09 */ NULL,53 /* 0x06 */ "PCM Center", 54 /* 0x07 */ "PCM LFE", 55 /* 0x08 */ "PCM Front Left", 56 /* 0x09 */ "PCM Front Right", 61 57 /* 0x0a */ NULL, 62 58 /* 0x0b */ NULL, 63 59 /* 0x0c */ "MIDI Reverb", 64 60 /* 0x0d */ "MIDI Chorus", 65 /* 0x0e */ NULL, 66 /* 0x0f */ NULL 61 /* 0x0e */ "PCM Side Left", 62 /* 0x0f */ "PCM Side Right", 63 /* 0x10 */ NULL, 64 /* 0x11 */ NULL, 65 /* 0x12 */ NULL, 66 /* 0x13 */ NULL, 67 /* 0x14 */ "Passthrough Left", 68 /* 0x15 */ "Passthrough Right", 69 /* 0x16 */ NULL, 70 /* 0x17 */ NULL, 71 /* 0x18 */ NULL, 72 /* 0x19 */ NULL, 73 /* 0x1a */ NULL, 74 /* 0x1b */ NULL, 75 /* 0x1c */ NULL, 76 /* 0x1d */ NULL, 77 /* 0x1e */ NULL, 78 /* 0x1f */ NULL 67 79 }; 68 80 69 static const char * const creative_ins[16] = { 81 // Physical inputs; corresponds with the public EXTIN_* defines. 82 const char * const snd_emu10k1_sblive_ins[16] = { 70 83 /* 0x00 */ "AC97 Left", 71 84 /* 0x01 */ "AC97 Right", … … 86 99 }; 87 100 88 static const char * const audigy_ins[16] = { 101 // Physical inputs; corresponds with the public A_EXTIN_* defines. 102 const char * const snd_emu10k1_audigy_ins[16] = { 89 103 /* 0x00 */ "AC97 Left", 90 104 /* 0x01 */ "AC97 Right", … … 105 119 }; 106 120 107 static const char * const creative_outs[32] = { 121 // Physical outputs; corresponds with the public EXTOUT_* defines. 122 const char * const snd_emu10k1_sblive_outs[32] = { 108 123 /* 0x00 */ "AC97 Left", 109 124 /* 0x01 */ "AC97 Right", … … 122 137 /* 0x0e */ "AC97 Surround Right", 123 138 /* 0x0f */ NULL, 139 // This is actually the FXBUS2 range; SB Live! 5.1 only. 124 140 /* 0x10 */ NULL, 125 141 /* 0x11 */ "Analog Center", … … 140 156 }; 141 157 142 static const char * const audigy_outs[32] = { 158 // Physical outputs; corresponds with the public A_EXTOUT_* defines. 159 const char * const snd_emu10k1_audigy_outs[32] = { 143 160 /* 0x00 */ "Digital Front Left", 144 161 /* 0x01 */ "Digital Front Right", … … 173 190 /* 0x1e */ NULL, 174 191 /* 0x1f */ NULL, 192 }; 193 194 // On the SB Live! 5.1, FXBUS2[1] and FXBUS2[2] are occupied by EXTOUT_ACENTER 195 // and EXTOUT_ALFE, so we can't connect inputs to them for multitrack recording. 196 // 197 // Since only 14 of the 16 EXTINs are used, this is not a big problem. 198 // We route AC97 to FX capture 14 and 15, SPDIF_CD to FX capture 0 and 3, 199 // and the rest of the EXTINs to the corresponding FX capture channel. 200 // Multitrack recorders will still see the center/LFE output signal 201 // on the second and third "input" channel. 202 const s8 snd_emu10k1_sblive51_fxbus2_map[16] = { 203 2, -1, -1, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 0, 1 175 204 }; 176 205 … … 320 349 static int snd_emu10k1_gpr_ctl_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 321 350 { 351 struct snd_emu10k1_fx8010_ctl *ctl = 352 (struct snd_emu10k1_fx8010_ctl *) kcontrol->private_value; 353 unsigned int i; 354 355 for (i = 0; i < ctl->vcount; i++) 356 ucontrol->value.integer.value[i] = ctl->value[i]; 357 return 0; 358 } 359 360 static int snd_emu10k1_gpr_ctl_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 361 { 322 362 struct snd_emu10k1 *emu = snd_kcontrol_chip(kcontrol); 323 363 struct snd_emu10k1_fx8010_ctl *ctl = 324 364 (struct snd_emu10k1_fx8010_ctl *) kcontrol->private_value; 325 unsigned long flags; 326 unsigned int i; 327 328 spin_lock_irqsave(&emu->reg_lock, flags); 329 for (i = 0; i < ctl->vcount; i++) 330 ucontrol->value.integer.value[i] = ctl->value[i]; 331 spin_unlock_irqrestore(&emu->reg_lock, flags); 332 return 0; 333 } 334 335 static int snd_emu10k1_gpr_ctl_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 336 { 337 struct snd_emu10k1 *emu = snd_kcontrol_chip(kcontrol); 338 struct snd_emu10k1_fx8010_ctl *ctl = 339 (struct snd_emu10k1_fx8010_ctl *) kcontrol->private_value; 340 unsigned long flags; 341 unsigned int nval, val; 365 int nval, val; 342 366 unsigned int i, j; 343 367 int change = 0; 344 368 345 spin_lock_irqsave(&emu->reg_lock, flags);346 369 for (i = 0; i < ctl->vcount; i++) { 347 370 nval = ucontrol->value.integer.value[i]; … … 357 380 snd_emu10k1_ptr_write(emu, emu->gpr_base + ctl->gpr[i], 0, val); 358 381 break; 382 case EMU10K1_GPR_TRANSLATION_NEGATE: 383 snd_emu10k1_ptr_write(emu, emu->gpr_base + ctl->gpr[i], 0, ~val); 384 break; 359 385 case EMU10K1_GPR_TRANSLATION_TABLE100: 360 386 snd_emu10k1_ptr_write(emu, emu->gpr_base + ctl->gpr[i], 0, db_table[val]); 387 break; 388 case EMU10K1_GPR_TRANSLATION_NEG_TABLE100: 389 snd_emu10k1_ptr_write(emu, emu->gpr_base + ctl->gpr[i], 0, 390 val == 100 ? 0x80000000 : -(int)db_table[val]); 361 391 break; 362 392 case EMU10K1_GPR_TRANSLATION_BASS: … … 382 412 } 383 413 __error: 384 spin_unlock_irqrestore(&emu->reg_lock, flags);385 414 return change; 386 415 } … … 643 672 kcontrol = ctl->kcontrol; 644 673 if (kcontrol->id.iface == id->iface && 645 !strcmp(kcontrol->id.name, id->name)&&646 kcontrol->id.index == id->index)674 kcontrol->id.index == id->index && 675 !strcmp(kcontrol->id.name, id->name)) 647 676 return ctl; 648 677 } … … 766 795 continue; 767 796 gctl_id = (struct snd_ctl_elem_id *)&gctl->id; 768 down_read(&emu->card->controls_rwsem);769 797 if (snd_ctl_find_id(emu->card, gctl_id)) { 770 up_read(&emu->card->controls_rwsem);771 798 err = -EEXIST; 772 799 goto __error; 773 800 } 774 up_read(&emu->card->controls_rwsem);775 801 if (gctl_id->iface != SNDRV_CTL_ELEM_IFACE_MIXER && 776 802 gctl_id->iface != SNDRV_CTL_ELEM_IFACE_PCM) { 803 err = -EINVAL; 804 goto __error; 805 } 806 switch (gctl->translation) { 807 case EMU10K1_GPR_TRANSLATION_NONE: 808 case EMU10K1_GPR_TRANSLATION_NEGATE: 809 break; 810 case EMU10K1_GPR_TRANSLATION_TABLE100: 811 case EMU10K1_GPR_TRANSLATION_NEG_TABLE100: 812 if (gctl->min != 0 || gctl->max != 100) { 813 err = -EINVAL; 814 goto __error; 815 } 816 break; 817 case EMU10K1_GPR_TRANSLATION_BASS: 818 case EMU10K1_GPR_TRANSLATION_TREBLE: 819 if (gctl->min != 0 || gctl->max != 40) { 820 err = -EINVAL; 821 goto __error; 822 } 823 break; 824 case EMU10K1_GPR_TRANSLATION_ONOFF: 825 if (gctl->min != 0 || gctl->max != 1) { 826 err = -EINVAL; 827 goto __error; 828 } 829 break; 830 default: 777 831 err = -EINVAL; 778 832 goto __error; … … 916 970 if (err < 0) 917 971 return err; 918 down_write(&card->controls_rwsem);919 972 ctl = snd_emu10k1_look_for_ctl(emu, &id); 920 973 if (ctl) 921 974 snd_ctl_remove(card, ctl->kcontrol); 922 up_write(&card->controls_rwsem);923 975 } 924 976 return 0; … … 1118 1170 #define SND_EMU10K1_CAPTURE_CHANNELS 4 1119 1171 1172 #define HR_VAL(v) ((v) * 0x80000000LL / 100 - 1) 1173 1120 1174 static void 1121 snd_emu10k1_init_mono_control (struct snd_emu10k1_fx8010_control_gpr *ctl,1122 const char *name, int gpr, int defval)1175 snd_emu10k1_init_mono_control2(struct snd_emu10k1_fx8010_control_gpr *ctl, 1176 const char *name, int gpr, int defval, int defval_hr) 1123 1177 { 1124 1178 ctl->id.iface = (__force int)SNDRV_CTL_ELEM_IFACE_MIXER; 1125 1179 strcpy(ctl->id.name, name); 1126 1180 ctl->vcount = ctl->count = 1; 1127 ctl->gpr[0] = gpr + 0; ctl->value[0] = defval;1128 1181 if (high_res_gpr_volume) { 1129 ctl->min = 0;1182 ctl->min = -1; 1130 1183 ctl->max = 0x7fffffff; 1131 1184 ctl->tlv = snd_emu10k1_db_linear; 1132 ctl->translation = EMU10K1_GPR_TRANSLATION_NONE; 1185 ctl->translation = EMU10K1_GPR_TRANSLATION_NEGATE; 1186 defval = defval_hr; 1133 1187 } else { 1134 1188 ctl->min = 0; 1135 1189 ctl->max = 100; 1136 1190 ctl->tlv = snd_emu10k1_db_scale1; 1137 ctl->translation = EMU10K1_GPR_TRANSLATION_TABLE100; 1138 } 1139 } 1191 ctl->translation = EMU10K1_GPR_TRANSLATION_NEG_TABLE100; 1192 } 1193 ctl->gpr[0] = gpr + 0; ctl->value[0] = defval; 1194 } 1195 #define snd_emu10k1_init_mono_control(ctl, name, gpr, defval) \ 1196 snd_emu10k1_init_mono_control2(ctl, name, gpr, defval, HR_VAL(defval)) 1140 1197 1141 1198 static void 1142 snd_emu10k1_init_stereo_control (struct snd_emu10k1_fx8010_control_gpr *ctl,1143 const char *name, int gpr, int defval)1199 snd_emu10k1_init_stereo_control2(struct snd_emu10k1_fx8010_control_gpr *ctl, 1200 const char *name, int gpr, int defval, int defval_hr) 1144 1201 { 1145 1202 ctl->id.iface = (__force int)SNDRV_CTL_ELEM_IFACE_MIXER; 1146 1203 strcpy(ctl->id.name, name); 1147 1204 ctl->vcount = ctl->count = 2; 1148 ctl->gpr[0] = gpr + 0; ctl->value[0] = defval;1149 ctl->gpr[1] = gpr + 1; ctl->value[1] = defval;1150 1205 if (high_res_gpr_volume) { 1151 ctl->min = 0;1206 ctl->min = -1; 1152 1207 ctl->max = 0x7fffffff; 1153 1208 ctl->tlv = snd_emu10k1_db_linear; 1154 ctl->translation = EMU10K1_GPR_TRANSLATION_NONE; 1209 ctl->translation = EMU10K1_GPR_TRANSLATION_NEGATE; 1210 defval = defval_hr; 1155 1211 } else { 1156 1212 ctl->min = 0; 1157 1213 ctl->max = 100; 1158 1214 ctl->tlv = snd_emu10k1_db_scale1; 1159 ctl->translation = EMU10K1_GPR_TRANSLATION_TABLE100; 1160 } 1161 } 1215 ctl->translation = EMU10K1_GPR_TRANSLATION_NEG_TABLE100; 1216 } 1217 ctl->gpr[0] = gpr + 0; ctl->value[0] = defval; 1218 ctl->gpr[1] = gpr + 1; ctl->value[1] = defval; 1219 } 1220 #define snd_emu10k1_init_stereo_control(ctl, name, gpr, defval) \ 1221 snd_emu10k1_init_stereo_control2(ctl, name, gpr, defval, HR_VAL(defval)) 1162 1222 1163 1223 static void … … 1189 1249 1190 1250 /* 1191 * Used for emu1010 - conversion from 32-bit capture inputs from HANA1192 * to 2 x 16-bit registers in audigy - their values are read via DMA.1251 * Used for emu1010 - conversion from 32-bit capture inputs from the FPGA 1252 * to 2 x 16-bit registers in Audigy - their values are read via DMA. 1193 1253 * Conversion is performed by Audigy DSP instructions of FX8010. 1194 1254 */ 1195 static intsnd_emu10k1_audigy_dsp_convert_32_to_2x16(1255 static void snd_emu10k1_audigy_dsp_convert_32_to_2x16( 1196 1256 struct snd_emu10k1_fx8010_code *icode, 1197 1257 u32 *ptr, int tmp, int bit_shifter16, 1198 1258 int reg_in, int reg_out) 1199 1259 { 1200 A_OP(icode, ptr, iACC3, A_GPR(tmp + 1), reg_in, A_C_00000000, A_C_00000000); 1201 A_OP(icode, ptr, iANDXOR, A_GPR(tmp), A_GPR(tmp + 1), A_GPR(bit_shifter16 - 1), A_C_00000000); 1202 A_OP(icode, ptr, iTSTNEG, A_GPR(tmp + 2), A_GPR(tmp), A_C_80000000, A_GPR(bit_shifter16 - 2)); 1203 A_OP(icode, ptr, iANDXOR, A_GPR(tmp + 2), A_GPR(tmp + 2), A_C_80000000, A_C_00000000); 1204 A_OP(icode, ptr, iANDXOR, A_GPR(tmp), A_GPR(tmp), A_GPR(bit_shifter16 - 3), A_C_00000000); 1205 A_OP(icode, ptr, iMACINT0, A_GPR(tmp), A_C_00000000, A_GPR(tmp), A_C_00010000); 1206 A_OP(icode, ptr, iANDXOR, reg_out, A_GPR(tmp), A_C_ffffffff, A_GPR(tmp + 2)); 1207 A_OP(icode, ptr, iACC3, reg_out + 1, A_GPR(tmp + 1), A_C_00000000, A_C_00000000); 1208 return 1; 1209 } 1260 // This leaves the low word in place, which is fine, 1261 // as the low bits are completely ignored subsequently. 1262 // reg_out[1] = reg_in 1263 A_OP(icode, ptr, iACC3, reg_out + 1, reg_in, A_C_00000000, A_C_00000000); 1264 // It is fine to read reg_in multiple times. 1265 // tmp = reg_in << 15 1266 A_OP(icode, ptr, iMACINT1, A_GPR(tmp), A_C_00000000, reg_in, A_GPR(bit_shifter16)); 1267 // Left-shift once more. This is a separate step, as the 1268 // signed multiplication would clobber the MSB. 1269 // reg_out[0] = tmp + ((tmp << 31) >> 31) 1270 A_OP(icode, ptr, iMAC3, reg_out, A_GPR(tmp), A_GPR(tmp), A_C_80000000); 1271 } 1272 1273 #define ENUM_GPR(name, size) name, name ## _dummy = name + (size) - 1 1210 1274 1211 1275 /* … … 1215 1279 static int _snd_emu10k1_audigy_init_efx(struct snd_emu10k1 *emu) 1216 1280 { 1217 int err, i, z, gpr, nctl; 1218 int bit_shifter16; 1219 const int playback = 10; 1220 const int capture = playback + (SND_EMU10K1_PLAYBACK_CHANNELS * 2); /* we reserve 10 voices */ 1221 const int stereo_mix = capture + 2; 1222 const int tmp = 0x88; 1223 u32 ptr; 1281 int err, z, nctl; 1282 enum { 1283 ENUM_GPR(playback, SND_EMU10K1_PLAYBACK_CHANNELS), 1284 ENUM_GPR(stereo_mix, 2), 1285 ENUM_GPR(capture, 2), 1286 ENUM_GPR(bit_shifter16, 1), 1287 // The fixed allocation of these breaks the pattern, but why not. 1288 // Splitting these into left/right is questionable, as it will break 1289 // down for center/lfe. But it works for stereo/quadro, so whatever. 1290 ENUM_GPR(bass_gpr, 2 * 5), // two sides, five coefficients 1291 ENUM_GPR(treble_gpr, 2 * 5), 1292 ENUM_GPR(bass_tmp, SND_EMU10K1_PLAYBACK_CHANNELS * 4), // four delay stages 1293 ENUM_GPR(treble_tmp, SND_EMU10K1_PLAYBACK_CHANNELS * 4), 1294 ENUM_GPR(tmp, 3), 1295 num_static_gprs 1296 }; 1297 int gpr = num_static_gprs; 1298 u32 ptr, ptr_skip; 1224 1299 struct snd_emu10k1_fx8010_code *icode = NULL; 1225 1300 struct snd_emu10k1_fx8010_control_gpr *controls = NULL, *ctl; … … 1247 1322 1248 1323 /* clear free GPRs */ 1249 for (i = 0; i < 512; i++) 1250 set_bit(i, icode->gpr_valid); 1324 memset(icode->gpr_valid, 0xff, 512 / 8); 1251 1325 1252 1326 /* clear TRAM data & address lines */ 1253 for (i = 0; i < 256; i++) 1254 set_bit(i, icode->tram_valid); 1327 memset(icode->tram_valid, 0xff, 256 / 8); 1255 1328 1256 1329 strcpy(icode->name, "Audigy DSP code for ALSA"); 1257 1330 ptr = 0; 1258 1331 nctl = 0; 1259 gpr = stereo_mix + 10; 1260 gpr_map[gpr++] = 0x00007fff; 1261 gpr_map[gpr++] = 0x00008000; 1262 gpr_map[gpr++] = 0x0000ffff; 1263 bit_shifter16 = gpr; 1264 1265 /* stop FX processor */ 1266 snd_emu10k1_ptr_write(emu, A_DBG, 0, (emu->fx8010.dbg = 0) | A_DBG_SINGLE_STEP); 1332 gpr_map[bit_shifter16] = 0x00008000; 1267 1333 1268 1334 #if 1 1269 1335 /* PCM front Playback Volume (independent from stereo mix) 1270 * playback = 0 + ( gpr * FXBUS_PCM_LEFT_FRONT >> 31)1271 * where gpr contains attenuation from corresponding mixer control1336 * playback = -gpr * FXBUS_PCM_LEFT_FRONT >> 31 1337 * where gpr contains negated attenuation from corresponding mixer control 1272 1338 * (snd_emu10k1_init_stereo_control) 1273 1339 */ 1274 A_OP(icode, &ptr, iMAC 0, A_GPR(playback), A_C_00000000, A_GPR(gpr), A_FXBUS(FXBUS_PCM_LEFT_FRONT));1275 A_OP(icode, &ptr, iMAC 0, A_GPR(playback+1), A_C_00000000, A_GPR(gpr+1), A_FXBUS(FXBUS_PCM_RIGHT_FRONT));1340 A_OP(icode, &ptr, iMAC1, A_GPR(playback), A_C_00000000, A_GPR(gpr), A_FXBUS(FXBUS_PCM_LEFT_FRONT)); 1341 A_OP(icode, &ptr, iMAC1, A_GPR(playback+1), A_C_00000000, A_GPR(gpr+1), A_FXBUS(FXBUS_PCM_RIGHT_FRONT)); 1276 1342 snd_emu10k1_init_stereo_control(&controls[nctl++], "PCM Front Playback Volume", gpr, 100); 1277 1343 gpr += 2; 1278 1344 1279 1345 /* PCM Surround Playback (independent from stereo mix) */ 1280 A_OP(icode, &ptr, iMAC 0, A_GPR(playback+2), A_C_00000000, A_GPR(gpr), A_FXBUS(FXBUS_PCM_LEFT_REAR));1281 A_OP(icode, &ptr, iMAC 0, A_GPR(playback+3), A_C_00000000, A_GPR(gpr+1), A_FXBUS(FXBUS_PCM_RIGHT_REAR));1346 A_OP(icode, &ptr, iMAC1, A_GPR(playback+2), A_C_00000000, A_GPR(gpr), A_FXBUS(FXBUS_PCM_LEFT_REAR)); 1347 A_OP(icode, &ptr, iMAC1, A_GPR(playback+3), A_C_00000000, A_GPR(gpr+1), A_FXBUS(FXBUS_PCM_RIGHT_REAR)); 1282 1348 snd_emu10k1_init_stereo_control(&controls[nctl++], "PCM Surround Playback Volume", gpr, 100); 1283 1349 gpr += 2; … … 1285 1351 /* PCM Side Playback (independent from stereo mix) */ 1286 1352 if (emu->card_capabilities->spk71) { 1287 A_OP(icode, &ptr, iMAC 0, A_GPR(playback+6), A_C_00000000, A_GPR(gpr), A_FXBUS(FXBUS_PCM_LEFT_SIDE));1288 A_OP(icode, &ptr, iMAC 0, A_GPR(playback+7), A_C_00000000, A_GPR(gpr+1), A_FXBUS(FXBUS_PCM_RIGHT_SIDE));1353 A_OP(icode, &ptr, iMAC1, A_GPR(playback+6), A_C_00000000, A_GPR(gpr), A_FXBUS(FXBUS_PCM_LEFT_SIDE)); 1354 A_OP(icode, &ptr, iMAC1, A_GPR(playback+7), A_C_00000000, A_GPR(gpr+1), A_FXBUS(FXBUS_PCM_RIGHT_SIDE)); 1289 1355 snd_emu10k1_init_stereo_control(&controls[nctl++], "PCM Side Playback Volume", gpr, 100); 1290 1356 gpr += 2; … … 1292 1358 1293 1359 /* PCM Center Playback (independent from stereo mix) */ 1294 A_OP(icode, &ptr, iMAC 0, A_GPR(playback+4), A_C_00000000, A_GPR(gpr), A_FXBUS(FXBUS_PCM_CENTER));1360 A_OP(icode, &ptr, iMAC1, A_GPR(playback+4), A_C_00000000, A_GPR(gpr), A_FXBUS(FXBUS_PCM_CENTER)); 1295 1361 snd_emu10k1_init_mono_control(&controls[nctl++], "PCM Center Playback Volume", gpr, 100); 1296 1362 gpr++; 1297 1363 1298 1364 /* PCM LFE Playback (independent from stereo mix) */ 1299 A_OP(icode, &ptr, iMAC 0, A_GPR(playback+5), A_C_00000000, A_GPR(gpr), A_FXBUS(FXBUS_PCM_LFE));1365 A_OP(icode, &ptr, iMAC1, A_GPR(playback+5), A_C_00000000, A_GPR(gpr), A_FXBUS(FXBUS_PCM_LFE)); 1300 1366 snd_emu10k1_init_mono_control(&controls[nctl++], "PCM LFE Playback Volume", gpr, 100); 1301 1367 gpr++; … … 1305 1371 */ 1306 1372 /* Wave (PCM) Playback Volume (will be renamed later) */ 1307 A_OP(icode, &ptr, iMAC 0, A_GPR(stereo_mix), A_C_00000000, A_GPR(gpr), A_FXBUS(FXBUS_PCM_LEFT));1308 A_OP(icode, &ptr, iMAC 0, A_GPR(stereo_mix+1), A_C_00000000, A_GPR(gpr+1), A_FXBUS(FXBUS_PCM_RIGHT));1373 A_OP(icode, &ptr, iMAC1, A_GPR(stereo_mix), A_C_00000000, A_GPR(gpr), A_FXBUS(FXBUS_PCM_LEFT)); 1374 A_OP(icode, &ptr, iMAC1, A_GPR(stereo_mix+1), A_C_00000000, A_GPR(gpr+1), A_FXBUS(FXBUS_PCM_RIGHT)); 1309 1375 snd_emu10k1_init_stereo_control(&controls[nctl++], "Wave Playback Volume", gpr, 100); 1310 1376 gpr += 2; 1311 1377 1312 1378 /* Synth Playback */ 1313 A_OP(icode, &ptr, iMAC 0, A_GPR(stereo_mix+0), A_GPR(stereo_mix+0), A_GPR(gpr), A_FXBUS(FXBUS_MIDI_LEFT));1314 A_OP(icode, &ptr, iMAC 0, A_GPR(stereo_mix+1), A_GPR(stereo_mix+1), A_GPR(gpr+1), A_FXBUS(FXBUS_MIDI_RIGHT));1379 A_OP(icode, &ptr, iMAC1, A_GPR(stereo_mix+0), A_GPR(stereo_mix+0), A_GPR(gpr), A_FXBUS(FXBUS_MIDI_LEFT)); 1380 A_OP(icode, &ptr, iMAC1, A_GPR(stereo_mix+1), A_GPR(stereo_mix+1), A_GPR(gpr+1), A_FXBUS(FXBUS_MIDI_RIGHT)); 1315 1381 snd_emu10k1_init_stereo_control(&controls[nctl++], "Synth Playback Volume", gpr, 100); 1316 1382 gpr += 2; 1317 1383 1318 1384 /* Wave (PCM) Capture */ 1319 A_OP(icode, &ptr, iMAC 0, A_GPR(capture+0), A_C_00000000, A_GPR(gpr), A_FXBUS(FXBUS_PCM_LEFT));1320 A_OP(icode, &ptr, iMAC 0, A_GPR(capture+1), A_C_00000000, A_GPR(gpr+1), A_FXBUS(FXBUS_PCM_RIGHT));1385 A_OP(icode, &ptr, iMAC1, A_GPR(capture+0), A_C_00000000, A_GPR(gpr), A_FXBUS(FXBUS_PCM_LEFT)); 1386 A_OP(icode, &ptr, iMAC1, A_GPR(capture+1), A_C_00000000, A_GPR(gpr+1), A_FXBUS(FXBUS_PCM_RIGHT)); 1321 1387 snd_emu10k1_init_stereo_control(&controls[nctl++], "PCM Capture Volume", gpr, 0); 1322 1388 gpr += 2; 1323 1389 1324 1390 /* Synth Capture */ 1325 A_OP(icode, &ptr, iMAC 0, A_GPR(capture+0), A_GPR(capture+0), A_GPR(gpr), A_FXBUS(FXBUS_MIDI_LEFT));1326 A_OP(icode, &ptr, iMAC 0, A_GPR(capture+1), A_GPR(capture+1), A_GPR(gpr+1), A_FXBUS(FXBUS_MIDI_RIGHT));1391 A_OP(icode, &ptr, iMAC1, A_GPR(capture+0), A_GPR(capture+0), A_GPR(gpr), A_FXBUS(FXBUS_MIDI_LEFT)); 1392 A_OP(icode, &ptr, iMAC1, A_GPR(capture+1), A_GPR(capture+1), A_GPR(gpr+1), A_FXBUS(FXBUS_MIDI_RIGHT)); 1327 1393 snd_emu10k1_init_stereo_control(&controls[nctl++], "Synth Capture Volume", gpr, 0); 1328 1394 gpr += 2; 1329 1395 1396 // We need to double the volume, as we configure the voices for half volume, 1397 // which is necessary for bit-identical reproduction. 1398 //{ static_assert(stereo_mix == playback + SND_EMU10K1_PLAYBACK_CHANNELS); } 1399 for (z = 0; z < SND_EMU10K1_PLAYBACK_CHANNELS + 2; z++) 1400 A_OP(icode, &ptr, iACC3, A_GPR(playback + z), A_GPR(playback + z), A_GPR(playback + z), A_C_00000000); 1401 1330 1402 /* 1331 1403 * inputs 1332 1404 */ 1333 1405 #define A_ADD_VOLUME_IN(var,vol,input) \ 1334 A_OP(icode, &ptr, iMAC0, A_GPR(var), A_GPR(var), A_GPR(vol), A_EXTIN(input)) 1335 1336 /* emu1212 DSP 0 and DSP 1 Capture */ 1406 A_OP(icode, &ptr, iMAC1, A_GPR(var), A_GPR(var), A_GPR(vol), A_EXTIN(input)) 1407 1337 1408 if (emu->card_capabilities->emu_model) { 1409 /* EMU1010 DSP 0 and DSP 1 Capture */ 1410 // The 24 MSB hold the actual value. We implicitly discard the 16 LSB. 1338 1411 if (emu->card_capabilities->ca0108_chip) { 1339 /* Note:JCD:No longer bit shift lower 16bits to upper 16bits of 32bit value. */ 1340 A_OP(icode, &ptr, iMACINT0, A_GPR(tmp), A_C_00000000, A3_EMU32IN(0x0), A_C_00000001); 1341 A_OP(icode, &ptr, iMAC0, A_GPR(capture+0), A_GPR(capture+0), A_GPR(gpr), A_GPR(tmp)); 1342 A_OP(icode, &ptr, iMACINT0, A_GPR(tmp), A_C_00000000, A3_EMU32IN(0x1), A_C_00000001); 1343 A_OP(icode, &ptr, iMAC0, A_GPR(capture+1), A_GPR(capture+1), A_GPR(gpr), A_GPR(tmp)); 1412 // For unclear reasons, the EMU32IN cannot be the Y operand! 1413 A_OP(icode, &ptr, iMAC1, A_GPR(capture+0), A_GPR(capture+0), A3_EMU32IN(0x0), A_GPR(gpr)); 1414 // A3_EMU32IN(0) is delayed by one sample, so all other A3_EMU32IN channels 1415 // need to be delayed as well; we use an auxiliary register for that. 1416 A_OP(icode, &ptr, iMAC1, A_GPR(capture+1), A_GPR(capture+1), A_GPR(gpr+2), A_GPR(gpr+1)); 1417 A_OP(icode, &ptr, iACC3, A_GPR(gpr+2), A3_EMU32IN(0x1), A_C_00000000, A_C_00000000); 1344 1418 } else { 1345 A_OP(icode, &ptr, iMAC0, A_GPR(capture+0), A_GPR(capture+0), A_GPR(gpr), A_P16VIN(0x0)); 1346 A_OP(icode, &ptr, iMAC0, A_GPR(capture+1), A_GPR(capture+1), A_GPR(gpr+1), A_P16VIN(0x1)); 1419 A_OP(icode, &ptr, iMAC1, A_GPR(capture+0), A_GPR(capture+0), A_P16VIN(0x0), A_GPR(gpr)); 1420 // A_P16VIN(0) is delayed by one sample, so all other A_P16VIN channels 1421 // need to be delayed as well; we use an auxiliary register for that. 1422 A_OP(icode, &ptr, iMAC1, A_GPR(capture+1), A_GPR(capture+1), A_GPR(gpr+2), A_GPR(gpr+1)); 1423 A_OP(icode, &ptr, iACC3, A_GPR(gpr+2), A_P16VIN(0x1), A_C_00000000, A_C_00000000); 1347 1424 } 1348 1425 snd_emu10k1_init_stereo_control(&controls[nctl++], "EMU Capture Volume", gpr, 0); 1426 gpr_map[gpr + 2] = 0x00000000; 1427 gpr += 3; 1428 } else { 1429 if (emu->card_capabilities->ac97_chip) { 1430 /* AC'97 Playback Volume - used only for mic (renamed later) */ 1431 A_ADD_VOLUME_IN(stereo_mix, gpr, A_EXTIN_AC97_L); 1432 A_ADD_VOLUME_IN(stereo_mix+1, gpr+1, A_EXTIN_AC97_R); 1433 snd_emu10k1_init_stereo_control(&controls[nctl++], "AMic Playback Volume", gpr, 0); 1434 gpr += 2; 1435 /* AC'97 Capture Volume - used only for mic */ 1436 A_ADD_VOLUME_IN(capture, gpr, A_EXTIN_AC97_L); 1437 A_ADD_VOLUME_IN(capture+1, gpr+1, A_EXTIN_AC97_R); 1438 snd_emu10k1_init_stereo_control(&controls[nctl++], "Mic Capture Volume", gpr, 0); 1439 gpr += 2; 1440 1441 /* mic capture buffer */ 1442 A_OP(icode, &ptr, iINTERP, A_EXTOUT(A_EXTOUT_MIC_CAP), A_EXTIN(A_EXTIN_AC97_L), A_C_40000000, A_EXTIN(A_EXTIN_AC97_R)); 1443 } 1444 1445 /* Audigy CD Playback Volume */ 1446 A_ADD_VOLUME_IN(stereo_mix, gpr, A_EXTIN_SPDIF_CD_L); 1447 A_ADD_VOLUME_IN(stereo_mix+1, gpr+1, A_EXTIN_SPDIF_CD_R); 1448 snd_emu10k1_init_stereo_control(&controls[nctl++], 1449 emu->card_capabilities->ac97_chip ? "Audigy CD Playback Volume" : "CD Playback Volume", 1450 gpr, 0); 1349 1451 gpr += 2; 1350 } 1351 /* AC'97 Playback Volume - used only for mic (renamed later) */ 1352 A_ADD_VOLUME_IN(stereo_mix, gpr, A_EXTIN_AC97_L); 1353 A_ADD_VOLUME_IN(stereo_mix+1, gpr+1, A_EXTIN_AC97_R); 1354 snd_emu10k1_init_stereo_control(&controls[nctl++], "AMic Playback Volume", gpr, 0); 1355 gpr += 2; 1356 /* AC'97 Capture Volume - used only for mic */ 1357 A_ADD_VOLUME_IN(capture, gpr, A_EXTIN_AC97_L); 1358 A_ADD_VOLUME_IN(capture+1, gpr+1, A_EXTIN_AC97_R); 1359 snd_emu10k1_init_stereo_control(&controls[nctl++], "Mic Capture Volume", gpr, 0); 1360 gpr += 2; 1361 1362 /* mic capture buffer */ 1363 A_OP(icode, &ptr, iINTERP, A_EXTOUT(A_EXTOUT_MIC_CAP), A_EXTIN(A_EXTIN_AC97_L), 0xcd, A_EXTIN(A_EXTIN_AC97_R)); 1364 1365 /* Audigy CD Playback Volume */ 1366 A_ADD_VOLUME_IN(stereo_mix, gpr, A_EXTIN_SPDIF_CD_L); 1367 A_ADD_VOLUME_IN(stereo_mix+1, gpr+1, A_EXTIN_SPDIF_CD_R); 1368 snd_emu10k1_init_stereo_control(&controls[nctl++], 1369 emu->card_capabilities->ac97_chip ? "Audigy CD Playback Volume" : "CD Playback Volume", 1370 gpr, 0); 1371 gpr += 2; 1372 /* Audigy CD Capture Volume */ 1373 A_ADD_VOLUME_IN(capture, gpr, A_EXTIN_SPDIF_CD_L); 1374 A_ADD_VOLUME_IN(capture+1, gpr+1, A_EXTIN_SPDIF_CD_R); 1375 snd_emu10k1_init_stereo_control(&controls[nctl++], 1376 emu->card_capabilities->ac97_chip ? "Audigy CD Capture Volume" : "CD Capture Volume", 1377 gpr, 0); 1378 gpr += 2; 1379 1380 /* Optical SPDIF Playback Volume */ 1381 A_ADD_VOLUME_IN(stereo_mix, gpr, A_EXTIN_OPT_SPDIF_L); 1382 A_ADD_VOLUME_IN(stereo_mix+1, gpr+1, A_EXTIN_OPT_SPDIF_R); 1383 snd_emu10k1_init_stereo_control(&controls[nctl++], SNDRV_CTL_NAME_IEC958("Optical ",PLAYBACK,VOLUME), gpr, 0); 1384 gpr += 2; 1385 /* Optical SPDIF Capture Volume */ 1386 A_ADD_VOLUME_IN(capture, gpr, A_EXTIN_OPT_SPDIF_L); 1387 A_ADD_VOLUME_IN(capture+1, gpr+1, A_EXTIN_OPT_SPDIF_R); 1388 snd_emu10k1_init_stereo_control(&controls[nctl++], SNDRV_CTL_NAME_IEC958("Optical ",CAPTURE,VOLUME), gpr, 0); 1389 gpr += 2; 1390 1391 /* Line2 Playback Volume */ 1392 A_ADD_VOLUME_IN(stereo_mix, gpr, A_EXTIN_LINE2_L); 1393 A_ADD_VOLUME_IN(stereo_mix+1, gpr+1, A_EXTIN_LINE2_R); 1394 snd_emu10k1_init_stereo_control(&controls[nctl++], 1395 emu->card_capabilities->ac97_chip ? "Line2 Playback Volume" : "Line Playback Volume", 1396 gpr, 0); 1397 gpr += 2; 1398 /* Line2 Capture Volume */ 1399 A_ADD_VOLUME_IN(capture, gpr, A_EXTIN_LINE2_L); 1400 A_ADD_VOLUME_IN(capture+1, gpr+1, A_EXTIN_LINE2_R); 1401 snd_emu10k1_init_stereo_control(&controls[nctl++], 1402 emu->card_capabilities->ac97_chip ? "Line2 Capture Volume" : "Line Capture Volume", 1403 gpr, 0); 1404 gpr += 2; 1405 1406 /* Philips ADC Playback Volume */ 1407 A_ADD_VOLUME_IN(stereo_mix, gpr, A_EXTIN_ADC_L); 1408 A_ADD_VOLUME_IN(stereo_mix+1, gpr+1, A_EXTIN_ADC_R); 1409 snd_emu10k1_init_stereo_control(&controls[nctl++], "Analog Mix Playback Volume", gpr, 0); 1410 gpr += 2; 1411 /* Philips ADC Capture Volume */ 1412 A_ADD_VOLUME_IN(capture, gpr, A_EXTIN_ADC_L); 1413 A_ADD_VOLUME_IN(capture+1, gpr+1, A_EXTIN_ADC_R); 1414 snd_emu10k1_init_stereo_control(&controls[nctl++], "Analog Mix Capture Volume", gpr, 0); 1415 gpr += 2; 1416 1417 /* Aux2 Playback Volume */ 1418 A_ADD_VOLUME_IN(stereo_mix, gpr, A_EXTIN_AUX2_L); 1419 A_ADD_VOLUME_IN(stereo_mix+1, gpr+1, A_EXTIN_AUX2_R); 1420 snd_emu10k1_init_stereo_control(&controls[nctl++], 1421 emu->card_capabilities->ac97_chip ? "Aux2 Playback Volume" : "Aux Playback Volume", 1422 gpr, 0); 1423 gpr += 2; 1424 /* Aux2 Capture Volume */ 1425 A_ADD_VOLUME_IN(capture, gpr, A_EXTIN_AUX2_L); 1426 A_ADD_VOLUME_IN(capture+1, gpr+1, A_EXTIN_AUX2_R); 1427 snd_emu10k1_init_stereo_control(&controls[nctl++], 1428 emu->card_capabilities->ac97_chip ? "Aux2 Capture Volume" : "Aux Capture Volume", 1429 gpr, 0); 1430 gpr += 2; 1452 /* Audigy CD Capture Volume */ 1453 A_ADD_VOLUME_IN(capture, gpr, A_EXTIN_SPDIF_CD_L); 1454 A_ADD_VOLUME_IN(capture+1, gpr+1, A_EXTIN_SPDIF_CD_R); 1455 snd_emu10k1_init_stereo_control(&controls[nctl++], 1456 emu->card_capabilities->ac97_chip ? "Audigy CD Capture Volume" : "CD Capture Volume", 1457 gpr, 0); 1458 gpr += 2; 1459 1460 /* Optical SPDIF Playback Volume */ 1461 A_ADD_VOLUME_IN(stereo_mix, gpr, A_EXTIN_OPT_SPDIF_L); 1462 A_ADD_VOLUME_IN(stereo_mix+1, gpr+1, A_EXTIN_OPT_SPDIF_R); 1463 snd_emu10k1_init_stereo_control(&controls[nctl++], SNDRV_CTL_NAME_IEC958("Optical ",PLAYBACK,VOLUME), gpr, 0); 1464 gpr += 2; 1465 /* Optical SPDIF Capture Volume */ 1466 A_ADD_VOLUME_IN(capture, gpr, A_EXTIN_OPT_SPDIF_L); 1467 A_ADD_VOLUME_IN(capture+1, gpr+1, A_EXTIN_OPT_SPDIF_R); 1468 snd_emu10k1_init_stereo_control(&controls[nctl++], SNDRV_CTL_NAME_IEC958("Optical ",CAPTURE,VOLUME), gpr, 0); 1469 gpr += 2; 1470 1471 /* Line2 Playback Volume */ 1472 A_ADD_VOLUME_IN(stereo_mix, gpr, A_EXTIN_LINE2_L); 1473 A_ADD_VOLUME_IN(stereo_mix+1, gpr+1, A_EXTIN_LINE2_R); 1474 snd_emu10k1_init_stereo_control(&controls[nctl++], 1475 emu->card_capabilities->ac97_chip ? "Line2 Playback Volume" : "Line Playback Volume", 1476 gpr, 0); 1477 gpr += 2; 1478 /* Line2 Capture Volume */ 1479 A_ADD_VOLUME_IN(capture, gpr, A_EXTIN_LINE2_L); 1480 A_ADD_VOLUME_IN(capture+1, gpr+1, A_EXTIN_LINE2_R); 1481 snd_emu10k1_init_stereo_control(&controls[nctl++], 1482 emu->card_capabilities->ac97_chip ? "Line2 Capture Volume" : "Line Capture Volume", 1483 gpr, 0); 1484 gpr += 2; 1485 1486 /* Philips ADC Playback Volume */ 1487 A_ADD_VOLUME_IN(stereo_mix, gpr, A_EXTIN_ADC_L); 1488 A_ADD_VOLUME_IN(stereo_mix+1, gpr+1, A_EXTIN_ADC_R); 1489 snd_emu10k1_init_stereo_control(&controls[nctl++], "Analog Mix Playback Volume", gpr, 0); 1490 gpr += 2; 1491 /* Philips ADC Capture Volume */ 1492 A_ADD_VOLUME_IN(capture, gpr, A_EXTIN_ADC_L); 1493 A_ADD_VOLUME_IN(capture+1, gpr+1, A_EXTIN_ADC_R); 1494 snd_emu10k1_init_stereo_control(&controls[nctl++], "Analog Mix Capture Volume", gpr, 0); 1495 gpr += 2; 1496 1497 /* Aux2 Playback Volume */ 1498 A_ADD_VOLUME_IN(stereo_mix, gpr, A_EXTIN_AUX2_L); 1499 A_ADD_VOLUME_IN(stereo_mix+1, gpr+1, A_EXTIN_AUX2_R); 1500 snd_emu10k1_init_stereo_control(&controls[nctl++], 1501 emu->card_capabilities->ac97_chip ? "Aux2 Playback Volume" : "Aux Playback Volume", 1502 gpr, 0); 1503 gpr += 2; 1504 /* Aux2 Capture Volume */ 1505 A_ADD_VOLUME_IN(capture, gpr, A_EXTIN_AUX2_L); 1506 A_ADD_VOLUME_IN(capture+1, gpr+1, A_EXTIN_AUX2_R); 1507 snd_emu10k1_init_stereo_control(&controls[nctl++], 1508 emu->card_capabilities->ac97_chip ? "Aux2 Capture Volume" : "Aux Capture Volume", 1509 gpr, 0); 1510 gpr += 2; 1511 } 1431 1512 1432 1513 /* Stereo Mix Front Playback Volume */ 1433 A_OP(icode, &ptr, iMAC 0, A_GPR(playback), A_GPR(playback), A_GPR(gpr), A_GPR(stereo_mix));1434 A_OP(icode, &ptr, iMAC 0, A_GPR(playback+1), A_GPR(playback+1), A_GPR(gpr+1), A_GPR(stereo_mix+1));1514 A_OP(icode, &ptr, iMAC1, A_GPR(playback), A_GPR(playback), A_GPR(gpr), A_GPR(stereo_mix)); 1515 A_OP(icode, &ptr, iMAC1, A_GPR(playback+1), A_GPR(playback+1), A_GPR(gpr+1), A_GPR(stereo_mix+1)); 1435 1516 snd_emu10k1_init_stereo_control(&controls[nctl++], "Front Playback Volume", gpr, 100); 1436 1517 gpr += 2; 1437 1518 1438 1519 /* Stereo Mix Surround Playback */ 1439 A_OP(icode, &ptr, iMAC 0, A_GPR(playback+2), A_GPR(playback+2), A_GPR(gpr), A_GPR(stereo_mix));1440 A_OP(icode, &ptr, iMAC 0, A_GPR(playback+3), A_GPR(playback+3), A_GPR(gpr+1), A_GPR(stereo_mix+1));1520 A_OP(icode, &ptr, iMAC1, A_GPR(playback+2), A_GPR(playback+2), A_GPR(gpr), A_GPR(stereo_mix)); 1521 A_OP(icode, &ptr, iMAC1, A_GPR(playback+3), A_GPR(playback+3), A_GPR(gpr+1), A_GPR(stereo_mix+1)); 1441 1522 snd_emu10k1_init_stereo_control(&controls[nctl++], "Surround Playback Volume", gpr, 0); 1442 1523 gpr += 2; … … 1444 1525 /* Stereo Mix Center Playback */ 1445 1526 /* Center = sub = Left/2 + Right/2 */ 1446 A_OP(icode, &ptr, iINTERP, A_GPR(tmp), A_GPR(stereo_mix), 0xcd, A_GPR(stereo_mix+1));1447 A_OP(icode, &ptr, iMAC 0, A_GPR(playback+4), A_GPR(playback+4), A_GPR(gpr), A_GPR(tmp));1527 A_OP(icode, &ptr, iINTERP, A_GPR(tmp), A_GPR(stereo_mix), A_C_40000000, A_GPR(stereo_mix+1)); 1528 A_OP(icode, &ptr, iMAC1, A_GPR(playback+4), A_GPR(playback+4), A_GPR(gpr), A_GPR(tmp)); 1448 1529 snd_emu10k1_init_mono_control(&controls[nctl++], "Center Playback Volume", gpr, 0); 1449 1530 gpr++; 1450 1531 1451 1532 /* Stereo Mix LFE Playback */ 1452 A_OP(icode, &ptr, iMAC 0, A_GPR(playback+5), A_GPR(playback+5), A_GPR(gpr), A_GPR(tmp));1533 A_OP(icode, &ptr, iMAC1, A_GPR(playback+5), A_GPR(playback+5), A_GPR(gpr), A_GPR(tmp)); 1453 1534 snd_emu10k1_init_mono_control(&controls[nctl++], "LFE Playback Volume", gpr, 0); 1454 1535 gpr++; … … 1456 1537 if (emu->card_capabilities->spk71) { 1457 1538 /* Stereo Mix Side Playback */ 1458 A_OP(icode, &ptr, iMAC 0, A_GPR(playback+6), A_GPR(playback+6), A_GPR(gpr), A_GPR(stereo_mix));1459 A_OP(icode, &ptr, iMAC 0, A_GPR(playback+7), A_GPR(playback+7), A_GPR(gpr+1), A_GPR(stereo_mix+1));1539 A_OP(icode, &ptr, iMAC1, A_GPR(playback+6), A_GPR(playback+6), A_GPR(gpr), A_GPR(stereo_mix)); 1540 A_OP(icode, &ptr, iMAC1, A_GPR(playback+7), A_GPR(playback+7), A_GPR(gpr+1), A_GPR(stereo_mix+1)); 1460 1541 snd_emu10k1_init_stereo_control(&controls[nctl++], "Side Playback Volume", gpr, 0); 1461 1542 gpr += 2; … … 1482 1563 * Process tone control 1483 1564 */ 1484 A_OP(icode, &ptr, iACC3, A_GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 0), A_GPR(playback + 0), A_C_00000000, A_C_00000000); /* left */1485 A_OP(icode, &ptr, iACC3, A_GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 1), A_GPR(playback + 1), A_C_00000000, A_C_00000000); /* right */1486 A_OP(icode, &ptr, iACC3, A_GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 2), A_GPR(playback + 2), A_C_00000000, A_C_00000000); /* rear left */1487 A_OP(icode, &ptr, iACC3, A_GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 3), A_GPR(playback + 3), A_C_00000000, A_C_00000000); /* rear right */1488 A_OP(icode, &ptr, iACC3, A_GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 4), A_GPR(playback + 4), A_C_00000000, A_C_00000000); /* center */1489 A_OP(icode, &ptr, iACC3, A_GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 5), A_GPR(playback + 5), A_C_00000000, A_C_00000000); /* LFE */1490 if (emu->card_capabilities->spk71) {1491 A_OP(icode, &ptr, iACC3, A_GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 6), A_GPR(playback + 6), A_C_00000000, A_C_00000000); /* side left */1492 A_OP(icode, &ptr, iACC3, A_GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 7), A_GPR(playback + 7), A_C_00000000, A_C_00000000); /* side right */1493 }1494 1495 1496 1565 ctl = &controls[nctl + 0]; 1497 1566 ctl->id.iface = (__force int)SNDRV_CTL_ELEM_IFACE_MIXER; … … 1512 1581 ctl->value[0] = ctl->value[1] = 20; 1513 1582 ctl->translation = EMU10K1_GPR_TRANSLATION_TREBLE; 1514 1515 #define BASS_GPR 0x8c1516 #define TREBLE_GPR 0x961517 1518 1583 for (z = 0; z < 5; z++) { 1519 1584 int j; 1520 1585 for (j = 0; j < 2; j++) { 1521 controls[nctl + 0].gpr[z * 2 + j] = BASS_GPR + z * 2 + j; 1522 controls[nctl + 1].gpr[z * 2 + j] = TREBLE_GPR + z * 2 + j; 1523 } 1524 } 1586 controls[nctl + 0].gpr[z * 2 + j] = bass_gpr + z * 2 + j; 1587 controls[nctl + 1].gpr[z * 2 + j] = treble_gpr + z * 2 + j; 1588 } 1589 } 1590 nctl += 2; 1591 1592 A_OP(icode, &ptr, iACC3, A_C_00000000, A_GPR(gpr), A_C_00000000, A_C_00000000); 1593 snd_emu10k1_init_mono_onoff_control(controls + nctl++, "Tone Control - Switch", gpr, 0); 1594 gpr++; 1595 A_OP(icode, &ptr, iSKIP, A_GPR_COND, A_GPR_COND, A_CC_REG_ZERO, A_GPR(gpr)); 1596 ptr_skip = ptr; 1525 1597 for (z = 0; z < 4; z++) { /* front/rear/center-lfe/side */ 1526 1598 int j, k, l, d; 1527 1599 for (j = 0; j < 2; j++) { /* left/right */ 1528 k = 0xb0+ (z * 8) + (j * 4);1529 l = 0xe0+ (z * 8) + (j * 4);1530 d = playback + SND_EMU10K1_PLAYBACK_CHANNELS +z * 2 + j;1531 1532 A_OP(icode, &ptr, iMAC0, A_C_00000000, A_C_00000000, A_GPR(d), A_GPR( BASS_GPR+ 0 + j));1533 A_OP(icode, &ptr, iMACMV, A_GPR(k+1), A_GPR(k), A_GPR(k+1), A_GPR( BASS_GPR+ 4 + j));1534 A_OP(icode, &ptr, iMACMV, A_GPR(k), A_GPR(d), A_GPR(k), A_GPR( BASS_GPR+ 2 + j));1535 A_OP(icode, &ptr, iMACMV, A_GPR(k+3), A_GPR(k+2), A_GPR(k+3), A_GPR( BASS_GPR+ 8 + j));1536 A_OP(icode, &ptr, iMAC0, A_GPR(k+2), A_GPR_ACCU, A_GPR(k+2), A_GPR( BASS_GPR+ 6 + j));1600 k = bass_tmp + (z * 8) + (j * 4); 1601 l = treble_tmp + (z * 8) + (j * 4); 1602 d = playback + z * 2 + j; 1603 1604 A_OP(icode, &ptr, iMAC0, A_C_00000000, A_C_00000000, A_GPR(d), A_GPR(bass_gpr + 0 + j)); 1605 A_OP(icode, &ptr, iMACMV, A_GPR(k+1), A_GPR(k), A_GPR(k+1), A_GPR(bass_gpr + 4 + j)); 1606 A_OP(icode, &ptr, iMACMV, A_GPR(k), A_GPR(d), A_GPR(k), A_GPR(bass_gpr + 2 + j)); 1607 A_OP(icode, &ptr, iMACMV, A_GPR(k+3), A_GPR(k+2), A_GPR(k+3), A_GPR(bass_gpr + 8 + j)); 1608 A_OP(icode, &ptr, iMAC0, A_GPR(k+2), A_GPR_ACCU, A_GPR(k+2), A_GPR(bass_gpr + 6 + j)); 1537 1609 A_OP(icode, &ptr, iACC3, A_GPR(k+2), A_GPR(k+2), A_GPR(k+2), A_C_00000000); 1538 1610 1539 A_OP(icode, &ptr, iMAC0, A_C_00000000, A_C_00000000, A_GPR(k+2), A_GPR( TREBLE_GPR+ 0 + j));1540 A_OP(icode, &ptr, iMACMV, A_GPR(l+1), A_GPR(l), A_GPR(l+1), A_GPR( TREBLE_GPR+ 4 + j));1541 A_OP(icode, &ptr, iMACMV, A_GPR(l), A_GPR(k+2), A_GPR(l), A_GPR( TREBLE_GPR+ 2 + j));1542 A_OP(icode, &ptr, iMACMV, A_GPR(l+3), A_GPR(l+2), A_GPR(l+3), A_GPR( TREBLE_GPR+ 8 + j));1543 A_OP(icode, &ptr, iMAC0, A_GPR(l+2), A_GPR_ACCU, A_GPR(l+2), A_GPR( TREBLE_GPR+ 6 + j));1611 A_OP(icode, &ptr, iMAC0, A_C_00000000, A_C_00000000, A_GPR(k+2), A_GPR(treble_gpr + 0 + j)); 1612 A_OP(icode, &ptr, iMACMV, A_GPR(l+1), A_GPR(l), A_GPR(l+1), A_GPR(treble_gpr + 4 + j)); 1613 A_OP(icode, &ptr, iMACMV, A_GPR(l), A_GPR(k+2), A_GPR(l), A_GPR(treble_gpr + 2 + j)); 1614 A_OP(icode, &ptr, iMACMV, A_GPR(l+3), A_GPR(l+2), A_GPR(l+3), A_GPR(treble_gpr + 8 + j)); 1615 A_OP(icode, &ptr, iMAC0, A_GPR(l+2), A_GPR_ACCU, A_GPR(l+2), A_GPR(treble_gpr + 6 + j)); 1544 1616 A_OP(icode, &ptr, iMACINT0, A_GPR(l+2), A_C_00000000, A_GPR(l+2), A_C_00000010); 1545 1617 … … 1550 1622 } 1551 1623 } 1552 nctl += 2; 1553 1554 #undef BASS_GPR 1555 #undef TREBLE_GPR 1556 1557 for (z = 0; z < 8; z++) { 1558 A_SWITCH(icode, &ptr, tmp + 0, playback + SND_EMU10K1_PLAYBACK_CHANNELS + z, gpr + 0); 1559 A_SWITCH_NEG(icode, &ptr, tmp + 1, gpr + 0); 1560 A_SWITCH(icode, &ptr, tmp + 1, playback + z, tmp + 1); 1561 A_OP(icode, &ptr, iACC3, A_GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + z), A_GPR(tmp + 0), A_GPR(tmp + 1), A_C_00000000); 1562 } 1563 snd_emu10k1_init_stereo_onoff_control(controls + nctl++, "Tone Control - Switch", gpr, 0); 1564 gpr += 2; 1624 gpr_map[gpr++] = ptr - ptr_skip; 1565 1625 1566 1626 /* Master volume (will be renamed later) */ 1567 A_OP(icode, &ptr, iMAC0, A_GPR(playback+0+SND_EMU10K1_PLAYBACK_CHANNELS), A_C_00000000, A_GPR(gpr), A_GPR(playback+0+SND_EMU10K1_PLAYBACK_CHANNELS)); 1568 A_OP(icode, &ptr, iMAC0, A_GPR(playback+1+SND_EMU10K1_PLAYBACK_CHANNELS), A_C_00000000, A_GPR(gpr), A_GPR(playback+1+SND_EMU10K1_PLAYBACK_CHANNELS)); 1569 A_OP(icode, &ptr, iMAC0, A_GPR(playback+2+SND_EMU10K1_PLAYBACK_CHANNELS), A_C_00000000, A_GPR(gpr), A_GPR(playback+2+SND_EMU10K1_PLAYBACK_CHANNELS)); 1570 A_OP(icode, &ptr, iMAC0, A_GPR(playback+3+SND_EMU10K1_PLAYBACK_CHANNELS), A_C_00000000, A_GPR(gpr), A_GPR(playback+3+SND_EMU10K1_PLAYBACK_CHANNELS)); 1571 A_OP(icode, &ptr, iMAC0, A_GPR(playback+4+SND_EMU10K1_PLAYBACK_CHANNELS), A_C_00000000, A_GPR(gpr), A_GPR(playback+4+SND_EMU10K1_PLAYBACK_CHANNELS)); 1572 A_OP(icode, &ptr, iMAC0, A_GPR(playback+5+SND_EMU10K1_PLAYBACK_CHANNELS), A_C_00000000, A_GPR(gpr), A_GPR(playback+5+SND_EMU10K1_PLAYBACK_CHANNELS)); 1573 A_OP(icode, &ptr, iMAC0, A_GPR(playback+6+SND_EMU10K1_PLAYBACK_CHANNELS), A_C_00000000, A_GPR(gpr), A_GPR(playback+6+SND_EMU10K1_PLAYBACK_CHANNELS)); 1574 A_OP(icode, &ptr, iMAC0, A_GPR(playback+7+SND_EMU10K1_PLAYBACK_CHANNELS), A_C_00000000, A_GPR(gpr), A_GPR(playback+7+SND_EMU10K1_PLAYBACK_CHANNELS)); 1627 for (z = 0; z < 8; z++) 1628 A_OP(icode, &ptr, iMAC1, A_GPR(playback+z), A_C_00000000, A_GPR(gpr), A_GPR(playback+z)); 1575 1629 snd_emu10k1_init_mono_control(&controls[nctl++], "Wave Master Playback Volume", gpr, 0); 1576 gpr += 2; 1577 1578 /* analog speakers */ 1579 A_PUT_STEREO_OUTPUT(A_EXTOUT_AFRONT_L, A_EXTOUT_AFRONT_R, playback + SND_EMU10K1_PLAYBACK_CHANNELS); 1580 A_PUT_STEREO_OUTPUT(A_EXTOUT_AREAR_L, A_EXTOUT_AREAR_R, playback+2 + SND_EMU10K1_PLAYBACK_CHANNELS); 1581 A_PUT_OUTPUT(A_EXTOUT_ACENTER, playback+4 + SND_EMU10K1_PLAYBACK_CHANNELS); 1582 A_PUT_OUTPUT(A_EXTOUT_ALFE, playback+5 + SND_EMU10K1_PLAYBACK_CHANNELS); 1583 if (emu->card_capabilities->spk71) 1584 A_PUT_STEREO_OUTPUT(A_EXTOUT_ASIDE_L, A_EXTOUT_ASIDE_R, playback+6 + SND_EMU10K1_PLAYBACK_CHANNELS); 1585 1586 /* headphone */ 1587 A_PUT_STEREO_OUTPUT(A_EXTOUT_HEADPHONE_L, A_EXTOUT_HEADPHONE_R, playback + SND_EMU10K1_PLAYBACK_CHANNELS); 1588 1589 /* digital outputs */ 1590 /* A_PUT_STEREO_OUTPUT(A_EXTOUT_FRONT_L, A_EXTOUT_FRONT_R, playback + SND_EMU10K1_PLAYBACK_CHANNELS); */ 1630 gpr++; 1631 1591 1632 if (emu->card_capabilities->emu_model) { 1592 1633 /* EMU1010 Outputs from PCM Front, Rear, Center, LFE, Side */ … … 1594 1635 for (z = 0; z < 8; z++) { 1595 1636 if (emu->card_capabilities->ca0108_chip) { 1596 A_OP(icode, &ptr, iACC3, A3_EMU32OUT(z), A_GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS +z), A_C_00000000, A_C_00000000);1637 A_OP(icode, &ptr, iACC3, A3_EMU32OUT(z), A_GPR(playback + z), A_C_00000000, A_C_00000000); 1597 1638 } else { 1598 A_OP(icode, &ptr, iACC3, A_EMU32OUTL(z), A_GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS +z), A_C_00000000, A_C_00000000);1639 A_OP(icode, &ptr, iACC3, A_EMU32OUTL(z), A_GPR(playback + z), A_C_00000000, A_C_00000000); 1599 1640 } 1600 1641 } 1601 } 1602 1603 /* IEC958 Optical Raw Playback Switch */ 1604 gpr_map[gpr++] = 0; 1605 gpr_map[gpr++] = 0x1008; 1606 gpr_map[gpr++] = 0xffff0000; 1607 for (z = 0; z < 2; z++) { 1608 A_OP(icode, &ptr, iMAC0, A_GPR(tmp + 2), A_FXBUS(FXBUS_PT_LEFT + z), A_C_00000000, A_C_00000000); 1609 A_OP(icode, &ptr, iSKIP, A_GPR_COND, A_GPR_COND, A_GPR(gpr - 2), A_C_00000001); 1610 A_OP(icode, &ptr, iACC3, A_GPR(tmp + 2), A_C_00000000, A_C_00010000, A_GPR(tmp + 2)); 1611 A_OP(icode, &ptr, iANDXOR, A_GPR(tmp + 2), A_GPR(tmp + 2), A_GPR(gpr - 1), A_C_00000000); 1612 A_SWITCH(icode, &ptr, tmp + 0, tmp + 2, gpr + z); 1613 A_SWITCH_NEG(icode, &ptr, tmp + 1, gpr + z); 1614 A_SWITCH(icode, &ptr, tmp + 1, playback + SND_EMU10K1_PLAYBACK_CHANNELS + z, tmp + 1); 1615 if ((z==1) && (emu->card_capabilities->spdif_bug)) { 1616 /* Due to a SPDIF output bug on some Audigy cards, this code delays the Right channel by 1 sample */ 1617 dev_info(emu->card->dev, 1618 "Installing spdif_bug patch: %s\n", 1619 emu->card_capabilities->name); 1620 A_OP(icode, &ptr, iACC3, A_EXTOUT(A_EXTOUT_FRONT_L + z), A_GPR(gpr - 3), A_C_00000000, A_C_00000000); 1621 A_OP(icode, &ptr, iACC3, A_GPR(gpr - 3), A_GPR(tmp + 0), A_GPR(tmp + 1), A_C_00000000); 1622 } else { 1623 A_OP(icode, &ptr, iACC3, A_EXTOUT(A_EXTOUT_FRONT_L + z), A_GPR(tmp + 0), A_GPR(tmp + 1), A_C_00000000); 1624 } 1625 } 1626 snd_emu10k1_init_stereo_onoff_control(controls + nctl++, SNDRV_CTL_NAME_IEC958("Optical Raw ",PLAYBACK,SWITCH), gpr, 0); 1627 gpr += 2; 1628 1629 A_PUT_STEREO_OUTPUT(A_EXTOUT_REAR_L, A_EXTOUT_REAR_R, playback+2 + SND_EMU10K1_PLAYBACK_CHANNELS); 1630 A_PUT_OUTPUT(A_EXTOUT_CENTER, playback+4 + SND_EMU10K1_PLAYBACK_CHANNELS); 1631 A_PUT_OUTPUT(A_EXTOUT_LFE, playback+5 + SND_EMU10K1_PLAYBACK_CHANNELS); 1642 } else { 1643 /* analog speakers */ 1644 A_PUT_STEREO_OUTPUT(A_EXTOUT_AFRONT_L, A_EXTOUT_AFRONT_R, playback); 1645 A_PUT_STEREO_OUTPUT(A_EXTOUT_AREAR_L, A_EXTOUT_AREAR_R, playback+2); 1646 A_PUT_OUTPUT(A_EXTOUT_ACENTER, playback+4); 1647 A_PUT_OUTPUT(A_EXTOUT_ALFE, playback+5); 1648 if (emu->card_capabilities->spk71) 1649 A_PUT_STEREO_OUTPUT(A_EXTOUT_ASIDE_L, A_EXTOUT_ASIDE_R, playback+6); 1650 1651 /* headphone */ 1652 A_PUT_STEREO_OUTPUT(A_EXTOUT_HEADPHONE_L, A_EXTOUT_HEADPHONE_R, playback); 1653 1654 /* IEC958 Optical Raw Playback Switch */ 1655 gpr_map[gpr++] = 0; 1656 gpr_map[gpr++] = 0x1008; 1657 gpr_map[gpr++] = 0xffff0000; 1658 for (z = 0; z < 2; z++) { 1659 A_OP(icode, &ptr, iMAC0, A_GPR(tmp + 2), A_FXBUS(FXBUS_PT_LEFT + z), A_C_00000000, A_C_00000000); 1660 A_OP(icode, &ptr, iSKIP, A_GPR_COND, A_GPR_COND, A_GPR(gpr - 2), A_C_00000001); 1661 A_OP(icode, &ptr, iACC3, A_GPR(tmp + 2), A_C_00000000, A_C_00010000, A_GPR(tmp + 2)); 1662 A_OP(icode, &ptr, iANDXOR, A_GPR(tmp + 2), A_GPR(tmp + 2), A_GPR(gpr - 1), A_C_00000000); 1663 A_SWITCH(icode, &ptr, tmp + 0, tmp + 2, gpr + z); 1664 A_SWITCH_NEG(icode, &ptr, tmp + 1, gpr + z); 1665 A_SWITCH(icode, &ptr, tmp + 1, playback + z, tmp + 1); 1666 if ((z==1) && (emu->card_capabilities->spdif_bug)) { 1667 /* Due to a SPDIF output bug on some Audigy cards, this code delays the Right channel by 1 sample */ 1668 dev_info(emu->card->dev, 1669 "Installing spdif_bug patch: %s\n", 1670 emu->card_capabilities->name); 1671 A_OP(icode, &ptr, iACC3, A_EXTOUT(A_EXTOUT_FRONT_L + z), A_GPR(gpr - 3), A_C_00000000, A_C_00000000); 1672 A_OP(icode, &ptr, iACC3, A_GPR(gpr - 3), A_GPR(tmp + 0), A_GPR(tmp + 1), A_C_00000000); 1673 } else { 1674 A_OP(icode, &ptr, iACC3, A_EXTOUT(A_EXTOUT_FRONT_L + z), A_GPR(tmp + 0), A_GPR(tmp + 1), A_C_00000000); 1675 } 1676 } 1677 snd_emu10k1_init_stereo_onoff_control(controls + nctl++, SNDRV_CTL_NAME_IEC958("Optical Raw ",PLAYBACK,SWITCH), gpr, 0); 1678 gpr += 2; 1679 1680 A_PUT_STEREO_OUTPUT(A_EXTOUT_REAR_L, A_EXTOUT_REAR_R, playback+2); 1681 A_PUT_OUTPUT(A_EXTOUT_CENTER, playback+4); 1682 A_PUT_OUTPUT(A_EXTOUT_LFE, playback+5); 1683 } 1632 1684 1633 1685 /* ADC buffer */ 1634 1686 #ifdef EMU10K1_CAPTURE_DIGITAL_OUT 1635 A_PUT_STEREO_OUTPUT(A_EXTOUT_ADC_CAP_L, A_EXTOUT_ADC_CAP_R, playback + SND_EMU10K1_PLAYBACK_CHANNELS);1687 A_PUT_STEREO_OUTPUT(A_EXTOUT_ADC_CAP_L, A_EXTOUT_ADC_CAP_R, playback); 1636 1688 #else 1637 1689 A_PUT_OUTPUT(A_EXTOUT_ADC_CAP_L, capture); … … 1640 1692 1641 1693 if (emu->card_capabilities->emu_model) { 1694 /* Capture 16 channels of S32_LE sound. */ 1642 1695 if (emu->card_capabilities->ca0108_chip) { 1643 1696 dev_info(emu->card->dev, "EMU2 inputs on\n"); 1644 for (z = 0; z < 0x10; z++) { 1697 /* Note that the Tina[2] DSPs have 16 more EMU32 inputs which we don't use. */ 1698 1699 snd_emu10k1_audigy_dsp_convert_32_to_2x16( 1700 icode, &ptr, tmp, bit_shifter16, A3_EMU32IN(0), A_FXBUS2(0)); 1701 // A3_EMU32IN(0) is delayed by one sample, so all other A3_EMU32IN channels 1702 // need to be delayed as well; we use an auxiliary register for that. 1703 for (z = 1; z < 0x10; z++) { 1645 1704 snd_emu10k1_audigy_dsp_convert_32_to_2x16( icode, &ptr, tmp, 1646 1705 bit_shifter16, 1647 A 3_EMU32IN(z),1706 A_GPR(gpr), 1648 1707 A_FXBUS2(z*2) ); 1708 A_OP(icode, &ptr, iACC3, A_GPR(gpr), A3_EMU32IN(z), A_C_00000000, A_C_00000000); 1709 gpr_map[gpr++] = 0x00000000; 1649 1710 } 1650 1711 } else { 1651 1712 dev_info(emu->card->dev, "EMU inputs on\n"); 1652 /* Capture 16 (originally 8) channels of S32_LE sound*/1713 /* Note that the Alice2 DSPs have 6 I2S inputs which we don't use. */ 1653 1714 1654 1715 /* … … 1656 1717 gpr, tmp); 1657 1718 */ 1658 /* For the EMU1010: How to get 32bit values from the DSP. High 16bits into L, low 16bits into R. */1659 /* A_P16VIN(0) is delayed by one sample,1660 * so all other A_P16VIN channels will need to also be delayed1661 */1662 /* Left ADC in. 1 of 2 */1663 1719 snd_emu10k1_audigy_dsp_convert_32_to_2x16( icode, &ptr, tmp, bit_shifter16, A_P16VIN(0x0), A_FXBUS2(0) ); 1664 /* Right ADC in 1 of 2 */ 1665 gpr_map[gpr++] = 0x00000000; 1666 /* Delaying by one sample: instead of copying the input 1667 * value A_P16VIN to output A_FXBUS2 as in the first channel, 1668 * we use an auxiliary register, delaying the value by one 1669 * sample 1670 */ 1671 snd_emu10k1_audigy_dsp_convert_32_to_2x16( icode, &ptr, tmp, bit_shifter16, A_GPR(gpr - 1), A_FXBUS2(2) ); 1672 A_OP(icode, &ptr, iACC3, A_GPR(gpr - 1), A_P16VIN(0x1), A_C_00000000, A_C_00000000); 1673 gpr_map[gpr++] = 0x00000000; 1674 snd_emu10k1_audigy_dsp_convert_32_to_2x16( icode, &ptr, tmp, bit_shifter16, A_GPR(gpr - 1), A_FXBUS2(4) ); 1675 A_OP(icode, &ptr, iACC3, A_GPR(gpr - 1), A_P16VIN(0x2), A_C_00000000, A_C_00000000); 1676 gpr_map[gpr++] = 0x00000000; 1677 snd_emu10k1_audigy_dsp_convert_32_to_2x16( icode, &ptr, tmp, bit_shifter16, A_GPR(gpr - 1), A_FXBUS2(6) ); 1678 A_OP(icode, &ptr, iACC3, A_GPR(gpr - 1), A_P16VIN(0x3), A_C_00000000, A_C_00000000); 1679 /* For 96kHz mode */ 1680 /* Left ADC in. 2 of 2 */ 1681 gpr_map[gpr++] = 0x00000000; 1682 snd_emu10k1_audigy_dsp_convert_32_to_2x16( icode, &ptr, tmp, bit_shifter16, A_GPR(gpr - 1), A_FXBUS2(0x8) ); 1683 A_OP(icode, &ptr, iACC3, A_GPR(gpr - 1), A_P16VIN(0x4), A_C_00000000, A_C_00000000); 1684 /* Right ADC in 2 of 2 */ 1685 gpr_map[gpr++] = 0x00000000; 1686 snd_emu10k1_audigy_dsp_convert_32_to_2x16( icode, &ptr, tmp, bit_shifter16, A_GPR(gpr - 1), A_FXBUS2(0xa) ); 1687 A_OP(icode, &ptr, iACC3, A_GPR(gpr - 1), A_P16VIN(0x5), A_C_00000000, A_C_00000000); 1688 gpr_map[gpr++] = 0x00000000; 1689 snd_emu10k1_audigy_dsp_convert_32_to_2x16( icode, &ptr, tmp, bit_shifter16, A_GPR(gpr - 1), A_FXBUS2(0xc) ); 1690 A_OP(icode, &ptr, iACC3, A_GPR(gpr - 1), A_P16VIN(0x6), A_C_00000000, A_C_00000000); 1691 gpr_map[gpr++] = 0x00000000; 1692 snd_emu10k1_audigy_dsp_convert_32_to_2x16( icode, &ptr, tmp, bit_shifter16, A_GPR(gpr - 1), A_FXBUS2(0xe) ); 1693 A_OP(icode, &ptr, iACC3, A_GPR(gpr - 1), A_P16VIN(0x7), A_C_00000000, A_C_00000000); 1694 /* Pavel Hofman - we still have voices, A_FXBUS2s, and 1695 * A_P16VINs available - 1696 * let's add 8 more capture channels - total of 16 1697 */ 1698 gpr_map[gpr++] = 0x00000000; 1699 snd_emu10k1_audigy_dsp_convert_32_to_2x16(icode, &ptr, tmp, 1700 bit_shifter16, 1701 A_GPR(gpr - 1), 1702 A_FXBUS2(0x10)); 1703 A_OP(icode, &ptr, iACC3, A_GPR(gpr - 1), A_P16VIN(0x8), 1704 A_C_00000000, A_C_00000000); 1705 gpr_map[gpr++] = 0x00000000; 1706 snd_emu10k1_audigy_dsp_convert_32_to_2x16(icode, &ptr, tmp, 1707 bit_shifter16, 1708 A_GPR(gpr - 1), 1709 A_FXBUS2(0x12)); 1710 A_OP(icode, &ptr, iACC3, A_GPR(gpr - 1), A_P16VIN(0x9), 1711 A_C_00000000, A_C_00000000); 1712 gpr_map[gpr++] = 0x00000000; 1713 snd_emu10k1_audigy_dsp_convert_32_to_2x16(icode, &ptr, tmp, 1714 bit_shifter16, 1715 A_GPR(gpr - 1), 1716 A_FXBUS2(0x14)); 1717 A_OP(icode, &ptr, iACC3, A_GPR(gpr - 1), A_P16VIN(0xa), 1718 A_C_00000000, A_C_00000000); 1719 gpr_map[gpr++] = 0x00000000; 1720 snd_emu10k1_audigy_dsp_convert_32_to_2x16(icode, &ptr, tmp, 1721 bit_shifter16, 1722 A_GPR(gpr - 1), 1723 A_FXBUS2(0x16)); 1724 A_OP(icode, &ptr, iACC3, A_GPR(gpr - 1), A_P16VIN(0xb), 1725 A_C_00000000, A_C_00000000); 1726 gpr_map[gpr++] = 0x00000000; 1727 snd_emu10k1_audigy_dsp_convert_32_to_2x16(icode, &ptr, tmp, 1728 bit_shifter16, 1729 A_GPR(gpr - 1), 1730 A_FXBUS2(0x18)); 1731 A_OP(icode, &ptr, iACC3, A_GPR(gpr - 1), A_P16VIN(0xc), 1732 A_C_00000000, A_C_00000000); 1733 gpr_map[gpr++] = 0x00000000; 1734 snd_emu10k1_audigy_dsp_convert_32_to_2x16(icode, &ptr, tmp, 1735 bit_shifter16, 1736 A_GPR(gpr - 1), 1737 A_FXBUS2(0x1a)); 1738 A_OP(icode, &ptr, iACC3, A_GPR(gpr - 1), A_P16VIN(0xd), 1739 A_C_00000000, A_C_00000000); 1740 gpr_map[gpr++] = 0x00000000; 1741 snd_emu10k1_audigy_dsp_convert_32_to_2x16(icode, &ptr, tmp, 1742 bit_shifter16, 1743 A_GPR(gpr - 1), 1744 A_FXBUS2(0x1c)); 1745 A_OP(icode, &ptr, iACC3, A_GPR(gpr - 1), A_P16VIN(0xe), 1746 A_C_00000000, A_C_00000000); 1747 gpr_map[gpr++] = 0x00000000; 1748 snd_emu10k1_audigy_dsp_convert_32_to_2x16(icode, &ptr, tmp, 1749 bit_shifter16, 1750 A_GPR(gpr - 1), 1751 A_FXBUS2(0x1e)); 1752 A_OP(icode, &ptr, iACC3, A_GPR(gpr - 1), A_P16VIN(0xf), 1753 A_C_00000000, A_C_00000000); 1720 /* A_P16VIN(0) is delayed by one sample, so all other A_P16VIN channels 1721 * will need to also be delayed; we use an auxiliary register for that. */ 1722 for (z = 1; z < 0x10; z++) { 1723 snd_emu10k1_audigy_dsp_convert_32_to_2x16( icode, &ptr, tmp, bit_shifter16, A_GPR(gpr), A_FXBUS2(z * 2) ); 1724 A_OP(icode, &ptr, iACC3, A_GPR(gpr), A_P16VIN(z), A_C_00000000, A_C_00000000); 1725 gpr_map[gpr++] = 0x00000000; 1726 } 1754 1727 } 1755 1728 … … 1775 1748 */ 1776 1749 1777 if (gpr > tmp) {1750 if (gpr > 512) { 1778 1751 snd_BUG(); 1779 1752 err = -EIO; 1780 1753 goto __err; 1781 1754 } 1755 1782 1756 /* clear remaining instruction memory */ 1783 1757 while (ptr < 0x400) … … 1804 1778 */ 1805 1779 1806 /* when volume = max, then copy only to avoid volume modification */ 1807 /* with iMAC0 (negative values) */ 1780 /* Volumes are in the [-2^31, 0] range, zero being mute. */ 1808 1781 static void _volume(struct snd_emu10k1_fx8010_code *icode, u32 *ptr, u32 dst, u32 src, u32 vol) 1809 1782 { 1810 OP(icode, ptr, iMAC0, dst, C_00000000, src, vol); 1811 OP(icode, ptr, iANDXOR, C_00000000, vol, C_ffffffff, C_7fffffff); 1812 OP(icode, ptr, iSKIP, GPR_COND, GPR_COND, CC_REG_NONZERO, C_00000001); 1813 OP(icode, ptr, iACC3, dst, src, C_00000000, C_00000000); 1783 OP(icode, ptr, iMAC1, dst, C_00000000, src, vol); 1814 1784 } 1815 1785 static void _volume_add(struct snd_emu10k1_fx8010_code *icode, u32 *ptr, u32 dst, u32 src, u32 vol) 1816 1786 { 1817 OP(icode, ptr, iANDXOR, C_00000000, vol, C_ffffffff, C_7fffffff); 1818 OP(icode, ptr, iSKIP, GPR_COND, GPR_COND, CC_REG_NONZERO, C_00000002); 1819 OP(icode, ptr, iMACINT0, dst, dst, src, C_00000001); 1820 OP(icode, ptr, iSKIP, C_00000000, C_7fffffff, C_7fffffff, C_00000001); 1821 OP(icode, ptr, iMAC0, dst, dst, src, vol); 1822 } 1823 static void _volume_out(struct snd_emu10k1_fx8010_code *icode, u32 *ptr, u32 dst, u32 src, u32 vol) 1824 { 1825 OP(icode, ptr, iANDXOR, C_00000000, vol, C_ffffffff, C_7fffffff); 1826 OP(icode, ptr, iSKIP, GPR_COND, GPR_COND, CC_REG_NONZERO, C_00000002); 1827 OP(icode, ptr, iACC3, dst, src, C_00000000, C_00000000); 1828 OP(icode, ptr, iSKIP, C_00000000, C_7fffffff, C_7fffffff, C_00000001); 1829 OP(icode, ptr, iMAC0, dst, C_00000000, src, vol); 1787 OP(icode, ptr, iMAC1, dst, dst, src, vol); 1830 1788 } 1831 1789 … … 1839 1797 _volume_add(icode, ptr, GPR(dst), EXTIN(src), GPR(vol)) 1840 1798 #define VOLUME_OUT(icode, ptr, dst, src, vol) \ 1841 _volume _out(icode, ptr, EXTOUT(dst), GPR(src), GPR(vol))1799 _volume(icode, ptr, EXTOUT(dst), GPR(src), GPR(vol)) 1842 1800 #define _SWITCH(icode, ptr, dst, src, sw) \ 1843 1801 OP((icode), ptr, iMACINT0, dst, C_00000000, src, sw); … … 1855 1813 { 1856 1814 int err, i, z, gpr, tmp, playback, capture; 1857 u32 ptr ;1815 u32 ptr, ptr_skip; 1858 1816 struct snd_emu10k1_fx8010_code *icode; 1859 1817 struct snd_emu10k1_fx8010_pcm_rec *ipcm = NULL; … … 1888 1846 1889 1847 /* clear free GPRs */ 1890 for (i = 0; i < 256; i++) 1891 set_bit(i, icode->gpr_valid); 1848 memset(icode->gpr_valid, 0xff, 256 / 8); 1892 1849 1893 1850 /* clear TRAM data & address lines */ 1894 for (i = 0; i < 160; i++) 1895 set_bit(i, icode->tram_valid); 1851 memset(icode->tram_valid, 0xff, 160 / 8); 1896 1852 1897 1853 strcpy(icode->name, "SB Live! FX8010 code for ALSA v1.2 by Jaroslav Kysela"); … … 1900 1856 playback = SND_EMU10K1_INPUTS; 1901 1857 /* we have 6 playback channels and tone control doubles */ 1902 capture = playback + (SND_EMU10K1_PLAYBACK_CHANNELS * 2);1858 capture = playback + SND_EMU10K1_PLAYBACK_CHANNELS; 1903 1859 gpr = capture + SND_EMU10K1_CAPTURE_CHANNELS; 1904 1860 tmp = 0x88; /* we need 4 temporary GPR */ 1905 1861 /* from 0x8c to 0xff is the area for tone control */ 1906 1862 1907 /* stop FX processor */1908 snd_emu10k1_ptr_write(emu, DBG, 0, (emu->fx8010.dbg = 0) | EMU10K1_DBG_SINGLE_STEP);1909 1910 1863 /* 1911 1864 * Process FX Buses 1912 1865 */ 1913 OP(icode, &ptr, iMACINT0, GPR(0), C_00000000, FXBUS(FXBUS_PCM_LEFT), C_0000000 4);1914 OP(icode, &ptr, iMACINT0, GPR(1), C_00000000, FXBUS(FXBUS_PCM_RIGHT), C_0000000 4);1915 OP(icode, &ptr, iMACINT0, GPR(2), C_00000000, FXBUS(FXBUS_MIDI_LEFT), C_0000000 4);1916 OP(icode, &ptr, iMACINT0, GPR(3), C_00000000, FXBUS(FXBUS_MIDI_RIGHT), C_0000000 4);1917 OP(icode, &ptr, iMACINT0, GPR(4), C_00000000, FXBUS(FXBUS_PCM_LEFT_REAR), C_0000000 4);1918 OP(icode, &ptr, iMACINT0, GPR(5), C_00000000, FXBUS(FXBUS_PCM_RIGHT_REAR), C_0000000 4);1919 OP(icode, &ptr, iMACINT0, GPR(6), C_00000000, FXBUS(FXBUS_PCM_CENTER), C_0000000 4);1920 OP(icode, &ptr, iMACINT0, GPR(7), C_00000000, FXBUS(FXBUS_PCM_LFE), C_0000000 4);1866 OP(icode, &ptr, iMACINT0, GPR(0), C_00000000, FXBUS(FXBUS_PCM_LEFT), C_00000008); 1867 OP(icode, &ptr, iMACINT0, GPR(1), C_00000000, FXBUS(FXBUS_PCM_RIGHT), C_00000008); 1868 OP(icode, &ptr, iMACINT0, GPR(2), C_00000000, FXBUS(FXBUS_MIDI_LEFT), C_00000008); 1869 OP(icode, &ptr, iMACINT0, GPR(3), C_00000000, FXBUS(FXBUS_MIDI_RIGHT), C_00000008); 1870 OP(icode, &ptr, iMACINT0, GPR(4), C_00000000, FXBUS(FXBUS_PCM_LEFT_REAR), C_00000008); 1871 OP(icode, &ptr, iMACINT0, GPR(5), C_00000000, FXBUS(FXBUS_PCM_RIGHT_REAR), C_00000008); 1872 OP(icode, &ptr, iMACINT0, GPR(6), C_00000000, FXBUS(FXBUS_PCM_CENTER), C_00000008); 1873 OP(icode, &ptr, iMACINT0, GPR(7), C_00000000, FXBUS(FXBUS_PCM_LFE), C_00000008); 1921 1874 OP(icode, &ptr, iMACINT0, GPR(8), C_00000000, C_00000000, C_00000000); /* S/PDIF left */ 1922 1875 OP(icode, &ptr, iMACINT0, GPR(9), C_00000000, C_00000000, C_00000000); /* S/PDIF right */ 1923 OP(icode, &ptr, iMACINT0, GPR(10), C_00000000, FXBUS(FXBUS_PCM_LEFT_FRONT), C_0000000 4);1924 OP(icode, &ptr, iMACINT0, GPR(11), C_00000000, FXBUS(FXBUS_PCM_RIGHT_FRONT), C_0000000 4);1876 OP(icode, &ptr, iMACINT0, GPR(10), C_00000000, FXBUS(FXBUS_PCM_LEFT_FRONT), C_00000008); 1877 OP(icode, &ptr, iMACINT0, GPR(11), C_00000000, FXBUS(FXBUS_PCM_RIGHT_FRONT), C_00000008); 1925 1878 1926 1879 /* Raw S/PDIF PCM */ … … 2016 1969 /* Wave Center/LFE Playback Volume */ 2017 1970 OP(icode, &ptr, iACC3, GPR(tmp + 0), FXBUS(FXBUS_PCM_LEFT), FXBUS(FXBUS_PCM_RIGHT), C_00000000); 2018 OP(icode, &ptr, iMACINT0, GPR(tmp + 0), C_00000000, GPR(tmp + 0), C_0000000 2);1971 OP(icode, &ptr, iMACINT0, GPR(tmp + 0), C_00000000, GPR(tmp + 0), C_00000004); 2019 1972 VOLUME(icode, &ptr, playback + 4, tmp + 0, gpr); 2020 1973 snd_emu10k1_init_mono_control(controls + i++, "Wave Center Playback Volume", gpr++, 0); … … 2207 2160 * Process tone control 2208 2161 */ 2209 OP(icode, &ptr, iACC3, GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 0), GPR(playback + 0), C_00000000, C_00000000); /* left */2210 OP(icode, &ptr, iACC3, GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 1), GPR(playback + 1), C_00000000, C_00000000); /* right */2211 OP(icode, &ptr, iACC3, GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 2), GPR(playback + 2), C_00000000, C_00000000); /* rear left */2212 OP(icode, &ptr, iACC3, GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 3), GPR(playback + 3), C_00000000, C_00000000); /* rear right */2213 OP(icode, &ptr, iACC3, GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 4), GPR(playback + 4), C_00000000, C_00000000); /* center */2214 OP(icode, &ptr, iACC3, GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 5), GPR(playback + 5), C_00000000, C_00000000); /* LFE */2215 2216 2162 ctl = &controls[i + 0]; 2217 2163 ctl->id.iface = (__force int)SNDRV_CTL_ELEM_IFACE_MIXER; … … 2245 2191 } 2246 2192 } 2193 i += 2; 2194 2195 OP(icode, &ptr, iACC3, C_00000000, GPR(gpr), C_00000000, C_00000000); 2196 snd_emu10k1_init_mono_onoff_control(controls + i++, "Tone Control - Switch", gpr, 0); 2197 gpr++; 2198 OP(icode, &ptr, iSKIP, GPR_COND, GPR_COND, CC_REG_ZERO, GPR(gpr)); 2199 ptr_skip = ptr; 2247 2200 for (z = 0; z < 3; z++) { /* front/rear/center-lfe */ 2248 2201 int j, k, l, d; … … 2250 2203 k = 0xa0 + (z * 8) + (j * 4); 2251 2204 l = 0xd0 + (z * 8) + (j * 4); 2252 d = playback + SND_EMU10K1_PLAYBACK_CHANNELS +z * 2 + j;2205 d = playback + z * 2 + j; 2253 2206 2254 2207 OP(icode, &ptr, iMAC0, C_00000000, C_00000000, GPR(d), GPR(BASS_GPR + 0 + j)); … … 2272 2225 } 2273 2226 } 2274 i += 2;2227 gpr_map[gpr++] = ptr - ptr_skip; 2275 2228 2276 2229 #undef BASS_GPR 2277 2230 #undef TREBLE_GPR 2278 2279 for (z = 0; z < 6; z++) {2280 SWITCH(icode, &ptr, tmp + 0, playback + SND_EMU10K1_PLAYBACK_CHANNELS + z, gpr + 0);2281 SWITCH_NEG(icode, &ptr, tmp + 1, gpr + 0);2282 SWITCH(icode, &ptr, tmp + 1, playback + z, tmp + 1);2283 OP(icode, &ptr, iACC3, GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + z), GPR(tmp + 0), GPR(tmp + 1), C_00000000);2284 }2285 snd_emu10k1_init_stereo_onoff_control(controls + i++, "Tone Control - Switch", gpr, 0);2286 gpr += 2;2287 2231 2288 2232 /* … … 2293 2237 2294 2238 for (z = 0; z < 2; z++) 2295 OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_AC97_L + z), GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS +z), C_00000000, C_00000000);2239 OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_AC97_L + z), GPR(playback + z), C_00000000, C_00000000); 2296 2240 } 2297 2241 … … 2302 2246 SWITCH(icode, &ptr, tmp + 0, 8 + z, gpr + z); 2303 2247 SWITCH_NEG(icode, &ptr, tmp + 1, gpr + z); 2304 SWITCH(icode, &ptr, tmp + 1, playback + SND_EMU10K1_PLAYBACK_CHANNELS +z, tmp + 1);2248 SWITCH(icode, &ptr, tmp + 1, playback + z, tmp + 1); 2305 2249 OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_TOSLINK_L + z), GPR(tmp + 0), GPR(tmp + 1), C_00000000); 2306 2250 #ifdef EMU10K1_CAPTURE_DIGITAL_OUT … … 2317 2261 2318 2262 for (z = 0; z < 2; z++) { 2319 SWITCH(icode, &ptr, tmp + 0, playback + SND_EMU10K1_PLAYBACK_CHANNELS +4 + z, gpr + 2 + z);2263 SWITCH(icode, &ptr, tmp + 0, playback + 4 + z, gpr + 2 + z); 2320 2264 SWITCH_NEG(icode, &ptr, tmp + 1, gpr + 2 + z); 2321 SWITCH(icode, &ptr, tmp + 1, playback + SND_EMU10K1_PLAYBACK_CHANNELS +z, tmp + 1);2265 SWITCH(icode, &ptr, tmp + 1, playback + z, tmp + 1); 2322 2266 OP(icode, &ptr, iACC3, GPR(tmp + 0), GPR(tmp + 0), GPR(tmp + 1), C_00000000); 2323 2267 VOLUME_OUT(icode, &ptr, EXTOUT_HEADPHONE_L + z, tmp + 0, gpr + z); … … 2336 2280 if (emu->fx8010.extout_mask & ((1<<EXTOUT_REAR_L)|(1<<EXTOUT_REAR_R))) 2337 2281 for (z = 0; z < 2; z++) 2338 OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_REAR_L + z), GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS +2 + z), C_00000000, C_00000000);2282 OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_REAR_L + z), GPR(playback + 2 + z), C_00000000, C_00000000); 2339 2283 2340 2284 if (emu->fx8010.extout_mask & ((1<<EXTOUT_AC97_REAR_L)|(1<<EXTOUT_AC97_REAR_R))) 2341 2285 for (z = 0; z < 2; z++) 2342 OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_AC97_REAR_L + z), GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS +2 + z), C_00000000, C_00000000);2286 OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_AC97_REAR_L + z), GPR(playback + 2 + z), C_00000000, C_00000000); 2343 2287 2344 2288 if (emu->fx8010.extout_mask & (1<<EXTOUT_AC97_CENTER)) { 2345 2289 #ifndef EMU10K1_CENTER_LFE_FROM_FRONT 2346 OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_AC97_CENTER), GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS +4), C_00000000, C_00000000);2347 OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_ACENTER), GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS +4), C_00000000, C_00000000);2290 OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_AC97_CENTER), GPR(playback + 4), C_00000000, C_00000000); 2291 OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_ACENTER), GPR(playback + 4), C_00000000, C_00000000); 2348 2292 #else 2349 OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_AC97_CENTER), GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS +0), C_00000000, C_00000000);2350 OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_ACENTER), GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS +0), C_00000000, C_00000000);2293 OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_AC97_CENTER), GPR(playback + 0), C_00000000, C_00000000); 2294 OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_ACENTER), GPR(playback + 0), C_00000000, C_00000000); 2351 2295 #endif 2352 2296 } … … 2354 2298 if (emu->fx8010.extout_mask & (1<<EXTOUT_AC97_LFE)) { 2355 2299 #ifndef EMU10K1_CENTER_LFE_FROM_FRONT 2356 OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_AC97_LFE), GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS +5), C_00000000, C_00000000);2357 OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_ALFE), GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS +5), C_00000000, C_00000000);2300 OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_AC97_LFE), GPR(playback + 5), C_00000000, C_00000000); 2301 OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_ALFE), GPR(playback + 5), C_00000000, C_00000000); 2358 2302 #else 2359 OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_AC97_LFE), GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS +1), C_00000000, C_00000000);2360 OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_ALFE), GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS +1), C_00000000, C_00000000);2303 OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_AC97_LFE), GPR(playback + 1), C_00000000, C_00000000); 2304 OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_ALFE), GPR(playback + 1), C_00000000, C_00000000); 2361 2305 #endif 2362 2306 } … … 2372 2316 /* EFX capture - capture the 16 EXTINS */ 2373 2317 if (emu->card_capabilities->sblive51) { 2374 /* On the Live! 5.1, FXBUS2(1) and FXBUS(2) are shared with EXTOUT_ACENTER 2375 * and EXTOUT_ALFE, so we can't connect inputs to them for multitrack recording. 2376 * 2377 * Since only 14 of the 16 EXTINs are used, this is not a big problem. 2378 * We route AC97L and R to FX capture 14 and 15, SPDIF CD in to FX capture 2379 * 0 and 3, then the rest of the EXTINs to the corresponding FX capture 2380 * channel. Multitrack recorders will still see the center/lfe output signal 2381 * on the second and third channels. 2382 */ 2383 OP(icode, &ptr, iACC3, FXBUS2(14), C_00000000, C_00000000, EXTIN(0)); 2384 OP(icode, &ptr, iACC3, FXBUS2(15), C_00000000, C_00000000, EXTIN(1)); 2385 OP(icode, &ptr, iACC3, FXBUS2(0), C_00000000, C_00000000, EXTIN(2)); 2386 OP(icode, &ptr, iACC3, FXBUS2(3), C_00000000, C_00000000, EXTIN(3)); 2387 for (z = 4; z < 14; z++) 2388 OP(icode, &ptr, iACC3, FXBUS2(z), C_00000000, C_00000000, EXTIN(z)); 2318 for (z = 0; z < 16; z++) { 2319 s8 c = snd_emu10k1_sblive51_fxbus2_map[z]; 2320 if (c != -1) 2321 OP(icode, &ptr, iACC3, FXBUS2(z), C_00000000, C_00000000, EXTIN(c)); 2322 } 2389 2323 } else { 2390 2324 for (z = 0; z < 16; z++) … … 2486 2420 spin_unlock_irq(&emu->emu_lock); 2487 2421 snd_emu10k1_ptr_write(emu, TCB, 0, 0); 2488 snd_emu10k1_ptr_write(emu, TCBS, 0, 0);2422 snd_emu10k1_ptr_write(emu, TCBS, 0, TCBS_BUFFSIZE_16K); 2489 2423 if (emu->fx8010.etram_pages.area != NULL) { 2490 2424 snd_dma_free_pages(&emu->fx8010.etram_pages); … … 2525 2459 { 2526 2460 const char * const *fxbus, * const *extin, * const *extout; 2527 unsigned short fxbus_mask,extin_mask, extout_mask;2461 unsigned short extin_mask, extout_mask; 2528 2462 int res; 2529 2463 2530 2464 info->internal_tram_size = emu->fx8010.itram_size; 2531 2465 info->external_tram_size = emu->fx8010.etram_pages.bytes / 2; 2532 fxbus = fxbuses; 2533 extin = emu->audigy ? audigy_ins : creative_ins; 2534 extout = emu->audigy ? audigy_outs : creative_outs; 2535 fxbus_mask = emu->fx8010.fxbus_mask; 2536 extin_mask = emu->fx8010.extin_mask; 2537 extout_mask = emu->fx8010.extout_mask; 2466 fxbus = snd_emu10k1_fxbus; 2467 extin = emu->audigy ? snd_emu10k1_audigy_ins : snd_emu10k1_sblive_ins; 2468 extout = emu->audigy ? snd_emu10k1_audigy_outs : snd_emu10k1_sblive_outs; 2469 extin_mask = emu->audigy ? ~0 : emu->fx8010.extin_mask; 2470 extout_mask = emu->audigy ? ~0 : emu->fx8010.extout_mask; 2538 2471 for (res = 0; res < 16; res++, fxbus++, extin++, extout++) { 2539 copy_string(info->fxbus_names[res], fxbus_mask & (1 << res) ? *fxbus : NULL, "FXBUS", res);2472 copy_string(info->fxbus_names[res], *fxbus, "FXBUS", res); 2540 2473 copy_string(info->extin_names[res], extin_mask & (1 << res) ? *extin : NULL, "Unused", res); 2541 2474 copy_string(info->extout_names[res], extout_mask & (1 << res) ? *extout : NULL, "Unused", res); … … 2653 2586 if (get_user(addr, (unsigned int __user *)argp)) 2654 2587 return -EFAULT; 2655 if (addr > 0x1ff) 2656 return -EINVAL; 2657 if (emu->audigy) 2658 snd_emu10k1_ptr_write(emu, A_DBG, 0, emu->fx8010.dbg |= A_DBG_SINGLE_STEP | addr); 2659 else 2660 snd_emu10k1_ptr_write(emu, DBG, 0, emu->fx8010.dbg |= EMU10K1_DBG_SINGLE_STEP | addr); 2661 udelay(10); 2662 if (emu->audigy) 2663 snd_emu10k1_ptr_write(emu, A_DBG, 0, emu->fx8010.dbg |= A_DBG_SINGLE_STEP | A_DBG_STEP_ADDR | addr); 2664 else 2665 snd_emu10k1_ptr_write(emu, DBG, 0, emu->fx8010.dbg |= EMU10K1_DBG_SINGLE_STEP | EMU10K1_DBG_STEP | addr); 2588 if (emu->audigy) { 2589 if (addr > A_DBG_STEP_ADDR) 2590 return -EINVAL; 2591 snd_emu10k1_ptr_write(emu, A_DBG, 0, emu->fx8010.dbg |= A_DBG_SINGLE_STEP); 2592 udelay(10); 2593 snd_emu10k1_ptr_write(emu, A_DBG, 0, emu->fx8010.dbg | A_DBG_STEP | addr); 2594 } else { 2595 if (addr > EMU10K1_DBG_SINGLE_STEP_ADDR) 2596 return -EINVAL; 2597 snd_emu10k1_ptr_write(emu, DBG, 0, emu->fx8010.dbg |= EMU10K1_DBG_SINGLE_STEP); 2598 udelay(10); 2599 snd_emu10k1_ptr_write(emu, DBG, 0, emu->fx8010.dbg | EMU10K1_DBG_STEP | addr); 2600 } 2666 2601 return 0; 2667 2602 case SNDRV_EMU10K1_IOCTL_DBG_READ: -
GPL/trunk/alsa-kernel/pci/emu10k1/emumixer.c
r703 r772 3 3 * Copyright (c) by Jaroslav Kysela <perex@perex.cz>, 4 4 * Takashi Iwai <tiwai@suse.de> 5 * Lee Revell <rlrevell@joe-job.com> 6 * James Courtier-Dutton <James@superbug.co.uk> 7 * Oswald Buddenhagen <oswald.buddenhagen@gmx.de> 5 8 * Creative Labs, Inc. 9 * 6 10 * Routines for control of EMU10K1 chips / mixer routines 7 * Multichannel PCM support Copyright (c) Lee Revell <rlrevell@joe-job.com>8 *9 * Copyright (c) by James Courtier-Dutton <James@superbug.co.uk>10 * Added EMU 1010 support.11 *12 * BUGS:13 * --14 *15 * TODO:16 * --17 11 */ 18 12 … … 30 24 static const DECLARE_TLV_DB_SCALE(snd_audigy_db_scale2, -10350, 50, 1); /* WM8775 gain scale */ 31 25 26 27 static int add_ctls(struct snd_emu10k1 *emu, const struct snd_kcontrol_new *tpl, 28 const char * const *ctls, unsigned nctls) 29 { 30 struct snd_kcontrol_new kctl = *tpl; 31 int err; 32 33 for (unsigned i = 0; i < nctls; i++) { 34 kctl.name = ctls[i]; 35 kctl.private_value = i; 36 err = snd_ctl_add(emu->card, snd_ctl_new1(&kctl, emu)); 37 if (err < 0) 38 return err; 39 } 40 return 0; 41 } 42 43 32 44 static int snd_emu10k1_spdif_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) 33 45 { … … 42 54 struct snd_emu10k1 *emu = snd_kcontrol_chip(kcontrol); 43 55 unsigned int idx = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id); 44 unsigned long flags;45 56 46 57 /* Limit: emu->spdif_bits */ 47 58 if (idx >= 3) 48 59 return -EINVAL; 49 spin_lock_irqsave(&emu->reg_lock, flags);50 60 ucontrol->value.iec958.status[0] = (emu->spdif_bits[idx] >> 0) & 0xff; 51 61 ucontrol->value.iec958.status[1] = (emu->spdif_bits[idx] >> 8) & 0xff; 52 62 ucontrol->value.iec958.status[2] = (emu->spdif_bits[idx] >> 16) & 0xff; 53 63 ucontrol->value.iec958.status[3] = (emu->spdif_bits[idx] >> 24) & 0xff; 54 spin_unlock_irqrestore(&emu->reg_lock, flags);55 64 return 0; 56 65 } … … 66 75 } 67 76 68 /* 69 * Items labels in enum mixer controls assigning source data to 70 * each destination 71 */ 72 static const char * const emu1010_src_texts[] = { 73 "Silence", 74 "Dock Mic A", 75 "Dock Mic B", 76 "Dock ADC1 Left", 77 "Dock ADC1 Right", 78 "Dock ADC2 Left", 79 "Dock ADC2 Right", 80 "Dock ADC3 Left", 81 "Dock ADC3 Right", 82 "0202 ADC Left", 83 "0202 ADC Right", 84 "0202 SPDIF Left", 85 "0202 SPDIF Right", 86 "ADAT 0", 87 "ADAT 1", 88 "ADAT 2", 89 "ADAT 3", 90 "ADAT 4", 91 "ADAT 5", 92 "ADAT 6", 93 "ADAT 7", 94 "DSP 0", 95 "DSP 1", 96 "DSP 2", 97 "DSP 3", 98 "DSP 4", 99 "DSP 5", 100 "DSP 6", 101 "DSP 7", 102 "DSP 8", 103 "DSP 9", 104 "DSP 10", 105 "DSP 11", 106 "DSP 12", 107 "DSP 13", 108 "DSP 14", 109 "DSP 15", 110 "DSP 16", 111 "DSP 17", 112 "DSP 18", 113 "DSP 19", 114 "DSP 20", 115 "DSP 21", 116 "DSP 22", 117 "DSP 23", 118 "DSP 24", 119 "DSP 25", 120 "DSP 26", 121 "DSP 27", 122 "DSP 28", 123 "DSP 29", 124 "DSP 30", 125 "DSP 31", 126 }; 127 128 /* 1616(m) cardbus */ 129 130 static const char * const emu1616_src_texts[] = { 131 "Silence", 132 "Dock Mic A", 133 "Dock Mic B", 134 "Dock ADC1 Left", 135 "Dock ADC1 Right", 136 "Dock ADC2 Left", 137 "Dock ADC2 Right", 138 "Dock SPDIF Left", 139 "Dock SPDIF Right", 140 "ADAT 0", 141 "ADAT 1", 142 "ADAT 2", 143 "ADAT 3", 144 "ADAT 4", 145 "ADAT 5", 146 "ADAT 6", 147 "ADAT 7", 148 "DSP 0", 149 "DSP 1", 150 "DSP 2", 151 "DSP 3", 152 "DSP 4", 153 "DSP 5", 154 "DSP 6", 155 "DSP 7", 156 "DSP 8", 157 "DSP 9", 158 "DSP 10", 159 "DSP 11", 160 "DSP 12", 161 "DSP 13", 162 "DSP 14", 163 "DSP 15", 164 "DSP 16", 165 "DSP 17", 166 "DSP 18", 167 "DSP 19", 168 "DSP 20", 169 "DSP 21", 170 "DSP 22", 171 "DSP 23", 172 "DSP 24", 173 "DSP 25", 174 "DSP 26", 175 "DSP 27", 176 "DSP 28", 177 "DSP 29", 178 "DSP 30", 179 "DSP 31", 180 }; 181 77 #define PAIR_PS(base, one, two, sfx) base " " one sfx, base " " two sfx 78 #define LR_PS(base, sfx) PAIR_PS(base, "Left", "Right", sfx) 79 80 #define ADAT_PS(pfx, sfx) \ 81 pfx "ADAT 0" sfx, pfx "ADAT 1" sfx, pfx "ADAT 2" sfx, pfx "ADAT 3" sfx, \ 82 pfx "ADAT 4" sfx, pfx "ADAT 5" sfx, pfx "ADAT 6" sfx, pfx "ADAT 7" sfx 83 84 #define PAIR_REGS(base, one, two) \ 85 base ## one ## 1, \ 86 base ## two ## 1 87 88 #define LR_REGS(base) PAIR_REGS(base, _LEFT, _RIGHT) 89 90 #define ADAT_REGS(base) \ 91 base+0, base+1, base+2, base+3, base+4, base+5, base+6, base+7 182 92 183 93 /* 184 94 * List of data sources available for each destination 185 95 */ 186 static const unsigned int emu1010_src_regs[] = { 187 EMU_SRC_SILENCE,/* 0 */ 188 EMU_SRC_DOCK_MIC_A1, /* 1 */ 189 EMU_SRC_DOCK_MIC_B1, /* 2 */ 190 EMU_SRC_DOCK_ADC1_LEFT1, /* 3 */ 191 EMU_SRC_DOCK_ADC1_RIGHT1, /* 4 */ 192 EMU_SRC_DOCK_ADC2_LEFT1, /* 5 */ 193 EMU_SRC_DOCK_ADC2_RIGHT1, /* 6 */ 194 EMU_SRC_DOCK_ADC3_LEFT1, /* 7 */ 195 EMU_SRC_DOCK_ADC3_RIGHT1, /* 8 */ 196 EMU_SRC_HAMOA_ADC_LEFT1, /* 9 */ 197 EMU_SRC_HAMOA_ADC_RIGHT1, /* 10 */ 198 EMU_SRC_HANA_SPDIF_LEFT1, /* 11 */ 199 EMU_SRC_HANA_SPDIF_RIGHT1, /* 12 */ 200 EMU_SRC_HANA_ADAT, /* 13 */ 201 EMU_SRC_HANA_ADAT+1, /* 14 */ 202 EMU_SRC_HANA_ADAT+2, /* 15 */ 203 EMU_SRC_HANA_ADAT+3, /* 16 */ 204 EMU_SRC_HANA_ADAT+4, /* 17 */ 205 EMU_SRC_HANA_ADAT+5, /* 18 */ 206 EMU_SRC_HANA_ADAT+6, /* 19 */ 207 EMU_SRC_HANA_ADAT+7, /* 20 */ 208 EMU_SRC_ALICE_EMU32A, /* 21 */ 209 EMU_SRC_ALICE_EMU32A+1, /* 22 */ 210 EMU_SRC_ALICE_EMU32A+2, /* 23 */ 211 EMU_SRC_ALICE_EMU32A+3, /* 24 */ 212 EMU_SRC_ALICE_EMU32A+4, /* 25 */ 213 EMU_SRC_ALICE_EMU32A+5, /* 26 */ 214 EMU_SRC_ALICE_EMU32A+6, /* 27 */ 215 EMU_SRC_ALICE_EMU32A+7, /* 28 */ 216 EMU_SRC_ALICE_EMU32A+8, /* 29 */ 217 EMU_SRC_ALICE_EMU32A+9, /* 30 */ 218 EMU_SRC_ALICE_EMU32A+0xa, /* 31 */ 219 EMU_SRC_ALICE_EMU32A+0xb, /* 32 */ 220 EMU_SRC_ALICE_EMU32A+0xc, /* 33 */ 221 EMU_SRC_ALICE_EMU32A+0xd, /* 34 */ 222 EMU_SRC_ALICE_EMU32A+0xe, /* 35 */ 223 EMU_SRC_ALICE_EMU32A+0xf, /* 36 */ 224 EMU_SRC_ALICE_EMU32B, /* 37 */ 225 EMU_SRC_ALICE_EMU32B+1, /* 38 */ 226 EMU_SRC_ALICE_EMU32B+2, /* 39 */ 227 EMU_SRC_ALICE_EMU32B+3, /* 40 */ 228 EMU_SRC_ALICE_EMU32B+4, /* 41 */ 229 EMU_SRC_ALICE_EMU32B+5, /* 42 */ 230 EMU_SRC_ALICE_EMU32B+6, /* 43 */ 231 EMU_SRC_ALICE_EMU32B+7, /* 44 */ 232 EMU_SRC_ALICE_EMU32B+8, /* 45 */ 233 EMU_SRC_ALICE_EMU32B+9, /* 46 */ 234 EMU_SRC_ALICE_EMU32B+0xa, /* 47 */ 235 EMU_SRC_ALICE_EMU32B+0xb, /* 48 */ 236 EMU_SRC_ALICE_EMU32B+0xc, /* 49 */ 237 EMU_SRC_ALICE_EMU32B+0xd, /* 50 */ 238 EMU_SRC_ALICE_EMU32B+0xe, /* 51 */ 239 EMU_SRC_ALICE_EMU32B+0xf, /* 52 */ 240 }; 96 97 #define DSP_TEXTS \ 98 "DSP 0", "DSP 1", "DSP 2", "DSP 3", "DSP 4", "DSP 5", "DSP 6", "DSP 7", \ 99 "DSP 8", "DSP 9", "DSP 10", "DSP 11", "DSP 12", "DSP 13", "DSP 14", "DSP 15", \ 100 "DSP 16", "DSP 17", "DSP 18", "DSP 19", "DSP 20", "DSP 21", "DSP 22", "DSP 23", \ 101 "DSP 24", "DSP 25", "DSP 26", "DSP 27", "DSP 28", "DSP 29", "DSP 30", "DSP 31" 102 103 #define PAIR_TEXTS(base, one, two) PAIR_PS(base, one, two, "") 104 #define LR_TEXTS(base) LR_PS(base, "") 105 #define ADAT_TEXTS(pfx) ADAT_PS(pfx, "") 106 107 #define EMU32_SRC_REGS \ 108 EMU_SRC_ALICE_EMU32A, \ 109 EMU_SRC_ALICE_EMU32A+1, \ 110 EMU_SRC_ALICE_EMU32A+2, \ 111 EMU_SRC_ALICE_EMU32A+3, \ 112 EMU_SRC_ALICE_EMU32A+4, \ 113 EMU_SRC_ALICE_EMU32A+5, \ 114 EMU_SRC_ALICE_EMU32A+6, \ 115 EMU_SRC_ALICE_EMU32A+7, \ 116 EMU_SRC_ALICE_EMU32A+8, \ 117 EMU_SRC_ALICE_EMU32A+9, \ 118 EMU_SRC_ALICE_EMU32A+0xa, \ 119 EMU_SRC_ALICE_EMU32A+0xb, \ 120 EMU_SRC_ALICE_EMU32A+0xc, \ 121 EMU_SRC_ALICE_EMU32A+0xd, \ 122 EMU_SRC_ALICE_EMU32A+0xe, \ 123 EMU_SRC_ALICE_EMU32A+0xf, \ 124 EMU_SRC_ALICE_EMU32B, \ 125 EMU_SRC_ALICE_EMU32B+1, \ 126 EMU_SRC_ALICE_EMU32B+2, \ 127 EMU_SRC_ALICE_EMU32B+3, \ 128 EMU_SRC_ALICE_EMU32B+4, \ 129 EMU_SRC_ALICE_EMU32B+5, \ 130 EMU_SRC_ALICE_EMU32B+6, \ 131 EMU_SRC_ALICE_EMU32B+7, \ 132 EMU_SRC_ALICE_EMU32B+8, \ 133 EMU_SRC_ALICE_EMU32B+9, \ 134 EMU_SRC_ALICE_EMU32B+0xa, \ 135 EMU_SRC_ALICE_EMU32B+0xb, \ 136 EMU_SRC_ALICE_EMU32B+0xc, \ 137 EMU_SRC_ALICE_EMU32B+0xd, \ 138 EMU_SRC_ALICE_EMU32B+0xe, \ 139 EMU_SRC_ALICE_EMU32B+0xf 140 141 /* 1010 rev1 */ 142 143 #define EMU1010_COMMON_TEXTS \ 144 "Silence", \ 145 PAIR_TEXTS("Dock Mic", "A", "B"), \ 146 LR_TEXTS("Dock ADC1"), \ 147 LR_TEXTS("Dock ADC2"), \ 148 LR_TEXTS("Dock ADC3"), \ 149 LR_TEXTS("0202 ADC"), \ 150 LR_TEXTS("1010 SPDIF"), \ 151 ADAT_TEXTS("1010 ") 152 153 static const char * const emu1010_src_texts[] = { 154 EMU1010_COMMON_TEXTS, 155 DSP_TEXTS, 156 }; 157 158 static const unsigned short emu1010_src_regs[] = { 159 EMU_SRC_SILENCE, 160 PAIR_REGS(EMU_SRC_DOCK_MIC, _A, _B), 161 LR_REGS(EMU_SRC_DOCK_ADC1), 162 LR_REGS(EMU_SRC_DOCK_ADC2), 163 LR_REGS(EMU_SRC_DOCK_ADC3), 164 LR_REGS(EMU_SRC_HAMOA_ADC), 165 LR_REGS(EMU_SRC_HANA_SPDIF), 166 ADAT_REGS(EMU_SRC_HANA_ADAT), 167 EMU32_SRC_REGS, 168 }; 169 //static_assert(ARRAY_SIZE(emu1010_src_regs) == ARRAY_SIZE(emu1010_src_texts)); 170 171 /* 1010 rev2 */ 172 173 #define EMU1010b_COMMON_TEXTS \ 174 "Silence", \ 175 PAIR_TEXTS("Dock Mic", "A", "B"), \ 176 LR_TEXTS("Dock ADC1"), \ 177 LR_TEXTS("Dock ADC2"), \ 178 LR_TEXTS("0202 ADC"), \ 179 LR_TEXTS("Dock SPDIF"), \ 180 LR_TEXTS("1010 SPDIF"), \ 181 ADAT_TEXTS("Dock "), \ 182 ADAT_TEXTS("1010 ") 183 184 static const char * const emu1010b_src_texts[] = { 185 EMU1010b_COMMON_TEXTS, 186 DSP_TEXTS, 187 }; 188 189 static const unsigned short emu1010b_src_regs[] = { 190 EMU_SRC_SILENCE, 191 PAIR_REGS(EMU_SRC_DOCK_MIC, _A, _B), 192 LR_REGS(EMU_SRC_DOCK_ADC1), 193 LR_REGS(EMU_SRC_DOCK_ADC2), 194 LR_REGS(EMU_SRC_HAMOA_ADC), 195 LR_REGS(EMU_SRC_MDOCK_SPDIF), 196 LR_REGS(EMU_SRC_HANA_SPDIF), 197 ADAT_REGS(EMU_SRC_MDOCK_ADAT), 198 ADAT_REGS(EMU_SRC_HANA_ADAT), 199 EMU32_SRC_REGS, 200 }; 201 //static_assert(ARRAY_SIZE(emu1010b_src_regs) == ARRAY_SIZE(emu1010b_src_texts)); 241 202 242 203 /* 1616(m) cardbus */ 243 static const unsigned int emu1616_src_regs[] = { 204 205 #define EMU1616_COMMON_TEXTS \ 206 "Silence", \ 207 PAIR_TEXTS("Mic", "A", "B"), \ 208 LR_TEXTS("ADC1"), \ 209 LR_TEXTS("ADC2"), \ 210 LR_TEXTS("SPDIF"), \ 211 ADAT_TEXTS("") 212 213 static const char * const emu1616_src_texts[] = { 214 EMU1616_COMMON_TEXTS, 215 DSP_TEXTS, 216 }; 217 218 static const unsigned short emu1616_src_regs[] = { 244 219 EMU_SRC_SILENCE, 245 EMU_SRC_DOCK_MIC_A1, 246 EMU_SRC_DOCK_MIC_B1, 247 EMU_SRC_DOCK_ADC1_LEFT1, 248 EMU_SRC_DOCK_ADC1_RIGHT1, 249 EMU_SRC_DOCK_ADC2_LEFT1, 250 EMU_SRC_DOCK_ADC2_RIGHT1, 251 EMU_SRC_MDOCK_SPDIF_LEFT1, 252 EMU_SRC_MDOCK_SPDIF_RIGHT1, 253 EMU_SRC_MDOCK_ADAT, 254 EMU_SRC_MDOCK_ADAT+1, 255 EMU_SRC_MDOCK_ADAT+2, 256 EMU_SRC_MDOCK_ADAT+3, 257 EMU_SRC_MDOCK_ADAT+4, 258 EMU_SRC_MDOCK_ADAT+5, 259 EMU_SRC_MDOCK_ADAT+6, 260 EMU_SRC_MDOCK_ADAT+7, 261 EMU_SRC_ALICE_EMU32A, 262 EMU_SRC_ALICE_EMU32A+1, 263 EMU_SRC_ALICE_EMU32A+2, 264 EMU_SRC_ALICE_EMU32A+3, 265 EMU_SRC_ALICE_EMU32A+4, 266 EMU_SRC_ALICE_EMU32A+5, 267 EMU_SRC_ALICE_EMU32A+6, 268 EMU_SRC_ALICE_EMU32A+7, 269 EMU_SRC_ALICE_EMU32A+8, 270 EMU_SRC_ALICE_EMU32A+9, 271 EMU_SRC_ALICE_EMU32A+0xa, 272 EMU_SRC_ALICE_EMU32A+0xb, 273 EMU_SRC_ALICE_EMU32A+0xc, 274 EMU_SRC_ALICE_EMU32A+0xd, 275 EMU_SRC_ALICE_EMU32A+0xe, 276 EMU_SRC_ALICE_EMU32A+0xf, 277 EMU_SRC_ALICE_EMU32B, 278 EMU_SRC_ALICE_EMU32B+1, 279 EMU_SRC_ALICE_EMU32B+2, 280 EMU_SRC_ALICE_EMU32B+3, 281 EMU_SRC_ALICE_EMU32B+4, 282 EMU_SRC_ALICE_EMU32B+5, 283 EMU_SRC_ALICE_EMU32B+6, 284 EMU_SRC_ALICE_EMU32B+7, 285 EMU_SRC_ALICE_EMU32B+8, 286 EMU_SRC_ALICE_EMU32B+9, 287 EMU_SRC_ALICE_EMU32B+0xa, 288 EMU_SRC_ALICE_EMU32B+0xb, 289 EMU_SRC_ALICE_EMU32B+0xc, 290 EMU_SRC_ALICE_EMU32B+0xd, 291 EMU_SRC_ALICE_EMU32B+0xe, 292 EMU_SRC_ALICE_EMU32B+0xf, 293 }; 220 PAIR_REGS(EMU_SRC_DOCK_MIC, _A, _B), 221 LR_REGS(EMU_SRC_DOCK_ADC1), 222 LR_REGS(EMU_SRC_DOCK_ADC2), 223 LR_REGS(EMU_SRC_MDOCK_SPDIF), 224 ADAT_REGS(EMU_SRC_MDOCK_ADAT), 225 EMU32_SRC_REGS, 226 }; 227 //static_assert(ARRAY_SIZE(emu1616_src_regs) == ARRAY_SIZE(emu1616_src_texts)); 228 229 /* 0404 rev1 & rev2 */ 230 231 #define EMU0404_COMMON_TEXTS \ 232 "Silence", \ 233 LR_TEXTS("ADC"), \ 234 LR_TEXTS("SPDIF") 235 236 static const char * const emu0404_src_texts[] = { 237 EMU0404_COMMON_TEXTS, 238 DSP_TEXTS, 239 }; 240 241 static const unsigned short emu0404_src_regs[] = { 242 EMU_SRC_SILENCE, 243 LR_REGS(EMU_SRC_HAMOA_ADC), 244 LR_REGS(EMU_SRC_HANA_SPDIF), 245 EMU32_SRC_REGS, 246 }; 247 //static_assert(ARRAY_SIZE(emu0404_src_regs) == ARRAY_SIZE(emu0404_src_texts)); 294 248 295 249 /* … … 297 251 * Each destination has an enum mixer control to choose a data source 298 252 */ 299 static const unsigned int emu1010_output_dst[] = { 300 EMU_DST_DOCK_DAC1_LEFT1, /* 0 */ 301 EMU_DST_DOCK_DAC1_RIGHT1, /* 1 */ 302 EMU_DST_DOCK_DAC2_LEFT1, /* 2 */ 303 EMU_DST_DOCK_DAC2_RIGHT1, /* 3 */ 304 EMU_DST_DOCK_DAC3_LEFT1, /* 4 */ 305 EMU_DST_DOCK_DAC3_RIGHT1, /* 5 */ 306 EMU_DST_DOCK_DAC4_LEFT1, /* 6 */ 307 EMU_DST_DOCK_DAC4_RIGHT1, /* 7 */ 308 EMU_DST_DOCK_PHONES_LEFT1, /* 8 */ 309 EMU_DST_DOCK_PHONES_RIGHT1, /* 9 */ 310 EMU_DST_DOCK_SPDIF_LEFT1, /* 10 */ 311 EMU_DST_DOCK_SPDIF_RIGHT1, /* 11 */ 312 EMU_DST_HANA_SPDIF_LEFT1, /* 12 */ 313 EMU_DST_HANA_SPDIF_RIGHT1, /* 13 */ 314 EMU_DST_HAMOA_DAC_LEFT1, /* 14 */ 315 EMU_DST_HAMOA_DAC_RIGHT1, /* 15 */ 316 EMU_DST_HANA_ADAT, /* 16 */ 317 EMU_DST_HANA_ADAT+1, /* 17 */ 318 EMU_DST_HANA_ADAT+2, /* 18 */ 319 EMU_DST_HANA_ADAT+3, /* 19 */ 320 EMU_DST_HANA_ADAT+4, /* 20 */ 321 EMU_DST_HANA_ADAT+5, /* 21 */ 322 EMU_DST_HANA_ADAT+6, /* 22 */ 323 EMU_DST_HANA_ADAT+7, /* 23 */ 253 254 #define LR_CTLS(base) LR_PS(base, " Playback Enum") 255 #define ADAT_CTLS(pfx) ADAT_PS(pfx, " Playback Enum") 256 257 /* 1010 rev1 */ 258 259 static const char * const emu1010_output_texts[] = { 260 LR_CTLS("Dock DAC1"), 261 LR_CTLS("Dock DAC2"), 262 LR_CTLS("Dock DAC3"), 263 LR_CTLS("Dock DAC4"), 264 LR_CTLS("Dock Phones"), 265 LR_CTLS("Dock SPDIF"), 266 LR_CTLS("0202 DAC"), 267 LR_CTLS("1010 SPDIF"), 268 ADAT_CTLS("1010 "), 269 }; 270 //static_assert(ARRAY_SIZE(emu1010_output_texts) <= NUM_OUTPUT_DESTS); 271 272 static const unsigned short emu1010_output_dst[] = { 273 LR_REGS(EMU_DST_DOCK_DAC1), 274 LR_REGS(EMU_DST_DOCK_DAC2), 275 LR_REGS(EMU_DST_DOCK_DAC3), 276 LR_REGS(EMU_DST_DOCK_DAC4), 277 LR_REGS(EMU_DST_DOCK_PHONES), 278 LR_REGS(EMU_DST_DOCK_SPDIF), 279 LR_REGS(EMU_DST_HAMOA_DAC), 280 LR_REGS(EMU_DST_HANA_SPDIF), 281 ADAT_REGS(EMU_DST_HANA_ADAT), 282 }; 283 //static_assert(ARRAY_SIZE(emu1010_output_dst) == ARRAY_SIZE(emu1010_output_texts)); 284 285 static const unsigned short emu1010_output_dflt[] = { 286 EMU_SRC_ALICE_EMU32A+0, EMU_SRC_ALICE_EMU32A+1, 287 EMU_SRC_ALICE_EMU32A+2, EMU_SRC_ALICE_EMU32A+3, 288 EMU_SRC_ALICE_EMU32A+4, EMU_SRC_ALICE_EMU32A+5, 289 EMU_SRC_ALICE_EMU32A+6, EMU_SRC_ALICE_EMU32A+7, 290 EMU_SRC_ALICE_EMU32A+0, EMU_SRC_ALICE_EMU32A+1, 291 EMU_SRC_ALICE_EMU32A+0, EMU_SRC_ALICE_EMU32A+1, 292 EMU_SRC_ALICE_EMU32A+0, EMU_SRC_ALICE_EMU32A+1, 293 EMU_SRC_ALICE_EMU32A+0, EMU_SRC_ALICE_EMU32A+1, 294 EMU_SRC_ALICE_EMU32A+0, EMU_SRC_ALICE_EMU32A+1, EMU_SRC_ALICE_EMU32A+2, EMU_SRC_ALICE_EMU32A+3, 295 EMU_SRC_ALICE_EMU32A+4, EMU_SRC_ALICE_EMU32A+5, EMU_SRC_ALICE_EMU32A+6, EMU_SRC_ALICE_EMU32A+7, 296 }; 297 //static_assert(ARRAY_SIZE(emu1010_output_dflt) == ARRAY_SIZE(emu1010_output_dst)); 298 299 /* 1010 rev2 */ 300 301 static const char * const snd_emu1010b_output_texts[] = { 302 LR_CTLS("Dock DAC1"), 303 LR_CTLS("Dock DAC2"), 304 LR_CTLS("Dock DAC3"), 305 LR_CTLS("Dock SPDIF"), 306 ADAT_CTLS("Dock "), 307 LR_CTLS("0202 DAC"), 308 LR_CTLS("1010 SPDIF"), 309 ADAT_CTLS("1010 "), 310 }; 311 //static_assert(ARRAY_SIZE(snd_emu1010b_output_texts) <= NUM_OUTPUT_DESTS); 312 313 static const unsigned short emu1010b_output_dst[] = { 314 LR_REGS(EMU_DST_DOCK_DAC1), 315 LR_REGS(EMU_DST_DOCK_DAC2), 316 LR_REGS(EMU_DST_DOCK_DAC3), 317 LR_REGS(EMU_DST_MDOCK_SPDIF), 318 ADAT_REGS(EMU_DST_MDOCK_ADAT), 319 LR_REGS(EMU_DST_HAMOA_DAC), 320 LR_REGS(EMU_DST_HANA_SPDIF), 321 ADAT_REGS(EMU_DST_HANA_ADAT), 322 }; 323 //static_assert(ARRAY_SIZE(emu1010b_output_dst) == ARRAY_SIZE(snd_emu1010b_output_texts)); 324 325 static const unsigned short emu1010b_output_dflt[] = { 326 EMU_SRC_ALICE_EMU32A+0, EMU_SRC_ALICE_EMU32A+1, 327 EMU_SRC_ALICE_EMU32A+2, EMU_SRC_ALICE_EMU32A+3, 328 EMU_SRC_ALICE_EMU32A+4, EMU_SRC_ALICE_EMU32A+5, 329 EMU_SRC_ALICE_EMU32A+0, EMU_SRC_ALICE_EMU32A+1, 330 EMU_SRC_ALICE_EMU32A+0, EMU_SRC_ALICE_EMU32A+1, EMU_SRC_ALICE_EMU32A+2, EMU_SRC_ALICE_EMU32A+3, 331 EMU_SRC_ALICE_EMU32A+4, EMU_SRC_ALICE_EMU32A+5, EMU_SRC_ALICE_EMU32A+6, EMU_SRC_ALICE_EMU32A+7, 332 EMU_SRC_ALICE_EMU32A+0, EMU_SRC_ALICE_EMU32A+1, 333 EMU_SRC_ALICE_EMU32A+0, EMU_SRC_ALICE_EMU32A+1, 334 EMU_SRC_ALICE_EMU32A+0, EMU_SRC_ALICE_EMU32A+1, EMU_SRC_ALICE_EMU32A+2, EMU_SRC_ALICE_EMU32A+3, 335 EMU_SRC_ALICE_EMU32A+4, EMU_SRC_ALICE_EMU32A+5, EMU_SRC_ALICE_EMU32A+6, EMU_SRC_ALICE_EMU32A+7, 324 336 }; 325 337 326 338 /* 1616(m) cardbus */ 327 static const unsigned int emu1616_output_dst[] = { 328 EMU_DST_DOCK_DAC1_LEFT1, 329 EMU_DST_DOCK_DAC1_RIGHT1, 330 EMU_DST_DOCK_DAC2_LEFT1, 331 EMU_DST_DOCK_DAC2_RIGHT1, 332 EMU_DST_DOCK_DAC3_LEFT1, 333 EMU_DST_DOCK_DAC3_RIGHT1, 334 EMU_DST_MDOCK_SPDIF_LEFT1, 335 EMU_DST_MDOCK_SPDIF_RIGHT1, 336 EMU_DST_MDOCK_ADAT, 337 EMU_DST_MDOCK_ADAT+1, 338 EMU_DST_MDOCK_ADAT+2, 339 EMU_DST_MDOCK_ADAT+3, 340 EMU_DST_MDOCK_ADAT+4, 341 EMU_DST_MDOCK_ADAT+5, 342 EMU_DST_MDOCK_ADAT+6, 343 EMU_DST_MDOCK_ADAT+7, 344 EMU_DST_MANA_DAC_LEFT, 345 EMU_DST_MANA_DAC_RIGHT, 346 }; 339 340 static const char * const snd_emu1616_output_texts[] = { 341 LR_CTLS("Dock DAC1"), 342 LR_CTLS("Dock DAC2"), 343 LR_CTLS("Dock DAC3"), 344 LR_CTLS("Dock SPDIF"), 345 ADAT_CTLS("Dock "), 346 LR_CTLS("Mana DAC"), 347 }; 348 //static_assert(ARRAY_SIZE(snd_emu1616_output_texts) <= NUM_OUTPUT_DESTS); 349 350 static const unsigned short emu1616_output_dst[] = { 351 LR_REGS(EMU_DST_DOCK_DAC1), 352 LR_REGS(EMU_DST_DOCK_DAC2), 353 LR_REGS(EMU_DST_DOCK_DAC3), 354 LR_REGS(EMU_DST_MDOCK_SPDIF), 355 ADAT_REGS(EMU_DST_MDOCK_ADAT), 356 EMU_DST_MANA_DAC_LEFT, EMU_DST_MANA_DAC_RIGHT, 357 }; 358 //static_assert(ARRAY_SIZE(emu1616_output_dst) == ARRAY_SIZE(snd_emu1616_output_texts)); 359 360 static const unsigned short emu1616_output_dflt[] = { 361 EMU_SRC_ALICE_EMU32A+0, EMU_SRC_ALICE_EMU32A+1, 362 EMU_SRC_ALICE_EMU32A+2, EMU_SRC_ALICE_EMU32A+3, 363 EMU_SRC_ALICE_EMU32A+4, EMU_SRC_ALICE_EMU32A+5, 364 EMU_SRC_ALICE_EMU32A+0, EMU_SRC_ALICE_EMU32A+1, 365 EMU_SRC_ALICE_EMU32A+0, EMU_SRC_ALICE_EMU32A+1, EMU_SRC_ALICE_EMU32A+2, EMU_SRC_ALICE_EMU32A+3, 366 EMU_SRC_ALICE_EMU32A+4, EMU_SRC_ALICE_EMU32A+5, EMU_SRC_ALICE_EMU32A+6, EMU_SRC_ALICE_EMU32A+7, 367 EMU_SRC_ALICE_EMU32A+0, EMU_SRC_ALICE_EMU32A+1, 368 }; 369 //static_assert(ARRAY_SIZE(emu1616_output_dflt) == ARRAY_SIZE(emu1616_output_dst)); 370 371 /* 0404 rev1 & rev2 */ 372 373 static const char * const snd_emu0404_output_texts[] = { 374 LR_CTLS("DAC"), 375 LR_CTLS("SPDIF"), 376 }; 377 //static_assert(ARRAY_SIZE(snd_emu0404_output_texts) <= NUM_OUTPUT_DESTS); 378 379 static const unsigned short emu0404_output_dst[] = { 380 LR_REGS(EMU_DST_HAMOA_DAC), 381 LR_REGS(EMU_DST_HANA_SPDIF), 382 }; 383 //static_assert(ARRAY_SIZE(emu0404_output_dst) == ARRAY_SIZE(snd_emu0404_output_texts)); 384 385 static const unsigned short emu0404_output_dflt[] = { 386 EMU_SRC_ALICE_EMU32A+0, EMU_SRC_ALICE_EMU32A+1, 387 EMU_SRC_ALICE_EMU32A+0, EMU_SRC_ALICE_EMU32A+1, 388 }; 389 //static_assert(ARRAY_SIZE(emu0404_output_dflt) == ARRAY_SIZE(emu0404_output_dst)); 347 390 348 391 /* 349 * Data destinations - HANA outputs going to Alice2 (audigy) for392 * Data destinations - FPGA outputs going to Alice2 (Audigy) for 350 393 * capture (EMU32 + I2S links) 351 394 * Each destination has an enum mixer control to choose a data source 352 395 */ 353 static const unsigned int emu1010_input_dst[] = { 396 397 static const char * const emu1010_input_texts[] = { 398 "DSP 0 Capture Enum", 399 "DSP 1 Capture Enum", 400 "DSP 2 Capture Enum", 401 "DSP 3 Capture Enum", 402 "DSP 4 Capture Enum", 403 "DSP 5 Capture Enum", 404 "DSP 6 Capture Enum", 405 "DSP 7 Capture Enum", 406 "DSP 8 Capture Enum", 407 "DSP 9 Capture Enum", 408 "DSP A Capture Enum", 409 "DSP B Capture Enum", 410 "DSP C Capture Enum", 411 "DSP D Capture Enum", 412 "DSP E Capture Enum", 413 "DSP F Capture Enum", 414 /* These exist only on rev1 EMU1010 cards. */ 415 "DSP 10 Capture Enum", 416 "DSP 11 Capture Enum", 417 "DSP 12 Capture Enum", 418 "DSP 13 Capture Enum", 419 "DSP 14 Capture Enum", 420 "DSP 15 Capture Enum", 421 }; 422 //static_assert(ARRAY_SIZE(emu1010_input_texts) <= NUM_INPUT_DESTS); 423 424 static const unsigned short emu1010_input_dst[] = { 354 425 EMU_DST_ALICE2_EMU32_0, 355 426 EMU_DST_ALICE2_EMU32_1, … … 368 439 EMU_DST_ALICE2_EMU32_E, 369 440 EMU_DST_ALICE2_EMU32_F, 441 /* These exist only on rev1 EMU1010 cards. */ 370 442 EMU_DST_ALICE_I2S0_LEFT, 371 443 EMU_DST_ALICE_I2S0_RIGHT, … … 375 447 EMU_DST_ALICE_I2S2_RIGHT, 376 448 }; 449 //static_assert(ARRAY_SIZE(emu1010_input_dst) == ARRAY_SIZE(emu1010_input_texts)); 450 451 static const unsigned short emu1010_input_dflt[] = { 452 EMU_SRC_DOCK_MIC_A1, 453 EMU_SRC_DOCK_MIC_B1, 454 EMU_SRC_HAMOA_ADC_LEFT1, 455 EMU_SRC_HAMOA_ADC_RIGHT1, 456 EMU_SRC_DOCK_ADC1_LEFT1, 457 EMU_SRC_DOCK_ADC1_RIGHT1, 458 EMU_SRC_DOCK_ADC2_LEFT1, 459 EMU_SRC_DOCK_ADC2_RIGHT1, 460 /* Pavel Hofman - setting defaults for all capture channels. 461 * Defaults only, users will set their own values anyways, let's 462 * just copy/paste. */ 463 EMU_SRC_DOCK_MIC_A1, 464 EMU_SRC_DOCK_MIC_B1, 465 EMU_SRC_HAMOA_ADC_LEFT1, 466 EMU_SRC_HAMOA_ADC_RIGHT1, 467 EMU_SRC_DOCK_ADC1_LEFT1, 468 EMU_SRC_DOCK_ADC1_RIGHT1, 469 EMU_SRC_DOCK_ADC2_LEFT1, 470 EMU_SRC_DOCK_ADC2_RIGHT1, 471 472 EMU_SRC_DOCK_ADC1_LEFT1, 473 EMU_SRC_DOCK_ADC1_RIGHT1, 474 EMU_SRC_DOCK_ADC2_LEFT1, 475 EMU_SRC_DOCK_ADC2_RIGHT1, 476 EMU_SRC_DOCK_ADC3_LEFT1, 477 EMU_SRC_DOCK_ADC3_RIGHT1, 478 }; 479 //static_assert(ARRAY_SIZE(emu1010_input_dflt) == ARRAY_SIZE(emu1010_input_dst)); 480 481 static const unsigned short emu0404_input_dflt[] = { 482 EMU_SRC_HAMOA_ADC_LEFT1, 483 EMU_SRC_HAMOA_ADC_RIGHT1, 484 EMU_SRC_SILENCE, 485 EMU_SRC_SILENCE, 486 EMU_SRC_SILENCE, 487 EMU_SRC_SILENCE, 488 EMU_SRC_SILENCE, 489 EMU_SRC_SILENCE, 490 EMU_SRC_HANA_SPDIF_LEFT1, 491 EMU_SRC_HANA_SPDIF_RIGHT1, 492 EMU_SRC_SILENCE, 493 EMU_SRC_SILENCE, 494 EMU_SRC_SILENCE, 495 EMU_SRC_SILENCE, 496 EMU_SRC_SILENCE, 497 EMU_SRC_SILENCE, 498 }; 499 500 struct snd_emu1010_routing_info { 501 const char * const *src_texts; 502 const char * const *out_texts; 503 const unsigned short *src_regs; 504 const unsigned short *out_regs; 505 const unsigned short *in_regs; 506 const unsigned short *out_dflts; 507 const unsigned short *in_dflts; 508 unsigned n_srcs; 509 unsigned n_outs; 510 unsigned n_ins; 511 }; 512 513 static const struct snd_emu1010_routing_info emu1010_routing_info[] = { 514 { 515 /* rev1 1010 */ 516 .src_regs = emu1010_src_regs, 517 .src_texts = emu1010_src_texts, 518 .n_srcs = ARRAY_SIZE(emu1010_src_texts), 519 520 .out_dflts = emu1010_output_dflt, 521 .out_regs = emu1010_output_dst, 522 .out_texts = emu1010_output_texts, 523 .n_outs = ARRAY_SIZE(emu1010_output_dst), 524 525 .in_dflts = emu1010_input_dflt, 526 .in_regs = emu1010_input_dst, 527 .n_ins = ARRAY_SIZE(emu1010_input_dst), 528 }, 529 { 530 /* rev2 1010 */ 531 .src_regs = emu1010b_src_regs, 532 .src_texts = emu1010b_src_texts, 533 .n_srcs = ARRAY_SIZE(emu1010b_src_texts), 534 535 .out_dflts = emu1010b_output_dflt, 536 .out_regs = emu1010b_output_dst, 537 .out_texts = snd_emu1010b_output_texts, 538 .n_outs = ARRAY_SIZE(emu1010b_output_dst), 539 540 .in_dflts = emu1010_input_dflt, 541 .in_regs = emu1010_input_dst, 542 .n_ins = ARRAY_SIZE(emu1010_input_dst) - 6, 543 }, 544 { 545 /* 1616(m) cardbus */ 546 .src_regs = emu1616_src_regs, 547 .src_texts = emu1616_src_texts, 548 .n_srcs = ARRAY_SIZE(emu1616_src_texts), 549 550 .out_dflts = emu1616_output_dflt, 551 .out_regs = emu1616_output_dst, 552 .out_texts = snd_emu1616_output_texts, 553 .n_outs = ARRAY_SIZE(emu1616_output_dst), 554 555 .in_dflts = emu1010_input_dflt, 556 .in_regs = emu1010_input_dst, 557 .n_ins = ARRAY_SIZE(emu1010_input_dst) - 6, 558 }, 559 { 560 /* 0404 */ 561 .src_regs = emu0404_src_regs, 562 .src_texts = emu0404_src_texts, 563 .n_srcs = ARRAY_SIZE(emu0404_src_texts), 564 565 .out_dflts = emu0404_output_dflt, 566 .out_regs = emu0404_output_dst, 567 .out_texts = snd_emu0404_output_texts, 568 .n_outs = ARRAY_SIZE(emu0404_output_dflt), 569 570 .in_dflts = emu0404_input_dflt, 571 .in_regs = emu1010_input_dst, 572 .n_ins = ARRAY_SIZE(emu1010_input_dst) - 6, 573 }, 574 }; 575 576 static unsigned emu1010_idx(struct snd_emu10k1 *emu) 577 { 578 return emu->card_capabilities->emu_model - 1; 579 } 580 581 static void snd_emu1010_output_source_apply(struct snd_emu10k1 *emu, 582 int channel, int src) 583 { 584 const struct snd_emu1010_routing_info *emu_ri = 585 &emu1010_routing_info[emu1010_idx(emu)]; 586 587 snd_emu1010_fpga_link_dst_src_write(emu, 588 emu_ri->out_regs[channel], emu_ri->src_regs[src]); 589 } 590 591 static void snd_emu1010_input_source_apply(struct snd_emu10k1 *emu, 592 int channel, int src) 593 { 594 const struct snd_emu1010_routing_info *emu_ri = 595 &emu1010_routing_info[emu1010_idx(emu)]; 596 597 snd_emu1010_fpga_link_dst_src_write(emu, 598 emu_ri->in_regs[channel], emu_ri->src_regs[src]); 599 } 600 601 static void snd_emu1010_apply_sources(struct snd_emu10k1 *emu) 602 { 603 const struct snd_emu1010_routing_info *emu_ri = 604 &emu1010_routing_info[emu1010_idx(emu)]; 605 606 for (unsigned i = 0; i < emu_ri->n_outs; i++) 607 snd_emu1010_output_source_apply( 608 emu, i, emu->emu1010.output_source[i]); 609 for (unsigned i = 0; i < emu_ri->n_ins; i++) 610 snd_emu1010_input_source_apply( 611 emu, i, emu->emu1010.input_source[i]); 612 } 613 614 static u8 emu1010_map_source(const struct snd_emu1010_routing_info *emu_ri, 615 unsigned val) 616 { 617 for (unsigned i = 0; i < emu_ri->n_srcs; i++) 618 if (val == emu_ri->src_regs[i]) 619 return i; 620 return 0; 621 } 377 622 378 623 static int snd_emu1010_input_output_source_info(struct snd_kcontrol *kcontrol, … … 380 625 { 381 626 struct snd_emu10k1 *emu = snd_kcontrol_chip(kcontrol); 382 383 if (emu->card_capabilities->emu_model == EMU_MODEL_EMU1616) 384 return snd_ctl_enum_info(uinfo, 1, 49, emu1616_src_texts); 385 else 386 return snd_ctl_enum_info(uinfo, 1, 53, emu1010_src_texts); 627 const struct snd_emu1010_routing_info *emu_ri = 628 &emu1010_routing_info[emu1010_idx(emu)]; 629 630 return snd_ctl_enum_info(uinfo, 1, emu_ri->n_srcs, emu_ri->src_texts); 387 631 } 388 632 … … 391 635 { 392 636 struct snd_emu10k1 *emu = snd_kcontrol_chip(kcontrol); 393 unsigned int channel; 394 395 channel = (kcontrol->private_value) & 0xff; 396 /* Limit: emu1010_output_dst, emu->emu1010.output_source */ 397 if (channel >= 24 || 398 (emu->card_capabilities->emu_model == EMU_MODEL_EMU1616 && 399 channel >= 18)) 637 const struct snd_emu1010_routing_info *emu_ri = 638 &emu1010_routing_info[emu1010_idx(emu)]; 639 unsigned channel = kcontrol->private_value; 640 641 if (channel >= emu_ri->n_outs) 400 642 return -EINVAL; 401 643 ucontrol->value.enumerated.item[0] = emu->emu1010.output_source[channel]; … … 407 649 { 408 650 struct snd_emu10k1 *emu = snd_kcontrol_chip(kcontrol); 409 unsigned int val;410 unsigned int channel;411 412 val = ucontrol->value.enumerated.item[0];413 i f (val >= 53 ||414 (emu->card_capabilities->emu_model == EMU_MODEL_EMU1616 && 415 val >= 49))651 const struct snd_emu1010_routing_info *emu_ri = 652 &emu1010_routing_info[emu1010_idx(emu)]; 653 unsigned val = ucontrol->value.enumerated.item[0]; 654 unsigned channel = kcontrol->private_value; 655 int change; 656 657 if (val >= emu_ri->n_srcs) 416 658 return -EINVAL; 417 channel = (kcontrol->private_value) & 0xff; 418 /* Limit: emu1010_output_dst, emu->emu1010.output_source */ 419 if (channel >= 24 || 420 (emu->card_capabilities->emu_model == EMU_MODEL_EMU1616 && 421 channel >= 18)) 659 if (channel >= emu_ri->n_outs) 422 660 return -EINVAL; 423 if (emu->emu1010.output_source[channel] == val) 424 return 0; 425 emu->emu1010.output_source[channel] = val; 426 if (emu->card_capabilities->emu_model == EMU_MODEL_EMU1616) 427 snd_emu1010_fpga_link_dst_src_write(emu, 428 emu1616_output_dst[channel], emu1616_src_regs[val]); 429 else 430 snd_emu1010_fpga_link_dst_src_write(emu, 431 emu1010_output_dst[channel], emu1010_src_regs[val]); 432 return 1; 433 } 661 change = (emu->emu1010.output_source[channel] != val); 662 if (change) { 663 emu->emu1010.output_source[channel] = val; 664 snd_emu1010_output_source_apply(emu, channel, val); 665 } 666 return change; 667 } 668 669 static const struct snd_kcontrol_new emu1010_output_source_ctl = { 670 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, 671 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE, 672 .info = snd_emu1010_input_output_source_info, 673 .get = snd_emu1010_output_source_get, 674 .put = snd_emu1010_output_source_put 675 }; 434 676 435 677 static int snd_emu1010_input_source_get(struct snd_kcontrol *kcontrol, … … 437 679 { 438 680 struct snd_emu10k1 *emu = snd_kcontrol_chip(kcontrol); 439 unsigned int channel;440 441 channel = (kcontrol->private_value) & 0xff;442 /* Limit: emu1010_input_dst, emu->emu1010.input_source */ 443 if (channel >= 22)681 const struct snd_emu1010_routing_info *emu_ri = 682 &emu1010_routing_info[emu1010_idx(emu)]; 683 unsigned channel = kcontrol->private_value; 684 685 if (channel >= emu_ri->n_ins) 444 686 return -EINVAL; 445 687 ucontrol->value.enumerated.item[0] = emu->emu1010.input_source[channel]; … … 451 693 { 452 694 struct snd_emu10k1 *emu = snd_kcontrol_chip(kcontrol); 453 unsigned int val;454 unsigned int channel;455 456 val = ucontrol->value.enumerated.item[0];457 i f (val >= 53 ||458 (emu->card_capabilities->emu_model == EMU_MODEL_EMU1616 && 459 val >= 49))695 const struct snd_emu1010_routing_info *emu_ri = 696 &emu1010_routing_info[emu1010_idx(emu)]; 697 unsigned val = ucontrol->value.enumerated.item[0]; 698 unsigned channel = kcontrol->private_value; 699 int change; 700 701 if (val >= emu_ri->n_srcs) 460 702 return -EINVAL; 461 channel = (kcontrol->private_value) & 0xff; 462 /* Limit: emu1010_input_dst, emu->emu1010.input_source */ 463 if (channel >= 22) 703 if (channel >= emu_ri->n_ins) 464 704 return -EINVAL; 465 if (emu->emu1010.input_source[channel] == val) 466 return 0; 467 emu->emu1010.input_source[channel] = val; 468 if (emu->card_capabilities->emu_model == EMU_MODEL_EMU1616) 469 snd_emu1010_fpga_link_dst_src_write(emu, 470 emu1010_input_dst[channel], emu1616_src_regs[val]); 471 else 472 snd_emu1010_fpga_link_dst_src_write(emu, 473 emu1010_input_dst[channel], emu1010_src_regs[val]); 474 return 1; 475 } 476 477 #define EMU1010_SOURCE_OUTPUT(xname,chid) \ 478 { \ 479 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ 480 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE, \ 481 .info = snd_emu1010_input_output_source_info, \ 482 .get = snd_emu1010_output_source_get, \ 483 .put = snd_emu1010_output_source_put, \ 484 .private_value = chid \ 485 } 486 487 static const struct snd_kcontrol_new snd_emu1010_output_enum_ctls[] = { 488 EMU1010_SOURCE_OUTPUT("Dock DAC1 Left Playback Enum", 0), 489 EMU1010_SOURCE_OUTPUT("Dock DAC1 Right Playback Enum", 1), 490 EMU1010_SOURCE_OUTPUT("Dock DAC2 Left Playback Enum", 2), 491 EMU1010_SOURCE_OUTPUT("Dock DAC2 Right Playback Enum", 3), 492 EMU1010_SOURCE_OUTPUT("Dock DAC3 Left Playback Enum", 4), 493 EMU1010_SOURCE_OUTPUT("Dock DAC3 Right Playback Enum", 5), 494 EMU1010_SOURCE_OUTPUT("Dock DAC4 Left Playback Enum", 6), 495 EMU1010_SOURCE_OUTPUT("Dock DAC4 Right Playback Enum", 7), 496 EMU1010_SOURCE_OUTPUT("Dock Phones Left Playback Enum", 8), 497 EMU1010_SOURCE_OUTPUT("Dock Phones Right Playback Enum", 9), 498 EMU1010_SOURCE_OUTPUT("Dock SPDIF Left Playback Enum", 0xa), 499 EMU1010_SOURCE_OUTPUT("Dock SPDIF Right Playback Enum", 0xb), 500 EMU1010_SOURCE_OUTPUT("1010 SPDIF Left Playback Enum", 0xc), 501 EMU1010_SOURCE_OUTPUT("1010 SPDIF Right Playback Enum", 0xd), 502 EMU1010_SOURCE_OUTPUT("0202 DAC Left Playback Enum", 0xe), 503 EMU1010_SOURCE_OUTPUT("0202 DAC Right Playback Enum", 0xf), 504 EMU1010_SOURCE_OUTPUT("1010 ADAT 0 Playback Enum", 0x10), 505 EMU1010_SOURCE_OUTPUT("1010 ADAT 1 Playback Enum", 0x11), 506 EMU1010_SOURCE_OUTPUT("1010 ADAT 2 Playback Enum", 0x12), 507 EMU1010_SOURCE_OUTPUT("1010 ADAT 3 Playback Enum", 0x13), 508 EMU1010_SOURCE_OUTPUT("1010 ADAT 4 Playback Enum", 0x14), 509 EMU1010_SOURCE_OUTPUT("1010 ADAT 5 Playback Enum", 0x15), 510 EMU1010_SOURCE_OUTPUT("1010 ADAT 6 Playback Enum", 0x16), 511 EMU1010_SOURCE_OUTPUT("1010 ADAT 7 Playback Enum", 0x17), 512 }; 513 514 515 /* 1616(m) cardbus */ 516 static const struct snd_kcontrol_new snd_emu1616_output_enum_ctls[] = { 517 EMU1010_SOURCE_OUTPUT("Dock DAC1 Left Playback Enum", 0), 518 EMU1010_SOURCE_OUTPUT("Dock DAC1 Right Playback Enum", 1), 519 EMU1010_SOURCE_OUTPUT("Dock DAC2 Left Playback Enum", 2), 520 EMU1010_SOURCE_OUTPUT("Dock DAC2 Right Playback Enum", 3), 521 EMU1010_SOURCE_OUTPUT("Dock DAC3 Left Playback Enum", 4), 522 EMU1010_SOURCE_OUTPUT("Dock DAC3 Right Playback Enum", 5), 523 EMU1010_SOURCE_OUTPUT("Dock SPDIF Left Playback Enum", 6), 524 EMU1010_SOURCE_OUTPUT("Dock SPDIF Right Playback Enum", 7), 525 EMU1010_SOURCE_OUTPUT("Dock ADAT 0 Playback Enum", 8), 526 EMU1010_SOURCE_OUTPUT("Dock ADAT 1 Playback Enum", 9), 527 EMU1010_SOURCE_OUTPUT("Dock ADAT 2 Playback Enum", 0xa), 528 EMU1010_SOURCE_OUTPUT("Dock ADAT 3 Playback Enum", 0xb), 529 EMU1010_SOURCE_OUTPUT("Dock ADAT 4 Playback Enum", 0xc), 530 EMU1010_SOURCE_OUTPUT("Dock ADAT 5 Playback Enum", 0xd), 531 EMU1010_SOURCE_OUTPUT("Dock ADAT 6 Playback Enum", 0xe), 532 EMU1010_SOURCE_OUTPUT("Dock ADAT 7 Playback Enum", 0xf), 533 EMU1010_SOURCE_OUTPUT("Mana DAC Left Playback Enum", 0x10), 534 EMU1010_SOURCE_OUTPUT("Mana DAC Right Playback Enum", 0x11), 535 }; 536 537 538 #define EMU1010_SOURCE_INPUT(xname,chid) \ 539 { \ 540 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ 541 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE, \ 542 .info = snd_emu1010_input_output_source_info, \ 543 .get = snd_emu1010_input_source_get, \ 544 .put = snd_emu1010_input_source_put, \ 545 .private_value = chid \ 546 } 547 548 static const struct snd_kcontrol_new snd_emu1010_input_enum_ctls[] = { 549 EMU1010_SOURCE_INPUT("DSP 0 Capture Enum", 0), 550 EMU1010_SOURCE_INPUT("DSP 1 Capture Enum", 1), 551 EMU1010_SOURCE_INPUT("DSP 2 Capture Enum", 2), 552 EMU1010_SOURCE_INPUT("DSP 3 Capture Enum", 3), 553 EMU1010_SOURCE_INPUT("DSP 4 Capture Enum", 4), 554 EMU1010_SOURCE_INPUT("DSP 5 Capture Enum", 5), 555 EMU1010_SOURCE_INPUT("DSP 6 Capture Enum", 6), 556 EMU1010_SOURCE_INPUT("DSP 7 Capture Enum", 7), 557 EMU1010_SOURCE_INPUT("DSP 8 Capture Enum", 8), 558 EMU1010_SOURCE_INPUT("DSP 9 Capture Enum", 9), 559 EMU1010_SOURCE_INPUT("DSP A Capture Enum", 0xa), 560 EMU1010_SOURCE_INPUT("DSP B Capture Enum", 0xb), 561 EMU1010_SOURCE_INPUT("DSP C Capture Enum", 0xc), 562 EMU1010_SOURCE_INPUT("DSP D Capture Enum", 0xd), 563 EMU1010_SOURCE_INPUT("DSP E Capture Enum", 0xe), 564 EMU1010_SOURCE_INPUT("DSP F Capture Enum", 0xf), 565 EMU1010_SOURCE_INPUT("DSP 10 Capture Enum", 0x10), 566 EMU1010_SOURCE_INPUT("DSP 11 Capture Enum", 0x11), 567 EMU1010_SOURCE_INPUT("DSP 12 Capture Enum", 0x12), 568 EMU1010_SOURCE_INPUT("DSP 13 Capture Enum", 0x13), 569 EMU1010_SOURCE_INPUT("DSP 14 Capture Enum", 0x14), 570 EMU1010_SOURCE_INPUT("DSP 15 Capture Enum", 0x15), 571 }; 572 573 705 change = (emu->emu1010.input_source[channel] != val); 706 if (change) { 707 emu->emu1010.input_source[channel] = val; 708 snd_emu1010_input_source_apply(emu, channel, val); 709 } 710 return change; 711 } 712 713 static const struct snd_kcontrol_new emu1010_input_source_ctl = { 714 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, 715 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE, 716 .info = snd_emu1010_input_output_source_info, 717 .get = snd_emu1010_input_source_get, 718 .put = snd_emu1010_input_source_put 719 }; 720 721 static int add_emu1010_source_mixers(struct snd_emu10k1 *emu) 722 { 723 const struct snd_emu1010_routing_info *emu_ri = 724 &emu1010_routing_info[emu1010_idx(emu)]; 725 int err; 726 727 err = add_ctls(emu, &emu1010_output_source_ctl, 728 emu_ri->out_texts, emu_ri->n_outs); 729 if (err < 0) 730 return err; 731 err = add_ctls(emu, &emu1010_input_source_ctl, 732 emu1010_input_texts, emu_ri->n_ins); 733 return err; 734 } 735 736 737 static const char * const snd_emu1010_adc_pads[] = { 738 "ADC1 14dB PAD 0202 Capture Switch", 739 "ADC1 14dB PAD Audio Dock Capture Switch", 740 "ADC2 14dB PAD Audio Dock Capture Switch", 741 "ADC3 14dB PAD Audio Dock Capture Switch", 742 }; 743 744 static const unsigned short snd_emu1010_adc_pad_regs[] = { 745 EMU_HANA_0202_ADC_PAD1, 746 EMU_HANA_DOCK_ADC_PAD1, 747 EMU_HANA_DOCK_ADC_PAD2, 748 EMU_HANA_DOCK_ADC_PAD3, 749 }; 574 750 575 751 #define snd_emu1010_adc_pads_info snd_ctl_boolean_mono_info … … 578 754 { 579 755 struct snd_emu10k1 *emu = snd_kcontrol_chip(kcontrol); 580 unsigned int mask = kcontrol->private_value & 0xff; 756 unsigned int mask = snd_emu1010_adc_pad_regs[kcontrol->private_value]; 757 581 758 ucontrol->value.integer.value[0] = (emu->emu1010.adc_pads & mask) ? 1 : 0; 582 759 return 0; … … 586 763 { 587 764 struct snd_emu10k1 *emu = snd_kcontrol_chip(kcontrol); 588 unsigned int mask = kcontrol->private_value & 0xff;765 unsigned int mask = snd_emu1010_adc_pad_regs[kcontrol->private_value]; 589 766 unsigned int val, cache; 767 int change; 768 590 769 val = ucontrol->value.integer.value[0]; 591 770 cache = emu->emu1010.adc_pads; … … 594 773 else 595 774 cache = cache & ~mask; 596 if (cache != emu->emu1010.adc_pads) { 775 change = (cache != emu->emu1010.adc_pads); 776 if (change) { 597 777 snd_emu1010_fpga_write(emu, EMU_HANA_ADC_PADS, cache ); 598 778 emu->emu1010.adc_pads = cache; 599 779 } 600 780 601 return 0; 602 } 603 604 605 606 #define EMU1010_ADC_PADS(xname,chid) \ 607 { \ 608 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ 609 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE, \ 610 .info = snd_emu1010_adc_pads_info, \ 611 .get = snd_emu1010_adc_pads_get, \ 612 .put = snd_emu1010_adc_pads_put, \ 613 .private_value = chid \ 614 } 615 616 static const struct snd_kcontrol_new snd_emu1010_adc_pads[] = { 617 EMU1010_ADC_PADS("ADC1 14dB PAD Audio Dock Capture Switch", EMU_HANA_DOCK_ADC_PAD1), 618 EMU1010_ADC_PADS("ADC2 14dB PAD Audio Dock Capture Switch", EMU_HANA_DOCK_ADC_PAD2), 619 EMU1010_ADC_PADS("ADC3 14dB PAD Audio Dock Capture Switch", EMU_HANA_DOCK_ADC_PAD3), 620 EMU1010_ADC_PADS("ADC1 14dB PAD 0202 Capture Switch", EMU_HANA_0202_ADC_PAD1), 781 return change; 782 } 783 784 static const struct snd_kcontrol_new emu1010_adc_pads_ctl = { 785 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, 786 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE, 787 .info = snd_emu1010_adc_pads_info, 788 .get = snd_emu1010_adc_pads_get, 789 .put = snd_emu1010_adc_pads_put 790 }; 791 792 793 static const char * const snd_emu1010_dac_pads[] = { 794 "DAC1 0202 14dB PAD Playback Switch", 795 "DAC1 Audio Dock 14dB PAD Playback Switch", 796 "DAC2 Audio Dock 14dB PAD Playback Switch", 797 "DAC3 Audio Dock 14dB PAD Playback Switch", 798 "DAC4 Audio Dock 14dB PAD Playback Switch", 799 }; 800 801 static const unsigned short snd_emu1010_dac_regs[] = { 802 EMU_HANA_0202_DAC_PAD1, 803 EMU_HANA_DOCK_DAC_PAD1, 804 EMU_HANA_DOCK_DAC_PAD2, 805 EMU_HANA_DOCK_DAC_PAD3, 806 EMU_HANA_DOCK_DAC_PAD4, 621 807 }; 622 808 … … 626 812 { 627 813 struct snd_emu10k1 *emu = snd_kcontrol_chip(kcontrol); 628 unsigned int mask = kcontrol->private_value & 0xff; 814 unsigned int mask = snd_emu1010_dac_regs[kcontrol->private_value]; 815 629 816 ucontrol->value.integer.value[0] = (emu->emu1010.dac_pads & mask) ? 1 : 0; 630 817 return 0; … … 634 821 { 635 822 struct snd_emu10k1 *emu = snd_kcontrol_chip(kcontrol); 636 unsigned int mask = kcontrol->private_value & 0xff;823 unsigned int mask = snd_emu1010_dac_regs[kcontrol->private_value]; 637 824 unsigned int val, cache; 825 int change; 826 638 827 val = ucontrol->value.integer.value[0]; 639 828 cache = emu->emu1010.dac_pads; … … 642 831 else 643 832 cache = cache & ~mask; 644 if (cache != emu->emu1010.dac_pads) { 833 change = (cache != emu->emu1010.dac_pads); 834 if (change) { 645 835 snd_emu1010_fpga_write(emu, EMU_HANA_DAC_PADS, cache ); 646 836 emu->emu1010.dac_pads = cache; 647 837 } 648 838 649 return 0; 650 } 651 652 653 654 #define EMU1010_DAC_PADS(xname,chid) \ 655 { \ 656 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ 657 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE, \ 658 .info = snd_emu1010_dac_pads_info, \ 659 .get = snd_emu1010_dac_pads_get, \ 660 .put = snd_emu1010_dac_pads_put, \ 661 .private_value = chid \ 662 } 663 664 static const struct snd_kcontrol_new snd_emu1010_dac_pads[] = { 665 EMU1010_DAC_PADS("DAC1 Audio Dock 14dB PAD Playback Switch", EMU_HANA_DOCK_DAC_PAD1), 666 EMU1010_DAC_PADS("DAC2 Audio Dock 14dB PAD Playback Switch", EMU_HANA_DOCK_DAC_PAD2), 667 EMU1010_DAC_PADS("DAC3 Audio Dock 14dB PAD Playback Switch", EMU_HANA_DOCK_DAC_PAD3), 668 EMU1010_DAC_PADS("DAC4 Audio Dock 14dB PAD Playback Switch", EMU_HANA_DOCK_DAC_PAD4), 669 EMU1010_DAC_PADS("DAC1 0202 14dB PAD Playback Switch", EMU_HANA_0202_DAC_PAD1), 670 }; 671 672 673 static int snd_emu1010_internal_clock_info(struct snd_kcontrol *kcontrol, 839 return change; 840 } 841 842 static const struct snd_kcontrol_new emu1010_dac_pads_ctl = { 843 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, 844 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE, 845 .info = snd_emu1010_dac_pads_info, 846 .get = snd_emu1010_dac_pads_get, 847 .put = snd_emu1010_dac_pads_put 848 }; 849 850 851 struct snd_emu1010_pads_info { 852 const char * const *adc_ctls, * const *dac_ctls; 853 unsigned n_adc_ctls, n_dac_ctls; 854 }; 855 856 static const struct snd_emu1010_pads_info emu1010_pads_info[] = { 857 { 858 /* rev1 1010 */ 859 .adc_ctls = snd_emu1010_adc_pads, 860 .n_adc_ctls = ARRAY_SIZE(snd_emu1010_adc_pads), 861 .dac_ctls = snd_emu1010_dac_pads, 862 .n_dac_ctls = ARRAY_SIZE(snd_emu1010_dac_pads), 863 }, 864 { 865 /* rev2 1010 */ 866 .adc_ctls = snd_emu1010_adc_pads, 867 .n_adc_ctls = ARRAY_SIZE(snd_emu1010_adc_pads) - 1, 868 .dac_ctls = snd_emu1010_dac_pads, 869 .n_dac_ctls = ARRAY_SIZE(snd_emu1010_dac_pads) - 1, 870 }, 871 { 872 /* 1616(m) cardbus */ 873 .adc_ctls = snd_emu1010_adc_pads + 1, 874 .n_adc_ctls = ARRAY_SIZE(snd_emu1010_adc_pads) - 2, 875 .dac_ctls = snd_emu1010_dac_pads + 1, 876 .n_dac_ctls = ARRAY_SIZE(snd_emu1010_dac_pads) - 2, 877 }, 878 { 879 /* 0404 */ 880 .adc_ctls = NULL, 881 .n_adc_ctls = 0, 882 .dac_ctls = NULL, 883 .n_dac_ctls = 0, 884 }, 885 }; 886 887 static const char * const emu1010_clock_texts[] = { 888 "44100", "48000", "SPDIF", "ADAT", "Dock", "BNC" 889 }; 890 891 static const u8 emu1010_clock_vals[] = { 892 EMU_HANA_WCLOCK_INT_44_1K, 893 EMU_HANA_WCLOCK_INT_48K, 894 EMU_HANA_WCLOCK_HANA_SPDIF_IN, 895 EMU_HANA_WCLOCK_HANA_ADAT_IN, 896 EMU_HANA_WCLOCK_2ND_HANA, 897 EMU_HANA_WCLOCK_SYNC_BNC, 898 }; 899 900 static const char * const emu0404_clock_texts[] = { 901 "44100", "48000", "SPDIF", "BNC" 902 }; 903 904 static const u8 emu0404_clock_vals[] = { 905 EMU_HANA_WCLOCK_INT_44_1K, 906 EMU_HANA_WCLOCK_INT_48K, 907 EMU_HANA_WCLOCK_HANA_SPDIF_IN, 908 EMU_HANA_WCLOCK_SYNC_BNC, 909 }; 910 911 struct snd_emu1010_clock_info { 912 const char * const *texts; 913 const u8 *vals; 914 unsigned num; 915 }; 916 917 static const struct snd_emu1010_clock_info emu1010_clock_info[] = { 918 { 919 // rev1 1010 920 .texts = emu1010_clock_texts, 921 .vals = emu1010_clock_vals, 922 .num = ARRAY_SIZE(emu1010_clock_vals), 923 }, 924 { 925 // rev2 1010 926 .texts = emu1010_clock_texts, 927 .vals = emu1010_clock_vals, 928 .num = ARRAY_SIZE(emu1010_clock_vals) - 1, 929 }, 930 { 931 // 1616(m) CardBus 932 .texts = emu1010_clock_texts, 933 // TODO: determine what is actually available. 934 // Pedantically, *every* source comes from the 2nd FPGA, as the 935 // card itself has no own (digital) audio ports. The user manual 936 // claims that ADAT and S/PDIF clock sources are separate, which 937 // can mean two things: either E-MU mapped the dock's sources to 938 // the primary ones, or they determine the meaning of the "Dock" 939 // source depending on how the ports are actually configured 940 // (which the 2nd FPGA must be doing anyway). 941 .vals = emu1010_clock_vals, 942 .num = ARRAY_SIZE(emu1010_clock_vals), 943 }, 944 { 945 // 0404 946 .texts = emu0404_clock_texts, 947 .vals = emu0404_clock_vals, 948 .num = ARRAY_SIZE(emu0404_clock_vals), 949 }, 950 }; 951 952 static int snd_emu1010_clock_source_info(struct snd_kcontrol *kcontrol, 674 953 struct snd_ctl_elem_info *uinfo) 675 954 { 676 st atic const char * const texts[4] = {677 "44100", "48000", "SPDIF", "ADAT"678 };955 struct snd_emu10k1 *emu = snd_kcontrol_chip(kcontrol); 956 const struct snd_emu1010_clock_info *emu_ci = 957 &emu1010_clock_info[emu1010_idx(emu)]; 679 958 680 return snd_ctl_enum_info(uinfo, 1, 4,texts);681 } 682 683 static int snd_emu1010_ internal_clock_get(struct snd_kcontrol *kcontrol,959 return snd_ctl_enum_info(uinfo, 1, emu_ci->num, emu_ci->texts); 960 } 961 962 static int snd_emu1010_clock_source_get(struct snd_kcontrol *kcontrol, 684 963 struct snd_ctl_elem_value *ucontrol) 685 964 { 686 965 struct snd_emu10k1 *emu = snd_kcontrol_chip(kcontrol); 687 966 688 ucontrol->value.enumerated.item[0] = emu->emu1010. internal_clock;689 return 0; 690 } 691 692 static int snd_emu1010_ internal_clock_put(struct snd_kcontrol *kcontrol,967 ucontrol->value.enumerated.item[0] = emu->emu1010.clock_source; 968 return 0; 969 } 970 971 static int snd_emu1010_clock_source_put(struct snd_kcontrol *kcontrol, 693 972 struct snd_ctl_elem_value *ucontrol) 694 973 { 695 974 struct snd_emu10k1 *emu = snd_kcontrol_chip(kcontrol); 975 const struct snd_emu1010_clock_info *emu_ci = 976 &emu1010_clock_info[emu1010_idx(emu)]; 696 977 unsigned int val; 697 978 int change = 0; 698 979 699 980 val = ucontrol->value.enumerated.item[0] ; 700 /* Limit: uinfo->value.enumerated.items = 4; */ 701 if (val >= 4) 981 if (val >= emu_ci->num) 702 982 return -EINVAL; 703 change = (emu->emu1010.internal_clock != val); 983 spin_lock_irq(&emu->reg_lock); 984 change = (emu->emu1010.clock_source != val); 704 985 if (change) { 705 emu->emu1010.internal_clock = val; 706 switch (val) { 707 case 0: 708 /* 44100 */ 709 /* Mute all */ 710 snd_emu1010_fpga_write(emu, EMU_HANA_UNMUTE, EMU_MUTE ); 711 /* Default fallback clock 48kHz */ 712 snd_emu1010_fpga_write(emu, EMU_HANA_DEFCLOCK, EMU_HANA_DEFCLOCK_44_1K ); 713 /* Word Clock source, Internal 44.1kHz x1 */ 714 snd_emu1010_fpga_write(emu, EMU_HANA_WCLOCK, 715 EMU_HANA_WCLOCK_INT_44_1K | EMU_HANA_WCLOCK_1X ); 716 /* Set LEDs on Audio Dock */ 717 snd_emu1010_fpga_write(emu, EMU_HANA_DOCK_LEDS_2, 718 EMU_HANA_DOCK_LEDS_2_44K | EMU_HANA_DOCK_LEDS_2_LOCK ); 719 /* Allow DLL to settle */ 720 msleep(10); 721 /* Unmute all */ 722 snd_emu1010_fpga_write(emu, EMU_HANA_UNMUTE, EMU_UNMUTE ); 723 break; 724 case 1: 725 /* 48000 */ 726 /* Mute all */ 727 snd_emu1010_fpga_write(emu, EMU_HANA_UNMUTE, EMU_MUTE ); 728 /* Default fallback clock 48kHz */ 729 snd_emu1010_fpga_write(emu, EMU_HANA_DEFCLOCK, EMU_HANA_DEFCLOCK_48K ); 730 /* Word Clock source, Internal 48kHz x1 */ 731 snd_emu1010_fpga_write(emu, EMU_HANA_WCLOCK, 732 EMU_HANA_WCLOCK_INT_48K | EMU_HANA_WCLOCK_1X ); 733 /* Set LEDs on Audio Dock */ 734 snd_emu1010_fpga_write(emu, EMU_HANA_DOCK_LEDS_2, 735 EMU_HANA_DOCK_LEDS_2_48K | EMU_HANA_DOCK_LEDS_2_LOCK ); 736 /* Allow DLL to settle */ 737 msleep(10); 738 /* Unmute all */ 739 snd_emu1010_fpga_write(emu, EMU_HANA_UNMUTE, EMU_UNMUTE ); 740 break; 741 742 case 2: /* Take clock from S/PDIF IN */ 743 /* Mute all */ 744 snd_emu1010_fpga_write(emu, EMU_HANA_UNMUTE, EMU_MUTE ); 745 /* Default fallback clock 48kHz */ 746 snd_emu1010_fpga_write(emu, EMU_HANA_DEFCLOCK, EMU_HANA_DEFCLOCK_48K ); 747 /* Word Clock source, sync to S/PDIF input */ 748 snd_emu1010_fpga_write(emu, EMU_HANA_WCLOCK, 749 EMU_HANA_WCLOCK_HANA_SPDIF_IN | EMU_HANA_WCLOCK_1X ); 750 /* Set LEDs on Audio Dock */ 751 snd_emu1010_fpga_write(emu, EMU_HANA_DOCK_LEDS_2, 752 EMU_HANA_DOCK_LEDS_2_EXT | EMU_HANA_DOCK_LEDS_2_LOCK ); 753 /* FIXME: We should set EMU_HANA_DOCK_LEDS_2_LOCK only when clock signal is present and valid */ 754 /* Allow DLL to settle */ 755 msleep(10); 756 /* Unmute all */ 757 snd_emu1010_fpga_write(emu, EMU_HANA_UNMUTE, EMU_UNMUTE ); 758 break; 759 760 case 3: 761 /* Take clock from ADAT IN */ 762 /* Mute all */ 763 snd_emu1010_fpga_write(emu, EMU_HANA_UNMUTE, EMU_MUTE ); 764 /* Default fallback clock 48kHz */ 765 snd_emu1010_fpga_write(emu, EMU_HANA_DEFCLOCK, EMU_HANA_DEFCLOCK_48K ); 766 /* Word Clock source, sync to ADAT input */ 767 snd_emu1010_fpga_write(emu, EMU_HANA_WCLOCK, 768 EMU_HANA_WCLOCK_HANA_ADAT_IN | EMU_HANA_WCLOCK_1X ); 769 /* Set LEDs on Audio Dock */ 770 snd_emu1010_fpga_write(emu, EMU_HANA_DOCK_LEDS_2, EMU_HANA_DOCK_LEDS_2_EXT | EMU_HANA_DOCK_LEDS_2_LOCK ); 771 /* FIXME: We should set EMU_HANA_DOCK_LEDS_2_LOCK only when clock signal is present and valid */ 772 /* Allow DLL to settle */ 773 msleep(10); 774 /* Unmute all */ 775 snd_emu1010_fpga_write(emu, EMU_HANA_UNMUTE, EMU_UNMUTE ); 776 777 778 break; 779 } 780 } 781 return change; 782 } 783 784 static const struct snd_kcontrol_new snd_emu1010_internal_clock = 785 { 786 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE, 787 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, 788 .name = "Clock Internal Rate", 789 .count = 1, 790 .info = snd_emu1010_internal_clock_info, 791 .get = snd_emu1010_internal_clock_get, 792 .put = snd_emu1010_internal_clock_put 986 emu->emu1010.clock_source = val; 987 emu->emu1010.wclock = emu_ci->vals[val]; 988 snd_emu1010_update_clock(emu); 989 990 snd_emu1010_fpga_write(emu, EMU_HANA_UNMUTE, EMU_MUTE); 991 snd_emu1010_fpga_write(emu, EMU_HANA_WCLOCK, emu->emu1010.wclock); 992 spin_unlock_irq(&emu->reg_lock); 993 994 msleep(10); // Allow DLL to settle 995 snd_emu1010_fpga_write(emu, EMU_HANA_UNMUTE, EMU_UNMUTE); 996 } else { 997 spin_unlock_irq(&emu->reg_lock); 998 } 999 return change; 1000 } 1001 1002 static const struct snd_kcontrol_new snd_emu1010_clock_source = 1003 { 1004 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE, 1005 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, 1006 .name = "Clock Source", 1007 .count = 1, 1008 .info = snd_emu1010_clock_source_info, 1009 .get = snd_emu1010_clock_source_get, 1010 .put = snd_emu1010_clock_source_put 1011 }; 1012 1013 static int snd_emu1010_clock_fallback_info(struct snd_kcontrol *kcontrol, 1014 struct snd_ctl_elem_info *uinfo) 1015 { 1016 static const char * const texts[2] = { 1017 "44100", "48000" 1018 }; 1019 1020 return snd_ctl_enum_info(uinfo, 1, 2, texts); 1021 } 1022 1023 static int snd_emu1010_clock_fallback_get(struct snd_kcontrol *kcontrol, 1024 struct snd_ctl_elem_value *ucontrol) 1025 { 1026 struct snd_emu10k1 *emu = snd_kcontrol_chip(kcontrol); 1027 1028 ucontrol->value.enumerated.item[0] = emu->emu1010.clock_fallback; 1029 return 0; 1030 } 1031 1032 static int snd_emu1010_clock_fallback_put(struct snd_kcontrol *kcontrol, 1033 struct snd_ctl_elem_value *ucontrol) 1034 { 1035 struct snd_emu10k1 *emu = snd_kcontrol_chip(kcontrol); 1036 unsigned int val = ucontrol->value.enumerated.item[0]; 1037 int change; 1038 1039 if (val >= 2) 1040 return -EINVAL; 1041 change = (emu->emu1010.clock_fallback != val); 1042 if (change) { 1043 emu->emu1010.clock_fallback = val; 1044 snd_emu1010_fpga_write(emu, EMU_HANA_DEFCLOCK, 1 - val); 1045 } 1046 return change; 1047 } 1048 1049 static const struct snd_kcontrol_new snd_emu1010_clock_fallback = 1050 { 1051 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE, 1052 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, 1053 .name = "Clock Fallback", 1054 .count = 1, 1055 .info = snd_emu1010_clock_fallback_info, 1056 .get = snd_emu1010_clock_fallback_get, 1057 .put = snd_emu1010_clock_fallback_put 793 1058 }; 794 1059 … … 827 1092 if (change) { 828 1093 emu->emu1010.optical_out = val; 829 tmp = (emu->emu1010.optical_in ? EMU_HANA_OPTICAL_IN_ADAT : 0) |830 (emu->emu1010.optical_out ? EMU_HANA_OPTICAL_OUT_ADAT : 0);1094 tmp = (emu->emu1010.optical_in ? EMU_HANA_OPTICAL_IN_ADAT : EMU_HANA_OPTICAL_IN_SPDIF) | 1095 (emu->emu1010.optical_out ? EMU_HANA_OPTICAL_OUT_ADAT : EMU_HANA_OPTICAL_OUT_SPDIF); 831 1096 snd_emu1010_fpga_write(emu, EMU_HANA_OPTICAL_TYPE, tmp); 832 1097 } … … 878 1143 if (change) { 879 1144 emu->emu1010.optical_in = val; 880 tmp = (emu->emu1010.optical_in ? EMU_HANA_OPTICAL_IN_ADAT : 0) |881 (emu->emu1010.optical_out ? EMU_HANA_OPTICAL_OUT_ADAT : 0);1145 tmp = (emu->emu1010.optical_in ? EMU_HANA_OPTICAL_IN_ADAT : EMU_HANA_OPTICAL_IN_SPDIF) | 1146 (emu->emu1010.optical_out ? EMU_HANA_OPTICAL_OUT_ADAT : EMU_HANA_OPTICAL_OUT_SPDIF); 882 1147 snd_emu1010_fpga_write(emu, EMU_HANA_OPTICAL_TYPE, tmp); 883 1148 } … … 925 1190 unsigned int source_id; 926 1191 unsigned int ngain, ogain; 927 u 32gpio;1192 u16 gpio; 928 1193 int change = 0; 929 unsigned long flags;930 1194 u32 source; 931 1195 /* If the capture source has changed, … … 941 1205 if (change) { 942 1206 snd_emu10k1_i2c_write(emu, ADC_MUX, 0); /* Mute input */ 943 spin_lock_irq save(&emu->emu_lock, flags);944 gpio = in l(emu->port + A_IOCFG);1207 spin_lock_irq(&emu->emu_lock); 1208 gpio = inw(emu->port + A_IOCFG); 945 1209 if (source_id==0) 946 out l(gpio | 0x4, emu->port + A_IOCFG);1210 outw(gpio | 0x4, emu->port + A_IOCFG); 947 1211 else 948 out l(gpio & ~0x4, emu->port + A_IOCFG);949 spin_unlock_irq restore(&emu->emu_lock, flags);1212 outw(gpio & ~0x4, emu->port + A_IOCFG); 1213 spin_unlock_irq(&emu->emu_lock); 950 1214 951 1215 ngain = emu->i2c_capture_volume[source_id][0]; /* Left */ … … 1006 1270 struct snd_emu10k1 *emu = snd_kcontrol_chip(kcontrol); 1007 1271 unsigned int ogain; 1008 unsigned int ngain ;1272 unsigned int ngain0, ngain1; 1009 1273 unsigned int source_id; 1010 1274 int change = 0; … … 1015 1279 if (source_id >= 2) 1016 1280 return -EINVAL; 1281 ngain0 = ucontrol->value.integer.value[0]; 1282 ngain1 = ucontrol->value.integer.value[1]; 1283 if (ngain0 > 0xff) 1284 return -EINVAL; 1285 if (ngain1 > 0xff) 1286 return -EINVAL; 1017 1287 ogain = emu->i2c_capture_volume[source_id][0]; /* Left */ 1018 ngain = ucontrol->value.integer.value[0]; 1019 if (ngain > 0xff) 1020 return 0; 1021 if (ogain != ngain) { 1288 if (ogain != ngain0) { 1022 1289 if (emu->i2c_capture_source == source_id) 1023 snd_emu10k1_i2c_write(emu, ADC_ATTEN_ADCL, ((ngain) & 0xff));1024 emu->i2c_capture_volume[source_id][0] = ngain ;1290 snd_emu10k1_i2c_write(emu, ADC_ATTEN_ADCL, ngain0); 1291 emu->i2c_capture_volume[source_id][0] = ngain0; 1025 1292 change = 1; 1026 1293 } 1027 1294 ogain = emu->i2c_capture_volume[source_id][1]; /* Right */ 1028 ngain = ucontrol->value.integer.value[1]; 1029 if (ngain > 0xff) 1030 return 0; 1031 if (ogain != ngain) { 1295 if (ogain != ngain1) { 1032 1296 if (emu->i2c_capture_source == source_id) 1033 snd_emu10k1_i2c_write(emu, ADC_ATTEN_ADCR, ((ngain) & 0xff));1034 emu->i2c_capture_volume[source_id][1] = ngain ;1297 snd_emu10k1_i2c_write(emu, ADC_ATTEN_ADCR, ngain1); 1298 emu->i2c_capture_volume[source_id][1] = ngain1; 1035 1299 change = 1; 1036 1300 } … … 1039 1303 } 1040 1304 1041 #define I2C_VOLUME(xname,chid) \ 1042 { \ 1043 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ 1044 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | \ 1045 SNDRV_CTL_ELEM_ACCESS_TLV_READ, \ 1046 .info = snd_audigy_i2c_volume_info, \ 1047 .get = snd_audigy_i2c_volume_get, \ 1048 .put = snd_audigy_i2c_volume_put, \ 1049 .tlv = { .p = snd_audigy_db_scale2 }, \ 1050 .private_value = chid \ 1051 } 1052 1053 1054 static const struct snd_kcontrol_new snd_audigy_i2c_volume_ctls[] = { 1055 I2C_VOLUME("Mic Capture Volume", 0), 1056 I2C_VOLUME("Line Capture Volume", 0) 1305 static const struct snd_kcontrol_new i2c_volume_ctl = { 1306 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, 1307 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | 1308 SNDRV_CTL_ELEM_ACCESS_TLV_READ, 1309 .info = snd_audigy_i2c_volume_info, 1310 .get = snd_audigy_i2c_volume_get, 1311 .put = snd_audigy_i2c_volume_put, 1312 .tlv = { .p = snd_audigy_db_scale2 } 1313 }; 1314 1315 static const char * const snd_audigy_i2c_volume_ctls[] = { 1316 "Mic Capture Volume", 1317 "Line Capture Volume", 1057 1318 }; 1058 1319 … … 1070 1331 struct snd_emu10k1 *emu = snd_kcontrol_chip(kcontrol); 1071 1332 unsigned int tmp; 1072 unsigned long flags; 1073 1074 1075 spin_lock_irqsave(&emu->reg_lock, flags); 1333 1076 1334 tmp = snd_emu10k1_ptr_read(emu, A_SPDIF_SAMPLERATE, 0); 1077 1335 switch (tmp & A_SPDIF_RATE_MASK) { … … 1088 1346 ucontrol->value.enumerated.item[0] = 1; 1089 1347 } 1090 spin_unlock_irqrestore(&emu->reg_lock, flags);1091 1348 return 0; 1092 1349 } … … 1098 1355 int change; 1099 1356 unsigned int reg, val, tmp; 1100 unsigned long flags;1101 1357 1102 1358 switch(ucontrol->value.enumerated.item[0]) { … … 1116 1372 1117 1373 1118 spin_lock_irq save(&emu->reg_lock, flags);1374 spin_lock_irq(&emu->reg_lock); 1119 1375 reg = snd_emu10k1_ptr_read(emu, A_SPDIF_SAMPLERATE, 0); 1120 1376 tmp = reg & ~A_SPDIF_RATE_MASK; … … 1123 1379 if (change) 1124 1380 snd_emu10k1_ptr_write(emu, A_SPDIF_SAMPLERATE, 0, tmp); 1125 spin_unlock_irq restore(&emu->reg_lock, flags);1381 spin_unlock_irq(&emu->reg_lock); 1126 1382 return change; 1127 1383 } … … 1146 1402 int change; 1147 1403 unsigned int val; 1148 unsigned long flags;1149 1404 1150 1405 /* Limit: emu->spdif_bits */ … … 1155 1410 (ucontrol->value.iec958.status[2] << 16) | 1156 1411 (ucontrol->value.iec958.status[3] << 24); 1157 spin_lock_irqsave(&emu->reg_lock, flags);1158 1412 change = val != emu->spdif_bits[idx]; 1159 1413 if (change) { … … 1161 1415 emu->spdif_bits[idx] = val; 1162 1416 } 1163 spin_unlock_irqrestore(&emu->reg_lock, flags);1164 1417 return change; 1165 1418 } … … 1189 1442 { 1190 1443 if (emu->audigy) { 1191 snd_emu10k1_ptr_write (emu, A_FXRT1, voice,1192 snd_emu10k1_compose_audigy_fxrt1(route));1193 snd_emu10k1_ptr_write(emu, A_FXRT2, voice,1194 snd_emu10k1_compose_audigy_fxrt2(route));1444 snd_emu10k1_ptr_write_multiple(emu, voice, 1445 A_FXRT1, snd_emu10k1_compose_audigy_fxrt1(route), 1446 A_FXRT2, snd_emu10k1_compose_audigy_fxrt2(route), 1447 REGLIST_END); 1195 1448 } else { 1196 1449 snd_emu10k1_ptr_write(emu, FXRT, voice, … … 1206 1459 snd_emu10k1_ptr_write(emu, DSL_FXSENDAMOUNT_D, voice, volume[3]); 1207 1460 if (emu->audigy) { 1208 unsigned int val = ((unsigned int)volume[4] << 24) | 1209 ((unsigned int)volume[5] << 16) | 1210 ((unsigned int)volume[6] << 8) | 1211 (unsigned int)volume[7]; 1212 snd_emu10k1_ptr_write(emu, A_SENDAMOUNTS, voice, val); 1461 snd_emu10k1_ptr_write(emu, A_SENDAMOUNTS, voice, 1462 snd_emu10k1_compose_audigy_sendamounts(volume)); 1213 1463 } 1214 1464 } … … 1229 1479 struct snd_ctl_elem_value *ucontrol) 1230 1480 { 1231 unsigned long flags;1232 1481 struct snd_emu10k1 *emu = snd_kcontrol_chip(kcontrol); 1233 1482 struct snd_emu10k1_pcm_mixer *mix = … … 1237 1486 int mask = emu->audigy ? 0x3f : 0x0f; 1238 1487 1239 spin_lock_irqsave(&emu->reg_lock, flags);1240 1488 for (voice = 0; voice < 3; voice++) 1241 1489 for (idx = 0; idx < num_efx; idx++) 1242 1490 ucontrol->value.integer.value[(voice * num_efx) + idx] = 1243 1491 mix->send_routing[voice][idx] & mask; 1244 spin_unlock_irqrestore(&emu->reg_lock, flags);1245 1492 return 0; 1246 1493 } … … 1249 1496 struct snd_ctl_elem_value *ucontrol) 1250 1497 { 1251 unsigned long flags;1252 1498 struct snd_emu10k1 *emu = snd_kcontrol_chip(kcontrol); 1253 1499 struct snd_emu10k1_pcm_mixer *mix = … … 1257 1503 int mask = emu->audigy ? 0x3f : 0x0f; 1258 1504 1259 spin_lock_irq save(&emu->reg_lock, flags);1505 spin_lock_irq(&emu->reg_lock); 1260 1506 for (voice = 0; voice < 3; voice++) 1261 1507 for (idx = 0; idx < num_efx; idx++) { … … 1266 1512 } 1267 1513 } 1268 if (change && mix->epcm ) {1269 if ( mix->epcm->voices[0] && mix->epcm->voices[1]) {1514 if (change && mix->epcm && mix->epcm->voices[0]) { 1515 if (!mix->epcm->voices[0]->last) { 1270 1516 update_emu10k1_fxrt(emu, mix->epcm->voices[0]->number, 1271 1517 &mix->send_routing[1][0]); 1272 update_emu10k1_fxrt(emu, mix->epcm->voices[ 1]->number,1518 update_emu10k1_fxrt(emu, mix->epcm->voices[0]->number + 1, 1273 1519 &mix->send_routing[2][0]); 1274 } else if (mix->epcm->voices[0]){1520 } else { 1275 1521 update_emu10k1_fxrt(emu, mix->epcm->voices[0]->number, 1276 1522 &mix->send_routing[0][0]); 1277 1523 } 1278 1524 } 1279 spin_unlock_irq restore(&emu->reg_lock, flags);1525 spin_unlock_irq(&emu->reg_lock); 1280 1526 return change; 1281 1527 } … … 1305 1551 struct snd_ctl_elem_value *ucontrol) 1306 1552 { 1307 unsigned long flags;1308 1553 struct snd_emu10k1 *emu = snd_kcontrol_chip(kcontrol); 1309 1554 struct snd_emu10k1_pcm_mixer *mix = … … 1312 1557 int num_efx = emu->audigy ? 8 : 4; 1313 1558 1314 spin_lock_irqsave(&emu->reg_lock, flags);1315 1559 for (idx = 0; idx < 3*num_efx; idx++) 1316 1560 ucontrol->value.integer.value[idx] = mix->send_volume[idx/num_efx][idx%num_efx]; 1317 spin_unlock_irqrestore(&emu->reg_lock, flags);1318 1561 return 0; 1319 1562 } … … 1322 1565 struct snd_ctl_elem_value *ucontrol) 1323 1566 { 1324 unsigned long flags;1325 1567 struct snd_emu10k1 *emu = snd_kcontrol_chip(kcontrol); 1326 1568 struct snd_emu10k1_pcm_mixer *mix = … … 1329 1571 int num_efx = emu->audigy ? 8 : 4; 1330 1572 1331 spin_lock_irq save(&emu->reg_lock, flags);1573 spin_lock_irq(&emu->reg_lock); 1332 1574 for (idx = 0; idx < 3*num_efx; idx++) { 1333 1575 val = ucontrol->value.integer.value[idx] & 255; … … 1337 1579 } 1338 1580 } 1339 if (change && mix->epcm ) {1340 if ( mix->epcm->voices[0] && mix->epcm->voices[1]) {1581 if (change && mix->epcm && mix->epcm->voices[0]) { 1582 if (!mix->epcm->voices[0]->last) { 1341 1583 update_emu10k1_send_volume(emu, mix->epcm->voices[0]->number, 1342 1584 &mix->send_volume[1][0]); 1343 update_emu10k1_send_volume(emu, mix->epcm->voices[ 1]->number,1585 update_emu10k1_send_volume(emu, mix->epcm->voices[0]->number + 1, 1344 1586 &mix->send_volume[2][0]); 1345 } else if (mix->epcm->voices[0]){1587 } else { 1346 1588 update_emu10k1_send_volume(emu, mix->epcm->voices[0]->number, 1347 1589 &mix->send_volume[0][0]); 1348 1590 } 1349 1591 } 1350 spin_unlock_irq restore(&emu->reg_lock, flags);1592 spin_unlock_irq(&emu->reg_lock); 1351 1593 return change; 1352 1594 } … … 1368 1610 uinfo->count = 3; 1369 1611 uinfo->value.integer.min = 0; 1370 uinfo->value.integer.max = 0x ffff;1612 uinfo->value.integer.max = 0x1fffd; 1371 1613 return 0; 1372 1614 } … … 1378 1620 struct snd_emu10k1_pcm_mixer *mix = 1379 1621 &emu->pcm_mixer[snd_ctl_get_ioffidx(kcontrol, &ucontrol->id)]; 1380 unsigned long flags;1381 1622 int idx; 1382 1623 1383 spin_lock_irqsave(&emu->reg_lock, flags);1384 1624 for (idx = 0; idx < 3; idx++) 1385 ucontrol->value.integer.value[idx] = mix->attn[idx]; 1386 spin_unlock_irqrestore(&emu->reg_lock, flags); 1625 ucontrol->value.integer.value[idx] = mix->attn[idx] * 0xffffU / 0x8000U; 1387 1626 return 0; 1388 1627 } … … 1391 1630 struct snd_ctl_elem_value *ucontrol) 1392 1631 { 1393 unsigned long flags;1394 1632 struct snd_emu10k1 *emu = snd_kcontrol_chip(kcontrol); 1395 1633 struct snd_emu10k1_pcm_mixer *mix = … … 1397 1635 int change = 0, idx, val; 1398 1636 1399 spin_lock_irq save(&emu->reg_lock, flags);1637 spin_lock_irq(&emu->reg_lock); 1400 1638 for (idx = 0; idx < 3; idx++) { 1401 val = ucontrol->value.integer.value[idx] & 0xffff; 1639 unsigned uval = ucontrol->value.integer.value[idx] & 0x1ffff; 1640 val = uval * 0x8000U / 0xffffU; 1402 1641 if (mix->attn[idx] != val) { 1403 1642 mix->attn[idx] = val; … … 1405 1644 } 1406 1645 } 1407 if (change && mix->epcm ) {1408 if ( mix->epcm->voices[0] && mix->epcm->voices[1]) {1646 if (change && mix->epcm && mix->epcm->voices[0]) { 1647 if (!mix->epcm->voices[0]->last) { 1409 1648 snd_emu10k1_ptr_write(emu, VTFT_VOLUMETARGET, mix->epcm->voices[0]->number, mix->attn[1]); 1410 snd_emu10k1_ptr_write(emu, VTFT_VOLUMETARGET, mix->epcm->voices[ 1]->number, mix->attn[2]);1411 } else if (mix->epcm->voices[0]){1649 snd_emu10k1_ptr_write(emu, VTFT_VOLUMETARGET, mix->epcm->voices[0]->number + 1, mix->attn[2]); 1650 } else { 1412 1651 snd_emu10k1_ptr_write(emu, VTFT_VOLUMETARGET, mix->epcm->voices[0]->number, mix->attn[0]); 1413 1652 } 1414 1653 } 1415 spin_unlock_irq restore(&emu->reg_lock, flags);1654 spin_unlock_irq(&emu->reg_lock); 1416 1655 return change; 1417 1656 } … … 1443 1682 struct snd_ctl_elem_value *ucontrol) 1444 1683 { 1445 unsigned long flags;1446 1684 struct snd_emu10k1 *emu = snd_kcontrol_chip(kcontrol); 1447 1685 struct snd_emu10k1_pcm_mixer *mix = … … 1451 1689 int mask = emu->audigy ? 0x3f : 0x0f; 1452 1690 1453 spin_lock_irqsave(&emu->reg_lock, flags);1454 1691 for (idx = 0; idx < num_efx; idx++) 1455 1692 ucontrol->value.integer.value[idx] = 1456 1693 mix->send_routing[0][idx] & mask; 1457 spin_unlock_irqrestore(&emu->reg_lock, flags);1458 1694 return 0; 1459 1695 } … … 1462 1698 struct snd_ctl_elem_value *ucontrol) 1463 1699 { 1464 unsigned long flags;1465 1700 struct snd_emu10k1 *emu = snd_kcontrol_chip(kcontrol); 1466 1701 int ch = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id); … … 1470 1705 int mask = emu->audigy ? 0x3f : 0x0f; 1471 1706 1472 spin_lock_irq save(&emu->reg_lock, flags);1707 spin_lock_irq(&emu->reg_lock); 1473 1708 for (idx = 0; idx < num_efx; idx++) { 1474 1709 val = ucontrol->value.integer.value[idx] & mask; … … 1485 1720 } 1486 1721 } 1487 spin_unlock_irq restore(&emu->reg_lock, flags);1722 spin_unlock_irq(&emu->reg_lock); 1488 1723 return change; 1489 1724 } … … 1513 1748 struct snd_ctl_elem_value *ucontrol) 1514 1749 { 1515 unsigned long flags;1516 1750 struct snd_emu10k1 *emu = snd_kcontrol_chip(kcontrol); 1517 1751 struct snd_emu10k1_pcm_mixer *mix = … … 1520 1754 int num_efx = emu->audigy ? 8 : 4; 1521 1755 1522 spin_lock_irqsave(&emu->reg_lock, flags);1523 1756 for (idx = 0; idx < num_efx; idx++) 1524 1757 ucontrol->value.integer.value[idx] = mix->send_volume[0][idx]; 1525 spin_unlock_irqrestore(&emu->reg_lock, flags);1526 1758 return 0; 1527 1759 } … … 1530 1762 struct snd_ctl_elem_value *ucontrol) 1531 1763 { 1532 unsigned long flags;1533 1764 struct snd_emu10k1 *emu = snd_kcontrol_chip(kcontrol); 1534 1765 int ch = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id); … … 1537 1768 int num_efx = emu->audigy ? 8 : 4; 1538 1769 1539 spin_lock_irq save(&emu->reg_lock, flags);1770 spin_lock_irq(&emu->reg_lock); 1540 1771 for (idx = 0; idx < num_efx; idx++) { 1541 1772 val = ucontrol->value.integer.value[idx] & 255; … … 1551 1782 } 1552 1783 } 1553 spin_unlock_irq restore(&emu->reg_lock, flags);1784 spin_unlock_irq(&emu->reg_lock); 1554 1785 return change; 1555 1786 } … … 1572 1803 uinfo->count = 1; 1573 1804 uinfo->value.integer.min = 0; 1574 uinfo->value.integer.max = 0x ffff;1805 uinfo->value.integer.max = 0x1fffd; 1575 1806 return 0; 1576 1807 } … … 1582 1813 struct snd_emu10k1_pcm_mixer *mix = 1583 1814 &emu->efx_pcm_mixer[snd_ctl_get_ioffidx(kcontrol, &ucontrol->id)]; 1584 unsigned long flags; 1585 1586 spin_lock_irqsave(&emu->reg_lock, flags); 1587 ucontrol->value.integer.value[0] = mix->attn[0]; 1588 spin_unlock_irqrestore(&emu->reg_lock, flags); 1815 1816 ucontrol->value.integer.value[0] = mix->attn[0] * 0xffffU / 0x8000U; 1589 1817 return 0; 1590 1818 } … … 1593 1821 struct snd_ctl_elem_value *ucontrol) 1594 1822 { 1595 unsigned long flags;1596 1823 struct snd_emu10k1 *emu = snd_kcontrol_chip(kcontrol); 1597 1824 int ch = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id); 1598 1825 struct snd_emu10k1_pcm_mixer *mix = &emu->efx_pcm_mixer[ch]; 1599 1826 int change = 0, val; 1600 1601 spin_lock_irqsave(&emu->reg_lock, flags); 1602 val = ucontrol->value.integer.value[0] & 0xffff; 1827 unsigned uval; 1828 1829 spin_lock_irq(&emu->reg_lock); 1830 uval = ucontrol->value.integer.value[0] & 0x1ffff; 1831 val = uval * 0x8000U / 0xffffU; 1603 1832 if (mix->attn[0] != val) { 1604 1833 mix->attn[0] = val; … … 1610 1839 } 1611 1840 } 1612 spin_unlock_irq restore(&emu->reg_lock, flags);1841 spin_unlock_irq(&emu->reg_lock); 1613 1842 return change; 1614 1843 } … … 1633 1862 1634 1863 if (emu->audigy) 1635 ucontrol->value.integer.value[0] = in l(emu->port + A_IOCFG) & A_IOCFG_GPOUT0 ? 1 : 0;1864 ucontrol->value.integer.value[0] = inw(emu->port + A_IOCFG) & A_IOCFG_GPOUT0 ? 1 : 0; 1636 1865 else 1637 1866 ucontrol->value.integer.value[0] = inl(emu->port + HCFG) & HCFG_GPOUT0 ? 1 : 0; … … 1646 1875 struct snd_ctl_elem_value *ucontrol) 1647 1876 { 1648 unsigned long flags;1649 1877 struct snd_emu10k1 *emu = snd_kcontrol_chip(kcontrol); 1650 1878 unsigned int reg, val, sw; … … 1654 1882 if (emu->card_capabilities->invert_shared_spdif) 1655 1883 sw = !sw; 1656 spin_lock_irq save(&emu->reg_lock, flags);1884 spin_lock_irq(&emu->emu_lock); 1657 1885 if ( emu->card_capabilities->i2c_adc) { 1658 1886 /* Do nothing for Audigy 2 ZS Notebook */ 1659 1887 } else if (emu->audigy) { 1660 reg = in l(emu->port + A_IOCFG);1888 reg = inw(emu->port + A_IOCFG); 1661 1889 val = sw ? A_IOCFG_GPOUT0 : 0; 1662 1890 change = (reg & A_IOCFG_GPOUT0) != val; … … 1664 1892 reg &= ~A_IOCFG_GPOUT0; 1665 1893 reg |= val; 1666 out l(reg | val, emu->port + A_IOCFG);1894 outw(reg | val, emu->port + A_IOCFG); 1667 1895 } 1668 1896 } … … 1675 1903 outl(reg | val, emu->port + HCFG); 1676 1904 } 1677 spin_unlock_irq restore(&emu->reg_lock, flags);1905 spin_unlock_irq(&emu->emu_lock); 1678 1906 return change; 1679 1907 } … … 1755 1983 } 1756 1984 1757 static struct snd_kcontrol *ctl_find(struct snd_card *card, const char *name)1758 {1759 struct snd_ctl_elem_id sid;1760 memset(&sid, 0, sizeof(sid));1761 strcpy(sid.name, name);1762 sid.iface = SNDRV_CTL_ELEM_IFACE_MIXER;1763 return snd_ctl_find_id(card, &sid);1764 }1765 1766 1985 static int rename_ctl(struct snd_card *card, const char *src, const char *dst) 1767 1986 { 1768 struct snd_kcontrol *kctl = ctl_find(card, src);1987 struct snd_kcontrol *kctl = snd_ctl_find_id_mixer(card, src); 1769 1988 if (kctl) { 1770 s trcpy(kctl->id.name, dst);1989 snd_ctl_rename(card, kctl, dst); 1771 1990 return 0; 1772 1991 } … … 1777 1996 int pcm_device, int multi_device) 1778 1997 { 1779 int err , pcm;1998 int err; 1780 1999 struct snd_kcontrol *kctl; 1781 2000 struct snd_card *card = emu->card; … … 2041 2260 return err; 2042 2261 2043 /* initialize the routing and volume table for each pcm playback stream */ 2044 for (pcm = 0; pcm < 32; pcm++) { 2045 struct snd_emu10k1_pcm_mixer *mix; 2046 int v; 2047 2048 mix = &emu->pcm_mixer[pcm]; 2049 mix->epcm = NULL; 2050 2051 for (v = 0; v < 4; v++) 2052 mix->send_routing[0][v] = 2053 mix->send_routing[1][v] = 2054 mix->send_routing[2][v] = v; 2055 2056 memset(&mix->send_volume, 0, sizeof(mix->send_volume)); 2057 mix->send_volume[0][0] = mix->send_volume[0][1] = 2058 mix->send_volume[1][0] = mix->send_volume[2][1] = 255; 2059 2060 mix->attn[0] = mix->attn[1] = mix->attn[2] = 0xffff; 2061 } 2062 2063 /* initialize the routing and volume table for the multichannel playback stream */ 2064 for (pcm = 0; pcm < NUM_EFX_PLAYBACK; pcm++) { 2065 struct snd_emu10k1_pcm_mixer *mix; 2066 int v; 2067 2068 mix = &emu->efx_pcm_mixer[pcm]; 2069 mix->epcm = NULL; 2070 2071 mix->send_routing[0][0] = pcm; 2072 mix->send_routing[0][1] = (pcm == 0) ? 1 : 0; 2073 for (v = 0; v < 2; v++) 2074 mix->send_routing[0][2+v] = 13+v; 2075 if (emu->audigy) 2076 for (v = 0; v < 4; v++) 2077 mix->send_routing[0][4+v] = 60+v; 2078 2079 memset(&mix->send_volume, 0, sizeof(mix->send_volume)); 2080 mix->send_volume[0][0] = 255; 2081 2082 mix->attn[0] = 0xffff; 2083 } 2084 2085 if (! emu->card_capabilities->ecard) { /* FIXME: APS has these controls? */ 2262 if (!emu->card_capabilities->ecard && !emu->card_capabilities->emu_model) { 2086 2263 /* sb live! and audigy */ 2087 2264 kctl = snd_ctl_new1(&snd_emu10k1_spdif_mask_control, emu); … … 2135 2312 } 2136 2313 2137 if (emu->card_capabilities->emu_model == EMU_MODEL_EMU1616) { 2138 /* 1616(m) cardbus */ 2139 int i; 2140 2141 for (i = 0; i < ARRAY_SIZE(snd_emu1616_output_enum_ctls); i++) { 2314 if (emu->card_capabilities->emu_model) { 2315 unsigned i, emu_idx = emu1010_idx(emu); 2316 const struct snd_emu1010_routing_info *emu_ri = 2317 &emu1010_routing_info[emu_idx]; 2318 const struct snd_emu1010_pads_info *emu_pi = &emu1010_pads_info[emu_idx]; 2319 2320 for (i = 0; i < emu_ri->n_ins; i++) 2321 emu->emu1010.input_source[i] = 2322 emu1010_map_source(emu_ri, emu_ri->in_dflts[i]); 2323 for (i = 0; i < emu_ri->n_outs; i++) 2324 emu->emu1010.output_source[i] = 2325 emu1010_map_source(emu_ri, emu_ri->out_dflts[i]); 2326 snd_emu1010_apply_sources(emu); 2327 2328 kctl = emu->ctl_clock_source = snd_ctl_new1(&snd_emu1010_clock_source, emu); 2329 err = snd_ctl_add(card, kctl); 2330 if (err < 0) 2331 return err; 2332 err = snd_ctl_add(card, 2333 snd_ctl_new1(&snd_emu1010_clock_fallback, emu)); 2334 if (err < 0) 2335 return err; 2336 2337 err = add_ctls(emu, &emu1010_adc_pads_ctl, 2338 emu_pi->adc_ctls, emu_pi->n_adc_ctls); 2339 if (err < 0) 2340 return err; 2341 err = add_ctls(emu, &emu1010_dac_pads_ctl, 2342 emu_pi->dac_ctls, emu_pi->n_dac_ctls); 2343 if (err < 0) 2344 return err; 2345 2346 if (!emu->card_capabilities->no_adat) { 2142 2347 err = snd_ctl_add(card, 2143 snd_ctl_new1(&snd_emu1616_output_enum_ctls[i], 2144 emu)); 2348 snd_ctl_new1(&snd_emu1010_optical_out, emu)); 2349 if (err < 0) 2350 return err; 2351 err = snd_ctl_add(card, 2352 snd_ctl_new1(&snd_emu1010_optical_in, emu)); 2145 2353 if (err < 0) 2146 2354 return err; 2147 2355 } 2148 for (i = 0; i < ARRAY_SIZE(snd_emu1010_input_enum_ctls); i++) { 2149 err = snd_ctl_add(card, 2150 snd_ctl_new1(&snd_emu1010_input_enum_ctls[i], 2151 emu)); 2152 if (err < 0) 2153 return err; 2154 } 2155 for (i = 0; i < ARRAY_SIZE(snd_emu1010_adc_pads) - 2; i++) { 2156 err = snd_ctl_add(card, 2157 snd_ctl_new1(&snd_emu1010_adc_pads[i], emu)); 2158 if (err < 0) 2159 return err; 2160 } 2161 for (i = 0; i < ARRAY_SIZE(snd_emu1010_dac_pads) - 2; i++) { 2162 err = snd_ctl_add(card, 2163 snd_ctl_new1(&snd_emu1010_dac_pads[i], emu)); 2164 if (err < 0) 2165 return err; 2166 } 2167 err = snd_ctl_add(card, 2168 snd_ctl_new1(&snd_emu1010_internal_clock, emu)); 2356 2357 err = add_emu1010_source_mixers(emu); 2169 2358 if (err < 0) 2170 2359 return err; 2171 err = snd_ctl_add(card,2172 snd_ctl_new1(&snd_emu1010_optical_out, emu));2173 if (err < 0)2174 return err;2175 err = snd_ctl_add(card,2176 snd_ctl_new1(&snd_emu1010_optical_in, emu));2177 if (err < 0)2178 return err;2179 2180 } else if (emu->card_capabilities->emu_model) {2181 /* all other e-mu cards for now */2182 int i;2183 2184 for (i = 0; i < ARRAY_SIZE(snd_emu1010_output_enum_ctls); i++) {2185 err = snd_ctl_add(card,2186 snd_ctl_new1(&snd_emu1010_output_enum_ctls[i],2187 emu));2188 if (err < 0)2189 return err;2190 }2191 for (i = 0; i < ARRAY_SIZE(snd_emu1010_input_enum_ctls); i++) {2192 err = snd_ctl_add(card,2193 snd_ctl_new1(&snd_emu1010_input_enum_ctls[i],2194 emu));2195 if (err < 0)2196 return err;2197 }2198 for (i = 0; i < ARRAY_SIZE(snd_emu1010_adc_pads); i++) {2199 err = snd_ctl_add(card,2200 snd_ctl_new1(&snd_emu1010_adc_pads[i], emu));2201 if (err < 0)2202 return err;2203 }2204 for (i = 0; i < ARRAY_SIZE(snd_emu1010_dac_pads); i++) {2205 err = snd_ctl_add(card,2206 snd_ctl_new1(&snd_emu1010_dac_pads[i], emu));2207 if (err < 0)2208 return err;2209 }2210 err = snd_ctl_add(card,2211 snd_ctl_new1(&snd_emu1010_internal_clock, emu));2212 if (err < 0)2213 return err;2214 err = snd_ctl_add(card,2215 snd_ctl_new1(&snd_emu1010_optical_out, emu));2216 if (err < 0)2217 return err;2218 err = snd_ctl_add(card,2219 snd_ctl_new1(&snd_emu1010_optical_in, emu));2220 if (err < 0)2221 return err;2222 2360 } 2223 2361 2224 2362 if ( emu->card_capabilities->i2c_adc) { 2225 int i;2226 2227 2363 err = snd_ctl_add(card, snd_ctl_new1(&snd_audigy_i2c_capture_source, emu)); 2228 2364 if (err < 0) 2229 2365 return err; 2230 2366 2231 for (i = 0; i < ARRAY_SIZE(snd_audigy_i2c_volume_ctls); i++) {2232 err = snd_ctl_add(card, snd_ctl_new1(&snd_audigy_i2c_volume_ctls[i], emu));2233 if (err < 0)2234 return err;2235 }2367 err = add_ctls(emu, &i2c_volume_ctl, 2368 snd_audigy_i2c_volume_ctls, 2369 ARRAY_SIZE(snd_audigy_i2c_volume_ctls)); 2370 if (err < 0) 2371 return err; 2236 2372 } 2237 2373 -
GPL/trunk/alsa-kernel/pci/emu10k1/emumpu401.c
r703 r772 105 105 static int snd_emu10k1_midi_cmd(struct snd_emu10k1 * emu, struct snd_emu10k1_midi *midi, unsigned char cmd, int ack) 106 106 { 107 unsigned long flags;108 107 int timeout, ok; 109 108 110 spin_lock_irq save(&midi->input_lock, flags);109 spin_lock_irq(&midi->input_lock); 111 110 mpu401_write_data(emu, midi, 0x00); 112 111 /* mpu401_clear_rx(emu, midi); */ … … 127 126 ok = 1; 128 127 } 129 spin_unlock_irq restore(&midi->input_lock, flags);128 spin_unlock_irq(&midi->input_lock); 130 129 if (!ok) { 131 130 dev_err(emu->card->dev, … … 143 142 struct snd_emu10k1 *emu; 144 143 struct snd_emu10k1_midi *midi = (struct snd_emu10k1_midi *)substream->rmidi->private_data; 145 unsigned long flags;146 144 147 145 emu = midi->emu; 148 146 if (snd_BUG_ON(!emu)) 149 147 return -ENXIO; 150 spin_lock_irq save(&midi->open_lock, flags);148 spin_lock_irq(&midi->open_lock); 151 149 midi->midi_mode |= EMU10K1_MIDI_MODE_INPUT; 152 150 midi->substream_input = substream; 153 151 if (!(midi->midi_mode & EMU10K1_MIDI_MODE_OUTPUT)) { 154 spin_unlock_irq restore(&midi->open_lock, flags);152 spin_unlock_irq(&midi->open_lock); 155 153 if (snd_emu10k1_midi_cmd(emu, midi, MPU401_RESET, 1)) 156 154 goto error_out; … … 158 156 goto error_out; 159 157 } else { 160 spin_unlock_irq restore(&midi->open_lock, flags);158 spin_unlock_irq(&midi->open_lock); 161 159 } 162 160 return 0; … … 170 168 struct snd_emu10k1 *emu; 171 169 struct snd_emu10k1_midi *midi = (struct snd_emu10k1_midi *)substream->rmidi->private_data; 172 unsigned long flags;173 170 174 171 emu = midi->emu; 175 172 if (snd_BUG_ON(!emu)) 176 173 return -ENXIO; 177 spin_lock_irq save(&midi->open_lock, flags);174 spin_lock_irq(&midi->open_lock); 178 175 midi->midi_mode |= EMU10K1_MIDI_MODE_OUTPUT; 179 176 midi->substream_output = substream; 180 177 if (!(midi->midi_mode & EMU10K1_MIDI_MODE_INPUT)) { 181 spin_unlock_irq restore(&midi->open_lock, flags);178 spin_unlock_irq(&midi->open_lock); 182 179 if (snd_emu10k1_midi_cmd(emu, midi, MPU401_RESET, 1)) 183 180 goto error_out; … … 185 182 goto error_out; 186 183 } else { 187 spin_unlock_irq restore(&midi->open_lock, flags);184 spin_unlock_irq(&midi->open_lock); 188 185 } 189 186 return 0; … … 197 194 struct snd_emu10k1 *emu; 198 195 struct snd_emu10k1_midi *midi = (struct snd_emu10k1_midi *)substream->rmidi->private_data; 199 unsigned long flags;200 196 int err = 0; 201 197 … … 203 199 if (snd_BUG_ON(!emu)) 204 200 return -ENXIO; 205 spin_lock_irq save(&midi->open_lock, flags);201 spin_lock_irq(&midi->open_lock); 206 202 snd_emu10k1_intr_disable(emu, midi->rx_enable); 207 203 midi->midi_mode &= ~EMU10K1_MIDI_MODE_INPUT; 208 204 midi->substream_input = NULL; 209 205 if (!(midi->midi_mode & EMU10K1_MIDI_MODE_OUTPUT)) { 210 spin_unlock_irq restore(&midi->open_lock, flags);206 spin_unlock_irq(&midi->open_lock); 211 207 err = snd_emu10k1_midi_cmd(emu, midi, MPU401_RESET, 0); 212 208 } else { 213 spin_unlock_irq restore(&midi->open_lock, flags);209 spin_unlock_irq(&midi->open_lock); 214 210 } 215 211 return err; … … 220 216 struct snd_emu10k1 *emu; 221 217 struct snd_emu10k1_midi *midi = (struct snd_emu10k1_midi *)substream->rmidi->private_data; 222 unsigned long flags;223 218 int err = 0; 224 219 … … 226 221 if (snd_BUG_ON(!emu)) 227 222 return -ENXIO; 228 spin_lock_irq save(&midi->open_lock, flags);223 spin_lock_irq(&midi->open_lock); 229 224 snd_emu10k1_intr_disable(emu, midi->tx_enable); 230 225 midi->midi_mode &= ~EMU10K1_MIDI_MODE_OUTPUT; 231 226 midi->substream_output = NULL; 232 227 if (!(midi->midi_mode & EMU10K1_MIDI_MODE_INPUT)) { 233 spin_unlock_irq restore(&midi->open_lock, flags);228 spin_unlock_irq(&midi->open_lock); 234 229 err = snd_emu10k1_midi_cmd(emu, midi, MPU401_RESET, 0); 235 230 } else { 236 spin_unlock_irq restore(&midi->open_lock, flags);231 spin_unlock_irq(&midi->open_lock); 237 232 } 238 233 return err; … … 257 252 struct snd_emu10k1 *emu; 258 253 struct snd_emu10k1_midi *midi = (struct snd_emu10k1_midi *)substream->rmidi->private_data; 259 unsigned long flags;260 254 261 255 emu = midi->emu; … … 268 262 269 263 /* try to send some amount of bytes here before interrupts */ 270 spin_lock_irq save(&midi->output_lock, flags);264 spin_lock_irq(&midi->output_lock); 271 265 while (max > 0) { 272 266 if (mpu401_output_ready(emu, midi)) { … … 274 268 snd_rawmidi_transmit(substream, &byte, 1) != 1) { 275 269 /* no more data */ 276 spin_unlock_irq restore(&midi->output_lock, flags);270 spin_unlock_irq(&midi->output_lock); 277 271 return; 278 272 } … … 283 277 } 284 278 } 285 spin_unlock_irq restore(&midi->output_lock, flags);279 spin_unlock_irq(&midi->output_lock); 286 280 snd_emu10k1_intr_enable(emu, midi->tx_enable); 287 281 } else { -
GPL/trunk/alsa-kernel/pci/emu10k1/emupcm.c
r703 r772 2 2 /* 3 3 * Copyright (c) by Jaroslav Kysela <perex@perex.cz> 4 * Lee Revell <rlrevell@joe-job.com> 5 * James Courtier-Dutton <James@superbug.co.uk> 6 * Oswald Buddenhagen <oswald.buddenhagen@gmx.de> 4 7 * Creative Labs, Inc. 8 * 5 9 * Routines for control of EMU10K1 chips / PCM routines 6 * Multichannel PCM support Copyright (c) Lee Revell <rlrevell@joe-job.com>7 *8 * BUGS:9 * --10 *11 * TODO:12 * --13 10 */ 14 11 … … 77 74 } 78 75 79 static snd_pcm_uframes_t snd_emu10k1_efx_playback_pointer(struct snd_pcm_substream *substream) 80 { 81 struct snd_emu10k1 *emu = snd_pcm_substream_chip(substream); 82 struct snd_pcm_runtime *runtime = substream->runtime; 83 struct snd_emu10k1_pcm *epcm = runtime->private_data; 84 unsigned int ptr; 85 86 if (!epcm->running) 87 return 0; 88 ptr = snd_emu10k1_ptr_read(emu, CCCA, epcm->voices[0]->number) & 0x00ffffff; 89 ptr += runtime->buffer_size; 90 ptr -= epcm->ccca_start_addr; 91 ptr %= runtime->buffer_size; 92 93 return ptr; 94 } 95 96 static int snd_emu10k1_pcm_channel_alloc(struct snd_emu10k1_pcm * epcm, int voices) 97 { 98 int err, i; 99 100 if (epcm->voices[1] != NULL && voices < 2) { 101 snd_emu10k1_voice_free(epcm->emu, epcm->voices[1]); 102 epcm->voices[1] = NULL; 103 } 104 for (i = 0; i < voices; i++) { 105 if (epcm->voices[i] == NULL) 106 break; 107 } 108 if (i == voices) 109 return 0; /* already allocated */ 110 111 for (i = 0; i < ARRAY_SIZE(epcm->voices); i++) { 76 static void snd_emu10k1_pcm_free_voices(struct snd_emu10k1_pcm *epcm) 77 { 78 for (unsigned i = 0; i < ARRAY_SIZE(epcm->voices); i++) { 112 79 if (epcm->voices[i]) { 113 80 snd_emu10k1_voice_free(epcm->emu, epcm->voices[i]); … … 115 82 } 116 83 } 84 } 85 86 static int snd_emu10k1_pcm_channel_alloc(struct snd_emu10k1_pcm *epcm, 87 int type, int count, int channels) 88 { 89 int err; 90 91 snd_emu10k1_pcm_free_voices(epcm); 92 117 93 err = snd_emu10k1_voice_alloc(epcm->emu, 118 epcm->type == PLAYBACK_EMUVOICE ? EMU10K1_PCM : EMU10K1_EFX, 119 voices, 120 &epcm->voices[0]); 121 94 type, count, channels, 95 epcm, &epcm->voices[0]); 122 96 if (err < 0) 123 97 return err; 124 epcm->voices[0]->epcm = epcm; 125 if (voices > 1) { 126 for (i = 1; i < voices; i++) { 127 epcm->voices[i] = &epcm->emu->voices[epcm->voices[0]->number + i]; 128 epcm->voices[i]->epcm = epcm; 129 } 130 } 98 131 99 if (epcm->extra == NULL) { 100 // The hardware supports only (half-)loop interrupts, so to support an 101 // arbitrary number of periods per buffer, we use an extra voice with a 102 // period-sized loop as the interrupt source. Additionally, the interrupt 103 // timing of the hardware is "suboptimal" and needs some compensation. 132 104 err = snd_emu10k1_voice_alloc(epcm->emu, 133 epcm->type == PLAYBACK_EMUVOICE ? EMU10K1_PCM : EMU10K1_EFX, 134 1, 135 &epcm->extra); 105 type + 1, 1, 1, 106 epcm, &epcm->extra); 136 107 if (err < 0) { 137 108 /* … … 140 111 voices, frame); 141 112 */ 142 for (i = 0; i < voices; i++) { 143 snd_emu10k1_voice_free(epcm->emu, epcm->voices[i]); 144 epcm->voices[i] = NULL; 145 } 113 snd_emu10k1_pcm_free_voices(epcm); 146 114 return err; 147 115 } 148 epcm->extra->epcm = epcm;149 116 epcm->extra->interrupt = snd_emu10k1_pcm_interrupt; 150 117 } 151 return 0; 152 } 153 154 static const unsigned int capture_period_sizes[31] = { 118 119 return 0; 120 } 121 122 // Primes 2-7 and 2^n multiples thereof, up to 16. 123 static const unsigned int efx_capture_channels[] = { 124 1, 2, 3, 4, 5, 6, 7, 8, 10, 12, 14, 16 125 }; 126 127 static const struct snd_pcm_hw_constraint_list hw_constraints_efx_capture_channels = { 128 .count = ARRAY_SIZE(efx_capture_channels), 129 .list = efx_capture_channels, 130 .mask = 0 131 }; 132 133 static const unsigned int capture_buffer_sizes[31] = { 155 134 384, 448, 512, 640, 156 135 384*2, 448*2, 512*2, 640*2, … … 163 142 }; 164 143 165 static const struct snd_pcm_hw_constraint_list hw_constraints_capture_ period_sizes = {144 static const struct snd_pcm_hw_constraint_list hw_constraints_capture_buffer_sizes = { 166 145 .count = 31, 167 .list = capture_ period_sizes,146 .list = capture_buffer_sizes, 168 147 .mask = 0 169 148 }; … … 196 175 } 197 176 177 static const unsigned int audigy_capture_rates[9] = { 178 8000, 11025, 12000, 16000, 22050, 24000, 32000, 44100, 48000 179 }; 180 181 static const struct snd_pcm_hw_constraint_list hw_constraints_audigy_capture_rates = { 182 .count = 9, 183 .list = audigy_capture_rates, 184 .mask = 0 185 }; 186 198 187 static unsigned int snd_emu10k1_audigy_capture_rate_reg(unsigned int rate) 199 188 { … … 201 190 case 8000: return A_ADCCR_SAMPLERATE_8; 202 191 case 11025: return A_ADCCR_SAMPLERATE_11; 203 case 12000: return A_ADCCR_SAMPLERATE_12; /* really supported? */192 case 12000: return A_ADCCR_SAMPLERATE_12; 204 193 case 16000: return ADCCR_SAMPLERATE_16; 205 194 case 22050: return ADCCR_SAMPLERATE_22; … … 212 201 return A_ADCCR_SAMPLERATE_8; 213 202 } 203 } 204 205 static void snd_emu10k1_constrain_capture_rates(struct snd_emu10k1 *emu, 206 struct snd_pcm_runtime *runtime) 207 { 208 if (emu->card_capabilities->emu_model && 209 emu->emu1010.word_clock == 44100) { 210 // This also sets the rate constraint by deleting SNDRV_PCM_RATE_KNOT 211 runtime->hw.rates = SNDRV_PCM_RATE_11025 | \ 212 SNDRV_PCM_RATE_22050 | \ 213 SNDRV_PCM_RATE_44100; 214 runtime->hw.rate_min = 11025; 215 runtime->hw.rate_max = 44100; 216 return; 217 } 218 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, 219 emu->audigy ? &hw_constraints_audigy_capture_rates : 220 &hw_constraints_capture_rates); 221 } 222 223 static void snd_emu1010_constrain_efx_rate(struct snd_emu10k1 *emu, 224 struct snd_pcm_runtime *runtime) 225 { 226 int rate; 227 228 rate = emu->emu1010.word_clock; 229 runtime->hw.rate_min = runtime->hw.rate_max = rate; 230 runtime->hw.rates = snd_pcm_rate_to_rate_bit(rate); 214 231 } 215 232 … … 250 267 } 251 268 252 /* 253 * calculate cache invalidate size 254 * 255 * stereo: channel is stereo 256 * w_16: using 16bit samples 257 * 258 * returns: cache invalidate size in samples 259 */ 260 static inline int emu10k1_ccis(int stereo, int w_16) 261 { 262 if (w_16) { 263 return stereo ? 24 : 26; 264 } else { 265 return stereo ? 24*2 : 26*2; 266 } 269 static u16 emu10k1_send_target_from_amount(u8 amount) 270 { 271 static const u8 shifts[8] = { 4, 4, 5, 6, 7, 8, 9, 10 }; 272 static const u16 offsets[8] = { 0, 0x200, 0x400, 0x800, 0x1000, 0x2000, 0x4000, 0x8000 }; 273 u8 exp; 274 275 if (amount == 0xff) 276 return 0xffff; 277 exp = amount >> 5; 278 return ((amount & 0x1f) << shifts[exp]) + offsets[exp]; 267 279 } 268 280 269 281 static void snd_emu10k1_pcm_init_voice(struct snd_emu10k1 *emu, 270 int master, int extra,271 282 struct snd_emu10k1_voice *evoice, 283 bool w_16, bool stereo, 272 284 unsigned int start_addr, 273 285 unsigned int end_addr, 274 struct snd_emu10k1_pcm_mixer *mix) 275 { 276 struct snd_pcm_substream *substream = evoice->epcm->substream; 277 struct snd_pcm_runtime *runtime = substream->runtime; 278 unsigned int silent_page, tmp; 279 int voice, stereo, w_16; 280 unsigned char send_amount[8]; 281 unsigned char send_routing[8]; 282 unsigned long flags; 283 unsigned int pitch_target; 284 unsigned int ccis; 286 const unsigned char *send_routing, 287 const unsigned char *send_amount) 288 { 289 unsigned int silent_page; 290 int voice; 285 291 286 292 voice = evoice->number; 287 stereo = runtime->channels == 2; 288 w_16 = snd_pcm_format_width(runtime->format) == 16; 289 290 if (!extra && stereo) { 291 start_addr >>= 1; 292 end_addr >>= 1; 293 } 294 if (w_16) { 295 start_addr >>= 1; 296 end_addr >>= 1; 297 } 298 299 spin_lock_irqsave(&emu->reg_lock, flags); 300 301 /* volume parameters */ 302 if (extra) { 303 memset(send_routing, 0, sizeof(send_routing)); 304 send_routing[0] = 0; 305 send_routing[1] = 1; 306 send_routing[2] = 2; 307 send_routing[3] = 3; 308 memset(send_amount, 0, sizeof(send_amount)); 293 294 silent_page = ((unsigned int)emu->silent_page.addr << emu->address_mode) | 295 (emu->address_mode ? MAP_PTI_MASK1 : MAP_PTI_MASK0); 296 snd_emu10k1_ptr_write_multiple(emu, voice, 297 // Not really necessary for the slave, but it doesn't hurt 298 CPF, stereo ? CPF_STEREO_MASK : 0, 299 // Assumption that PT is already 0 so no harm overwriting 300 PTRX, (send_amount[0] << 8) | send_amount[1], 301 // Stereo slaves don't need to have the addresses set, but it doesn't hurt 302 DSL, end_addr | (send_amount[3] << 24), 303 PSST, start_addr | (send_amount[2] << 24), 304 CCCA, emu10k1_select_interprom(evoice->epcm->pitch_target) | 305 (w_16 ? 0 : CCCA_8BITSELECT), 306 // Clear filter delay memory 307 Z1, 0, 308 Z2, 0, 309 // Invalidate maps 310 MAPA, silent_page, 311 MAPB, silent_page, 312 // Disable filter (in conjunction with CCCA_RESONANCE == 0) 313 VTFT, VTFT_FILTERTARGET_MASK, 314 CVCF, CVCF_CURRENTFILTER_MASK, 315 REGLIST_END); 316 // Setup routing 317 if (emu->audigy) { 318 snd_emu10k1_ptr_write_multiple(emu, voice, 319 A_FXRT1, snd_emu10k1_compose_audigy_fxrt1(send_routing), 320 A_FXRT2, snd_emu10k1_compose_audigy_fxrt2(send_routing), 321 A_SENDAMOUNTS, snd_emu10k1_compose_audigy_sendamounts(send_amount), 322 REGLIST_END); 323 for (int i = 0; i < 4; i++) { 324 u32 aml = emu10k1_send_target_from_amount(send_amount[2 * i]); 325 u32 amh = emu10k1_send_target_from_amount(send_amount[2 * i + 1]); 326 snd_emu10k1_ptr_write(emu, A_CSBA + i, voice, (amh << 16) | aml); 327 } 309 328 } else { 310 /* mono, left, right (master voice = left) */311 tmp = stereo ? (master ? 1 : 2) : 0;312 memcpy(send_routing, &mix->send_routing[tmp][0], 8);313 memcpy(send_amount, &mix->send_volume[tmp][0], 8);314 }315 316 ccis = emu10k1_ccis(stereo, w_16);317 318 if (master) {319 evoice->epcm->ccca_start_addr = start_addr + ccis;320 if (extra) {321 start_addr += ccis;322 end_addr += ccis + emu->delay_pcm_irq;323 }324 if (stereo && !extra) {325 snd_emu10k1_ptr_write(emu, CPF, voice, CPF_STEREO_MASK);326 snd_emu10k1_ptr_write(emu, CPF, (voice + 1), CPF_STEREO_MASK);327 } else {328 snd_emu10k1_ptr_write(emu, CPF, voice, 0);329 }330 }331 332 /* setup routing */333 if (emu->audigy) {334 snd_emu10k1_ptr_write(emu, A_FXRT1, voice,335 snd_emu10k1_compose_audigy_fxrt1(send_routing));336 snd_emu10k1_ptr_write(emu, A_FXRT2, voice,337 snd_emu10k1_compose_audigy_fxrt2(send_routing));338 snd_emu10k1_ptr_write(emu, A_SENDAMOUNTS, voice,339 ((unsigned int)send_amount[4] << 24) |340 ((unsigned int)send_amount[5] << 16) |341 ((unsigned int)send_amount[6] << 8) |342 (unsigned int)send_amount[7]);343 } else344 329 snd_emu10k1_ptr_write(emu, FXRT, voice, 345 330 snd_emu10k1_compose_send_routing(send_routing)); 346 /* Stop CA */ 347 /* Assumption that PT is already 0 so no harm overwriting */ 348 snd_emu10k1_ptr_write(emu, PTRX, voice, (send_amount[0] << 8) | send_amount[1]); 349 snd_emu10k1_ptr_write(emu, DSL, voice, end_addr | (send_amount[3] << 24)); 350 snd_emu10k1_ptr_write(emu, PSST, voice, 351 (start_addr + (extra ? emu->delay_pcm_irq : 0)) | 352 (send_amount[2] << 24)); 353 if (emu->card_capabilities->emu_model) 354 pitch_target = PITCH_48000; /* Disable interpolators on emu1010 card */ 355 else 356 pitch_target = emu10k1_calc_pitch_target(runtime->rate); 357 if (extra) 358 snd_emu10k1_ptr_write(emu, CCCA, voice, start_addr | 359 emu10k1_select_interprom(pitch_target) | 360 (w_16 ? 0 : CCCA_8BITSELECT)); 361 else 362 snd_emu10k1_ptr_write(emu, CCCA, voice, (start_addr + ccis) | 363 emu10k1_select_interprom(pitch_target) | 364 (w_16 ? 0 : CCCA_8BITSELECT)); 365 /* Clear filter delay memory */ 366 snd_emu10k1_ptr_write(emu, Z1, voice, 0); 367 snd_emu10k1_ptr_write(emu, Z2, voice, 0); 368 /* invalidate maps */ 369 silent_page = ((unsigned int)emu->silent_page.addr << emu->address_mode) | (emu->address_mode ? MAP_PTI_MASK1 : MAP_PTI_MASK0); 370 snd_emu10k1_ptr_write(emu, MAPA, voice, silent_page); 371 snd_emu10k1_ptr_write(emu, MAPB, voice, silent_page); 372 /* modulation envelope */ 373 snd_emu10k1_ptr_write(emu, CVCF, voice, 0xffff); 374 snd_emu10k1_ptr_write(emu, VTFT, voice, 0xffff); 375 snd_emu10k1_ptr_write(emu, ATKHLDM, voice, 0); 376 snd_emu10k1_ptr_write(emu, DCYSUSM, voice, 0x007f); 377 snd_emu10k1_ptr_write(emu, LFOVAL1, voice, 0x8000); 378 snd_emu10k1_ptr_write(emu, LFOVAL2, voice, 0x8000); 379 snd_emu10k1_ptr_write(emu, FMMOD, voice, 0); 380 snd_emu10k1_ptr_write(emu, TREMFRQ, voice, 0); 381 snd_emu10k1_ptr_write(emu, FM2FRQ2, voice, 0); 382 snd_emu10k1_ptr_write(emu, ENVVAL, voice, 0x8000); 383 /* volume envelope */ 384 snd_emu10k1_ptr_write(emu, ATKHLDV, voice, 0x7f7f); 385 snd_emu10k1_ptr_write(emu, ENVVOL, voice, 0x0000); 386 /* filter envelope */ 387 snd_emu10k1_ptr_write(emu, PEFE_FILTERAMOUNT, voice, 0x7f); 388 /* pitch envelope */ 389 snd_emu10k1_ptr_write(emu, PEFE_PITCHAMOUNT, voice, 0); 390 391 spin_unlock_irqrestore(&emu->reg_lock, flags); 331 } 332 333 emu->voices[voice].dirty = 1; 334 } 335 336 static void snd_emu10k1_pcm_init_voices(struct snd_emu10k1 *emu, 337 struct snd_emu10k1_voice *evoice, 338 bool w_16, bool stereo, 339 unsigned int start_addr, 340 unsigned int end_addr, 341 struct snd_emu10k1_pcm_mixer *mix) 342 { 343 spin_lock_irq(&emu->reg_lock); 344 snd_emu10k1_pcm_init_voice(emu, evoice, w_16, stereo, 345 start_addr, end_addr, 346 &mix->send_routing[stereo][0], 347 &mix->send_volume[stereo][0]); 348 if (stereo) 349 snd_emu10k1_pcm_init_voice(emu, evoice + 1, w_16, true, 350 start_addr, end_addr, 351 &mix->send_routing[2][0], 352 &mix->send_volume[2][0]); 353 spin_unlock_irq(&emu->reg_lock); 354 } 355 356 static void snd_emu10k1_pcm_init_extra_voice(struct snd_emu10k1 *emu, 357 struct snd_emu10k1_voice *evoice, 358 bool w_16, 359 unsigned int start_addr, 360 unsigned int end_addr) 361 { 362 static const unsigned char send_routing[8] = { 0, 1, 2, 3, 4, 5, 6, 7 }; 363 static const unsigned char send_amount[8] = { 0, 0, 0, 0, 0, 0, 0, 0 }; 364 365 snd_emu10k1_pcm_init_voice(emu, evoice, w_16, false, 366 start_addr, end_addr, 367 send_routing, send_amount); 392 368 } 393 369 … … 399 375 struct snd_emu10k1_pcm *epcm = runtime->private_data; 400 376 size_t alloc_size; 377 int type, channels, count; 401 378 int err; 402 379 403 err = snd_emu10k1_pcm_channel_alloc(epcm, params_channels(hw_params)); 380 if (epcm->type == PLAYBACK_EMUVOICE) { 381 type = EMU10K1_PCM; 382 channels = 1; 383 count = params_channels(hw_params); 384 } else { 385 type = EMU10K1_EFX; 386 channels = params_channels(hw_params); 387 count = 1; 388 } 389 err = snd_emu10k1_pcm_channel_alloc(epcm, type, count, channels); 404 390 if (err < 0) 405 391 return err; … … 442 428 epcm->extra = NULL; 443 429 } 444 if (epcm->voices[1]) { 445 snd_emu10k1_voice_free(epcm->emu, epcm->voices[1]); 446 epcm->voices[1] = NULL; 447 } 448 if (epcm->voices[0]) { 449 snd_emu10k1_voice_free(epcm->emu, epcm->voices[0]); 450 epcm->voices[0] = NULL; 451 } 430 snd_emu10k1_pcm_free_voices(epcm); 452 431 if (epcm->memblk) { 453 432 snd_emu10k1_free_pages(emu, epcm->memblk); … … 459 438 } 460 439 461 static int snd_emu10k1_efx_playback_hw_free(struct snd_pcm_substream *substream)462 {463 struct snd_emu10k1 *emu = snd_pcm_substream_chip(substream);464 struct snd_pcm_runtime *runtime = substream->runtime;465 struct snd_emu10k1_pcm *epcm;466 int i;467 468 if (runtime->private_data == NULL)469 return 0;470 epcm = runtime->private_data;471 if (epcm->extra) {472 snd_emu10k1_voice_free(epcm->emu, epcm->extra);473 epcm->extra = NULL;474 }475 for (i = 0; i < NUM_EFX_PLAYBACK; i++) {476 if (epcm->voices[i]) {477 snd_emu10k1_voice_free(epcm->emu, epcm->voices[i]);478 epcm->voices[i] = NULL;479 }480 }481 if (epcm->memblk) {482 snd_emu10k1_free_pages(emu, epcm->memblk);483 epcm->memblk = NULL;484 epcm->start_addr = 0;485 }486 snd_pcm_lib_free_pages(substream);487 return 0;488 }489 490 440 static int snd_emu10k1_playback_prepare(struct snd_pcm_substream *substream) 491 441 { … … 493 443 struct snd_pcm_runtime *runtime = substream->runtime; 494 444 struct snd_emu10k1_pcm *epcm = runtime->private_data; 445 bool w_16 = snd_pcm_format_width(runtime->format) == 16; 446 bool stereo = runtime->channels == 2; 495 447 unsigned int start_addr, end_addr; 496 497 start_addr = epcm->start_addr; 498 end_addr = snd_pcm_lib_period_bytes(substream);499 if ( runtime->channels == 2) {500 start_addr >>= 1;501 end_addr >>=1;502 }503 end_addr += start_addr; 504 s nd_emu10k1_pcm_init_voice(emu, 1, 1, epcm->extra,505 start_addr, end_addr, NULL);506 s tart_addr = epcm->start_addr;507 end_addr = epcm->start_addr + snd_pcm_lib_buffer_bytes(substream);508 s nd_emu10k1_pcm_init_voice(emu, 1, 0, epcm->voices[0],509 start_addr, end_addr,510 &emu->pcm_mixer[substream->number]);511 if (epcm->voices[1])512 snd_emu10k1_pcm_init_voice(emu, 0, 0, epcm->voices[1],513 start_addr, end_addr,514 &emu->pcm_mixer[substream->number]); 448 unsigned int rate; 449 450 rate = runtime->rate; 451 if (emu->card_capabilities->emu_model && 452 emu->emu1010.word_clock == 44100) 453 rate = rate * 480 / 441; 454 epcm->pitch_target = emu10k1_calc_pitch_target(rate); 455 456 start_addr = epcm->start_addr >> w_16; 457 end_addr = start_addr + runtime->period_size; 458 snd_emu10k1_pcm_init_extra_voice(emu, epcm->extra, w_16, 459 start_addr, end_addr); 460 start_addr >>= stereo; 461 epcm->ccca_start_addr = start_addr; 462 end_addr = start_addr + runtime->buffer_size; 463 snd_emu10k1_pcm_init_voices(emu, epcm->voices[0], w_16, stereo, 464 start_addr, end_addr, 465 &emu->pcm_mixer[substream->number]); 466 515 467 return 0; 516 468 } … … 521 473 struct snd_pcm_runtime *runtime = substream->runtime; 522 474 struct snd_emu10k1_pcm *epcm = runtime->private_data; 523 unsigned int start_addr, end_addr; 524 unsigned int channel_size; 525 int i; 526 527 start_addr = epcm->start_addr; 528 end_addr = epcm->start_addr + snd_pcm_lib_buffer_bytes(substream); 529 530 /* 531 * the kX driver leaves some space between voices 532 */ 533 channel_size = ( end_addr - start_addr ) / NUM_EFX_PLAYBACK; 534 535 snd_emu10k1_pcm_init_voice(emu, 1, 1, epcm->extra, 536 start_addr, start_addr + (channel_size / 2), NULL); 537 538 /* only difference with the master voice is we use it for the pointer */ 539 snd_emu10k1_pcm_init_voice(emu, 1, 0, epcm->voices[0], 540 start_addr, start_addr + channel_size, 541 &emu->efx_pcm_mixer[0]); 542 543 start_addr += channel_size; 544 for (i = 1; i < NUM_EFX_PLAYBACK; i++) { 545 snd_emu10k1_pcm_init_voice(emu, 0, 0, epcm->voices[i], 546 start_addr, start_addr + channel_size, 547 &emu->efx_pcm_mixer[i]); 475 unsigned int start_addr; 476 unsigned int extra_size, channel_size; 477 unsigned int i; 478 479 epcm->pitch_target = PITCH_48000; 480 481 start_addr = epcm->start_addr >> 1; // 16-bit voices 482 483 extra_size = runtime->period_size; 484 channel_size = runtime->buffer_size; 485 486 snd_emu10k1_pcm_init_extra_voice(emu, epcm->extra, true, 487 start_addr, start_addr + extra_size); 488 489 epcm->ccca_start_addr = start_addr; 490 for (i = 0; i < runtime->channels; i++) { 491 snd_emu10k1_pcm_init_voices(emu, epcm->voices[i], true, false, 492 start_addr, start_addr + channel_size, 493 &emu->efx_pcm_mixer[i]); 548 494 start_addr += channel_size; 549 495 } … … 562 508 .rate_min = 48000, 563 509 .rate_max = 48000, 564 .channels_min = NUM_EFX_PLAYBACK,510 .channels_min = 1, 565 511 .channels_max = NUM_EFX_PLAYBACK, 566 .buffer_bytes_max = (64*1024), 567 .period_bytes_min = 64, 568 .period_bytes_max = (64*1024), 512 .buffer_bytes_max = (128*1024), 513 .period_bytes_max = (128*1024), 569 514 .periods_min = 2, 570 .periods_max = 2,515 .periods_max = 1024, 571 516 .fifo_size = 0, 572 517 }; … … 586 531 break; 587 532 case CAPTURE_EFX: 533 if (emu->card_capabilities->emu_model) { 534 // The upper 32 16-bit capture voices, two for each of the 16 32-bit channels. 535 // The lower voices are occupied by A_EXTOUT_*_CAP*. 536 epcm->capture_cr_val = 0; 537 epcm->capture_cr_val2 = 0xffffffff >> (32 - runtime->channels * 2); 538 } 588 539 if (emu->audigy) { 589 snd_emu10k1_ptr_write(emu, A_FXWC1, 0, 0); 590 snd_emu10k1_ptr_write(emu, A_FXWC2, 0, 0); 540 snd_emu10k1_ptr_write_multiple(emu, 0, 541 A_FXWC1, 0, 542 A_FXWC2, 0, 543 REGLIST_END); 591 544 } else 592 545 snd_emu10k1_ptr_write(emu, FXWC, 0, 0); … … 599 552 epcm->capture_bs_val = 0; 600 553 for (idx = 0; idx < 31; idx++) { 601 if (capture_ period_sizes[idx] == epcm->capture_bufsize) {554 if (capture_buffer_sizes[idx] == epcm->capture_bufsize) { 602 555 epcm->capture_bs_val = idx + 1; 603 556 break; … … 609 562 } 610 563 if (epcm->type == CAPTURE_AC97ADC) { 564 unsigned rate = runtime->rate; 565 if (!(runtime->hw.rates & SNDRV_PCM_RATE_48000)) 566 rate = rate * 480 / 441; 567 611 568 epcm->capture_cr_val = emu->audigy ? A_ADCCR_LCHANENABLE : ADCCR_LCHANENABLE; 612 569 if (runtime->channels > 1) 613 570 epcm->capture_cr_val |= emu->audigy ? A_ADCCR_RCHANENABLE : ADCCR_RCHANENABLE; 614 571 epcm->capture_cr_val |= emu->audigy ? 615 snd_emu10k1_audigy_capture_rate_reg(runtime->rate) : 616 snd_emu10k1_capture_rate_reg(runtime->rate); 617 } 618 return 0; 619 } 620 621 static void snd_emu10k1_playback_invalidate_cache(struct snd_emu10k1 *emu, int extra, struct snd_emu10k1_voice *evoice) 622 { 623 struct snd_pcm_runtime *runtime; 624 unsigned int voice, stereo, i, ccis, cra = 64, cs, sample; 625 626 if (evoice == NULL) 627 return; 628 runtime = evoice->epcm->substream->runtime; 572 snd_emu10k1_audigy_capture_rate_reg(rate) : 573 snd_emu10k1_capture_rate_reg(rate); 574 } 575 return 0; 576 } 577 578 static void snd_emu10k1_playback_fill_cache(struct snd_emu10k1 *emu, 579 unsigned voice, 580 u32 sample, bool stereo) 581 { 582 u32 ccr; 583 584 // We assume that the cache is resting at this point (i.e., 585 // CCR_CACHEINVALIDSIZE is very small). 586 587 // Clear leading frames. For simplicitly, this does too much, 588 // except for 16-bit stereo. And the interpolator will actually 589 // access them at all only when we're pitch-shifting. 590 for (int i = 0; i < 3; i++) 591 snd_emu10k1_ptr_write(emu, CD0 + i, voice, sample); 592 593 // Fill cache 594 ccr = (64 - 3) << REG_SHIFT(CCR_CACHEINVALIDSIZE); 595 if (stereo) { 596 // The engine goes haywire if CCR_READADDRESS is out of sync 597 snd_emu10k1_ptr_write(emu, CCR, voice + 1, ccr); 598 } 599 snd_emu10k1_ptr_write(emu, CCR, voice, ccr); 600 } 601 602 static void snd_emu10k1_playback_prepare_voices(struct snd_emu10k1 *emu, 603 struct snd_emu10k1_pcm *epcm, 604 bool w_16, bool stereo, 605 int channels) 606 { 607 struct snd_pcm_substream *substream = epcm->substream; 608 struct snd_pcm_runtime *runtime = substream->runtime; 609 unsigned eloop_start = epcm->start_addr >> w_16; 610 unsigned loop_start = eloop_start >> stereo; 611 unsigned eloop_size = runtime->period_size; 612 unsigned loop_size = runtime->buffer_size; 613 u32 sample = w_16 ? 0 : 0x80808080; 614 615 // To make the playback actually start at the 1st frame, 616 // we need to compensate for two circumstances: 617 // - The actual position is delayed by the cache size (64 frames) 618 // - The interpolator is centered around the 4th frame 619 loop_start += (epcm->resume_pos + 64 - 3) % loop_size; 620 for (int i = 0; i < channels; i++) { 621 unsigned voice = epcm->voices[i]->number; 622 snd_emu10k1_ptr_write(emu, CCCA_CURRADDR, voice, loop_start); 623 loop_start += loop_size; 624 snd_emu10k1_playback_fill_cache(emu, voice, sample, stereo); 625 } 626 627 // The interrupt is triggered when CCCA_CURRADDR (CA) wraps around, 628 // which is ahead of the actual playback position, so the interrupt 629 // source needs to be delayed. 630 // 631 // In principle, this wouldn't need to be the cache's entire size - in 632 // practice, CCR_CACHEINVALIDSIZE (CIS) > `fetch threshold` has never 633 // been observed, and assuming 40 _bytes_ should be safe. 634 // 635 // The cache fills are somewhat random, which makes it impossible to 636 // align them with the interrupts. This makes a non-delayed interrupt 637 // source not practical, as the interrupt handler would have to wait 638 // for (CA - CIS) >= period_boundary for every channel in the stream. 639 // 640 // This is why all other (open) drivers for these chips use timer-based 641 // interrupts. 642 // 643 eloop_start += (epcm->resume_pos + eloop_size - 3) % eloop_size; 644 snd_emu10k1_ptr_write(emu, CCCA_CURRADDR, epcm->extra->number, eloop_start); 645 646 // It takes a moment until the cache fills complete, 647 // but the unmuting takes long enough for that. 648 } 649 650 static void snd_emu10k1_playback_commit_volume(struct snd_emu10k1 *emu, 651 struct snd_emu10k1_voice *evoice, 652 unsigned int vattn) 653 { 654 snd_emu10k1_ptr_write_multiple(emu, evoice->number, 655 VTFT, vattn | VTFT_FILTERTARGET_MASK, 656 CVCF, vattn | CVCF_CURRENTFILTER_MASK, 657 REGLIST_END); 658 } 659 660 static void snd_emu10k1_playback_unmute_voice(struct snd_emu10k1 *emu, 661 struct snd_emu10k1_voice *evoice, 662 bool stereo, bool master, 663 struct snd_emu10k1_pcm_mixer *mix) 664 { 665 unsigned int vattn; 666 unsigned int tmp; 667 668 tmp = stereo ? (master ? 1 : 2) : 0; 669 vattn = mix->attn[tmp] << 16; 670 snd_emu10k1_playback_commit_volume(emu, evoice, vattn); 671 } 672 673 static void snd_emu10k1_playback_unmute_voices(struct snd_emu10k1 *emu, 674 struct snd_emu10k1_voice *evoice, 675 bool stereo, 676 struct snd_emu10k1_pcm_mixer *mix) 677 { 678 snd_emu10k1_playback_unmute_voice(emu, evoice, stereo, true, mix); 679 if (stereo) 680 snd_emu10k1_playback_unmute_voice(emu, evoice + 1, true, false, mix); 681 } 682 683 static void snd_emu10k1_playback_mute_voice(struct snd_emu10k1 *emu, 684 struct snd_emu10k1_voice *evoice) 685 { 686 snd_emu10k1_playback_commit_volume(emu, evoice, 0); 687 } 688 689 static void snd_emu10k1_playback_mute_voices(struct snd_emu10k1 *emu, 690 struct snd_emu10k1_voice *evoice, 691 bool stereo) 692 { 693 snd_emu10k1_playback_mute_voice(emu, evoice); 694 if (stereo) 695 snd_emu10k1_playback_mute_voice(emu, evoice + 1); 696 } 697 698 static void snd_emu10k1_playback_commit_pitch(struct snd_emu10k1 *emu, 699 u32 voice, u32 pitch_target) 700 { 701 u32 ptrx = snd_emu10k1_ptr_read(emu, PTRX, voice); 702 u32 cpf = snd_emu10k1_ptr_read(emu, CPF, voice); 703 snd_emu10k1_ptr_write_multiple(emu, voice, 704 PTRX, (ptrx & ~PTRX_PITCHTARGET_MASK) | pitch_target, 705 CPF, (cpf & ~(CPF_CURRENTPITCH_MASK | CPF_FRACADDRESS_MASK)) | pitch_target, 706 REGLIST_END); 707 } 708 709 static void snd_emu10k1_playback_trigger_voice(struct snd_emu10k1 *emu, 710 struct snd_emu10k1_voice *evoice) 711 { 712 unsigned int voice; 713 629 714 voice = evoice->number; 630 stereo = (!extra && runtime->channels == 2); 631 sample = snd_pcm_format_width(runtime->format) == 16 ? 0 : 0x80808080; 632 ccis = emu10k1_ccis(stereo, sample == 0); 633 /* set cs to 2 * number of cache registers beside the invalidated */ 634 cs = (sample == 0) ? (32-ccis) : (64-ccis+1) >> 1; 635 if (cs > 16) cs = 16; 636 for (i = 0; i < cs; i++) { 637 snd_emu10k1_ptr_write(emu, CD0 + i, voice, sample); 638 if (stereo) { 639 snd_emu10k1_ptr_write(emu, CD0 + i, voice + 1, sample); 640 } 641 } 642 /* reset cache */ 643 snd_emu10k1_ptr_write(emu, CCR_CACHEINVALIDSIZE, voice, 0); 644 snd_emu10k1_ptr_write(emu, CCR_READADDRESS, voice, cra); 645 if (stereo) { 646 snd_emu10k1_ptr_write(emu, CCR_CACHEINVALIDSIZE, voice + 1, 0); 647 snd_emu10k1_ptr_write(emu, CCR_READADDRESS, voice + 1, cra); 648 } 649 /* fill cache */ 650 snd_emu10k1_ptr_write(emu, CCR_CACHEINVALIDSIZE, voice, ccis); 651 if (stereo) { 652 snd_emu10k1_ptr_write(emu, CCR_CACHEINVALIDSIZE, voice+1, ccis); 653 } 654 } 655 656 static void snd_emu10k1_playback_prepare_voice(struct snd_emu10k1 *emu, struct snd_emu10k1_voice *evoice, 657 int master, int extra, 658 struct snd_emu10k1_pcm_mixer *mix) 659 { 660 struct snd_pcm_substream *substream; 661 struct snd_pcm_runtime *runtime; 662 unsigned int attn, vattn; 663 unsigned int voice, tmp; 664 665 if (evoice == NULL) /* skip second voice for mono */ 666 return; 667 substream = evoice->epcm->substream; 668 runtime = substream->runtime; 715 snd_emu10k1_playback_commit_pitch(emu, voice, evoice->epcm->pitch_target << 16); 716 } 717 718 static void snd_emu10k1_playback_stop_voice(struct snd_emu10k1 *emu, 719 struct snd_emu10k1_voice *evoice) 720 { 721 unsigned int voice; 722 669 723 voice = evoice->number; 670 671 attn = extra ? 0 : 0x00ff; 672 tmp = runtime->channels == 2 ? (master ? 1 : 2) : 0; 673 vattn = mix != NULL ? (mix->attn[tmp] << 16) : 0; 674 snd_emu10k1_ptr_write(emu, IFATN, voice, attn); 675 snd_emu10k1_ptr_write(emu, VTFT, voice, vattn | 0xffff); 676 snd_emu10k1_ptr_write(emu, CVCF, voice, vattn | 0xffff); 677 snd_emu10k1_ptr_write(emu, DCYSUSV, voice, 0x7f7f); 678 snd_emu10k1_voice_clear_loop_stop(emu, voice); 679 } 680 681 static void snd_emu10k1_playback_trigger_voice(struct snd_emu10k1 *emu, struct snd_emu10k1_voice *evoice, int master, int extra) 682 { 683 struct snd_pcm_substream *substream; 684 struct snd_pcm_runtime *runtime; 685 unsigned int voice, pitch, pitch_target; 686 687 if (evoice == NULL) /* skip second voice for mono */ 688 return; 689 substream = evoice->epcm->substream; 690 runtime = substream->runtime; 691 voice = evoice->number; 692 693 pitch = snd_emu10k1_rate_to_pitch(runtime->rate) >> 8; 694 if (emu->card_capabilities->emu_model) 695 pitch_target = PITCH_48000; /* Disable interpolators on emu1010 card */ 696 else 697 pitch_target = emu10k1_calc_pitch_target(runtime->rate); 698 snd_emu10k1_ptr_write(emu, PTRX_PITCHTARGET, voice, pitch_target); 699 if (master || evoice->epcm->type == PLAYBACK_EFX) 700 snd_emu10k1_ptr_write(emu, CPF_CURRENTPITCH, voice, pitch_target); 701 snd_emu10k1_ptr_write(emu, IP, voice, pitch); 702 if (extra) 703 snd_emu10k1_voice_intr_enable(emu, voice); 704 } 705 706 static void snd_emu10k1_playback_stop_voice(struct snd_emu10k1 *emu, struct snd_emu10k1_voice *evoice) 707 { 708 unsigned int voice; 709 710 if (evoice == NULL) 711 return; 712 voice = evoice->number; 713 snd_emu10k1_voice_intr_disable(emu, voice); 714 snd_emu10k1_ptr_write(emu, PTRX_PITCHTARGET, voice, 0); 715 snd_emu10k1_ptr_write(emu, CPF_CURRENTPITCH, voice, 0); 716 snd_emu10k1_ptr_write(emu, IFATN, voice, 0xffff); 717 snd_emu10k1_ptr_write(emu, VTFT, voice, 0xffff); 718 snd_emu10k1_ptr_write(emu, CVCF, voice, 0xffff); 719 snd_emu10k1_ptr_write(emu, IP, voice, 0); 720 } 721 722 static inline void snd_emu10k1_playback_mangle_extra(struct snd_emu10k1 *emu, 723 struct snd_emu10k1_pcm *epcm, 724 struct snd_pcm_substream *substream, 725 struct snd_pcm_runtime *runtime) 726 { 727 unsigned int ptr, period_pos; 728 729 /* try to sychronize the current position for the interrupt 730 source voice */ 731 period_pos = runtime->status->hw_ptr - runtime->hw_ptr_interrupt; 732 period_pos %= runtime->period_size; 733 ptr = snd_emu10k1_ptr_read(emu, CCCA, epcm->extra->number); 734 ptr &= ~0x00ffffff; 735 ptr |= epcm->ccca_start_addr + period_pos; 736 snd_emu10k1_ptr_write(emu, CCCA, epcm->extra->number, ptr); 724 snd_emu10k1_playback_commit_pitch(emu, voice, 0); 725 } 726 727 static void snd_emu10k1_playback_set_running(struct snd_emu10k1 *emu, 728 struct snd_emu10k1_pcm *epcm) 729 { 730 epcm->running = 1; 731 snd_emu10k1_voice_intr_enable(emu, epcm->extra->number); 732 } 733 734 static void snd_emu10k1_playback_set_stopped(struct snd_emu10k1 *emu, 735 struct snd_emu10k1_pcm *epcm) 736 { 737 snd_emu10k1_voice_intr_disable(emu, epcm->extra->number); 738 epcm->running = 0; 737 739 } 738 740 … … 744 746 struct snd_emu10k1_pcm *epcm = runtime->private_data; 745 747 struct snd_emu10k1_pcm_mixer *mix; 748 bool w_16 = snd_pcm_format_width(runtime->format) == 16; 749 bool stereo = runtime->channels == 2; 746 750 int result = 0; 747 751 … … 754 758 switch (cmd) { 755 759 case SNDRV_PCM_TRIGGER_START: 756 snd_emu10k1_playback_invalidate_cache(emu, 1, epcm->extra); /* do we need this? */ 757 snd_emu10k1_playback_invalidate_cache(emu, 0, epcm->voices[0]); 760 snd_emu10k1_playback_prepare_voices(emu, epcm, w_16, stereo, 1); 758 761 fallthrough; 759 762 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 760 763 case SNDRV_PCM_TRIGGER_RESUME: 761 if (cmd == SNDRV_PCM_TRIGGER_PAUSE_RELEASE)762 snd_emu10k1_playback_mangle_extra(emu, epcm, substream, runtime);763 764 mix = &emu->pcm_mixer[substream->number]; 764 snd_emu10k1_playback_prepare_voice(emu, epcm->voices[0], 1, 0, mix); 765 snd_emu10k1_playback_prepare_voice(emu, epcm->voices[1], 0, 0, mix); 766 snd_emu10k1_playback_prepare_voice(emu, epcm->extra, 1, 1, NULL); 767 snd_emu10k1_playback_trigger_voice(emu, epcm->voices[0], 1, 0); 768 snd_emu10k1_playback_trigger_voice(emu, epcm->voices[1], 0, 0); 769 snd_emu10k1_playback_trigger_voice(emu, epcm->extra, 1, 1); 770 epcm->running = 1; 765 snd_emu10k1_playback_unmute_voices(emu, epcm->voices[0], stereo, mix); 766 snd_emu10k1_playback_set_running(emu, epcm); 767 snd_emu10k1_playback_trigger_voice(emu, epcm->voices[0]); 768 snd_emu10k1_playback_trigger_voice(emu, epcm->extra); 771 769 break; 772 770 case SNDRV_PCM_TRIGGER_STOP: 773 771 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 774 772 case SNDRV_PCM_TRIGGER_SUSPEND: 775 epcm->running = 0;776 773 snd_emu10k1_playback_stop_voice(emu, epcm->voices[0]); 777 snd_emu10k1_playback_stop_voice(emu, epcm->voices[1]);778 774 snd_emu10k1_playback_stop_voice(emu, epcm->extra); 775 snd_emu10k1_playback_set_stopped(emu, epcm); 776 snd_emu10k1_playback_mute_voices(emu, epcm->voices[0], stereo); 779 777 break; 780 778 default: … … 811 809 case CAPTURE_EFX: 812 810 if (emu->audigy) { 813 snd_emu10k1_ptr_write(emu, A_FXWC1, 0, epcm->capture_cr_val); 814 snd_emu10k1_ptr_write(emu, A_FXWC2, 0, epcm->capture_cr_val2); 811 snd_emu10k1_ptr_write_multiple(emu, 0, 812 A_FXWC1, epcm->capture_cr_val, 813 A_FXWC2, epcm->capture_cr_val2, 814 REGLIST_END); 815 815 dev_dbg(emu->card->dev, 816 816 "cr_val=0x%x, cr_val2=0x%x\n", … … 839 839 case CAPTURE_EFX: 840 840 if (emu->audigy) { 841 snd_emu10k1_ptr_write(emu, A_FXWC1, 0, 0); 842 snd_emu10k1_ptr_write(emu, A_FXWC2, 0, 0); 841 snd_emu10k1_ptr_write_multiple(emu, 0, 842 A_FXWC1, 0, 843 A_FXWC2, 0, 844 REGLIST_END); 843 845 } else 844 846 snd_emu10k1_ptr_write(emu, FXWC, 0, 0); … … 860 862 struct snd_pcm_runtime *runtime = substream->runtime; 861 863 struct snd_emu10k1_pcm *epcm = runtime->private_data; 862 unsignedint ptr;864 int ptr; 863 865 864 866 if (!epcm->running) 865 867 return 0; 868 866 869 ptr = snd_emu10k1_ptr_read(emu, CCCA, epcm->voices[0]->number) & 0x00ffffff; 867 #if 0 /* Perex's code */868 ptr += runtime->buffer_size;869 870 ptr -= epcm->ccca_start_addr; 870 ptr %= runtime->buffer_size; 871 #else /* EMU10K1 Open Source code from Creative */ 872 if (ptr < epcm->ccca_start_addr) 873 ptr += runtime->buffer_size - epcm->ccca_start_addr; 874 else { 875 ptr -= epcm->ccca_start_addr; 876 if (ptr >= runtime->buffer_size) 877 ptr -= runtime->buffer_size; 878 } 879 #endif 871 872 // This is the size of the whole cache minus the interpolator read-ahead, 873 // which leads us to the actual playback position. 874 // 875 // The cache is constantly kept mostly filled, so in principle we could 876 // return a more advanced position representing how far the hardware has 877 // already read the buffer, and set runtime->delay accordingly. However, 878 // this would be slightly different for every channel (and remarkably slow 879 // to obtain), so only a fixed worst-case value would be practical. 880 // 881 ptr -= 64 - 3; 882 if (ptr < 0) 883 ptr += runtime->buffer_size; 884 880 885 /* 881 886 dev_dbg(emu->card->dev, … … 887 892 } 888 893 894 static u64 snd_emu10k1_efx_playback_voice_mask(struct snd_emu10k1_pcm *epcm, 895 int channels) 896 { 897 u64 mask = 0; 898 899 for (int i = 0; i < channels; i++) { 900 int voice = epcm->voices[i]->number; 901 mask |= 1ULL << voice; 902 } 903 return mask; 904 } 905 906 static void snd_emu10k1_efx_playback_freeze_voices(struct snd_emu10k1 *emu, 907 struct snd_emu10k1_pcm *epcm, 908 int channels) 909 { 910 for (int i = 0; i < channels; i++) { 911 int voice = epcm->voices[i]->number; 912 snd_emu10k1_ptr_write(emu, CPF_STOP, voice, 1); 913 snd_emu10k1_playback_commit_pitch(emu, voice, PITCH_48000 << 16); 914 } 915 } 916 917 static void snd_emu10k1_efx_playback_unmute_voices(struct snd_emu10k1 *emu, 918 struct snd_emu10k1_pcm *epcm, 919 int channels) 920 { 921 for (int i = 0; i < channels; i++) 922 snd_emu10k1_playback_unmute_voice(emu, epcm->voices[i], false, true, 923 &emu->efx_pcm_mixer[i]); 924 } 925 926 static void snd_emu10k1_efx_playback_stop_voices(struct snd_emu10k1 *emu, 927 struct snd_emu10k1_pcm *epcm, 928 int channels) 929 { 930 for (int i = 0; i < channels; i++) 931 snd_emu10k1_playback_stop_voice(emu, epcm->voices[i]); 932 snd_emu10k1_playback_set_stopped(emu, epcm); 933 934 for (int i = 0; i < channels; i++) 935 snd_emu10k1_playback_mute_voice(emu, epcm->voices[i]); 936 } 889 937 890 938 static int snd_emu10k1_efx_playback_trigger(struct snd_pcm_substream *substream, … … 894 942 struct snd_pcm_runtime *runtime = substream->runtime; 895 943 struct snd_emu10k1_pcm *epcm = runtime->private_data; 896 int i;944 u64 mask; 897 945 int result = 0; 898 946 … … 900 948 switch (cmd) { 901 949 case SNDRV_PCM_TRIGGER_START: 902 /* prepare voices */903 for (i = 0; i < NUM_EFX_PLAYBACK; i++) {904 snd_emu10k1_playback_invalidate_cache(emu, 0, epcm->voices[i]);905 }906 snd_emu10k1_playback_invalidate_cache(emu, 1, epcm->extra);907 fallthrough;908 950 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 909 951 case SNDRV_PCM_TRIGGER_RESUME: 910 snd_emu10k1_playback_prepare_voice(emu, epcm->extra, 1, 1, NULL); 911 snd_emu10k1_playback_prepare_voice(emu, epcm->voices[0], 0, 0, 912 &emu->efx_pcm_mixer[0]); 913 for (i = 1; i < NUM_EFX_PLAYBACK; i++) 914 snd_emu10k1_playback_prepare_voice(emu, epcm->voices[i], 0, 0, 915 &emu->efx_pcm_mixer[i]); 916 snd_emu10k1_playback_trigger_voice(emu, epcm->voices[0], 0, 0); 917 snd_emu10k1_playback_trigger_voice(emu, epcm->extra, 1, 1); 918 for (i = 1; i < NUM_EFX_PLAYBACK; i++) 919 snd_emu10k1_playback_trigger_voice(emu, epcm->voices[i], 0, 0); 920 epcm->running = 1; 952 mask = snd_emu10k1_efx_playback_voice_mask( 953 epcm, runtime->channels); 954 for (int i = 0; i < 10; i++) { 955 // Note that the freeze is not interruptible, so we make no 956 // effort to reset the bits outside the error handling here. 957 snd_emu10k1_voice_set_loop_stop_multiple(emu, mask); 958 snd_emu10k1_efx_playback_freeze_voices( 959 emu, epcm, runtime->channels); 960 snd_emu10k1_playback_prepare_voices( 961 emu, epcm, true, false, runtime->channels); 962 963 // It might seem to make more sense to unmute the voices only after 964 // they have been started, to potentially avoid torturing the speakers 965 // if something goes wrong. However, we cannot unmute atomically, 966 // which means that we'd get some mild artifacts in the regular case. 967 snd_emu10k1_efx_playback_unmute_voices(emu, epcm, runtime->channels); 968 969 snd_emu10k1_playback_set_running(emu, epcm); 970 result = snd_emu10k1_voice_clear_loop_stop_multiple_atomic(emu, mask); 971 if (result == 0) { 972 // The extra voice is allowed to lag a bit 973 snd_emu10k1_playback_trigger_voice(emu, epcm->extra); 974 goto leave; 975 } 976 977 snd_emu10k1_efx_playback_stop_voices( 978 emu, epcm, runtime->channels); 979 980 if (result != -EAGAIN) 981 break; 982 // The sync start can legitimately fail due to NMIs, etc. 983 } 984 snd_emu10k1_voice_clear_loop_stop_multiple(emu, mask); 921 985 break; 922 986 case SNDRV_PCM_TRIGGER_SUSPEND: 923 987 case SNDRV_PCM_TRIGGER_STOP: 924 988 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 925 epcm->running = 0;926 for (i = 0; i < NUM_EFX_PLAYBACK; i++) {927 snd_emu10k1_playback_stop_voice(emu, epcm->voices[i]);928 }929 989 snd_emu10k1_playback_stop_voice(emu, epcm->extra); 990 snd_emu10k1_efx_playback_stop_voices( 991 emu, epcm, runtime->channels); 992 993 epcm->resume_pos = snd_emu10k1_playback_pointer(substream); 930 994 break; 931 995 default: … … 933 997 break; 934 998 } 999 leave: 935 1000 spin_unlock(&emu->reg_lock); 936 1001 return result; … … 972 1037 .channels_max = 2, 973 1038 .buffer_bytes_max = (128*1024), 974 .period_bytes_min = 64,975 1039 .period_bytes_max = (128*1024), 976 .periods_min = 1,1040 .periods_min = 2, 977 1041 .periods_max = 1024, 978 1042 .fifo_size = 0, … … 990 1054 SNDRV_PCM_INFO_MMAP_VALID), 991 1055 .formats = SNDRV_PCM_FMTBIT_S16_LE, 992 .rates = SNDRV_PCM_RATE_8000_48000 ,1056 .rates = SNDRV_PCM_RATE_8000_48000 | SNDRV_PCM_RATE_KNOT, 993 1057 .rate_min = 8000, 994 1058 .rate_max = 48000, … … 1010 1074 SNDRV_PCM_INFO_MMAP_VALID), 1011 1075 .formats = SNDRV_PCM_FMTBIT_S16_LE, 1012 .rates = SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 | 1013 SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 | 1014 SNDRV_PCM_RATE_176400 | SNDRV_PCM_RATE_192000, 1015 .rate_min = 44100, 1016 .rate_max = 192000, 1017 .channels_min = 8, 1018 .channels_max = 8, 1076 .rates = SNDRV_PCM_RATE_48000, 1077 .rate_min = 48000, 1078 .rate_max = 48000, 1079 .channels_min = 1, 1080 .channels_max = 16, 1019 1081 .buffer_bytes_max = (64*1024), 1020 1082 .period_bytes_min = 384, … … 1077 1139 } 1078 1140 1141 static int snd_emu10k1_playback_set_constraints(struct snd_pcm_runtime *runtime) 1142 { 1143 int err; 1144 1145 // The buffer size must be a multiple of the period size, to avoid a 1146 // mismatch between the extra voice and the regular voices. 1147 err = snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS); 1148 if (err < 0) 1149 return err; 1150 // The hardware is typically the cache's size of 64 frames ahead. 1151 // Leave enough time for actually filling up the buffer. 1152 err = snd_pcm_hw_constraint_minmax( 1153 runtime, SNDRV_PCM_HW_PARAM_PERIOD_SIZE, 128, UINT_MAX); 1154 return err; 1155 } 1156 1079 1157 static int snd_emu10k1_efx_playback_open(struct snd_pcm_substream *substream) 1080 1158 { … … 1083 1161 struct snd_emu10k1_pcm_mixer *mix; 1084 1162 struct snd_pcm_runtime *runtime = substream->runtime; 1085 int i ;1163 int i, j, err; 1086 1164 1087 1165 epcm = kzalloc(sizeof(*epcm), GFP_KERNEL); … … 1092 1170 epcm->substream = substream; 1093 1171 1094 emu->pcm_playback_efx_substream = substream;1095 1096 1172 runtime->private_data = epcm; 1097 1173 runtime->private_free = snd_emu10k1_pcm_free_substream; 1098 1174 runtime->hw = snd_emu10k1_efx_playback; 1099 1175 if (emu->card_capabilities->emu_model) 1176 snd_emu1010_constrain_efx_rate(emu, runtime); 1177 err = snd_emu10k1_playback_set_constraints(runtime); 1178 if (err < 0) { 1179 kfree(epcm); 1180 return err; 1181 } 1182 1100 1183 for (i = 0; i < NUM_EFX_PLAYBACK; i++) { 1101 1184 mix = &emu->efx_pcm_mixer[i]; 1102 mix->send_routing[0][0] = i; 1185 for (j = 0; j < 8; j++) 1186 mix->send_routing[0][j] = i + j; 1103 1187 memset(&mix->send_volume, 0, sizeof(mix->send_volume)); 1104 1188 mix->send_volume[0][0] = 255; 1105 mix->attn[0] = 0x ffff;1189 mix->attn[0] = 0x8000; 1106 1190 mix->epcm = epcm; 1107 1191 snd_emu10k1_pcm_efx_mixer_notify(emu, i, 1); … … 1127 1211 runtime->private_free = snd_emu10k1_pcm_free_substream; 1128 1212 runtime->hw = snd_emu10k1_playback; 1129 err = snd_ pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS);1213 err = snd_emu10k1_playback_set_constraints(runtime); 1130 1214 if (err < 0) { 1131 1215 kfree(epcm); 1132 1216 return err; 1133 1217 } 1134 err = snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_BYTES, 256, UINT_MAX); 1135 if (err < 0) { 1136 kfree(epcm); 1137 return err; 1138 } 1139 if (emu->card_capabilities->emu_model && emu->emu1010.internal_clock == 0) 1140 sample_rate = 44100; 1218 if (emu->card_capabilities->emu_model) 1219 sample_rate = emu->emu1010.word_clock; 1141 1220 else 1142 1221 sample_rate = 48000; … … 1147 1226 } 1148 1227 mix = &emu->pcm_mixer[substream->number]; 1149 for (i = 0; i < 4; i++)1228 for (i = 0; i < 8; i++) 1150 1229 mix->send_routing[0][i] = mix->send_routing[1][i] = mix->send_routing[2][i] = i; 1151 1230 memset(&mix->send_volume, 0, sizeof(mix->send_volume)); 1152 1231 mix->send_volume[0][0] = mix->send_volume[0][1] = 1153 1232 mix->send_volume[1][0] = mix->send_volume[2][1] = 255; 1154 mix->attn[0] = mix->attn[1] = mix->attn[2] = 0x ffff;1233 mix->attn[0] = mix->attn[1] = mix->attn[2] = 0x8000; 1155 1234 mix->epcm = epcm; 1156 1235 snd_emu10k1_pcm_mixer_notify(emu, substream->number, 1); … … 1188 1267 runtime->private_free = snd_emu10k1_pcm_free_substream; 1189 1268 runtime->hw = snd_emu10k1_capture; 1269 snd_emu10k1_constrain_capture_rates(emu, runtime); 1270 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES, 1271 &hw_constraints_capture_buffer_sizes); 1190 1272 emu->capture_interrupt = snd_emu10k1_pcm_ac97adc_interrupt; 1191 1273 emu->pcm_capture_substream = substream; 1192 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES, &hw_constraints_capture_period_sizes);1193 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, &hw_constraints_capture_rates);1194 1274 return 0; 1195 1275 } … … 1226 1306 runtime->hw.rates = SNDRV_PCM_RATE_8000; 1227 1307 runtime->hw.rate_min = runtime->hw.rate_max = 8000; 1228 runtime->hw.channels_min = 1; 1308 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES, 1309 &hw_constraints_capture_buffer_sizes); 1229 1310 emu->capture_mic_interrupt = snd_emu10k1_pcm_ac97mic_interrupt; 1230 1311 emu->pcm_capture_mic_substream = substream; 1231 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES, &hw_constraints_capture_period_sizes);1232 1312 return 0; 1233 1313 } … … 1237 1317 struct snd_emu10k1 *emu = snd_pcm_substream_chip(substream); 1238 1318 1239 emu->capture_ interrupt = NULL;1319 emu->capture_mic_interrupt = NULL; 1240 1320 emu->pcm_capture_mic_substream = NULL; 1241 1321 return 0; … … 1248 1328 struct snd_pcm_runtime *runtime = substream->runtime; 1249 1329 int nefx = emu->audigy ? 64 : 32; 1250 int idx ;1330 int idx, err; 1251 1331 1252 1332 epcm = kzalloc(sizeof(*epcm), GFP_KERNEL); … … 1264 1344 substream->runtime->private_free = snd_emu10k1_pcm_free_substream; 1265 1345 runtime->hw = snd_emu10k1_capture_efx; 1266 runtime->hw.rates = SNDRV_PCM_RATE_48000;1267 runtime->hw.rate_min = runtime->hw.rate_max = 48000;1268 spin_lock_irq(&emu->reg_lock);1269 1346 if (emu->card_capabilities->emu_model) { 1270 /* Nb. of channels has been increased to 16 */ 1271 /* TODO 1272 * SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE 1273 * SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 | 1274 * SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 | 1275 * SNDRV_PCM_RATE_176400 | SNDRV_PCM_RATE_192000 1276 * rate_min = 44100, 1277 * rate_max = 192000, 1278 * channels_min = 16, 1279 * channels_max = 16, 1280 * Need to add mixer control to fix sample rate 1281 * 1347 snd_emu1010_constrain_efx_rate(emu, runtime); 1348 /* 1282 1349 * There are 32 mono channels of 16bits each. 1283 * 24bit Audio uses 2x channels over 16bit 1284 * 96kHz uses 2x channels over 48kHz 1285 * 192kHz uses 4x channels over 48kHz 1286 * So, for 48kHz 24bit, one has 16 channels 1287 * for 96kHz 24bit, one has 8 channels 1288 * for 192kHz 24bit, one has 4 channels 1289 * 1350 * 24bit Audio uses 2x channels over 16bit, 1351 * 96kHz uses 2x channels over 48kHz, 1352 * 192kHz uses 4x channels over 48kHz. 1353 * So, for 48kHz 24bit, one has 16 channels, 1354 * for 96kHz 24bit, one has 8 channels, 1355 * for 192kHz 24bit, one has 4 channels. 1356 * 1010rev2 and 1616(m) cards have double that, 1357 * but we don't exceed 16 channels anyway. 1290 1358 */ 1291 #if 11292 switch (emu->emu1010.internal_clock) {1293 case 0:1294 /* For 44.1kHz */1295 runtime->hw.rates = SNDRV_PCM_RATE_44100;1296 runtime->hw.rate_min = runtime->hw.rate_max = 44100;1297 runtime->hw.channels_min =1298 runtime->hw.channels_max = 16;1299 break;1300 case 1:1301 /* For 48kHz */1302 runtime->hw.rates = SNDRV_PCM_RATE_48000;1303 runtime->hw.rate_min = runtime->hw.rate_max = 48000;1304 runtime->hw.channels_min =1305 runtime->hw.channels_max = 16;1306 break;1307 }1308 #endif1309 1359 #if 0 1310 1360 /* For 96kHz */ 1311 runtime->hw.rates = SNDRV_PCM_RATE_96000;1312 runtime->hw.rate_min = runtime->hw.rate_max = 96000;1313 1361 runtime->hw.channels_min = runtime->hw.channels_max = 4; 1314 1362 #endif 1315 1363 #if 0 1316 1364 /* For 192kHz */ 1317 runtime->hw.rates = SNDRV_PCM_RATE_192000;1318 runtime->hw.rate_min = runtime->hw.rate_max = 192000;1319 1365 runtime->hw.channels_min = runtime->hw.channels_max = 2; 1320 1366 #endif 1321 1367 runtime->hw.formats = SNDRV_PCM_FMTBIT_S32_LE; 1322 /* efx_voices_mask[0] is expected to be zero1323 * efx_voices_mask[1] is expected to have 32bits set1324 */1325 1368 } else { 1369 spin_lock_irq(&emu->reg_lock); 1326 1370 runtime->hw.channels_min = runtime->hw.channels_max = 0; 1327 1371 for (idx = 0; idx < nefx; idx++) { … … 1331 1375 } 1332 1376 } 1333 } 1334 epcm->capture_cr_val = emu->efx_voices_mask[0]; 1335 epcm->capture_cr_val2 = emu->efx_voices_mask[1]; 1336 spin_unlock_irq(&emu->reg_lock); 1377 epcm->capture_cr_val = emu->efx_voices_mask[0]; 1378 epcm->capture_cr_val2 = emu->efx_voices_mask[1]; 1379 spin_unlock_irq(&emu->reg_lock); 1380 } 1381 err = snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, 1382 &hw_constraints_efx_capture_channels); 1383 if (err < 0) { 1384 kfree(epcm); 1385 return err; 1386 } 1387 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES, 1388 &hw_constraints_capture_buffer_sizes); 1337 1389 emu->capture_efx_interrupt = snd_emu10k1_pcm_efx_interrupt; 1338 1390 emu->pcm_capture_efx_substream = substream; 1339 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES, &hw_constraints_capture_period_sizes);1340 1391 return 0; 1341 1392 } … … 1345 1396 struct snd_emu10k1 *emu = snd_pcm_substream_chip(substream); 1346 1397 1347 emu->capture_ interrupt = NULL;1398 emu->capture_efx_interrupt = NULL; 1348 1399 emu->pcm_capture_efx_substream = NULL; 1349 1400 return 0; … … 1373 1424 .close = snd_emu10k1_efx_playback_close, 1374 1425 .hw_params = snd_emu10k1_playback_hw_params, 1375 .hw_free = snd_emu10k1_ efx_playback_hw_free,1426 .hw_free = snd_emu10k1_playback_hw_free, 1376 1427 .prepare = snd_emu10k1_efx_playback_prepare, 1377 1428 .trigger = snd_emu10k1_efx_playback_trigger, 1378 .pointer = snd_emu10k1_ efx_playback_pointer,1429 .pointer = snd_emu10k1_playback_pointer, 1379 1430 }; 1380 1431 … … 1488 1539 int idx; 1489 1540 1490 spin_lock_irq(&emu->reg_lock);1491 1541 for (idx = 0; idx < nefx; idx++) 1492 1542 ucontrol->value.integer.value[idx] = (emu->efx_voices_mask[idx / 32] & (1 << (idx % 32))) ? 1 : 0; 1493 spin_unlock_irq(&emu->reg_lock);1494 1543 return 0; 1495 1544 } … … 1500 1549 unsigned int nval[2], bits; 1501 1550 int nefx = emu->audigy ? 64 : 32; 1502 int nefxb = emu->audigy ? 7 : 6;1503 1551 int change, idx; 1504 1552 … … 1509 1557 bits++; 1510 1558 } 1511 1512 for (idx = 0; idx < nefxb; idx++) 1513 if (1 << idx == bits) 1514 break; 1515 1516 if (idx >= nefxb) 1559 1560 if (bits == 9 || bits == 11 || bits == 13 || bits == 15 || bits > 16) 1517 1561 return -EINVAL; 1518 1562 … … 1646 1690 pcm->tram_pos = INITIAL_TRAM_POS(pcm->buffer_size); 1647 1691 pcm->tram_shift = 0; 1648 snd_emu10k1_ptr_write(emu, emu->gpr_base + pcm->gpr_running, 0, 0); /* reset */ 1649 snd_emu10k1_ptr_write(emu, emu->gpr_base + pcm->gpr_trigger, 0, 0); /* reset */ 1650 snd_emu10k1_ptr_write(emu, emu->gpr_base + pcm->gpr_size, 0, runtime->buffer_size); 1651 snd_emu10k1_ptr_write(emu, emu->gpr_base + pcm->gpr_ptr, 0, 0); /* reset ptr number */ 1652 snd_emu10k1_ptr_write(emu, emu->gpr_base + pcm->gpr_count, 0, runtime->period_size); 1653 snd_emu10k1_ptr_write(emu, emu->gpr_base + pcm->gpr_tmpcount, 0, runtime->period_size); 1692 snd_emu10k1_ptr_write_multiple(emu, 0, 1693 emu->gpr_base + pcm->gpr_running, 0, /* reset */ 1694 emu->gpr_base + pcm->gpr_trigger, 0, /* reset */ 1695 emu->gpr_base + pcm->gpr_size, runtime->buffer_size, 1696 emu->gpr_base + pcm->gpr_ptr, 0, /* reset ptr number */ 1697 emu->gpr_base + pcm->gpr_count, runtime->period_size, 1698 emu->gpr_base + pcm->gpr_tmpcount, runtime->period_size, 1699 REGLIST_END); 1654 1700 for (i = 0; i < pcm->channels; i++) 1655 1701 snd_emu10k1_ptr_write(emu, TANKMEMADDRREGBASE + 0x80 + pcm->etram[i], 0, (TANKMEMADDRREG_READ|TANKMEMADDRREG_ALIGN) + i * (runtime->buffer_size / pcm->channels)); … … 1782 1828 int err; 1783 1829 1784 err = snd_pcm_new(emu->card, "emu10k1 efx", device, 8, 1, &pcm);1830 err = snd_pcm_new(emu->card, "emu10k1 efx", device, emu->audigy ? 0 : 8, 1, &pcm); 1785 1831 if (err < 0) 1786 1832 return err; … … 1788 1834 pcm->private_data = emu; 1789 1835 1790 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_emu10k1_fx8010_playback_ops); 1836 if (!emu->audigy) 1837 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_emu10k1_fx8010_playback_ops); 1791 1838 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_emu10k1_capture_efx_ops); 1792 1839 1793 1840 pcm->info_flags = 0; 1794 strcpy(pcm->name, "Multichannel Capture/PT Playback"); 1841 if (emu->audigy) 1842 strcpy(pcm->name, "Multichannel Capture"); 1843 else 1844 strcpy(pcm->name, "Multichannel Capture/PT Playback"); 1795 1845 emu->pcm_efx = pcm; 1796 1846 1797 /* EFX capture - record the "FXBUS2" channels, by default we connect the EXTINs 1798 * to these 1799 */ 1800 1801 /* emu->efx_voices_mask[0] = FXWC_DEFAULTROUTE_C | FXWC_DEFAULTROUTE_A; */ 1802 if (emu->audigy) { 1803 emu->efx_voices_mask[0] = 0; 1804 if (emu->card_capabilities->emu_model) 1805 /* Pavel Hofman - 32 voices will be used for 1806 * capture (write mode) - 1807 * each bit = corresponding voice 1808 */ 1809 emu->efx_voices_mask[1] = 0xffffffff; 1810 else 1847 if (!emu->card_capabilities->emu_model) { 1848 // On Sound Blasters, the DSP code copies the EXTINs to FXBUS2. 1849 // The mask determines which of these and the EXTOUTs the multi- 1850 // channel capture actually records (the channel order is fixed). 1851 if (emu->audigy) { 1852 emu->efx_voices_mask[0] = 0; 1811 1853 emu->efx_voices_mask[1] = 0xffff; 1854 } else { 1855 emu->efx_voices_mask[0] = 0xffff0000; 1856 emu->efx_voices_mask[1] = 0; 1857 } 1858 kctl = snd_ctl_new1(&snd_emu10k1_pcm_efx_voices_mask, emu); 1859 if (!kctl) 1860 return -ENOMEM; 1861 kctl->id.device = device; 1862 err = snd_ctl_add(emu->card, kctl); 1863 if (err < 0) 1864 return err; 1812 1865 } else { 1813 emu->efx_voices_mask[0] = 0xffff0000; 1814 emu->efx_voices_mask[1] = 0; 1815 } 1816 /* For emu1010, the control has to set 32 upper bits (voices) 1817 * out of the 64 bits (voices) to true for the 16-channels capture 1818 * to work correctly. Correct A_FXWC2 initial value (0xffffffff) 1819 * is already defined but the snd_emu10k1_pcm_efx_voices_mask 1820 * control can override this register's value. 1821 */ 1822 kctl = snd_ctl_new1(&snd_emu10k1_pcm_efx_voices_mask, emu); 1823 if (!kctl) 1824 return -ENOMEM; 1825 kctl->id.device = device; 1826 err = snd_ctl_add(emu->card, kctl); 1827 if (err < 0) 1828 return err; 1866 // On E-MU cards, the DSP code copies the P16VINs/EMU32INs to 1867 // FXBUS2. These are already selected & routed by the FPGA, 1868 // so there is no need to apply additional masking. 1869 } 1829 1870 1830 1871 snd_pcm_set_managed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV, &emu->pci->dev, -
GPL/trunk/alsa-kernel/pci/emu10k1/emuproc.c
r679 r772 2 2 /* 3 3 * Copyright (c) by Jaroslav Kysela <perex@perex.cz> 4 * Lee Revell <rlrevell@joe-job.com> 5 * James Courtier-Dutton <James@superbug.co.uk> 6 * Oswald Buddenhagen <oswald.buddenhagen@gmx.de> 4 7 * Creative Labs, Inc. 8 * 5 9 * Routines for control of EMU10K1 chips / proc interface routines 6 *7 * Copyright (c) by James Courtier-Dutton <James@superbug.co.uk>8 * Added EMU 1010 support.9 *10 * BUGS:11 * --12 *13 * TODO:14 * --15 10 */ 16 11 … … 67 62 struct snd_info_buffer *buffer) 68 63 { 69 /* FIXME - output names are in emufx.c too */ 70 static const char * const creative_outs[32] = { 71 /* 00 */ "AC97 Left", 72 /* 01 */ "AC97 Right", 73 /* 02 */ "Optical IEC958 Left", 74 /* 03 */ "Optical IEC958 Right", 75 /* 04 */ "Center", 76 /* 05 */ "LFE", 77 /* 06 */ "Headphone Left", 78 /* 07 */ "Headphone Right", 79 /* 08 */ "Surround Left", 80 /* 09 */ "Surround Right", 81 /* 10 */ "PCM Capture Left", 82 /* 11 */ "PCM Capture Right", 83 /* 12 */ "MIC Capture", 84 /* 13 */ "AC97 Surround Left", 85 /* 14 */ "AC97 Surround Right", 86 /* 15 */ "???", 87 /* 16 */ "???", 88 /* 17 */ "Analog Center", 89 /* 18 */ "Analog LFE", 90 /* 19 */ "???", 91 /* 20 */ "???", 92 /* 21 */ "???", 93 /* 22 */ "???", 94 /* 23 */ "???", 95 /* 24 */ "???", 96 /* 25 */ "???", 97 /* 26 */ "???", 98 /* 27 */ "???", 99 /* 28 */ "???", 100 /* 29 */ "???", 101 /* 30 */ "???", 102 /* 31 */ "???" 103 }; 104 105 static const char * const audigy_outs[64] = { 106 /* 00 */ "Digital Front Left", 107 /* 01 */ "Digital Front Right", 108 /* 02 */ "Digital Center", 109 /* 03 */ "Digital LEF", 110 /* 04 */ "Headphone Left", 111 /* 05 */ "Headphone Right", 112 /* 06 */ "Digital Rear Left", 113 /* 07 */ "Digital Rear Right", 114 /* 08 */ "Front Left", 115 /* 09 */ "Front Right", 116 /* 10 */ "Center", 117 /* 11 */ "LFE", 118 /* 12 */ "???", 119 /* 13 */ "???", 120 /* 14 */ "Rear Left", 121 /* 15 */ "Rear Right", 122 /* 16 */ "AC97 Front Left", 123 /* 17 */ "AC97 Front Right", 124 /* 18 */ "ADC Capture Left", 125 /* 19 */ "ADC Capture Right", 126 /* 20 */ "???", 127 /* 21 */ "???", 128 /* 22 */ "???", 129 /* 23 */ "???", 130 /* 24 */ "???", 131 /* 25 */ "???", 132 /* 26 */ "???", 133 /* 27 */ "???", 134 /* 28 */ "???", 135 /* 29 */ "???", 136 /* 30 */ "???", 137 /* 31 */ "???", 138 /* 32 */ "FXBUS2_0", 139 /* 33 */ "FXBUS2_1", 140 /* 34 */ "FXBUS2_2", 141 /* 35 */ "FXBUS2_3", 142 /* 36 */ "FXBUS2_4", 143 /* 37 */ "FXBUS2_5", 144 /* 38 */ "FXBUS2_6", 145 /* 39 */ "FXBUS2_7", 146 /* 40 */ "FXBUS2_8", 147 /* 41 */ "FXBUS2_9", 148 /* 42 */ "FXBUS2_10", 149 /* 43 */ "FXBUS2_11", 150 /* 44 */ "FXBUS2_12", 151 /* 45 */ "FXBUS2_13", 152 /* 46 */ "FXBUS2_14", 153 /* 47 */ "FXBUS2_15", 154 /* 48 */ "FXBUS2_16", 155 /* 49 */ "FXBUS2_17", 156 /* 50 */ "FXBUS2_18", 157 /* 51 */ "FXBUS2_19", 158 /* 52 */ "FXBUS2_20", 159 /* 53 */ "FXBUS2_21", 160 /* 54 */ "FXBUS2_22", 161 /* 55 */ "FXBUS2_23", 162 /* 56 */ "FXBUS2_24", 163 /* 57 */ "FXBUS2_25", 164 /* 58 */ "FXBUS2_26", 165 /* 59 */ "FXBUS2_27", 166 /* 60 */ "FXBUS2_28", 167 /* 61 */ "FXBUS2_29", 168 /* 62 */ "FXBUS2_30", 169 /* 63 */ "FXBUS2_31" 170 }; 171 172 struct snd_emu10k1 *emu = entry->private_data; 173 unsigned int val, val1; 174 int nefx = emu->audigy ? 64 : 32; 175 const char * const *outputs = emu->audigy ? audigy_outs : creative_outs; 64 struct snd_emu10k1 *emu = entry->private_data; 65 const char * const *inputs = emu->audigy ? 66 snd_emu10k1_audigy_ins : snd_emu10k1_sblive_ins; 67 const char * const *outputs = emu->audigy ? 68 snd_emu10k1_audigy_outs : snd_emu10k1_sblive_outs; 69 unsigned short extin_mask = emu->audigy ? ~0 : emu->fx8010.extin_mask; 70 unsigned short extout_mask = emu->audigy ? ~0 : emu->fx8010.extout_mask; 71 unsigned int val, val1, ptrx, psst, dsl, snda; 72 int nefx = emu->audigy ? 32 : 16; 176 73 int idx; 177 74 178 75 snd_iprintf(buffer, "EMU10K1\n\n"); 179 76 snd_iprintf(buffer, "Card : %s\n", 180 emu->audigy ? "Audigy" : (emu->card_capabilities->ecard ? "EMU APS" : "Creative")); 77 emu->card_capabilities->emu_model ? "E-MU D.A.S." : 78 emu->card_capabilities->ecard ? "E-MU A.P.S." : 79 emu->audigy ? "SB Audigy" : "SB Live!"); 181 80 snd_iprintf(buffer, "Internal TRAM (words) : 0x%x\n", emu->fx8010.itram_size); 182 81 snd_iprintf(buffer, "External TRAM (words) : 0x%x\n", (int)emu->fx8010.etram_pages.bytes / 2); 183 snd_iprintf(buffer, "\n"); 184 snd_iprintf(buffer, " Effect Send Routing:\n");82 83 snd_iprintf(buffer, "\nEffect Send Routing & Amounts:\n"); 185 84 for (idx = 0; idx < NUM_G; idx++) { 186 val = emu->audigy ? 187 snd_emu10k1_ptr_read(emu, A_FXRT1, idx) : 188 snd_emu10k1_ptr_read(emu, FXRT, idx); 189 val1 = emu->audigy ? 190 snd_emu10k1_ptr_read(emu, A_FXRT2, idx) : 191 0; 85 ptrx = snd_emu10k1_ptr_read(emu, PTRX, idx); 86 psst = snd_emu10k1_ptr_read(emu, PSST, idx); 87 dsl = snd_emu10k1_ptr_read(emu, DSL, idx); 192 88 if (emu->audigy) { 193 snd_iprintf(buffer, "Ch%i: A=%i, B=%i, C=%i, D=%i, ", 89 val = snd_emu10k1_ptr_read(emu, A_FXRT1, idx); 90 val1 = snd_emu10k1_ptr_read(emu, A_FXRT2, idx); 91 snda = snd_emu10k1_ptr_read(emu, A_SENDAMOUNTS, idx); 92 snd_iprintf(buffer, "Ch%-2i: A=%2i:%02x, B=%2i:%02x, C=%2i:%02x, D=%2i:%02x, ", 194 93 idx, 195 val & 0x3f, 196 (val >> 8) & 0x3f, 197 (val >> 16) & 0x3f, 198 (val >> 24) & 0x3f );199 snd_iprintf(buffer, "E=% i, F=%i, G=%i, H=%i\n",200 val1 & 0x3f, 201 (val1 >> 8) & 0x3f, 202 (val1 >> 16) & 0x3f, 203 (val1 >> 24) & 0x3f );94 val & 0x3f, REG_VAL_GET(PTRX_FXSENDAMOUNT_A, ptrx), 95 (val >> 8) & 0x3f, REG_VAL_GET(PTRX_FXSENDAMOUNT_B, ptrx), 96 (val >> 16) & 0x3f, REG_VAL_GET(PSST_FXSENDAMOUNT_C, psst), 97 (val >> 24) & 0x3f, REG_VAL_GET(DSL_FXSENDAMOUNT_D, dsl)); 98 snd_iprintf(buffer, "E=%2i:%02x, F=%2i:%02x, G=%2i:%02x, H=%2i:%02x\n", 99 val1 & 0x3f, (snda >> 24) & 0xff, 100 (val1 >> 8) & 0x3f, (snda >> 16) & 0xff, 101 (val1 >> 16) & 0x3f, (snda >> 8) & 0xff, 102 (val1 >> 24) & 0x3f, snda & 0xff); 204 103 } else { 205 snd_iprintf(buffer, "Ch%i: A=%i, B=%i, C=%i, D=%i\n", 104 val = snd_emu10k1_ptr_read(emu, FXRT, idx); 105 snd_iprintf(buffer, "Ch%-2i: A=%2i:%02x, B=%2i:%02x, C=%2i:%02x, D=%2i:%02x\n", 206 106 idx, 207 (val >> 16) & 0x0f, 208 (val >> 20) & 0x0f, 209 (val >> 24) & 0x0f, 210 (val >> 28) & 0x0f); 211 } 212 } 213 snd_iprintf(buffer, "\nCaptured FX Outputs :\n"); 214 for (idx = 0; idx < nefx; idx++) { 215 if (emu->efx_voices_mask[idx/32] & (1 << (idx%32))) 216 snd_iprintf(buffer, " Output %02i [%s]\n", idx, outputs[idx]); 217 } 218 snd_iprintf(buffer, "\nAll FX Outputs :\n"); 219 for (idx = 0; idx < (emu->audigy ? 64 : 32); idx++) 220 snd_iprintf(buffer, " Output %02i [%s]\n", idx, outputs[idx]); 107 (val >> 16) & 0x0f, REG_VAL_GET(PTRX_FXSENDAMOUNT_A, ptrx), 108 (val >> 20) & 0x0f, REG_VAL_GET(PTRX_FXSENDAMOUNT_B, ptrx), 109 (val >> 24) & 0x0f, REG_VAL_GET(PSST_FXSENDAMOUNT_C, psst), 110 (val >> 28) & 0x0f, REG_VAL_GET(DSL_FXSENDAMOUNT_D, dsl)); 111 } 112 } 113 snd_iprintf(buffer, "\nEffect Send Targets:\n"); 114 // Audigy actually has 64, but we don't use them all. 115 for (idx = 0; idx < 32; idx++) { 116 const char *c = snd_emu10k1_fxbus[idx]; 117 if (c) 118 snd_iprintf(buffer, " Channel %02i [%s]\n", idx, c); 119 } 120 if (!emu->card_capabilities->emu_model) { 121 snd_iprintf(buffer, "\nOutput Channels:\n"); 122 for (idx = 0; idx < 32; idx++) 123 if (outputs[idx] && (extout_mask & (1 << idx))) 124 snd_iprintf(buffer, " Channel %02i [%s]\n", idx, outputs[idx]); 125 snd_iprintf(buffer, "\nInput Channels:\n"); 126 for (idx = 0; idx < 16; idx++) 127 if (inputs[idx] && (extin_mask & (1 << idx))) 128 snd_iprintf(buffer, " Channel %02i [%s]\n", idx, inputs[idx]); 129 snd_iprintf(buffer, "\nMultichannel Capture Sources:\n"); 130 for (idx = 0; idx < nefx; idx++) 131 if (emu->efx_voices_mask[0] & (1 << idx)) 132 snd_iprintf(buffer, " Channel %02i [Output: %s]\n", 133 idx, outputs[idx] ? outputs[idx] : "???"); 134 if (emu->audigy) { 135 for (idx = 0; idx < 32; idx++) 136 if (emu->efx_voices_mask[1] & (1 << idx)) 137 snd_iprintf(buffer, " Channel %02i [Input: %s]\n", 138 idx + 32, inputs[idx] ? inputs[idx] : "???"); 139 } else { 140 for (idx = 0; idx < 16; idx++) { 141 if (emu->efx_voices_mask[0] & ((1 << 16) << idx)) { 142 if (emu->card_capabilities->sblive51) { 143 s8 c = snd_emu10k1_sblive51_fxbus2_map[idx]; 144 if (c == -1) 145 snd_iprintf(buffer, " Channel %02i [Output: %s]\n", 146 idx + 16, outputs[idx + 16]); 147 else 148 snd_iprintf(buffer, " Channel %02i [Input: %s]\n", 149 idx + 16, inputs[c]); 150 } else { 151 snd_iprintf(buffer, " Channel %02i [Input: %s]\n", 152 idx + 16, inputs[idx] ? inputs[idx] : "???"); 153 } 154 } 155 } 156 } 157 } 221 158 } 222 159 … … 227 164 u32 value; 228 165 u32 value2; 229 u32 rate;230 166 231 167 if (emu->card_capabilities->emu_model) { 232 snd_emu1010_fpga_read(emu, 0x38, &value); 233 if ((value & 0x1) == 0) { 234 snd_emu1010_fpga_read(emu, 0x2a, &value); 235 snd_emu1010_fpga_read(emu, 0x2b, &value2); 236 rate = 0x1770000 / (((value << 5) | value2)+1); 237 snd_iprintf(buffer, "ADAT Locked : %u\n", rate); 238 } else { 239 snd_iprintf(buffer, "ADAT Unlocked\n"); 240 } 241 snd_emu1010_fpga_read(emu, 0x20, &value); 242 if ((value & 0x4) == 0) { 243 snd_emu1010_fpga_read(emu, 0x28, &value); 244 snd_emu1010_fpga_read(emu, 0x29, &value2); 245 rate = 0x1770000 / (((value << 5) | value2)+1); 246 snd_iprintf(buffer, "SPDIF Locked : %d\n", rate); 247 } else { 248 snd_iprintf(buffer, "SPDIF Unlocked\n"); 249 } 168 // This represents the S/PDIF lock status on 0404b, which is 169 // kinda weird and unhelpful, because monitoring it via IRQ is 170 // impractical (one gets an IRQ flood as long as it is desynced). 171 snd_emu1010_fpga_read(emu, EMU_HANA_IRQ_STATUS, &value); 172 snd_iprintf(buffer, "Lock status 1: %#x\n", value & 0x10); 173 174 // Bit 0x1 in LO being 0 is supposedly for ADAT lock. 175 // The registers are always all zero on 0404b. 176 snd_emu1010_fpga_read(emu, EMU_HANA_LOCK_STS_LO, &value); 177 snd_emu1010_fpga_read(emu, EMU_HANA_LOCK_STS_HI, &value2); 178 snd_iprintf(buffer, "Lock status 2: %#x %#x\n", value, value2); 179 180 snd_iprintf(buffer, "S/PDIF rate: %dHz\n", 181 snd_emu1010_get_raw_rate(emu, EMU_HANA_WCLOCK_HANA_SPDIF_IN)); 182 if (emu->card_capabilities->emu_model != EMU_MODEL_EMU0404) { 183 snd_iprintf(buffer, "ADAT rate: %dHz\n", 184 snd_emu1010_get_raw_rate(emu, EMU_HANA_WCLOCK_HANA_ADAT_IN)); 185 snd_iprintf(buffer, "Dock rate: %dHz\n", 186 snd_emu1010_get_raw_rate(emu, EMU_HANA_WCLOCK_2ND_HANA)); 187 } 188 if (emu->card_capabilities->emu_model == EMU_MODEL_EMU0404 || 189 emu->card_capabilities->emu_model == EMU_MODEL_EMU1010) 190 snd_iprintf(buffer, "BNC rate: %dHz\n", 191 snd_emu1010_get_raw_rate(emu, EMU_HANA_WCLOCK_SYNC_BNC)); 192 193 snd_emu1010_fpga_read(emu, EMU_HANA_SPDIF_MODE, &value); 194 if (value & EMU_HANA_SPDIF_MODE_RX_INVALID) 195 snd_iprintf(buffer, "\nS/PDIF input invalid\n"); 196 else 197 snd_iprintf(buffer, "\nS/PDIF mode: %s%s\n", 198 value & EMU_HANA_SPDIF_MODE_RX_PRO ? "professional" : "consumer", 199 value & EMU_HANA_SPDIF_MODE_RX_NOCOPY ? ", no copy" : ""); 250 200 } else { 251 201 snd_emu10k1_proc_spdif_status(emu, buffer, "CD-ROM S/PDIF In", CDCS, CDSRCS); … … 274 224 } 275 225 276 static void snd_emu10k1_proc_acode_read(struct snd_info_entry *entry, 226 struct emu10k1_reg_entry { 227 unsigned short base, size; 228 const char *name; 229 }; 230 231 static const struct emu10k1_reg_entry sblive_reg_entries[] = { 232 { 0, 0x10, "FXBUS" }, 233 { 0x10, 0x10, "EXTIN" }, 234 { 0x20, 0x10, "EXTOUT" }, 235 { 0x30, 0x10, "FXBUS2" }, 236 { 0x40, 0x20, NULL }, // Constants 237 { 0x100, 0x100, "GPR" }, 238 { 0x200, 0x80, "ITRAM_DATA" }, 239 { 0x280, 0x20, "ETRAM_DATA" }, 240 { 0x300, 0x80, "ITRAM_ADDR" }, 241 { 0x380, 0x20, "ETRAM_ADDR" }, 242 { 0x400, 0, NULL } 243 }; 244 245 static const struct emu10k1_reg_entry audigy_reg_entries[] = { 246 { 0, 0x40, "FXBUS" }, 247 { 0x40, 0x10, "EXTIN" }, 248 { 0x50, 0x10, "P16VIN" }, 249 { 0x60, 0x20, "EXTOUT" }, 250 { 0x80, 0x20, "FXBUS2" }, 251 { 0xa0, 0x10, "EMU32OUTH" }, 252 { 0xb0, 0x10, "EMU32OUTL" }, 253 { 0xc0, 0x20, NULL }, // Constants 254 // This can't be quite right - overlap. 255 //{ 0x100, 0xc0, "ITRAM_CTL" }, 256 //{ 0x1c0, 0x40, "ETRAM_CTL" }, 257 { 0x160, 0x20, "A3_EMU32IN" }, 258 { 0x1e0, 0x20, "A3_EMU32OUT" }, 259 { 0x200, 0xc0, "ITRAM_DATA" }, 260 { 0x2c0, 0x40, "ETRAM_DATA" }, 261 { 0x300, 0xc0, "ITRAM_ADDR" }, 262 { 0x3c0, 0x40, "ETRAM_ADDR" }, 263 { 0x400, 0x200, "GPR" }, 264 { 0x600, 0, NULL } 265 }; 266 267 static const char * const emu10k1_const_entries[] = { 268 "C_00000000", 269 "C_00000001", 270 "C_00000002", 271 "C_00000003", 272 "C_00000004", 273 "C_00000008", 274 "C_00000010", 275 "C_00000020", 276 "C_00000100", 277 "C_00010000", 278 "C_00000800", 279 "C_10000000", 280 "C_20000000", 281 "C_40000000", 282 "C_80000000", 283 "C_7fffffff", 284 "C_ffffffff", 285 "C_fffffffe", 286 "C_c0000000", 287 "C_4f1bbcdc", 288 "C_5a7ef9db", 289 "C_00100000", 290 "GPR_ACCU", 291 "GPR_COND", 292 "GPR_NOISE0", 293 "GPR_NOISE1", 294 "GPR_IRQ", 295 "GPR_DBAC", 296 "GPR_DBACE", 297 "???", 298 }; 299 300 static int disasm_emu10k1_reg(char *buffer, 301 const struct emu10k1_reg_entry *entries, 302 unsigned reg, const char *pfx) 303 { 304 for (int i = 0; ; i++) { 305 unsigned base = entries[i].base; 306 unsigned size = entries[i].size; 307 if (!size) 308 return sprintf(buffer, "%s0x%03x", pfx, reg); 309 if (reg >= base && reg < base + size) { 310 const char *name = entries[i].name; 311 reg -= base; 312 if (name) 313 return sprintf(buffer, "%s%s(%u)", pfx, name, reg); 314 return sprintf(buffer, "%s%s", pfx, emu10k1_const_entries[reg]); 315 } 316 } 317 } 318 319 static int disasm_sblive_reg(char *buffer, unsigned reg, const char *pfx) 320 { 321 return disasm_emu10k1_reg(buffer, sblive_reg_entries, reg, pfx); 322 } 323 324 static int disasm_audigy_reg(char *buffer, unsigned reg, const char *pfx) 325 { 326 return disasm_emu10k1_reg(buffer, audigy_reg_entries, reg, pfx); 327 } 328 329 static void snd_emu10k1_proc_acode_read(struct snd_info_entry *entry, 277 330 struct snd_info_buffer *buffer) 278 331 { 279 332 u32 pc; 280 333 struct snd_emu10k1 *emu = entry->private_data; 334 static const char * const insns[16] = { 335 "MAC0", "MAC1", "MAC2", "MAC3", "MACINT0", "MACINT1", "ACC3", "MACMV", 336 "ANDXOR", "TSTNEG", "LIMITGE", "LIMITLT", "LOG", "EXP", "INTERP", "SKIP", 337 }; 338 static const char spaces[] = " "; 339 const int nspaces = sizeof(spaces) - 1; 281 340 282 341 snd_iprintf(buffer, "FX8010 Instruction List '%s'\n", emu->fx8010.name); … … 284 343 for (pc = 0; pc < (emu->audigy ? 1024 : 512); pc++) { 285 344 u32 low, high; 345 int len; 346 char buf[100]; 347 char *bufp = buf; 286 348 287 349 low = snd_emu10k1_efx_read(emu, pc * 2); 288 350 high = snd_emu10k1_efx_read(emu, pc * 2 + 1); 289 if (emu->audigy) 290 snd_iprintf(buffer, " OP(0x%02x, 0x%03x, 0x%03x, 0x%03x, 0x%03x) /* 0x%04x: 0x%08x%08x */\n", 291 (high >> 24) & 0x0f, 292 (high >> 12) & 0x7ff, 293 (high >> 0) & 0x7ff, 294 (low >> 12) & 0x7ff, 295 (low >> 0) & 0x7ff, 296 pc, 297 high, low); 298 else 299 snd_iprintf(buffer, " OP(0x%02x, 0x%03x, 0x%03x, 0x%03x, 0x%03x) /* 0x%04x: 0x%08x%08x */\n", 300 (high >> 20) & 0x0f, 301 (high >> 10) & 0x3ff, 302 (high >> 0) & 0x3ff, 303 (low >> 10) & 0x3ff, 304 (low >> 0) & 0x3ff, 305 pc, 306 high, low); 351 if (emu->audigy) { 352 bufp += sprintf(bufp, " %-7s ", insns[(high >> 24) & 0x0f]); 353 bufp += disasm_audigy_reg(bufp, (high >> 12) & 0x7ff, ""); 354 bufp += disasm_audigy_reg(bufp, (high >> 0) & 0x7ff, ", "); 355 bufp += disasm_audigy_reg(bufp, (low >> 12) & 0x7ff, ", "); 356 bufp += disasm_audigy_reg(bufp, (low >> 0) & 0x7ff, ", "); 357 } else { 358 bufp += sprintf(bufp, " %-7s ", insns[(high >> 20) & 0x0f]); 359 bufp += disasm_sblive_reg(bufp, (high >> 10) & 0x3ff, ""); 360 bufp += disasm_sblive_reg(bufp, (high >> 0) & 0x3ff, ", "); 361 bufp += disasm_sblive_reg(bufp, (low >> 10) & 0x3ff, ", "); 362 bufp += disasm_sblive_reg(bufp, (low >> 0) & 0x3ff, ", "); 363 } 364 len = (int)(ptrdiff_t)(bufp - buf); 365 snd_iprintf(buffer, "%s %s /* 0x%04x: 0x%08x%08x */\n", 366 buf, &spaces[nspaces - clamp(65 - len, 0, nspaces)], 367 pc, high, low); 307 368 } 308 369 } … … 366 427 struct snd_emu10k1_voice *voice; 367 428 int idx; 368 369 snd_iprintf(buffer, "ch\tuse\tpcm\tefx\tsynth\tmidi\n"); 429 static const char * const types[] = { 430 "Unused", "EFX", "EFX IRQ", "PCM", "PCM IRQ", "Synth" 431 }; 432 //static_assert(ARRAY_SIZE(types) == EMU10K1_NUM_TYPES); 433 434 snd_iprintf(buffer, "ch\tdirty\tlast\tuse\n"); 370 435 for (idx = 0; idx < NUM_G; idx++) { 371 436 voice = &emu->voices[idx]; 372 snd_iprintf(buffer, "%i\t% i\t%i\t%i\t%i\t%i\n",437 snd_iprintf(buffer, "%i\t%u\t%u\t%s\n", 373 438 idx, 374 voice->use, 375 voice->pcm, 376 voice->efx, 377 voice->synth, 378 voice->midi); 439 voice->dirty, 440 voice->last, 441 types[voice->use]); 379 442 } 380 443 } 381 444 382 445 #ifdef CONFIG_SND_DEBUG 446 447 static void snd_emu_proc_emu1010_link_read(struct snd_emu10k1 *emu, 448 struct snd_info_buffer *buffer, 449 u32 dst) 450 { 451 u32 src = snd_emu1010_fpga_link_dst_src_read(emu, dst); 452 snd_iprintf(buffer, "%04x: %04x\n", dst, src); 453 } 454 383 455 static void snd_emu_proc_emu1010_reg_read(struct snd_info_entry *entry, 384 456 struct snd_info_buffer *buffer) … … 391 463 for(i = 0; i < 0x40; i+=1) { 392 464 snd_emu1010_fpga_read(emu, i, &value); 393 snd_iprintf(buffer, "%02X: %08X, %02X\n", i, value, (value >> 8) & 0x7f); 465 snd_iprintf(buffer, "%02x: %02x\n", i, value); 466 } 467 468 snd_iprintf(buffer, "\nEMU1010 Routes:\n\n"); 469 470 for (i = 0; i < 16; i++) // To Alice2/Tina[2] via EMU32 471 snd_emu_proc_emu1010_link_read(emu, buffer, i); 472 if (emu->card_capabilities->emu_model != EMU_MODEL_EMU0404) 473 for (i = 0; i < 32; i++) // To Dock via EDI 474 snd_emu_proc_emu1010_link_read(emu, buffer, 0x100 + i); 475 if (emu->card_capabilities->emu_model != EMU_MODEL_EMU1616) 476 for (i = 0; i < 8; i++) // To Hamoa/local 477 snd_emu_proc_emu1010_link_read(emu, buffer, 0x200 + i); 478 for (i = 0; i < 8; i++) // To Hamoa/Mana/local 479 snd_emu_proc_emu1010_link_read(emu, buffer, 0x300 + i); 480 if (emu->card_capabilities->emu_model == EMU_MODEL_EMU1616) { 481 for (i = 0; i < 16; i++) // To Tina2 via EMU32 482 snd_emu_proc_emu1010_link_read(emu, buffer, 0x400 + i); 483 } else if (emu->card_capabilities->emu_model != EMU_MODEL_EMU0404) { 484 for (i = 0; i < 8; i++) // To Hana ADAT 485 snd_emu_proc_emu1010_link_read(emu, buffer, 0x400 + i); 486 if (emu->card_capabilities->emu_model == EMU_MODEL_EMU1010B) { 487 for (i = 0; i < 16; i++) // To Tina via EMU32 488 snd_emu_proc_emu1010_link_read(emu, buffer, 0x500 + i); 489 } else { 490 // To Alice2 via I2S 491 snd_emu_proc_emu1010_link_read(emu, buffer, 0x500); 492 snd_emu_proc_emu1010_link_read(emu, buffer, 0x501); 493 snd_emu_proc_emu1010_link_read(emu, buffer, 0x600); 494 snd_emu_proc_emu1010_link_read(emu, buffer, 0x601); 495 snd_emu_proc_emu1010_link_read(emu, buffer, 0x700); 496 snd_emu_proc_emu1010_link_read(emu, buffer, 0x701); 497 } 394 498 } 395 499 } … … 400 504 struct snd_emu10k1 *emu = entry->private_data; 401 505 unsigned long value; 402 unsigned long flags;403 506 int i; 404 507 snd_iprintf(buffer, "IO Registers:\n\n"); 405 508 for(i = 0; i < 0x40; i+=4) { 406 spin_lock_irqsave(&emu->emu_lock, flags);407 509 value = inl(emu->port + i); 408 spin_unlock_irqrestore(&emu->emu_lock, flags);409 510 snd_iprintf(buffer, "%02X: %08lX\n", i, value); 410 511 } … … 415 516 { 416 517 struct snd_emu10k1 *emu = entry->private_data; 417 unsigned long flags;418 518 char line[64]; 419 519 u32 reg, val; … … 422 522 continue; 423 523 if (reg < 0x40 && val <= 0xffffffff) { 424 spin_lock_irqsave(&emu->emu_lock, flags);425 524 outl(val, emu->port + (reg & 0xfffffffc)); 426 spin_unlock_irqrestore(&emu->emu_lock, flags);427 525 } 428 526 } … … 434 532 unsigned int chn) 435 533 { 436 unsigned long flags;437 534 unsigned int regptr, val; 438 535 439 536 regptr = (reg << 16) | chn; 440 537 441 spin_lock_irq save(&emu->emu_lock, flags);538 spin_lock_irq(&emu->emu_lock); 442 539 outl(regptr, emu->port + iobase + PTR); 443 540 val = inl(emu->port + iobase + DATA); 444 spin_unlock_irq restore(&emu->emu_lock, flags);541 spin_unlock_irq(&emu->emu_lock); 445 542 return val; 446 543 } … … 453 550 { 454 551 unsigned int regptr; 455 unsigned long flags;456 552 457 553 regptr = (reg << 16) | chn; 458 554 459 spin_lock_irq save(&emu->emu_lock, flags);555 spin_lock_irq(&emu->emu_lock); 460 556 outl(regptr, emu->port + iobase + PTR); 461 557 outl(data, emu->port + iobase + DATA); 462 spin_unlock_irq restore(&emu->emu_lock, flags);558 spin_unlock_irq(&emu->emu_lock); 463 559 } 464 560 … … 478 574 snd_iprintf(buffer, "%02X: ",i); 479 575 for (j = 0; j < voices; j++) { 480 if(iobase == 0) 481 value = snd_ptr_read(emu, 0, i, j); 482 else 483 value = snd_ptr_read(emu, 0x20, i, j); 576 value = snd_ptr_read(emu, iobase, i, j); 484 577 snd_iprintf(buffer, "%08lX ", value); 485 578 } … … 489 582 490 583 static void snd_emu_proc_ptr_reg_write(struct snd_info_entry *entry, 491 struct snd_info_buffer *buffer, int iobase) 584 struct snd_info_buffer *buffer, 585 int iobase, int length, int voices) 492 586 { 493 587 struct snd_emu10k1 *emu = entry->private_data; … … 497 591 if (sscanf(line, "%x %x %x", ®, &channel_id, &val) != 3) 498 592 continue; 499 if (reg < 0xa0 && val <= 0xffffffff && channel_id <= 3)593 if (reg < length && channel_id < voices) 500 594 snd_ptr_write(emu, iobase, reg, channel_id, val); 501 595 } … … 505 599 struct snd_info_buffer *buffer) 506 600 { 507 snd_emu_proc_ptr_reg_write(entry, buffer, 0 );601 snd_emu_proc_ptr_reg_write(entry, buffer, 0, 0x80, 64); 508 602 } 509 603 … … 511 605 struct snd_info_buffer *buffer) 512 606 { 513 snd_emu_proc_ptr_reg_write(entry, buffer, 0x20); 607 struct snd_emu10k1 *emu = entry->private_data; 608 snd_emu_proc_ptr_reg_write(entry, buffer, 0x20, 609 emu->card_capabilities->ca0108_chip ? 0xa0 : 0x80, 4); 514 610 } 515 611 … … 567 663 snd_emu_proc_ptr_reg_read00b, 568 664 snd_emu_proc_ptr_reg_write00); 569 snd_card_rw_proc_new(emu->card, "ptr_regs20a", emu, 570 snd_emu_proc_ptr_reg_read20a, 571 snd_emu_proc_ptr_reg_write20); 572 snd_card_rw_proc_new(emu->card, "ptr_regs20b", emu, 573 snd_emu_proc_ptr_reg_read20b, 574 snd_emu_proc_ptr_reg_write20); 575 snd_card_rw_proc_new(emu->card, "ptr_regs20c", emu, 576 snd_emu_proc_ptr_reg_read20c, 577 snd_emu_proc_ptr_reg_write20); 665 if (!emu->card_capabilities->emu_model && 666 (emu->card_capabilities->ca0151_chip || emu->card_capabilities->ca0108_chip)) { 667 snd_card_rw_proc_new(emu->card, "ptr_regs20a", emu, 668 snd_emu_proc_ptr_reg_read20a, 669 snd_emu_proc_ptr_reg_write20); 670 snd_card_rw_proc_new(emu->card, "ptr_regs20b", emu, 671 snd_emu_proc_ptr_reg_read20b, 672 snd_emu_proc_ptr_reg_write20); 673 if (emu->card_capabilities->ca0108_chip) 674 snd_card_rw_proc_new(emu->card, "ptr_regs20c", emu, 675 snd_emu_proc_ptr_reg_read20c, 676 snd_emu_proc_ptr_reg_write20); 677 } 578 678 #endif 579 679 -
GPL/trunk/alsa-kernel/pci/emu10k1/io.c
r679 r772 2 2 /* 3 3 * Copyright (c) by Jaroslav Kysela <perex@perex.cz> 4 * Lee Revell <rlrevell@joe-job.com> 5 * James Courtier-Dutton <James@superbug.co.uk> 6 * Oswald Buddenhagen <oswald.buddenhagen@gmx.de> 4 7 * Creative Labs, Inc. 8 * 5 9 * Routines for control of EMU10K1 chips 6 *7 * BUGS:8 * --9 *10 * TODO:11 * --12 10 */ 13 11 … … 19 17 #include "p17v.h" 20 18 19 static inline bool check_ptr_reg(struct snd_emu10k1 *emu, unsigned int reg) 20 { 21 if (snd_BUG_ON(!emu)) 22 return false; 23 if (snd_BUG_ON(reg & (emu->audigy ? (0xffff0000 & ~A_PTR_ADDRESS_MASK) 24 : (0xffff0000 & ~PTR_ADDRESS_MASK)))) 25 return false; 26 if (snd_BUG_ON(reg & 0x0000ffff & ~PTR_CHANNELNUM_MASK)) 27 return false; 28 return true; 29 } 30 21 31 unsigned int snd_emu10k1_ptr_read(struct snd_emu10k1 * emu, unsigned int reg, unsigned int chn) 22 32 { … … 25 35 unsigned int mask; 26 36 27 mask = emu->audigy ? A_PTR_ADDRESS_MASK : PTR_ADDRESS_MASK; 28 regptr = ((reg << 16) & mask) | (chn & PTR_CHANNELNUM_MASK); 37 regptr = (reg << 16) | chn; 38 if (!check_ptr_reg(emu, regptr)) 39 return 0; 40 41 spin_lock_irqsave(&emu->emu_lock, flags); 42 outl(regptr, emu->port + PTR); 43 val = inl(emu->port + DATA); 44 spin_unlock_irqrestore(&emu->emu_lock, flags); 29 45 30 46 if (reg & 0xff000000) { … … 33 49 size = (reg >> 24) & 0x3f; 34 50 offset = (reg >> 16) & 0x1f; 35 mask = ( (1 << size) - 1) << offset;51 mask = (1 << size) - 1; 36 52 37 spin_lock_irqsave(&emu->emu_lock, flags); 38 outl(regptr, emu->port + PTR); 39 val = inl(emu->port + DATA); 40 spin_unlock_irqrestore(&emu->emu_lock, flags); 41 42 return (val & mask) >> offset; 43 } else { 44 spin_lock_irqsave(&emu->emu_lock, flags); 45 outl(regptr, emu->port + PTR); 46 val = inl(emu->port + DATA); 47 spin_unlock_irqrestore(&emu->emu_lock, flags); 53 return (val >> offset) & mask; 54 } else { 48 55 return val; 49 56 } … … 58 65 unsigned int mask; 59 66 60 if (snd_BUG_ON(!emu)) 67 regptr = (reg << 16) | chn; 68 if (!check_ptr_reg(emu, regptr)) 61 69 return; 62 mask = emu->audigy ? A_PTR_ADDRESS_MASK : PTR_ADDRESS_MASK;63 regptr = ((reg << 16) & mask) | (chn & PTR_CHANNELNUM_MASK);64 70 65 71 if (reg & 0xff000000) { … … 68 74 size = (reg >> 24) & 0x3f; 69 75 offset = (reg >> 16) & 0x1f; 70 mask = ((1 << size) - 1) << offset; 71 data = (data << offset) & mask; 76 mask = (1 << size) - 1; 77 if (snd_BUG_ON(data & ~mask)) 78 return; 79 mask <<= offset; 80 data <<= offset; 72 81 73 82 spin_lock_irqsave(&emu->emu_lock, flags); 74 83 outl(regptr, emu->port + PTR); 75 84 data |= inl(emu->port + DATA) & ~mask; 76 outl(data, emu->port + DATA);77 spin_unlock_irqrestore(&emu->emu_lock, flags);78 85 } else { 79 86 spin_lock_irqsave(&emu->emu_lock, flags); 80 87 outl(regptr, emu->port + PTR); 88 } 89 outl(data, emu->port + DATA); 90 spin_unlock_irqrestore(&emu->emu_lock, flags); 91 } 92 93 EXPORT_SYMBOL(snd_emu10k1_ptr_write); 94 95 void snd_emu10k1_ptr_write_multiple(struct snd_emu10k1 *emu, unsigned int chn, ...) 96 { 97 va_list va; 98 u32 addr_mask; 99 unsigned long flags; 100 101 if (snd_BUG_ON(!emu)) 102 return; 103 if (snd_BUG_ON(chn & ~PTR_CHANNELNUM_MASK)) 104 return; 105 addr_mask = ~((emu->audigy ? A_PTR_ADDRESS_MASK : PTR_ADDRESS_MASK) >> 16); 106 107 va_start(va, chn); 108 spin_lock_irqsave(&emu->emu_lock, flags); 109 for (;;) { 110 u32 data; 111 u32 reg = va_arg(va, u32); 112 if (reg == REGLIST_END) 113 break; 114 data = va_arg(va, u32); 115 if (snd_BUG_ON(reg & addr_mask)) // Only raw registers supported here 116 continue; 117 outl((reg << 16) | chn, emu->port + PTR); 81 118 outl(data, emu->port + DATA); 82 spin_unlock_irqrestore(&emu->emu_lock, flags); 83 } 84 } 85 86 EXPORT_SYMBOL(snd_emu10k1_ptr_write); 119 } 120 spin_unlock_irqrestore(&emu->emu_lock, flags); 121 va_end(va); 122 } 123 124 EXPORT_SYMBOL(snd_emu10k1_ptr_write_multiple); 87 125 88 126 unsigned int snd_emu10k1_ptr20_read(struct snd_emu10k1 * emu, … … 96 134 97 135 spin_lock_irqsave(&emu->emu_lock, flags); 98 outl(regptr, emu->port + 0x20 + PTR);99 val = inl(emu->port + 0x20 + DATA);136 outl(regptr, emu->port + PTR2); 137 val = inl(emu->port + DATA2); 100 138 spin_unlock_irqrestore(&emu->emu_lock, flags); 101 139 return val; … … 113 151 114 152 spin_lock_irqsave(&emu->emu_lock, flags); 115 outl(regptr, emu->port + 0x20 + PTR);116 outl(data, emu->port + 0x20 + DATA);153 outl(regptr, emu->port + PTR2); 154 outl(data, emu->port + DATA2); 117 155 spin_unlock_irqrestore(&emu->emu_lock, flags); 118 156 } … … 129 167 spin_lock(&emu->spi_lock); 130 168 if (emu->card_capabilities->ca0108_chip) 131 reg = 0x3c; /* PTR20, reg 0x3c */169 reg = P17V_SPI; 132 170 else { 133 171 /* For other chip types the SPI register … … 234 272 } 235 273 236 int snd_emu1010_fpga_write(struct snd_emu10k1 * emu, u32 reg, u32 value) 237 { 238 unsigned long flags; 239 240 if (reg > 0x3f) 241 return 1; 274 static void snd_emu1010_fpga_write_locked(struct snd_emu10k1 *emu, u32 reg, u32 value) 275 { 276 if (snd_BUG_ON(reg > 0x3f)) 277 return; 242 278 reg += 0x40; /* 0x40 upwards are registers. */ 243 if (value > 0x3f) /* 0 to 0x3f are values */ 244 return 1; 245 spin_lock_irqsave(&emu->emu_lock, flags); 246 outl(reg, emu->port + A_IOCFG); 279 if (snd_BUG_ON(value > 0x3f)) /* 0 to 0x3f are values */ 280 return; 281 outw(reg, emu->port + A_GPIO); 247 282 udelay(10); 248 out l(reg | 0x80, emu->port + A_IOCFG); /* High bit clocks the value into the fpga. */283 outw(reg | 0x80, emu->port + A_GPIO); /* High bit clocks the value into the fpga. */ 249 284 udelay(10); 250 out l(value, emu->port + A_IOCFG);285 outw(value, emu->port + A_GPIO); 251 286 udelay(10); 252 outl(value | 0x80 , emu->port + A_IOCFG); /* High bit clocks the value into the fpga. */ 253 spin_unlock_irqrestore(&emu->emu_lock, flags); 254 255 return 0; 256 } 257 258 int snd_emu1010_fpga_read(struct snd_emu10k1 * emu, u32 reg, u32 *value) 259 { 260 unsigned long flags; 261 if (reg > 0x3f) 262 return 1; 287 outw(value | 0x80 , emu->port + A_GPIO); /* High bit clocks the value into the fpga. */ 288 udelay(10); 289 } 290 291 void snd_emu1010_fpga_write(struct snd_emu10k1 *emu, u32 reg, u32 value) 292 { 293 unsigned long flags; 294 295 spin_lock_irqsave(&emu->emu_lock, flags); 296 snd_emu1010_fpga_write_locked(emu, reg, value); 297 spin_unlock_irqrestore(&emu->emu_lock, flags); 298 } 299 300 static void snd_emu1010_fpga_read_locked(struct snd_emu10k1 *emu, u32 reg, u32 *value) 301 { 302 // The higest input pin is used as the designated interrupt trigger, 303 // so it needs to be masked out. 304 // But note that any other input pin change will also cause an IRQ, 305 // so using this function often causes an IRQ as a side effect. 306 u32 mask = emu->card_capabilities->ca0108_chip ? 0x1f : 0x7f; 307 if (snd_BUG_ON(reg > 0x3f)) 308 return; 263 309 reg += 0x40; /* 0x40 upwards are registers. */ 264 spin_lock_irqsave(&emu->emu_lock, flags); 265 outl(reg, emu->port + A_IOCFG); 310 outw(reg, emu->port + A_GPIO); 266 311 udelay(10); 267 out l(reg | 0x80, emu->port + A_IOCFG); /* High bit clocks the value into the fpga. */312 outw(reg | 0x80, emu->port + A_GPIO); /* High bit clocks the value into the fpga. */ 268 313 udelay(10); 269 *value = ((inl(emu->port + A_IOCFG) >> 8) & 0x7f); 270 spin_unlock_irqrestore(&emu->emu_lock, flags); 271 272 return 0; 314 *value = ((inw(emu->port + A_GPIO) >> 8) & mask); 315 } 316 317 void snd_emu1010_fpga_read(struct snd_emu10k1 *emu, u32 reg, u32 *value) 318 { 319 unsigned long flags; 320 321 spin_lock_irqsave(&emu->emu_lock, flags); 322 snd_emu1010_fpga_read_locked(emu, reg, value); 323 spin_unlock_irqrestore(&emu->emu_lock, flags); 273 324 } 274 325 … … 276 327 * but one Source can feed any number of Destinations simultaneously. 277 328 */ 278 int snd_emu1010_fpga_link_dst_src_write(struct snd_emu10k1 * emu, u32 dst, u32 src) 279 { 280 snd_emu1010_fpga_write(emu, 0x00, ((dst >> 8) & 0x3f) ); 281 snd_emu1010_fpga_write(emu, 0x01, (dst & 0x3f) ); 282 snd_emu1010_fpga_write(emu, 0x02, ((src >> 8) & 0x3f) ); 283 snd_emu1010_fpga_write(emu, 0x03, (src & 0x3f) ); 284 285 return 0; 329 void snd_emu1010_fpga_link_dst_src_write(struct snd_emu10k1 *emu, u32 dst, u32 src) 330 { 331 unsigned long flags; 332 333 if (snd_BUG_ON(dst & ~0x71f)) 334 return; 335 if (snd_BUG_ON(src & ~0x71f)) 336 return; 337 spin_lock_irqsave(&emu->emu_lock, flags); 338 snd_emu1010_fpga_write_locked(emu, EMU_HANA_DESTHI, dst >> 8); 339 snd_emu1010_fpga_write_locked(emu, EMU_HANA_DESTLO, dst & 0x1f); 340 snd_emu1010_fpga_write_locked(emu, EMU_HANA_SRCHI, src >> 8); 341 snd_emu1010_fpga_write_locked(emu, EMU_HANA_SRCLO, src & 0x1f); 342 spin_unlock_irqrestore(&emu->emu_lock, flags); 343 } 344 345 u32 snd_emu1010_fpga_link_dst_src_read(struct snd_emu10k1 *emu, u32 dst) 346 { 347 unsigned long flags; 348 u32 hi, lo; 349 350 if (snd_BUG_ON(dst & ~0x71f)) 351 return 0; 352 spin_lock_irqsave(&emu->emu_lock, flags); 353 snd_emu1010_fpga_write_locked(emu, EMU_HANA_DESTHI, dst >> 8); 354 snd_emu1010_fpga_write_locked(emu, EMU_HANA_DESTLO, dst & 0x1f); 355 snd_emu1010_fpga_read_locked(emu, EMU_HANA_SRCHI, &hi); 356 snd_emu1010_fpga_read_locked(emu, EMU_HANA_SRCLO, &lo); 357 spin_unlock_irqrestore(&emu->emu_lock, flags); 358 return (hi << 8) | lo; 359 } 360 361 int snd_emu1010_get_raw_rate(struct snd_emu10k1 *emu, u8 src) 362 { 363 u32 reg_lo, reg_hi, value, value2; 364 365 switch (src) { 366 case EMU_HANA_WCLOCK_HANA_SPDIF_IN: 367 snd_emu1010_fpga_read(emu, EMU_HANA_SPDIF_MODE, &value); 368 if (value & EMU_HANA_SPDIF_MODE_RX_INVALID) 369 return 0; 370 reg_lo = EMU_HANA_WC_SPDIF_LO; 371 reg_hi = EMU_HANA_WC_SPDIF_HI; 372 break; 373 case EMU_HANA_WCLOCK_HANA_ADAT_IN: 374 reg_lo = EMU_HANA_WC_ADAT_LO; 375 reg_hi = EMU_HANA_WC_ADAT_HI; 376 break; 377 case EMU_HANA_WCLOCK_SYNC_BNC: 378 reg_lo = EMU_HANA_WC_BNC_LO; 379 reg_hi = EMU_HANA_WC_BNC_HI; 380 break; 381 case EMU_HANA_WCLOCK_2ND_HANA: 382 reg_lo = EMU_HANA2_WC_SPDIF_LO; 383 reg_hi = EMU_HANA2_WC_SPDIF_HI; 384 break; 385 default: 386 return 0; 387 } 388 snd_emu1010_fpga_read(emu, reg_hi, &value); 389 snd_emu1010_fpga_read(emu, reg_lo, &value2); 390 // FIXME: The /4 is valid for 0404b, but contradicts all other info. 391 return 0x1770000 / 4 / (((value << 5) | value2) + 1); 392 } 393 394 void snd_emu1010_update_clock(struct snd_emu10k1 *emu) 395 { 396 int clock; 397 u32 leds; 398 399 switch (emu->emu1010.wclock) { 400 case EMU_HANA_WCLOCK_INT_44_1K | EMU_HANA_WCLOCK_1X: 401 clock = 44100; 402 leds = EMU_HANA_DOCK_LEDS_2_44K; 403 break; 404 case EMU_HANA_WCLOCK_INT_48K | EMU_HANA_WCLOCK_1X: 405 clock = 48000; 406 leds = EMU_HANA_DOCK_LEDS_2_48K; 407 break; 408 default: 409 clock = snd_emu1010_get_raw_rate( 410 emu, emu->emu1010.wclock & EMU_HANA_WCLOCK_SRC_MASK); 411 // The raw rate reading is rather coarse (it cannot accurately 412 // represent 44.1 kHz) and fluctuates slightly. Luckily, the 413 // clock comes from digital inputs, which use standardized rates. 414 // So we round to the closest standard rate and ignore discrepancies. 415 if (clock < 46000) { 416 clock = 44100; 417 leds = EMU_HANA_DOCK_LEDS_2_EXT | EMU_HANA_DOCK_LEDS_2_44K; 418 } else { 419 clock = 48000; 420 leds = EMU_HANA_DOCK_LEDS_2_EXT | EMU_HANA_DOCK_LEDS_2_48K; 421 } 422 break; 423 } 424 emu->emu1010.word_clock = clock; 425 426 // FIXME: this should probably represent the AND of all currently 427 // used sources' lock status. But we don't know how to get that ... 428 leds |= EMU_HANA_DOCK_LEDS_2_LOCK; 429 430 snd_emu1010_fpga_write(emu, EMU_HANA_DOCK_LEDS_2, leds); 286 431 } 287 432 … … 314 459 315 460 spin_lock_irqsave(&emu->emu_lock, flags); 316 /* voice interrupt */317 461 if (voicenum >= 32) { 318 462 outl(CLIEH << 16, emu->port + PTR); … … 334 478 335 479 spin_lock_irqsave(&emu->emu_lock, flags); 336 /* voice interrupt */337 480 if (voicenum >= 32) { 338 481 outl(CLIEH << 16, emu->port + PTR); … … 353 496 354 497 spin_lock_irqsave(&emu->emu_lock, flags); 355 /* voice interrupt */356 498 if (voicenum >= 32) { 357 499 outl(CLIPH << 16, emu->port + PTR); … … 371 513 372 514 spin_lock_irqsave(&emu->emu_lock, flags); 373 /* voice interrupt */374 515 if (voicenum >= 32) { 375 516 outl(HLIEH << 16, emu->port + PTR); … … 391 532 392 533 spin_lock_irqsave(&emu->emu_lock, flags); 393 /* voice interrupt */394 534 if (voicenum >= 32) { 395 535 outl(HLIEH << 16, emu->port + PTR); … … 410 550 411 551 spin_lock_irqsave(&emu->emu_lock, flags); 412 /* voice interrupt */413 552 if (voicenum >= 32) { 414 553 outl(HLIPH << 16, emu->port + PTR); … … 422 561 } 423 562 563 #if 0 424 564 void snd_emu10k1_voice_set_loop_stop(struct snd_emu10k1 *emu, unsigned int voicenum) 425 565 { … … 428 568 429 569 spin_lock_irqsave(&emu->emu_lock, flags); 430 /* voice interrupt */431 570 if (voicenum >= 32) { 432 571 outl(SOLEH << 16, emu->port + PTR); … … 448 587 449 588 spin_lock_irqsave(&emu->emu_lock, flags); 450 /* voice interrupt */451 589 if (voicenum >= 32) { 452 590 outl(SOLEH << 16, emu->port + PTR); … … 460 598 outl(sol, emu->port + DATA); 461 599 spin_unlock_irqrestore(&emu->emu_lock, flags); 600 } 601 #endif 602 603 void snd_emu10k1_voice_set_loop_stop_multiple(struct snd_emu10k1 *emu, u64 voices) 604 { 605 unsigned long flags; 606 607 spin_lock_irqsave(&emu->emu_lock, flags); 608 outl(SOLEL << 16, emu->port + PTR); 609 outl(inl(emu->port + DATA) | (u32)voices, emu->port + DATA); 610 outl(SOLEH << 16, emu->port + PTR); 611 outl(inl(emu->port + DATA) | (u32)(voices >> 32), emu->port + DATA); 612 spin_unlock_irqrestore(&emu->emu_lock, flags); 613 } 614 615 void snd_emu10k1_voice_clear_loop_stop_multiple(struct snd_emu10k1 *emu, u64 voices) 616 { 617 unsigned long flags; 618 619 spin_lock_irqsave(&emu->emu_lock, flags); 620 outl(SOLEL << 16, emu->port + PTR); 621 outl(inl(emu->port + DATA) & (u32)~voices, emu->port + DATA); 622 outl(SOLEH << 16, emu->port + PTR); 623 outl(inl(emu->port + DATA) & (u32)(~voices >> 32), emu->port + DATA); 624 spin_unlock_irqrestore(&emu->emu_lock, flags); 625 } 626 627 int snd_emu10k1_voice_clear_loop_stop_multiple_atomic(struct snd_emu10k1 *emu, u64 voices) 628 { 629 unsigned long flags; 630 u32 soll, solh; 631 int ret = -EIO; 632 633 spin_lock_irqsave(&emu->emu_lock, flags); 634 635 outl(SOLEL << 16, emu->port + PTR); 636 soll = inl(emu->port + DATA); 637 outl(SOLEH << 16, emu->port + PTR); 638 solh = inl(emu->port + DATA); 639 640 soll &= (u32)~voices; 641 solh &= (u32)(~voices >> 32); 642 643 for (int tries = 0; tries < 1000; tries++) { 644 const u32 quart = 1U << (REG_SIZE(WC_CURRENTCHANNEL) - 2); 645 // First we wait for the third quarter of the sample cycle ... 646 u32 wc = inl(emu->port + WC); 647 u32 cc = REG_VAL_GET(WC_CURRENTCHANNEL, wc); 648 if (cc >= quart * 2 && cc < quart * 3) { 649 // ... and release the low voices, while the high ones are serviced. 650 outl(SOLEL << 16, emu->port + PTR); 651 outl(soll, emu->port + DATA); 652 // Then we wait for the first quarter of the next sample cycle ... 653 for (; tries < 1000; tries++) { 654 cc = REG_VAL_GET(WC_CURRENTCHANNEL, inl(emu->port + WC)); 655 if (cc < quart) 656 goto good; 657 // We will block for 10+ us with interrupts disabled. This is 658 // not nice at all, but necessary for reasonable reliability. 659 udelay(1); 660 } 661 break; 662 good: 663 // ... and release the high voices, while the low ones are serviced. 664 outl(SOLEH << 16, emu->port + PTR); 665 outl(solh, emu->port + DATA); 666 // Finally we verify that nothing interfered in fact. 667 if (REG_VAL_GET(WC_SAMPLECOUNTER, inl(emu->port + WC)) == 668 ((REG_VAL_GET(WC_SAMPLECOUNTER, wc) + 1) & REG_MASK0(WC_SAMPLECOUNTER))) { 669 ret = 0; 670 } else { 671 ret = -EAGAIN; 672 } 673 break; 674 } 675 // Don't block for too long 676 spin_unlock_irqrestore(&emu->emu_lock, flags); 677 udelay(1); 678 spin_lock_irqsave(&emu->emu_lock, flags); 679 } 680 681 spin_unlock_irqrestore(&emu->emu_lock, flags); 682 return ret; 462 683 } 463 684 … … 504 725 spin_unlock_irqrestore(&emu->emu_lock, flags); 505 726 } 506 507 /*508 * convert rate to pitch509 */510 511 unsigned int snd_emu10k1_rate_to_pitch(unsigned int rate)512 {513 static const u32 logMagTable[128] = {514 0x00000, 0x02dfc, 0x05b9e, 0x088e6, 0x0b5d6, 0x0e26f, 0x10eb3, 0x13aa2,515 0x1663f, 0x1918a, 0x1bc84, 0x1e72e, 0x2118b, 0x23b9a, 0x2655d, 0x28ed5,516 0x2b803, 0x2e0e8, 0x30985, 0x331db, 0x359eb, 0x381b6, 0x3a93d, 0x3d081,517 0x3f782, 0x41e42, 0x444c1, 0x46b01, 0x49101, 0x4b6c4, 0x4dc49, 0x50191,518 0x5269e, 0x54b6f, 0x57006, 0x59463, 0x5b888, 0x5dc74, 0x60029, 0x623a7,519 0x646ee, 0x66a00, 0x68cdd, 0x6af86, 0x6d1fa, 0x6f43c, 0x7164b, 0x73829,520 0x759d4, 0x77b4f, 0x79c9a, 0x7bdb5, 0x7dea1, 0x7ff5e, 0x81fed, 0x8404e,521 0x86082, 0x88089, 0x8a064, 0x8c014, 0x8df98, 0x8fef1, 0x91e20, 0x93d26,522 0x95c01, 0x97ab4, 0x9993e, 0x9b79f, 0x9d5d9, 0x9f3ec, 0xa11d8, 0xa2f9d,523 0xa4d3c, 0xa6ab5, 0xa8808, 0xaa537, 0xac241, 0xadf26, 0xafbe7, 0xb1885,524 0xb3500, 0xb5157, 0xb6d8c, 0xb899f, 0xba58f, 0xbc15e, 0xbdd0c, 0xbf899,525 0xc1404, 0xc2f50, 0xc4a7b, 0xc6587, 0xc8073, 0xc9b3f, 0xcb5ed, 0xcd07c,526 0xceaec, 0xd053f, 0xd1f73, 0xd398a, 0xd5384, 0xd6d60, 0xd8720, 0xda0c3,527 0xdba4a, 0xdd3b4, 0xded03, 0xe0636, 0xe1f4e, 0xe384a, 0xe512c, 0xe69f3,528 0xe829f, 0xe9b31, 0xeb3a9, 0xecc08, 0xee44c, 0xefc78, 0xf148a, 0xf2c83,529 0xf4463, 0xf5c2a, 0xf73da, 0xf8b71, 0xfa2f0, 0xfba57, 0xfd1a7, 0xfe8df530 };531 static const char logSlopeTable[128] = {532 0x5c, 0x5c, 0x5b, 0x5a, 0x5a, 0x59, 0x58, 0x58,533 0x57, 0x56, 0x56, 0x55, 0x55, 0x54, 0x53, 0x53,534 0x52, 0x52, 0x51, 0x51, 0x50, 0x50, 0x4f, 0x4f,535 0x4e, 0x4d, 0x4d, 0x4d, 0x4c, 0x4c, 0x4b, 0x4b,536 0x4a, 0x4a, 0x49, 0x49, 0x48, 0x48, 0x47, 0x47,537 0x47, 0x46, 0x46, 0x45, 0x45, 0x45, 0x44, 0x44,538 0x43, 0x43, 0x43, 0x42, 0x42, 0x42, 0x41, 0x41,539 0x41, 0x40, 0x40, 0x40, 0x3f, 0x3f, 0x3f, 0x3e,540 0x3e, 0x3e, 0x3d, 0x3d, 0x3d, 0x3c, 0x3c, 0x3c,541 0x3b, 0x3b, 0x3b, 0x3b, 0x3a, 0x3a, 0x3a, 0x39,542 0x39, 0x39, 0x39, 0x38, 0x38, 0x38, 0x38, 0x37,543 0x37, 0x37, 0x37, 0x36, 0x36, 0x36, 0x36, 0x35,544 0x35, 0x35, 0x35, 0x34, 0x34, 0x34, 0x34, 0x34,545 0x33, 0x33, 0x33, 0x33, 0x32, 0x32, 0x32, 0x32,546 0x32, 0x31, 0x31, 0x31, 0x31, 0x31, 0x30, 0x30,547 0x30, 0x30, 0x30, 0x2f, 0x2f, 0x2f, 0x2f, 0x2f548 };549 int i;550 551 if (rate == 0)552 return 0; /* Bail out if no leading "1" */553 rate *= 11185; /* Scale 48000 to 0x20002380 */554 for (i = 31; i > 0; i--) {555 if (rate & 0x80000000) { /* Detect leading "1" */556 return (((unsigned int) (i - 15) << 20) +557 logMagTable[0x7f & (rate >> 24)] +558 (0x7f & (rate >> 17)) *559 logSlopeTable[0x7f & (rate >> 24)]);560 }561 rate <<= 1;562 }563 564 return 0; /* Should never reach this point */565 }566 -
GPL/trunk/alsa-kernel/pci/emu10k1/irq.c
r679 r772 4 4 * Creative Labs, Inc. 5 5 * Routines for IRQ control of EMU10K1 chips 6 *7 * BUGS:8 * --9 *10 * TODO:11 * --12 6 */ 13 7 … … 19 13 { 20 14 struct snd_emu10k1 *emu = dev_id; 21 unsigned int status, status2, orig_status, orig_status2;15 unsigned int status, orig_status; 22 16 int handled = 0; 23 17 int timeout = 0; 24 18 25 while (((status = inl(emu->port + IPR)) != 0) && (timeout < 1000)) { 26 timeout++; 27 orig_status = status; 19 while ((status = inl(emu->port + IPR)) != 0) { 28 20 handled = 1; 29 21 if ((status & 0xffffffff) == 0xffffffff) { … … 32 24 break; 33 25 } 26 if (++timeout == 1000) { 27 dev_info(emu->card->dev, "emu10k1 irq routine failure\n"); 28 break; 29 } 30 orig_status = status; 34 31 if (status & IPR_PCIERROR) { 35 32 dev_err(emu->card->dev, "interrupt: PCI error\n"); … … 45 42 } 46 43 if (status & IPR_CHANNELLOOP) { 44 struct snd_emu10k1_voice *pvoice; 47 45 int voice; 48 46 int voice_max = status & IPR_CHANNELNUMBERMASK; 49 47 u32 val; 50 struct snd_emu10k1_voice *pvoice = emu->voices;51 48 52 49 val = snd_emu10k1_ptr_read(emu, CLIPL, 0); 50 pvoice = emu->voices; 53 51 for (voice = 0; voice <= voice_max; voice++) { 54 52 if (voice == 0x20) … … 66 64 } 67 65 val = snd_emu10k1_ptr_read(emu, HLIPL, 0); 66 pvoice = emu->voices; 68 67 for (voice = 0; voice <= voice_max; voice++) { 69 68 if (voice == 0x20) … … 80 79 pvoice++; 81 80 } 82 status &= ~ IPR_CHANNELLOOP;81 status &= ~(IPR_CHANNELLOOP | IPR_CHANNELNUMBERMASK); 83 82 } 84 status &= ~IPR_CHANNELNUMBERMASK;85 83 if (status & (IPR_ADCBUFFULL|IPR_ADCBUFHALFFULL)) { 86 84 if (emu->capture_interrupt) … … 140 138 } 141 139 if (status & IPR_P16V) { 142 while ((status2 = inl(emu->port + IPR2)) != 0) { 143 u32 mask = INTE2_PLAYBACK_CH_0_LOOP; /* Full Loop */ 144 struct snd_emu10k1_voice *pvoice = &(emu->p16v_voices[0]); 145 struct snd_emu10k1_voice *cvoice = &(emu->p16v_capture_voice); 146 147 /* dev_dbg(emu->card->dev, "status2=0x%x\n", status2); */ 148 orig_status2 = status2; 149 if(status2 & mask) { 150 if(pvoice->use) { 151 snd_pcm_period_elapsed(pvoice->epcm->substream); 152 } else { 153 dev_err(emu->card->dev, 154 "p16v: status: 0x%08x, mask=0x%08x, pvoice=%p, use=%d\n", 155 status2, mask, pvoice, 156 pvoice->use); 157 } 158 } 159 if(status2 & 0x110000) { 160 /* dev_info(emu->card->dev, "capture int found\n"); */ 161 if(cvoice->use) { 162 /* dev_info(emu->card->dev, "capture period_elapsed\n"); */ 163 snd_pcm_period_elapsed(cvoice->epcm->substream); 164 } 165 } 166 outl(orig_status2, emu->port + IPR2); /* ack all */ 167 } 140 if (emu->p16v_interrupt) 141 emu->p16v_interrupt(emu); 142 else 143 outl(0, emu->port + INTE2); 168 144 status &= ~IPR_P16V; 145 } 146 if (status & IPR_A_GPIO) { 147 if (emu->gpio_interrupt) 148 emu->gpio_interrupt(emu); 149 else 150 snd_emu10k1_intr_disable(emu, INTE_A_GPIOENABLE); 151 status &= ~IPR_A_GPIO; 169 152 } 170 153 171 154 if (status) { 172 unsigned int bits;173 155 dev_err(emu->card->dev, 174 156 "unhandled interrupt: 0x%08x\n", status); 175 //make sure any interrupts we don't handle are disabled:176 bits = INTE_FXDSPENABLE |177 INTE_PCIERRORENABLE |178 INTE_VOLINCRENABLE |179 INTE_VOLDECRENABLE |180 INTE_MUTEENABLE |181 INTE_MICBUFENABLE |182 INTE_ADCBUFENABLE |183 INTE_EFXBUFENABLE |184 INTE_GPSPDIFENABLE |185 INTE_CDSPDIFENABLE |186 INTE_INTERVALTIMERENB |187 INTE_MIDITXENABLE |188 INTE_MIDIRXENABLE;189 if (emu->audigy)190 bits |= INTE_A_MIDITXENABLE2 | INTE_A_MIDIRXENABLE2;191 snd_emu10k1_intr_disable(emu, bits);192 157 } 193 158 outl(orig_status, emu->port + IPR); /* ack all */ 194 159 } 195 if (timeout == 1000)196 dev_info(emu->card->dev, "emu10k1 irq routine failure\n");197 160 198 161 return IRQ_RETVAL(handled); -
GPL/trunk/alsa-kernel/pci/emu10k1/memory.c
r703 r772 316 316 return NULL; 317 317 318 idx = runtime->period_size >= runtime->buffer_size ?319 (emu->delay_pcm_irq * 2) : 0;320 318 mutex_lock(&hdr->block_mutex); 321 blk = search_empty(emu, runtime->dma_bytes + idx);319 blk = search_empty(emu, runtime->dma_bytes); 322 320 if (blk == NULL) { 323 321 mutex_unlock(&hdr->block_mutex); … … 325 323 } 326 324 /* fill buffer addresses but pointers are not stored so that 327 * snd_free_pci_page() is not called in insynth_free()325 * snd_free_pci_page() is not called in synth_free() 328 326 */ 329 327 idx = 0; -
GPL/trunk/alsa-kernel/pci/emu10k1/p16v.c
r717 r772 150 150 }; 151 151 152 static void snd_p16v_pcm_free_substream(struct snd_pcm_runtime *runtime)153 {154 struct snd_emu10k1_pcm *epcm = runtime->private_data;155 156 kfree(epcm);157 }158 159 152 /* open_playback callback */ 160 153 static int snd_p16v_pcm_open_playback_channel(struct snd_pcm_substream *substream, int channel_id) 161 154 { 162 struct snd_emu10k1 *emu = snd_pcm_substream_chip(substream);163 struct snd_emu10k1_voice *channel = &(emu->p16v_voices[channel_id]);164 struct snd_emu10k1_pcm *epcm;165 155 struct snd_pcm_runtime *runtime = substream->runtime; 166 156 int err; 167 157 168 epcm = kzalloc(sizeof(*epcm), GFP_KERNEL);169 /* dev_dbg(emu->card->dev, "epcm kcalloc: %p\n", epcm); */170 171 if (epcm == NULL)172 return -ENOMEM;173 epcm->emu = emu;174 epcm->substream = substream;175 158 /* 176 159 dev_dbg(emu->card->dev, "epcm device=%d, channel_id=%d\n", 177 160 substream->pcm->device, channel_id); 178 161 */ 179 runtime->private_data = epcm;180 runtime->private_free = snd_p16v_pcm_free_substream;181 162 182 163 runtime->hw = snd_p16v_playback_hw; 183 164 184 channel->emu = emu;185 channel->number = channel_id;186 187 channel->use=1;188 165 #if 0 /* debug */ 189 166 dev_dbg(emu->card->dev, … … 194 171 #endif /* debug */ 195 172 /* channel->interrupt = snd_p16v_pcm_channel_interrupt; */ 196 channel->epcm = epcm;197 173 err = snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS); 198 174 if (err < 0) … … 206 182 return 0; 207 183 } 184 208 185 /* open_capture callback */ 209 186 static int snd_p16v_pcm_open_capture_channel(struct snd_pcm_substream *substream, int channel_id) 210 187 { 211 struct snd_emu10k1 *emu = snd_pcm_substream_chip(substream);212 struct snd_emu10k1_voice *channel = &(emu->p16v_capture_voice);213 struct snd_emu10k1_pcm *epcm;214 188 struct snd_pcm_runtime *runtime = substream->runtime; 215 189 int err; 216 190 217 epcm = kzalloc(sizeof(*epcm), GFP_KERNEL);218 /* dev_dbg(emu->card->dev, "epcm kcalloc: %p\n", epcm); */219 220 if (epcm == NULL)221 return -ENOMEM;222 epcm->emu = emu;223 epcm->substream = substream;224 191 /* 225 192 dev_dbg(emu->card->dev, "epcm device=%d, channel_id=%d\n", 226 193 substream->pcm->device, channel_id); 227 194 */ 228 runtime->private_data = epcm;229 runtime->private_free = snd_p16v_pcm_free_substream;230 195 231 196 runtime->hw = snd_p16v_capture_hw; 232 197 233 channel->emu = emu;234 channel->number = channel_id;235 236 channel->use=1;237 #if 0 /* debug */238 dev_dbg(emu->card->dev,239 "p16v: open channel_id=%d, channel=%p, use=0x%x\n",240 channel_id, channel, channel->use);241 dev_dbg(emu->card->dev, "open:channel_id=%d, chip=%p, channel=%p\n",242 channel_id, chip, channel);243 #endif /* debug */244 /* channel->interrupt = snd_p16v_pcm_channel_interrupt; */245 channel->epcm = epcm;246 198 err = snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS); 247 199 if (err < 0) … … 255 207 static int snd_p16v_pcm_close_playback(struct snd_pcm_substream *substream) 256 208 { 257 struct snd_emu10k1 *emu = snd_pcm_substream_chip(substream);258 //struct snd_pcm_runtime *runtime = substream->runtime;259 //struct snd_emu10k1_pcm *epcm = runtime->private_data;260 emu->p16v_voices[substream->pcm->device - emu->p16v_device_offset].use = 0;261 /* FIXME: maybe zero others */262 209 return 0; 263 210 } … … 266 213 static int snd_p16v_pcm_close_capture(struct snd_pcm_substream *substream) 267 214 { 268 struct snd_emu10k1 *emu = snd_pcm_substream_chip(substream);269 //struct snd_pcm_runtime *runtime = substream->runtime;270 //struct snd_emu10k1_pcm *epcm = runtime->private_data;271 emu->p16v_capture_voice.use = 0;272 /* FIXME: maybe zero others */273 215 return 0; 274 216 } … … 313 255 #endif /* debug */ 314 256 tmp = snd_emu10k1_ptr_read(emu, A_SPDIF_SAMPLERATE, channel); 257 tmp &= ~(A_SPDIF_RATE_MASK | A_EHC_SRC48_MASK); 315 258 switch (runtime->rate) { 316 259 case 44100: 317 snd_emu10k1_ptr_write(emu, A_SPDIF_SAMPLERATE, channel, (tmp & ~0xe0e0) | 0x8080); 260 snd_emu10k1_ptr_write(emu, A_SPDIF_SAMPLERATE, channel, 261 tmp | A_SPDIF_44100 | A_EHC_SRC48_44); 318 262 break; 319 263 case 96000: 320 snd_emu10k1_ptr_write(emu, A_SPDIF_SAMPLERATE, channel, (tmp & ~0xe0e0) | 0x4040); 264 snd_emu10k1_ptr_write(emu, A_SPDIF_SAMPLERATE, channel, 265 tmp | A_SPDIF_96000 | A_EHC_SRC48_96); 321 266 break; 322 267 case 192000: 323 snd_emu10k1_ptr_write(emu, A_SPDIF_SAMPLERATE, channel, (tmp & ~0xe0e0) | 0x2020); 268 snd_emu10k1_ptr_write(emu, A_SPDIF_SAMPLERATE, channel, 269 tmp | A_SPDIF_192000 | A_EHC_SRC48_192); 324 270 break; 325 271 case 48000: 326 272 default: 327 snd_emu10k1_ptr_write(emu, A_SPDIF_SAMPLERATE, channel, (tmp & ~0xe0e0) | 0x0000); 273 snd_emu10k1_ptr_write(emu, A_SPDIF_SAMPLERATE, channel, 274 tmp | A_SPDIF_48000 | A_EHC_SRC48_BYPASS); 328 275 break; 329 276 } … … 341 288 snd_emu10k1_ptr20_write(emu, PLAYBACK_PERIOD_SIZE, channel, 0); // buffer size in bytes 342 289 snd_emu10k1_ptr20_write(emu, PLAYBACK_POINTER, channel, 0); 343 snd_emu10k1_ptr20_write(emu, 0x07, channel, 0x0);344 snd_emu10k1_ptr20_write(emu, 0x08, channel, 0);290 snd_emu10k1_ptr20_write(emu, PLAYBACK_FIFO_END_ADDRESS, channel, 0); 291 snd_emu10k1_ptr20_write(emu, PLAYBACK_FIFO_POINTER, channel, 0); 345 292 346 293 return 0; … … 353 300 struct snd_pcm_runtime *runtime = substream->runtime; 354 301 int channel = substream->pcm->device - emu->p16v_device_offset; 355 u32 tmp;356 302 357 303 /* … … 363 309 frames_to_bytes(runtime, 1)); 364 310 */ 365 tmp = snd_emu10k1_ptr_read(emu, A_SPDIF_SAMPLERATE, channel);366 311 switch (runtime->rate) { 367 312 case 44100: 368 snd_emu10k1_ptr_write(emu, A_ SPDIF_SAMPLERATE, channel, (tmp & ~0x0e00) | 0x0800);313 snd_emu10k1_ptr_write(emu, A_I2S_CAPTURE_RATE, channel, A_I2S_CAPTURE_44100); 369 314 break; 370 315 case 96000: 371 snd_emu10k1_ptr_write(emu, A_ SPDIF_SAMPLERATE, channel, (tmp & ~0x0e00) | 0x0400);316 snd_emu10k1_ptr_write(emu, A_I2S_CAPTURE_RATE, channel, A_I2S_CAPTURE_96000); 372 317 break; 373 318 case 192000: 374 snd_emu10k1_ptr_write(emu, A_ SPDIF_SAMPLERATE, channel, (tmp & ~0x0e00) | 0x0200);319 snd_emu10k1_ptr_write(emu, A_I2S_CAPTURE_RATE, channel, A_I2S_CAPTURE_192000); 375 320 break; 376 321 case 48000: 377 322 default: 378 snd_emu10k1_ptr_write(emu, A_ SPDIF_SAMPLERATE, channel, (tmp & ~0x0e00) | 0x0000);323 snd_emu10k1_ptr_write(emu, A_I2S_CAPTURE_RATE, channel, A_I2S_CAPTURE_48000); 379 324 break; 380 325 } 381 326 /* FIXME: Check emu->buffer.size before actually writing to it. */ 382 snd_emu10k1_ptr20_write(emu, 0x13, channel, 0);327 snd_emu10k1_ptr20_write(emu, CAPTURE_FIFO_POINTER, channel, 0); 383 328 snd_emu10k1_ptr20_write(emu, CAPTURE_DMA_ADDR, channel, runtime->dma_addr); 384 329 snd_emu10k1_ptr20_write(emu, CAPTURE_BUFFER_SIZE, channel, frames_to_bytes(runtime, runtime->buffer_size) << 16); // buffer size in bytes … … 412 357 } 413 358 359 static void snd_p16v_interrupt(struct snd_emu10k1 *emu) 360 { 361 unsigned int status; 362 363 while ((status = inl(emu->port + IPR2)) != 0) { 364 u32 mask = INTE2_PLAYBACK_CH_0_LOOP; /* Full Loop */ 365 366 /* dev_dbg(emu->card->dev, "p16v status=0x%x\n", status); */ 367 if (status & mask) { 368 struct snd_pcm_substream *substream = 369 emu->pcm_p16v->streams[SNDRV_PCM_STREAM_PLAYBACK].substream; 370 struct snd_pcm_runtime *runtime = substream->runtime; 371 372 if (runtime && runtime->private_data) { 373 snd_pcm_period_elapsed(substream); 374 } else { 375 dev_err(emu->card->dev, 376 "p16v: status: 0x%08x, mask=0x%08x\n", 377 status, mask); 378 } 379 } 380 if (status & 0x110000) { 381 struct snd_pcm_substream *substream = 382 emu->pcm_p16v->streams[SNDRV_PCM_STREAM_CAPTURE].substream; 383 struct snd_pcm_runtime *runtime = substream->runtime; 384 385 /* dev_info(emu->card->dev, "capture int found\n"); */ 386 if (runtime && runtime->private_data) { 387 /* dev_info(emu->card->dev, "capture period_elapsed\n"); */ 388 snd_pcm_period_elapsed(substream); 389 } 390 } 391 outl(status, emu->port + IPR2); /* ack all */ 392 } 393 } 394 414 395 /* trigger_playback callback */ 415 396 static int snd_p16v_pcm_trigger_playback(struct snd_pcm_substream *substream, … … 418 399 struct snd_emu10k1 *emu = snd_pcm_substream_chip(substream); 419 400 struct snd_pcm_runtime *runtime; 420 struct snd_emu10k1_pcm *epcm;421 401 int channel; 422 402 int result = 0; … … 440 420 continue; 441 421 runtime = s->runtime; 442 epcm = runtime->private_data;443 422 channel = substream->pcm->device-emu->p16v_device_offset; 444 423 /* dev_dbg(emu->card->dev, "p16v channel=%d\n", channel); */ 445 epcm->running =running;424 runtime->private_data = (void *)(ptrdiff_t)running; 446 425 basic |= (0x1<<channel); 447 426 inte |= (INTE2_PLAYBACK_CH_0_LOOP<<channel); … … 472 451 struct snd_emu10k1 *emu = snd_pcm_substream_chip(substream); 473 452 struct snd_pcm_runtime *runtime = substream->runtime; 474 struct snd_emu10k1_pcm *epcm = runtime->private_data;475 453 int channel = 0; 476 454 int result = 0; … … 481 459 snd_p16v_intr_enable(emu, inte); 482 460 snd_emu10k1_ptr20_write(emu, BASIC_INTERRUPT, 0, snd_emu10k1_ptr20_read(emu, BASIC_INTERRUPT, 0)|(0x100<<channel)); 483 epcm->running =1;461 runtime->private_data = (void *)1; 484 462 break; 485 463 case SNDRV_PCM_TRIGGER_STOP: … … 487 465 snd_p16v_intr_disable(emu, inte); 488 466 //snd_emu10k1_ptr20_write(emu, EXTENDED_INT_MASK, 0, snd_emu10k1_ptr20_read(emu, EXTENDED_INT_MASK, 0) & ~(0x110000<<channel)); 489 epcm->running = 0;467 runtime->private_data = NULL; 490 468 break; 491 469 default: … … 502 480 struct snd_emu10k1 *emu = snd_pcm_substream_chip(substream); 503 481 struct snd_pcm_runtime *runtime = substream->runtime; 504 struct snd_emu10k1_pcm *epcm = runtime->private_data;505 482 snd_pcm_uframes_t ptr, ptr1, ptr2,ptr3,ptr4 = 0; 506 483 int channel = substream->pcm->device - emu->p16v_device_offset; 507 if (!epcm->running) 484 485 if (!runtime->private_data) 508 486 return 0; 509 487 … … 527 505 struct snd_emu10k1 *emu = snd_pcm_substream_chip(substream); 528 506 struct snd_pcm_runtime *runtime = substream->runtime; 529 struct snd_emu10k1_pcm *epcm = runtime->private_data;530 507 snd_pcm_uframes_t ptr, ptr1, ptr2 = 0; 531 508 int channel = 0; 532 509 533 if (! epcm->running)510 if (!runtime->private_data) 534 511 return 0; 535 512 … … 592 569 strcpy(pcm->name, "p16v"); 593 570 emu->pcm_p16v = pcm; 571 emu->p16v_interrupt = snd_p16v_interrupt; 594 572 595 573 for(substream = pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream; -
GPL/trunk/alsa-kernel/pci/emu10k1/p16v.h
r679 r772 3 3 * Copyright (c) by James Courtier-Dutton <James@superbug.demon.co.uk> 4 4 * Driver p16v chips 5 * Version: 0.216 *7 * FEATURES currently supported:8 * Output fixed at S32_LE, 2 channel to hw:0,09 * Rates: 44.1, 48, 96, 192.10 *11 * Changelog:12 * 0.813 * Use separate card based buffer for periods table.14 * 0.915 * Use 2 channel output streams instead of 8 channel.16 * (8 channel output streams might be good for ASIO type output)17 * Corrected speaker output, so Front -> Front etc.18 * 0.1019 * Fixed missed interrupts.20 * 0.1121 * Add Sound card model number and names.22 * Add Analog volume controls.23 * 0.1224 * Corrected playback interrupts. Now interrupt per period, instead of half period.25 * 0.1326 * Use single trigger for multichannel.27 * 0.1428 * Mic capture now works at fixed: S32_LE, 96000Hz, Stereo.29 * 0.1530 * Force buffer_size / period_size == INTEGER.31 * 0.1632 * Update p16v.c to work with changed alsa api.33 * 0.1734 * Update p16v.c to work with changed alsa api. Removed boot_devs.35 * 0.1836 * Merging with snd-emu10k1 driver.37 * 0.1938 * One stereo channel at 24bit now works.39 * 0.2040 * Added better register defines.41 * 0.2142 * Split from p16v.c43 *44 * BUGS:45 * Some stability problems when unloading the snd-p16v kernel module.46 * --47 *48 * TODO:49 * SPDIF out.50 * Find out how to change capture sample rates. E.g. To record SPDIF at 48000Hz.51 * Currently capture fixed at 48000Hz.52 *53 * --54 * GENERAL INFO:55 * Model: SB024056 * P16V Chip: CA0151-DBS57 * Audigy 2 Chip: CA0102-IAT58 * AC97 Codec: STAC 972159 * ADC: Philips 1361T (Stereo 24bit)60 * DAC: CS4382-K (8-channel, 24bit, 192Khz)61 5 * 62 6 * This code was initially based on code from ALSA's emu10k1x.c which is: … … 65 9 66 10 /********************************************************************************************************/ 67 /* Audigy2 P16V pointer-offset register set, accessed through the PTR2 and DATA2 registers */11 /* Audigy2 P16V pointer-offset register set, accessed through the PTR2 and DATA2 registers */ 68 12 /********************************************************************************************************/ 69 13 -
GPL/trunk/alsa-kernel/pci/emu10k1/p17v.h
r679 r772 3 3 * Copyright (c) by James Courtier-Dutton <James@superbug.demon.co.uk> 4 4 * Driver p17v chips 5 * Version: 0.016 5 */ 7 6 8 7 /******************************************************************************/ 9 /* Audigy2Value Tina (P17V) pointer-offset register set, 10 * accessed through the PTR20 and DATA24 registers*/8 /* Audigy2Value Tina (P17V) pointer-offset register set, */ 9 /* accessed through the PTR2 and DATA2 registers */ 11 10 /******************************************************************************/ 12 11 -
GPL/trunk/alsa-kernel/pci/emu10k1/timer.c
r703 r772 3 3 * Copyright (c) by Lee Revell <rlrevell@joe-job.com> 4 4 * Clemens Ladisch <clemens@ladisch.de> 5 * Oswald Buddenhagen <oswald.buddenhagen@gmx.de> 6 * 5 7 * Routines for control of EMU10K1 chips 6 *7 * BUGS:8 * --9 *10 * TODO:11 * --12 8 */ 13 9 … … 19 15 { 20 16 struct snd_emu10k1 *emu; 21 unsigned long flags;22 17 unsigned int delay; 23 18 … … 26 21 if (delay < 5 ) /* minimum time is 5 ticks */ 27 22 delay = 5; 28 spin_lock_irqsave(&emu->reg_lock, flags);29 23 snd_emu10k1_intr_enable(emu, INTE_INTERVALTIMERENB); 30 24 outw(delay & TIMER_RATE_MASK, emu->port + TIMER); 31 spin_unlock_irqrestore(&emu->reg_lock, flags);32 25 return 0; 33 26 } … … 36 29 { 37 30 struct snd_emu10k1 *emu; 38 unsigned long flags;39 31 40 32 emu = snd_timer_chip(timer); 41 spin_lock_irqsave(&emu->reg_lock, flags);42 33 snd_emu10k1_intr_disable(emu, INTE_INTERVALTIMERENB); 43 spin_unlock_irqrestore(&emu->reg_lock, flags);44 34 return 0; 35 } 36 37 static unsigned long snd_emu10k1_timer_c_resolution(struct snd_timer *timer) 38 { 39 struct snd_emu10k1 *emu = snd_timer_chip(timer); 40 41 if (emu->card_capabilities->emu_model && 42 emu->emu1010.word_clock == 44100) 43 return 22676; // 1 sample @ 44.1 kHz = 22.675736...us 44 else 45 return 20833; // 1 sample @ 48 kHz = 20.833...us 45 46 } 46 47 … … 48 49 unsigned long *num, unsigned long *den) 49 50 { 51 struct snd_emu10k1 *emu = snd_timer_chip(timer); 52 50 53 *num = 1; 51 *den = 48000; 54 if (emu->card_capabilities->emu_model) 55 *den = emu->emu1010.word_clock; 56 else 57 *den = 48000; 52 58 return 0; 53 59 } … … 55 61 static const struct snd_timer_hardware snd_emu10k1_timer_hw = { 56 62 .flags = SNDRV_TIMER_HW_AUTO, 57 .resolution = 20833, /* 1 sample @ 48KHZ = 20.833...us */58 63 .ticks = 1024, 59 64 .start = snd_emu10k1_timer_start, 60 65 .stop = snd_emu10k1_timer_stop, 66 .c_resolution = snd_emu10k1_timer_c_resolution, 61 67 .precise_resolution = snd_emu10k1_timer_precise_resolution, 62 68 }; -
GPL/trunk/alsa-kernel/pci/emu10k1/tina2.h
r679 r772 3 3 * Copyright (c) by James Courtier-Dutton <James@superbug.demon.co.uk> 4 4 * Driver tina2 chips 5 * Version: 0.16 5 */ 7 6 -
GPL/trunk/alsa-kernel/pci/emu10k1/voice.c
r679 r772 2 2 /* 3 3 * Copyright (c) by Jaroslav Kysela <perex@perex.cz> 4 * Lee Revell <rlrevell@joe-job.com> 5 * Oswald Buddenhagen <oswald.buddenhagen@gmx.de> 4 6 * Creative Labs, Inc. 5 * Lee Revell <rlrevell@joe-job.com>7 * 6 8 * Routines for control of EMU10K1 chips - voice manager 7 *8 * Rewrote voice allocator for multichannel support - rlrevell 12/20049 *10 * BUGS:11 * --12 *13 * TODO:14 * --15 9 */ 16 10 … … 24 18 * the card record and each allocation begins where the last left off. The 25 19 * hardware requires stereo interleaved voices be aligned to an even/odd 26 * boundary. For multichannel voice allocation we ensure than the block of 27 * voices does not cross the 32 voice boundary. This simplifies the 28 * multichannel support and ensures we can use a single write to the 29 * (set|clear)_loop_stop registers. Otherwise (for example) the voices would 30 * get out of sync when pausing/resuming a stream. 20 * boundary. 31 21 * --rlrevell 32 22 */ 33 23 34 24 static int voice_alloc(struct snd_emu10k1 *emu, int type, int number, 35 struct snd_emu10k1_ voice **rvoice)25 struct snd_emu10k1_pcm *epcm, struct snd_emu10k1_voice **rvoice) 36 26 { 37 27 struct snd_emu10k1_voice *voice; 38 int i, j, k, first_voice, last_voice,skip;28 int i, j, k, skip; 39 29 40 *rvoice = NULL; 41 first_voice = last_voice = 0; 42 for (i = emu->next_free_voice, j = 0; j < NUM_G ; i += number, j += number) { 30 for (i = emu->next_free_voice, j = 0; j < NUM_G; i = (i + skip) % NUM_G, j += skip) { 43 31 /* 44 32 dev_dbg(emu->card->dev, "i %d j %d next free %d!\n", 45 33 i, j, emu->next_free_voice); 46 34 */ 47 i %= NUM_G;48 35 49 36 /* stereo voices must be even/odd */ 50 if ((number == 2) && (i % 2)) {51 i++;37 if ((number > 1) && (i % 2)) { 38 skip = 1; 52 39 continue; 53 40 } 54 55 skip = 0; 41 56 42 for (k = 0; k < number; k++) { 57 voice = &emu->voices[ (i+k) % NUM_G];43 voice = &emu->voices[i + k]; 58 44 if (voice->use) { 59 skip = 1;60 break;45 skip = k + 1; 46 goto next; 61 47 } 62 48 } 63 if (!skip) { 64 /* dev_dbg(emu->card->dev, "allocated voice %d\n", i); */65 first_voice = i;66 last_voice = (i + number) % NUM_G;67 emu->next_free_voice = last_voice;68 break;49 50 for (k = 0; k < number; k++) { 51 voice = &emu->voices[i + k]; 52 voice->use = type; 53 voice->epcm = epcm; 54 /* dev_dbg(emu->card->dev, "allocated voice %d\n", i + k); */ 69 55 } 56 voice->last = 1; 57 58 *rvoice = &emu->voices[i]; 59 emu->next_free_voice = (i + number) % NUM_G; 60 return 0; 61 62 next: ; 70 63 } 71 72 if (first_voice == last_voice) 73 return -ENOMEM; 74 75 for (i = 0; i < number; i++) { 76 voice = &emu->voices[(first_voice + i) % NUM_G]; 77 /* 78 dev_dbg(emu->card->dev, "voice alloc - %i, %i of %i\n", 79 voice->number, idx-first_voice+1, number); 80 */ 81 voice->use = 1; 82 switch (type) { 83 case EMU10K1_PCM: 84 voice->pcm = 1; 85 break; 86 case EMU10K1_SYNTH: 87 voice->synth = 1; 88 break; 89 case EMU10K1_MIDI: 90 voice->midi = 1; 91 break; 92 case EMU10K1_EFX: 93 voice->efx = 1; 94 break; 95 } 96 } 97 *rvoice = &emu->voices[first_voice]; 98 return 0; 64 return -ENOMEM; // -EBUSY would have been better 99 65 } 100 66 101 int snd_emu10k1_voice_alloc(struct snd_emu10k1 *emu, int type, int number, 102 struct snd_emu10k1_voice **rvoice) 67 static void voice_free(struct snd_emu10k1 *emu, 68 struct snd_emu10k1_voice *pvoice) 69 { 70 if (pvoice->dirty) 71 snd_emu10k1_voice_init(emu, pvoice->number); 72 pvoice->interrupt = NULL; 73 pvoice->use = pvoice->dirty = pvoice->last = 0; 74 pvoice->epcm = NULL; 75 } 76 77 int snd_emu10k1_voice_alloc(struct snd_emu10k1 *emu, int type, int count, int channels, 78 struct snd_emu10k1_pcm *epcm, struct snd_emu10k1_voice **rvoice) 103 79 { 104 80 unsigned long flags; … … 107 83 if (snd_BUG_ON(!rvoice)) 108 84 return -EINVAL; 109 if (snd_BUG_ON(!number)) 85 if (snd_BUG_ON(!count)) 86 return -EINVAL; 87 if (snd_BUG_ON(!channels)) 110 88 return -EINVAL; 111 89 112 90 spin_lock_irqsave(&emu->voice_lock, flags); 113 for (;;) { 114 result = voice_alloc(emu, type, number, rvoice); 115 if (result == 0 || type == EMU10K1_SYNTH || type == EMU10K1_MIDI) 116 break; 117 118 /* free a voice from synth */ 119 if (emu->get_synth_voice) { 91 for (int got = 0; got < channels; ) { 92 result = voice_alloc(emu, type, count, epcm, &rvoice[got]); 93 if (result == 0) { 94 got++; 95 /* 96 dev_dbg(emu->card->dev, "voice alloc - %i, %i of %i\n", 97 rvoice[got - 1]->number, got, want); 98 */ 99 continue; 100 } 101 if (type != EMU10K1_SYNTH && emu->get_synth_voice) { 102 /* free a voice from synth */ 120 103 result = emu->get_synth_voice(emu); 121 104 if (result >= 0) { 122 struct snd_emu10k1_voice *pvoice = &emu->voices[result]; 123 pvoice->interrupt = NULL; 124 pvoice->use = pvoice->pcm = pvoice->synth = pvoice->midi = pvoice->efx = 0; 125 pvoice->epcm = NULL; 105 voice_free(emu, &emu->voices[result]); 106 continue; 126 107 } 127 108 } 128 if (result < 0) 129 break; 109 for (int i = 0; i < got; i++) { 110 for (int j = 0; j < count; j++) 111 voice_free(emu, rvoice[i] + j); 112 rvoice[i] = NULL; 113 } 114 break; 130 115 } 131 116 spin_unlock_irqrestore(&emu->voice_lock, flags); … … 140 125 { 141 126 unsigned long flags; 127 int last; 142 128 143 129 if (snd_BUG_ON(!pvoice)) 144 130 return -EINVAL; 145 131 spin_lock_irqsave(&emu->voice_lock, flags); 146 pvoice->interrupt = NULL;147 pvoice->use = pvoice->pcm = pvoice->synth = pvoice->midi = pvoice->efx = 0;148 pvoice->epcm = NULL;149 snd_emu10k1_voice_init(emu, pvoice->number);132 do { 133 last = pvoice->last; 134 voice_free(emu, pvoice++); 135 } while (!last); 150 136 spin_unlock_irqrestore(&emu->voice_lock, flags); 151 137 return 0;
Note:
See TracChangeset
for help on using the changeset viewer.
