Changeset 772 for GPL/trunk/alsa-kernel/include/sound/emu10k1.h
- Timestamp:
- Apr 19, 2025, 8:08:37 PM (4 months ago)
- Location:
- GPL/trunk
- Files:
-
- 2 edited
-
. (modified) (1 prop)
-
alsa-kernel/include/sound/emu10k1.h (modified) (75 diffs)
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GPL/trunk
- Property svn:mergeinfo changed
/GPL/branches/uniaud32-6.6-LTS (added) merged: 765,768-769 /GPL/branches/uniaud32-exp (added) merged: 735-741,743-744,748-751,753-760,762-764 /GPL/branches/uniaud32-next merged: 718-734
- Property svn:mergeinfo changed
-
GPL/trunk/alsa-kernel/include/sound/emu10k1.h
r717 r772 26 26 27 27 #define EMUPAGESIZE 4096 28 #define MAXREQVOICES 829 28 #define MAXPAGES0 4096 /* 32 bit mode */ 30 29 #define MAXPAGES1 8192 /* 31 bit mode */ 31 #define RESERVED 032 #define NUM_MIDI 1633 30 #define NUM_G 64 /* use all channels */ 34 #define NUM_FXSENDS 435 31 #define NUM_EFX_PLAYBACK 16 36 32 … … 40 36 41 37 #define TMEMSIZE 256*1024 42 #define TMEMSIZEREG 443 38 44 39 #define IP_TO_CP(ip) ((ip == 0) ? 0 : (((0x00001000uL | (ip & 0x00000FFFL)) << (((ip >> 12) & 0x000FL) + 4)) & 0xFFFF0000uL)) 40 41 // This is used to define hardware bit-fields (sub-registers) by combining 42 // the bit shift and count with the actual register address. The passed 43 // mask must represent a single run of adjacent bits. 44 // The non-concatenating (_NC) variant should be used directly only for 45 // sub-registers that do not follow the <register>_<field> naming pattern. 46 #define SUB_REG_NC(reg, field, mask) \ 47 enum { \ 48 field ## _MASK = mask, \ 49 field = reg | \ 50 (__builtin_ctz(mask) << 16) | \ 51 (__builtin_popcount(mask) << 24), \ 52 }; 53 #define SUB_REG(reg, field, mask) SUB_REG_NC(reg, reg ## _ ## field, mask) 54 55 // Macros for manipulating values of bit-fields declared using the above macros. 56 // Best used with constant register addresses, as otherwise quite some code is 57 // generated. The actual register read/write functions handle combined addresses 58 // automatically, so use of these macros conveys no advantage when accessing a 59 // single sub-register at a time. 60 #define REG_SHIFT(r) (((r) >> 16) & 0x1f) 61 #define REG_SIZE(r) (((r) >> 24) & 0x1f) 62 #define REG_MASK0(r) ((1U << REG_SIZE(r)) - 1U) 63 #define REG_MASK(r) (REG_MASK0(r) << REG_SHIFT(r)) 64 #define REG_VAL_GET(r, v) ((v & REG_MASK(r)) >> REG_SHIFT(r)) 65 #define REG_VAL_PUT(r, v) ((v) << REG_SHIFT(r)) 66 67 // List terminator for snd_emu10k1_ptr_write_multiple() 68 #define REGLIST_END ~0 45 69 46 70 // Audigy specify registers are prefixed with 'A_' … … 67 91 #define IPR_P16V 0x80000000 /* Bit set when the CA0151 P16V chip wishes 68 92 to interrupt */ 69 #define IPR_ GPIOMSG 0x20000000 /* GPIO message interrupt (RE'd, still not sure70 which INTE bits enable it)*/93 #define IPR_WATERMARK_REACHED 0x40000000 94 #define IPR_A_GPIO 0x20000000 /* GPIO input pin change */ 71 95 72 96 /* The next two interrupts are for the midi port on the Audigy Drive (A_MPU1) */ … … 96 120 #define IPR_MIDIRECVBUFEMPTY 0x00000080 /* MIDI UART receive buffer empty */ 97 121 #define IPR_CHANNELLOOP 0x00000040 /* Channel (half) loop interrupt(s) pending */ 122 /* The interrupt is triggered shortly after */ 123 /* CCR_READADDRESS has crossed the boundary; */ 124 /* due to the cache, this runs ahead of the */ 125 /* actual playback position. */ 98 126 #define IPR_CHANNELNUMBERMASK 0x0000003f /* When IPR_CHANNELLOOP is set, indicates the */ 99 127 /* highest set channel in CLIPL, CLIPH, HLIPL, */ 100 /* or HLIPH. When IP is written with CL set, */128 /* or HLIPH. When IPR is written with CL set, */ 101 129 /* the bit in H/CLIPL or H/CLIPH corresponding */ 102 /* to the C IN value written will be cleared. */130 /* to the CN value written will be cleared. */ 103 131 104 132 #define INTE 0x0c /* Interrupt enable register */ … … 128 156 /* lockups if enabled. */ 129 157 158 #define INTE_A_GPIOENABLE 0x00040000 /* Enable GPIO input change interrupts */ 159 130 160 /* The next two interrupts are for the midi port on the Audigy Drive (A_MPU1) */ 131 161 #define INTE_A_MIDITXENABLE2 0x00020000 /* Enable MIDI transmit-buffer-empty interrupts */ 132 162 #define INTE_A_MIDIRXENABLE2 0x00010000 /* Enable MIDI receive-buffer-empty interrupts */ 133 163 164 #define INTE_A_SPDIF_BUFFULL_ENABLE 0x00008000 165 #define INTE_A_SPDIF_HALFBUFFULL_ENABLE 0x00004000 134 166 135 167 #define INTE_SAMPLERATETRACKER 0x00002000 /* Enable sample rate tracker interrupts */ … … 150 182 151 183 #define WC 0x10 /* Wall Clock register */ 184 #ifndef TARGET_OS2 185 SUB_REG(WC, SAMPLECOUNTER, 0x03FFFFC0) /* Sample periods elapsed since reset */ 186 SUB_REG(WC, CURRENTCHANNEL, 0x0000003F) /* Channel [0..63] currently being serviced */ 187 /* NOTE: Each channel takes 1/64th of a sample */ 188 /* period to be serviced. */ 189 190 #else 152 191 #define WC_SAMPLECOUNTER_MASK 0x03FFFFC0 /* Sample periods elapsed since reset */ 153 192 #define WC_SAMPLECOUNTER 0x14060010 154 #define WC_CURRENTCHANNEL 0x0 000003F /* Channel [0..63] currently being serviced */193 #define WC_CURRENTCHANNEL 0x0700003F /* Channel [0..63] currently being serviced */ 155 194 /* NOTE: Each channel takes 1/64th of a sample */ 156 195 /* period to be serviced. */ 157 196 #endif 158 197 #define HCFG 0x14 /* Hardware config register */ 159 198 /* NOTE: There is no reason to use the legacy */ … … 181 220 182 221 /* Specific to Alice2, CA0102 */ 222 183 223 #define HCFG_CODECFORMAT_AC97_1 0x00000000 /* AC97 CODEC format -- Ver 1.03 */ 184 224 #define HCFG_CODECFORMAT_AC97_2 0x00010000 /* AC97 CODEC format -- Ver 2.1 */ … … 201 241 /* Rest of HCFG 0x0000000f same as below. LOCKSOUNDCACHE etc. */ 202 242 203 204 205 243 /* Older chips */ 244 206 245 #define HCFG_CODECFORMAT_AC97 0x00000000 /* AC97 CODEC format -- Primary Output */ 207 246 #define HCFG_CODECFORMAT_I2S 0x00010000 /* I2S CODEC format -- Secondary (Rear) Output */ … … 226 265 #define HCFG_LOCKSOUNDCACHE 0x00000008 /* 1 = Cancel bustmaster accesses to soundcache */ 227 266 /* NOTE: This should generally never be used. */ 267 #ifndef TARGET_OS2 268 SUB_REG(HCFG, LOCKTANKCACHE, 0x00000004) /* 1 = Cancel bustmaster accesses to tankcache */ 269 /* NOTE: This should generally never be used. */ 270 #else 228 271 #define HCFG_LOCKTANKCACHE_MASK 0x00000004 /* 1 = Cancel bustmaster accesses to tankcache */ 229 272 /* NOTE: This should generally never be used. */ 230 273 #define HCFG_LOCKTANKCACHE 0x01020014 274 #endif 231 275 #define HCFG_MUTEBUTTONENABLE 0x00000002 /* 1 = Master mute button sets AUDIOENABLE = 0. */ 232 276 /* NOTE: This is a 'cheap' way to implement a */ … … 239 283 /* completely initialized. */ 240 284 241 // For Audigy, MPU port move to 0x70-0x74 ptr register285 // On Audigy, the MPU port moved to the 0x70-0x74 ptr registers 242 286 243 287 #define MUDATA 0x18 /* MPU401 data register (8 bits) */ … … 252 296 #define MUSTAT_ORDYN 0x40 /* 0 = MUDATA can accept a command or data */ 253 297 254 #define A_IOCFG 0x18 /* GPIO on Audigy card (16bits) */ 255 #define A_GPINPUT_MASK 0xff00 298 #define A_GPIO 0x18 /* GPIO on Audigy card (16bits) */ 299 #define A_GPINPUT_MASK 0xff00 /* Alice/2 has 8 input pins */ 300 #define A3_GPINPUT_MASK 0x3f00 /* ... while Tina/2 has only 6 */ 256 301 #define A_GPOUTPUT_MASK 0x00ff 257 302 303 // The GPIO port is used for I/O config on Sound Blasters; 304 // card-specific info can be found in the emu_chip_details table. 305 // On E-MU cards the port is used as the interface to the FPGA. 306 258 307 // Audigy output/GPIO stuff taken from the kX drivers 308 #define A_IOCFG A_GPIO 259 309 #define A_IOCFG_GPOUT0 0x0044 /* analog/digital */ 260 310 #define A_IOCFG_DISABLE_ANALOG 0x0040 /* = 'enable' for Audigy2 (chiprev=4) */ … … 272 322 #define A_IOCFG_PHONES_JACK 0x0100 /* LiveDrive */ 273 323 274 /* outputs:275 * for audigy2 platinum: 0xa00276 * for a2 platinum ex: 0x1c00277 * for a1 platinum: 0x0278 */279 280 324 #define TIMER 0x1a /* Timer terminal count register */ 281 325 /* NOTE: After the rate is changed, a maximum */ 282 326 /* of 1024 sample periods should be allowed */ 283 327 /* before the new rate is guaranteed accurate. */ 284 #define TIMER_RATE_MASK 0x0 00003ff/* Timer interrupt rate in sample periods */328 #define TIMER_RATE_MASK 0x03ff /* Timer interrupt rate in sample periods */ 285 329 /* 0 == 1024 periods, [1..4] are not useful */ 286 #define TIMER_RATE 0x0a00001a287 330 288 331 #define AC97DATA 0x1c /* AC97 register set data register (16 bit) */ … … 318 361 /* 0x00000200 8-channel output. */ 319 362 /* 0x00000004 pauses stream/irq fail. */ 320 /* Rest of bits no nothing to sound output */363 /* Rest of bits do nothing to sound output */ 321 364 /* bit 0: Enable P16V audio. 322 365 * bit 1: Lock P16V record memory cache. … … 332 375 #define IPR3 0x38 /* Cdif interrupt pending register */ 333 376 #define INTE3 0x3c /* Cdif interrupt enable register. */ 377 334 378 /************************************************************************************************/ 335 379 /* PCI function 1 registers, address = <val> + PCIBASE1 */ … … 350 394 #define JOYSTICK_COMPARATOR 0xf0 /* Joystick comparator data */ 351 395 352 353 396 /********************************************************************************************************/ 354 397 /* Emu10k1 pointer-offset register set, accessed through the PTR and DATA registers */ 355 398 /********************************************************************************************************/ 356 399 400 // No official documentation was released for EMU10K1, but some info 401 // about playback can be extrapolated from the EMU8K documents: 402 // "AWE32/EMU8000 Programmerâs Guide" (emu8kpgm.pdf) - registers 403 // "AWE32 Developer's Information Pack" (adip301.pdf) - high-level view 404 405 // The short version: 406 // - The engine has 64 playback channels, also called voices. The channels 407 // operate independently, except when paired for stereo (see below). 408 // - PCM samples are fetched into the cache; see description of CD0 below. 409 // - Samples are consumed at the rate CPF_CURRENTPITCH. 410 // - 8-bit samples are transformed upon use: cooked = (raw ^ 0x80) << 8 411 // - 8 samples are read at CCR_READADDRESS:CPF_FRACADDRESS and interpolated 412 // according to CCCA_INTERPROM_*. With CCCA_INTERPROM_0 selected and a zero 413 // CPF_FRACADDRESS, this results in CCR_READADDRESS[3] being used verbatim. 414 // - The value is multiplied by CVCF_CURRENTVOL. 415 // - The value goes through a filter with cutoff CVCF_CURRENTFILTER; 416 // delay stages Z1 and Z2. 417 // - The value is added by so-called `sends` to 4 (EMU10K1) / 8 (EMU10K2) 418 // of the 16 (EMU10K1) / 64 (EMU10K2) FX bus accumulators via FXRT*, 419 // multiplied by a per-send amount (*_FXSENDAMOUNT_*). 420 // The scaling of the send amounts is exponential-ish. 421 // - The DSP has a go at FXBUS* and outputs the values to EXTOUT* or EMU32OUT*. 422 // - The pitch, volume, and filter cutoff can be modulated by two envelope 423 // engines and two low frequency oscillators. 424 // - To avoid abrupt changes to the parameters (which may cause audible 425 // distortion), the modulation engine sets the target registers, towards 426 // which the current registers "swerve" gradually. 427 428 // For the odd channel in a stereo pair, these registers are meaningless: 429 // CPF_STEREO, CPF_CURRENTPITCH, PTRX_PITCHTARGET, CCR_CACHEINVALIDSIZE, 430 // PSST_LOOPSTARTADDR, DSL_LOOPENDADDR, CCCA_CURRADDR 431 // The somewhat non-obviously still meaningful ones are: 432 // CPF_STOP, CPF_FRACADDRESS, CCR_READADDRESS (!), 433 // CCCA_INTERPROM, CCCA_8BITSELECT (!) 434 // (The envelope engine is ignored here, as stereo matters only for verbatim playback.) 435 357 436 #define CPF 0x00 /* Current pitch and fraction register */ 437 #ifndef TARGET_OS2 438 SUB_REG(CPF, CURRENTPITCH, 0xffff0000) /* Current pitch (linear, 0x4000 == unity pitch shift) */ 439 #else 358 440 #define CPF_CURRENTPITCH_MASK 0xffff0000 /* Current pitch (linear, 0x4000 == unity pitch shift) */ 359 441 #define CPF_CURRENTPITCH 0x10100000 442 #endif 360 443 #define CPF_STEREO_MASK 0x00008000 /* 1 = Even channel interleave, odd channel locked */ 444 #ifndef TARGET_OS2 445 SUB_REG(CPF, STOP, 0x00004000) /* 1 = Current pitch forced to 0 */ 446 /* Can be set only while matching bit in SOLEx is 1 */ 447 #else 448 #define CPF_STOP 0x00004000 /* 1 = Current pitch forced to 0 */ 361 449 #define CPF_STOP_MASK 0x00004000 /* 1 = Current pitch forced to 0 */ 450 #endif 362 451 #define CPF_FRACADDRESS_MASK 0x00003fff /* Linear fractional address of the current channel */ 363 452 364 453 #define PTRX 0x01 /* Pitch target and send A/B amounts register */ 454 #ifndef TARGET_OS2 455 SUB_REG(PTRX, PITCHTARGET, 0xffff0000) /* Pitch target of specified channel */ 456 SUB_REG(PTRX, FXSENDAMOUNT_A, 0x0000ff00) /* Linear level of channel output sent to FX send bus A */ 457 SUB_REG(PTRX, FXSENDAMOUNT_B, 0x000000ff) /* Linear level of channel output sent to FX send bus B */ 458 #else 365 459 #define PTRX_PITCHTARGET_MASK 0xffff0000 /* Pitch target of specified channel */ 366 460 #define PTRX_PITCHTARGET 0x10100001 … … 369 463 #define PTRX_FXSENDAMOUNT_B_MASK 0x000000ff /* Linear level of channel output sent to FX send bus B */ 370 464 #define PTRX_FXSENDAMOUNT_B 0x08000001 371 465 #endif 466 467 // Note: the volumes are raw multpliers, so real 100% is impossible. 372 468 #define CVCF 0x02 /* Current volume and filter cutoff register */ 469 #ifndef TARGET_OS2 470 SUB_REG(CVCF, CURRENTVOL, 0xffff0000) /* Current linear volume of specified channel */ 471 SUB_REG(CVCF, CURRENTFILTER, 0x0000ffff) /* Current filter cutoff frequency of specified channel */ 472 #else 373 473 #define CVCF_CURRENTVOL_MASK 0xffff0000 /* Current linear volume of specified channel */ 374 474 #define CVCF_CURRENTVOL 0x10100002 375 475 #define CVCF_CURRENTFILTER_MASK 0x0000ffff /* Current filter cutoff frequency of specified channel */ 376 476 #define CVCF_CURRENTFILTER 0x10000002 477 #endif 377 478 378 479 #define VTFT 0x03 /* Volume target and filter cutoff target register */ 480 #ifndef TARGET_OS2 481 SUB_REG(VTFT, VOLUMETARGET, 0xffff0000) /* Volume target of specified channel */ 482 SUB_REG(VTFT, FILTERTARGET, 0x0000ffff) /* Filter cutoff target of specified channel */ 483 #else 379 484 #define VTFT_VOLUMETARGET_MASK 0xffff0000 /* Volume target of specified channel */ 380 485 #define VTFT_VOLUMETARGET 0x10100003 381 486 #define VTFT_FILTERTARGET_MASK 0x0000ffff /* Filter cutoff target of specified channel */ 382 487 #define VTFT_FILTERTARGET 0x10000003 488 #endif 383 489 384 490 #define Z1 0x05 /* Filter delay memory 1 register */ … … 387 493 388 494 #define PSST 0x06 /* Send C amount and loop start address register */ 495 #ifndef TARGET_OS2 496 SUB_REG(PSST, FXSENDAMOUNT_C, 0xff000000) /* Linear level of channel output sent to FX send bus C */ 497 SUB_REG(PSST, LOOPSTARTADDR, 0x00ffffff) /* Loop start address of the specified channel */ 498 #else 389 499 #define PSST_FXSENDAMOUNT_C_MASK 0xff000000 /* Linear level of channel output sent to FX send bus C */ 390 500 … … 393 503 #define PSST_LOOPSTARTADDR_MASK 0x00ffffff /* Loop start address of the specified channel */ 394 504 #define PSST_LOOPSTARTADDR 0x18000006 395 396 #define DSL 0x07 /* Send D amount and loop start address register */ 505 #endif 506 507 #define DSL 0x07 /* Send D amount and loop end address register */ 508 #ifndef TARGET_OS2 509 SUB_REG(DSL, FXSENDAMOUNT_D, 0xff000000) /* Linear level of channel output sent to FX send bus D */ 510 SUB_REG(DSL, LOOPENDADDR, 0x00ffffff) /* Loop end address of the specified channel */ 511 #else 397 512 #define DSL_FXSENDAMOUNT_D_MASK 0xff000000 /* Linear level of channel output sent to FX send bus D */ 398 513 … … 401 516 #define DSL_LOOPENDADDR_MASK 0x00ffffff /* Loop end address of the specified channel */ 402 517 #define DSL_LOOPENDADDR 0x18000007 518 #endif 403 519 404 520 #define CCCA 0x08 /* Filter Q, interp. ROM, byte size, cur. addr register */ 521 #ifndef TARGET_OS2 522 SUB_REG(CCCA, RESONANCE, 0xf0000000) /* Lowpass filter resonance (Q) height */ 523 #else 405 524 #define CCCA_RESONANCE 0xf0000000 /* Lowpass filter resonance (Q) height */ 406 #define CCCA_INTERPROMMASK 0x0e000000 /* Selects passband of interpolation ROM */ 525 #endif 526 #define CCCA_INTERPROM_MASK 0x0e000000 /* Selects passband of interpolation ROM */ 407 527 /* 1 == full band, 7 == lowpass */ 408 528 /* ROM 0 is used when pitch shifting downward or less */ … … 419 539 #define CCCA_INTERPROM_7 0x0e000000 /* Select interpolation ROM 7 */ 420 540 #define CCCA_8BITSELECT 0x01000000 /* 1 = Sound memory for this channel uses 8-bit samples */ 541 /* 8-bit samples are unsigned, 16-bit ones signed */ 542 #ifndef TARGET_OS2 543 SUB_REG(CCCA, CURRADDR, 0x00ffffff) /* Current address of the selected channel */ 544 #else 421 545 #define CCCA_CURRADDR_MASK 0x00ffffff /* Current address of the selected channel */ 422 546 #define CCCA_CURRADDR 0x18000008 547 #endif 423 548 424 549 #define CCR 0x09 /* Cache control register */ 550 #ifndef TARGET_OS2 551 SUB_REG(CCR, CACHEINVALIDSIZE, 0xfe000000) /* Number of invalid samples before the read address */ 552 #else 425 553 #define CCR_CACHEINVALIDSIZE 0x07190009 426 554 #define CCR_CACHEINVALIDSIZE_MASK 0xfe000000 /* Number of invalid samples cache for this channel */ 555 #endif 427 556 #define CCR_CACHELOOPFLAG 0x01000000 /* 1 = Cache has a loop service pending */ 428 557 #define CCR_INTERLEAVEDSAMPLES 0x00800000 /* 1 = A cache service will fetch interleaved samples */ 558 /* Auto-set from CPF_STEREO_MASK */ 429 559 #define CCR_WORDSIZEDSAMPLES 0x00400000 /* 1 = A cache service will fetch word sized samples */ 560 /* Auto-set from CCCA_8BITSELECT */ 561 #ifndef TARGET_OS2 562 SUB_REG(CCR, READADDRESS, 0x003f0000) /* Next cached sample to play */ 563 SUB_REG(CCR, LOOPINVALSIZE, 0x0000fe00) /* Number of invalid samples in cache prior to loop */ 564 #else 430 565 #define CCR_READADDRESS 0x06100009 431 566 #define CCR_READADDRESS_MASK 0x003f0000 /* Location of cache just beyond current cache service */ 432 567 #define CCR_LOOPINVALSIZE 0x0000fe00 /* Number of invalid samples in cache prior to loop */ 433 568 /* NOTE: This is valid only if CACHELOOPFLAG is set */ 569 #endif 570 /* NOTE: This is valid only if CACHELOOPFLAG is set */ 434 571 #define CCR_LOOPFLAG 0x00000100 /* Set for a single sample period when a loop occurs */ 572 #ifndef TARGET_OS2 573 SUB_REG(CCR, CACHELOOPADDRHI, 0x000000ff) /* CLP_LOOPSTARTADDR's hi byte if CACHELOOPFLAG is set */ 574 #else 435 575 #define CCR_CACHELOOPADDRHI 0x000000ff /* DSL_LOOPSTARTADDR's hi byte if CACHELOOPFLAG is set */ 576 #endif 436 577 437 578 #define CLP 0x0a /* Cache loop register (valid if CCR_CACHELOOPFLAG = 1) */ 438 579 /* NOTE: This register is normally not used */ 580 #ifndef TARGET_OS2 581 SUB_REG(CLP, CACHELOOPADDR, 0x0000ffff) /* Cache loop address low word */ 582 #else 439 583 #define CLP_CACHELOOPADDR 0x0000ffff /* Cache loop address (DSL_LOOPSTARTADDR [0..15]) */ 584 #endif 440 585 441 586 #define FXRT 0x0b /* Effects send routing register */ … … 447 592 #define FXRT_CHANNELD 0xf0000000 /* Effects send bus number for channel's effects send D */ 448 593 449 #define A_HR 0x0b /* High Resolution. 24bit playback from host to DSP. */450 594 #define MAPA 0x0c /* Cache map A */ 451 452 595 #define MAPB 0x0d /* Cache map B */ 453 596 … … 458 601 #define MAP_PTI_MASK1 0x00001fff /* The 13 bit index to one of the 8192 PTE dwords */ 459 602 460 /* 0x0e, 0x0f: Not used*/603 /* 0x0e, 0x0f: Internal state, at least on Audigy */ 461 604 462 605 #define ENVVOL 0x10 /* Volume envelope register */ 463 #define ENVVOL_MASK 0x0000ffff /* Current value of volume envelope state variable */ 606 #define ENVVOL_MASK 0x0000ffff /* Current value of volume envelope state variable */ 464 607 /* 0x8000-n == 666*n usec delay */ 465 608 466 609 #define ATKHLDV 0x11 /* Volume envelope hold and attack register */ 467 #define ATKHLDV_PHASE0 610 #define ATKHLDV_PHASE0_MASK 0x00008000 /* 0 = Begin attack phase */ 468 611 #define ATKHLDV_HOLDTIME_MASK 0x00007f00 /* Envelope hold time (127-n == n*88.2msec) */ 469 612 #define ATKHLDV_ATTACKTIME_MASK 0x0000007f /* Envelope attack time, log encoded */ … … 471 614 472 615 #define DCYSUSV 0x12 /* Volume envelope sustain and decay register */ 473 #define DCYSUSV_PHASE1_MASK 0x00008000 /* 0 = Begin attackphase, 1 = begin release phase */616 #define DCYSUSV_PHASE1_MASK 0x00008000 /* 0 = Begin decay phase, 1 = begin release phase */ 474 617 #define DCYSUSV_SUSTAINLEVEL_MASK 0x00007f00 /* 127 = full, 0 = off, 0.75dB increments */ 475 #define DCYSUSV_CHANNELENABLE_MASK 0x00000080 /* 1= Inhibit envelope engine from writing values in */618 #define DCYSUSV_CHANNELENABLE_MASK 0x00000080 /* 0 = Inhibit envelope engine from writing values in */ 476 619 /* this channel and from writing to pitch, filter and */ 477 620 /* volume targets. */ … … 488 631 489 632 #define ATKHLDM 0x15 /* Modulation envelope hold and attack register */ 490 #define ATKHLDM_PHASE0 633 #define ATKHLDM_PHASE0_MASK 0x00008000 /* 0 = Begin attack phase */ 491 634 #define ATKHLDM_HOLDTIME 0x00007f00 /* Envelope hold time (127-n == n*42msec) */ 492 635 #define ATKHLDM_ATTACKTIME 0x0000007f /* Envelope attack time, log encoded */ … … 494 637 495 638 #define DCYSUSM 0x16 /* Modulation envelope decay and sustain register */ 496 #define DCYSUSM_PHASE1_MASK 0x00008000 /* 0 = Begin attackphase, 1 = begin release phase */639 #define DCYSUSM_PHASE1_MASK 0x00008000 /* 0 = Begin decay phase, 1 = begin release phase */ 497 640 #define DCYSUSM_SUSTAINLEVEL_MASK 0x00007f00 /* 127 = full, 0 = off, 0.75dB increments */ 498 641 #define DCYSUSM_DECAYTIME_MASK 0x0000007f /* Envelope decay time, log encoded */ … … 509 652 510 653 #define IFATN 0x19 /* Initial filter cutoff and attenuation register */ 654 #ifndef TARGET_OS2 655 SUB_REG(IFATN, FILTERCUTOFF, 0x0000ff00) /* Initial filter cutoff frequency in exponential units */ 656 /* 6 most significant bits are semitones */ 657 /* 2 least significant bits are fractions */ 658 SUB_REG(IFATN, ATTENUATION, 0x000000ff) /* Initial attenuation in 0.375dB steps */ 659 660 #else 511 661 #define IFATN_FILTERCUTOFF_MASK 0x0000ff00 /* Initial filter cutoff frequency in exponential units */ 512 662 /* 6 most significant bits are semitones */ … … 515 665 #define IFATN_ATTENUATION_MASK 0x000000ff /* Initial attenuation in 0.375dB steps */ 516 666 #define IFATN_ATTENUATION 0x08000019 517 518 667 #endif 519 668 #define PEFE 0x1a /* Pitch envelope and filter envelope amount register */ 669 #ifndef TARGET_OS2 670 SUB_REG(PEFE, PITCHAMOUNT, 0x0000ff00) /* Pitch envlope amount */ 671 /* Signed 2's complement, +/- one octave peak extremes */ 672 SUB_REG(PEFE, FILTERAMOUNT, 0x000000ff) /* Filter envlope amount */ 673 /* Signed 2's complement, +/- six octaves peak extremes */ 674 #else 520 675 #define PEFE_PITCHAMOUNT_MASK 0x0000ff00 /* Pitch envlope amount */ 521 676 /* Signed 2's complement, +/- one octave peak extremes */ … … 524 679 /* Signed 2's complement, +/- six octaves peak extremes */ 525 680 #define PEFE_FILTERAMOUNT 0x0800001a 681 #endif 682 683 526 684 #define FMMOD 0x1b /* Vibrato/filter modulation from LFO register */ 527 685 #define FMMOD_MODVIBRATO 0x0000ff00 /* Vibrato LFO modulation depth */ … … 530 688 /* Signed 2's complement, +/- three octave extremes */ 531 689 532 533 690 #define TREMFRQ 0x1c /* Tremolo amount and modulation LFO frequency register */ 534 691 #define TREMFRQ_DEPTH 0x0000ff00 /* Tremolo depth */ 535 692 /* Signed 2's complement, with +/- 12dB extremes */ 536 537 693 #define TREMFRQ_FREQUENCY 0x000000ff /* Tremolo LFO frequency */ 538 694 /* ??Hz steps, maximum of ?? Hz. */ 695 539 696 #define FM2FRQ2 0x1d /* Vibrato amount and vibrato LFO frequency register */ 540 697 #define FM2FRQ2_DEPTH 0x0000ff00 /* Vibrato LFO vibrato depth */ … … 550 707 /* 0x1f: not used */ 551 708 552 #define CD0 0x20 /* Cache data 0 register */ 553 #define CD1 0x21 /* Cache data 1 register */ 554 #define CD2 0x22 /* Cache data 2 register */ 555 #define CD3 0x23 /* Cache data 3 register */ 556 #define CD4 0x24 /* Cache data 4 register */ 557 #define CD5 0x25 /* Cache data 5 register */ 558 #define CD6 0x26 /* Cache data 6 register */ 559 #define CD7 0x27 /* Cache data 7 register */ 560 #define CD8 0x28 /* Cache data 8 register */ 561 #define CD9 0x29 /* Cache data 9 register */ 562 #define CDA 0x2a /* Cache data A register */ 563 #define CDB 0x2b /* Cache data B register */ 564 #define CDC 0x2c /* Cache data C register */ 565 #define CDD 0x2d /* Cache data D register */ 566 #define CDE 0x2e /* Cache data E register */ 567 #define CDF 0x2f /* Cache data F register */ 568 569 /* 0x30-3f seem to be the same as 0x20-2f */ 709 // 32 cache registers (== 128 bytes) per channel follow. 710 // In stereo mode, the two channels' caches are concatenated into one, 711 // and hold the interleaved frames. 712 // The cache holds 64 frames, so the upper half is not used in 8-bit mode. 713 // All registers mentioned below count in frames. 714 // The cache is a ring buffer; CCR_READADDRESS operates modulo 64. 715 // The cache is filled from (CCCA_CURRADDR - CCR_CACHEINVALIDSIZE) 716 // into (CCR_READADDRESS - CCR_CACHEINVALIDSIZE). 717 // The engine has a fetch threshold of 32 bytes, so it tries to keep 718 // CCR_CACHEINVALIDSIZE below 8 (16-bit stereo), 16 (16-bit mono, 719 // 8-bit stereo), or 32 (8-bit mono). The actual transfers are pretty 720 // unpredictable, especially if several voices are running. 721 // Frames are consumed at CCR_READADDRESS, which is incremented afterwards, 722 // along with CCCA_CURRADDR and CCR_CACHEINVALIDSIZE. This implies that the 723 // actual playback position always lags CCCA_CURRADDR by exactly 64 frames. 724 #define CD0 0x20 /* Cache data registers 0 .. 0x1f */ 570 725 571 726 #define PTB 0x40 /* Page table base register */ … … 604 759 /* simultaneously. */ 605 760 606 #define FXWC_DEFAULTROUTE_C (1<<0) /* left emu out? */607 #define FXWC_DEFAULTROUTE_B (1<<1) /* right emu out? */608 #define FXWC_DEFAULTROUTE_A (1<<12)609 #define FXWC_DEFAULTROUTE_D (1<<13)610 #define FXWC_ADCLEFT (1<<18)611 #define FXWC_CDROMSPDIFLEFT (1<<18)612 #define FXWC_ADCRIGHT (1<<19)613 #define FXWC_CDROMSPDIFRIGHT (1<<19)614 #define FXWC_MIC (1<<20)615 #define FXWC_ZOOMLEFT (1<<20)616 #define FXWC_ZOOMRIGHT (1<<21)617 #define FXWC_SPDIFLEFT (1<<22) /* 0x00400000 */618 #define FXWC_SPDIFRIGHT (1<<23) /* 0x00800000 */619 620 761 #define A_TBLSZ 0x43 /* Effects Tank Internal Table Size. Only low byte or register used */ 621 762 … … 640 781 #define FXBA_MASK 0xfffff000 /* 20 bit base address */ 641 782 642 #define A_HWM 0x48 /* High PCI Water Mark - word access, defaults to 3f */783 #define A_HWM 0x48 /* High PCI Water Mark - word access, defaults to 3f */ 643 784 644 785 #define MICBS 0x49 /* Microphone buffer size register */ … … 648 789 #define FXBS 0x4b /* FX buffer size register */ 649 790 650 /* register: 0x4c..4f: ffff-ffff current amounts, per-channel */ 651 652 /* The following mask values define the size of the ADC, MIX and FX buffers in bytes */ 791 /* The following mask values define the size of the ADC, MIC and FX buffers in bytes */ 653 792 #define ADCBS_BUFSIZE_NONE 0x00000000 654 793 #define ADCBS_BUFSIZE_384 0x00000001 … … 684 823 #define ADCBS_BUFSIZE_65536 0x0000001f 685 824 686 /* Current Send B, A Amounts */ 687 #define A_CSBA 0x4c 688 689 /* Current Send D, C Amounts */ 690 #define A_CSDC 0x4d 691 692 /* Current Send F, E Amounts */ 693 #define A_CSFE 0x4e 694 695 /* Current Send H, G Amounts */ 696 #define A_CSHG 0x4f 697 698 699 #define CDCS 0x50 /* CD-ROM digital channel status register */ 700 701 #define GPSCS 0x51 /* General Purpose SPDIF channel status register*/ 702 703 #define DBG 0x52 /* DO NOT PROGRAM THIS REGISTER!!! MAY DESTROY CHIP */ 704 705 /* S/PDIF Input C Channel Status */ 706 #define A_SPSC 0x52 707 708 #define REG53 0x53 /* DO NOT PROGRAM THIS REGISTER!!! MAY DESTROY CHIP */ 709 710 #define A_DBG 0x53 711 #define A_DBG_SINGLE_STEP 0x00020000 /* Set to zero to start dsp */ 712 #define A_DBG_ZC 0x40000000 /* zero tram counter */ 713 #define A_DBG_STEP_ADDR 0x000003ff 714 #define A_DBG_SATURATION_OCCURED 0x20000000 715 #define A_DBG_SATURATION_ADDR 0x0ffc0000 716 717 // NOTE: 0x54,55,56: 64-bit 825 // On Audigy, the FX send amounts are not applied instantly, but determine 826 // targets towards which the following registers swerve gradually. 827 #define A_CSBA 0x4c /* FX send B & A current amounts */ 828 #define A_CSDC 0x4d /* FX send D & C current amounts */ 829 #define A_CSFE 0x4e /* FX send F & E current amounts */ 830 #define A_CSHG 0x4f /* FX send H & G current amounts */ 831 832 // NOTE: 0x50,51,52: 64-bit (split over voices 0 & 1) 833 #define CDCS 0x50 /* CD-ROM digital channel status register */ 834 835 #define GPSCS 0x51 /* General Purpose SPDIF channel status register */ 836 837 // Corresponding EMU10K1_DBG_* constants are in the public header 838 #define DBG 0x52 839 840 #define A_SPSC 0x52 /* S/PDIF Input C Channel Status */ 841 842 #define REG53 0x53 /* DO NOT PROGRAM THIS REGISTER!!! MAY DESTROY CHIP */ 843 844 // Corresponding A_DBG_* constants are in the public header 845 #define A_DBG 0x53 846 847 // NOTE: 0x54,55,56: 64-bit (split over voices 0 & 1) 718 848 #define SPCS0 0x54 /* SPDIF output Channel Status 0 register */ 719 849 … … 748 878 /* 0x57: Not used */ 749 879 750 /* The 32-bit CLIx and SOL x registers all have one bit per channel control/status*/880 /* The 32-bit CLIx and SOLEx registers all have one bit per channel control/status */ 751 881 #define CLIEL 0x58 /* Channel loop interrupt enable low register */ 752 753 882 #define CLIEH 0x59 /* Channel loop interrupt enable high register */ 754 883 755 884 #define CLIPL 0x5a /* Channel loop interrupt pending low register */ 756 757 885 #define CLIPH 0x5b /* Channel loop interrupt pending high register */ 758 886 887 // These cause CPF_STOP_MASK to be set shortly after CCCA_CURRADDR passes DSL_LOOPENDADDR. 888 // Subsequent changes to the address registers don't resume; clearing the bit here or in CPF does. 889 // The registers are NOT synchronized; the next serviced channel picks up immediately. 759 890 #define SOLEL 0x5c /* Stop on loop enable low register */ 760 761 891 #define SOLEH 0x5d /* Stop on loop enable high register */ 762 892 … … 768 898 769 899 #define AC97SLOT 0x5f /* additional AC97 slots enable bits */ 770 #define AC97SLOT_REAR_RIGHT 0x01 /* Rear left */ 771 #define AC97SLOT_REAR_LEFT 0x02 /* Rear right */ 772 #define AC97SLOT_CNTR 0x10 /* Center enable */ 773 #define AC97SLOT_LFE 0x20 /* LFE enable */ 774 775 /* PCB Revision */ 776 #define A_PCB 0x5f 900 #define AC97SLOT_REAR_RIGHT 0x01 /* Rear left */ 901 #define AC97SLOT_REAR_LEFT 0x02 /* Rear right */ 902 #define AC97SLOT_CNTR 0x10 /* Center enable */ 903 #define AC97SLOT_LFE 0x20 /* LFE enable */ 904 905 #define A_PCB 0x5f /* PCB Revision */ 777 906 778 907 // NOTE: 0x60,61,62: 64-bit … … 797 926 798 927 #define MICIDX 0x63 /* Microphone recording buffer index register */ 928 #ifndef TARGET_OS2 929 SUB_REG(MICIDX, IDX, 0x0000ffff) 930 #else 799 931 #define MICIDX_MASK 0x0000ffff /* 16-bit value */ 800 932 #define MICIDX_IDX 0x10000063 933 #endif 801 934 802 935 #define ADCIDX 0x64 /* ADC recording buffer index register */ 936 #ifndef TARGET_OS2 937 SUB_REG(ADCIDX, IDX, 0x0000ffff) 938 #else 803 939 #define ADCIDX_MASK 0x0000ffff /* 16 bit index field */ 804 940 #define ADCIDX_IDX 0x10000064 941 #endif 805 942 806 943 #define A_ADCIDX 0x63 944 #ifndef TARGET_OS2 945 SUB_REG(A_ADCIDX, IDX, 0x0000ffff) 946 #else 807 947 #define A_ADCIDX_IDX 0x10000063 948 #endif 808 949 809 950 #define A_MICIDX 0x64 951 #ifndef TARGET_OS2 952 SUB_REG(A_MICIDX, IDX, 0x0000ffff) 953 #else 810 954 #define A_MICIDX_IDX 0x10000064 955 #endif 811 956 812 957 #define FXIDX 0x65 /* FX recording buffer index register */ 958 #ifndef TARGET_OS2 959 SUB_REG(FXIDX, IDX, 0x0000ffff) 960 #else 813 961 #define FXIDX_MASK 0x0000ffff /* 16-bit value */ 814 962 #define FXIDX_IDX 0x10000065 815 816 /* The 32-bit HLIx and HLIPx registers all have one bit per channel control/status */ 963 #endif 964 965 /* The 32-bit HLIEx and HLIPx registers all have one bit per channel control/status */ 817 966 #define HLIEL 0x66 /* Channel half loop interrupt enable low register */ 818 819 967 #define HLIEH 0x67 /* Channel half loop interrupt enable high register */ 820 968 821 969 #define HLIPL 0x68 /* Channel half loop interrupt pending low register */ 822 823 970 #define HLIPH 0x69 /* Channel half loop interrupt pending high register */ 824 971 825 /* S/PDIF Host Record Index (bypasses SRC) */ 826 #define A_SPRI 0x6a 827 /* S/PDIF Host Record Address */ 828 #define A_SPRA 0x6b 829 /* S/PDIF Host Record Control */ 830 #define A_SPRC 0x6c 831 /* Delayed Interrupt Counter & Enable */ 832 #define A_DICE 0x6d 833 /* Tank Table Base */ 834 #define A_TTB 0x6e 835 /* Tank Delay Offset */ 836 #define A_TDOF 0x6f 972 #define A_SPRI 0x6a /* S/PDIF Host Record Index (bypasses SRC) */ 973 #define A_SPRA 0x6b /* S/PDIF Host Record Address */ 974 #define A_SPRC 0x6c /* S/PDIF Host Record Control */ 975 976 #define A_DICE 0x6d /* Delayed Interrupt Counter & Enable */ 977 978 #define A_TTB 0x6e /* Tank Table Base */ 979 #define A_TDOF 0x6f /* Tank Delay Offset */ 837 980 838 981 /* This is the MPU port on the card (via the game port) */ … … 847 990 848 991 /* The next two are the Audigy equivalent of FXWC */ 849 /* the Audigy can record any output (16bit, 48kHz, up to 64 channel simultaneously) */992 /* the Audigy can record any output (16bit, 48kHz, up to 64 channels simultaneously) */ 850 993 /* Each bit selects a channel for recording */ 851 994 #define A_FXWC1 0x74 /* Selects 0x7f-0x60 for FX recording */ 852 995 #define A_FXWC2 0x75 /* Selects 0x9f-0x80 for FX recording */ 853 996 854 /* Extended Hardware Control */ 855 #define A_SPDIF_SAMPLERATE 0x76 /* Set the sample rate of SPDIF output */ 856 #define A_SAMPLE_RATE 0x76 /* Various sample rate settings. */ 857 #define A_SAMPLE_RATE_NOT_USED 0x0ffc111e /* Bits that are not used and cannot be set. */ 858 #define A_SAMPLE_RATE_UNKNOWN 0xf0030001 /* Bits that can be set, but have unknown use. */ 997 #define A_EHC 0x76 /* Extended Hardware Control */ 998 999 #define A_SPDIF_SAMPLERATE A_EHC /* Set the sample rate of SPDIF output */ 859 1000 #define A_SPDIF_RATE_MASK 0x000000e0 /* Any other values for rates, just use 48000 */ 860 #define A_SPDIF_48000 0x00000000 1001 #define A_SPDIF_48000 0x00000000 /* kX calls this BYPASS */ 861 1002 #define A_SPDIF_192000 0x00000020 862 1003 #define A_SPDIF_96000 0x00000040 863 1004 #define A_SPDIF_44100 0x00000080 864 1005 #define A_SPDIF_MUTED 0x000000c0 1006 1007 #ifndef TARGET_OS2 1008 SUB_REG_NC(A_EHC, A_I2S_CAPTURE_RATE, 0x00000e00) /* This sets the capture PCM rate, but it is */ 1009 /* unclear if this sets the ADC rate as well. */ 1010 #else 1011 #define A_I2S_CAPTURE_RATE 0x00000e00 865 1012 #define A_I2S_CAPTURE_RATE_MASK 0x00000e00 /* This sets the capture PCM rate, but it is */ 866 #define A_I2S_CAPTURE_48000 0x00000000 /* unclear if this sets the ADC rate as well. */ 867 #define A_I2S_CAPTURE_192000 0x00000200 868 #define A_I2S_CAPTURE_96000 0x00000400 869 #define A_I2S_CAPTURE_44100 0x00000800 870 871 #define A_PCM_RATE_MASK 0x0000e000 /* This sets the playback PCM rate on the P16V */ 872 #define A_PCM_48000 0x00000000 873 #define A_PCM_192000 0x00002000 874 #define A_PCM_96000 0x00004000 875 #define A_PCM_44100 0x00008000 876 877 /* I2S0 Sample Rate Tracker Status */ 878 #define A_SRT3 0x77 879 880 /* I2S1 Sample Rate Tracker Status */ 881 #define A_SRT4 0x78 882 883 /* I2S2 Sample Rate Tracker Status */ 884 #define A_SRT5 0x79 1013 /* unclear if this sets the ADC rate as well. */ 1014 #endif 1015 #define A_I2S_CAPTURE_48000 0x0 1016 #define A_I2S_CAPTURE_192000 0x1 1017 #define A_I2S_CAPTURE_96000 0x2 1018 #define A_I2S_CAPTURE_44100 0x4 1019 1020 #define A_EHC_SRC48_MASK 0x0000e000 /* This sets the playback PCM rate on the P16V */ 1021 #define A_EHC_SRC48_BYPASS 0x00000000 1022 #define A_EHC_SRC48_192 0x00002000 1023 #define A_EHC_SRC48_96 0x00004000 1024 #define A_EHC_SRC48_44 0x00008000 1025 #define A_EHC_SRC48_MUTED 0x0000c000 1026 1027 #define A_EHC_P17V_TVM 0x00000001 /* Tank virtual memory mode */ 1028 #define A_EHC_P17V_SEL0_MASK 0x00030000 /* Aka A_EHC_P16V_PB_RATE; 00: 48, 01: 44.1, 10: 96, 11: 192 */ 1029 #define A_EHC_P17V_SEL1_MASK 0x000c0000 1030 #define A_EHC_P17V_SEL2_MASK 0x00300000 1031 #define A_EHC_P17V_SEL3_MASK 0x00c00000 1032 1033 #define A_EHC_ASYNC_BYPASS 0x80000000 1034 1035 #define A_SRT3 0x77 /* I2S0 Sample Rate Tracker Status */ 1036 #define A_SRT4 0x78 /* I2S1 Sample Rate Tracker Status */ 1037 #define A_SRT5 0x79 /* I2S2 Sample Rate Tracker Status */ 885 1038 /* - default to 0x01080000 on my audigy 2 ZS --rlrevell */ 886 1039 887 /* Tank Table DMA Address */ 888 #define A_TTDA 0x7a 889 /* Tank Table DMA Data */ 890 #define A_TTDD 0x7b 1040 #define A_SRT_ESTSAMPLERATE 0x001fffff 1041 #define A_SRT_RATELOCKED 0x01000000 1042 1043 #define A_TTDA 0x7a /* Tank Table DMA Address */ 1044 #define A_TTDD 0x7b /* Tank Table DMA Data */ 1045 1046 // In A_FXRT1 & A_FXRT2, the 0x80 bit of each byte completely disables the 1047 // filter (CVCF_CURRENTFILTER) for the corresponding channel. There is no 1048 // effect on the volume (CVCF_CURRENTVOLUME) or the interpolator's filter 1049 // (CCCA_INTERPROM_MASK). 891 1050 892 1051 #define A_FXRT2 0x7c … … 901 1060 #define A_FXSENDAMOUNT_G_MASK 0x0000FF00 902 1061 #define A_FXSENDAMOUNT_H_MASK 0x000000FF 903 /* 0x7c, 0x7e "high bit is used for filtering" */ 904 1062 905 1063 /* The send amounts for this one are the same as used with the emu10k1 */ 906 1064 #define A_FXRT1 0x7e … … 911 1069 912 1070 /* 0x7f: Not used */ 913 /* Each FX general purpose register is 32 bits in length, all bits are used */ 914 #define FXGPREGBASE 0x100 /* FX general purpose registers base */ 915 #define A_FXGPREGBASE 0x400 /* Audigy GPRs, 0x400 to 0x5ff */ 916 917 #define A_TANKMEMCTLREGBASE 0x100 /* Tank memory control registers base - only for Audigy */ 918 #define A_TANKMEMCTLREG_MASK 0x1f /* only 5 bits used - only for Audigy */ 919 920 /* Tank audio data is logarithmically compressed down to 16 bits before writing to TRAM and is */ 921 /* decompressed back to 20 bits on a read. There are a total of 160 locations, the last 32 */ 922 /* locations are for external TRAM. */ 923 #define TANKMEMDATAREGBASE 0x200 /* Tank memory data registers base */ 924 #define TANKMEMDATAREG_MASK 0x000fffff /* 20 bit tank audio data field */ 925 926 /* Combined address field and memory opcode or flag field. 160 locations, last 32 are external */ 927 #define TANKMEMADDRREGBASE 0x300 /* Tank memory address registers base */ 928 #define TANKMEMADDRREG_ADDR_MASK 0x000fffff /* 20 bit tank address field */ 929 #define TANKMEMADDRREG_CLEAR 0x00800000 /* Clear tank memory */ 930 #define TANKMEMADDRREG_ALIGN 0x00400000 /* Align read or write relative to tank access */ 931 #define TANKMEMADDRREG_WRITE 0x00200000 /* Write to tank memory */ 932 #define TANKMEMADDRREG_READ 0x00100000 /* Read from tank memory */ 933 934 #define MICROCODEBASE 0x400 /* Microcode data base address */ 1071 1072 /* The public header defines the GPR and TRAM base addresses that 1073 * are valid for _both_ CPU and DSP addressing. */ 935 1074 936 1075 /* Each DSP microcode instruction is mapped into 2 doublewords */ 937 1076 /* NOTE: When writing, always write the LO doubleword first. Reads can be in either order. */ 938 #define LOWORD_OPX_MASK 0x000ffc00 /* Instruction operand X */ 939 #define LOWORD_OPY_MASK 0x000003ff /* Instruction operand Y */ 940 #define HIWORD_OPCODE_MASK 0x00f00000 /* Instruction opcode */ 941 #define HIWORD_RESULT_MASK 0x000ffc00 /* Instruction result */ 942 #define HIWORD_OPA_MASK 0x000003ff /* Instruction operand A */ 943 944 945 /* Audigy Soundcard have a different instruction format */ 1077 #define MICROCODEBASE 0x400 /* Microcode data base address */ 946 1078 #define A_MICROCODEBASE 0x600 947 #define A_LOWORD_OPY_MASK 0x000007ff 948 #define A_LOWORD_OPX_MASK 0x007ff000 949 #define A_HIWORD_OPCODE_MASK 0x0f000000 950 #define A_HIWORD_RESULT_MASK 0x007ff000 951 #define A_HIWORD_OPA_MASK 0x000007ff 1079 952 1080 953 1081 /************************************************************************************************/ 954 /* E MU1010m HANA FPGA registers*/1082 /* E-MU Digital Audio System overview */ 955 1083 /************************************************************************************************/ 1084 1085 // - These cards use a regular PCI-attached Audigy chip (Alice2/Tina/Tina2); 1086 // the PCIe variants simply put the Audigy chip behind a PCI bridge. 1087 // - All physical PCM I/O is routed through an additional FPGA; the regular 1088 // EXTIN/EXTOUT ports are unconnected. 1089 // - The FPGA has a signal routing matrix, to connect each destination (output 1090 // socket or capture channel) to a source (input socket or playback channel). 1091 // - The FPGA is controlled via Audigy's GPIO port, while sample data is 1092 // transmitted via proprietary EMU32 serial links. On first-generation 1093 // E-MU 1010 cards, Audigy's I2S inputs are also used for sample data. 1094 // - The Audio/Micro Dock is attached to Hana via EDI, a "network" link. 1095 // - The Audigy chip operates in slave mode; the clock is supplied by the FPGA. 1096 // Gen1 E-MU 1010 cards have two crystals (for 44.1 kHz and 48 kHz multiples), 1097 // while the later cards use a single crystal and a PLL chip. 1098 // - The whole card is switched to 2x/4x mode to achieve 88.2/96/176.4/192 kHz 1099 // sample rates. Alice2/Tina keeps running at 44.1/48 kHz, but multiple channels 1100 // are bundled. 1101 // - The number of available EMU32/EDI channels is hit in 2x/4x mode, so the total 1102 // number of usable inputs/outputs is limited, esp. with ADAT in use. 1103 // - S/PDIF is unavailable in 4x mode (only over TOSLINK on newer 1010 cards) due 1104 // to being unspecified at 176.4/192 kHz. Therefore, the Dock's S/PDIF channels 1105 // can overlap with the Dock's ADC/DAC's high channels. 1106 // - The code names are mentioned below and in the emu_chip_details table. 1107 1108 /************************************************************************************************/ 1109 /* EMU1010 FPGA registers */ 1110 /************************************************************************************************/ 1111 956 1112 #define EMU_HANA_DESTHI 0x00 /* 0000xxx 3 bits Link Destination */ 957 1113 #define EMU_HANA_DESTLO 0x01 /* 00xxxxx 5 bits */ 1114 958 1115 #define EMU_HANA_SRCHI 0x02 /* 0000xxx 3 bits Link Source */ 959 1116 #define EMU_HANA_SRCLO 0x03 /* 00xxxxx 5 bits */ 1117 960 1118 #define EMU_HANA_DOCK_PWR 0x04 /* 000000x 1 bits Audio Dock power */ 961 1119 #define EMU_HANA_DOCK_PWR_ON 0x01 /* Audio Dock power on */ 1120 962 1121 #define EMU_HANA_WCLOCK 0x05 /* 0000xxx 3 bits Word Clock source select */ 963 1122 /* Must be written after power on to reset DLL */ … … 968 1127 #define EMU_HANA_WCLOCK_HANA_SPDIF_IN 0x02 969 1128 #define EMU_HANA_WCLOCK_HANA_ADAT_IN 0x03 970 #define EMU_HANA_WCLOCK_SYNC_BNC N0x041129 #define EMU_HANA_WCLOCK_SYNC_BNC 0x04 971 1130 #define EMU_HANA_WCLOCK_2ND_HANA 0x05 972 1131 #define EMU_HANA_WCLOCK_SRC_RESERVED 0x06 … … 978 1137 #define EMU_HANA_WCLOCK_MULT_RESERVED 0x18 979 1138 1139 // If the selected external clock source is/becomes invalid or incompatible 1140 // with the clock multiplier, the clock source is reset to this value, and 1141 // a WCLK_CHANGED interrupt is raised. 980 1142 #define EMU_HANA_DEFCLOCK 0x06 /* 000000x 1 bits Default Word Clock */ 981 1143 #define EMU_HANA_DEFCLOCK_48K 0x00 … … 997 1159 998 1160 #define EMU_HANA_SPDIF_MODE 0x0a /* 00xxxxx 5 bits SPDIF MODE */ 999 #define EMU_HANA_SPDIF_MODE_TX_CO MSUMER 0x001161 #define EMU_HANA_SPDIF_MODE_TX_CONSUMER 0x00 1000 1162 #define EMU_HANA_SPDIF_MODE_TX_PRO 0x01 1001 1163 #define EMU_HANA_SPDIF_MODE_TX_NOCOPY 0x02 1002 #define EMU_HANA_SPDIF_MODE_RX_CO MSUMER 0x001164 #define EMU_HANA_SPDIF_MODE_RX_CONSUMER 0x00 1003 1165 #define EMU_HANA_SPDIF_MODE_RX_PRO 0x04 1004 1166 #define EMU_HANA_SPDIF_MODE_RX_NOCOPY 0x08 … … 1012 1174 1013 1175 #define EMU_HANA_MIDI_IN 0x0c /* 000000x 1 bit Control MIDI */ 1014 #define EMU_HANA_MIDI_IN_FROM_HAMOA 0x00 /* HAMOA MIDI in to Alice 2 MIDI B */ 1015 #define EMU_HANA_MIDI_IN_FROM_DOCK 0x01 /* Audio Dock MIDI in to Alice 2 MIDI B */ 1176 #define EMU_HANA_MIDI_INA_FROM_HAMOA 0x01 /* HAMOA MIDI in to Alice 2 MIDI A */ 1177 #define EMU_HANA_MIDI_INA_FROM_DOCK1 0x02 /* Audio Dock-1 MIDI in to Alice 2 MIDI A */ 1178 #define EMU_HANA_MIDI_INA_FROM_DOCK2 0x03 /* Audio Dock-2 MIDI in to Alice 2 MIDI A */ 1179 #define EMU_HANA_MIDI_INB_FROM_HAMOA 0x08 /* HAMOA MIDI in to Alice 2 MIDI B */ 1180 #define EMU_HANA_MIDI_INB_FROM_DOCK1 0x10 /* Audio Dock-1 MIDI in to Alice 2 MIDI B */ 1181 #define EMU_HANA_MIDI_INB_FROM_DOCK2 0x18 /* Audio Dock-2 MIDI in to Alice 2 MIDI B */ 1016 1182 1017 1183 #define EMU_HANA_DOCK_LEDS_1 0x0d /* 000xxxx 4 bit Audio Dock LEDs */ … … 1038 1204 1039 1205 #define EMU_HANA_ADC_PADS 0x10 /* 0000xxx 3 bit Audio Dock ADC 14dB pads */ 1040 #define EMU_HANA_DOCK_ADC_PAD1 0x01 /* 14dB Attenuation on Audio Dock ADC 1 */1041 #define EMU_HANA_DOCK_ADC_PAD2 0x02 /* 14dB Attenuation on Audio Dock ADC 2 */1042 #define EMU_HANA_DOCK_ADC_PAD3 0x04 /* 14dB Attenuation on Audio Dock ADC 3 */1043 #define EMU_HANA_0202_ADC_PAD1 0x08 /* 14dB Attenuation on 0202 ADC 1 */1206 #define EMU_HANA_DOCK_ADC_PAD1 0x01 /* 14dB Attenuation on Audio Dock ADC 1 */ 1207 #define EMU_HANA_DOCK_ADC_PAD2 0x02 /* 14dB Attenuation on Audio Dock ADC 2 */ 1208 #define EMU_HANA_DOCK_ADC_PAD3 0x04 /* 14dB Attenuation on Audio Dock ADC 3 */ 1209 #define EMU_HANA_0202_ADC_PAD1 0x08 /* 14dB Attenuation on 0202 ADC 1 */ 1044 1210 1045 1211 #define EMU_HANA_DOCK_MISC 0x11 /* 0xxxxxx 6 bit Audio Dock misc bits */ 1046 #define EMU_HANA_DOCK_DAC1_MUTE 0x01 /* DAC 1 Mute */1047 #define EMU_HANA_DOCK_DAC2_MUTE 0x02 /* DAC 2 Mute */1048 #define EMU_HANA_DOCK_DAC3_MUTE 0x04 /* DAC 3 Mute */1049 #define EMU_HANA_DOCK_DAC4_MUTE 0x08 /* DAC 4 Mute */1212 #define EMU_HANA_DOCK_DAC1_MUTE 0x01 /* DAC 1 Mute */ 1213 #define EMU_HANA_DOCK_DAC2_MUTE 0x02 /* DAC 2 Mute */ 1214 #define EMU_HANA_DOCK_DAC3_MUTE 0x04 /* DAC 3 Mute */ 1215 #define EMU_HANA_DOCK_DAC4_MUTE 0x08 /* DAC 4 Mute */ 1050 1216 #define EMU_HANA_DOCK_PHONES_192_DAC1 0x00 /* DAC 1 Headphones source at 192kHz */ 1051 1217 #define EMU_HANA_DOCK_PHONES_192_DAC2 0x10 /* DAC 2 Headphones source at 192kHz */ … … 1054 1220 1055 1221 #define EMU_HANA_MIDI_OUT 0x12 /* 00xxxxx 5 bit Source for each MIDI out port */ 1056 #define EMU_HANA_MIDI_OUT_0202 0x01 /* 0202 MIDI from Alice 2. 0 = A, 1 = B */1057 #define EMU_HANA_MIDI_OUT_DOCK1 0x02 /* Audio Dock MIDI1 front, from Alice 2. 0 = A, 1 = B */1058 #define EMU_HANA_MIDI_OUT_DOCK2 0x04 /* Audio Dock MIDI2 rear, from Alice 2. 0 = A, 1 = B */1059 #define EMU_HANA_MIDI_OUT_SYNC2 0x08 /* Sync card. Not the actual MIDI out jack. 0 = A, 1 = B */1060 #define EMU_HANA_MIDI_OUT_LOOP 0x10 /* 0 = bits (3:0) normal. 1 = MIDI loopback enabled. */1222 #define EMU_HANA_MIDI_OUT_0202 0x01 /* 0202 MIDI from Alice 2. 0 = A, 1 = B */ 1223 #define EMU_HANA_MIDI_OUT_DOCK1 0x02 /* Audio Dock MIDI1 front, from Alice 2. 0 = A, 1 = B */ 1224 #define EMU_HANA_MIDI_OUT_DOCK2 0x04 /* Audio Dock MIDI2 rear, from Alice 2. 0 = A, 1 = B */ 1225 #define EMU_HANA_MIDI_OUT_SYNC2 0x08 /* Sync card. Not the actual MIDI out jack. 0 = A, 1 = B */ 1226 #define EMU_HANA_MIDI_OUT_LOOP 0x10 /* 0 = bits (3:0) normal. 1 = MIDI loopback enabled. */ 1061 1227 1062 1228 #define EMU_HANA_DAC_PADS 0x13 /* 00xxxxx 5 bit DAC 14dB attenuation pads */ 1063 #define EMU_HANA_DOCK_DAC_PAD1 0x01 /* 14dB Attenuation on AudioDock DAC 1. Left and Right */1064 #define EMU_HANA_DOCK_DAC_PAD2 0x02 /* 14dB Attenuation on AudioDock DAC 2. Left and Right */1065 #define EMU_HANA_DOCK_DAC_PAD3 0x04 /* 14dB Attenuation on AudioDock DAC 3. Left and Right */1066 #define EMU_HANA_DOCK_DAC_PAD4 0x08 /* 14dB Attenuation on AudioDock DAC 4. Left and Right */1067 #define EMU_HANA_0202_DAC_PAD1 0x10 /* 14dB Attenuation on 0202 DAC 1. Left and Right */1229 #define EMU_HANA_DOCK_DAC_PAD1 0x01 /* 14dB Attenuation on AudioDock DAC 1. Left and Right */ 1230 #define EMU_HANA_DOCK_DAC_PAD2 0x02 /* 14dB Attenuation on AudioDock DAC 2. Left and Right */ 1231 #define EMU_HANA_DOCK_DAC_PAD3 0x04 /* 14dB Attenuation on AudioDock DAC 3. Left and Right */ 1232 #define EMU_HANA_DOCK_DAC_PAD4 0x08 /* 14dB Attenuation on AudioDock DAC 4. Left and Right */ 1233 #define EMU_HANA_0202_DAC_PAD1 0x10 /* 14dB Attenuation on 0202 DAC 1. Left and Right */ 1068 1234 1069 1235 /* 0x14 - 0x1f Unused R/W registers */ 1070 #define EMU_HANA_IRQ_STATUS 0x20 /* 000xxxx 4 bits IRQ Status */ 1071 #if 0 /* Already defined for reg 0x09 IRQ_ENABLE */ 1072 #define EMU_HANA_IRQ_WCLK_CHANGED 0x01 1073 #define EMU_HANA_IRQ_ADAT 0x02 1074 #define EMU_HANA_IRQ_DOCK 0x04 1075 #define EMU_HANA_IRQ_DOCK_LOST 0x08 1076 #endif 1236 1237 #define EMU_HANA_IRQ_STATUS 0x20 /* 00xxxxx 5 bits IRQ Status */ 1238 /* Same bits as for EMU_HANA_IRQ_ENABLE */ 1239 /* Reading the register resets it. */ 1077 1240 1078 1241 #define EMU_HANA_OPTION_CARDS 0x21 /* 000xxxx 4 bits Presence of option cards */ 1079 #define EMU_HANA_OPTION_HAMOA 0x01 /* HAMOA card present */ 1080 #define EMU_HANA_OPTION_SYNC 0x02 /* Sync card present */ 1081 #define EMU_HANA_OPTION_DOCK_ONLINE 0x04 /* Audio Dock online and FPGA configured */ 1082 #define EMU_HANA_OPTION_DOCK_OFFLINE 0x08 /* Audio Dock online and FPGA not configured */ 1083 1084 #define EMU_HANA_ID 0x22 /* 1010101 7 bits ID byte & 0x7f = 0x55 */ 1242 #define EMU_HANA_OPTION_HAMOA 0x01 /* Hamoa (analog I/O) card present */ 1243 #define EMU_HANA_OPTION_SYNC 0x02 /* Sync card present */ 1244 #define EMU_HANA_OPTION_DOCK_ONLINE 0x04 /* Audio/Micro dock present and FPGA configured */ 1245 #define EMU_HANA_OPTION_DOCK_OFFLINE 0x08 /* Audio/Micro dock present and FPGA not configured */ 1246 1247 #define EMU_HANA_ID 0x22 /* 1010101 7 bits ID byte & 0x7f = 0x55 with Alice2 */ 1248 /* 0010101 5 bits ID byte & 0x1f = 0x15 with Tina/2 */ 1085 1249 1086 1250 #define EMU_HANA_MAJOR_REV 0x23 /* 0000xxx 3 bit Hana FPGA Major rev */ … … 1091 1255 1092 1256 #define EMU_DOCK_BOARD_ID 0x27 /* 00000xx 2 bits Audio Dock ID pins */ 1093 #define EMU_DOCK_BOARD_ID0 0x00 /* ID bit 0 */ 1094 #define EMU_DOCK_BOARD_ID1 0x03 /* ID bit 1 */ 1257 #define EMU_DOCK_BOARD_ID0 0x00 /* ID bit 0 */ 1258 #define EMU_DOCK_BOARD_ID1 0x03 /* ID bit 1 */ 1259 1260 // The actual code disagrees about the bit width of the registers - 1261 // the formula used is freq = 0x1770000 / (((X_HI << 5) | X_LO) + 1) 1095 1262 1096 1263 #define EMU_HANA_WC_SPDIF_HI 0x28 /* 0xxxxxx 6 bit SPDIF IN Word clock, upper 6 bits */ … … 1105 1272 #define EMU_HANA2_WC_SPDIF_HI 0x2e /* 0xxxxxx 6 bit HANA2 SPDIF IN Word clock, upper 6 bits */ 1106 1273 #define EMU_HANA2_WC_SPDIF_LO 0x2f /* 0xxxxxx 6 bit HANA2 SPDIF IN Word clock, lower 6 bits */ 1274 1107 1275 /* 0x30 - 0x3f Unused Read only registers */ 1108 1276 1277 // The meaning of this is not clear; kX-project just calls it "lock" in some info-only code. 1278 #define EMU_HANA_LOCK_STS_LO 0x38 /* 0xxxxxx lower 6 bits */ 1279 #define EMU_HANA_LOCK_STS_HI 0x39 /* 0xxxxxx upper 6 bits */ 1280 1109 1281 /************************************************************************************************/ 1110 /* EMU1010 m HANADestinations */1282 /* EMU1010 Audio Destinations */ 1111 1283 /************************************************************************************************/ 1112 /* Hana, original 1010,1212,1820 using Alice2 1113 * Destiniations for SRATEX = 1X rates: 44.1 kHz or 48 kHz 1284 /* Hana, original 1010,1212m,1820[m] using Alice2 1114 1285 * 0x00, 0x00-0x0f: 16 EMU32 channels to Alice2 1115 * 0x01, 0x 10-0x1f: 32 Elinkchannels to Audio Dock1116 * 0x01,0x00: Dock DAC 1 Left1117 * 0x01,0x04: Dock DAC 1 Right1118 * 0x01,0x08: Dock DAC 2 Left1119 * 0x01,0x0c: Dock DAC 2 Right1120 * 0x01,0x10: Dock DAC 3 Left1121 * 0x01, 0x12: PHONES Left1122 * 0x01,0x14: Dock DAC 3 Right1123 * 0x01, 0x16: PHONES Right1124 * 0x01,0x18: Dock DAC 4 Left1125 * 0x01,0x1a: S/PDIF Left1126 * 0x01,0x1c: Dock DAC 4 Right1127 * 0x01,0x1e: S/PDIF Right1286 * 0x01, 0x00-0x1f: 32 EDI channels to Audio Dock 1287 * 0x00: Dock DAC 1 Left 1288 * 0x04: Dock DAC 1 Right 1289 * 0x08: Dock DAC 2 Left 1290 * 0x0c: Dock DAC 2 Right 1291 * 0x10: Dock DAC 3 Left 1292 * 0x12: PHONES Left (n/a in 2x/4x mode; output mirrors DAC4 Left) 1293 * 0x14: Dock DAC 3 Right 1294 * 0x16: PHONES Right (n/a in 2x/4x mode; output mirrors DAC4 Right) 1295 * 0x18: Dock DAC 4 Left 1296 * 0x1a: S/PDIF Left 1297 * 0x1c: Dock DAC 4 Right 1298 * 0x1e: S/PDIF Right 1128 1299 * 0x02, 0x00: Hana S/PDIF Left 1129 1300 * 0x02, 0x01: Hana S/PDIF Right 1130 * 0x03, 0x00: Ha noa DAC Left1131 * 0x03, 0x01: Ha noa DAC Right1301 * 0x03, 0x00: Hamoa DAC Left 1302 * 0x03, 0x01: Hamoa DAC Right 1132 1303 * 0x04, 0x00-0x07: Hana ADAT 1133 1304 * 0x05, 0x00: I2S0 Left to Alice2 … … 1141 1312 * Not needed. 1142 1313 * 1143 * Hana3, rev2 1010,1212,1616 using Tina 1144 * Destinations for SRATEX = 1X rates: 44.1 kHz or 48 kHz 1314 * Hana3, rev2 1010,1212m,1616[m] using Tina 1145 1315 * 0x00, 0x00-0x0f: 16 EMU32A channels to Tina 1146 * 0x01, 0x 10-0x1f: 32 EDI channels to Micro Dock1147 * 0x01,0x00: Dock DAC 1 Left1148 * 0x01,0x04: Dock DAC 1 Right1149 * 0x01,0x08: Dock DAC 2 Left1150 * 0x01,0x0c: Dock DAC 2 Right1151 * 0x01,0x10: Dock DAC 3 Left1152 * 0x01,0x12: Dock S/PDIF Left1153 * 0x01,0x14: Dock DAC 3 Right1154 * 0x01,0x16: Dock S/PDIF Right1155 * 0x01,0x18-0x1f: Dock ADAT 0-71316 * 0x01, 0x00-0x1f: 32 EDI channels to Micro Dock 1317 * 0x00: Dock DAC 1 Left 1318 * 0x04: Dock DAC 1 Right 1319 * 0x08: Dock DAC 2 Left 1320 * 0x0c: Dock DAC 2 Right 1321 * 0x10: Dock DAC 3 Left 1322 * 0x12: Dock S/PDIF Left 1323 * 0x14: Dock DAC 3 Right 1324 * 0x16: Dock S/PDIF Right 1325 * 0x18-0x1f: Dock ADAT 0-7 1156 1326 * 0x02, 0x00: Hana3 S/PDIF Left 1157 1327 * 0x02, 0x01: Hana3 S/PDIF Right 1158 * 0x03, 0x00: Ha noa DAC Left1159 * 0x03, 0x01: Ha noa DAC Right1328 * 0x03, 0x00: Hamoa DAC Left 1329 * 0x03, 0x01: Hamoa DAC Right 1160 1330 * 0x04, 0x00-0x07: Hana3 ADAT 0-7 1161 1331 * 0x05, 0x00-0x0f: 16 EMU32B channels to Tina … … 1163 1333 * 1164 1334 * HanaLite, rev1 0404 using Alice2 1165 * Destiniations for SRATEX = 1X rates: 44.1 kHz or 48 kHz 1166 * 0x00, 0x00-0x0f: 16 EMU32 channels to Alice2 1167 * 0x01: Not used 1168 * 0x02, 0x00: S/PDIF Left 1169 * 0x02, 0x01: S/PDIF Right 1170 * 0x03, 0x00: DAC Left 1171 * 0x03, 0x01: DAC Right 1172 * 0x04-0x07: Not used 1173 * 1174 * HanaLiteLite, rev2 0404 using Alice2 1175 * Destiniations for SRATEX = 1X rates: 44.1 kHz or 48 kHz 1176 * 0x00, 0x00-0x0f: 16 EMU32 channels to Alice2 1335 * HanaLiteLite, rev2 0404 using Tina 1336 * 0x00, 0x00-0x0f: 16 EMU32 channels to Alice2/Tina 1177 1337 * 0x01: Not used 1178 1338 * 0x02, 0x00: S/PDIF Left … … 1183 1343 * 1184 1344 * Mana, Cardbus 1616 using Tina2 1185 * Destinations for SRATEX = 1X rates: 44.1 kHz or 48 kHz1186 1345 * 0x00, 0x00-0x0f: 16 EMU32A channels to Tina2 1187 * 0x01, 0x10-0x1f: 32 EDI channels to Micro Dock 1188 * 0x01, 0x00: Dock DAC 1 Left 1189 * 0x01, 0x04: Dock DAC 1 Right 1190 * 0x01, 0x08: Dock DAC 2 Left 1191 * 0x01, 0x0c: Dock DAC 2 Right 1192 * 0x01, 0x10: Dock DAC 3 Left 1193 * 0x01, 0x12: Dock S/PDIF Left 1194 * 0x01, 0x14: Dock DAC 3 Right 1195 * 0x01, 0x16: Dock S/PDIF Right 1196 * 0x01, 0x18-0x1f: Dock ADAT 0-7 1346 * 0x01, 0x00-0x1f: 32 EDI channels to Micro Dock 1347 * (same as rev2 1010) 1197 1348 * 0x02: Not used 1198 1349 * 0x03, 0x00: Mana DAC Left … … 1200 1351 * 0x04, 0x00-0x0f: 16 EMU32B channels to Tina2 1201 1352 * 0x05-0x07: Not used 1202 *1203 *1204 1353 */ 1354 1205 1355 /* 32-bit destinations of signal in the Hana FPGA. Destinations are either 1206 * physical outputs of Hana, or outputs going to Alice2 (audigy) for capture 1207 * - 16 x EMU_DST_ALICE2_EMU32_X. 1208 */ 1209 /* EMU32 = 32-bit serial channel between Alice2 (audigy) and Hana (FPGA) */ 1210 /* EMU_DST_ALICE2_EMU32_X - data channels from Hana to Alice2 used for capture. 1211 * Which data is fed into a EMU_DST_ALICE2_EMU32_X channel in Hana depends on 1212 * setup of mixer control for each destination - see emumixer.c - 1213 * snd_emu1010_output_enum_ctls[], snd_emu1010_input_enum_ctls[] 1356 * physical outputs of Hana, or outputs going to Alice2/Tina for capture - 1357 * 16 x EMU_DST_ALICE2_EMU32_X (2x on rev2 boards). Which data is fed into 1358 * a channel depends on the mixer control setting for each destination - see 1359 * the register arrays in emumixer.c. 1214 1360 */ 1215 1361 #define EMU_DST_ALICE2_EMU32_0 0x000f /* 16 EMU32 channels to Alice2 +0 to +0xf */ 1362 /* This channel is delayed by one sample. */ 1216 1363 #define EMU_DST_ALICE2_EMU32_1 0x0000 /* 16 EMU32 channels to Alice2 +0 to +0xf */ 1217 1364 #define EMU_DST_ALICE2_EMU32_2 0x0001 /* 16 EMU32 channels to Alice2 +0 to +0xf */ … … 1271 1418 #define EMU_DST_HANA_SPDIF_LEFT1 0x0200 /* Hana SPDIF Left, 1st or 48kHz only */ 1272 1419 #define EMU_DST_HANA_SPDIF_LEFT2 0x0202 /* Hana SPDIF Left, 2nd or 96kHz */ 1420 #define EMU_DST_HANA_SPDIF_LEFT3 0x0204 /* Hana SPDIF Left, 3rd or 192kHz */ 1421 #define EMU_DST_HANA_SPDIF_LEFT4 0x0206 /* Hana SPDIF Left, 4th or 192kHz */ 1273 1422 #define EMU_DST_HANA_SPDIF_RIGHT1 0x0201 /* Hana SPDIF Right, 1st or 48kHz only */ 1274 1423 #define EMU_DST_HANA_SPDIF_RIGHT2 0x0203 /* Hana SPDIF Right, 2nd or 96kHz */ 1424 #define EMU_DST_HANA_SPDIF_RIGHT3 0x0205 /* Hana SPDIF Right, 3rd or 192kHz */ 1425 #define EMU_DST_HANA_SPDIF_RIGHT4 0x0207 /* Hana SPDIF Right, 4th or 192kHz */ 1275 1426 #define EMU_DST_HAMOA_DAC_LEFT1 0x0300 /* Hamoa DAC Left, 1st or 48kHz only */ 1276 1427 #define EMU_DST_HAMOA_DAC_LEFT2 0x0302 /* Hamoa DAC Left, 2nd or 96kHz */ … … 1281 1432 #define EMU_DST_HAMOA_DAC_RIGHT3 0x0305 /* Hamoa DAC Right, 3rd or 192kHz */ 1282 1433 #define EMU_DST_HAMOA_DAC_RIGHT4 0x0307 /* Hamoa DAC Right, 4th or 192kHz */ 1434 // In S/MUX mode, the samples of one channel are adjacent. 1283 1435 #define EMU_DST_HANA_ADAT 0x0400 /* Hana ADAT 8 channel out +0 to +7 */ 1284 1436 #define EMU_DST_ALICE_I2S0_LEFT 0x0500 /* Alice2 I2S0 Left */ … … 1290 1442 1291 1443 /* Additional destinations for 1616(M)/Microdock */ 1292 /* Microdock S/PDIF OUT Left, 1st or 48kHz only */ 1293 #define EMU_DST_MDOCK_SPDIF_LEFT1 0x0112 1294 /* Microdock S/PDIF OUT Left, 2nd or 96kHz */ 1295 #define EMU_DST_MDOCK_SPDIF_LEFT2 0x0113 1296 /* Microdock S/PDIF OUT Right, 1st or 48kHz only */ 1297 #define EMU_DST_MDOCK_SPDIF_RIGHT1 0x0116 1298 /* Microdock S/PDIF OUT Right, 2nd or 96kHz */ 1299 #define EMU_DST_MDOCK_SPDIF_RIGHT2 0x0117 1300 /* Microdock S/PDIF ADAT 8 channel out +8 to +f */ 1301 #define EMU_DST_MDOCK_ADAT 0x0118 1302 1303 /* Headphone jack on 1010 cardbus? 44.1/48kHz only? */ 1304 #define EMU_DST_MANA_DAC_LEFT 0x0300 1305 /* Headphone jack on 1010 cardbus? 44.1/48kHz only? */ 1306 #define EMU_DST_MANA_DAC_RIGHT 0x0301 1444 1445 #define EMU_DST_MDOCK_SPDIF_LEFT1 0x0112 /* Microdock S/PDIF OUT Left, 1st or 48kHz only */ 1446 #define EMU_DST_MDOCK_SPDIF_LEFT2 0x0113 /* Microdock S/PDIF OUT Left, 2nd or 96kHz */ 1447 #define EMU_DST_MDOCK_SPDIF_RIGHT1 0x0116 /* Microdock S/PDIF OUT Right, 1st or 48kHz only */ 1448 #define EMU_DST_MDOCK_SPDIF_RIGHT2 0x0117 /* Microdock S/PDIF OUT Right, 2nd or 96kHz */ 1449 #define EMU_DST_MDOCK_ADAT 0x0118 /* Microdock S/PDIF ADAT 8 channel out +8 to +f */ 1450 1451 #define EMU_DST_MANA_DAC_LEFT 0x0300 /* Headphone jack on 1010 cardbus? 44.1/48kHz only? */ 1452 #define EMU_DST_MANA_DAC_RIGHT 0x0301 /* Headphone jack on 1010 cardbus? 44.1/48kHz only? */ 1307 1453 1308 1454 /************************************************************************************************/ 1309 /* EMU1010 m HANASources */1455 /* EMU1010 Audio Sources */ 1310 1456 /************************************************************************************************/ 1311 /* Hana, original 1010,1212,1820 using Alice2 1312 * Sources SRATEX = 1X rates: 44.1 kHz or 48 kHz 1313 * 0x00,0x00-0x1f: Silence 1314 * 0x01, 0x10-0x1f: 32 Elink channels from Audio Dock 1315 * 0x01, 0x00: Dock Mic A 1316 * 0x01, 0x04: Dock Mic B 1317 * 0x01, 0x08: Dock ADC 1 Left 1318 * 0x01, 0x0c: Dock ADC 1 Right 1319 * 0x01, 0x10: Dock ADC 2 Left 1320 * 0x01, 0x14: Dock ADC 2 Right 1321 * 0x01, 0x18: Dock ADC 3 Left 1322 * 0x01, 0x1c: Dock ADC 3 Right 1323 * 0x02, 0x00: Hana ADC Left 1324 * 0x02, 0x01: Hana ADC Right 1457 /* Hana, original 1010,1212m,1820[m] using Alice2 1458 * 0x00, 0x00-0x1f: Silence 1459 * 0x01, 0x00-0x1f: 32 EDI channels from Audio Dock 1460 * 0x00: Dock Mic A 1461 * 0x04: Dock Mic B 1462 * 0x08: Dock ADC 1 Left 1463 * 0x0c: Dock ADC 1 Right 1464 * 0x10: Dock ADC 2 Left 1465 * 0x14: Dock ADC 2 Right 1466 * 0x18: Dock ADC 3 Left 1467 * 0x1c: Dock ADC 3 Right 1468 * 0x02, 0x00: Hamoa ADC Left 1469 * 0x02, 0x01: Hamoa ADC Right 1325 1470 * 0x03, 0x00-0x0f: 16 inputs from Alice2 Emu32A output 1326 1471 * 0x03, 0x10-0x1f: 16 inputs from Alice2 Emu32B output … … 1333 1478 * Not needed. 1334 1479 * 1335 * Hana3, rev2 1010,1212,1616 using Tina 1336 * Sources SRATEX = 1X rates: 44.1 kHz or 48 kHz 1337 * 0x00,0x00-0x1f: Silence 1338 * 0x01, 0x10-0x1f: 32 Elink channels from Audio Dock 1339 * 0x01, 0x00: Dock Mic A 1340 * 0x01, 0x04: Dock Mic B 1341 * 0x01, 0x08: Dock ADC 1 Left 1342 * 0x01, 0x0c: Dock ADC 1 Right 1343 * 0x01, 0x10: Dock ADC 2 Left 1344 * 0x01, 0x12: Dock S/PDIF Left 1345 * 0x01, 0x14: Dock ADC 2 Right 1346 * 0x01, 0x16: Dock S/PDIF Right 1347 * 0x01, 0x18-0x1f: Dock ADAT 0-7 1348 * 0x01, 0x18: Dock ADC 3 Left 1349 * 0x01, 0x1c: Dock ADC 3 Right 1350 * 0x02, 0x00: Hanoa ADC Left 1351 * 0x02, 0x01: Hanoa ADC Right 1480 * Hana3, rev2 1010,1212m,1616[m] using Tina 1481 * 0x00, 0x00-0x1f: Silence 1482 * 0x01, 0x00-0x1f: 32 EDI channels from Micro Dock 1483 * 0x00: Dock Mic A 1484 * 0x04: Dock Mic B 1485 * 0x08: Dock ADC 1 Left 1486 * 0x0c: Dock ADC 1 Right 1487 * 0x10: Dock ADC 2 Left 1488 * 0x12: Dock S/PDIF Left 1489 * 0x14: Dock ADC 2 Right 1490 * 0x16: Dock S/PDIF Right 1491 * 0x18-0x1f: Dock ADAT 0-7 1492 * 0x02, 0x00: Hamoa ADC Left 1493 * 0x02, 0x01: Hamoa ADC Right 1352 1494 * 0x03, 0x00-0x0f: 16 inputs from Tina Emu32A output 1353 1495 * 0x03, 0x10-0x1f: 16 inputs from Tina Emu32B output … … 1358 1500 * 1359 1501 * HanaLite, rev1 0404 using Alice2 1360 * Sources SRATEX = 1X rates: 44.1 kHz or 48 kHz1361 * 0x00, 0x00-0x1f: Silence1502 * HanaLiteLite, rev2 0404 using Tina 1503 * 0x00, 0x00-0x1f: Silence 1362 1504 * 0x01: Not used 1363 1505 * 0x02, 0x00: ADC Left 1364 1506 * 0x02, 0x01: ADC Right 1365 * 0x03, 0x00-0x0f: 16 inputs from Alice2 Emu32A output 1366 * 0x03, 0x10-0x1f: 16 inputs from Alice2 Emu32B output 1367 * 0x04: Not used 1368 * 0x05, 0x00: S/PDIF Left 1369 * 0x05, 0x01: S/PDIF Right 1370 * 0x06-0x07: Not used 1371 * 1372 * HanaLiteLite, rev2 0404 using Alice2 1373 * Sources SRATEX = 1X rates: 44.1 kHz or 48 kHz 1374 * 0x00,0x00-0x1f: Silence 1375 * 0x01: Not used 1376 * 0x02, 0x00: ADC Left 1377 * 0x02, 0x01: ADC Right 1378 * 0x03, 0x00-0x0f: 16 inputs from Alice2 Emu32A output 1379 * 0x03, 0x10-0x1f: 16 inputs from Alice2 Emu32B output 1507 * 0x03, 0x00-0x0f: 16 inputs from Alice2/Tina Emu32A output 1508 * 0x03, 0x10-0x1f: 16 inputs from Alice2/Tina Emu32B output 1380 1509 * 0x04: Not used 1381 1510 * 0x05, 0x00: S/PDIF Left … … 1384 1513 * 1385 1514 * Mana, Cardbus 1616 using Tina2 1386 * Sources SRATEX = 1X rates: 44.1 kHz or 48 kHz 1387 * 0x00,0x00-0x1f: Silence 1388 * 0x01, 0x10-0x1f: 32 Elink channels from Audio Dock 1389 * 0x01, 0x00: Dock Mic A 1390 * 0x01, 0x04: Dock Mic B 1391 * 0x01, 0x08: Dock ADC 1 Left 1392 * 0x01, 0x0c: Dock ADC 1 Right 1393 * 0x01, 0x10: Dock ADC 2 Left 1394 * 0x01, 0x12: Dock S/PDIF Left 1395 * 0x01, 0x14: Dock ADC 2 Right 1396 * 0x01, 0x16: Dock S/PDIF Right 1397 * 0x01, 0x18-0x1f: Dock ADAT 0-7 1398 * 0x01, 0x18: Dock ADC 3 Left 1399 * 0x01, 0x1c: Dock ADC 3 Right 1515 * 0x00, 0x00-0x1f: Silence 1516 * 0x01, 0x00-0x1f: 32 EDI channels from Micro Dock 1517 * (same as rev2 1010) 1400 1518 * 0x02: Not used 1401 * 0x03, 0x00-0x0f: 16 inputs from Tina Emu32A output1402 * 0x03, 0x10-0x1f: 16 inputs from Tina Emu32B output1519 * 0x03, 0x00-0x0f: 16 inputs from Tina2 Emu32A output 1520 * 0x03, 0x10-0x1f: 16 inputs from Tina2 Emu32B output 1403 1521 * 0x04-0x07: Not used 1404 *1405 1522 */ 1406 1523 1407 1524 /* 32-bit sources of signal in the Hana FPGA. The sources are routed to 1408 * destinations using mixer control for each destination - see emumixer.c 1409 * Sources are either physical inputs of FPGA, 1410 * or outputs from Alice (audigy) - 16 x EMU_SRC_ALICE_EMU32A + 1411 * 16 x EMU_SRC_ALICE_EMU32B 1525 * destinations using a mixer control for each destination - see emumixer.c. 1526 * Sources are either physical inputs of Hana, or inputs from Alice2/Tina - 1527 * 16 x EMU_SRC_ALICE_EMU32A + 16 x EMU_SRC_ALICE_EMU32B. 1412 1528 */ 1413 1529 #define EMU_SRC_SILENCE 0x0000 /* Silence */ … … 1454 1570 #define EMU_SRC_ALICE_EMU32A 0x0300 /* Alice2 EMU32a 16 outputs. +0 to +0xf */ 1455 1571 #define EMU_SRC_ALICE_EMU32B 0x0310 /* Alice2 EMU32b 16 outputs. +0 to +0xf */ 1572 // In S/MUX mode, the samples of one channel are adjacent. 1456 1573 #define EMU_SRC_HANA_ADAT 0x0400 /* Hana ADAT 8 channel in +0 to +7 */ 1457 1574 #define EMU_SRC_HANA_SPDIF_LEFT1 0x0500 /* Hana SPDIF Left, 1st or 48kHz only */ 1458 1575 #define EMU_SRC_HANA_SPDIF_LEFT2 0x0502 /* Hana SPDIF Left, 2nd or 96kHz */ 1576 #define EMU_SRC_HANA_SPDIF_LEFT3 0x0504 /* Hana SPDIF Left, 3rd or 192kHz */ 1577 #define EMU_SRC_HANA_SPDIF_LEFT4 0x0506 /* Hana SPDIF Left, 4th or 192kHz */ 1459 1578 #define EMU_SRC_HANA_SPDIF_RIGHT1 0x0501 /* Hana SPDIF Right, 1st or 48kHz only */ 1460 1579 #define EMU_SRC_HANA_SPDIF_RIGHT2 0x0503 /* Hana SPDIF Right, 2nd or 96kHz */ 1580 #define EMU_SRC_HANA_SPDIF_RIGHT3 0x0505 /* Hana SPDIF Right, 3rd or 192kHz */ 1581 #define EMU_SRC_HANA_SPDIF_RIGHT4 0x0507 /* Hana SPDIF Right, 4th or 192kHz */ 1461 1582 1462 1583 /* Additional inputs for 1616(M)/Microdock */ 1463 /* Microdock S/PDIF Left, 1st or 48kHz only */ 1464 #define EMU_SRC_MDOCK_SPDIF_LEFT1 0x0112 1465 /* Microdock S/PDIF Left, 2nd or 96kHz */ 1466 #define EMU_SRC_MDOCK_SPDIF_LEFT2 0x0113 1467 /* Microdock S/PDIF Right, 1st or 48kHz only */ 1468 #define EMU_SRC_MDOCK_SPDIF_RIGHT1 0x0116 1469 /* Microdock S/PDIF Right, 2nd or 96kHz */ 1470 #define EMU_SRC_MDOCK_SPDIF_RIGHT2 0x0117 1471 /* Microdock ADAT 8 channel in +8 to +f */ 1472 #define EMU_SRC_MDOCK_ADAT 0x0118 1584 1585 #define EMU_SRC_MDOCK_SPDIF_LEFT1 0x0112 /* Microdock S/PDIF Left, 1st or 48kHz only */ 1586 #define EMU_SRC_MDOCK_SPDIF_LEFT2 0x0113 /* Microdock S/PDIF Left, 2nd or 96kHz */ 1587 #define EMU_SRC_MDOCK_SPDIF_RIGHT1 0x0116 /* Microdock S/PDIF Right, 1st or 48kHz only */ 1588 #define EMU_SRC_MDOCK_SPDIF_RIGHT2 0x0117 /* Microdock S/PDIF Right, 2nd or 96kHz */ 1589 #define EMU_SRC_MDOCK_ADAT 0x0118 /* Microdock ADAT 8 channel in +8 to +f */ 1473 1590 1474 1591 /* 0x600 and 0x700 no used */ 1475 1592 1593 1594 /* ------------------- CONSTANTS -------------------- */ 1595 1596 extern const char * const snd_emu10k1_fxbus[32]; 1597 extern const char * const snd_emu10k1_sblive_ins[16]; 1598 extern const char * const snd_emu10k1_audigy_ins[16]; 1599 extern const char * const snd_emu10k1_sblive_outs[32]; 1600 extern const char * const snd_emu10k1_audigy_outs[32]; 1601 extern const s8 snd_emu10k1_sblive51_fxbus2_map[16]; 1602 1476 1603 /* ------------------- STRUCTURES -------------------- */ 1477 1604 1478 1605 enum { 1606 EMU10K1_UNUSED, // This must be zero 1479 1607 EMU10K1_EFX, 1608 EMU10K1_EFX_IRQ, 1480 1609 EMU10K1_PCM, 1610 EMU10K1_PCM_IRQ, 1481 1611 EMU10K1_SYNTH, 1482 EMU10K1_ MIDI1612 EMU10K1_NUM_TYPES 1483 1613 }; 1484 1614 … … 1486 1616 1487 1617 struct snd_emu10k1_voice { 1488 struct snd_emu10k1 *emu; 1489 int number; 1490 unsigned int use: 1, 1491 pcm: 1, 1492 efx: 1, 1493 synth: 1, 1494 midi: 1; 1618 unsigned char number; 1619 unsigned char use; 1620 unsigned char dirty; 1621 unsigned char last; 1495 1622 void (*interrupt)(struct snd_emu10k1 *emu, struct snd_emu10k1_voice *pvoice); 1496 1623 … … 1514 1641 unsigned short running; 1515 1642 unsigned short first_ptr; 1643 snd_pcm_uframes_t resume_pos; 1516 1644 struct snd_util_memblk *memblk; 1645 unsigned int pitch_target; 1517 1646 unsigned int start_addr; 1518 1647 unsigned int ccca_start_addr; … … 1532 1661 unsigned char send_routing[3][8]; 1533 1662 unsigned char send_volume[3][8]; 1663 // 0x8000 is neutral. The mixer code rescales it to 0xffff to maintain 1664 // backwards compatibility with user space. 1534 1665 unsigned short attn[3]; 1535 1666 struct snd_emu10k1_pcm *epcm; … … 1540 1671 1541 1672 #define snd_emu10k1_compose_audigy_fxrt1(route) \ 1542 ((unsigned int)route[0] | ((unsigned int)route[1] << 8) | ((unsigned int)route[2] << 16) | ((unsigned int)route[3] << 24) )1673 ((unsigned int)route[0] | ((unsigned int)route[1] << 8) | ((unsigned int)route[2] << 16) | ((unsigned int)route[3] << 24) | 0x80808080) 1543 1674 1544 1675 #define snd_emu10k1_compose_audigy_fxrt2(route) \ 1545 ((unsigned int)route[4] | ((unsigned int)route[5] << 8) | ((unsigned int)route[6] << 16) | ((unsigned int)route[7] << 24)) 1676 ((unsigned int)route[4] | ((unsigned int)route[5] << 8) | ((unsigned int)route[6] << 16) | ((unsigned int)route[7] << 24) | 0x80808080) 1677 1678 #define snd_emu10k1_compose_audigy_sendamounts(vol) \ 1679 (((unsigned int)vol[4] << 24) | ((unsigned int)vol[5] << 16) | ((unsigned int)vol[6] << 8) | (unsigned int)vol[7]) 1546 1680 1547 1681 struct snd_emu10k1_memblk { … … 1563 1697 unsigned int count; /* count of GPR (1..16) */ 1564 1698 unsigned short gpr[32]; /* GPR number(s) */ 1565 unsignedint value[32];1566 unsigned int min;/* minimum range */1567 unsigned int max;/* maximum range */1699 int value[32]; 1700 int min; /* minimum range */ 1701 int max; /* maximum range */ 1568 1702 unsigned int translation; /* translation type (EMU10K1_GPR_TRANSLATION*) */ 1569 1703 struct snd_kcontrol *kcontrol; … … 1600 1734 1601 1735 struct snd_emu10k1_fx8010 { 1602 unsigned short fxbus_mask; /* used FX buses (bitmask) */ 1603 unsigned short extin_mask; /* used external inputs (bitmask) */ 1604 unsigned short extout_mask; /* used external outputs (bitmask) */ 1605 unsigned short pad1; 1736 unsigned short extin_mask; /* used external inputs (bitmask); not used for Audigy */ 1737 unsigned short extout_mask; /* used external outputs (bitmask); not used for Audigy */ 1606 1738 unsigned int itram_size; /* internal TRAM size in samples */ 1607 1739 struct snd_dma_buffer etram_pages; /* external TRAM pages and size */ … … 1640 1772 }; 1641 1773 1774 // Chip-o-logy: 1775 // - All SB Live! cards use EMU10K1 chips 1776 // - All SB Audigy cards use CA* chips, termed "emu10k2" by the driver 1777 // - Original Audigy uses CA0100 "Alice" 1778 // - Audigy 2 uses CA0102/CA10200 "Alice2" 1779 // - Has an interface for CA0151 (P16V) "Alice3" 1780 // - Audigy 2 Value uses CA0108/CA10300 "Tina" 1781 // - Approximately a CA0102 with an on-chip CA0151 (P17V) 1782 // - Audigy 2 ZS NB uses CA0109 "Tina2" 1783 // - Cardbus version of CA0108 1642 1784 struct snd_emu_chip_details { 1643 1785 u32 vendor; … … 1645 1787 u32 subsystem; 1646 1788 unsigned char revision; 1647 unsigned char emu10k1_chip; /* Original SB Live. Not SB Live 24bit. */ 1648 unsigned char emu10k2_chip; /* Audigy 1 or Audigy 2. */ 1649 unsigned char ca0102_chip; /* Audigy 1 or Audigy 2. Not SB Audigy 2 Value. */ 1650 unsigned char ca0108_chip; /* Audigy 2 Value */ 1651 unsigned char ca_cardbus_chip; /* Audigy 2 ZS Notebook */ 1652 unsigned char ca0151_chip; /* P16V */ 1653 unsigned char spk71; /* Has 7.1 speakers */ 1654 unsigned char sblive51; /* SBLive! 5.1 - extout 0x11 -> center, 0x12 -> lfe */ 1655 unsigned char spdif_bug; /* Has Spdif phasing bug */ 1656 unsigned char ac97_chip; /* Has an AC97 chip: 1 = mandatory, 2 = optional */ 1657 unsigned char ecard; /* APS EEPROM */ 1658 unsigned char emu_model; /* EMU model type */ 1659 unsigned char spi_dac; /* SPI interface for DAC */ 1660 unsigned char i2c_adc; /* I2C interface for ADC */ 1661 unsigned char adc_1361t; /* Use Philips 1361T ADC */ 1662 unsigned char invert_shared_spdif; /* analog/digital switch inverted */ 1789 unsigned char emu_model; /* EMU model type */ 1790 #ifndef TARGET_OS2 1791 unsigned int emu10k1_chip:1; /* Original SB Live. Not SB Live 24bit. */ 1792 /* Redundant with emu10k2_chip being unset. */ 1793 unsigned int emu10k2_chip:1; /* Audigy 1 or Audigy 2. */ 1794 unsigned int ca0102_chip:1; /* Audigy 1 or Audigy 2. Not SB Audigy 2 Value. */ 1795 /* Redundant with ca0108_chip being unset. */ 1796 unsigned int ca0108_chip:1; /* Audigy 2 Value */ 1797 unsigned int ca_cardbus_chip:1; /* Audigy 2 ZS Notebook */ 1798 unsigned int ca0151_chip:1; /* P16V */ 1799 unsigned int spk20:1; /* Stereo only */ 1800 unsigned int spk71:1; /* Has 7.1 speakers */ 1801 unsigned int no_adat:1; /* Has no ADAT, only SPDIF */ 1802 unsigned int sblive51:1; /* SBLive! 5.1 - extout 0x11 -> center, 0x12 -> lfe */ 1803 unsigned int spdif_bug:1; /* Has Spdif phasing bug */ 1804 unsigned int ac97_chip:2; /* Has an AC97 chip: 1 = mandatory, 2 = optional */ 1805 unsigned int ecard:1; /* APS EEPROM */ 1806 unsigned int spi_dac:1; /* SPI interface for DAC; requires ca0108_chip */ 1807 unsigned int i2c_adc:1; /* I2C interface for ADC; requires ca0108_chip */ 1808 unsigned int adc_1361t:1; /* Use Philips 1361T ADC */ 1809 unsigned int invert_shared_spdif:1; /* analog/digital switch inverted */ 1810 #else 1811 unsigned int emu10k1_chip; /* Original SB Live. Not SB Live 24bit. */ 1812 /* Redundant with emu10k2_chip being unset. */ 1813 unsigned int emu10k2_chip; /* Audigy 1 or Audigy 2. */ 1814 unsigned int ca0102_chip; /* Audigy 1 or Audigy 2. Not SB Audigy 2 Value. */ 1815 /* Redundant with ca0108_chip being unset. */ 1816 unsigned int ca0108_chip; /* Audigy 2 Value */ 1817 unsigned int ca_cardbus_chip; /* Audigy 2 ZS Notebook */ 1818 unsigned int ca0151_chip; /* P16V */ 1819 unsigned int spk20; /* Stereo only */ 1820 unsigned int spk71; /* Has 7.1 speakers */ 1821 unsigned int no_adat; /* Has no ADAT, only SPDIF */ 1822 unsigned int sblive51; /* SBLive! 5.1 - extout 0x11 -> center, 0x12 -> lfe */ 1823 unsigned int spdif_bug; /* Has Spdif phasing bug */ 1824 unsigned int ac97_chip; /* Has an AC97 chip: 1 = mandatory, 2 = optional */ 1825 unsigned int ecard; /* APS EEPROM */ 1826 unsigned int spi_dac; /* SPI interface for DAC; requires ca0108_chip */ 1827 unsigned int i2c_adc; /* I2C interface for ADC; requires ca0108_chip */ 1828 unsigned int adc_1361t; /* Use Philips 1361T ADC */ 1829 unsigned int invert_shared_spdif; /* analog/digital switch inverted */ 1830 #endif 1663 1831 const char *driver; 1664 1832 const char *name; … … 1666 1834 }; 1667 1835 1836 #define NUM_OUTPUT_DESTS 28 1837 #define NUM_INPUT_DESTS 22 1838 1668 1839 struct snd_emu1010 { 1669 unsigned int output_source[64];1670 unsigned int input_source[64];1840 unsigned char output_source[NUM_OUTPUT_DESTS]; 1841 unsigned char input_source[NUM_INPUT_DESTS]; 1671 1842 unsigned int adc_pads; /* bit mask */ 1672 1843 unsigned int dac_pads; /* bit mask */ 1673 unsigned int internal_clock; /* 44100 or 48000 */ 1844 unsigned int wclock; /* Cached register value */ 1845 unsigned int word_clock; /* Cached effective value */ 1846 unsigned int clock_source; 1847 unsigned int clock_fallback; 1674 1848 unsigned int optical_in; /* 0:SPDIF, 1:ADAT */ 1675 1849 unsigned int optical_out; /* 0:SPDIF, 1:ADAT */ 1676 struct delayed_work firmware_work; 1677 u32 last_reg; 1850 struct work_struct work; 1678 1851 }; 1679 1852 … … 1692 1865 unsigned int serial; /* serial number */ 1693 1866 unsigned short model; /* subsystem id */ 1694 unsigned int card_type; /* EMU10K1_CARD_* */1695 1867 unsigned int ecard_ctrl; /* ecard control bits */ 1696 1868 unsigned int address_mode; /* address mode */ 1697 1869 unsigned long dma_mask; /* PCI DMA mask */ 1698 1870 bool iommu_workaround; /* IOMMU workaround needed */ 1699 unsigned int delay_pcm_irq; /* in samples */1700 1871 int max_cache_pages; /* max memory size / PAGE_SIZE */ 1701 1872 struct snd_dma_buffer silent_page; /* silent page */ … … 1733 1904 int (*get_synth_voice)(struct snd_emu10k1 *emu); 1734 1905 1735 spinlock_t reg_lock; 1736 spinlock_t emu_lock; 1737 spinlock_t voice_lock; 1906 spinlock_t reg_lock; // high-level driver lock 1907 spinlock_t emu_lock; // low-level i/o lock 1908 spinlock_t voice_lock; // voice allocator lock 1738 1909 spinlock_t spi_lock; /* serialises access to spi port */ 1739 1910 spinlock_t i2c_lock; /* serialises access to i2c port */ 1740 1911 1741 1912 struct snd_emu10k1_voice voices[NUM_G]; 1742 struct snd_emu10k1_voice p16v_voices[4];1743 struct snd_emu10k1_voice p16v_capture_voice;1744 1913 int p16v_device_offset; 1745 1914 u32 p16v_capture_source; … … 1754 1923 struct snd_kcontrol *ctl_efx_send_volume; 1755 1924 struct snd_kcontrol *ctl_efx_attn; 1925 struct snd_kcontrol *ctl_clock_source; 1756 1926 1757 1927 void (*hwvol_interrupt)(struct snd_emu10k1 *emu, unsigned int status); … … 1761 1931 void (*spdif_interrupt)(struct snd_emu10k1 *emu, unsigned int status); 1762 1932 void (*dsp_interrupt)(struct snd_emu10k1 *emu); 1933 void (*gpio_interrupt)(struct snd_emu10k1 *emu); 1934 void (*p16v_interrupt)(struct snd_emu10k1 *emu); 1763 1935 1764 1936 struct snd_pcm_substream *pcm_capture_substream; 1765 1937 struct snd_pcm_substream *pcm_capture_mic_substream; 1766 1938 struct snd_pcm_substream *pcm_capture_efx_substream; 1767 struct snd_pcm_substream *pcm_playback_efx_substream;1768 1939 1769 1940 struct snd_timer *timer; … … 1821 1992 unsigned int snd_emu10k1_ptr_read(struct snd_emu10k1 * emu, unsigned int reg, unsigned int chn); 1822 1993 void snd_emu10k1_ptr_write(struct snd_emu10k1 *emu, unsigned int reg, unsigned int chn, unsigned int data); 1994 void snd_emu10k1_ptr_write_multiple(struct snd_emu10k1 *emu, unsigned int chn, ...); 1823 1995 unsigned int snd_emu10k1_ptr20_read(struct snd_emu10k1 * emu, unsigned int reg, unsigned int chn); 1824 1996 void snd_emu10k1_ptr20_write(struct snd_emu10k1 *emu, unsigned int reg, unsigned int chn, unsigned int data); 1825 1997 int snd_emu10k1_spi_write(struct snd_emu10k1 * emu, unsigned int data); 1826 1998 int snd_emu10k1_i2c_write(struct snd_emu10k1 *emu, u32 reg, u32 value); 1827 int snd_emu1010_fpga_write(struct snd_emu10k1 * emu, u32 reg, u32 value); 1828 int snd_emu1010_fpga_read(struct snd_emu10k1 * emu, u32 reg, u32 *value); 1829 int snd_emu1010_fpga_link_dst_src_write(struct snd_emu10k1 * emu, u32 dst, u32 src); 1999 void snd_emu1010_fpga_write(struct snd_emu10k1 *emu, u32 reg, u32 value); 2000 void snd_emu1010_fpga_read(struct snd_emu10k1 *emu, u32 reg, u32 *value); 2001 void snd_emu1010_fpga_link_dst_src_write(struct snd_emu10k1 *emu, u32 dst, u32 src); 2002 u32 snd_emu1010_fpga_link_dst_src_read(struct snd_emu10k1 *emu, u32 dst); 2003 int snd_emu1010_get_raw_rate(struct snd_emu10k1 *emu, u8 src); 2004 void snd_emu1010_update_clock(struct snd_emu10k1 *emu); 1830 2005 unsigned int snd_emu10k1_efx_read(struct snd_emu10k1 *emu, unsigned int pc); 1831 2006 void snd_emu10k1_intr_enable(struct snd_emu10k1 *emu, unsigned int intrenb); … … 1837 2012 void snd_emu10k1_voice_half_loop_intr_disable(struct snd_emu10k1 *emu, unsigned int voicenum); 1838 2013 void snd_emu10k1_voice_half_loop_intr_ack(struct snd_emu10k1 *emu, unsigned int voicenum); 2014 #if 0 1839 2015 void snd_emu10k1_voice_set_loop_stop(struct snd_emu10k1 *emu, unsigned int voicenum); 1840 2016 void snd_emu10k1_voice_clear_loop_stop(struct snd_emu10k1 *emu, unsigned int voicenum); 2017 #endif 2018 void snd_emu10k1_voice_set_loop_stop_multiple(struct snd_emu10k1 *emu, u64 voices); 2019 void snd_emu10k1_voice_clear_loop_stop_multiple(struct snd_emu10k1 *emu, u64 voices); 2020 int snd_emu10k1_voice_clear_loop_stop_multiple_atomic(struct snd_emu10k1 *emu, u64 voices); 1841 2021 void snd_emu10k1_wait(struct snd_emu10k1 *emu, unsigned int wait); 1842 2022 static inline unsigned int snd_emu10k1_wc(struct snd_emu10k1 *emu) { return (inl(emu->port + WC) >> 6) & 0xfffff; } 1843 2023 unsigned short snd_emu10k1_ac97_read(struct snd_ac97 *ac97, unsigned short reg); 1844 2024 void snd_emu10k1_ac97_write(struct snd_ac97 *ac97, unsigned short reg, unsigned short data); 1845 unsigned int snd_emu10k1_rate_to_pitch(unsigned int rate);1846 2025 1847 2026 #ifdef CONFIG_PM_SLEEP … … 1871 2050 1872 2051 /* voice allocation */ 1873 int snd_emu10k1_voice_alloc(struct snd_emu10k1 *emu, int type, int pair, struct snd_emu10k1_voice **rvoice); 2052 int snd_emu10k1_voice_alloc(struct snd_emu10k1 *emu, int type, int count, int channels, 2053 struct snd_emu10k1_pcm *epcm, struct snd_emu10k1_voice **rvoice); 1874 2054 int snd_emu10k1_voice_free(struct snd_emu10k1 *emu, struct snd_emu10k1_voice *pvoice); 1875 2055
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