Changeset 76 for GPL/trunk/alsa-kernel/pci/cs4281.c

Timestamp:

Apr 9, 2006, 12:09:39 PM (19 years ago)

Author:

vladest

Message:

Latest ALSA patches
HDA patches
Patch for Intel from Rudy's
Fixes locks on NM256 chipsets
Fixes PM on Maestro3 chipsets

File:

• GPL/trunk/alsa-kernel/pci/cs4281.c (modified) (9 diffs)

GPL/trunk/alsa-kernel/pci/cs4281.c

@@ -1092 +1092 @@
         change = 1;
     }
-    if (ucontrol->value.integer.value[0] != volL) {
+    if (ucontrol->value.integer.value[0] != volR) {
         volR = CS_VOL_MASK - (ucontrol->value.integer.value[1] & CS_VOL_MASK);
         snd_cs4281_pokeBA0(chip, regR, volR);
@@ -1462 +1462 @@
 {
     unsigned int tmp;
-    int timeout;
+    unsigned long end_time;
     int retry_count = 2;
 
@@ -1541 +1541 @@
      * Wait for the DLL ready signal from the clock logic.
      */
-#ifdef TARGET_OS2
-    //  end_time = (jiffies + 1000) + 1;
-#else
-    //  end_time = (jiffies + HZ / 4) + 1;
-#endif
-    timeout = HZ;
+    end_time = jiffies + HZ;
     do {
         /*
@@ -1554 +1549 @@
         if (snd_cs4281_peekBA0(chip, BA0_CLKCR1) & BA0_CLKCR1_DLLRDY)
             goto __ok0;
-        snd_cs4281_delay_long();
-    } while (timeout-- > 0);
+        schedule_timeout_uninterruptible(1);
+    } while (time_after_eq(end_time, jiffies));
 
     snd_printk(KERN_ERR "DLLRDY not seen\n");
@@ -1572 +1567 @@
      * Wait for the codec ready signal from the AC97 codec.
      */
-#ifdef TARGET_OS2
-    //  end_time = (jiffies + 1000) + 1;
-#else
-    //  end_time = (jiffies + (3 * HZ) / 4) + 1;
-#endif
-    timeout = HZ;
+    end_time = jiffies + HZ;
     do {
         /*
@@ -1585 +1575 @@
         if (snd_cs4281_peekBA0(chip, BA0_ACSTS) & BA0_ACSTS_CRDY)
             goto __ok1;
-        snd_cs4281_delay_long();
-    } while (timeout-- > 0);
+        schedule_timeout_uninterruptible(1);
+    } while (time_after_eq(end_time, jiffies));
 
     snd_printk(KERN_ERR "never read codec ready from AC'97 (0x%x)\n", snd_cs4281_peekBA0(chip, BA0_ACSTS));
@@ -1593 +1583 @@
 __ok1:
     if (chip->dual_codec) {
-        timeout = HZ;
+        end_time = jiffies + HZ;
         do {
             if (snd_cs4281_peekBA0(chip, BA0_ACSTS2) & BA0_ACSTS_CRDY)
                 goto __codec2_ok;
-            snd_cs4281_delay_long();
-        } while (timeout-- > 0);
+            schedule_timeout_uninterruptible(1);
+        } while (time_after_eq(end_time, jiffies));
         snd_printk(KERN_INFO "secondary codec doesn't respond. disable it...\n");
         chip->dual_codec = 0;
@@ -1615 +1605 @@
      *  the codec is pumping ADC data across the AC-link.
      */
-
-#ifdef TARGET_OS2
-    //  end_time = (jiffies + 5000);
-#else
-    //  end_time = (jiffies + (5 * HZ) / 4) + 1;
-#endif
-    timeout = HZ;
+    end_time = jiffies + HZ;
     do {
         /*
@@ -1629 +1613 @@
         if ((snd_cs4281_peekBA0(chip, BA0_ACISV) & (BA0_ACISV_SLV(3) | BA0_ACISV_SLV(4))) == (BA0_ACISV_SLV(3) | BA0_ACISV_SLV(4)))
             goto __ok2;
-        snd_cs4281_delay_long();
-    } while (timeout-- > 0);
+        schedule_timeout_uninterruptible(1);
+    } while (time_after_eq(end_time, jiffies));
 
     if (--retry_count > 0)