Changeset 76 for GPL/trunk/alsa-kernel/pci/ca0106/ca0106.h
- Timestamp:
- Apr 9, 2006, 12:09:39 PM (19 years ago)
- File:
-
- 1 edited
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GPL/trunk/alsa-kernel/pci/ca0106/ca0106.h (modified) (12 diffs)
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GPL/trunk/alsa-kernel/pci/ca0106/ca0106.h
r32 r76 6 6 * FEATURES currently supported: 7 7 * See ca0106_main.c for features. 8 * 8 * 9 9 * Changelog: 10 10 * Support interrupts per period. … … 154 154 * bit 9 0 = Mute / 1 = Analog out. 155 155 * bit 10 0 = Line-in / 1 = Mic-in. 156 157 156 * bit 11 0 = ? / 1 = ? 157 * bit 12 0 = 48 Khz / 1 = 96 Khz Analog out on SB Live 24bit. 158 158 * bit 13 0 = ? / 1 = ? 159 159 * bit 14 0 = Mute / 1 = Analog out … … 173 173 /* CA0106 pointer-offset register set, accessed through the PTR and DATA registers */ 174 174 /********************************************************************************************************/ 175 175 176 176 /* Initally all registers from 0x00 to 0x3f have zero contents. */ 177 177 #define PLAYBACK_LIST_ADDR 0x00 /* Base DMA address of a list of pointers to each period/size */ 178 /* One list entry: 4 bytes for DMA address, 178 /* One list entry: 4 bytes for DMA address, 179 179 * 4 bytes for period_size << 16. 180 180 * One list entry is 8 bytes long. … … 218 218 * Playback mixer out enable [31:28] (one bit per channel) 219 219 */ 220 /* The Digital out jack is shared with the Center/LFE Analogue output. 220 /* The Digital out jack is shared with the Center/LFE Analogue output. 221 221 * The jack has 4 poles. I will call 1 - Tip, 2 - Next to 1, 3 - Next to 2, 4 - Next to 3 222 222 * For Analogue: 1 -> Center Speaker, 2 -> Sub Woofer, 3 -> Ground, 4 -> Ground … … 231 231 */ 232 232 /* A standard 2 pole mono mini-jack to RCA plug can be used for SPDIF Stereo PCM output from the Front channel. 233 * A standard 3 pole stereo mini-jack to 2 RCA plugs can be used for SPDIF AC3/DTS and Stereo PCM output utilising the Rear channel and just one of the RCA plugs. 233 * A standard 3 pole stereo mini-jack to 2 RCA plugs can be used for SPDIF AC3/DTS and Stereo PCM output utilising the Rear channel and just one of the RCA plugs. 234 234 */ 235 235 #define SPCS0 0x41 /* SPDIF output Channel Status 0 register. For Rear. default=0x02108004, non-audio=0x02108006 */ … … 331 331 #define CAPTURE_SOURCE_CHANNEL3 0x000f0000 /* 3 - Mic in, Line in, TAD in, Aux in. */ 332 332 #define CAPTURE_SOURCE_RECORD_MAP 0x0000ffff /* Default 0x00e4 */ 333 /* Record Map [7:0] (2 bits per channel) 0=mapped to channel 0, 1=mapped to channel 1, 2=mapped to channel2, 3=mapped to channel3 333 /* Record Map [7:0] (2 bits per channel) 0=mapped to channel 0, 1=mapped to channel 1, 2=mapped to channel2, 3=mapped to channel3 334 334 * Record source select for channel 0 [18:16] 335 335 * Record source select for channel 1 [22:20] … … 400 400 /* Similar to register 0x66, except that the destination is the I2S mixer instead of the SPDIF mixer. I.E. Outputs to the Analog outputs instead of SPDIF. */ 401 401 #define UNKNOWN6b 0x6b /* Unknown. Readonly. Default 00400000 00400000 00400000 00400000 */ 402 #define UART_A_DATA 0x6c /* Uart, used in setting sample rates, bits per sample etc. */ 403 #define UART_A_CMD 0x6d /* Uart, used in setting sample rates, bits per sample etc. */ 404 #define UART_B_DATA 0x6e /* Uart, Unknown. */ 405 #define UART_B_CMD 0x6f /* Uart, Unknown. */ 402 #define MIDI_UART_A_DATA 0x6c /* Midi Uart A Data */ 403 #define MIDI_UART_A_CMD 0x6d /* Midi Uart A Command/Status */ 404 #define MIDI_UART_B_DATA 0x6e /* Midi Uart B Data (currently unused) */ 405 #define MIDI_UART_B_CMD 0x6f /* Midi Uart B Command/Status (currently unused) */ 406 407 /* unique channel identifier for midi->channel */ 408 409 #define CA0106_MIDI_CHAN_A 0x1 410 #define CA0106_MIDI_CHAN_B 0x2 411 412 /* from mpu401 */ 413 414 #define CA0106_MIDI_INPUT_AVAIL 0x80 415 #define CA0106_MIDI_OUTPUT_READY 0x40 416 #define CA0106_MPU401_RESET 0xff 417 #define CA0106_MPU401_ENTER_UART 0x3f 418 #define CA0106_MPU401_ACK 0xfe 419 406 420 #define SAMPLE_RATE_TRACKER_STATUS 0x70 /* Readonly. Default 00108000 00108000 00500000 00500000 */ 407 421 /* Estimated sample rate [19:0] Relative to 48kHz. 0x8000 = 1.0 … … 418 432 * SRC input source select [4] 0=Audio from digital mixer, 1=Audio from analog source. 419 433 * Record rate [9:8] (0=48kHz, 1=Not available, 2=96kHz, 3=192Khz) 420 * Record mixer output enable [12:10] 434 * Record mixer output enable [12:10] 421 435 * I2S input rate master mode [15:14] (0=48kHz, 1=44.1kHz, 2=96kHz, 3=192Khz) 422 436 * I2S output rate [17:16] (0=48kHz, 1=44.1kHz, 2=96kHz, 3=192Khz) … … 431 445 * Record Source 0 input [29:28] (0=SPDIF in, 1=I2S in, 2=AC97 Mic, 3=AC97 PCM) 432 446 * Record Source 1 input [31:30] (0=SPDIF in, 1=I2S in, 2=AC97 Mic, 3=AC97 PCM) 433 */ 447 */ 434 448 /* Sample rate output control register Channel=1 435 449 * I2S Input 0 volume Right [7:0] … … 453 467 * I2S output enable [19:16] 454 468 * SPDIF output enable [27:24] 455 */ 469 */ 456 470 #define UNKNOWN73 0x73 /* Unknown. Readonly. Default 0x0 */ 457 471 #define CHIP_VERSION 0x74 /* P17 Chip version. Channel_id 0 only. Default 00000071 */ … … 478 492 #define SPI 0x7a /* SPI: Serial Interface Register */ 479 493 #define I2C_A 0x7b /* I2C Address. 32 bit */ 480 #define I2C_D0 0x7c/* I2C Data Port 0. 32 bit */481 #define I2C_D1 0x7d/* I2C Data Port 1. 32 bit */494 #define I2C_D0 0x7c /* I2C Data Port 0. 32 bit */ 495 #define I2C_D1 0x7d /* I2C Data Port 1. 32 bit */ 482 496 //I2C values 483 #define I2C_A_ADC_ADD_MASK 0x000000fe//The address is a 7 bit address484 #define I2C_A_ADC_RW_MASK 0x00000001//bit mask for R/W485 #define I2C_A_ADC_TRANS_MASK 0x00000010//Bit mask for I2c address DAC value486 #define I2C_A_ADC_ABORT_MASK 0x00000020//Bit mask for I2C transaction abort flag487 #define I2C_A_ADC_LAST_MASK 0x00000040//Bit mask for Last word transaction488 #define I2C_A_ADC_BYTE_MASK 0x00000080//Bit mask for Byte Mode489 490 #define I2C_A_ADC_ADD 0x00000034 //This is the Device address for ADC491 #define I2C_A_ADC_READ 0x00000001//To perform a read operation492 #define I2C_A_ADC_START 0x00000100//Start I2C transaction493 #define I2C_A_ADC_ABORT 0x00000200//I2C transaction abort494 #define I2C_A_ADC_LAST 0x00000400//I2C last transaction495 #define I2C_A_ADC_BYTE 0x00000800//I2C one byte mode496 497 #define I2C_D_ADC_REG_MASK 0xfe000000 //ADC address register498 #define I2C_D_ADC_DAT_MASK 0x01ff0000//ADC data register499 500 #define ADC_TIMEOUT 0x00000007//ADC Timeout Clock Disable501 #define ADC_IFC_CTRL 0x0000000b//ADC Interface Control502 #define ADC_MASTER 0x0000000c//ADC Master Mode Control503 #define ADC_POWER 0x0000000d//ADC PowerDown Control504 #define ADC_ATTEN_ADCL 0x0000000e//ADC Attenuation ADCL505 #define ADC_ATTEN_ADCR 0x0000000f//ADC Attenuation ADCR506 #define ADC_ALC_CTRL1 0x00000010//ADC ALC Control 1507 #define ADC_ALC_CTRL2 0x00000011//ADC ALC Control 2508 #define ADC_ALC_CTRL3 0x00000012//ADC ALC Control 3509 #define ADC_NOISE_CTRL 0x00000013//ADC Noise Gate Control510 #define ADC_LIMIT_CTRL 0x00000014//ADC Limiter Control511 #define ADC_MUX 0x00000015//ADC Mux offset497 #define I2C_A_ADC_ADD_MASK 0x000000fe //The address is a 7 bit address 498 #define I2C_A_ADC_RW_MASK 0x00000001 //bit mask for R/W 499 #define I2C_A_ADC_TRANS_MASK 0x00000010 //Bit mask for I2c address DAC value 500 #define I2C_A_ADC_ABORT_MASK 0x00000020 //Bit mask for I2C transaction abort flag 501 #define I2C_A_ADC_LAST_MASK 0x00000040 //Bit mask for Last word transaction 502 #define I2C_A_ADC_BYTE_MASK 0x00000080 //Bit mask for Byte Mode 503 504 #define I2C_A_ADC_ADD 0x00000034 //This is the Device address for ADC 505 #define I2C_A_ADC_READ 0x00000001 //To perform a read operation 506 #define I2C_A_ADC_START 0x00000100 //Start I2C transaction 507 #define I2C_A_ADC_ABORT 0x00000200 //I2C transaction abort 508 #define I2C_A_ADC_LAST 0x00000400 //I2C last transaction 509 #define I2C_A_ADC_BYTE 0x00000800 //I2C one byte mode 510 511 #define I2C_D_ADC_REG_MASK 0xfe000000 //ADC address register 512 #define I2C_D_ADC_DAT_MASK 0x01ff0000 //ADC data register 513 514 #define ADC_TIMEOUT 0x00000007 //ADC Timeout Clock Disable 515 #define ADC_IFC_CTRL 0x0000000b //ADC Interface Control 516 #define ADC_MASTER 0x0000000c //ADC Master Mode Control 517 #define ADC_POWER 0x0000000d //ADC PowerDown Control 518 #define ADC_ATTEN_ADCL 0x0000000e //ADC Attenuation ADCL 519 #define ADC_ATTEN_ADCR 0x0000000f //ADC Attenuation ADCR 520 #define ADC_ALC_CTRL1 0x00000010 //ADC ALC Control 1 521 #define ADC_ALC_CTRL2 0x00000011 //ADC ALC Control 2 522 #define ADC_ALC_CTRL3 0x00000012 //ADC ALC Control 3 523 #define ADC_NOISE_CTRL 0x00000013 //ADC Noise Gate Control 524 #define ADC_LIMIT_CTRL 0x00000014 //ADC Limiter Control 525 #define ADC_MUX 0x00000015 //ADC Mux offset 512 526 513 527 #if 0 514 528 /* FIXME: Not tested yet. */ 515 #define ADC_GAIN_MASK 0x000000ff//Mask for ADC Gain516 #define ADC_ZERODB 0x000000cf//Value to set ADC to 0dB517 #define ADC_MUTE_MASK 0x000000c0//Mask for ADC mute518 #define ADC_MUTE 0x000000c0//Value to mute ADC519 #define ADC_OSR 0x00000008//Mask for ADC oversample rate select520 #define ADC_TIMEOUT_DISABLE 0x00000008//Value and mask to disable Timeout clock521 #define ADC_HPF_DISABLE 0x00000100//Value and mask to disable High pass filter522 #define ADC_TRANWIN_MASK 0x00000070//Mask for Length of Transient Window529 #define ADC_GAIN_MASK 0x000000ff //Mask for ADC Gain 530 #define ADC_ZERODB 0x000000cf //Value to set ADC to 0dB 531 #define ADC_MUTE_MASK 0x000000c0 //Mask for ADC mute 532 #define ADC_MUTE 0x000000c0 //Value to mute ADC 533 #define ADC_OSR 0x00000008 //Mask for ADC oversample rate select 534 #define ADC_TIMEOUT_DISABLE 0x00000008 //Value and mask to disable Timeout clock 535 #define ADC_HPF_DISABLE 0x00000100 //Value and mask to disable High pass filter 536 #define ADC_TRANWIN_MASK 0x00000070 //Mask for Length of Transient Window 523 537 #endif 524 538 525 #define ADC_MUX_MASK 0x0000000f//Mask for ADC Mux526 #define ADC_MUX_MIC 0x00000002//Value to select Mic at ADC Mux527 #define ADC_MUX_LINEIN 0x00000004//Value to select LineIn at ADC Mux528 #define ADC_MUX_PHONE 0x00000001//Value to select TAD at ADC Mux (Not used)529 #define ADC_MUX_AUX 0x00000008//Value to select Aux at ADC Mux539 #define ADC_MUX_MASK 0x0000000f //Mask for ADC Mux 540 #define ADC_MUX_MIC 0x00000002 //Value to select Mic at ADC Mux 541 #define ADC_MUX_LINEIN 0x00000004 //Value to select LineIn at ADC Mux 542 #define ADC_MUX_PHONE 0x00000001 //Value to select TAD at ADC Mux (Not used) 543 #define ADC_MUX_AUX 0x00000008 //Value to select Aux at ADC Mux 530 544 531 545 #define SET_CHANNEL 0 /* Testing channel outputs 0=Front, 1=Center/LFE, 2=Unknown, 3=Rear */ … … 539 553 #define CONTROL_UNKNOWN_CHANNEL 2 540 554 541 typedef struct snd_ca0106_channel ca0106_channel_t; 542 typedef struct snd_ca0106 ca0106_t; 543 typedef struct snd_ca0106_pcm ca0106_pcm_t;555 #include "ca_midi.h" 556 557 struct snd_ca0106; 544 558 545 559 struct snd_ca0106_channel { 546 ca0106_t*emu;560 struct snd_ca0106 *emu; 547 561 int number; 548 562 int use; 549 void (*interrupt)( ca0106_t *emu, ca0106_channel_t*channel);550 ca0106_pcm_t*epcm;563 void (*interrupt)(struct snd_ca0106 *emu, struct snd_ca0106_channel *channel); 564 struct snd_ca0106_pcm *epcm; 551 565 }; 552 566 553 567 struct snd_ca0106_pcm { 554 ca0106_t*emu;555 s nd_pcm_substream_t*substream;568 struct snd_ca0106 *emu; 569 struct snd_pcm_substream *substream; 556 570 int channel_id; 557 571 unsigned short running; 558 572 }; 559 573 560 typedef struct { 561 u32 serial; 562 char * name; 563 int ac97; 564 int gpio_type; 565 int i2c_adc; 566 } ca0106_details_t; 574 struct snd_ca0106_details { 575 u32 serial; 576 char * name; 577 int ac97; 578 int gpio_type; 579 int i2c_adc; 580 int spi_dac; 581 }; 567 582 568 583 // definition of the chip-specific record 569 584 struct snd_ca0106 { 570 snd_card_t *card; 571 ca0106_details_t *details; 572 struct pci_dev *pci; 573 574 unsigned long port; 575 struct resource *res_port; 576 int irq; 577 578 unsigned int revision; /* chip revision */ 579 unsigned int serial; /* serial number */ 580 unsigned short model; /* subsystem id */ 581 582 spinlock_t emu_lock; 583 584 ac97_t *ac97; 585 snd_pcm_t *pcm; 586 587 ca0106_channel_t playback_channels[4]; 588 ca0106_channel_t capture_channels[4]; 589 u32 spdif_bits[4]; /* s/pdif out setup */ 590 int spdif_enable; 591 int capture_source; 592 int capture_mic_line_in; 593 594 struct snd_dma_buffer buffer; 585 struct snd_card *card; 586 struct snd_ca0106_details *details; 587 struct pci_dev *pci; 588 589 unsigned long port; 590 struct resource *res_port; 591 int irq; 592 593 unsigned int revision; /* chip revision */ 594 unsigned int serial; /* serial number */ 595 unsigned short model; /* subsystem id */ 596 597 spinlock_t emu_lock; 598 599 struct snd_ac97 *ac97; 600 struct snd_pcm *pcm; 601 602 struct snd_ca0106_channel playback_channels[4]; 603 struct snd_ca0106_channel capture_channels[4]; 604 u32 spdif_bits[4]; /* s/pdif out setup */ 605 int spdif_enable; 606 int capture_source; 607 int capture_mic_line_in; 608 609 struct snd_dma_buffer buffer; 610 611 struct snd_ca_midi midi; 612 struct snd_ca_midi midi2; 595 613 }; 596 614 597 int __devinit snd_ca0106_mixer(ca0106_t *emu); 598 int __devinit snd_ca0106_proc_init(ca0106_t * emu); 599 600 unsigned int snd_ca0106_ptr_read(ca0106_t * emu, 601 unsigned int reg, 602 unsigned int chn); 603 604 void snd_ca0106_ptr_write(ca0106_t *emu, 605 unsigned int reg, 606 unsigned int chn, 607 unsigned int data); 608 609 int snd_ca0106_i2c_write(ca0106_t *emu, u32 reg, u32 value); 615 int snd_ca0106_mixer(struct snd_ca0106 *emu); 616 int snd_ca0106_proc_init(struct snd_ca0106 * emu); 617 618 unsigned int snd_ca0106_ptr_read(struct snd_ca0106 * emu, 619 unsigned int reg, 620 unsigned int chn); 621 622 void snd_ca0106_ptr_write(struct snd_ca0106 *emu, 623 unsigned int reg, 624 unsigned int chn, 625 unsigned int data); 626 627 int snd_ca0106_i2c_write(struct snd_ca0106 *emu, u32 reg, u32 value); 628 629
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