Ignore:
Timestamp:
Mar 18, 2021, 8:57:36 PM (4 years ago)
Author:
David Azarewicz
Message:

Merge changes from Paul's uniaud32next branch.

Location:
GPL/trunk
Files:
2 edited

Legend:

Unmodified
Added
Removed

  • GPL/trunk

  • GPL/trunk/alsa-kernel/include/sound/emu10k1.h

    r598 r679  
    1 #ifndef __SOUND_EMU10K1_H
    2 #define __SOUND_EMU10K1_H
    3 
    4 #include <linux/types.h>
    5 
     1/* SPDX-License-Identifier: GPL-2.0-or-later */
    62/*
    73 *  Copyright (c) by Jaroslav Kysela <perex@perex.cz>,
    84 *                   Creative Labs, Inc.
    95 *  Definitions for EMU10K1 (SB Live!) chips
    10  *
    11  *
    12  *   This program is free software; you can redistribute it and/or modify
    13  *   it under the terms of the GNU General Public License as published by
    14  *   the Free Software Foundation; either version 2 of the License, or
    15  *   (at your option) any later version.
    16  *
    17  *   This program is distributed in the hope that it will be useful,
    18  *   but WITHOUT ANY WARRANTY; without even the implied warranty of
    19  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
    20  *   GNU General Public License for more details.
    21  *
    22  *   You should have received a copy of the GNU General Public License
    23  *   along with this program; if not, write to the Free Software
    24  *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
    25  *
    266 */
    27 
    28 #ifdef __KERNEL__
     7#ifndef __SOUND_EMU10K1_H
     8#define __SOUND_EMU10K1_H
     9
    2910
    3011#include <sound/pcm.h>
    … …  
    3718#include <linux/interrupt.h>
    3819#include <linux/mutex.h>
    39 
    40 #include <asm/io.h>
     20#include <linux/firmware.h>
     21#include <linux/io.h>
     22
     23#include <uapi/sound/emu10k1.h>
    4124
    4225/* ------------------- DEFINES -------------------- */
    … …  
    4427#define EMUPAGESIZE     4096
    4528#define MAXREQVOICES    8
    46 #define MAXPAGES        8192
     29#define MAXPAGES0       4096    /* 32 bit mode */
     30#define MAXPAGES1       8192    /* 31 bit mode */
    4731#define RESERVED        0
    4832#define NUM_MIDI        16
    … …  
    5337/* FIXME? - according to the OSS driver the EMU10K1 needs a 29 bit DMA mask */
    5438#define EMU10K1_DMA_MASK        0x7fffffffUL    /* 31bit */
    55 #define AUDIGY_DMA_MASK         0x7fffffffUL    /* 31bit FIXME - 32 should work? */
    56                                                 /* See ALSA bug #1276 - rlrevell */
     39#define AUDIGY_DMA_MASK         0xffffffffUL    /* 32bit mode */
    5740
    5841#define TMEMSIZE        256*1024
    … …  
    439422#define CCCA_CURRADDR           0x18000008
    440423
    441 /* undefine CCR to avoid conflict with the definition for SH */
    442 #undef CCR
    443424#define CCR                     0x09            /* Cache control register                               */
    444425#define CCR_CACHEINVALIDSIZE    0x07190009
    … …  
    471452#define MAPB                    0x0d            /* Cache map B                                          */
    472453
    473 #define MAP_PTE_MASK            0xffffe000      /* The 19 MSBs of the PTE indexed by the PTI            */
    474 #define MAP_PTI_MASK            0x00001fff      /* The 13 bit index to one of the 8192 PTE dwords       */
     454#define MAP_PTE_MASK0           0xfffff000      /* The 20 MSBs of the PTE indexed by the PTI            */
     455#define MAP_PTI_MASK0           0x00000fff      /* The 12 bit index to one of the 4096 PTE dwords       */
     456
     457#define MAP_PTE_MASK1           0xffffe000      /* The 19 MSBs of the PTE indexed by the PTI            */
     458#define MAP_PTI_MASK1           0x00001fff      /* The 13 bit index to one of the 8192 PTE dwords       */
    475459
    476460/* 0x0e, 0x0f: Not used */
    … …  
    16121596        unsigned int tram_pos;
    16131597        unsigned int tram_shift;
    1614         struct snd_emu10k1_fx8010_irq *irq;
     1598        struct snd_emu10k1_fx8010_irq irq;
    16151599};
    16161600
    … …  
    16901674        unsigned int optical_in; /* 0:SPDIF, 1:ADAT */
    16911675        unsigned int optical_out; /* 0:SPDIF, 1:ADAT */
    1692         struct task_struct *firmware_thread;
     1676        struct delayed_work firmware_work;
     1677        u32 last_reg;
    16931678};
    16941679
    … …  
    17091694        unsigned int card_type;                 /* EMU10K1_CARD_* */
    17101695        unsigned int ecard_ctrl;                /* ecard control bits */
     1696        unsigned int address_mode;              /* address mode */
    17111697        unsigned long dma_mask;                 /* PCI DMA mask */
     1698        bool iommu_workaround;                  /* IOMMU workaround needed */
    17121699        unsigned int delay_pcm_irq;             /* in samples */
    17131700        int max_cache_pages;                    /* max memory size / PAGE_SIZE */
    … …  
    17181705
    17191706        struct snd_util_memhdr *memhdr;         /* page allocation list */
    1720         struct snd_emu10k1_memblk *reserved_page;       /* reserved page */
    17211707
    17221708        struct list_head mapped_link_head;
    … …  
    17891775        unsigned int next_free_voice;
    17901776
    1791 #ifdef CONFIG_PM
     1777        const struct firmware *firmware;
     1778        const struct firmware *dock_fw;
     1779
     1780#ifdef CONFIG_PM_SLEEP
    17921781        unsigned int *saved_ptr;
    17931782        unsigned int *saved_gpr;
    … …  
    17971786        unsigned int *p16v_saved;
    17981787        unsigned int saved_a_iocfg, saved_hcfg;
     1788        bool suspend;
    17991789#endif
    18001790
    … …  
    18101800                       struct snd_emu10k1 ** remu);
    18111801
    1812 int snd_emu10k1_pcm(struct snd_emu10k1 * emu, int device, struct snd_pcm ** rpcm);
    1813 int snd_emu10k1_pcm_mic(struct snd_emu10k1 * emu, int device, struct snd_pcm ** rpcm);
    1814 int snd_emu10k1_pcm_efx(struct snd_emu10k1 * emu, int device, struct snd_pcm ** rpcm);
    1815 int snd_p16v_pcm(struct snd_emu10k1 * emu, int device, struct snd_pcm ** rpcm);
     1802int snd_emu10k1_pcm(struct snd_emu10k1 *emu, int device);
     1803int snd_emu10k1_pcm_mic(struct snd_emu10k1 *emu, int device);
     1804int snd_emu10k1_pcm_efx(struct snd_emu10k1 *emu, int device);
     1805int snd_p16v_pcm(struct snd_emu10k1 *emu, int device);
    18161806int snd_p16v_free(struct snd_emu10k1 * emu);
    18171807int snd_p16v_mixer(struct snd_emu10k1 * emu);
    1818 int snd_emu10k1_pcm_multi(struct snd_emu10k1 * emu, int device, struct snd_pcm ** rpcm);
    1819 int snd_emu10k1_fx8010_pcm(struct snd_emu10k1 * emu, int device, struct snd_pcm ** rpcm);
     1808int snd_emu10k1_pcm_multi(struct snd_emu10k1 *emu, int device);
     1809int snd_emu10k1_fx8010_pcm(struct snd_emu10k1 *emu, int device);
    18201810int snd_emu10k1_mixer(struct snd_emu10k1 * emu, int pcm_device, int multi_device);
    18211811int snd_emu10k1_timer(struct snd_emu10k1 * emu, int device);
    1822 int snd_emu10k1_fx8010_new(struct snd_emu10k1 *emu, int device, struct snd_hwdep ** rhwdep);
     1812int snd_emu10k1_fx8010_new(struct snd_emu10k1 *emu, int device);
    18231813
    18241814irqreturn_t snd_emu10k1_interrupt(int irq, void *dev_id);
    … …  
    18571847unsigned int snd_emu10k1_rate_to_pitch(unsigned int rate);
    18581848
    1859 #ifdef CONFIG_PM
     1849#ifdef CONFIG_PM_SLEEP
    18601850void snd_emu10k1_suspend_regs(struct snd_emu10k1 *emu);
    18611851void snd_emu10k1_resume_init(struct snd_emu10k1 *emu);
    … …  
    18741864struct snd_util_memblk *snd_emu10k1_alloc_pages(struct snd_emu10k1 *emu, struct snd_pcm_substream *substream);
    18751865int snd_emu10k1_free_pages(struct snd_emu10k1 *emu, struct snd_util_memblk *blk);
     1866int snd_emu10k1_alloc_pages_maybe_wider(struct snd_emu10k1 *emu, size_t size,
     1867                                        struct snd_dma_buffer *dmab);
    18761868struct snd_util_memblk *snd_emu10k1_synth_alloc(struct snd_emu10k1 *emu, unsigned int size);
    18771869int snd_emu10k1_synth_free(struct snd_emu10k1 *emu, struct snd_util_memblk *blk);
    … …  
    18961888                                            unsigned char gpr_running,
    18971889                                            void *private_data,
    1898                                             struct snd_emu10k1_fx8010_irq **r_irq);
     1890                                            struct snd_emu10k1_fx8010_irq *irq);
    18991891int snd_emu10k1_fx8010_unregister_irq_handler(struct snd_emu10k1 *emu,
    19001892                                              struct snd_emu10k1_fx8010_irq *irq);
    19011893
    1902 #endif /* __KERNEL__ */
    1903 
    1904 /*
    1905  * ---- FX8010 ----
    1906  */
    1907 
    1908 #define EMU10K1_CARD_CREATIVE                   0x00000000
    1909 #define EMU10K1_CARD_EMUAPS                     0x00000001
    1910 
    1911 #define EMU10K1_FX8010_PCM_COUNT                8
    1912 
    1913 /* instruction set */
    1914 #define iMAC0    0x00   /* R = A + (X * Y >> 31)   ; saturation */
    1915 #define iMAC1    0x01   /* R = A + (-X * Y >> 31)  ; saturation */
    1916 #define iMAC2    0x02   /* R = A + (X * Y >> 31)   ; wraparound */
    1917 #define iMAC3    0x03   /* R = A + (-X * Y >> 31)  ; wraparound */
    1918 #define iMACINT0 0x04   /* R = A + X * Y           ; saturation */
    1919 #define iMACINT1 0x05   /* R = A + X * Y           ; wraparound (31-bit) */
    1920 #define iACC3    0x06   /* R = A + X + Y           ; saturation */
    1921 #define iMACMV   0x07   /* R = A, acc += X * Y >> 31 */
    1922 #define iANDXOR  0x08   /* R = (A & X) ^ Y */
    1923 #define iTSTNEG  0x09   /* R = (A >= Y) ? X : ~X */
    1924 #define iLIMITGE 0x0a   /* R = (A >= Y) ? X : Y */
    1925 #define iLIMITLT 0x0b   /* R = (A < Y) ? X : Y */
    1926 #define iLOG     0x0c   /* R = linear_data, A (log_data), X (max_exp), Y (format_word) */
    1927 #define iEXP     0x0d   /* R = log_data, A (linear_data), X (max_exp), Y (format_word) */
    1928 #define iINTERP  0x0e   /* R = A + (X * (Y - A) >> 31)  ; saturation */
    1929 #define iSKIP    0x0f   /* R = A (cc_reg), X (count), Y (cc_test) */
    1930 
    1931 /* GPRs */
    1932 #define FXBUS(x)        (0x00 + (x))    /* x = 0x00 - 0x0f */
    1933 #define EXTIN(x)        (0x10 + (x))    /* x = 0x00 - 0x0f */
    1934 #define EXTOUT(x)       (0x20 + (x))    /* x = 0x00 - 0x0f physical outs -> FXWC low 16 bits */
    1935 #define FXBUS2(x)       (0x30 + (x))    /* x = 0x00 - 0x0f copies of fx buses for capture -> FXWC high 16 bits */
    1936                                         /* NB: 0x31 and 0x32 are shared with Center/LFE on SB live 5.1 */
    1937 
    1938 #define C_00000000      0x40
    1939 #define C_00000001      0x41
    1940 #define C_00000002      0x42
    1941 #define C_00000003      0x43
    1942 #define C_00000004      0x44
    1943 #define C_00000008      0x45
    1944 #define C_00000010      0x46
    1945 #define C_00000020      0x47
    1946 #define C_00000100      0x48
    1947 #define C_00010000      0x49
    1948 #define C_00080000      0x4a
    1949 #define C_10000000      0x4b
    1950 #define C_20000000      0x4c
    1951 #define C_40000000      0x4d
    1952 #define C_80000000      0x4e
    1953 #define C_7fffffff      0x4f
    1954 #define C_ffffffff      0x50
    1955 #define C_fffffffe      0x51
    1956 #define C_c0000000      0x52
    1957 #define C_4f1bbcdc      0x53
    1958 #define C_5a7ef9db      0x54
    1959 #define C_00100000      0x55            /* ?? */
    1960 #define GPR_ACCU        0x56            /* ACCUM, accumulator */
    1961 #define GPR_COND        0x57            /* CCR, condition register */
    1962 #define GPR_NOISE0      0x58            /* noise source */
    1963 #define GPR_NOISE1      0x59            /* noise source */
    1964 #define GPR_IRQ         0x5a            /* IRQ register */
    1965 #define GPR_DBAC        0x5b            /* TRAM Delay Base Address Counter */
    1966 #define GPR(x)          (FXGPREGBASE + (x)) /* free GPRs: x = 0x00 - 0xff */
    1967 #define ITRAM_DATA(x)   (TANKMEMDATAREGBASE + 0x00 + (x)) /* x = 0x00 - 0x7f */
    1968 #define ETRAM_DATA(x)   (TANKMEMDATAREGBASE + 0x80 + (x)) /* x = 0x00 - 0x1f */
    1969 #define ITRAM_ADDR(x)   (TANKMEMADDRREGBASE + 0x00 + (x)) /* x = 0x00 - 0x7f */
    1970 #define ETRAM_ADDR(x)   (TANKMEMADDRREGBASE + 0x80 + (x)) /* x = 0x00 - 0x1f */
    1971 
    1972 #define A_ITRAM_DATA(x) (TANKMEMDATAREGBASE + 0x00 + (x)) /* x = 0x00 - 0xbf */
    1973 #define A_ETRAM_DATA(x) (TANKMEMDATAREGBASE + 0xc0 + (x)) /* x = 0x00 - 0x3f */
    1974 #define A_ITRAM_ADDR(x) (TANKMEMADDRREGBASE + 0x00 + (x)) /* x = 0x00 - 0xbf */
    1975 #define A_ETRAM_ADDR(x) (TANKMEMADDRREGBASE + 0xc0 + (x)) /* x = 0x00 - 0x3f */
    1976 #define A_ITRAM_CTL(x)  (A_TANKMEMCTLREGBASE + 0x00 + (x)) /* x = 0x00 - 0xbf */
    1977 #define A_ETRAM_CTL(x)  (A_TANKMEMCTLREGBASE + 0xc0 + (x)) /* x = 0x00 - 0x3f */
    1978 
    1979 #define A_FXBUS(x)      (0x00 + (x))    /* x = 0x00 - 0x3f FX buses */
    1980 #define A_EXTIN(x)      (0x40 + (x))    /* x = 0x00 - 0x0f physical ins */
    1981 #define A_P16VIN(x)     (0x50 + (x))    /* x = 0x00 - 0x0f p16v ins (A2 only) "EMU32 inputs" */
    1982 #define A_EXTOUT(x)     (0x60 + (x))    /* x = 0x00 - 0x1f physical outs -> A_FXWC1 0x79-7f unknown   */
    1983 #define A_FXBUS2(x)     (0x80 + (x))    /* x = 0x00 - 0x1f extra outs used for EFX capture -> A_FXWC2 */
    1984 #define A_EMU32OUTH(x)  (0xa0 + (x))    /* x = 0x00 - 0x0f "EMU32_OUT_10 - _1F" - ??? */
    1985 #define A_EMU32OUTL(x)  (0xb0 + (x))    /* x = 0x00 - 0x0f "EMU32_OUT_1 - _F" - ??? */
    1986 #define A3_EMU32IN(x)   (0x160 + (x))   /* x = 0x00 - 0x3f "EMU32_IN_00 - _3F" - Only when .device = 0x0008 */
    1987 #define A3_EMU32OUT(x)  (0x1E0 + (x))   /* x = 0x00 - 0x0f "EMU32_OUT_00 - _3F" - Only when .device = 0x0008 */
    1988 #define A_GPR(x)        (A_FXGPREGBASE + (x))
    1989 
    1990 /* cc_reg constants */
    1991 #define CC_REG_NORMALIZED C_00000001
    1992 #define CC_REG_BORROW   C_00000002
    1993 #define CC_REG_MINUS    C_00000004
    1994 #define CC_REG_ZERO     C_00000008
    1995 #define CC_REG_SATURATE C_00000010
    1996 #define CC_REG_NONZERO  C_00000100
    1997 
    1998 /* FX buses */
    1999 #define FXBUS_PCM_LEFT          0x00
    2000 #define FXBUS_PCM_RIGHT         0x01
    2001 #define FXBUS_PCM_LEFT_REAR     0x02
    2002 #define FXBUS_PCM_RIGHT_REAR    0x03
    2003 #define FXBUS_MIDI_LEFT         0x04
    2004 #define FXBUS_MIDI_RIGHT        0x05
    2005 #define FXBUS_PCM_CENTER        0x06
    2006 #define FXBUS_PCM_LFE           0x07
    2007 #define FXBUS_PCM_LEFT_FRONT    0x08
    2008 #define FXBUS_PCM_RIGHT_FRONT   0x09
    2009 #define FXBUS_MIDI_REVERB       0x0c
    2010 #define FXBUS_MIDI_CHORUS       0x0d
    2011 #define FXBUS_PCM_LEFT_SIDE     0x0e
    2012 #define FXBUS_PCM_RIGHT_SIDE    0x0f
    2013 #define FXBUS_PT_LEFT           0x14
    2014 #define FXBUS_PT_RIGHT          0x15
    2015 
    2016 /* Inputs */
    2017 #define EXTIN_AC97_L       0x00 /* AC'97 capture channel - left */
    2018 #define EXTIN_AC97_R       0x01 /* AC'97 capture channel - right */
    2019 #define EXTIN_SPDIF_CD_L   0x02 /* internal S/PDIF CD - onboard - left */
    2020 #define EXTIN_SPDIF_CD_R   0x03 /* internal S/PDIF CD - onboard - right */
    2021 #define EXTIN_ZOOM_L       0x04 /* Zoom Video I2S - left */
    2022 #define EXTIN_ZOOM_R       0x05 /* Zoom Video I2S - right */
    2023 #define EXTIN_TOSLINK_L    0x06 /* LiveDrive - TOSLink Optical - left */
    2024 #define EXTIN_TOSLINK_R    0x07 /* LiveDrive - TOSLink Optical - right */
    2025 #define EXTIN_LINE1_L      0x08 /* LiveDrive - Line/Mic 1 - left */
    2026 #define EXTIN_LINE1_R      0x09 /* LiveDrive - Line/Mic 1 - right */
    2027 #define EXTIN_COAX_SPDIF_L 0x0a /* LiveDrive - Coaxial S/PDIF - left */
    2028 #define EXTIN_COAX_SPDIF_R 0x0b /* LiveDrive - Coaxial S/PDIF - right */
    2029 #define EXTIN_LINE2_L      0x0c /* LiveDrive - Line/Mic 2 - left */
    2030 #define EXTIN_LINE2_R      0x0d /* LiveDrive - Line/Mic 2 - right */
    2031 
    2032 /* Outputs */
    2033 #define EXTOUT_AC97_L      0x00 /* AC'97 playback channel - left */
    2034 #define EXTOUT_AC97_R      0x01 /* AC'97 playback channel - right */
    2035 #define EXTOUT_TOSLINK_L   0x02 /* LiveDrive - TOSLink Optical - left */
    2036 #define EXTOUT_TOSLINK_R   0x03 /* LiveDrive - TOSLink Optical - right */
    2037 #define EXTOUT_AC97_CENTER 0x04 /* SB Live 5.1 - center */
    2038 #define EXTOUT_AC97_LFE    0x05 /* SB Live 5.1 - LFE */
    2039 #define EXTOUT_HEADPHONE_L 0x06 /* LiveDrive - Headphone - left */
    2040 #define EXTOUT_HEADPHONE_R 0x07 /* LiveDrive - Headphone - right */
    2041 #define EXTOUT_REAR_L      0x08 /* Rear channel - left */
    2042 #define EXTOUT_REAR_R      0x09 /* Rear channel - right */
    2043 #define EXTOUT_ADC_CAP_L   0x0a /* ADC Capture buffer - left */
    2044 #define EXTOUT_ADC_CAP_R   0x0b /* ADC Capture buffer - right */
    2045 #define EXTOUT_MIC_CAP     0x0c /* MIC Capture buffer */
    2046 #define EXTOUT_AC97_REAR_L 0x0d /* SB Live 5.1 (c) 2003 - Rear Left */
    2047 #define EXTOUT_AC97_REAR_R 0x0e /* SB Live 5.1 (c) 2003 - Rear Right */
    2048 #define EXTOUT_ACENTER     0x11 /* Analog Center */
    2049 #define EXTOUT_ALFE        0x12 /* Analog LFE */
    2050 
    2051 /* Audigy Inputs */
    2052 #define A_EXTIN_AC97_L          0x00    /* AC'97 capture channel - left */
    2053 #define A_EXTIN_AC97_R          0x01    /* AC'97 capture channel - right */
    2054 #define A_EXTIN_SPDIF_CD_L      0x02    /* digital CD left */
    2055 #define A_EXTIN_SPDIF_CD_R      0x03    /* digital CD left */
    2056 #define A_EXTIN_OPT_SPDIF_L     0x04    /* audigy drive Optical SPDIF - left */
    2057 #define A_EXTIN_OPT_SPDIF_R     0x05    /*                              right */
    2058 #define A_EXTIN_LINE2_L         0x08    /* audigy drive line2/mic2 - left */
    2059 #define A_EXTIN_LINE2_R         0x09    /*                           right */
    2060 #define A_EXTIN_ADC_L           0x0a    /* Philips ADC - left */
    2061 #define A_EXTIN_ADC_R           0x0b    /*               right */
    2062 #define A_EXTIN_AUX2_L          0x0c    /* audigy drive aux2 - left */
    2063 #define A_EXTIN_AUX2_R          0x0d    /*                   - right */
    2064 
    2065 /* Audigiy Outputs */
    2066 #define A_EXTOUT_FRONT_L        0x00    /* digital front left */
    2067 #define A_EXTOUT_FRONT_R        0x01    /*               right */
    2068 #define A_EXTOUT_CENTER         0x02    /* digital front center */
    2069 #define A_EXTOUT_LFE            0x03    /* digital front lfe */
    2070 #define A_EXTOUT_HEADPHONE_L    0x04    /* headphone audigy drive left */
    2071 #define A_EXTOUT_HEADPHONE_R    0x05    /*                        right */
    2072 #define A_EXTOUT_REAR_L         0x06    /* digital rear left */
    2073 #define A_EXTOUT_REAR_R         0x07    /*              right */
    2074 #define A_EXTOUT_AFRONT_L       0x08    /* analog front left */
    2075 #define A_EXTOUT_AFRONT_R       0x09    /*              right */
    2076 #define A_EXTOUT_ACENTER        0x0a    /* analog center */
    2077 #define A_EXTOUT_ALFE           0x0b    /* analog LFE */
    2078 #define A_EXTOUT_ASIDE_L        0x0c    /* analog side left  - Audigy 2 ZS */
    2079 #define A_EXTOUT_ASIDE_R        0x0d    /*             right - Audigy 2 ZS */
    2080 #define A_EXTOUT_AREAR_L        0x0e    /* analog rear left */
    2081 #define A_EXTOUT_AREAR_R        0x0f    /*             right */
    2082 #define A_EXTOUT_AC97_L         0x10    /* AC97 left (front) */
    2083 #define A_EXTOUT_AC97_R         0x11    /*      right */
    2084 #define A_EXTOUT_ADC_CAP_L      0x16    /* ADC capture buffer left */
    2085 #define A_EXTOUT_ADC_CAP_R      0x17    /*                    right */
    2086 #define A_EXTOUT_MIC_CAP        0x18    /* Mic capture buffer */
    2087 
    2088 /* Audigy constants */
    2089 #define A_C_00000000    0xc0
    2090 #define A_C_00000001    0xc1
    2091 #define A_C_00000002    0xc2
    2092 #define A_C_00000003    0xc3
    2093 #define A_C_00000004    0xc4
    2094 #define A_C_00000008    0xc5
    2095 #define A_C_00000010    0xc6
    2096 #define A_C_00000020    0xc7
    2097 #define A_C_00000100    0xc8
    2098 #define A_C_00010000    0xc9
    2099 #define A_C_00000800    0xca
    2100 #define A_C_10000000    0xcb
    2101 #define A_C_20000000    0xcc
    2102 #define A_C_40000000    0xcd
    2103 #define A_C_80000000    0xce
    2104 #define A_C_7fffffff    0xcf
    2105 #define A_C_ffffffff    0xd0
    2106 #define A_C_fffffffe    0xd1
    2107 #define A_C_c0000000    0xd2
    2108 #define A_C_4f1bbcdc    0xd3
    2109 #define A_C_5a7ef9db    0xd4
    2110 #define A_C_00100000    0xd5
    2111 #define A_GPR_ACCU      0xd6            /* ACCUM, accumulator */
    2112 #define A_GPR_COND      0xd7            /* CCR, condition register */
    2113 #define A_GPR_NOISE0    0xd8            /* noise source */
    2114 #define A_GPR_NOISE1    0xd9            /* noise source */
    2115 #define A_GPR_IRQ       0xda            /* IRQ register */
    2116 #define A_GPR_DBAC      0xdb            /* TRAM Delay Base Address Counter - internal */
    2117 #define A_GPR_DBACE     0xde            /* TRAM Delay Base Address Counter - external */
    2118 
    2119 /* definitions for debug register */
    2120 #define EMU10K1_DBG_ZC                  0x80000000      /* zero tram counter */
    2121 #define EMU10K1_DBG_SATURATION_OCCURED  0x02000000      /* saturation control */
    2122 #define EMU10K1_DBG_SATURATION_ADDR     0x01ff0000      /* saturation address */
    2123 #define EMU10K1_DBG_SINGLE_STEP         0x00008000      /* single step mode */
    2124 #define EMU10K1_DBG_STEP                0x00004000      /* start single step */
    2125 #define EMU10K1_DBG_CONDITION_CODE      0x00003e00      /* condition code */
    2126 #define EMU10K1_DBG_SINGLE_STEP_ADDR    0x000001ff      /* single step address */
    2127 
    2128 /* tank memory address line */
    2129 #ifndef __KERNEL__
    2130 #define TANKMEMADDRREG_ADDR_MASK 0x000fffff     /* 20 bit tank address field                    */
    2131 #define TANKMEMADDRREG_CLEAR     0x00800000     /* Clear tank memory                            */
    2132 #define TANKMEMADDRREG_ALIGN     0x00400000     /* Align read or write relative to tank access  */
    2133 #define TANKMEMADDRREG_WRITE     0x00200000     /* Write to tank memory                         */
    2134 #define TANKMEMADDRREG_READ      0x00100000     /* Read from tank memory                        */
    2135 #endif
    2136 
    2137 struct snd_emu10k1_fx8010_info {
    2138         unsigned int internal_tram_size;        /* in samples */
    2139         unsigned int external_tram_size;        /* in samples */
    2140         char fxbus_names[16][32];               /* names of FXBUSes */
    2141         char extin_names[16][32];               /* names of external inputs */
    2142         char extout_names[32][32];              /* names of external outputs */
    2143         unsigned int gpr_controls;              /* count of GPR controls */
    2144 };
    2145 
    2146 #define EMU10K1_GPR_TRANSLATION_NONE            0
    2147 #define EMU10K1_GPR_TRANSLATION_TABLE100        1
    2148 #define EMU10K1_GPR_TRANSLATION_BASS            2
    2149 #define EMU10K1_GPR_TRANSLATION_TREBLE          3
    2150 #define EMU10K1_GPR_TRANSLATION_ONOFF           4
    2151 
    2152 struct snd_emu10k1_fx8010_control_gpr {
    2153         struct snd_ctl_elem_id id;              /* full control ID definition */
    2154         unsigned int vcount;            /* visible count */
    2155         unsigned int count;             /* count of GPR (1..16) */
    2156         unsigned short gpr[32];         /* GPR number(s) */
    2157         unsigned int value[32];         /* initial values */
    2158         unsigned int min;               /* minimum range */
    2159         unsigned int max;               /* maximum range */
    2160         unsigned int translation;       /* translation type (EMU10K1_GPR_TRANSLATION*) */
    2161         const unsigned int *tlv;
    2162 };
    2163 
    2164 /* old ABI without TLV support */
    2165 struct snd_emu10k1_fx8010_control_old_gpr {
    2166         struct snd_ctl_elem_id id;
    2167         unsigned int vcount;
    2168         unsigned int count;
    2169         unsigned short gpr[32];
    2170         unsigned int value[32];
    2171         unsigned int min;
    2172         unsigned int max;
    2173         unsigned int translation;
    2174 };
    2175 
    2176 struct snd_emu10k1_fx8010_code {
    2177         char name[128];
    2178 
    2179         DECLARE_BITMAP(gpr_valid, 0x200); /* bitmask of valid initializers */
    2180         __u32 __user *gpr_map;          /* initializers */
    2181 
    2182         unsigned int gpr_add_control_count; /* count of GPR controls to add/replace */
    2183         struct snd_emu10k1_fx8010_control_gpr __user *gpr_add_controls; /* GPR controls to add/replace */
    2184 
    2185         unsigned int gpr_del_control_count; /* count of GPR controls to remove */
    2186         struct snd_ctl_elem_id __user *gpr_del_controls; /* IDs of GPR controls to remove */
    2187 
    2188         unsigned int gpr_list_control_count; /* count of GPR controls to list */
    2189         unsigned int gpr_list_control_total; /* total count of GPR controls */
    2190         struct snd_emu10k1_fx8010_control_gpr __user *gpr_list_controls; /* listed GPR controls */
    2191 
    2192         DECLARE_BITMAP(tram_valid, 0x100); /* bitmask of valid initializers */
    2193         __u32 __user *tram_data_map;      /* data initializers */
    2194         __u32 __user *tram_addr_map;      /* map initializers */
    2195 
    2196         DECLARE_BITMAP(code_valid, 1024); /* bitmask of valid instructions */
    2197         __u32 __user *code;               /* one instruction - 64 bits */
    2198 };
    2199 
    2200 struct snd_emu10k1_fx8010_tram {
    2201         unsigned int address;           /* 31.bit == 1 -> external TRAM */
    2202         unsigned int size;              /* size in samples (4 bytes) */
    2203         unsigned int *samples;          /* pointer to samples (20-bit) */
    2204                                         /* NULL->clear memory */
    2205 };
    2206 
    2207 struct snd_emu10k1_fx8010_pcm_rec {
    2208         unsigned int substream;         /* substream number */
    2209         unsigned int res1;              /* reserved */
    2210         unsigned int channels;          /* 16-bit channels count, zero = remove this substream */
    2211         unsigned int tram_start;        /* ring buffer position in TRAM (in samples) */
    2212         unsigned int buffer_size;       /* count of buffered samples */
    2213         unsigned short gpr_size;                /* GPR containing size of ringbuffer in samples (host) */
    2214         unsigned short gpr_ptr;         /* GPR containing current pointer in the ring buffer (host = reset, FX8010) */
    2215         unsigned short gpr_count;       /* GPR containing count of samples between two interrupts (host) */
    2216         unsigned short gpr_tmpcount;    /* GPR containing current count of samples to interrupt (host = set, FX8010) */
    2217         unsigned short gpr_trigger;     /* GPR containing trigger (activate) information (host) */
    2218         unsigned short gpr_running;     /* GPR containing info if PCM is running (FX8010) */
    2219         unsigned char pad;              /* reserved */
    2220         unsigned char etram[32];        /* external TRAM address & data (one per channel) */
    2221         unsigned int res2;              /* reserved */
    2222 };
    2223 
    2224 #define SNDRV_EMU10K1_VERSION           SNDRV_PROTOCOL_VERSION(1, 0, 1)
    2225 
    2226 #define SNDRV_EMU10K1_IOCTL_INFO        _IOR ('H', 0x10, struct snd_emu10k1_fx8010_info)
    2227 #define SNDRV_EMU10K1_IOCTL_CODE_POKE   _IOW ('H', 0x11, struct snd_emu10k1_fx8010_code)
    2228 #define SNDRV_EMU10K1_IOCTL_CODE_PEEK   _IOWR('H', 0x12, struct snd_emu10k1_fx8010_code)
    2229 #define SNDRV_EMU10K1_IOCTL_TRAM_SETUP  _IOW ('H', 0x20, int)
    2230 #define SNDRV_EMU10K1_IOCTL_TRAM_POKE   _IOW ('H', 0x21, struct snd_emu10k1_fx8010_tram)
    2231 #define SNDRV_EMU10K1_IOCTL_TRAM_PEEK   _IOWR('H', 0x22, struct snd_emu10k1_fx8010_tram)
    2232 #define SNDRV_EMU10K1_IOCTL_PCM_POKE    _IOW ('H', 0x30, struct snd_emu10k1_fx8010_pcm_rec)
    2233 #define SNDRV_EMU10K1_IOCTL_PCM_PEEK    _IOWR('H', 0x31, struct snd_emu10k1_fx8010_pcm_rec)
    2234 #define SNDRV_EMU10K1_IOCTL_PVERSION    _IOR ('H', 0x40, int)
    2235 #define SNDRV_EMU10K1_IOCTL_STOP        _IO  ('H', 0x80)
    2236 #define SNDRV_EMU10K1_IOCTL_CONTINUE    _IO  ('H', 0x81)
    2237 #define SNDRV_EMU10K1_IOCTL_ZERO_TRAM_COUNTER _IO ('H', 0x82)
    2238 #define SNDRV_EMU10K1_IOCTL_SINGLE_STEP _IOW ('H', 0x83, int)
    2239 #define SNDRV_EMU10K1_IOCTL_DBG_READ    _IOR ('H', 0x84, int)
    2240 
    2241 /* typedefs for compatibility to user-space */
    2242 typedef struct snd_emu10k1_fx8010_info emu10k1_fx8010_info_t;
    2243 typedef struct snd_emu10k1_fx8010_control_gpr emu10k1_fx8010_control_gpr_t;
    2244 typedef struct snd_emu10k1_fx8010_code emu10k1_fx8010_code_t;
    2245 typedef struct snd_emu10k1_fx8010_tram emu10k1_fx8010_tram_t;
    2246 typedef struct snd_emu10k1_fx8010_pcm_rec emu10k1_fx8010_pcm_t;
    2247 
    22481894#endif  /* __SOUND_EMU10K1_H */
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