Changeset 34 for GPL/trunk/alsa-kernel/include/sound/emu10k1.h
- Timestamp:
- Dec 11, 2005, 5:57:39 PM (20 years ago)
- File:
-
- 1 edited
-
GPL/trunk/alsa-kernel/include/sound/emu10k1.h (modified) (42 diffs)
Legend:
- Unmodified
- Added
- Removed
-
GPL/trunk/alsa-kernel/include/sound/emu10k1.h
r33 r34 26 26 #ifdef __KERNEL__ 27 27 28 #include "pcm.h"29 #include "rawmidi.h"30 #include "hwdep.h"31 #include "ac97_codec.h"32 #include "util_mem.h"28 #include <sound/pcm.h> 29 #include <sound/rawmidi.h> 30 #include <sound/hwdep.h> 31 #include <sound/ac97_codec.h> 32 #include <sound/util_mem.h> 33 33 #include <sound/pcm-indirect.h> 34 #include <sound/timer.h> 35 #include <linux/interrupt.h> 34 36 #include <asm/io.h> 35 #include <sound/timer.h>36 37 #ifndef PCI_VENDOR_ID_CREATIVE38 #define PCI_VENDOR_ID_CREATIVE 0x110239 #endif40 #ifndef PCI_DEVICE_ID_CREATIVE_EMU10K141 #define PCI_DEVICE_ID_CREATIVE_EMU10K1 0x000242 #endif43 37 44 38 /* ------------------- DEFINES -------------------- */ … … 51 45 #define NUM_G 64 /* use all channels */ 52 46 #define NUM_FXSENDS 4 53 //#define NUM_EFX_PLAYBACK 16 54 #define NUM_EFX_PLAYBACK 6 47 #define NUM_EFX_PLAYBACK 16 55 48 56 49 /* FIXME? - according to the OSS driver the EMU10K1 needs a 29 bit DMA mask */ 57 50 #define EMU10K1_DMA_MASK 0x7fffffffUL /* 31bit */ 58 #define AUDIGY_DMA_MASK 0x ffffffffUL /* 32bit*/59 51 #define AUDIGY_DMA_MASK 0x7fffffffUL /* 31bit FIXME - 32 should work? */ 52 /* See ALSA bug #1276 - rlrevell */ 60 53 61 54 #define TMEMSIZE 256*1024 … … 85 78 /* Clear pending interrupts by writing a 1 to */ 86 79 /* the relevant bits and zero to the other bits */ 87 88 #define IPR_P16V 0x80000000 /* Bit set when the CA0151 P16V chip wishes to interrupt */ 89 #define IPR_GPIOMSG 0x20000000 /* GPIO message interrupt (RE'd, still not sure which INTE bits enable it) */ 80 #define IPR_P16V 0x80000000 /* Bit set when the CA0151 P16V chip wishes 81 to interrupt */ 82 #define IPR_GPIOMSG 0x20000000 /* GPIO message interrupt (RE'd, still not sure 83 which INTE bits enable it) */ 90 84 91 85 /* The next two interrupts are for the midi port on the Audigy Drive (A_MPU1) */ … … 93 87 #define IPR_A_MIDIRECVBUFEMPTY2 0x08000000 /* MIDI UART receive buffer empty */ 94 88 95 #define IPR_SPDIFBUFFULL 0x04000000 /* SPDIF capture related, 10k2 only? (RE) */ 96 #define IPR_SPDIFBUFHALFFULL 0x02000000 /* SPDIF capture related? (RE) */ 89 #define IPR_SPDIFBUFFULL 0x04000000 /* SPDIF capture related, 10k2 only? (RE) */ 90 #define IPR_SPDIFBUFHALFFULL 0x02000000 /* SPDIF capture related? (RE) */ 91 97 92 #define IPR_SAMPLERATETRACKER 0x01000000 /* Sample rate tracker lock status change */ 98 93 #define IPR_FXDSP 0x00800000 /* Enable FX DSP interrupts */ … … 113 108 #define IPR_MIDITRANSBUFEMPTY 0x00000100 /* MIDI UART transmit buffer empty */ 114 109 #define IPR_MIDIRECVBUFEMPTY 0x00000080 /* MIDI UART receive buffer empty */ 115 #define IPR_CHANNELLOOP 0x00000040 /* Channel (half) loop interrupt(s) pending*/110 #define IPR_CHANNELLOOP 0x00000040 /* Channel (half) loop interrupt(s) pending */ 116 111 #define IPR_CHANNELNUMBERMASK 0x0000003f /* When IPR_CHANNELLOOP is set, indicates the */ 117 /* Highest set channel in CLIPL or CLIPH. When*/118 /* IP is written with CL set, the bit in CLIPL*/119 /* or CLIPH corresponding to the CIN value*/120 /* written will be cleared.*/112 /* highest set channel in CLIPL, CLIPH, HLIPL, */ 113 /* or HLIPH. When IP is written with CL set, */ 114 /* the bit in H/CLIPL or H/CLIPH corresponding */ 115 /* to the CIN value written will be cleared. */ 121 116 122 117 #define INTE 0x0c /* Interrupt enable register */ … … 245 240 #define A_GPINPUT_MASK 0xff00 246 241 #define A_GPOUTPUT_MASK 0x00ff 242 247 243 // Audigy output/GPIO stuff taken from the kX drivers 248 #define A_IOCFG_GPOUT0 0x0044 /* analog/digital*/249 #define A_IOCFG_DISABLE_ANALOG 0x0040 /* = 'enable' for Audigy2 (chiprev=4)*/250 #define A_IOCFG_ENABLE_DIGITAL 244 #define A_IOCFG_GPOUT0 0x0044 /* analog/digital */ 245 #define A_IOCFG_DISABLE_ANALOG 0x0040 /* = 'enable' for Audigy2 (chiprev=4) */ 246 #define A_IOCFG_ENABLE_DIGITAL 0x0004 251 247 #define A_IOCFG_UNKNOWN_20 0x0020 252 #define A_IOCFG_DISABLE_AC97_FRONT 0x0080 /* turn off ac97 front -> front (10k2.1) 253 #define A_IOCFG_GPOUT1 0x0002 /* IR? drive's internal bypass (?)*/248 #define A_IOCFG_DISABLE_AC97_FRONT 0x0080 /* turn off ac97 front -> front (10k2.1) */ 249 #define A_IOCFG_GPOUT1 0x0002 /* IR? drive's internal bypass (?) */ 254 250 #define A_IOCFG_GPOUT2 0x0001 /* IR */ 255 256 #define A_IOCFG_MULTIPURPOSE_JACK 0x2000 /* center+lfe+rear_center (a2/a2ex) */ 257 /* + digital for generic 10k2 */ 258 #define A_IOCFG_DIGITAL_JACK 0x1000 /* digital for a2 platinum */ 251 #define A_IOCFG_MULTIPURPOSE_JACK 0x2000 /* center+lfe+rear_center (a2/a2ex) */ 252 /* + digital for generic 10k2 */ 253 #define A_IOCFG_DIGITAL_JACK 0x1000 /* digital for a2 platinum */ 259 254 #define A_IOCFG_FRONT_JACK 0x4000 260 255 #define A_IOCFG_REAR_JACK 0x8000 261 #define A_IOCFG_PHONES_JACK 0x0100 /* LiveDrive 256 #define A_IOCFG_PHONES_JACK 0x0100 /* LiveDrive */ 262 257 263 258 /* outputs: 264 * for audigy2 platinum:0xa00265 * for a2 platinum ex:0x1c00266 * for a1 platinum:0x0259 * for audigy2 platinum: 0xa00 260 * for a2 platinum ex: 0x1c00 261 * for a1 platinum: 0x0 267 262 */ 263 268 264 #define TIMER 0x1a /* Timer terminal count register */ 269 265 /* NOTE: After the rate is changed, a maximum */ … … 281 277 282 278 /* Available on the Audigy 2 and Audigy 4 only. This is the P16V chip. */ 283 #define PTR2 0x20 /* Indexed register set pointer register*/284 #define DATA2 0x24 /* Indexed register set data register*/285 #define IPR2 0x28 /* P16V interrupt pending register*/279 #define PTR2 0x20 /* Indexed register set pointer register */ 280 #define DATA2 0x24 /* Indexed register set data register */ 281 #define IPR2 0x28 /* P16V interrupt pending register */ 286 282 #define IPR2_PLAYBACK_CH_0_LOOP 0x00001000 /* Playback Channel 0 loop */ 287 283 #define IPR2_PLAYBACK_CH_0_HALF_LOOP 0x00000100 /* Playback Channel 0 half loop */ 288 284 #define IPR2_CAPTURE_CH_0_LOOP 0x00100000 /* Capture Channel 0 loop */ 289 285 #define IPR2_CAPTURE_CH_0_HALF_LOOP 0x00010000 /* Capture Channel 0 half loop */ 290 /* 0x00000100 Playback. Only in once per period.291 * 0x00110000 Capture. Int on half buffer.292 */293 #define INTE2 0x2c /* P16V Interrupt enable register.*/286 /* 0x00000100 Playback. Only in once per period. 287 * 0x00110000 Capture. Int on half buffer. 288 */ 289 #define INTE2 0x2c /* P16V Interrupt enable register. */ 294 290 #define INTE2_PLAYBACK_CH_0_LOOP 0x00001000 /* Playback Channel 0 loop */ 295 291 #define INTE2_PLAYBACK_CH_0_HALF_LOOP 0x00000100 /* Playback Channel 0 half loop */ … … 302 298 #define INTE2_CAPTURE_CH_0_LOOP 0x00100000 /* Capture Channel 0 loop */ 303 299 #define INTE2_CAPTURE_CH_0_HALF_LOOP 0x00010000 /* Caputre Channel 0 half loop */ 304 #define HCFG2 0x34/* Defaults: 0, win2000 sets it to 00004201 */305 /* 0x00000000 2-channel output. */306 /* 0x00000200 8-channel output. */307 /* 0x00000004 pauses stream/irq fail. */308 /* Rest of bits no nothing to sound output */309 /* bit 0: Enable P16V audio.310 * bit 1: Lock P16V record memory cache.311 * bit 2: Lock P16V playback memory cache.312 * bit 3: Dummy record insert zero samples.313 * bit 8: Record 8-channel in phase.314 * bit 9: Playback 8-channel in phase.315 * bit 11-12: Playback mixer attenuation: 0=0dB, 1=-6dB, 2=-12dB, 3=Mute.316 * bit 13: Playback mixer enable.317 * bit 14: Route SRC48 mixer output to fx engine.318 * bit 15: Enable IEEE 1394 chip.319 */320 #define IPR3 0x38 /* Cdif interrupt pending register*/321 #define INTE3 0x3c /* Cdif interrupt enable register.*/300 #define HCFG2 0x34 /* Defaults: 0, win2000 sets it to 00004201 */ 301 /* 0x00000000 2-channel output. */ 302 /* 0x00000200 8-channel output. */ 303 /* 0x00000004 pauses stream/irq fail. */ 304 /* Rest of bits no nothing to sound output */ 305 /* bit 0: Enable P16V audio. 306 * bit 1: Lock P16V record memory cache. 307 * bit 2: Lock P16V playback memory cache. 308 * bit 3: Dummy record insert zero samples. 309 * bit 8: Record 8-channel in phase. 310 * bit 9: Playback 8-channel in phase. 311 * bit 11-12: Playback mixer attenuation: 0=0dB, 1=-6dB, 2=-12dB, 3=Mute. 312 * bit 13: Playback mixer enable. 313 * bit 14: Route SRC48 mixer output to fx engine. 314 * bit 15: Enable IEEE 1394 chip. 315 */ 316 #define IPR3 0x38 /* Cdif interrupt pending register */ 317 #define INTE3 0x3c /* Cdif interrupt enable register. */ 322 318 /************************************************************************************************/ 323 319 /* PCI function 1 registers, address = <val> + PCIBASE1 */ … … 443 439 444 440 #define ENVVOL 0x10 /* Volume envelope register */ 445 #define ENVVOL_MASK 0x0000ffff /* Current value of volume envelope state variable */ 441 #define ENVVOL_MASK 0x0000ffff /* Current value of volume envelope state variable */ 446 442 /* 0x8000-n == 666*n usec delay */ 447 443 … … 529 525 /* NOTE: All channels contain internal variables; do */ 530 526 /* not write to these locations. */ 527 531 528 /* 1f something */ 529 532 530 #define CD0 0x20 /* Cache data 0 register */ 533 531 #define CD1 0x21 /* Cache data 1 register */ … … 579 577 #define FXWC 0x43 /* FX output write channels register */ 580 578 /* When set, each bit enables the writing of the */ 581 /* corresponding FX output channel into host memory */ 579 /* corresponding FX output channel (internal registers */ 580 /* 0x20-0x3f) to host memory. This mode of recording */ 581 /* is 16bit, 48KHz only. All 32 channels can be enabled */ 582 /* simultaneously. */ 583 582 584 #define FXWC_DEFAULTROUTE_C (1<<0) /* left emu out? */ 583 585 #define FXWC_DEFAULTROUTE_B (1<<1) /* right emu out? */ … … 613 615 #define FXBA 0x47 /* FX Buffer Address */ 614 616 #define FXBA_MASK 0xfffff000 /* 20 bit base address */ 615 /* 0x48 something - word access, defaults to 3f */ 617 618 /* 0x48 something - word access, defaults to 3f */ 619 616 620 #define MICBS 0x49 /* Microphone buffer size register */ 617 621 … … 717 721 718 722 #define SPBYPASS 0x5e /* SPDIF BYPASS mode register */ 719 #define SPBYPASS_SPDIF0_MASK 0x00000003 /* SPDIF 0 bypass mode */ 720 #define SPBYPASS_SPDIF1_MASK 0x0000000c /* SPDIF 1 bypass mode */ 721 /* bypass mode: 0 - DSP; 1 - SPDIF A, 2 - SPDIF B, 3 - SPDIF C */ 722 #define SPBYPASS_FORMAT 0x00000f00 /* If 1, SPDIF XX uses 24 bit, if 0 - 20 bit */ 723 #define SPBYPASS_SPDIF0_MASK 0x00000003 /* SPDIF 0 bypass mode */ 724 #define SPBYPASS_SPDIF1_MASK 0x0000000c /* SPDIF 1 bypass mode */ 725 /* bypass mode: 0 - DSP; 1 - SPDIF A, 2 - SPDIF B, 3 - SPDIF C */ 726 #define SPBYPASS_FORMAT 0x00000f00 /* If 1, SPDIF XX uses 24 bit, if 0 - 20 bit */ 727 723 728 #define AC97SLOT 0x5f /* additional AC97 slots enable bits */ 724 #define AC97SLOT_REAR_RIGHT 0x01/* Rear left */725 #define AC97SLOT_REAR_LEFT 0x02/* Rear right */729 #define AC97SLOT_REAR_RIGHT 0x01 /* Rear left */ 730 #define AC97SLOT_REAR_LEFT 0x02 /* Rear right */ 726 731 #define AC97SLOT_CNTR 0x10 /* Center enable */ 727 732 #define AC97SLOT_LFE 0x20 /* LFE enable */ … … 737 742 738 743 /* These three bitfields apply to CDSRCS, GPSRCS, and (except as noted) ZVSRCS. */ 739 #define SRCS_SPDIFVALID 0x04000000 /* SPDIF stream valid*/744 #define SRCS_SPDIFVALID 0x04000000 /* SPDIF stream valid */ 740 745 #define SRCS_SPDIFLOCKED 0x02000000 /* SPDIF stream locked */ 741 746 #define SRCS_RATELOCKED 0x01000000 /* Sample rate locked */ … … 765 770 #define FXIDX_IDX 0x10000065 766 771 767 /* The 32-bit HLIx and HLIPx registers all have one bit per channel control/status 768 #define HLIEL 0x66 /* Channel half loop interrupt enable low register*/769 770 #define HLIEH 0x67 /* Channel half loop interrupt enable high register*/771 772 #define HLIPL 0x68 /* Channel half loop interrupt pending low register*/773 774 #define HLIPH 0x69 /* Channel half loop interrupt pending high register*/772 /* The 32-bit HLIx and HLIPx registers all have one bit per channel control/status */ 773 #define HLIEL 0x66 /* Channel half loop interrupt enable low register */ 774 775 #define HLIEH 0x67 /* Channel half loop interrupt enable high register */ 776 777 #define HLIPL 0x68 /* Channel half loop interrupt pending low register */ 778 779 #define HLIPH 0x69 /* Channel half loop interrupt pending high register */ 775 780 776 781 // 0x6a,6b,6c used for some recording … … 786 791 #define A_MUDATA2 0x72 787 792 #define A_MUCMD2 0x73 788 #define A_MUSTAT2 A_MUCMD2 793 #define A_MUSTAT2 A_MUCMD2 789 794 790 795 /* The next two are the Audigy equivalent of FXWC */ … … 795 800 796 801 #define A_SPDIF_SAMPLERATE 0x76 /* Set the sample rate of SPDIF output */ 797 #define A_SAMPLE_RATE 0x76 /* Various sample rate settings. */ 798 #define A_SAMPLE_RATE_NOT_USED 0x0ffc111e /* Bits that are not used and cannot be set. */ 799 #define A_SAMPLE_RATE_UNKNOWN 0xf0030001 /* Bits that can be set, but have unknown use. */ 800 #define A_SPDIF_RATE_MASK 0x000000e0 /* Any other values for rates, just use 48000 */ 801 #define A_SPDIF_48000 0x00000000 802 #define A_SPDIF_192000 0x00000020 803 #define A_SPDIF_96000 0x00000040 804 #define A_SPDIF_44100 0x00000080 805 806 #define A_I2S_CAPTURE_RATE_MASK 0x00000e00 /* This sets the capture PCM rate, but it is */ 807 #define A_I2S_CAPTURE_48000 0x00000000 /* unclear if this sets the ADC rate as well. */ 808 #define A_I2S_CAPTURE_192000 0x00000200 809 #define A_I2S_CAPTURE_96000 0x00000400 810 #define A_I2S_CAPTURE_44100 0x00000800 811 812 #define A_PCM_RATE_MASK 0x0000e000 /* This sets the playback PCM rate on the P16V */ 813 #define A_PCM_48000 0x00000000 814 #define A_PCM_192000 0x00002000 815 #define A_PCM_96000 0x00004000 816 #define A_PCM_44100 0x00008000 817 /* 0x77,0x78,0x79 "something i2s-related" - default to 0x01080000 on my audigy 2 ZS --rlrevell */ 802 #define A_SAMPLE_RATE 0x76 /* Various sample rate settings. */ 803 #define A_SAMPLE_RATE_NOT_USED 0x0ffc111e /* Bits that are not used and cannot be set. */ 804 #define A_SAMPLE_RATE_UNKNOWN 0xf0030001 /* Bits that can be set, but have unknown use. */ 805 #define A_SPDIF_RATE_MASK 0x000000e0 /* Any other values for rates, just use 48000 */ 806 #define A_SPDIF_48000 0x00000000 807 #define A_SPDIF_192000 0x00000020 808 #define A_SPDIF_96000 0x00000040 809 #define A_SPDIF_44100 0x00000080 810 811 #define A_I2S_CAPTURE_RATE_MASK 0x00000e00 /* This sets the capture PCM rate, but it is */ 812 #define A_I2S_CAPTURE_48000 0x00000000 /* unclear if this sets the ADC rate as well. */ 813 #define A_I2S_CAPTURE_192000 0x00000200 814 #define A_I2S_CAPTURE_96000 0x00000400 815 #define A_I2S_CAPTURE_44100 0x00000800 816 817 #define A_PCM_RATE_MASK 0x0000e000 /* This sets the playback PCM rate on the P16V */ 818 #define A_PCM_48000 0x00000000 819 #define A_PCM_192000 0x00002000 820 #define A_PCM_96000 0x00004000 821 #define A_PCM_44100 0x00008000 822 823 /* 0x77,0x78,0x79 "something i2s-related" - default to 0x01080000 on my audigy 2 ZS --rlrevell */ 818 824 /* 0x7a, 0x7b - lookup tables */ 819 825 … … 830 836 #define A_FXSENDAMOUNT_H_MASK 0x000000FF 831 837 /* 0x7c, 0x7e "high bit is used for filtering" */ 838 832 839 /* The send amounts for this one are the same as used with the emu10k1 */ 833 840 #define A_FXRT1 0x7e … … 842 849 #define A_FXGPREGBASE 0x400 /* Audigy GPRs, 0x400 to 0x5ff */ 843 850 844 #define A_TANKMEMCTLREGBASE 0x100/* Tank memory control registers base - only for Audigy */845 #define A_TANKMEMCTLREG_MASK 0x1f/* only 5 bits used - only for Audigy */851 #define A_TANKMEMCTLREGBASE 0x100 /* Tank memory control registers base - only for Audigy */ 852 #define A_TANKMEMCTLREG_MASK 0x1f /* only 5 bits used - only for Audigy */ 846 853 847 854 /* Tank audio data is logarithmically compressed down to 16 bits before writing to TRAM and is */ … … 881 888 /* ------------------- STRUCTURES -------------------- */ 882 889 883 typedef struct _snd_emu10k1 emu10k1_t; 884 typedef struct _snd_emu10k1_voice emu10k1_voice_t; 885 typedef struct _snd_emu10k1_pcm emu10k1_pcm_t; 886 887 typedef enum { 888 EMU10K1_EFX, 889 EMU10K1_PCM, 890 EMU10K1_SYNTH, 891 EMU10K1_MIDI 892 } emu10k1_voice_type_t; 893 894 struct _snd_emu10k1_voice { 895 emu10k1_t *emu; 890 enum { 891 EMU10K1_EFX, 892 EMU10K1_PCM, 893 EMU10K1_SYNTH, 894 EMU10K1_MIDI 895 }; 896 897 struct snd_emu10k1; 898 899 struct snd_emu10k1_voice { 900 struct snd_emu10k1 *emu; 896 901 int number; 897 int use: 1,898 899 900 901 902 void (*interrupt)(emu10k1_t *emu, emu10k1_voice_t*pvoice);903 904 emu10k1_pcm_t*epcm;905 }; 906 907 typedefenum {908 909 910 911 912 913 } snd_emu10k1_pcm_type_t;914 915 struct _snd_emu10k1_pcm {916 emu10k1_t*emu;917 snd_emu10k1_pcm_type_t type;918 snd_pcm_substream_t*substream;919 emu10k1_voice_t*voices[NUM_EFX_PLAYBACK];920 emu10k1_voice_t*extra;902 unsigned int use: 1, 903 pcm: 1, 904 efx: 1, 905 synth: 1, 906 midi: 1; 907 void (*interrupt)(struct snd_emu10k1 *emu, struct snd_emu10k1_voice *pvoice); 908 909 struct snd_emu10k1_pcm *epcm; 910 }; 911 912 enum { 913 PLAYBACK_EMUVOICE, 914 PLAYBACK_EFX, 915 CAPTURE_AC97ADC, 916 CAPTURE_AC97MIC, 917 CAPTURE_EFX 918 }; 919 920 struct snd_emu10k1_pcm { 921 struct snd_emu10k1 *emu; 922 int type; 923 struct snd_pcm_substream *substream; 924 struct snd_emu10k1_voice *voices[NUM_EFX_PLAYBACK]; 925 struct snd_emu10k1_voice *extra; 921 926 unsigned short running; 922 927 unsigned short first_ptr; 923 s nd_util_memblk_t*memblk;928 struct snd_util_memblk *memblk; 924 929 unsigned int start_addr; 925 930 unsigned int ccca_start_addr; … … 935 940 }; 936 941 937 typedef struct { 942 struct snd_emu10k1_pcm_mixer { 943 /* mono, left, right x 8 sends (4 on emu10k1) */ 938 944 unsigned char send_routing[3][8]; 939 945 unsigned char send_volume[3][8]; 940 946 unsigned short attn[3]; 941 emu10k1_pcm_t*epcm;942 } emu10k1_pcm_mixer_t;947 struct snd_emu10k1_pcm *epcm; 948 }; 943 949 944 950 #define snd_emu10k1_compose_send_routing(route) \ … … 951 957 ((unsigned int)route[4] | ((unsigned int)route[5] << 8) | ((unsigned int)route[6] << 16) | ((unsigned int)route[7] << 24)) 952 958 953 typedefstruct snd_emu10k1_memblk {954 s nd_util_memblk_tmem;959 struct snd_emu10k1_memblk { 960 struct snd_util_memblk mem; 955 961 /* private part */ 956 962 int first_page, last_page, pages, mapped_page; … … 958 964 struct list_head mapped_link; 959 965 struct list_head mapped_order_link; 960 } emu10k1_memblk_t;966 }; 961 967 962 968 #define snd_emu10k1_memblk_offset(blk) (((blk)->mapped_page << PAGE_SHIFT) | ((blk)->mem.offset & (PAGE_SIZE - 1))) … … 964 970 #define EMU10K1_MAX_TRAM_BLOCKS_PER_CODE 16 965 971 966 typedef struct{972 struct snd_emu10k1_fx8010_ctl { 967 973 struct list_head list; /* list link container */ 968 974 unsigned int vcount; 969 975 unsigned int count; /* count of GPR (1..16) */ 970 unsigned short gpr[32];/* GPR number(s) */976 unsigned short gpr[32]; /* GPR number(s) */ 971 977 unsigned int value[32]; 972 978 unsigned int min; /* minimum range */ 973 979 unsigned int max; /* maximum range */ 974 980 unsigned int translation; /* translation type (EMU10K1_GPR_TRANSLATION*) */ 975 s nd_kcontrol_t*kcontrol;976 } snd_emu10k1_fx8010_ctl_t;977 978 typedef void (snd_fx8010_irq_handler_t)( emu10k1_t*emu, void *private_data);979 980 typedef struct _snd_emu10k1_fx8010_irq {981 struct _snd_emu10k1_fx8010_irq *next;982 983 981 struct snd_kcontrol *kcontrol; 982 }; 983 984 typedef void (snd_fx8010_irq_handler_t)(struct snd_emu10k1 *emu, void *private_data); 985 986 struct snd_emu10k1_fx8010_irq { 987 struct snd_emu10k1_fx8010_irq *next; 988 snd_fx8010_irq_handler_t *handler; 989 unsigned short gpr_running; 984 990 void *private_data; 985 } snd_emu10k1_fx8010_irq_t;986 987 typedef struct{991 }; 992 993 struct snd_emu10k1_fx8010_pcm { 988 994 unsigned int valid: 1, 989 995 opened: 1, … … 991 997 unsigned int channels; /* 16-bit channels count */ 992 998 unsigned int tram_start; /* initial ring buffer position in TRAM (in samples) */ 993 994 unsigned short gpr_size;/* GPR containing size of ring buffer in samples (host) */995 unsigned short gpr_ptr;/* GPR containing current pointer in the ring buffer (host = reset, FX8010) */996 unsigned short gpr_count;/* GPR containing count of samples between two interrupts (host) */997 unsigned short gpr_tmpcount;/* GPR containing current count of samples to interrupt (host = set, FX8010) */998 unsigned short gpr_trigger;/* GPR containing trigger (activate) information (host) */999 unsigned short gpr_running;/* GPR containing info if PCM is running (FX8010) */1000 1001 snd_pcm_indirect_t pcm_rec;999 unsigned int buffer_size; /* count of buffered samples */ 1000 unsigned short gpr_size; /* GPR containing size of ring buffer in samples (host) */ 1001 unsigned short gpr_ptr; /* GPR containing current pointer in the ring buffer (host = reset, FX8010) */ 1002 unsigned short gpr_count; /* GPR containing count of samples between two interrupts (host) */ 1003 unsigned short gpr_tmpcount; /* GPR containing current count of samples to interrupt (host = set, FX8010) */ 1004 unsigned short gpr_trigger; /* GPR containing trigger (activate) information (host) */ 1005 unsigned short gpr_running; /* GPR containing info if PCM is running (FX8010) */ 1006 unsigned char etram[32]; /* external TRAM address & data */ 1007 struct snd_pcm_indirect pcm_rec; 1002 1008 unsigned int tram_pos; 1003 1009 unsigned int tram_shift; 1004 s nd_emu10k1_fx8010_irq_t*irq;1005 } snd_emu10k1_fx8010_pcm_t;1006 1007 typedef struct{1010 struct snd_emu10k1_fx8010_irq *irq; 1011 }; 1012 1013 struct snd_emu10k1_fx8010 { 1008 1014 unsigned short fxbus_mask; /* used FX buses (bitmask) */ 1009 1015 unsigned short extin_mask; /* used external inputs (bitmask) */ 1010 1016 unsigned short extout_mask; /* used external outputs (bitmask) */ 1011 1017 unsigned short pad1; 1012 1013 1018 unsigned int itram_size; /* internal TRAM size in samples */ 1019 struct snd_dma_buffer etram_pages; /* external TRAM pages and size */ 1014 1020 unsigned int dbg; /* FX debugger register */ 1015 1021 unsigned char name[128]; … … 1018 1024 struct list_head gpr_ctl; /* GPR controls */ 1019 1025 struct semaphore lock; 1020 s nd_emu10k1_fx8010_pcm_tpcm[8];1026 struct snd_emu10k1_fx8010_pcm pcm[8]; 1021 1027 spinlock_t irq_lock; 1022 s nd_emu10k1_fx8010_irq_t*irq_handlers;1023 } snd_emu10k1_fx8010_t;1024 1025 #define emu10k1_gpr_ctl(n) list_entry(n, s nd_emu10k1_fx8010_ctl_t, list)1026 1027 typedef struct{1028 struct _snd_emu10k1 *emu;1029 s nd_rawmidi_t*rmidi;1030 s nd_rawmidi_substream_t*substream_input;1031 s nd_rawmidi_substream_t*substream_output;1028 struct snd_emu10k1_fx8010_irq *irq_handlers; 1029 }; 1030 1031 #define emu10k1_gpr_ctl(n) list_entry(n, struct snd_emu10k1_fx8010_ctl, list) 1032 1033 struct snd_emu10k1_midi { 1034 struct snd_emu10k1 *emu; 1035 struct snd_rawmidi *rmidi; 1036 struct snd_rawmidi_substream *substream_input; 1037 struct snd_rawmidi_substream *substream_output; 1032 1038 unsigned int midi_mode; 1033 1039 spinlock_t input_lock; … … 1037 1043 int port; 1038 1044 int ipr_tx, ipr_rx; 1039 void (*interrupt)( emu10k1_t*emu, unsigned int status);1040 } emu10k1_midi_t;1041 1042 typedef struct{1043 1044 1045 1046 1047 1048 1049 1050 unsigned char ca_cardbus_chip; /* Audigy 2 ZS Notebook*/1051 unsigned char ca0108_chip; /* Audigy 2 Value*/1052 1053 1054 unsigned char sblive51;/* SBLive! 5.1 - extout 0x11 -> center, 0x12 -> lfe */1055 1056 unsigned char ac97_chip; /* Has an AC97 chip*/1057 1058 const char *driver;1059 const char *name;1060 const char *id;/* for backward compatibility - can be NULL if not needed */1061 } emu_chip_details_t;1062 1063 struct _snd_emu10k1 {1045 void (*interrupt)(struct snd_emu10k1 *emu, unsigned int status); 1046 }; 1047 1048 struct snd_emu_chip_details { 1049 u32 vendor; 1050 u32 device; 1051 u32 subsystem; 1052 unsigned char revision; 1053 unsigned char emu10k1_chip; /* Original SB Live. Not SB Live 24bit. */ 1054 unsigned char emu10k2_chip; /* Audigy 1 or Audigy 2. */ 1055 unsigned char ca0102_chip; /* Audigy 1 or Audigy 2. Not SB Audigy 2 Value. */ 1056 unsigned char ca0108_chip; /* Audigy 2 Value */ 1057 unsigned char ca_cardbus_chip; /* Audigy 2 ZS Notebook */ 1058 unsigned char ca0151_chip; /* P16V */ 1059 unsigned char spk71; /* Has 7.1 speakers */ 1060 unsigned char sblive51; /* SBLive! 5.1 - extout 0x11 -> center, 0x12 -> lfe */ 1061 unsigned char spdif_bug; /* Has Spdif phasing bug */ 1062 unsigned char ac97_chip; /* Has an AC97 chip: 1 = mandatory, 2 = optional */ 1063 unsigned char ecard; /* APS EEPROM */ 1064 const char *driver; 1065 const char *name; 1066 const char *id; /* for backward compatibility - can be NULL if not needed */ 1067 }; 1068 1069 struct snd_emu10k1 { 1064 1070 int irq; 1065 1071 1066 unsigned long port; /* I/O port number */ 1067 unsigned int tos_link: 1, /* tos link detected */ 1068 rear_ac97: 1; /* rear channels are on AC'97 */ 1069 const emu_chip_details_t *card_capabilities; /* Contains profile of card capabilities */ 1072 unsigned long port; /* I/O port number */ 1073 unsigned int tos_link: 1, /* tos link detected */ 1074 rear_ac97: 1, /* rear channels are on AC'97 */ 1075 enable_ir: 1; 1076 /* Contains profile of card capabilities */ 1077 const struct snd_emu_chip_details *card_capabilities; 1070 1078 unsigned int audigy; /* is Audigy? */ 1071 1079 unsigned int revision; /* chip revision */ … … 1074 1082 unsigned int card_type; /* EMU10K1_CARD_* */ 1075 1083 unsigned int ecard_ctrl; /* ecard control bits */ 1076 unsigned long dma_mask; /* PCI DMA mask */ 1077 int max_cache_pages; /* max memory size / PAGE_SIZE */ 1078 struct snd_dma_buffer silent_page; /* silent page */ 1079 struct snd_dma_buffer ptb_pages; /* page table pages */ 1080 struct snd_dma_device p16v_dma_dev; 1081 struct snd_dma_buffer p16v_buffer; 1082 snd_util_memhdr_t *memhdr; /* page allocation list */ 1083 emu10k1_memblk_t *reserved_page; /* reserved page */ 1084 unsigned long dma_mask; /* PCI DMA mask */ 1085 int max_cache_pages; /* max memory size / PAGE_SIZE */ 1086 struct snd_dma_buffer silent_page; /* silent page */ 1087 struct snd_dma_buffer ptb_pages; /* page table pages */ 1088 struct snd_dma_device p16v_dma_dev; 1089 struct snd_dma_buffer p16v_buffer; 1090 1091 struct snd_util_memhdr *memhdr; /* page allocation list */ 1092 struct snd_emu10k1_memblk *reserved_page; /* reserved page */ 1084 1093 1085 1094 struct list_head mapped_link_head; … … 1091 1100 unsigned int spdif_bits[3]; /* s/pdif out setup */ 1092 1101 1093 s nd_emu10k1_fx8010_tfx8010; /* FX8010 info */1102 struct snd_emu10k1_fx8010 fx8010; /* FX8010 info */ 1094 1103 int gpr_base; 1095 1096 ac97_t*ac97;1104 1105 struct snd_ac97 *ac97; 1097 1106 1098 1107 struct pci_dev *pci; 1099 snd_card_t *card; 1100 snd_pcm_t *pcm; 1101 snd_pcm_t *pcm_mic; 1102 snd_pcm_t *pcm_efx; 1103 snd_pcm_t *pcm_p16v; 1108 struct snd_card *card; 1109 struct snd_pcm *pcm; 1110 struct snd_pcm *pcm_mic; 1111 struct snd_pcm *pcm_efx; 1112 struct snd_pcm *pcm_multi; 1113 struct snd_pcm *pcm_p16v; 1104 1114 1105 1115 spinlock_t synth_lock; 1106 1116 void *synth; 1107 int (*get_synth_voice)( emu10k1_t*emu);1117 int (*get_synth_voice)(struct snd_emu10k1 *emu); 1108 1118 1109 1119 spinlock_t reg_lock; … … 1112 1122 struct semaphore ptb_lock; 1113 1123 1114 emu10k1_voice_t voices[NUM_G]; 1115 emu10k1_voice_t p16v_voices[4]; 1116 emu10k1_voice_t p16v_capture_voice; 1117 int p16v_device_offset; 1118 u32 p16v_capture_source; 1119 u32 p16v_capture_channel; 1120 emu10k1_pcm_mixer_t pcm_mixer[32]; 1121 emu10k1_pcm_mixer_t efx_pcm_mixer[NUM_EFX_PLAYBACK]; 1122 snd_kcontrol_t *ctl_send_routing; 1123 snd_kcontrol_t *ctl_send_volume; 1124 snd_kcontrol_t *ctl_attn; 1125 snd_kcontrol_t *ctl_efx_send_routing; 1126 snd_kcontrol_t *ctl_efx_send_volume; 1127 snd_kcontrol_t *ctl_efx_attn; 1128 1129 void (*hwvol_interrupt)(emu10k1_t *emu, unsigned int status); 1130 void (*capture_interrupt)(emu10k1_t *emu, unsigned int status); 1131 void (*capture_mic_interrupt)(emu10k1_t *emu, unsigned int status); 1132 void (*capture_efx_interrupt)(emu10k1_t *emu, unsigned int status); 1133 void (*spdif_interrupt)(emu10k1_t *emu, unsigned int status); 1134 void (*dsp_interrupt)(emu10k1_t *emu); 1135 1136 snd_pcm_substream_t *pcm_capture_substream; 1137 snd_pcm_substream_t *pcm_capture_mic_substream; 1138 snd_pcm_substream_t *pcm_capture_efx_substream; 1139 snd_pcm_substream_t *pcm_playback_efx_substream; 1140 1141 snd_timer_t *timer; 1142 1143 emu10k1_midi_t midi; 1144 emu10k1_midi_t midi2; /* for audigy */ 1145 1146 unsigned int efx_voices_mask[2]; 1147 unsigned int next_free_voice; 1148 }; 1149 1150 int snd_emu10k1_create(snd_card_t * card, 1124 struct snd_emu10k1_voice voices[NUM_G]; 1125 struct snd_emu10k1_voice p16v_voices[4]; 1126 struct snd_emu10k1_voice p16v_capture_voice; 1127 int p16v_device_offset; 1128 u32 p16v_capture_source; 1129 u32 p16v_capture_channel; 1130 struct snd_emu10k1_pcm_mixer pcm_mixer[32]; 1131 struct snd_emu10k1_pcm_mixer efx_pcm_mixer[NUM_EFX_PLAYBACK]; 1132 struct snd_kcontrol *ctl_send_routing; 1133 struct snd_kcontrol *ctl_send_volume; 1134 struct snd_kcontrol *ctl_attn; 1135 struct snd_kcontrol *ctl_efx_send_routing; 1136 struct snd_kcontrol *ctl_efx_send_volume; 1137 struct snd_kcontrol *ctl_efx_attn; 1138 1139 void (*hwvol_interrupt)(struct snd_emu10k1 *emu, unsigned int status); 1140 void (*capture_interrupt)(struct snd_emu10k1 *emu, unsigned int status); 1141 void (*capture_mic_interrupt)(struct snd_emu10k1 *emu, unsigned int status); 1142 void (*capture_efx_interrupt)(struct snd_emu10k1 *emu, unsigned int status); 1143 void (*spdif_interrupt)(struct snd_emu10k1 *emu, unsigned int status); 1144 void (*dsp_interrupt)(struct snd_emu10k1 *emu); 1145 1146 struct snd_pcm_substream *pcm_capture_substream; 1147 struct snd_pcm_substream *pcm_capture_mic_substream; 1148 struct snd_pcm_substream *pcm_capture_efx_substream; 1149 struct snd_pcm_substream *pcm_playback_efx_substream; 1150 1151 struct snd_timer *timer; 1152 1153 struct snd_emu10k1_midi midi; 1154 struct snd_emu10k1_midi midi2; /* for audigy */ 1155 1156 unsigned int efx_voices_mask[2]; 1157 unsigned int next_free_voice; 1158 1159 #ifdef CONFIG_PM 1160 unsigned int *saved_ptr; 1161 unsigned int *saved_gpr; 1162 unsigned int *tram_val_saved; 1163 unsigned int *tram_addr_saved; 1164 unsigned int *saved_icode; 1165 unsigned int *p16v_saved; 1166 unsigned int saved_a_iocfg, saved_hcfg; 1167 #endif 1168 1169 }; 1170 1171 int snd_emu10k1_create(struct snd_card *card, 1151 1172 struct pci_dev *pci, 1152 1173 unsigned short extin_mask, 1153 1174 unsigned short extout_mask, 1154 1175 long max_cache_bytes, 1155 1156 1157 emu10k1_t** remu);1158 1159 int snd_emu10k1_pcm( emu10k1_t * emu, int device, snd_pcm_t** rpcm);1160 int snd_emu10k1_pcm_mic( emu10k1_t * emu, int device, snd_pcm_t** rpcm);1161 int snd_emu10k1_pcm_efx( emu10k1_t * emu, int device, snd_pcm_t** rpcm);1162 int snd_p16v_pcm( emu10k1_t * emu, int device, snd_pcm_t** rpcm);1163 int snd_p16v_free( emu10k1_t* emu);1164 int snd_p16v_mixer( emu10k1_t* emu);1165 int snd_emu10k1_pcm_multi( emu10k1_t * emu, int device, snd_pcm_t** rpcm);1166 int snd_emu10k1_fx8010_pcm( emu10k1_t * emu, int device, snd_pcm_t** rpcm);1167 int snd_emu10k1_mixer( emu10k1_t* emu, int pcm_device, int multi_device);1168 int snd_emu10k1_timer( emu10k1_t* emu, int device);1169 int snd_emu10k1_fx8010_new( emu10k1_t *emu, int device, snd_hwdep_t** rhwdep);1176 int enable_ir, 1177 uint subsystem, 1178 struct snd_emu10k1 ** remu); 1179 1180 int snd_emu10k1_pcm(struct snd_emu10k1 * emu, int device, struct snd_pcm ** rpcm); 1181 int snd_emu10k1_pcm_mic(struct snd_emu10k1 * emu, int device, struct snd_pcm ** rpcm); 1182 int snd_emu10k1_pcm_efx(struct snd_emu10k1 * emu, int device, struct snd_pcm ** rpcm); 1183 int snd_p16v_pcm(struct snd_emu10k1 * emu, int device, struct snd_pcm ** rpcm); 1184 int snd_p16v_free(struct snd_emu10k1 * emu); 1185 int snd_p16v_mixer(struct snd_emu10k1 * emu); 1186 int snd_emu10k1_pcm_multi(struct snd_emu10k1 * emu, int device, struct snd_pcm ** rpcm); 1187 int snd_emu10k1_fx8010_pcm(struct snd_emu10k1 * emu, int device, struct snd_pcm ** rpcm); 1188 int snd_emu10k1_mixer(struct snd_emu10k1 * emu, int pcm_device, int multi_device); 1189 int snd_emu10k1_timer(struct snd_emu10k1 * emu, int device); 1190 int snd_emu10k1_fx8010_new(struct snd_emu10k1 *emu, int device, struct snd_hwdep ** rhwdep); 1170 1191 1171 1192 irqreturn_t snd_emu10k1_interrupt(int irq, void *dev_id, struct pt_regs *regs); 1172 1193 1173 /* initialization */ 1174 void snd_emu10k1_voice_init(emu10k1_t * emu, int voice);1175 int snd_emu10k1_init_efx(emu10k1_t*emu);1176 void snd_emu10k1_free_efx(emu10k1_t *emu);1177 int snd_emu10k1_ fx8010_tram_setup(emu10k1_t *emu, u32 size);1194 void snd_emu10k1_voice_init(struct snd_emu10k1 * emu, int voice); 1195 int snd_emu10k1_init_efx(struct snd_emu10k1 *emu); 1196 void snd_emu10k1_free_efx(struct snd_emu10k1 *emu); 1197 int snd_emu10k1_fx8010_tram_setup(struct snd_emu10k1 *emu, u32 size); 1198 int snd_emu10k1_done(struct snd_emu10k1 * emu); 1178 1199 1179 1200 /* I/O functions */ 1180 unsigned int snd_emu10k1_ptr_read(emu10k1_t * emu, unsigned int reg, unsigned int chn); 1181 void snd_emu10k1_ptr_write(emu10k1_t *emu, unsigned int reg, unsigned int chn, unsigned int data); 1182 unsigned int snd_emu10k1_ptr20_read(emu10k1_t * emu, unsigned int reg, unsigned int chn); 1183 void snd_emu10k1_ptr20_write(emu10k1_t *emu, unsigned int reg, unsigned int chn, unsigned int data); 1184 void snd_emu10k1_efx_write(emu10k1_t *emu, unsigned int pc, unsigned int data); 1185 unsigned int snd_emu10k1_efx_read(emu10k1_t *emu, unsigned int pc); 1186 void snd_emu10k1_intr_enable(emu10k1_t *emu, unsigned int intrenb); 1187 void snd_emu10k1_intr_disable(emu10k1_t *emu, unsigned int intrenb); 1188 void snd_emu10k1_voice_intr_enable(emu10k1_t *emu, unsigned int voicenum); 1189 void snd_emu10k1_voice_intr_disable(emu10k1_t *emu, unsigned int voicenum); 1190 void snd_emu10k1_voice_intr_ack(emu10k1_t *emu, unsigned int voicenum); 1191 void snd_emu10k1_voice_half_loop_intr_enable(emu10k1_t *emu, unsigned int voicenum); 1192 void snd_emu10k1_voice_half_loop_intr_disable(emu10k1_t *emu, unsigned int voicenum); 1193 void snd_emu10k1_voice_half_loop_intr_ack(emu10k1_t *emu, unsigned int voicenum); 1194 void snd_emu10k1_voice_set_loop_stop(emu10k1_t *emu, unsigned int voicenum); 1195 void snd_emu10k1_voice_clear_loop_stop(emu10k1_t *emu, unsigned int voicenum); 1196 void snd_emu10k1_wait(emu10k1_t *emu, unsigned int wait); 1197 static inline unsigned int snd_emu10k1_wc(emu10k1_t *emu) { return (inl(emu->port + WC) >> 6) & 0xfffff; } 1198 unsigned short snd_emu10k1_ac97_read(ac97_t *ac97, unsigned short reg); 1199 void snd_emu10k1_ac97_write(ac97_t *ac97, unsigned short reg, unsigned short data); 1201 unsigned int snd_emu10k1_ptr_read(struct snd_emu10k1 * emu, unsigned int reg, unsigned int chn); 1202 void snd_emu10k1_ptr_write(struct snd_emu10k1 *emu, unsigned int reg, unsigned int chn, unsigned int data); 1203 unsigned int snd_emu10k1_ptr20_read(struct snd_emu10k1 * emu, unsigned int reg, unsigned int chn); 1204 void snd_emu10k1_ptr20_write(struct snd_emu10k1 *emu, unsigned int reg, unsigned int chn, unsigned int data); 1205 unsigned int snd_emu10k1_efx_read(struct snd_emu10k1 *emu, unsigned int pc); 1206 void snd_emu10k1_intr_enable(struct snd_emu10k1 *emu, unsigned int intrenb); 1207 void snd_emu10k1_intr_disable(struct snd_emu10k1 *emu, unsigned int intrenb); 1208 void snd_emu10k1_voice_intr_enable(struct snd_emu10k1 *emu, unsigned int voicenum); 1209 void snd_emu10k1_voice_intr_disable(struct snd_emu10k1 *emu, unsigned int voicenum); 1210 void snd_emu10k1_voice_intr_ack(struct snd_emu10k1 *emu, unsigned int voicenum); 1211 void snd_emu10k1_voice_half_loop_intr_enable(struct snd_emu10k1 *emu, unsigned int voicenum); 1212 void snd_emu10k1_voice_half_loop_intr_disable(struct snd_emu10k1 *emu, unsigned int voicenum); 1213 void snd_emu10k1_voice_half_loop_intr_ack(struct snd_emu10k1 *emu, unsigned int voicenum); 1214 void snd_emu10k1_voice_set_loop_stop(struct snd_emu10k1 *emu, unsigned int voicenum); 1215 void snd_emu10k1_voice_clear_loop_stop(struct snd_emu10k1 *emu, unsigned int voicenum); 1216 void snd_emu10k1_wait(struct snd_emu10k1 *emu, unsigned int wait); 1217 static inline unsigned int snd_emu10k1_wc(struct snd_emu10k1 *emu) { return (inl(emu->port + WC) >> 6) & 0xfffff; } 1218 unsigned short snd_emu10k1_ac97_read(struct snd_ac97 *ac97, unsigned short reg); 1219 void snd_emu10k1_ac97_write(struct snd_ac97 *ac97, unsigned short reg, unsigned short data); 1200 1220 unsigned int snd_emu10k1_rate_to_pitch(unsigned int rate); 1201 unsigned char snd_emu10k1_sum_vol_attn(unsigned int value); 1221 1222 #ifdef CONFIG_PM 1223 void snd_emu10k1_suspend_regs(struct snd_emu10k1 *emu); 1224 void snd_emu10k1_resume_init(struct snd_emu10k1 *emu); 1225 void snd_emu10k1_resume_regs(struct snd_emu10k1 *emu); 1226 int snd_emu10k1_efx_alloc_pm_buffer(struct snd_emu10k1 *emu); 1227 void snd_emu10k1_efx_free_pm_buffer(struct snd_emu10k1 *emu); 1228 void snd_emu10k1_efx_suspend(struct snd_emu10k1 *emu); 1229 void snd_emu10k1_efx_resume(struct snd_emu10k1 *emu); 1230 int snd_p16v_alloc_pm_buffer(struct snd_emu10k1 *emu); 1231 void snd_p16v_free_pm_buffer(struct snd_emu10k1 *emu); 1232 void snd_p16v_suspend(struct snd_emu10k1 *emu); 1233 void snd_p16v_resume(struct snd_emu10k1 *emu); 1234 #endif 1202 1235 1203 1236 /* memory allocation */ 1204 s nd_util_memblk_t *snd_emu10k1_alloc_pages(emu10k1_t *emu, snd_pcm_substream_t*substream);1205 int snd_emu10k1_free_pages( emu10k1_t *emu, snd_util_memblk_t*blk);1206 s nd_util_memblk_t *snd_emu10k1_synth_alloc(emu10k1_t*emu, unsigned int size);1207 int snd_emu10k1_synth_free( emu10k1_t *emu, snd_util_memblk_t*blk);1208 int snd_emu10k1_synth_bzero( emu10k1_t *emu, snd_util_memblk_t*blk, int offset, int size);1209 int snd_emu10k1_synth_copy_from_user( emu10k1_t *emu, snd_util_memblk_t *blk, int offset, const char *data, int size);1210 int snd_emu10k1_memblk_map( emu10k1_t *emu, emu10k1_memblk_t*blk);1237 struct snd_util_memblk *snd_emu10k1_alloc_pages(struct snd_emu10k1 *emu, struct snd_pcm_substream *substream); 1238 int snd_emu10k1_free_pages(struct snd_emu10k1 *emu, struct snd_util_memblk *blk); 1239 struct snd_util_memblk *snd_emu10k1_synth_alloc(struct snd_emu10k1 *emu, unsigned int size); 1240 int snd_emu10k1_synth_free(struct snd_emu10k1 *emu, struct snd_util_memblk *blk); 1241 int snd_emu10k1_synth_bzero(struct snd_emu10k1 *emu, struct snd_util_memblk *blk, int offset, int size); 1242 int snd_emu10k1_synth_copy_from_user(struct snd_emu10k1 *emu, struct snd_util_memblk *blk, int offset, const char __user *data, int size); 1243 int snd_emu10k1_memblk_map(struct snd_emu10k1 *emu, struct snd_emu10k1_memblk *blk); 1211 1244 1212 1245 /* voice allocation */ 1213 int snd_emu10k1_voice_alloc( emu10k1_t *emu, emu10k1_voice_type_t type, int pair, emu10k1_voice_t**rvoice);1214 int snd_emu10k1_voice_free( emu10k1_t *emu, emu10k1_voice_t*pvoice);1246 int snd_emu10k1_voice_alloc(struct snd_emu10k1 *emu, int type, int pair, struct snd_emu10k1_voice **rvoice); 1247 int snd_emu10k1_voice_free(struct snd_emu10k1 *emu, struct snd_emu10k1_voice *pvoice); 1215 1248 1216 1249 /* MIDI uart */ 1217 int snd_emu10k1_midi( emu10k1_t* emu);1218 int snd_emu10k1_audigy_midi( emu10k1_t* emu);1250 int snd_emu10k1_midi(struct snd_emu10k1 * emu); 1251 int snd_emu10k1_audigy_midi(struct snd_emu10k1 * emu); 1219 1252 1220 1253 /* proc interface */ 1221 int snd_emu10k1_proc_init( emu10k1_t* emu);1254 int snd_emu10k1_proc_init(struct snd_emu10k1 * emu); 1222 1255 1223 1256 /* fx8010 irq handler */ 1224 int snd_emu10k1_fx8010_register_irq_handler( emu10k1_t*emu,1225 1226 1227 1228 snd_emu10k1_fx8010_irq_t**r_irq);1229 int snd_emu10k1_fx8010_unregister_irq_handler( emu10k1_t*emu,1230 snd_emu10k1_fx8010_irq_t*irq);1257 int snd_emu10k1_fx8010_register_irq_handler(struct snd_emu10k1 *emu, 1258 snd_fx8010_irq_handler_t *handler, 1259 unsigned char gpr_running, 1260 void *private_data, 1261 struct snd_emu10k1_fx8010_irq **r_irq); 1262 int snd_emu10k1_fx8010_unregister_irq_handler(struct snd_emu10k1 *emu, 1263 struct snd_emu10k1_fx8010_irq *irq); 1231 1264 1232 1265 #endif /* __KERNEL__ */ … … 1262 1295 #define FXBUS(x) (0x00 + (x)) /* x = 0x00 - 0x0f */ 1263 1296 #define EXTIN(x) (0x10 + (x)) /* x = 0x00 - 0x0f */ 1264 #define EXTOUT(x) (0x20 + (x))/* x = 0x00 - 0x0f physical outs -> FXWC low 16 bits */1265 #define FXBUS2(x) (0x30 + (x))/* x = 0x00 - 0x0f copies of fx buses for capture -> FXWC high 16 bits */1266 /* NB: 0x31 and 0x32 are shared with Center/LFE on SB live 5.1 */1297 #define EXTOUT(x) (0x20 + (x)) /* x = 0x00 - 0x0f physical outs -> FXWC low 16 bits */ 1298 #define FXBUS2(x) (0x30 + (x)) /* x = 0x00 - 0x0f copies of fx buses for capture -> FXWC high 16 bits */ 1299 /* NB: 0x31 and 0x32 are shared with Center/LFE on SB live 5.1 */ 1267 1300 1268 1301 #define C_00000000 0x40 … … 1300 1333 #define ETRAM_ADDR(x) (TANKMEMADDRREGBASE + 0x80 + (x)) /* x = 0x00 - 0x1f */ 1301 1334 1302 #define A_ITRAM_DATA(x) 1303 #define A_ETRAM_DATA(x) 1304 #define A_ITRAM_ADDR(x) 1305 #define A_ETRAM_ADDR(x) 1306 #define A_ITRAM_CTL(x) 1307 #define A_ETRAM_CTL(x) 1308 1309 #define A_FXBUS(x) (0x00 + (x))/* x = 0x00 - 0x3f FX buses */1310 #define A_EXTIN(x) (0x40 + (x))/* x = 0x00 - 0x0f physical ins */1311 #define A_P16VIN(x) (0x50 + (x))/* x = 0x00 - 0x0f p16v ins (A2 only) "EMU32 inputs" */1312 #define A_EXTOUT(x) (0x60 + (x))/* x = 0x00 - 0x1f physical outs -> A_FXWC1 0x79-7f unknown */1313 #define A_FXBUS2(x) (0x80 + (x))/* x = 0x00 - 0x1f extra outs used for EFX capture -> A_FXWC2 */1314 #define A_EMU32OUTH(x) (0xa0 + (x))/* x = 0x00 - 0x0f "EMU32_OUT_10 - _1F" - ??? */1315 #define A_EMU32OUTL(x) (0xb0 + (x))/* x = 0x00 - 0x0f "EMU32_OUT_1 - _F" - ??? */1335 #define A_ITRAM_DATA(x) (TANKMEMDATAREGBASE + 0x00 + (x)) /* x = 0x00 - 0xbf */ 1336 #define A_ETRAM_DATA(x) (TANKMEMDATAREGBASE + 0xc0 + (x)) /* x = 0x00 - 0x3f */ 1337 #define A_ITRAM_ADDR(x) (TANKMEMADDRREGBASE + 0x00 + (x)) /* x = 0x00 - 0xbf */ 1338 #define A_ETRAM_ADDR(x) (TANKMEMADDRREGBASE + 0xc0 + (x)) /* x = 0x00 - 0x3f */ 1339 #define A_ITRAM_CTL(x) (A_TANKMEMCTLREGBASE + 0x00 + (x)) /* x = 0x00 - 0xbf */ 1340 #define A_ETRAM_CTL(x) (A_TANKMEMCTLREGBASE + 0xc0 + (x)) /* x = 0x00 - 0x3f */ 1341 1342 #define A_FXBUS(x) (0x00 + (x)) /* x = 0x00 - 0x3f FX buses */ 1343 #define A_EXTIN(x) (0x40 + (x)) /* x = 0x00 - 0x0f physical ins */ 1344 #define A_P16VIN(x) (0x50 + (x)) /* x = 0x00 - 0x0f p16v ins (A2 only) "EMU32 inputs" */ 1345 #define A_EXTOUT(x) (0x60 + (x)) /* x = 0x00 - 0x1f physical outs -> A_FXWC1 0x79-7f unknown */ 1346 #define A_FXBUS2(x) (0x80 + (x)) /* x = 0x00 - 0x1f extra outs used for EFX capture -> A_FXWC2 */ 1347 #define A_EMU32OUTH(x) (0xa0 + (x)) /* x = 0x00 - 0x0f "EMU32_OUT_10 - _1F" - ??? */ 1348 #define A_EMU32OUTL(x) (0xb0 + (x)) /* x = 0x00 - 0x0f "EMU32_OUT_1 - _F" - ??? */ 1316 1349 #define A_GPR(x) (A_FXGPREGBASE + (x)) 1317 1350 … … 1337 1370 #define FXBUS_MIDI_REVERB 0x0c 1338 1371 #define FXBUS_MIDI_CHORUS 0x0d 1339 #define FXBUS_PCM_LEFT_SIDE 1340 #define FXBUS_PCM_RIGHT_SIDE 1372 #define FXBUS_PCM_LEFT_SIDE 0x0e 1373 #define FXBUS_PCM_RIGHT_SIDE 0x0f 1341 1374 #define FXBUS_PT_LEFT 0x14 1342 1375 #define FXBUS_PT_RIGHT 0x15 … … 1363 1396 #define EXTOUT_TOSLINK_L 0x02 /* LiveDrive - TOSLink Optical - left */ 1364 1397 #define EXTOUT_TOSLINK_R 0x03 /* LiveDrive - TOSLink Optical - right */ 1365 #define EXTOUT_AC97_CENTER 0x04 1366 #define EXTOUT_AC97_LFE 1398 #define EXTOUT_AC97_CENTER 0x04 /* SB Live 5.1 - center */ 1399 #define EXTOUT_AC97_LFE 0x05 /* SB Live 5.1 - LFE */ 1367 1400 #define EXTOUT_HEADPHONE_L 0x06 /* LiveDrive - Headphone - left */ 1368 1401 #define EXTOUT_HEADPHONE_R 0x07 /* LiveDrive - Headphone - right */ … … 1372 1405 #define EXTOUT_ADC_CAP_R 0x0b /* ADC Capture buffer - right */ 1373 1406 #define EXTOUT_MIC_CAP 0x0c /* MIC Capture buffer */ 1374 #define EXTOUT_AC97_REAR_L 0x0d 1375 #define EXTOUT_AC97_REAR_R 0x0e 1407 #define EXTOUT_AC97_REAR_L 0x0d /* SB Live 5.1 (c) 2003 - Rear Left */ 1408 #define EXTOUT_AC97_REAR_R 0x0e /* SB Live 5.1 (c) 2003 - Rear Right */ 1376 1409 #define EXTOUT_ACENTER 0x11 /* Analog Center */ 1377 1410 #define EXTOUT_ALFE 0x12 /* Analog LFE */ … … 1383 1416 #define A_EXTIN_SPDIF_CD_R 0x03 /* digital CD left */ 1384 1417 #define A_EXTIN_OPT_SPDIF_L 0x04 /* audigy drive Optical SPDIF - left */ 1385 #define A_EXTIN_OPT_SPDIF_R 0x05 /* right */ 1418 #define A_EXTIN_OPT_SPDIF_R 0x05 /* right */ 1386 1419 #define A_EXTIN_LINE2_L 0x08 /* audigy drive line2/mic2 - left */ 1387 1420 #define A_EXTIN_LINE2_R 0x09 /* right */ … … 1404 1437 #define A_EXTOUT_ACENTER 0x0a /* analog center */ 1405 1438 #define A_EXTOUT_ALFE 0x0b /* analog LFE */ 1406 #define A_EXTOUT_ASIDE_L 0x0c/* analog side left - Audigy 2 ZS */1407 #define A_EXTOUT_ASIDE_R 0x0d/* right - Audigy 2 ZS */1439 #define A_EXTOUT_ASIDE_L 0x0c /* analog side left - Audigy 2 ZS */ 1440 #define A_EXTOUT_ASIDE_R 0x0d /* right - Audigy 2 ZS */ 1408 1441 #define A_EXTOUT_AREAR_L 0x0e /* analog rear left */ 1409 1442 #define A_EXTOUT_AREAR_R 0x0f /* right */ … … 1439 1472 #define A_GPR_ACCU 0xd6 /* ACCUM, accumulator */ 1440 1473 #define A_GPR_COND 0xd7 /* CCR, condition register */ 1441 #define A_GPR_NOISE0 0xd8/* noise source */1442 #define A_GPR_NOISE1 0xd9/* noise source */1443 #define A_GPR_IRQ 0xda/* IRQ register */1444 #define A_GPR_DBAC 0xdb/* TRAM Delay Base Address Counter - internal */1445 #define A_GPR_DBACE 0xde/* TRAM Delay Base Address Counter - external */1474 #define A_GPR_NOISE0 0xd8 /* noise source */ 1475 #define A_GPR_NOISE1 0xd9 /* noise source */ 1476 #define A_GPR_IRQ 0xda /* IRQ register */ 1477 #define A_GPR_DBAC 0xdb /* TRAM Delay Base Address Counter - internal */ 1478 #define A_GPR_DBACE 0xde /* TRAM Delay Base Address Counter - external */ 1446 1479 1447 1480 /* definitions for debug register */ … … 1463 1496 #endif 1464 1497 1465 typedef struct{1498 struct snd_emu10k1_fx8010_info { 1466 1499 unsigned int internal_tram_size; /* in samples */ 1467 1500 unsigned int external_tram_size; /* in samples */ … … 1470 1503 char extout_names[32][32]; /* names of external outputs */ 1471 1504 unsigned int gpr_controls; /* count of GPR controls */ 1472 } emu10k1_fx8010_info_t;1505 }; 1473 1506 1474 1507 #define EMU10K1_GPR_TRANSLATION_NONE 0 … … 1478 1511 #define EMU10K1_GPR_TRANSLATION_ONOFF 4 1479 1512 1480 typedef struct{1481 s nd_ctl_elem_id_tid; /* full control ID definition */1513 struct snd_emu10k1_fx8010_control_gpr { 1514 struct snd_ctl_elem_id id; /* full control ID definition */ 1482 1515 unsigned int vcount; /* visible count */ 1483 1516 unsigned int count; /* count of GPR (1..16) */ 1484 unsigned short gpr[32];/* GPR number(s) */1517 unsigned short gpr[32]; /* GPR number(s) */ 1485 1518 unsigned int value[32]; /* initial values */ 1486 1519 unsigned int min; /* minimum range */ 1487 1520 unsigned int max; /* maximum range */ 1488 1521 unsigned int translation; /* translation type (EMU10K1_GPR_TRANSLATION*) */ 1489 } emu10k1_fx8010_control_gpr_t;1490 1491 typedef struct{1522 }; 1523 1524 struct snd_emu10k1_fx8010_code { 1492 1525 char name[128]; 1493 1526 1494 1495 u_int32_t __user *gpr_map;/* initializers */1527 DECLARE_BITMAP(gpr_valid, 0x200); /* bitmask of valid initializers */ 1528 u_int32_t __user *gpr_map; /* initializers */ 1496 1529 1497 1530 unsigned int gpr_add_control_count; /* count of GPR controls to add/replace */ 1498 emu10k1_fx8010_control_gpr_t*gpr_add_controls; /* GPR controls to add/replace */1531 struct snd_emu10k1_fx8010_control_gpr __user *gpr_add_controls; /* GPR controls to add/replace */ 1499 1532 1500 1533 unsigned int gpr_del_control_count; /* count of GPR controls to remove */ 1501 s nd_ctl_elem_id_t*gpr_del_controls; /* IDs of GPR controls to remove */1534 struct snd_ctl_elem_id __user *gpr_del_controls; /* IDs of GPR controls to remove */ 1502 1535 1503 1536 unsigned int gpr_list_control_count; /* count of GPR controls to list */ 1504 1537 unsigned int gpr_list_control_total; /* total count of GPR controls */ 1505 emu10k1_fx8010_control_gpr_t*gpr_list_controls; /* listed GPR controls */1506 1507 1508 1509 1510 1511 1512 u_int32_t __user *code;/* one instruction - 64 bits */1513 } emu10k1_fx8010_code_t;1514 1515 typedef struct{1538 struct snd_emu10k1_fx8010_control_gpr __user *gpr_list_controls; /* listed GPR controls */ 1539 1540 DECLARE_BITMAP(tram_valid, 0x100); /* bitmask of valid initializers */ 1541 u_int32_t __user *tram_data_map; /* data initializers */ 1542 u_int32_t __user *tram_addr_map; /* map initializers */ 1543 1544 DECLARE_BITMAP(code_valid, 1024); /* bitmask of valid instructions */ 1545 u_int32_t __user *code; /* one instruction - 64 bits */ 1546 }; 1547 1548 struct snd_emu10k1_fx8010_tram { 1516 1549 unsigned int address; /* 31.bit == 1 -> external TRAM */ 1517 1550 unsigned int size; /* size in samples (4 bytes) */ 1518 1551 unsigned int *samples; /* pointer to samples (20-bit) */ 1519 1552 /* NULL->clear memory */ 1520 } emu10k1_fx8010_tram_t;1521 1522 typedef struct{1553 }; 1554 1555 struct snd_emu10k1_fx8010_pcm_rec { 1523 1556 unsigned int substream; /* substream number */ 1524 1557 unsigned int res1; /* reserved */ 1525 1558 unsigned int channels; /* 16-bit channels count, zero = remove this substream */ 1526 1559 unsigned int tram_start; /* ring buffer position in TRAM (in samples) */ 1527 1528 unsigned short gpr_size;/* GPR containing size of ringbuffer in samples (host) */1529 unsigned short gpr_ptr;/* GPR containing current pointer in the ring buffer (host = reset, FX8010) */1530 unsigned short gpr_count;/* GPR containing count of samples between two interrupts (host) */1531 unsigned short gpr_tmpcount;/* GPR containing current count of samples to interrupt (host = set, FX8010) */1532 unsigned short gpr_trigger;/* GPR containing trigger (activate) information (host) */1533 unsigned short gpr_running;/* GPR containing info if PCM is running (FX8010) */1560 unsigned int buffer_size; /* count of buffered samples */ 1561 unsigned short gpr_size; /* GPR containing size of ringbuffer in samples (host) */ 1562 unsigned short gpr_ptr; /* GPR containing current pointer in the ring buffer (host = reset, FX8010) */ 1563 unsigned short gpr_count; /* GPR containing count of samples between two interrupts (host) */ 1564 unsigned short gpr_tmpcount; /* GPR containing current count of samples to interrupt (host = set, FX8010) */ 1565 unsigned short gpr_trigger; /* GPR containing trigger (activate) information (host) */ 1566 unsigned short gpr_running; /* GPR containing info if PCM is running (FX8010) */ 1534 1567 unsigned char pad; /* reserved */ 1535 1568 unsigned char etram[32]; /* external TRAM address & data (one per channel) */ 1536 1569 unsigned int res2; /* reserved */ 1537 } emu10k1_fx8010_pcm_t;1538 1539 #define SNDRV_EMU10K1_IOCTL_INFO _IOR ('H', 0x10, emu10k1_fx8010_info_t)1540 #define SNDRV_EMU10K1_IOCTL_CODE_POKE _IOW ('H', 0x11, emu10k1_fx8010_code_t)1541 #define SNDRV_EMU10K1_IOCTL_CODE_PEEK _IOWR('H', 0x12, emu10k1_fx8010_code_t)1570 }; 1571 1572 #define SNDRV_EMU10K1_IOCTL_INFO _IOR ('H', 0x10, struct snd_emu10k1_fx8010_info) 1573 #define SNDRV_EMU10K1_IOCTL_CODE_POKE _IOW ('H', 0x11, struct snd_emu10k1_fx8010_code) 1574 #define SNDRV_EMU10K1_IOCTL_CODE_PEEK _IOWR('H', 0x12, struct snd_emu10k1_fx8010_code) 1542 1575 #define SNDRV_EMU10K1_IOCTL_TRAM_SETUP _IOW ('H', 0x20, int) 1543 #define SNDRV_EMU10K1_IOCTL_TRAM_POKE _IOW ('H', 0x21, emu10k1_fx8010_tram_t)1544 #define SNDRV_EMU10K1_IOCTL_TRAM_PEEK _IOWR('H', 0x22, emu10k1_fx8010_tram_t)1545 #define SNDRV_EMU10K1_IOCTL_PCM_POKE _IOW ('H', 0x30, emu10k1_fx8010_pcm_t)1546 #define SNDRV_EMU10K1_IOCTL_PCM_PEEK _IOWR('H', 0x31, emu10k1_fx8010_pcm_t)1576 #define SNDRV_EMU10K1_IOCTL_TRAM_POKE _IOW ('H', 0x21, struct snd_emu10k1_fx8010_tram) 1577 #define SNDRV_EMU10K1_IOCTL_TRAM_PEEK _IOWR('H', 0x22, struct snd_emu10k1_fx8010_tram) 1578 #define SNDRV_EMU10K1_IOCTL_PCM_POKE _IOW ('H', 0x30, struct snd_emu10k1_fx8010_pcm_rec) 1579 #define SNDRV_EMU10K1_IOCTL_PCM_PEEK _IOWR('H', 0x31, struct snd_emu10k1_fx8010_pcm_rec) 1547 1580 #define SNDRV_EMU10K1_IOCTL_STOP _IO ('H', 0x80) 1548 1581 #define SNDRV_EMU10K1_IOCTL_CONTINUE _IO ('H', 0x81) … … 1551 1584 #define SNDRV_EMU10K1_IOCTL_DBG_READ _IOR ('H', 0x84, int) 1552 1585 1586 /* typedefs for compatibility to user-space */ 1587 typedef struct snd_emu10k1_fx8010_info emu10k1_fx8010_info_t; 1588 typedef struct snd_emu10k1_fx8010_control_gpr emu10k1_fx8010_control_gpr_t; 1589 typedef struct snd_emu10k1_fx8010_code emu10k1_fx8010_code_t; 1590 typedef struct snd_emu10k1_fx8010_tram emu10k1_fx8010_tram_t; 1591 typedef struct snd_emu10k1_fx8010_pcm_rec emu10k1_fx8010_pcm_t; 1592 1553 1593 #endif /* __SOUND_EMU10K1_H */
Note:
See TracChangeset
for help on using the changeset viewer.
