Changeset 305 for GPL/branches/uniaud-2.0/alsa-kernel/pci/cs4281.c
- Timestamp:
- Mar 24, 2008, 2:43:42 AM (17 years ago)
- File:
-
- 1 edited
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GPL/branches/uniaud-2.0/alsa-kernel/pci/cs4281.c (modified) (18 diffs)
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GPL/branches/uniaud-2.0/alsa-kernel/pci/cs4281.c
r135 r305 1 1 /* 2 2 * Driver for Cirrus Logic CS4281 based PCI soundcard 3 * Copyright (c) by Jaroslav Kysela <perex@ suse.cz>,3 * Copyright (c) by Jaroslav Kysela <perex@perex.cz>, 4 4 * 5 5 * … … 20 20 */ 21 21 22 #include <sound/driver.h>23 22 #include <asm/io.h> 24 23 #include <linux/delay.h> … … 27 26 #include <linux/pci.h> 28 27 #include <linux/slab.h> 28 #include <linux/gameport.h> 29 #include <linux/moduleparam.h> 29 30 #include <sound/core.h> 30 31 #include <sound/control.h> … … 32 33 #include <sound/rawmidi.h> 33 34 #include <sound/ac97_codec.h> 35 #include <sound/tlv.h> 34 36 #include <sound/opl3.h> 35 #define SNDRV_GET_ID36 37 #include <sound/initval.h> 37 38 38 #ifndef LINUX_2_2 39 #include <linux/gameport.h> 40 #endif 41 42 MODULE_AUTHOR("Jaroslav Kysela <perex@suse.cz>"); 39 40 MODULE_AUTHOR("Jaroslav Kysela <perex@perex.cz>"); 43 41 MODULE_DESCRIPTION("Cirrus Logic CS4281"); 44 42 MODULE_LICENSE("GPL"); 45 MODULE_CLASSES("{sound}"); 46 MODULE_DEVICES("{{Cirrus Logic,CS4281}}"); 43 MODULE_SUPPORTED_DEVICE("{{Cirrus Logic,CS4281}}"); 47 44 48 45 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */ … … 51 48 static int dual_codec[SNDRV_CARDS]; /* dual codec */ 52 49 53 MODULE_PARM(index, "1-" __MODULE_STRING(SNDRV_CARDS) "i");50 module_param_array(index, int, NULL, 0444); 54 51 MODULE_PARM_DESC(index, "Index value for CS4281 soundcard."); 55 MODULE_PARM_SYNTAX(index, SNDRV_INDEX_DESC); 56 MODULE_PARM(id, "1-" __MODULE_STRING(SNDRV_CARDS) "s"); 52 module_param_array(id, charp, NULL, 0444); 57 53 MODULE_PARM_DESC(id, "ID string for CS4281 soundcard."); 58 MODULE_PARM_SYNTAX(id, SNDRV_ID_DESC); 59 MODULE_PARM(enable, "1-" __MODULE_STRING(SNDRV_CARDS) "i"); 54 module_param_array(enable, bool, NULL, 0444); 60 55 MODULE_PARM_DESC(enable, "Enable CS4281 soundcard."); 61 MODULE_PARM_SYNTAX(enable, SNDRV_ENABLE_DESC); 62 MODULE_PARM(dual_codec, "1-" __MODULE_STRING(SNDRV_CARDS) "i"); 56 module_param_array(dual_codec, bool, NULL, 0444); 63 57 MODULE_PARM_DESC(dual_codec, "Secondary Codec ID (0 = disabled)."); 64 MODULE_PARM_SYNTAX(dual_codec, SNDRV_ENABLED ",allows:{{0,3}}");65 66 /*67 *68 */69 70 #ifndef PCI_VENDOR_ID_CIRRUS71 #define PCI_VENDOR_ID_CIRRUS 0x101372 #endif73 #ifndef PCI_DEVICE_ID_CIRRUS_428174 #define PCI_DEVICE_ID_CIRRUS_4281 0x600575 #endif76 58 77 59 /* … … 105 87 106 88 #define BA0_HIMR 0x000c /* Host Interrupt Mask Register */ 107 /* Use same contants as for BA0_HISR */89 /* Use same contants as for BA0_HISR */ 108 90 109 91 #define BA0_IIER 0x0010 /* ISA Interrupt Enable Register */ … … 216 198 217 199 #define BA0_EPPMC 0x03e4 /* Extended PCI Power Management Control */ 218 #define BA0_EPPMC_FPDN 200 #define BA0_EPPMC_FPDN (1<<14) /* Full Power DowN */ 219 201 220 202 #define BA0_GPIOR 0x03e8 /* GPIO Pin Interface Register */ … … 446 428 */ 447 429 448 typedef struct snd_cs4281 cs4281_t; 449 typedef struct snd_cs4281_dma cs4281_dma_t; 450 451 struct snd_cs4281_dma { 452 snd_pcm_substream_t *substream; 453 unsigned int regDBA; /* offset to DBA register */ 454 unsigned int regDCA; /* offset to DCA register */ 455 unsigned int regDBC; /* offset to DBC register */ 456 unsigned int regDCC; /* offset to DCC register */ 457 unsigned int regDMR; /* offset to DMR register */ 458 unsigned int regDCR; /* offset to DCR register */ 459 unsigned int regHDSR; /* offset to HDSR register */ 460 unsigned int regFCR; /* offset to FCR register */ 461 unsigned int regFSIC; /* offset to FSIC register */ 462 unsigned int valDMR; /* DMA mode */ 463 unsigned int valDCR; /* DMA command */ 464 unsigned int valFCR; /* FIFO control */ 465 unsigned int fifo_offset; /* FIFO offset within BA1 */ 466 unsigned char left_slot; /* FIFO left slot */ 467 unsigned char right_slot; /* FIFO right slot */ 468 int frag; /* period number */ 430 struct cs4281_dma { 431 struct snd_pcm_substream *substream; 432 unsigned int regDBA; /* offset to DBA register */ 433 unsigned int regDCA; /* offset to DCA register */ 434 unsigned int regDBC; /* offset to DBC register */ 435 unsigned int regDCC; /* offset to DCC register */ 436 unsigned int regDMR; /* offset to DMR register */ 437 unsigned int regDCR; /* offset to DCR register */ 438 unsigned int regHDSR; /* offset to HDSR register */ 439 unsigned int regFCR; /* offset to FCR register */ 440 unsigned int regFSIC; /* offset to FSIC register */ 441 unsigned int valDMR; /* DMA mode */ 442 unsigned int valDCR; /* DMA command */ 443 unsigned int valFCR; /* FIFO control */ 444 unsigned int fifo_offset; /* FIFO offset within BA1 */ 445 unsigned char left_slot; /* FIFO left slot */ 446 unsigned char right_slot; /* FIFO right slot */ 447 int frag; /* period number */ 469 448 }; 470 449 471 450 #define SUSPEND_REGISTERS 20 472 451 473 struct snd_cs4281 {474 475 476 unsigned longba0; /* virtual (accessible) address */477 unsigned longba1; /* virtual (accessible) address */478 479 480 481 482 483 ac97_bus_t*ac97_bus;484 ac97_t*ac97;485 ac97_t*ac97_secondary;486 487 488 snd_card_t*card;489 snd_pcm_t*pcm;490 snd_rawmidi_t*rmidi;491 snd_rawmidi_substream_t*midi_input;492 snd_rawmidi_substream_t*midi_output;493 494 cs4281_dma_tdma[4];495 496 497 498 499 500 501 502 503 504 505 506 507 508 struct snd_cs4281_gameport *gameport;452 struct cs4281 { 453 int irq; 454 455 void __iomem *ba0; /* virtual (accessible) address */ 456 void __iomem *ba1; /* virtual (accessible) address */ 457 unsigned long ba0_addr; 458 unsigned long ba1_addr; 459 460 int dual_codec; 461 462 struct snd_ac97_bus *ac97_bus; 463 struct snd_ac97 *ac97; 464 struct snd_ac97 *ac97_secondary; 465 466 struct pci_dev *pci; 467 struct snd_card *card; 468 struct snd_pcm *pcm; 469 struct snd_rawmidi *rmidi; 470 struct snd_rawmidi_substream *midi_input; 471 struct snd_rawmidi_substream *midi_output; 472 473 struct cs4281_dma dma[4]; 474 475 unsigned char src_left_play_slot; 476 unsigned char src_right_play_slot; 477 unsigned char src_left_rec_slot; 478 unsigned char src_right_rec_slot; 479 480 unsigned int spurious_dhtc_irq; 481 unsigned int spurious_dtc_irq; 482 483 spinlock_t reg_lock; 484 unsigned int midcr; 485 unsigned int uartm; 486 487 struct gameport *gameport; 509 488 510 489 #ifdef CONFIG_PM 511 490 u32 suspend_regs[SUSPEND_REGISTERS]; 512 491 #endif 513 492 514 493 }; 515 494 516 static irqreturn_t snd_cs4281_interrupt(int irq, void *dev_id , struct pt_regs *regs);495 static irqreturn_t snd_cs4281_interrupt(int irq, void *dev_id); 517 496 518 497 static struct pci_device_id snd_cs4281_ids[] = { 519 520 498 { 0x1013, 0x6005, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0, }, /* CS4281 */ 499 { 0, } 521 500 }; 522 501 … … 526 505 * constants 527 506 */ 507 528 508 #define CS4281_FIFO_SIZE 32 529 509 … … 532 512 */ 533 513 534 static void snd_cs4281_delay(unsigned int delay) 535 { 536 if (delay > 999) { 537 unsigned long end_time; 538 delay = (delay * HZ) / 1000000; 539 if (delay < 1) 540 delay = 1; 541 end_time = jiffies + delay; 542 do { 543 set_current_state(TASK_UNINTERRUPTIBLE); 544 schedule_timeout(1); 545 } while (time_after_eq(end_time, jiffies)); 546 } else { 547 udelay(delay); 548 } 549 } 550 551 inline static void snd_cs4281_delay_long(void) 552 { 553 set_current_state(TASK_UNINTERRUPTIBLE); 554 schedule_timeout(1); 555 } 556 557 static inline void snd_cs4281_pokeBA0(cs4281_t *chip, unsigned long offset, unsigned int val) 558 { 559 writel(val, chip->ba0 + offset); 560 } 561 562 static inline unsigned int snd_cs4281_peekBA0(cs4281_t *chip, unsigned long offset) 563 { 564 return readl(chip->ba0 + offset); 565 } 566 567 static void snd_cs4281_ac97_write(ac97_t *ac97, 568 unsigned short reg, unsigned short val) 569 { 570 /* 571 * 1. Write ACCAD = Command Address Register = 46Ch for AC97 register address 572 * 2. Write ACCDA = Command Data Register = 470h for data to write to AC97 573 * 3. Write ACCTL = Control Register = 460h for initiating the write 574 * 4. Read ACCTL = 460h, DCV should be reset by now and 460h = 07h 575 * 5. if DCV not cleared, break and return error 576 */ 577 cs4281_t *chip = ac97->private_data; 578 int count; 579 580 /* 581 * Setup the AC97 control registers on the CS461x to send the 582 * appropriate command to the AC97 to perform the read. 583 * ACCAD = Command Address Register = 46Ch 584 * ACCDA = Command Data Register = 470h 585 * ACCTL = Control Register = 460h 586 * set DCV - will clear when process completed 587 * reset CRW - Write command 588 * set VFRM - valid frame enabled 589 * set ESYN - ASYNC generation enabled 590 * set RSTN - ARST# inactive, AC97 codec not reset 591 */ 592 snd_cs4281_pokeBA0(chip, BA0_ACCAD, reg); 593 snd_cs4281_pokeBA0(chip, BA0_ACCDA, val); 594 snd_cs4281_pokeBA0(chip, BA0_ACCTL, BA0_ACCTL_DCV | BA0_ACCTL_VFRM | 595 BA0_ACCTL_ESYN | (ac97->num ? BA0_ACCTL_TC : 0)); 596 for (count = 0; count < 2000; count++) { 597 /* 598 * First, we want to wait for a short time. 514 static inline void snd_cs4281_pokeBA0(struct cs4281 *chip, unsigned long offset, 515 unsigned int val) 516 { 517 writel(val, chip->ba0 + offset); 518 } 519 520 static inline unsigned int snd_cs4281_peekBA0(struct cs4281 *chip, unsigned long offset) 521 { 522 return readl(chip->ba0 + offset); 523 } 524 525 static void snd_cs4281_ac97_write(struct snd_ac97 *ac97, 526 unsigned short reg, unsigned short val) 527 { 528 /* 529 * 1. Write ACCAD = Command Address Register = 46Ch for AC97 register address 530 * 2. Write ACCDA = Command Data Register = 470h for data to write to AC97 531 * 3. Write ACCTL = Control Register = 460h for initiating the write 532 * 4. Read ACCTL = 460h, DCV should be reset by now and 460h = 07h 533 * 5. if DCV not cleared, break and return error 534 */ 535 struct cs4281 *chip = ac97->private_data; 536 int count; 537 538 /* 539 * Setup the AC97 control registers on the CS461x to send the 540 * appropriate command to the AC97 to perform the read. 541 * ACCAD = Command Address Register = 46Ch 542 * ACCDA = Command Data Register = 470h 543 * ACCTL = Control Register = 460h 544 * set DCV - will clear when process completed 545 * reset CRW - Write command 546 * set VFRM - valid frame enabled 547 * set ESYN - ASYNC generation enabled 548 * set RSTN - ARST# inactive, AC97 codec not reset 599 549 */ 600 udelay(10); 601 /* 602 * Now, check to see if the write has completed. 603 * ACCTL = 460h, DCV should be reset by now and 460h = 07h 604 */ 605 if (!(snd_cs4281_peekBA0(chip, BA0_ACCTL) & BA0_ACCTL_DCV)) { 606 return; 607 } 608 } 609 snd_printk(KERN_ERR "AC'97 write problem, reg = 0x%x, val = 0x%x\n", reg, val); 610 } 611 612 static unsigned short snd_cs4281_ac97_read(ac97_t *ac97, 613 unsigned short reg) 614 { 615 cs4281_t *chip = ac97->private_data; 616 int count; 617 unsigned short result; 618 // FIXME: volatile is necessary in the following due to a bug of 619 // some gcc versions 620 volatile int ac97_num = ((volatile ac97_t *)ac97)->num; 621 622 /* 623 * 1. Write ACCAD = Command Address Register = 46Ch for AC97 register address 624 * 2. Write ACCDA = Command Data Register = 470h for data to write to AC97 625 * 3. Write ACCTL = Control Register = 460h for initiating the write 626 * 4. Read ACCTL = 460h, DCV should be reset by now and 460h = 17h 627 * 5. if DCV not cleared, break and return error 628 * 6. Read ACSTS = Status Register = 464h, check VSTS bit 629 */ 630 631 snd_cs4281_peekBA0(chip, ac97_num ? BA0_ACSDA2 : BA0_ACSDA); 632 633 /* 634 * Setup the AC97 control registers on the CS461x to send the 635 * appropriate command to the AC97 to perform the read. 636 * ACCAD = Command Address Register = 46Ch 637 * ACCDA = Command Data Register = 470h 638 * ACCTL = Control Register = 460h 639 * set DCV - will clear when process completed 640 * set CRW - Read command 641 * set VFRM - valid frame enabled 642 * set ESYN - ASYNC generation enabled 643 * set RSTN - ARST# inactive, AC97 codec not reset 644 */ 645 646 snd_cs4281_pokeBA0(chip, BA0_ACCAD, reg); 647 snd_cs4281_pokeBA0(chip, BA0_ACCDA, 0); 648 snd_cs4281_pokeBA0(chip, BA0_ACCTL, BA0_ACCTL_DCV | BA0_ACCTL_CRW | 649 BA0_ACCTL_VFRM | BA0_ACCTL_ESYN | 650 (ac97_num ? BA0_ACCTL_TC : 0)); 651 652 653 /* 654 * Wait for the read to occur. 655 */ 656 for (count = 0; count < 500; count++) { 657 /* 658 * First, we want to wait for a short time. 659 */ 660 udelay(10); 661 /* 662 * Now, check to see if the read has completed. 663 * ACCTL = 460h, DCV should be reset by now and 460h = 17h 664 */ 665 if (!(snd_cs4281_peekBA0(chip, BA0_ACCTL) & BA0_ACCTL_DCV)) 666 goto __ok1; 667 } 668 669 snd_printk(KERN_ERR "AC'97 read problem (ACCTL_DCV), reg = 0x%x\n", reg); 670 result = 0xffff; 671 goto __end; 672 673 __ok1: 674 /* 675 * Wait for the valid status bit to go active. 676 */ 677 for (count = 0; count < 100; count++) { 678 /* 679 * Read the AC97 status register. 680 * ACSTS = Status Register = 464h 681 * VSTS - Valid Status 682 */ 683 if (snd_cs4281_peekBA0(chip, ac97_num ? BA0_ACSTS2 : BA0_ACSTS) & BA0_ACSTS_VSTS) 684 goto __ok2; 685 udelay(10); 686 } 687 688 snd_printk(KERN_ERR "AC'97 read problem (ACSTS_VSTS), reg = 0x%x\n", reg); 689 result = 0xffff; 690 goto __end; 691 692 __ok2: 693 /* 694 * Read the data returned from the AC97 register. 695 * ACSDA = Status Data Register = 474h 696 */ 697 result = snd_cs4281_peekBA0(chip, ac97_num ? BA0_ACSDA2 : BA0_ACSDA); 698 699 __end: 700 return result; 550 snd_cs4281_pokeBA0(chip, BA0_ACCAD, reg); 551 snd_cs4281_pokeBA0(chip, BA0_ACCDA, val); 552 snd_cs4281_pokeBA0(chip, BA0_ACCTL, BA0_ACCTL_DCV | BA0_ACCTL_VFRM | 553 BA0_ACCTL_ESYN | (ac97->num ? BA0_ACCTL_TC : 0)); 554 for (count = 0; count < 2000; count++) { 555 /* 556 * First, we want to wait for a short time. 557 */ 558 udelay(10); 559 /* 560 * Now, check to see if the write has completed. 561 * ACCTL = 460h, DCV should be reset by now and 460h = 07h 562 */ 563 if (!(snd_cs4281_peekBA0(chip, BA0_ACCTL) & BA0_ACCTL_DCV)) { 564 return; 565 } 566 } 567 snd_printk(KERN_ERR "AC'97 write problem, reg = 0x%x, val = 0x%x\n", reg, val); 568 } 569 570 static unsigned short snd_cs4281_ac97_read(struct snd_ac97 *ac97, 571 unsigned short reg) 572 { 573 struct cs4281 *chip = ac97->private_data; 574 int count; 575 unsigned short result; 576 // FIXME: volatile is necessary in the following due to a bug of 577 // some gcc versions 578 volatile int ac97_num = ((volatile struct snd_ac97 *)ac97)->num; 579 580 /* 581 * 1. Write ACCAD = Command Address Register = 46Ch for AC97 register address 582 * 2. Write ACCDA = Command Data Register = 470h for data to write to AC97 583 * 3. Write ACCTL = Control Register = 460h for initiating the write 584 * 4. Read ACCTL = 460h, DCV should be reset by now and 460h = 17h 585 * 5. if DCV not cleared, break and return error 586 * 6. Read ACSTS = Status Register = 464h, check VSTS bit 587 */ 588 589 snd_cs4281_peekBA0(chip, ac97_num ? BA0_ACSDA2 : BA0_ACSDA); 590 591 /* 592 * Setup the AC97 control registers on the CS461x to send the 593 * appropriate command to the AC97 to perform the read. 594 * ACCAD = Command Address Register = 46Ch 595 * ACCDA = Command Data Register = 470h 596 * ACCTL = Control Register = 460h 597 * set DCV - will clear when process completed 598 * set CRW - Read command 599 * set VFRM - valid frame enabled 600 * set ESYN - ASYNC generation enabled 601 * set RSTN - ARST# inactive, AC97 codec not reset 602 */ 603 604 snd_cs4281_pokeBA0(chip, BA0_ACCAD, reg); 605 snd_cs4281_pokeBA0(chip, BA0_ACCDA, 0); 606 snd_cs4281_pokeBA0(chip, BA0_ACCTL, BA0_ACCTL_DCV | BA0_ACCTL_CRW | 607 BA0_ACCTL_VFRM | BA0_ACCTL_ESYN | 608 (ac97_num ? BA0_ACCTL_TC : 0)); 609 610 611 /* 612 * Wait for the read to occur. 613 */ 614 for (count = 0; count < 500; count++) { 615 /* 616 * First, we want to wait for a short time. 617 */ 618 udelay(10); 619 /* 620 * Now, check to see if the read has completed. 621 * ACCTL = 460h, DCV should be reset by now and 460h = 17h 622 */ 623 if (!(snd_cs4281_peekBA0(chip, BA0_ACCTL) & BA0_ACCTL_DCV)) 624 goto __ok1; 625 } 626 627 snd_printk(KERN_ERR "AC'97 read problem (ACCTL_DCV), reg = 0x%x\n", reg); 628 result = 0xffff; 629 goto __end; 630 631 __ok1: 632 /* 633 * Wait for the valid status bit to go active. 634 */ 635 for (count = 0; count < 100; count++) { 636 /* 637 * Read the AC97 status register. 638 * ACSTS = Status Register = 464h 639 * VSTS - Valid Status 640 */ 641 if (snd_cs4281_peekBA0(chip, ac97_num ? BA0_ACSTS2 : BA0_ACSTS) & BA0_ACSTS_VSTS) 642 goto __ok2; 643 udelay(10); 644 } 645 646 snd_printk(KERN_ERR "AC'97 read problem (ACSTS_VSTS), reg = 0x%x\n", reg); 647 result = 0xffff; 648 goto __end; 649 650 __ok2: 651 /* 652 * Read the data returned from the AC97 register. 653 * ACSDA = Status Data Register = 474h 654 */ 655 result = snd_cs4281_peekBA0(chip, ac97_num ? BA0_ACSDA2 : BA0_ACSDA); 656 657 __end: 658 return result; 701 659 } 702 660 … … 705 663 */ 706 664 707 static int snd_cs4281_trigger(s nd_pcm_substream_t*substream, int cmd)708 { 709 cs4281_dma_t *dma = (cs4281_dma_t *)substream->runtime->private_data;710 cs4281_t*chip = snd_pcm_substream_chip(substream);711 712 713 714 715 716 717 718 719 720 721 722 723 724 725 726 727 728 729 730 731 732 733 734 735 if(dma->regFCR != BA0_FCR0)736 737 738 739 740 741 742 743 744 745 746 665 static int snd_cs4281_trigger(struct snd_pcm_substream *substream, int cmd) 666 { 667 struct cs4281_dma *dma = substream->runtime->private_data; 668 struct cs4281 *chip = snd_pcm_substream_chip(substream); 669 670 spin_lock(&chip->reg_lock); 671 switch (cmd) { 672 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 673 dma->valDCR |= BA0_DCR_MSK; 674 dma->valFCR |= BA0_FCR_FEN; 675 break; 676 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 677 dma->valDCR &= ~BA0_DCR_MSK; 678 dma->valFCR &= ~BA0_FCR_FEN; 679 break; 680 case SNDRV_PCM_TRIGGER_START: 681 case SNDRV_PCM_TRIGGER_RESUME: 682 snd_cs4281_pokeBA0(chip, dma->regDMR, dma->valDMR & ~BA0_DMR_DMA); 683 dma->valDMR |= BA0_DMR_DMA; 684 dma->valDCR &= ~BA0_DCR_MSK; 685 dma->valFCR |= BA0_FCR_FEN; 686 break; 687 case SNDRV_PCM_TRIGGER_STOP: 688 case SNDRV_PCM_TRIGGER_SUSPEND: 689 dma->valDMR &= ~(BA0_DMR_DMA|BA0_DMR_POLL); 690 dma->valDCR |= BA0_DCR_MSK; 691 dma->valFCR &= ~BA0_FCR_FEN; 692 /* Leave wave playback FIFO enabled for FM */ 693 if (dma->regFCR != BA0_FCR0) 694 dma->valFCR &= ~BA0_FCR_FEN; 695 break; 696 default: 697 spin_unlock(&chip->reg_lock); 698 return -EINVAL; 699 } 700 snd_cs4281_pokeBA0(chip, dma->regDMR, dma->valDMR); 701 snd_cs4281_pokeBA0(chip, dma->regFCR, dma->valFCR); 702 snd_cs4281_pokeBA0(chip, dma->regDCR, dma->valDCR); 703 spin_unlock(&chip->reg_lock); 704 return 0; 747 705 } 748 706 749 707 static unsigned int snd_cs4281_rate(unsigned int rate, unsigned int *real_rate) 750 708 { 751 unsigned int val = ~0; 752 753 if (real_rate) 754 *real_rate = rate; 755 /* special "hardcoded" rates */ 756 switch (rate) { 757 case 8000: return 5; 758 case 11025: return 4; 759 case 16000: return 3; 760 case 22050: return 2; 761 case 44100: return 1; 762 case 48000: return 0; 763 default: 764 goto __variable; 765 } 766 __variable: 767 val = 1536000 / rate; 768 if (real_rate) 769 *real_rate = 1536000 / val; 770 return val; 771 } 772 773 static void snd_cs4281_mode(cs4281_t *chip, cs4281_dma_t *dma, snd_pcm_runtime_t *runtime, int capture, int src) 774 { 775 int rec_mono; 776 777 dma->valDMR = BA0_DMR_TYPE_SINGLE | BA0_DMR_AUTO | 778 (capture ? BA0_DMR_TR_WRITE : BA0_DMR_TR_READ); 779 if (runtime->channels == 1) 780 dma->valDMR |= BA0_DMR_MONO; 781 if (snd_pcm_format_unsigned(runtime->format) > 0) 782 dma->valDMR |= BA0_DMR_USIGN; 783 if (snd_pcm_format_big_endian(runtime->format) > 0) 784 dma->valDMR |= BA0_DMR_BEND; 785 switch (snd_pcm_format_width(runtime->format)) { 786 case 8: dma->valDMR |= BA0_DMR_SIZE8; 787 if (runtime->channels == 1) 788 dma->valDMR |= BA0_DMR_SWAPC; 789 break; 790 case 32: dma->valDMR |= BA0_DMR_SIZE20; break; 791 } 792 dma->frag = 0; /* for workaround */ 793 dma->valDCR = BA0_DCR_TCIE | BA0_DCR_MSK; 794 if (runtime->buffer_size != runtime->period_size) 795 dma->valDCR |= BA0_DCR_HTCIE; 796 /* Initialize DMA */ 797 snd_cs4281_pokeBA0(chip, dma->regDBA, runtime->dma_addr); 798 snd_cs4281_pokeBA0(chip, dma->regDBC, runtime->buffer_size - 1); 799 rec_mono = (chip->dma[1].valDMR & BA0_DMR_MONO) == BA0_DMR_MONO; 800 snd_cs4281_pokeBA0(chip, BA0_SRCSA, (chip->src_left_play_slot << 0) | 801 (chip->src_right_play_slot << 8) | 802 (chip->src_left_rec_slot << 16) | 803 ((rec_mono ? 31 : chip->src_right_rec_slot) << 24)); 804 if (!src) 805 goto __skip_src; 806 if (!capture) { 807 if (dma->left_slot == chip->src_left_play_slot) { 808 unsigned int val = snd_cs4281_rate(runtime->rate, NULL); 809 snd_assert(dma->right_slot == chip->src_right_play_slot, ); 810 snd_cs4281_pokeBA0(chip, BA0_DACSR, val); 811 } 812 } else { 813 if (dma->left_slot == chip->src_left_rec_slot) { 814 unsigned int val = snd_cs4281_rate(runtime->rate, NULL); 815 snd_assert(dma->right_slot == chip->src_right_rec_slot, ); 816 snd_cs4281_pokeBA0(chip, BA0_ADCSR, val); 817 } 818 } 819 __skip_src: 820 /* Deactivate wave playback FIFO before changing slot assignments */ 821 if(dma->regFCR == BA0_FCR0) 822 snd_cs4281_pokeBA0(chip, dma->regFCR, snd_cs4281_peekBA0(chip, dma->regFCR) & ~BA0_FCR_FEN); 823 /* Initialize FIFO */ 824 dma->valFCR = BA0_FCR_LS(dma->left_slot) | 825 BA0_FCR_RS(capture && (dma->valDMR & BA0_DMR_MONO) ? 31 : dma->right_slot) | 826 BA0_FCR_SZ(CS4281_FIFO_SIZE) | 827 BA0_FCR_OF(dma->fifo_offset); 828 snd_cs4281_pokeBA0(chip, dma->regFCR, dma->valFCR | (capture ? BA0_FCR_PSH : 0)); 829 /* Activate FIFO again for FM playback */ 830 if(dma->regFCR == BA0_FCR0) 831 snd_cs4281_pokeBA0(chip, dma->regFCR, dma->valFCR | BA0_FCR_FEN); 832 /* Clear FIFO Status and Interrupt Control Register */ 833 snd_cs4281_pokeBA0(chip, dma->regFSIC, 0); 834 } 835 836 static int snd_cs4281_hw_params(snd_pcm_substream_t * substream, 837 snd_pcm_hw_params_t * hw_params) 838 { 839 return snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params)); 840 } 841 842 static int snd_cs4281_hw_free(snd_pcm_substream_t * substream) 843 { 844 return snd_pcm_lib_free_pages(substream); 845 } 846 847 static int snd_cs4281_playback_prepare(snd_pcm_substream_t * substream) 848 { 849 snd_pcm_runtime_t *runtime = substream->runtime; 850 cs4281_dma_t *dma = (cs4281_dma_t *)runtime->private_data; 851 cs4281_t *chip = snd_pcm_substream_chip(substream); 852 853 spin_lock_irq(&chip->reg_lock); 854 snd_cs4281_mode(chip, dma, runtime, 0, 1); 855 spin_unlock_irq(&chip->reg_lock); 856 return 0; 857 } 858 859 static int snd_cs4281_capture_prepare(snd_pcm_substream_t * substream) 860 { 861 snd_pcm_runtime_t *runtime = substream->runtime; 862 cs4281_dma_t *dma = (cs4281_dma_t *)runtime->private_data; 863 cs4281_t *chip = snd_pcm_substream_chip(substream); 864 865 spin_lock_irq(&chip->reg_lock); 866 snd_cs4281_mode(chip, dma, runtime, 1, 1); 867 spin_unlock_irq(&chip->reg_lock); 868 return 0; 869 } 870 871 static snd_pcm_uframes_t snd_cs4281_pointer(snd_pcm_substream_t * substream) 872 { 873 snd_pcm_runtime_t *runtime = substream->runtime; 874 cs4281_dma_t *dma = (cs4281_dma_t *)runtime->private_data; 875 cs4281_t *chip = snd_pcm_substream_chip(substream); 876 877 // printk("DCC = 0x%x, buffer_size = 0x%x, jiffies = %li\n", snd_cs4281_peekBA0(chip, dma->regDCC), runtime->buffer_size, jiffies); 878 return runtime->buffer_size - 879 snd_cs4281_peekBA0(chip, dma->regDCC) - 1; 880 } 881 882 static snd_pcm_hardware_t snd_cs4281_playback = 883 { 884 /* info: */ (SNDRV_PCM_INFO_MMAP | 885 SNDRV_PCM_INFO_INTERLEAVED | 886 SNDRV_PCM_INFO_MMAP_VALID | 887 SNDRV_PCM_INFO_PAUSE | 888 SNDRV_PCM_INFO_RESUME | 889 SNDRV_PCM_INFO_SYNC_START), 890 /* formats: */ SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S8 | 891 SNDRV_PCM_FMTBIT_U16_LE | SNDRV_PCM_FMTBIT_S16_LE | 892 SNDRV_PCM_FMTBIT_U16_BE | SNDRV_PCM_FMTBIT_S16_BE | 893 SNDRV_PCM_FMTBIT_U32_LE | SNDRV_PCM_FMTBIT_S32_LE | 894 SNDRV_PCM_FMTBIT_U32_BE | SNDRV_PCM_FMTBIT_S32_BE, 895 /* rates: */ SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000, 896 /* rate_min: */ 4000, 897 /* rate_max: */ 48000, 898 /* channels_min: */ 1, 899 /* channels_max: */ 2, 900 /* buffer_bytes_max: */ (512*1024), 901 /* period_bytes_min: */ 64, 902 /* period_bytes_max: */ (512*1024), 903 /* periods_min: */ 1, 904 /* periods_max: */ 2, 905 /* fifo_size: */ CS4281_FIFO_SIZE, 709 unsigned int val = ~0; 710 711 if (real_rate) 712 *real_rate = rate; 713 /* special "hardcoded" rates */ 714 switch (rate) { 715 case 8000: return 5; 716 case 11025: return 4; 717 case 16000: return 3; 718 case 22050: return 2; 719 case 44100: return 1; 720 case 48000: return 0; 721 default: 722 goto __variable; 723 } 724 __variable: 725 val = 1536000 / rate; 726 if (real_rate) 727 *real_rate = 1536000 / val; 728 return val; 729 } 730 731 static void snd_cs4281_mode(struct cs4281 *chip, struct cs4281_dma *dma, 732 struct snd_pcm_runtime *runtime, 733 int capture, int src) 734 { 735 int rec_mono; 736 737 dma->valDMR = BA0_DMR_TYPE_SINGLE | BA0_DMR_AUTO | 738 (capture ? BA0_DMR_TR_WRITE : BA0_DMR_TR_READ); 739 if (runtime->channels == 1) 740 dma->valDMR |= BA0_DMR_MONO; 741 if (snd_pcm_format_unsigned(runtime->format) > 0) 742 dma->valDMR |= BA0_DMR_USIGN; 743 if (snd_pcm_format_big_endian(runtime->format) > 0) 744 dma->valDMR |= BA0_DMR_BEND; 745 switch (snd_pcm_format_width(runtime->format)) { 746 case 8: dma->valDMR |= BA0_DMR_SIZE8; 747 if (runtime->channels == 1) 748 dma->valDMR |= BA0_DMR_SWAPC; 749 break; 750 case 32: dma->valDMR |= BA0_DMR_SIZE20; break; 751 } 752 dma->frag = 0; /* for workaround */ 753 dma->valDCR = BA0_DCR_TCIE | BA0_DCR_MSK; 754 if (runtime->buffer_size != runtime->period_size) 755 dma->valDCR |= BA0_DCR_HTCIE; 756 /* Initialize DMA */ 757 snd_cs4281_pokeBA0(chip, dma->regDBA, runtime->dma_addr); 758 snd_cs4281_pokeBA0(chip, dma->regDBC, runtime->buffer_size - 1); 759 rec_mono = (chip->dma[1].valDMR & BA0_DMR_MONO) == BA0_DMR_MONO; 760 snd_cs4281_pokeBA0(chip, BA0_SRCSA, (chip->src_left_play_slot << 0) | 761 (chip->src_right_play_slot << 8) | 762 (chip->src_left_rec_slot << 16) | 763 ((rec_mono ? 31 : chip->src_right_rec_slot) << 24)); 764 if (!src) 765 goto __skip_src; 766 if (!capture) { 767 if (dma->left_slot == chip->src_left_play_slot) { 768 unsigned int val = snd_cs4281_rate(runtime->rate, NULL); 769 snd_assert(dma->right_slot == chip->src_right_play_slot, ); 770 snd_cs4281_pokeBA0(chip, BA0_DACSR, val); 771 } 772 } else { 773 if (dma->left_slot == chip->src_left_rec_slot) { 774 unsigned int val = snd_cs4281_rate(runtime->rate, NULL); 775 snd_assert(dma->right_slot == chip->src_right_rec_slot, ); 776 snd_cs4281_pokeBA0(chip, BA0_ADCSR, val); 777 } 778 } 779 __skip_src: 780 /* Deactivate wave playback FIFO before changing slot assignments */ 781 if (dma->regFCR == BA0_FCR0) 782 snd_cs4281_pokeBA0(chip, dma->regFCR, snd_cs4281_peekBA0(chip, dma->regFCR) & ~BA0_FCR_FEN); 783 /* Initialize FIFO */ 784 dma->valFCR = BA0_FCR_LS(dma->left_slot) | 785 BA0_FCR_RS(capture && (dma->valDMR & BA0_DMR_MONO) ? 31 : dma->right_slot) | 786 BA0_FCR_SZ(CS4281_FIFO_SIZE) | 787 BA0_FCR_OF(dma->fifo_offset); 788 snd_cs4281_pokeBA0(chip, dma->regFCR, dma->valFCR | (capture ? BA0_FCR_PSH : 0)); 789 /* Activate FIFO again for FM playback */ 790 if (dma->regFCR == BA0_FCR0) 791 snd_cs4281_pokeBA0(chip, dma->regFCR, dma->valFCR | BA0_FCR_FEN); 792 /* Clear FIFO Status and Interrupt Control Register */ 793 snd_cs4281_pokeBA0(chip, dma->regFSIC, 0); 794 } 795 796 static int snd_cs4281_hw_params(struct snd_pcm_substream *substream, 797 struct snd_pcm_hw_params *hw_params) 798 { 799 return snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params)); 800 } 801 802 static int snd_cs4281_hw_free(struct snd_pcm_substream *substream) 803 { 804 return snd_pcm_lib_free_pages(substream); 805 } 806 807 static int snd_cs4281_playback_prepare(struct snd_pcm_substream *substream) 808 { 809 struct snd_pcm_runtime *runtime = substream->runtime; 810 struct cs4281_dma *dma = runtime->private_data; 811 struct cs4281 *chip = snd_pcm_substream_chip(substream); 812 813 spin_lock_irq(&chip->reg_lock); 814 snd_cs4281_mode(chip, dma, runtime, 0, 1); 815 spin_unlock_irq(&chip->reg_lock); 816 return 0; 817 } 818 819 static int snd_cs4281_capture_prepare(struct snd_pcm_substream *substream) 820 { 821 struct snd_pcm_runtime *runtime = substream->runtime; 822 struct cs4281_dma *dma = runtime->private_data; 823 struct cs4281 *chip = snd_pcm_substream_chip(substream); 824 825 spin_lock_irq(&chip->reg_lock); 826 snd_cs4281_mode(chip, dma, runtime, 1, 1); 827 spin_unlock_irq(&chip->reg_lock); 828 return 0; 829 } 830 831 static snd_pcm_uframes_t snd_cs4281_pointer(struct snd_pcm_substream *substream) 832 { 833 struct snd_pcm_runtime *runtime = substream->runtime; 834 struct cs4281_dma *dma = runtime->private_data; 835 struct cs4281 *chip = snd_pcm_substream_chip(substream); 836 837 // printk("DCC = 0x%x, buffer_size = 0x%x, jiffies = %li\n", snd_cs4281_peekBA0(chip, dma->regDCC), runtime->buffer_size, jiffies); 838 return runtime->buffer_size - 839 snd_cs4281_peekBA0(chip, dma->regDCC) - 1; 840 } 841 842 static struct snd_pcm_hardware snd_cs4281_playback = 843 { 844 .info = SNDRV_PCM_INFO_MMAP | 845 SNDRV_PCM_INFO_INTERLEAVED | 846 SNDRV_PCM_INFO_MMAP_VALID | 847 SNDRV_PCM_INFO_PAUSE | 848 SNDRV_PCM_INFO_RESUME, 849 .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S8 | 850 SNDRV_PCM_FMTBIT_U16_LE | SNDRV_PCM_FMTBIT_S16_LE | 851 SNDRV_PCM_FMTBIT_U16_BE | SNDRV_PCM_FMTBIT_S16_BE | 852 SNDRV_PCM_FMTBIT_U32_LE | SNDRV_PCM_FMTBIT_S32_LE | 853 SNDRV_PCM_FMTBIT_U32_BE | SNDRV_PCM_FMTBIT_S32_BE, 854 .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000, 855 .rate_min = 4000, 856 .rate_max = 48000, 857 .channels_min = 1, 858 .channels_max = 2, 859 .buffer_bytes_max = (512*1024), 860 .period_bytes_min = 64, 861 .period_bytes_max = (512*1024), 862 .periods_min = 1, 863 .periods_max = 2, 864 .fifo_size = CS4281_FIFO_SIZE, 906 865 }; 907 866 908 static snd_pcm_hardware_t snd_cs4281_capture = 909 { 910 /* info: */ (SNDRV_PCM_INFO_MMAP | 911 SNDRV_PCM_INFO_INTERLEAVED | 912 SNDRV_PCM_INFO_MMAP_VALID | 913 SNDRV_PCM_INFO_PAUSE | 914 SNDRV_PCM_INFO_RESUME | 915 SNDRV_PCM_INFO_SYNC_START), 916 /* formats: */ //SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S8 | 917 SNDRV_PCM_FMTBIT_U16_LE | SNDRV_PCM_FMTBIT_S16_LE | 918 SNDRV_PCM_FMTBIT_U16_BE | SNDRV_PCM_FMTBIT_S16_BE | 919 SNDRV_PCM_FMTBIT_U32_LE | SNDRV_PCM_FMTBIT_S32_LE | 920 SNDRV_PCM_FMTBIT_U32_BE | SNDRV_PCM_FMTBIT_S32_BE, 921 /* rates: */ SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000, 922 /* rate_min: */ 4000, 923 /* rate_max: */ 48000, 924 /* channels_min: */ 1, 925 /* channels_max: */ 2, 926 /* buffer_bytes_max: */ (512*1024), 927 /* period_bytes_min: */ 64, 928 /* period_bytes_max: */ (512*1024), 929 /* periods_min: */ 1, 930 /* periods_max: */ 2, 931 /* fifo_size: */ CS4281_FIFO_SIZE, 867 static struct snd_pcm_hardware snd_cs4281_capture = 868 { 869 .info = SNDRV_PCM_INFO_MMAP | 870 SNDRV_PCM_INFO_INTERLEAVED | 871 SNDRV_PCM_INFO_MMAP_VALID | 872 SNDRV_PCM_INFO_PAUSE | 873 SNDRV_PCM_INFO_RESUME, 874 .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S8 | 875 SNDRV_PCM_FMTBIT_U16_LE | SNDRV_PCM_FMTBIT_S16_LE | 876 SNDRV_PCM_FMTBIT_U16_BE | SNDRV_PCM_FMTBIT_S16_BE | 877 SNDRV_PCM_FMTBIT_U32_LE | SNDRV_PCM_FMTBIT_S32_LE | 878 SNDRV_PCM_FMTBIT_U32_BE | SNDRV_PCM_FMTBIT_S32_BE, 879 .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000, 880 .rate_min = 4000, 881 .rate_max = 48000, 882 .channels_min = 1, 883 .channels_max = 2, 884 .buffer_bytes_max = (512*1024), 885 .period_bytes_min = 64, 886 .period_bytes_max = (512*1024), 887 .periods_min = 1, 888 .periods_max = 2, 889 .fifo_size = CS4281_FIFO_SIZE, 932 890 }; 933 891 934 static int snd_cs4281_playback_open(snd_pcm_substream_t * substream) 935 { 936 cs4281_t *chip = snd_pcm_substream_chip(substream); 937 snd_pcm_runtime_t *runtime = substream->runtime; 938 cs4281_dma_t *dma; 939 940 dma = &chip->dma[0]; 941 dma->substream = substream; 942 dma->left_slot = 0; 943 dma->right_slot = 1; 944 runtime->private_data = dma; 945 runtime->hw = snd_cs4281_playback; 946 snd_pcm_set_sync(substream); 947 /* should be detected from the AC'97 layer, but it seems 948 that although CS4297A rev B reports 18-bit ADC resolution, 949 samples are 20-bit */ 950 snd_pcm_hw_constraint_msbits(runtime, 0, 32, 20); 951 return 0; 952 } 953 954 static int snd_cs4281_capture_open(snd_pcm_substream_t * substream) 955 { 956 cs4281_t *chip = snd_pcm_substream_chip(substream); 957 snd_pcm_runtime_t *runtime = substream->runtime; 958 cs4281_dma_t *dma; 959 960 dma = &chip->dma[1]; 961 dma->substream = substream; 962 dma->left_slot = 10; 963 dma->right_slot = 11; 964 runtime->private_data = dma; 965 runtime->hw = snd_cs4281_capture; 966 snd_pcm_set_sync(substream); 967 /* should be detected from the AC'97 layer, but it seems 968 that although CS4297A rev B reports 18-bit ADC resolution, 969 samples are 20-bit */ 970 snd_pcm_hw_constraint_msbits(runtime, 0, 32, 20); 971 return 0; 972 } 973 974 static int snd_cs4281_playback_close(snd_pcm_substream_t * substream) 975 { 976 cs4281_dma_t *dma = (cs4281_dma_t *)substream->runtime->private_data; 977 978 dma->substream = NULL; 979 return 0; 980 } 981 982 static int snd_cs4281_capture_close(snd_pcm_substream_t * substream) 983 { 984 cs4281_dma_t *dma = (cs4281_dma_t *)substream->runtime->private_data; 985 986 dma->substream = NULL; 987 return 0; 988 } 989 990 static snd_pcm_ops_t snd_cs4281_playback_ops = { 991 /* .open = */ snd_cs4281_playback_open, 992 /* .close = */ snd_cs4281_playback_close, 993 /* .ioctl = */ snd_pcm_lib_ioctl, 994 /* .hw_params = */ snd_cs4281_hw_params, 995 /* .hw_free = */ snd_cs4281_hw_free, 996 /* .prepare = */ snd_cs4281_playback_prepare, 997 /* .trigger = */ snd_cs4281_trigger, 998 /* .pointer = */ snd_cs4281_pointer, 999 0,0,0,0 892 static int snd_cs4281_playback_open(struct snd_pcm_substream *substream) 893 { 894 struct cs4281 *chip = snd_pcm_substream_chip(substream); 895 struct snd_pcm_runtime *runtime = substream->runtime; 896 struct cs4281_dma *dma; 897 898 dma = &chip->dma[0]; 899 dma->substream = substream; 900 dma->left_slot = 0; 901 dma->right_slot = 1; 902 runtime->private_data = dma; 903 runtime->hw = snd_cs4281_playback; 904 /* should be detected from the AC'97 layer, but it seems 905 that although CS4297A rev B reports 18-bit ADC resolution, 906 samples are 20-bit */ 907 snd_pcm_hw_constraint_msbits(runtime, 0, 32, 20); 908 return 0; 909 } 910 911 static int snd_cs4281_capture_open(struct snd_pcm_substream *substream) 912 { 913 struct cs4281 *chip = snd_pcm_substream_chip(substream); 914 struct snd_pcm_runtime *runtime = substream->runtime; 915 struct cs4281_dma *dma; 916 917 dma = &chip->dma[1]; 918 dma->substream = substream; 919 dma->left_slot = 10; 920 dma->right_slot = 11; 921 runtime->private_data = dma; 922 runtime->hw = snd_cs4281_capture; 923 /* should be detected from the AC'97 layer, but it seems 924 that although CS4297A rev B reports 18-bit ADC resolution, 925 samples are 20-bit */ 926 snd_pcm_hw_constraint_msbits(runtime, 0, 32, 20); 927 return 0; 928 } 929 930 static int snd_cs4281_playback_close(struct snd_pcm_substream *substream) 931 { 932 struct cs4281_dma *dma = substream->runtime->private_data; 933 934 dma->substream = NULL; 935 return 0; 936 } 937 938 static int snd_cs4281_capture_close(struct snd_pcm_substream *substream) 939 { 940 struct cs4281_dma *dma = substream->runtime->private_data; 941 942 dma->substream = NULL; 943 return 0; 944 } 945 946 static struct snd_pcm_ops snd_cs4281_playback_ops = { 947 .open = snd_cs4281_playback_open, 948 .close = snd_cs4281_playback_close, 949 .ioctl = snd_pcm_lib_ioctl, 950 .hw_params = snd_cs4281_hw_params, 951 .hw_free = snd_cs4281_hw_free, 952 .prepare = snd_cs4281_playback_prepare, 953 .trigger = snd_cs4281_trigger, 954 .pointer = snd_cs4281_pointer, 1000 955 }; 1001 956 1002 static snd_pcm_ops_t snd_cs4281_capture_ops = { 1003 /* .open = */ snd_cs4281_capture_open, 1004 /* .close = */ snd_cs4281_capture_close, 1005 /* .ioctl = */ snd_pcm_lib_ioctl, 1006 /* .hw_params = */ snd_cs4281_hw_params, 1007 /* .hw_free = */ snd_cs4281_hw_free, 1008 /* .prepare = */ snd_cs4281_capture_prepare, 1009 /* .trigger = */ snd_cs4281_trigger, 1010 /* .pointer = */ snd_cs4281_pointer, 1011 0,0,0,0 957 static struct snd_pcm_ops snd_cs4281_capture_ops = { 958 .open = snd_cs4281_capture_open, 959 .close = snd_cs4281_capture_close, 960 .ioctl = snd_pcm_lib_ioctl, 961 .hw_params = snd_cs4281_hw_params, 962 .hw_free = snd_cs4281_hw_free, 963 .prepare = snd_cs4281_capture_prepare, 964 .trigger = snd_cs4281_trigger, 965 .pointer = snd_cs4281_pointer, 1012 966 }; 1013 967 1014 static void snd_cs4281_pcm_free(snd_pcm_t *pcm) 1015 { 1016 cs4281_t *chip = pcm->private_data; 1017 chip->pcm = NULL; 1018 snd_pcm_lib_preallocate_free_for_all(pcm); 1019 } 1020 1021 static int __devinit snd_cs4281_pcm(cs4281_t * chip, int device, snd_pcm_t ** rpcm) 1022 { 1023 snd_pcm_t *pcm; 1024 int err; 1025 1026 if (rpcm) 1027 *rpcm = NULL; 1028 err = snd_pcm_new(chip->card, "CS4281", device, 1, 1, &pcm); 1029 if (err < 0) 1030 return err; 1031 1032 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cs4281_playback_ops); 1033 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_cs4281_capture_ops); 1034 1035 pcm->private_data = chip; 1036 pcm->private_free = snd_cs4281_pcm_free; 1037 pcm->info_flags = 0; 1038 strcpy(pcm->name, "CS4281"); 1039 chip->pcm = pcm; 1040 1041 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV, 1042 snd_dma_pci_data(chip->pci), 64*1024, 512*1024); 1043 1044 if (rpcm) 1045 *rpcm = pcm; 1046 return 0; 968 static int __devinit snd_cs4281_pcm(struct cs4281 * chip, int device, 969 struct snd_pcm ** rpcm) 970 { 971 struct snd_pcm *pcm; 972 int err; 973 974 if (rpcm) 975 *rpcm = NULL; 976 err = snd_pcm_new(chip->card, "CS4281", device, 1, 1, &pcm); 977 if (err < 0) 978 return err; 979 980 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cs4281_playback_ops); 981 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_cs4281_capture_ops); 982 983 pcm->private_data = chip; 984 pcm->info_flags = 0; 985 strcpy(pcm->name, "CS4281"); 986 chip->pcm = pcm; 987 988 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV, 989 snd_dma_pci_data(chip->pci), 64*1024, 512*1024); 990 991 if (rpcm) 992 *rpcm = pcm; 993 return 0; 1047 994 } 1048 995 … … 1050 997 * Mixer section 1051 998 */ 999 1052 1000 #define CS_VOL_MASK 0x1f 1053 1001 1054 static int snd_cs4281_info_volume(snd_kcontrol_t * kcontrol, snd_ctl_elem_info_t * uinfo) 1055 { 1056 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; 1057 uinfo->count = 2; 1058 uinfo->value.integer.min = 0; 1059 uinfo->value.integer.max = CS_VOL_MASK; 1060 return 0; 1061 } 1062 1063 static int snd_cs4281_get_volume(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol) 1064 { 1065 cs4281_t *chip = snd_kcontrol_chip(kcontrol); 1066 int regL = (kcontrol->private_value >> 16) & 0xffff; 1067 int regR = kcontrol->private_value & 0xffff; 1068 int volL, volR; 1069 1070 volL = CS_VOL_MASK - (snd_cs4281_peekBA0(chip, regL) & CS_VOL_MASK); 1071 volR = CS_VOL_MASK - (snd_cs4281_peekBA0(chip, regR) & CS_VOL_MASK); 1072 1073 ucontrol->value.integer.value[0] = volL; 1074 ucontrol->value.integer.value[1] = volR; 1075 return 0; 1076 } 1077 1078 static int snd_cs4281_put_volume(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol) 1079 { 1080 cs4281_t *chip = snd_kcontrol_chip(kcontrol); 1081 int change = 0; 1082 int regL = (kcontrol->private_value >> 16) & 0xffff; 1083 int regR = kcontrol->private_value & 0xffff; 1084 int volL, volR; 1085 1086 volL = CS_VOL_MASK - (snd_cs4281_peekBA0(chip, regL) & CS_VOL_MASK); 1087 volR = CS_VOL_MASK - (snd_cs4281_peekBA0(chip, regR) & CS_VOL_MASK); 1088 1089 if (ucontrol->value.integer.value[0] != volL) { 1090 volL = CS_VOL_MASK - (ucontrol->value.integer.value[0] & CS_VOL_MASK); 1091 snd_cs4281_pokeBA0(chip, regL, volL); 1092 change = 1; 1093 } 1094 if (ucontrol->value.integer.value[0] != volR) { 1095 volR = CS_VOL_MASK - (ucontrol->value.integer.value[1] & CS_VOL_MASK); 1096 snd_cs4281_pokeBA0(chip, regR, volR); 1097 change = 1; 1098 } 1099 return change; 1100 } 1101 1102 static snd_kcontrol_new_t snd_cs4281_fm_vol = 1103 { 1104 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, 1105 .name = "Synth Playback Volume", 1106 .info = snd_cs4281_info_volume, 1107 .get = snd_cs4281_get_volume, 1108 .put = snd_cs4281_put_volume, 1109 .private_value = ((BA0_FMLVC << 16) | BA0_FMRVC) 1002 static int snd_cs4281_info_volume(struct snd_kcontrol *kcontrol, 1003 struct snd_ctl_elem_info *uinfo) 1004 { 1005 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; 1006 uinfo->count = 2; 1007 uinfo->value.integer.min = 0; 1008 uinfo->value.integer.max = CS_VOL_MASK; 1009 return 0; 1010 } 1011 1012 static int snd_cs4281_get_volume(struct snd_kcontrol *kcontrol, 1013 struct snd_ctl_elem_value *ucontrol) 1014 { 1015 struct cs4281 *chip = snd_kcontrol_chip(kcontrol); 1016 int regL = (kcontrol->private_value >> 16) & 0xffff; 1017 int regR = kcontrol->private_value & 0xffff; 1018 int volL, volR; 1019 1020 volL = CS_VOL_MASK - (snd_cs4281_peekBA0(chip, regL) & CS_VOL_MASK); 1021 volR = CS_VOL_MASK - (snd_cs4281_peekBA0(chip, regR) & CS_VOL_MASK); 1022 1023 ucontrol->value.integer.value[0] = volL; 1024 ucontrol->value.integer.value[1] = volR; 1025 return 0; 1026 } 1027 1028 static int snd_cs4281_put_volume(struct snd_kcontrol *kcontrol, 1029 struct snd_ctl_elem_value *ucontrol) 1030 { 1031 struct cs4281 *chip = snd_kcontrol_chip(kcontrol); 1032 int change = 0; 1033 int regL = (kcontrol->private_value >> 16) & 0xffff; 1034 int regR = kcontrol->private_value & 0xffff; 1035 int volL, volR; 1036 1037 volL = CS_VOL_MASK - (snd_cs4281_peekBA0(chip, regL) & CS_VOL_MASK); 1038 volR = CS_VOL_MASK - (snd_cs4281_peekBA0(chip, regR) & CS_VOL_MASK); 1039 1040 if (ucontrol->value.integer.value[0] != volL) { 1041 volL = CS_VOL_MASK - (ucontrol->value.integer.value[0] & CS_VOL_MASK); 1042 snd_cs4281_pokeBA0(chip, regL, volL); 1043 change = 1; 1044 } 1045 if (ucontrol->value.integer.value[1] != volR) { 1046 volR = CS_VOL_MASK - (ucontrol->value.integer.value[1] & CS_VOL_MASK); 1047 snd_cs4281_pokeBA0(chip, regR, volR); 1048 change = 1; 1049 } 1050 return change; 1051 } 1052 1053 static const DECLARE_TLV_DB_SCALE(db_scale_dsp, -4650, 150, 0); 1054 1055 static struct snd_kcontrol_new snd_cs4281_fm_vol = 1056 { 1057 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, 1058 .name = "Synth Playback Volume", 1059 .info = snd_cs4281_info_volume, 1060 .get = snd_cs4281_get_volume, 1061 .put = snd_cs4281_put_volume, 1062 .private_value = ((BA0_FMLVC << 16) | BA0_FMRVC), 1063 .tlv = { .p = db_scale_dsp }, 1110 1064 }; 1111 1065 1112 static snd_kcontrol_new_t snd_cs4281_pcm_vol = 1113 { 1114 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, 1115 .name = "PCM Stream Playback Volume", 1116 .info = snd_cs4281_info_volume, 1117 .get = snd_cs4281_get_volume, 1118 .put = snd_cs4281_put_volume, 1119 .private_value = ((BA0_PPLVC << 16) | BA0_PPRVC) 1066 static struct snd_kcontrol_new snd_cs4281_pcm_vol = 1067 { 1068 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, 1069 .name = "PCM Stream Playback Volume", 1070 .info = snd_cs4281_info_volume, 1071 .get = snd_cs4281_get_volume, 1072 .put = snd_cs4281_put_volume, 1073 .private_value = ((BA0_PPLVC << 16) | BA0_PPRVC), 1074 .tlv = { .p = db_scale_dsp }, 1120 1075 }; 1121 1076 1122 static void snd_cs4281_mixer_free_ac97_bus(ac97_bus_t *bus) 1123 { 1124 cs4281_t *chip = bus->private_data; 1125 chip->ac97_bus = NULL; 1126 } 1127 1128 1129 static void snd_cs4281_mixer_free_ac97(ac97_t *ac97) 1130 { 1131 cs4281_t *chip = ac97->private_data; 1132 if (ac97->num) 1133 chip->ac97_secondary = NULL; 1134 else 1135 chip->ac97 = NULL; 1136 } 1137 1138 static int __devinit snd_cs4281_mixer(cs4281_t * chip) 1139 { 1140 snd_card_t *card = chip->card; 1141 ac97_template_t ac97; 1142 int err; 1143 static ac97_bus_ops_t ops = { 1144 0,0, 1145 snd_cs4281_ac97_write, 1146 snd_cs4281_ac97_read, 1147 0,0 1148 }; 1149 if ((err = snd_ac97_bus(card, 0, &ops, chip, &chip->ac97_bus)) < 0) 1150 return err; 1151 1152 chip->ac97_bus->private_free = snd_cs4281_mixer_free_ac97_bus; 1153 1154 memset(&ac97, 0, sizeof(ac97)); 1155 ac97.private_data = chip; 1156 ac97.private_free = snd_cs4281_mixer_free_ac97; 1157 if ((err = snd_ac97_mixer(chip->ac97_bus, &ac97, &chip->ac97)) < 0) 1158 return err; 1159 if (chip->dual_codec) { 1160 ac97.num = 1; 1161 if ((err = snd_ac97_mixer(chip->ac97_bus, &ac97, &chip->ac97_secondary)) < 0) 1162 return err; 1163 } 1164 if ((err = snd_ctl_add(card, snd_ctl_new1(&snd_cs4281_fm_vol, chip))) < 0) 1165 return err; 1166 if ((err = snd_ctl_add(card, snd_ctl_new1(&snd_cs4281_pcm_vol, chip))) < 0) 1167 return err; 1168 return 0; 1169 } 1077 static void snd_cs4281_mixer_free_ac97_bus(struct snd_ac97_bus *bus) 1078 { 1079 struct cs4281 *chip = bus->private_data; 1080 chip->ac97_bus = NULL; 1081 } 1082 1083 static void snd_cs4281_mixer_free_ac97(struct snd_ac97 *ac97) 1084 { 1085 struct cs4281 *chip = ac97->private_data; 1086 if (ac97->num) 1087 chip->ac97_secondary = NULL; 1088 else 1089 chip->ac97 = NULL; 1090 } 1091 1092 static int __devinit snd_cs4281_mixer(struct cs4281 * chip) 1093 { 1094 struct snd_card *card = chip->card; 1095 struct snd_ac97_template ac97; 1096 int err; 1097 static struct snd_ac97_bus_ops ops = { 1098 .write = snd_cs4281_ac97_write, 1099 .read = snd_cs4281_ac97_read, 1100 }; 1101 1102 if ((err = snd_ac97_bus(card, 0, &ops, chip, &chip->ac97_bus)) < 0) 1103 return err; 1104 chip->ac97_bus->private_free = snd_cs4281_mixer_free_ac97_bus; 1105 1106 memset(&ac97, 0, sizeof(ac97)); 1107 ac97.private_data = chip; 1108 ac97.private_free = snd_cs4281_mixer_free_ac97; 1109 if ((err = snd_ac97_mixer(chip->ac97_bus, &ac97, &chip->ac97)) < 0) 1110 return err; 1111 if (chip->dual_codec) { 1112 ac97.num = 1; 1113 if ((err = snd_ac97_mixer(chip->ac97_bus, &ac97, &chip->ac97_secondary)) < 0) 1114 return err; 1115 } 1116 if ((err = snd_ctl_add(card, snd_ctl_new1(&snd_cs4281_fm_vol, chip))) < 0) 1117 return err; 1118 if ((err = snd_ctl_add(card, snd_ctl_new1(&snd_cs4281_pcm_vol, chip))) < 0) 1119 return err; 1120 return 0; 1121 } 1122 1170 1123 1171 1124 /* … … 1173 1126 */ 1174 1127 1175 static void snd_cs4281_proc_read(snd_info_entry_t *entry, 1176 snd_info_buffer_t * buffer) 1177 { 1178 cs4281_t *chip = entry->private_data; 1179 1180 snd_iprintf(buffer, "Cirrus Logic CS4281\n\n"); 1181 snd_iprintf(buffer, "Spurious half IRQs : %u\n", chip->spurious_dhtc_irq); 1182 snd_iprintf(buffer, "Spurious end IRQs : %u\n", chip->spurious_dtc_irq); 1183 } 1184 1185 static long snd_cs4281_BA0_read(snd_info_entry_t *entry, void *file_private_data, 1186 struct file *file, char __user *buf, 1187 unsigned long count, unsigned long pos) 1188 { 1189 long size; 1190 cs4281_t *chip = entry->private_data; 1191 1192 size = count; 1193 if (pos + size > CS4281_BA0_SIZE) 1194 size = (long)CS4281_BA0_SIZE - pos; 1195 if (size > 0) { 1196 if (copy_to_user_fromio(buf, (char*)chip->ba0 + pos, size)) 1197 return -EFAULT; 1198 } 1199 return size; 1200 } 1201 1202 static long snd_cs4281_BA1_read(snd_info_entry_t *entry, void *file_private_data, 1203 struct file *file, char __user *buf, 1204 unsigned long count, unsigned long pos) 1205 { 1206 long size; 1207 cs4281_t *chip = entry->private_data; 1208 1209 size = count; 1210 if (pos + size > CS4281_BA1_SIZE) 1211 size = (long)CS4281_BA1_SIZE - pos; 1212 if (size > 0) { 1213 if (copy_to_user_fromio(buf, (char*)chip->ba1 + pos, size)) 1214 return -EFAULT; 1215 } 1216 return size; 1128 static void snd_cs4281_proc_read(struct snd_info_entry *entry, 1129 struct snd_info_buffer *buffer) 1130 { 1131 struct cs4281 *chip = entry->private_data; 1132 1133 snd_iprintf(buffer, "Cirrus Logic CS4281\n\n"); 1134 snd_iprintf(buffer, "Spurious half IRQs : %u\n", chip->spurious_dhtc_irq); 1135 snd_iprintf(buffer, "Spurious end IRQs : %u\n", chip->spurious_dtc_irq); 1136 } 1137 1138 static long snd_cs4281_BA0_read(struct snd_info_entry *entry, 1139 void *file_private_data, 1140 struct file *file, char __user *buf, 1141 unsigned long count, unsigned long pos) 1142 { 1143 long size; 1144 struct cs4281 *chip = entry->private_data; 1145 1146 size = count; 1147 if (pos + size > CS4281_BA0_SIZE) 1148 size = (long)CS4281_BA0_SIZE - pos; 1149 if (size > 0) { 1150 if (copy_to_user_fromio(buf, chip->ba0 + pos, size)) 1151 return -EFAULT; 1152 } 1153 return size; 1154 } 1155 1156 static long snd_cs4281_BA1_read(struct snd_info_entry *entry, 1157 void *file_private_data, 1158 struct file *file, char __user *buf, 1159 unsigned long count, unsigned long pos) 1160 { 1161 long size; 1162 struct cs4281 *chip = entry->private_data; 1163 1164 size = count; 1165 if (pos + size > CS4281_BA1_SIZE) 1166 size = (long)CS4281_BA1_SIZE - pos; 1167 if (size > 0) { 1168 if (copy_to_user_fromio(buf, chip->ba1 + pos, size)) 1169 return -EFAULT; 1170 } 1171 return size; 1217 1172 } 1218 1173 … … 1225 1180 }; 1226 1181 1227 static void __devinit snd_cs4281_proc_init( cs4281_t* chip)1228 { 1229 snd_info_entry_t*entry;1230 1231 1232 snd_info_set_text_ops(entry, chip, 1024, snd_cs4281_proc_read);1233 1234 1235 1236 1237 1238 1239 1240 1241 1242 1243 1244 1182 static void __devinit snd_cs4281_proc_init(struct cs4281 * chip) 1183 { 1184 struct snd_info_entry *entry; 1185 1186 if (! snd_card_proc_new(chip->card, "cs4281", &entry)) 1187 snd_info_set_text_ops(entry, chip, snd_cs4281_proc_read); 1188 if (! snd_card_proc_new(chip->card, "cs4281_BA0", &entry)) { 1189 entry->content = SNDRV_INFO_CONTENT_DATA; 1190 entry->private_data = chip; 1191 entry->c.ops = &snd_cs4281_proc_ops_BA0; 1192 entry->size = CS4281_BA0_SIZE; 1193 } 1194 if (! snd_card_proc_new(chip->card, "cs4281_BA1", &entry)) { 1195 entry->content = SNDRV_INFO_CONTENT_DATA; 1196 entry->private_data = chip; 1197 entry->c.ops = &snd_cs4281_proc_ops_BA1; 1198 entry->size = CS4281_BA1_SIZE; 1199 } 1245 1200 } 1246 1201 … … 1249 1204 */ 1250 1205 1251 #ifndef LINUX_2_2 1252 1253 typedef struct snd_cs4281_gameport { 1254 struct gameport info; 1255 cs4281_t *chip; 1256 } cs4281_gameport_t; 1206 #if defined(CONFIG_GAMEPORT) || (defined(MODULE) && defined(CONFIG_GAMEPORT_MODULE)) 1257 1207 1258 1208 static void snd_cs4281_gameport_trigger(struct gameport *gameport) 1259 1209 { 1260 cs4281_gameport_t *gp = (cs4281_gameport_t *)gameport; 1261 cs4281_t *chip; 1262 snd_assert(gp, return); 1263 chip = gp->chip; 1264 snd_cs4281_pokeBA0(chip, BA0_JSPT, 0xff); 1210 struct cs4281 *chip = gameport_get_port_data(gameport); 1211 1212 snd_assert(chip, return); 1213 snd_cs4281_pokeBA0(chip, BA0_JSPT, 0xff); 1265 1214 } 1266 1215 1267 1216 static unsigned char snd_cs4281_gameport_read(struct gameport *gameport) 1268 1217 { 1269 cs4281_gameport_t *gp = (cs4281_gameport_t *)gameport; 1270 cs4281_t *chip; 1271 snd_assert(gp, return 0); 1272 chip = gp->chip; 1273 return snd_cs4281_peekBA0(chip, BA0_JSPT); 1218 struct cs4281 *chip = gameport_get_port_data(gameport); 1219 1220 snd_assert(chip, return 0); 1221 return snd_cs4281_peekBA0(chip, BA0_JSPT); 1274 1222 } 1275 1223 1276 1224 #ifdef COOKED_MODE 1277 static int snd_cs4281_gameport_cooked_read(struct gameport *gameport, int *axes, int *buttons) 1278 { 1279 cs4281_gameport_t *gp = (cs4281_gameport_t *)gameport; 1280 cs4281_t *chip; 1281 unsigned js1, js2, jst; 1282 1283 snd_assert(gp, return 0); 1284 chip = gp->chip; 1285 1286 js1 = snd_cs4281_peekBA0(chip, BA0_JSC1); 1287 js2 = snd_cs4281_peekBA0(chip, BA0_JSC2); 1288 jst = snd_cs4281_peekBA0(chip, BA0_JSPT); 1289 1290 *buttons = (~jst >> 4) & 0x0F; 1291 1292 axes[0] = ((js1 & JSC1_Y1V_MASK) >> JSC1_Y1V_SHIFT) & 0xFFFF; 1293 axes[1] = ((js1 & JSC1_X1V_MASK) >> JSC1_X1V_SHIFT) & 0xFFFF; 1294 axes[2] = ((js2 & JSC2_Y2V_MASK) >> JSC2_Y2V_SHIFT) & 0xFFFF; 1295 axes[3] = ((js2 & JSC2_X2V_MASK) >> JSC2_X2V_SHIFT) & 0xFFFF; 1296 1297 for(jst=0;jst<4;++jst) 1298 if(axes[jst]==0xFFFF) axes[jst] = -1; 1299 return 0; 1300 } 1225 static int snd_cs4281_gameport_cooked_read(struct gameport *gameport, 1226 int *axes, int *buttons) 1227 { 1228 struct cs4281 *chip = gameport_get_port_data(gameport); 1229 unsigned js1, js2, jst; 1230 1231 snd_assert(chip, return 0); 1232 1233 js1 = snd_cs4281_peekBA0(chip, BA0_JSC1); 1234 js2 = snd_cs4281_peekBA0(chip, BA0_JSC2); 1235 jst = snd_cs4281_peekBA0(chip, BA0_JSPT); 1236 1237 *buttons = (~jst >> 4) & 0x0F; 1238 1239 axes[0] = ((js1 & JSC1_Y1V_MASK) >> JSC1_Y1V_SHIFT) & 0xFFFF; 1240 axes[1] = ((js1 & JSC1_X1V_MASK) >> JSC1_X1V_SHIFT) & 0xFFFF; 1241 axes[2] = ((js2 & JSC2_Y2V_MASK) >> JSC2_Y2V_SHIFT) & 0xFFFF; 1242 axes[3] = ((js2 & JSC2_X2V_MASK) >> JSC2_X2V_SHIFT) & 0xFFFF; 1243 1244 for (jst = 0; jst < 4; ++jst) 1245 if (axes[jst] == 0xFFFF) axes[jst] = -1; 1246 return 0; 1247 } 1248 #else 1249 #define snd_cs4281_gameport_cooked_read NULL 1301 1250 #endif 1302 1251 1303 1252 static int snd_cs4281_gameport_open(struct gameport *gameport, int mode) 1304 1253 { 1305 1254 switch (mode) { 1306 1255 #ifdef COOKED_MODE 1307 1308 1256 case GAMEPORT_MODE_COOKED: 1257 return 0; 1309 1258 #endif 1310 case GAMEPORT_MODE_RAW: 1311 return 0; 1312 default: 1313 return -1; 1314 } 1315 return 0; 1316 } 1317 1318 static void __devinit snd_cs4281_gameport(cs4281_t *chip) 1319 { 1320 cs4281_gameport_t *gp; 1321 gp = kmalloc(sizeof(*gp), GFP_KERNEL); 1322 if (! gp) { 1323 snd_printk(KERN_ERR "cannot allocate gameport area\n"); 1324 return; 1325 } 1326 memset(gp, 0, sizeof(*gp)); 1327 gp->info.open = snd_cs4281_gameport_open; 1328 gp->info.read = snd_cs4281_gameport_read; 1329 gp->info.trigger = snd_cs4281_gameport_trigger; 1330 #ifdef COOKED_MODE 1331 gp->info.cooked_read = snd_cs4281_gameport_cooked_read; 1332 #endif 1333 gp->chip = chip; 1334 chip->gameport = gp; 1335 1336 snd_cs4281_pokeBA0(chip, BA0_JSIO, 0xFF); // ? 1337 snd_cs4281_pokeBA0(chip, BA0_JSCTL, JSCTL_SP_MEDIUM_SLOW); 1338 gameport_register_port(&gp->info); 1339 } 1340 1341 #endif /* !LINUX_2_2 */ 1342 1343 1344 static int snd_cs4281_free(cs4281_t *chip) 1345 { 1346 #ifndef LINUX_2_2 1347 if (chip->gameport) { 1348 gameport_unregister_port(&chip->gameport->info); 1349 kfree(chip->gameport); 1350 } 1351 #endif 1352 if (chip->irq >= 0) 1353 synchronize_irq(chip->irq); 1354 1355 /* Mask interrupts */ 1356 snd_cs4281_pokeBA0(chip, BA0_HIMR, 0x7fffffff); 1357 /* Stop the DLL Clock logic. */ 1358 snd_cs4281_pokeBA0(chip, BA0_CLKCR1, 0); 1359 /* Sound System Power Management - Turn Everything OFF */ 1360 snd_cs4281_pokeBA0(chip, BA0_SSPM, 0); 1361 /* PCI interface - D3 state */ 1362 pci_set_power_state(chip->pci, 3); 1363 1364 if (chip->irq >= 0) 1365 free_irq(chip->irq, (void *)chip); 1366 if (chip->ba0) 1367 iounmap((void *) chip->ba0); 1368 if (chip->ba1) 1369 iounmap((void *) chip->ba1); 1370 pci_release_regions(chip->pci); 1371 kfree(chip); 1372 return 0; 1373 } 1374 1375 static int snd_cs4281_dev_free(snd_device_t *device) 1376 { 1377 cs4281_t *chip = device->device_data; 1378 return snd_cs4281_free(chip); 1379 } 1380 1381 static int snd_cs4281_chip_init(cs4281_t *chip); /* defined below */ 1382 #ifdef CONFIG_PM 1383 static int cs4281_suspend(snd_card_t *card, unsigned int state); 1384 static int cs4281_resume(snd_card_t *card, unsigned int state); 1385 #endif 1386 1387 static int __devinit snd_cs4281_create(snd_card_t * card, 1388 struct pci_dev *pci, 1389 cs4281_t ** rchip, 1390 int dual_codec) 1391 { 1392 cs4281_t *chip; 1393 unsigned int tmp; 1394 int err; 1395 #ifdef TARGET_OS2 1396 static snd_device_ops_t ops = { 1397 snd_cs4281_dev_free,0,0,0 1398 }; 1259 case GAMEPORT_MODE_RAW: 1260 return 0; 1261 default: 1262 return -1; 1263 } 1264 return 0; 1265 } 1266 1267 static int __devinit snd_cs4281_create_gameport(struct cs4281 *chip) 1268 { 1269 struct gameport *gp; 1270 1271 chip->gameport = gp = gameport_allocate_port(); 1272 if (!gp) { 1273 printk(KERN_ERR "cs4281: cannot allocate memory for gameport\n"); 1274 return -ENOMEM; 1275 } 1276 1277 gameport_set_name(gp, "CS4281 Gameport"); 1278 gameport_set_phys(gp, "pci%s/gameport0", pci_name(chip->pci)); 1279 gameport_set_dev_parent(gp, &chip->pci->dev); 1280 gp->open = snd_cs4281_gameport_open; 1281 gp->read = snd_cs4281_gameport_read; 1282 gp->trigger = snd_cs4281_gameport_trigger; 1283 gp->cooked_read = snd_cs4281_gameport_cooked_read; 1284 gameport_set_port_data(gp, chip); 1285 1286 snd_cs4281_pokeBA0(chip, BA0_JSIO, 0xFF); // ? 1287 snd_cs4281_pokeBA0(chip, BA0_JSCTL, JSCTL_SP_MEDIUM_SLOW); 1288 1289 gameport_register_port(gp); 1290 1291 return 0; 1292 } 1293 1294 static void snd_cs4281_free_gameport(struct cs4281 *chip) 1295 { 1296 if (chip->gameport) { 1297 gameport_unregister_port(chip->gameport); 1298 chip->gameport = NULL; 1299 } 1300 } 1399 1301 #else 1400 static snd_device_ops_t ops = { 1401 dev_free: snd_cs4281_dev_free, 1402 }; 1403 #endif 1404 1405 *rchip = NULL; 1406 if ((err = pci_enable_device(pci)) < 0) 1407 return err; 1408 chip = kcalloc(1, sizeof(*chip), GFP_KERNEL); 1409 if (chip == NULL) 1410 return -ENOMEM; 1411 spin_lock_init(&chip->reg_lock); 1412 chip->card = card; 1413 chip->pci = pci; 1414 chip->irq = -1; 1415 pci_set_master(pci); 1416 if (dual_codec < 0 || dual_codec > 3) { 1417 snd_printk(KERN_ERR "invalid snd_dual_codec option %d\n", dual_codec); 1418 dual_codec = 0; 1419 } 1420 chip->dual_codec = dual_codec; 1421 1422 if ((err = pci_request_regions(pci, "CS4281")) < 0) { 1423 kfree(chip); 1424 return err; 1425 } 1426 chip->ba0_addr = pci_resource_start(pci, 0); 1427 chip->ba1_addr = pci_resource_start(pci, 1); 1428 chip->ba0 = (unsigned long) ioremap_nocache(chip->ba0_addr, pci_resource_len(pci, 0)); 1429 chip->ba1 = (unsigned long) ioremap_nocache(chip->ba1_addr, pci_resource_len(pci, 1)); 1430 if (!chip->ba0 || !chip->ba1) { 1431 snd_cs4281_free(chip); 1432 return -ENOMEM; 1433 } 1434 1435 if (request_irq(pci->irq, snd_cs4281_interrupt, SA_INTERRUPT|SA_SHIRQ, "CS4281", (void *)chip)) { 1436 snd_printk(KERN_ERR "unable to grab IRQ %d\n", pci->irq); 1437 snd_cs4281_free(chip); 1438 return -ENOMEM; 1439 } 1440 chip->irq = pci->irq; 1441 1442 tmp = snd_cs4281_chip_init(chip); 1443 if(tmp) { 1444 snd_cs4281_free(chip); 1445 return tmp; 1446 } 1447 1448 snd_cs4281_proc_init(chip); 1449 1450 snd_card_set_pm_callback(card, cs4281_suspend, cs4281_resume, chip); 1451 1452 if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) < 0) { 1453 snd_cs4281_free(chip); 1454 return err; 1455 } 1456 1457 *rchip = chip; 1458 return 0; 1459 } 1460 1461 static int snd_cs4281_chip_init(cs4281_t *chip) 1462 { 1463 unsigned int tmp; 1464 unsigned long end_time; 1465 int retry_count = 2; 1466 1467 /* Having EPPMC.FPDN=1 prevent proper chip initialisation */ 1468 tmp = snd_cs4281_peekBA0(chip, BA0_EPPMC); 1469 if (tmp & BA0_EPPMC_FPDN) 1470 snd_cs4281_pokeBA0(chip, BA0_EPPMC, tmp & ~BA0_EPPMC_FPDN); 1471 __retry: 1472 tmp = snd_cs4281_peekBA0(chip, BA0_CFLR); 1473 if (tmp != BA0_CFLR_DEFAULT) { 1474 snd_cs4281_pokeBA0(chip, BA0_CFLR, BA0_CFLR_DEFAULT); 1475 tmp = snd_cs4281_peekBA0(chip, BA0_CFLR); 1476 if (tmp != BA0_CFLR_DEFAULT) { 1477 snd_printk(KERN_ERR "CFLR setup failed (0x%x)\n", tmp); 1478 return -EIO; 1479 } 1480 } 1481 1482 /* Set the 'Configuration Write Protect' register 1483 * to 4281h. Allows vendor-defined configuration 1484 * space between 0e4h and 0ffh to be written. */ 1485 snd_cs4281_pokeBA0(chip, BA0_CWPR, 0x4281); 1486 1487 if ((tmp = snd_cs4281_peekBA0(chip, BA0_SERC1)) != (BA0_SERC1_SO1EN | BA0_SERC1_AC97)) { 1488 snd_printk(KERN_ERR "SERC1 AC'97 check failed (0x%x)\n", tmp); 1489 return -EIO; 1490 } 1491 if ((tmp = snd_cs4281_peekBA0(chip, BA0_SERC2)) != (BA0_SERC2_SI1EN | BA0_SERC2_AC97)) { 1492 snd_printk(KERN_ERR "SERC2 AC'97 check failed (0x%x)\n", tmp); 1493 return -EIO; 1494 } 1495 1496 /* Sound System Power Management */ 1497 snd_cs4281_pokeBA0(chip, BA0_SSPM, BA0_SSPM_MIXEN | BA0_SSPM_CSRCEN | 1498 BA0_SSPM_PSRCEN | BA0_SSPM_JSEN | 1499 BA0_SSPM_ACLEN | BA0_SSPM_FMEN); 1500 1501 /* Serial Port Power Management */ 1502 /* Blast the clock control register to zero so that the 1503 * PLL starts out in a known state, and blast the master serial 1504 * port control register to zero so that the serial ports also 1505 * start out in a known state. */ 1506 snd_cs4281_pokeBA0(chip, BA0_CLKCR1, 0); 1507 snd_cs4281_pokeBA0(chip, BA0_SERMC, 0); 1508 1509 /* Make ESYN go to zero to turn off 1510 * the Sync pulse on the AC97 link. */ 1511 snd_cs4281_pokeBA0(chip, BA0_ACCTL, 0); 1512 udelay(50); 1513 1514 /* Drive the ARST# pin low for a minimum of 1uS (as defined in the AC97 1515 * spec) and then drive it high. This is done for non AC97 modes since 1516 * there might be logic external to the CS4281 that uses the ARST# line 1517 * for a reset. */ 1518 snd_cs4281_pokeBA0(chip, BA0_SPMC, 0); 1519 udelay(50); 1520 snd_cs4281_pokeBA0(chip, BA0_SPMC, BA0_SPMC_RSTN); 1521 snd_cs4281_delay(50000); 1522 1523 if (chip->dual_codec) 1524 snd_cs4281_pokeBA0(chip, BA0_SPMC, BA0_SPMC_RSTN | BA0_SPMC_ASDI2E); 1525 1526 /* 1527 * Set the serial port timing configuration. 1528 */ 1529 snd_cs4281_pokeBA0(chip, BA0_SERMC, 1530 (chip->dual_codec ? BA0_SERMC_TCID(chip->dual_codec) : BA0_SERMC_TCID(1)) | 1531 BA0_SERMC_PTC_AC97 | BA0_SERMC_MSPE); 1532 1533 /* 1534 * Start the DLL Clock logic. 1535 */ 1536 snd_cs4281_pokeBA0(chip, BA0_CLKCR1, BA0_CLKCR1_DLLP); 1537 snd_cs4281_delay(50000); 1538 snd_cs4281_pokeBA0(chip, BA0_CLKCR1, BA0_CLKCR1_SWCE | BA0_CLKCR1_DLLP); 1539 1540 /* 1541 * Wait for the DLL ready signal from the clock logic. 1542 */ 1543 end_time = jiffies + HZ; 1544 do { 1545 /* 1546 * Read the AC97 status register to see if we've seen a CODEC 1547 * signal from the AC97 codec. 1548 */ 1549 if (snd_cs4281_peekBA0(chip, BA0_CLKCR1) & BA0_CLKCR1_DLLRDY) 1550 goto __ok0; 1551 schedule_timeout_uninterruptible(1); 1552 } while (time_after_eq(end_time, jiffies)); 1553 1554 snd_printk(KERN_ERR "DLLRDY not seen\n"); 1555 return -EIO; 1556 1557 __ok0: 1558 1559 /* 1560 * The first thing we do here is to enable sync generation. As soon 1561 * as we start receiving bit clock, we'll start producing the SYNC 1562 * signal. 1563 */ 1564 snd_cs4281_pokeBA0(chip, BA0_ACCTL, BA0_ACCTL_ESYN); 1565 1566 /* 1567 * Wait for the codec ready signal from the AC97 codec. 1568 */ 1569 end_time = jiffies + HZ; 1570 do { 1571 /* 1572 * Read the AC97 status register to see if we've seen a CODEC 1573 * signal from the AC97 codec. 1574 */ 1575 if (snd_cs4281_peekBA0(chip, BA0_ACSTS) & BA0_ACSTS_CRDY) 1576 goto __ok1; 1577 schedule_timeout_uninterruptible(1); 1578 } while (time_after_eq(end_time, jiffies)); 1579 1580 snd_printk(KERN_ERR "never read codec ready from AC'97 (0x%x)\n", snd_cs4281_peekBA0(chip, BA0_ACSTS)); 1581 return -EIO; 1582 1583 __ok1: 1584 if (chip->dual_codec) { 1585 end_time = jiffies + HZ; 1586 do { 1587 if (snd_cs4281_peekBA0(chip, BA0_ACSTS2) & BA0_ACSTS_CRDY) 1588 goto __codec2_ok; 1589 schedule_timeout_uninterruptible(1); 1590 } while (time_after_eq(end_time, jiffies)); 1591 snd_printk(KERN_INFO "secondary codec doesn't respond. disable it...\n"); 1592 chip->dual_codec = 0; 1593 __codec2_ok: ; 1594 } 1595 1596 /* 1597 * Assert the valid frame signal so that we can start sending commands 1598 * to the AC97 codec. 1599 */ 1600 1601 snd_cs4281_pokeBA0(chip, BA0_ACCTL, BA0_ACCTL_VFRM | BA0_ACCTL_ESYN); 1602 1603 /* 1604 * Wait until we've sampled input slots 3 and 4 as valid, meaning that 1605 * the codec is pumping ADC data across the AC-link. 1606 */ 1607 end_time = jiffies + HZ; 1608 do { 1609 /* 1610 * Read the input slot valid register and see if input slots 3 1611 * 4 are valid yet. 1612 */ 1613 if ((snd_cs4281_peekBA0(chip, BA0_ACISV) & (BA0_ACISV_SLV(3) | BA0_ACISV_SLV(4))) == (BA0_ACISV_SLV(3) | BA0_ACISV_SLV(4))) 1614 goto __ok2; 1615 schedule_timeout_uninterruptible(1); 1616 } while (time_after_eq(end_time, jiffies)); 1617 1618 if (--retry_count > 0) 1619 goto __retry; 1620 snd_printk(KERN_ERR "never read ISV3 and ISV4 from AC'97\n"); 1621 return -EIO; 1622 1623 __ok2: 1624 1625 /* 1626 * Now, assert valid frame and the slot 3 and 4 valid bits. This will 1627 * commense the transfer of digital audio data to the AC97 codec. 1628 */ 1629 snd_cs4281_pokeBA0(chip, BA0_ACOSV, BA0_ACOSV_SLV(3) | BA0_ACOSV_SLV(4)); 1630 1631 /* 1632 * Initialize DMA structures 1633 */ 1634 for (tmp = 0; tmp < 4; tmp++) { 1635 cs4281_dma_t *dma = &chip->dma[tmp]; 1636 dma->regDBA = BA0_DBA0 + (tmp * 0x10); 1637 dma->regDCA = BA0_DCA0 + (tmp * 0x10); 1638 dma->regDBC = BA0_DBC0 + (tmp * 0x10); 1639 dma->regDCC = BA0_DCC0 + (tmp * 0x10); 1640 dma->regDMR = BA0_DMR0 + (tmp * 8); 1641 dma->regDCR = BA0_DCR0 + (tmp * 8); 1642 dma->regHDSR = BA0_HDSR0 + (tmp * 4); 1643 dma->regFCR = BA0_FCR0 + (tmp * 4); 1644 dma->regFSIC = BA0_FSIC0 + (tmp * 4); 1645 dma->fifo_offset = tmp * CS4281_FIFO_SIZE; 1646 1647 snd_cs4281_pokeBA0(chip, dma->regFCR, 1648 BA0_FCR_LS(31) | 1649 BA0_FCR_RS(31) | 1650 BA0_FCR_SZ(CS4281_FIFO_SIZE) | 1651 BA0_FCR_OF(dma->fifo_offset)); 1652 } 1653 1654 chip->src_left_play_slot = 0; /* AC'97 left PCM playback (3) */ 1655 chip->src_right_play_slot = 1; /* AC'97 right PCM playback (4) */ 1656 chip->src_left_rec_slot = 10; /* AC'97 left PCM record (3) */ 1657 chip->src_right_rec_slot = 11; /* AC'97 right PCM record (4) */ 1658 1659 /* Activate wave playback FIFO for FM playback */ 1660 chip->dma[0].valFCR = BA0_FCR_FEN | BA0_FCR_LS(0) | 1661 BA0_FCR_RS(1) | 1662 BA0_FCR_SZ(CS4281_FIFO_SIZE) | 1663 BA0_FCR_OF(chip->dma[0].fifo_offset); 1664 snd_cs4281_pokeBA0(chip, chip->dma[0].regFCR, chip->dma[0].valFCR); 1665 snd_cs4281_pokeBA0(chip, BA0_SRCSA, (chip->src_left_play_slot << 0) | 1666 (chip->src_right_play_slot << 8) | 1667 (chip->src_left_rec_slot << 16) | 1668 (chip->src_right_rec_slot << 24)); 1669 1670 /* Initialize digital volume */ 1671 snd_cs4281_pokeBA0(chip, BA0_PPLVC, 0); 1672 snd_cs4281_pokeBA0(chip, BA0_PPRVC, 0); 1673 1674 /* Enable IRQs */ 1675 snd_cs4281_pokeBA0(chip, BA0_HICR, BA0_HICR_EOI); 1676 /* Unmask interrupts */ 1677 snd_cs4281_pokeBA0(chip, BA0_HIMR, 0x7fffffff & ~( 1678 BA0_HISR_MIDI | 1679 BA0_HISR_DMAI | 1680 BA0_HISR_DMA(0) | 1681 BA0_HISR_DMA(1) | 1682 BA0_HISR_DMA(2) | 1683 BA0_HISR_DMA(3))); 1684 synchronize_irq(chip->irq); 1685 1686 return 0; 1302 static inline int snd_cs4281_create_gameport(struct cs4281 *chip) { return -ENOSYS; } 1303 static inline void snd_cs4281_free_gameport(struct cs4281 *chip) { } 1304 #endif /* CONFIG_GAMEPORT || (MODULE && CONFIG_GAMEPORT_MODULE) */ 1305 1306 static int snd_cs4281_free(struct cs4281 *chip) 1307 { 1308 snd_cs4281_free_gameport(chip); 1309 1310 if (chip->irq >= 0) 1311 synchronize_irq(chip->irq); 1312 1313 /* Mask interrupts */ 1314 snd_cs4281_pokeBA0(chip, BA0_HIMR, 0x7fffffff); 1315 /* Stop the DLL Clock logic. */ 1316 snd_cs4281_pokeBA0(chip, BA0_CLKCR1, 0); 1317 /* Sound System Power Management - Turn Everything OFF */ 1318 snd_cs4281_pokeBA0(chip, BA0_SSPM, 0); 1319 /* PCI interface - D3 state */ 1320 pci_set_power_state(chip->pci, 3); 1321 1322 if (chip->irq >= 0) 1323 free_irq(chip->irq, chip); 1324 if (chip->ba0) 1325 iounmap(chip->ba0); 1326 if (chip->ba1) 1327 iounmap(chip->ba1); 1328 pci_release_regions(chip->pci); 1329 pci_disable_device(chip->pci); 1330 1331 kfree(chip); 1332 return 0; 1333 } 1334 1335 static int snd_cs4281_dev_free(struct snd_device *device) 1336 { 1337 struct cs4281 *chip = device->device_data; 1338 return snd_cs4281_free(chip); 1339 } 1340 1341 static int snd_cs4281_chip_init(struct cs4281 *chip); /* defined below */ 1342 1343 static int __devinit snd_cs4281_create(struct snd_card *card, 1344 struct pci_dev *pci, 1345 struct cs4281 ** rchip, 1346 int dual_codec) 1347 { 1348 struct cs4281 *chip; 1349 unsigned int tmp; 1350 int err; 1351 static struct snd_device_ops ops = { 1352 .dev_free = snd_cs4281_dev_free, 1353 }; 1354 1355 *rchip = NULL; 1356 if ((err = pci_enable_device(pci)) < 0) 1357 return err; 1358 chip = kzalloc(sizeof(*chip), GFP_KERNEL); 1359 if (chip == NULL) { 1360 pci_disable_device(pci); 1361 return -ENOMEM; 1362 } 1363 spin_lock_init(&chip->reg_lock); 1364 chip->card = card; 1365 chip->pci = pci; 1366 chip->irq = -1; 1367 pci_set_master(pci); 1368 if (dual_codec < 0 || dual_codec > 3) { 1369 snd_printk(KERN_ERR "invalid dual_codec option %d\n", dual_codec); 1370 dual_codec = 0; 1371 } 1372 chip->dual_codec = dual_codec; 1373 1374 if ((err = pci_request_regions(pci, "CS4281")) < 0) { 1375 kfree(chip); 1376 pci_disable_device(pci); 1377 return err; 1378 } 1379 chip->ba0_addr = pci_resource_start(pci, 0); 1380 chip->ba1_addr = pci_resource_start(pci, 1); 1381 1382 chip->ba0 = ioremap_nocache(chip->ba0_addr, pci_resource_len(pci, 0)); 1383 chip->ba1 = ioremap_nocache(chip->ba1_addr, pci_resource_len(pci, 1)); 1384 if (!chip->ba0 || !chip->ba1) { 1385 snd_cs4281_free(chip); 1386 return -ENOMEM; 1387 } 1388 1389 if (request_irq(pci->irq, snd_cs4281_interrupt, IRQF_SHARED, 1390 "CS4281", chip)) { 1391 snd_printk(KERN_ERR "unable to grab IRQ %d\n", pci->irq); 1392 snd_cs4281_free(chip); 1393 return -ENOMEM; 1394 } 1395 chip->irq = pci->irq; 1396 1397 tmp = snd_cs4281_chip_init(chip); 1398 if (tmp) { 1399 snd_cs4281_free(chip); 1400 return tmp; 1401 } 1402 1403 if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) < 0) { 1404 snd_cs4281_free(chip); 1405 return err; 1406 } 1407 1408 snd_cs4281_proc_init(chip); 1409 1410 snd_card_set_dev(card, &pci->dev); 1411 1412 *rchip = chip; 1413 return 0; 1414 } 1415 1416 static int snd_cs4281_chip_init(struct cs4281 *chip) 1417 { 1418 unsigned int tmp; 1419 unsigned long end_time; 1420 int retry_count = 2; 1421 1422 /* Having EPPMC.FPDN=1 prevent proper chip initialisation */ 1423 tmp = snd_cs4281_peekBA0(chip, BA0_EPPMC); 1424 if (tmp & BA0_EPPMC_FPDN) 1425 snd_cs4281_pokeBA0(chip, BA0_EPPMC, tmp & ~BA0_EPPMC_FPDN); 1426 1427 __retry: 1428 tmp = snd_cs4281_peekBA0(chip, BA0_CFLR); 1429 if (tmp != BA0_CFLR_DEFAULT) { 1430 snd_cs4281_pokeBA0(chip, BA0_CFLR, BA0_CFLR_DEFAULT); 1431 tmp = snd_cs4281_peekBA0(chip, BA0_CFLR); 1432 if (tmp != BA0_CFLR_DEFAULT) { 1433 snd_printk(KERN_ERR "CFLR setup failed (0x%x)\n", tmp); 1434 return -EIO; 1435 } 1436 } 1437 1438 /* Set the 'Configuration Write Protect' register 1439 * to 4281h. Allows vendor-defined configuration 1440 * space between 0e4h and 0ffh to be written. */ 1441 snd_cs4281_pokeBA0(chip, BA0_CWPR, 0x4281); 1442 1443 if ((tmp = snd_cs4281_peekBA0(chip, BA0_SERC1)) != (BA0_SERC1_SO1EN | BA0_SERC1_AC97)) { 1444 snd_printk(KERN_ERR "SERC1 AC'97 check failed (0x%x)\n", tmp); 1445 return -EIO; 1446 } 1447 if ((tmp = snd_cs4281_peekBA0(chip, BA0_SERC2)) != (BA0_SERC2_SI1EN | BA0_SERC2_AC97)) { 1448 snd_printk(KERN_ERR "SERC2 AC'97 check failed (0x%x)\n", tmp); 1449 return -EIO; 1450 } 1451 1452 /* Sound System Power Management */ 1453 snd_cs4281_pokeBA0(chip, BA0_SSPM, BA0_SSPM_MIXEN | BA0_SSPM_CSRCEN | 1454 BA0_SSPM_PSRCEN | BA0_SSPM_JSEN | 1455 BA0_SSPM_ACLEN | BA0_SSPM_FMEN); 1456 1457 /* Serial Port Power Management */ 1458 /* Blast the clock control register to zero so that the 1459 * PLL starts out in a known state, and blast the master serial 1460 * port control register to zero so that the serial ports also 1461 * start out in a known state. */ 1462 snd_cs4281_pokeBA0(chip, BA0_CLKCR1, 0); 1463 snd_cs4281_pokeBA0(chip, BA0_SERMC, 0); 1464 1465 /* Make ESYN go to zero to turn off 1466 * the Sync pulse on the AC97 link. */ 1467 snd_cs4281_pokeBA0(chip, BA0_ACCTL, 0); 1468 udelay(50); 1469 1470 /* Drive the ARST# pin low for a minimum of 1uS (as defined in the AC97 1471 * spec) and then drive it high. This is done for non AC97 modes since 1472 * there might be logic external to the CS4281 that uses the ARST# line 1473 * for a reset. */ 1474 snd_cs4281_pokeBA0(chip, BA0_SPMC, 0); 1475 udelay(50); 1476 snd_cs4281_pokeBA0(chip, BA0_SPMC, BA0_SPMC_RSTN); 1477 msleep(50); 1478 1479 if (chip->dual_codec) 1480 snd_cs4281_pokeBA0(chip, BA0_SPMC, BA0_SPMC_RSTN | BA0_SPMC_ASDI2E); 1481 1482 /* 1483 * Set the serial port timing configuration. 1484 */ 1485 snd_cs4281_pokeBA0(chip, BA0_SERMC, 1486 (chip->dual_codec ? BA0_SERMC_TCID(chip->dual_codec) : BA0_SERMC_TCID(1)) | 1487 BA0_SERMC_PTC_AC97 | BA0_SERMC_MSPE); 1488 1489 /* 1490 * Start the DLL Clock logic. 1491 */ 1492 snd_cs4281_pokeBA0(chip, BA0_CLKCR1, BA0_CLKCR1_DLLP); 1493 msleep(50); 1494 snd_cs4281_pokeBA0(chip, BA0_CLKCR1, BA0_CLKCR1_SWCE | BA0_CLKCR1_DLLP); 1495 1496 /* 1497 * Wait for the DLL ready signal from the clock logic. 1498 */ 1499 end_time = jiffies + HZ; 1500 do { 1501 /* 1502 * Read the AC97 status register to see if we've seen a CODEC 1503 * signal from the AC97 codec. 1504 */ 1505 if (snd_cs4281_peekBA0(chip, BA0_CLKCR1) & BA0_CLKCR1_DLLRDY) 1506 goto __ok0; 1507 schedule_timeout_uninterruptible(1); 1508 } while (time_after_eq(end_time, jiffies)); 1509 1510 snd_printk(KERN_ERR "DLLRDY not seen\n"); 1511 return -EIO; 1512 1513 __ok0: 1514 1515 /* 1516 * The first thing we do here is to enable sync generation. As soon 1517 * as we start receiving bit clock, we'll start producing the SYNC 1518 * signal. 1519 */ 1520 snd_cs4281_pokeBA0(chip, BA0_ACCTL, BA0_ACCTL_ESYN); 1521 1522 /* 1523 * Wait for the codec ready signal from the AC97 codec. 1524 */ 1525 end_time = jiffies + HZ; 1526 do { 1527 /* 1528 * Read the AC97 status register to see if we've seen a CODEC 1529 * signal from the AC97 codec. 1530 */ 1531 if (snd_cs4281_peekBA0(chip, BA0_ACSTS) & BA0_ACSTS_CRDY) 1532 goto __ok1; 1533 schedule_timeout_uninterruptible(1); 1534 } while (time_after_eq(end_time, jiffies)); 1535 1536 snd_printk(KERN_ERR "never read codec ready from AC'97 (0x%x)\n", snd_cs4281_peekBA0(chip, BA0_ACSTS)); 1537 return -EIO; 1538 1539 __ok1: 1540 if (chip->dual_codec) { 1541 end_time = jiffies + HZ; 1542 do { 1543 if (snd_cs4281_peekBA0(chip, BA0_ACSTS2) & BA0_ACSTS_CRDY) 1544 goto __codec2_ok; 1545 schedule_timeout_uninterruptible(1); 1546 } while (time_after_eq(end_time, jiffies)); 1547 snd_printk(KERN_INFO "secondary codec doesn't respond. disable it...\n"); 1548 chip->dual_codec = 0; 1549 __codec2_ok: ; 1550 } 1551 1552 /* 1553 * Assert the valid frame signal so that we can start sending commands 1554 * to the AC97 codec. 1555 */ 1556 1557 snd_cs4281_pokeBA0(chip, BA0_ACCTL, BA0_ACCTL_VFRM | BA0_ACCTL_ESYN); 1558 1559 /* 1560 * Wait until we've sampled input slots 3 and 4 as valid, meaning that 1561 * the codec is pumping ADC data across the AC-link. 1562 */ 1563 1564 end_time = jiffies + HZ; 1565 do { 1566 /* 1567 * Read the input slot valid register and see if input slots 3 1568 * 4 are valid yet. 1569 */ 1570 if ((snd_cs4281_peekBA0(chip, BA0_ACISV) & (BA0_ACISV_SLV(3) | BA0_ACISV_SLV(4))) == (BA0_ACISV_SLV(3) | BA0_ACISV_SLV(4))) 1571 goto __ok2; 1572 schedule_timeout_uninterruptible(1); 1573 } while (time_after_eq(end_time, jiffies)); 1574 1575 if (--retry_count > 0) 1576 goto __retry; 1577 snd_printk(KERN_ERR "never read ISV3 and ISV4 from AC'97\n"); 1578 return -EIO; 1579 1580 __ok2: 1581 1582 /* 1583 * Now, assert valid frame and the slot 3 and 4 valid bits. This will 1584 * commense the transfer of digital audio data to the AC97 codec. 1585 */ 1586 snd_cs4281_pokeBA0(chip, BA0_ACOSV, BA0_ACOSV_SLV(3) | BA0_ACOSV_SLV(4)); 1587 1588 /* 1589 * Initialize DMA structures 1590 */ 1591 for (tmp = 0; tmp < 4; tmp++) { 1592 struct cs4281_dma *dma = &chip->dma[tmp]; 1593 dma->regDBA = BA0_DBA0 + (tmp * 0x10); 1594 dma->regDCA = BA0_DCA0 + (tmp * 0x10); 1595 dma->regDBC = BA0_DBC0 + (tmp * 0x10); 1596 dma->regDCC = BA0_DCC0 + (tmp * 0x10); 1597 dma->regDMR = BA0_DMR0 + (tmp * 8); 1598 dma->regDCR = BA0_DCR0 + (tmp * 8); 1599 dma->regHDSR = BA0_HDSR0 + (tmp * 4); 1600 dma->regFCR = BA0_FCR0 + (tmp * 4); 1601 dma->regFSIC = BA0_FSIC0 + (tmp * 4); 1602 dma->fifo_offset = tmp * CS4281_FIFO_SIZE; 1603 snd_cs4281_pokeBA0(chip, dma->regFCR, 1604 BA0_FCR_LS(31) | 1605 BA0_FCR_RS(31) | 1606 BA0_FCR_SZ(CS4281_FIFO_SIZE) | 1607 BA0_FCR_OF(dma->fifo_offset)); 1608 } 1609 1610 chip->src_left_play_slot = 0; /* AC'97 left PCM playback (3) */ 1611 chip->src_right_play_slot = 1; /* AC'97 right PCM playback (4) */ 1612 chip->src_left_rec_slot = 10; /* AC'97 left PCM record (3) */ 1613 chip->src_right_rec_slot = 11; /* AC'97 right PCM record (4) */ 1614 1615 /* Activate wave playback FIFO for FM playback */ 1616 chip->dma[0].valFCR = BA0_FCR_FEN | BA0_FCR_LS(0) | 1617 BA0_FCR_RS(1) | 1618 BA0_FCR_SZ(CS4281_FIFO_SIZE) | 1619 BA0_FCR_OF(chip->dma[0].fifo_offset); 1620 snd_cs4281_pokeBA0(chip, chip->dma[0].regFCR, chip->dma[0].valFCR); 1621 snd_cs4281_pokeBA0(chip, BA0_SRCSA, (chip->src_left_play_slot << 0) | 1622 (chip->src_right_play_slot << 8) | 1623 (chip->src_left_rec_slot << 16) | 1624 (chip->src_right_rec_slot << 24)); 1625 1626 /* Initialize digital volume */ 1627 snd_cs4281_pokeBA0(chip, BA0_PPLVC, 0); 1628 snd_cs4281_pokeBA0(chip, BA0_PPRVC, 0); 1629 1630 /* Enable IRQs */ 1631 snd_cs4281_pokeBA0(chip, BA0_HICR, BA0_HICR_EOI); 1632 /* Unmask interrupts */ 1633 snd_cs4281_pokeBA0(chip, BA0_HIMR, 0x7fffffff & ~( 1634 BA0_HISR_MIDI | 1635 BA0_HISR_DMAI | 1636 BA0_HISR_DMA(0) | 1637 BA0_HISR_DMA(1) | 1638 BA0_HISR_DMA(2) | 1639 BA0_HISR_DMA(3))); 1640 synchronize_irq(chip->irq); 1641 1642 return 0; 1687 1643 } 1688 1644 … … 1691 1647 */ 1692 1648 1693 static void snd_cs4281_midi_reset( cs4281_t*chip)1694 { 1695 1696 1697 1698 } 1699 1700 static int snd_cs4281_midi_input_open(s nd_rawmidi_substream_t *substream)1701 { 1702 cs4281_t*chip = substream->rmidi->private_data;1703 1704 1705 1706 chip->midi_output = substream;1707 1708 1709 1710 1711 1712 1713 1714 } 1715 1716 static int snd_cs4281_midi_input_close(s nd_rawmidi_substream_t *substream)1717 { 1718 cs4281_t*chip = substream->rmidi->private_data;1719 1720 1721 1722 1723 1724 1725 1726 1727 1728 1729 1730 1731 } 1732 1733 static int snd_cs4281_midi_output_open(s nd_rawmidi_substream_t *substream)1734 { 1735 cs4281_t*chip = substream->rmidi->private_data;1736 1737 1738 1739 1740 chip->midi_input = substream;1741 1742 1743 1744 1745 1746 1747 1748 } 1749 1750 static int snd_cs4281_midi_output_close(s nd_rawmidi_substream_t *substream)1751 { 1752 cs4281_t*chip = substream->rmidi->private_data;1753 1754 1755 1756 1757 1758 1759 1760 1761 1762 1763 1764 1765 } 1766 1767 static void snd_cs4281_midi_input_trigger(s nd_rawmidi_substream_t *substream, int up)1768 { 1769 1770 cs4281_t*chip = substream->rmidi->private_data;1771 1772 1773 1774 1775 1776 1777 1778 1779 1780 1781 1782 1783 1784 1785 } 1786 1787 static void snd_cs4281_midi_output_trigger(s nd_rawmidi_substream_t *substream, int up)1788 { 1789 1790 cs4281_t*chip = substream->rmidi->private_data;1791 1792 1793 1794 1795 1796 1797 1798 1799 1800 1801 1802 1803 1804 1805 1806 1807 1808 1809 1810 1811 1812 1813 1814 1649 static void snd_cs4281_midi_reset(struct cs4281 *chip) 1650 { 1651 snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr | BA0_MIDCR_MRST); 1652 udelay(100); 1653 snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr); 1654 } 1655 1656 static int snd_cs4281_midi_input_open(struct snd_rawmidi_substream *substream) 1657 { 1658 struct cs4281 *chip = substream->rmidi->private_data; 1659 1660 spin_lock_irq(&chip->reg_lock); 1661 chip->midcr |= BA0_MIDCR_RXE; 1662 chip->midi_input = substream; 1663 if (!(chip->uartm & CS4281_MODE_OUTPUT)) { 1664 snd_cs4281_midi_reset(chip); 1665 } else { 1666 snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr); 1667 } 1668 spin_unlock_irq(&chip->reg_lock); 1669 return 0; 1670 } 1671 1672 static int snd_cs4281_midi_input_close(struct snd_rawmidi_substream *substream) 1673 { 1674 struct cs4281 *chip = substream->rmidi->private_data; 1675 1676 spin_lock_irq(&chip->reg_lock); 1677 chip->midcr &= ~(BA0_MIDCR_RXE | BA0_MIDCR_RIE); 1678 chip->midi_input = NULL; 1679 if (!(chip->uartm & CS4281_MODE_OUTPUT)) { 1680 snd_cs4281_midi_reset(chip); 1681 } else { 1682 snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr); 1683 } 1684 chip->uartm &= ~CS4281_MODE_INPUT; 1685 spin_unlock_irq(&chip->reg_lock); 1686 return 0; 1687 } 1688 1689 static int snd_cs4281_midi_output_open(struct snd_rawmidi_substream *substream) 1690 { 1691 struct cs4281 *chip = substream->rmidi->private_data; 1692 1693 spin_lock_irq(&chip->reg_lock); 1694 chip->uartm |= CS4281_MODE_OUTPUT; 1695 chip->midcr |= BA0_MIDCR_TXE; 1696 chip->midi_output = substream; 1697 if (!(chip->uartm & CS4281_MODE_INPUT)) { 1698 snd_cs4281_midi_reset(chip); 1699 } else { 1700 snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr); 1701 } 1702 spin_unlock_irq(&chip->reg_lock); 1703 return 0; 1704 } 1705 1706 static int snd_cs4281_midi_output_close(struct snd_rawmidi_substream *substream) 1707 { 1708 struct cs4281 *chip = substream->rmidi->private_data; 1709 1710 spin_lock_irq(&chip->reg_lock); 1711 chip->midcr &= ~(BA0_MIDCR_TXE | BA0_MIDCR_TIE); 1712 chip->midi_output = NULL; 1713 if (!(chip->uartm & CS4281_MODE_INPUT)) { 1714 snd_cs4281_midi_reset(chip); 1715 } else { 1716 snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr); 1717 } 1718 chip->uartm &= ~CS4281_MODE_OUTPUT; 1719 spin_unlock_irq(&chip->reg_lock); 1720 return 0; 1721 } 1722 1723 static void snd_cs4281_midi_input_trigger(struct snd_rawmidi_substream *substream, int up) 1724 { 1725 unsigned long flags; 1726 struct cs4281 *chip = substream->rmidi->private_data; 1727 1728 spin_lock_irqsave(&chip->reg_lock, flags); 1729 if (up) { 1730 if ((chip->midcr & BA0_MIDCR_RIE) == 0) { 1731 chip->midcr |= BA0_MIDCR_RIE; 1732 snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr); 1733 } 1734 } else { 1735 if (chip->midcr & BA0_MIDCR_RIE) { 1736 chip->midcr &= ~BA0_MIDCR_RIE; 1737 snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr); 1738 } 1739 } 1740 spin_unlock_irqrestore(&chip->reg_lock, flags); 1741 } 1742 1743 static void snd_cs4281_midi_output_trigger(struct snd_rawmidi_substream *substream, int up) 1744 { 1745 unsigned long flags; 1746 struct cs4281 *chip = substream->rmidi->private_data; 1747 unsigned char byte; 1748 1749 spin_lock_irqsave(&chip->reg_lock, flags); 1750 if (up) { 1751 if ((chip->midcr & BA0_MIDCR_TIE) == 0) { 1752 chip->midcr |= BA0_MIDCR_TIE; 1753 /* fill UART FIFO buffer at first, and turn Tx interrupts only if necessary */ 1754 while ((chip->midcr & BA0_MIDCR_TIE) && 1755 (snd_cs4281_peekBA0(chip, BA0_MIDSR) & BA0_MIDSR_TBF) == 0) { 1756 if (snd_rawmidi_transmit(substream, &byte, 1) != 1) { 1757 chip->midcr &= ~BA0_MIDCR_TIE; 1758 } else { 1759 snd_cs4281_pokeBA0(chip, BA0_MIDWP, byte); 1760 } 1761 } 1762 snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr); 1763 } 1764 } else { 1765 if (chip->midcr & BA0_MIDCR_TIE) { 1766 chip->midcr &= ~BA0_MIDCR_TIE; 1767 snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr); 1768 } 1769 } 1770 spin_unlock_irqrestore(&chip->reg_lock, flags); 1815 1771 } 1816 1772 1817 1773 static struct snd_rawmidi_ops snd_cs4281_midi_output = 1818 1774 { 1819 1820 1821 1775 .open = snd_cs4281_midi_output_open, 1776 .close = snd_cs4281_midi_output_close, 1777 .trigger = snd_cs4281_midi_output_trigger, 1822 1778 }; 1823 1779 1824 1780 static struct snd_rawmidi_ops snd_cs4281_midi_input = 1825 1781 { 1826 1827 1828 1782 .open = snd_cs4281_midi_input_open, 1783 .close = snd_cs4281_midi_input_close, 1784 .trigger = snd_cs4281_midi_input_trigger, 1829 1785 }; 1830 1786 1831 static int __devinit snd_cs4281_midi(cs4281_t * chip, int device, snd_rawmidi_t **rrawmidi) 1832 { 1833 snd_rawmidi_t *rmidi; 1834 int err; 1835 1836 if (rrawmidi) 1837 *rrawmidi = NULL; 1838 if ((err = snd_rawmidi_new(chip->card, "CS4281", device, 1, 1, &rmidi)) < 0) 1839 return err; 1840 strcpy(rmidi->name, "CS4281"); 1841 snd_rawmidi_set_ops(rmidi, SNDRV_RAWMIDI_STREAM_OUTPUT, &snd_cs4281_midi_output); 1842 snd_rawmidi_set_ops(rmidi, SNDRV_RAWMIDI_STREAM_INPUT, &snd_cs4281_midi_input); 1843 rmidi->info_flags |= SNDRV_RAWMIDI_INFO_OUTPUT | SNDRV_RAWMIDI_INFO_INPUT | SNDRV_RAWMIDI_INFO_DUPLEX; 1844 rmidi->private_data = chip; 1845 chip->rmidi = rmidi; 1846 if (rrawmidi) 1847 *rrawmidi = rmidi; 1848 return 0; 1787 static int __devinit snd_cs4281_midi(struct cs4281 * chip, int device, 1788 struct snd_rawmidi **rrawmidi) 1789 { 1790 struct snd_rawmidi *rmidi; 1791 int err; 1792 1793 if (rrawmidi) 1794 *rrawmidi = NULL; 1795 if ((err = snd_rawmidi_new(chip->card, "CS4281", device, 1, 1, &rmidi)) < 0) 1796 return err; 1797 strcpy(rmidi->name, "CS4281"); 1798 snd_rawmidi_set_ops(rmidi, SNDRV_RAWMIDI_STREAM_OUTPUT, &snd_cs4281_midi_output); 1799 snd_rawmidi_set_ops(rmidi, SNDRV_RAWMIDI_STREAM_INPUT, &snd_cs4281_midi_input); 1800 rmidi->info_flags |= SNDRV_RAWMIDI_INFO_OUTPUT | SNDRV_RAWMIDI_INFO_INPUT | SNDRV_RAWMIDI_INFO_DUPLEX; 1801 rmidi->private_data = chip; 1802 chip->rmidi = rmidi; 1803 if (rrawmidi) 1804 *rrawmidi = rmidi; 1805 return 0; 1849 1806 } 1850 1807 … … 1853 1810 */ 1854 1811 1855 static irqreturn_t snd_cs4281_interrupt(int irq, void *dev_id, struct pt_regs *regs) 1856 { 1857 cs4281_t *chip = dev_id; 1858 unsigned int status, dma, val; 1859 cs4281_dma_t *cdma; 1860 1861 if (chip == NULL) 1862 return IRQ_NONE; 1863 status = snd_cs4281_peekBA0(chip, BA0_HISR); 1864 if ((status & 0x7fffffff) == 0) { 1865 snd_cs4281_pokeBA0(chip, BA0_HICR, BA0_HICR_EOI); 1866 return IRQ_NONE; 1867 } 1868 1869 if (status & (BA0_HISR_DMA(0)|BA0_HISR_DMA(1)|BA0_HISR_DMA(2)|BA0_HISR_DMA(3))) { 1870 for (dma = 0; dma < 4; dma++) 1871 if (status & BA0_HISR_DMA(dma)) { 1872 cdma = &chip->dma[dma]; 1873 spin_lock(&chip->reg_lock); 1874 /* ack DMA IRQ */ 1875 val = snd_cs4281_peekBA0(chip, cdma->regHDSR); 1876 /* workaround, sometimes CS4281 acknowledges */ 1877 /* end or middle transfer position twice */ 1878 cdma->frag++; 1879 if ((val & BA0_HDSR_DHTC) && !(cdma->frag & 1)) { 1880 cdma->frag--; 1881 chip->spurious_dhtc_irq++; 1882 spin_unlock(&chip->reg_lock); 1883 continue; 1884 } 1885 if ((val & BA0_HDSR_DTC) && (cdma->frag & 1)) { 1886 cdma->frag--; 1887 chip->spurious_dtc_irq++; 1888 spin_unlock(&chip->reg_lock); 1889 continue; 1890 } 1891 spin_unlock(&chip->reg_lock); 1892 snd_pcm_period_elapsed(cdma->substream); 1893 } 1894 } 1895 1896 if ((status & BA0_HISR_MIDI) && chip->rmidi) { 1897 unsigned char c; 1898 1899 spin_lock(&chip->reg_lock); 1900 while ((snd_cs4281_peekBA0(chip, BA0_MIDSR) & BA0_MIDSR_RBE) == 0) { 1901 c = snd_cs4281_peekBA0(chip, BA0_MIDRP); 1902 if ((chip->midcr & BA0_MIDCR_RIE) == 0) 1903 continue; 1904 spin_unlock(&chip->reg_lock); 1905 snd_rawmidi_receive(chip->midi_input, &c, 1); 1906 spin_lock(&chip->reg_lock); 1907 } 1908 while ((snd_cs4281_peekBA0(chip, BA0_MIDSR) & BA0_MIDSR_TBF) == 0) { 1909 if ((chip->midcr & BA0_MIDCR_TIE) == 0) 1910 break; 1911 if (snd_rawmidi_transmit(chip->midi_output, &c, 1) != 1) { 1912 chip->midcr &= ~BA0_MIDCR_TIE; 1913 snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr); 1914 break; 1915 } 1916 snd_cs4281_pokeBA0(chip, BA0_MIDWP, c); 1917 } 1918 spin_unlock(&chip->reg_lock); 1919 } 1920 1921 /* EOI to the PCI part... reenables interrupts */ 1922 snd_cs4281_pokeBA0(chip, BA0_HICR, BA0_HICR_EOI); 1923 return IRQ_HANDLED; 1924 1925 } 1812 static irqreturn_t snd_cs4281_interrupt(int irq, void *dev_id) 1813 { 1814 struct cs4281 *chip = dev_id; 1815 unsigned int status, dma, val; 1816 struct cs4281_dma *cdma; 1817 1818 if (chip == NULL) 1819 return IRQ_NONE; 1820 status = snd_cs4281_peekBA0(chip, BA0_HISR); 1821 if ((status & 0x7fffffff) == 0) { 1822 snd_cs4281_pokeBA0(chip, BA0_HICR, BA0_HICR_EOI); 1823 return IRQ_NONE; 1824 } 1825 1826 if (status & (BA0_HISR_DMA(0)|BA0_HISR_DMA(1)|BA0_HISR_DMA(2)|BA0_HISR_DMA(3))) { 1827 for (dma = 0; dma < 4; dma++) 1828 if (status & BA0_HISR_DMA(dma)) { 1829 cdma = &chip->dma[dma]; 1830 spin_lock(&chip->reg_lock); 1831 /* ack DMA IRQ */ 1832 val = snd_cs4281_peekBA0(chip, cdma->regHDSR); 1833 /* workaround, sometimes CS4281 acknowledges */ 1834 /* end or middle transfer position twice */ 1835 cdma->frag++; 1836 if ((val & BA0_HDSR_DHTC) && !(cdma->frag & 1)) { 1837 cdma->frag--; 1838 chip->spurious_dhtc_irq++; 1839 spin_unlock(&chip->reg_lock); 1840 continue; 1841 } 1842 if ((val & BA0_HDSR_DTC) && (cdma->frag & 1)) { 1843 cdma->frag--; 1844 chip->spurious_dtc_irq++; 1845 spin_unlock(&chip->reg_lock); 1846 continue; 1847 } 1848 spin_unlock(&chip->reg_lock); 1849 snd_pcm_period_elapsed(cdma->substream); 1850 } 1851 } 1852 1853 if ((status & BA0_HISR_MIDI) && chip->rmidi) { 1854 unsigned char c; 1855 1856 spin_lock(&chip->reg_lock); 1857 while ((snd_cs4281_peekBA0(chip, BA0_MIDSR) & BA0_MIDSR_RBE) == 0) { 1858 c = snd_cs4281_peekBA0(chip, BA0_MIDRP); 1859 if ((chip->midcr & BA0_MIDCR_RIE) == 0) 1860 continue; 1861 snd_rawmidi_receive(chip->midi_input, &c, 1); 1862 } 1863 while ((snd_cs4281_peekBA0(chip, BA0_MIDSR) & BA0_MIDSR_TBF) == 0) { 1864 if ((chip->midcr & BA0_MIDCR_TIE) == 0) 1865 break; 1866 if (snd_rawmidi_transmit(chip->midi_output, &c, 1) != 1) { 1867 chip->midcr &= ~BA0_MIDCR_TIE; 1868 snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr); 1869 break; 1870 } 1871 snd_cs4281_pokeBA0(chip, BA0_MIDWP, c); 1872 } 1873 spin_unlock(&chip->reg_lock); 1874 } 1875 1876 /* EOI to the PCI part... reenables interrupts */ 1877 snd_cs4281_pokeBA0(chip, BA0_HICR, BA0_HICR_EOI); 1878 1879 return IRQ_HANDLED; 1880 } 1881 1926 1882 1927 1883 /* 1928 1884 * OPL3 command 1929 1885 */ 1930 static void snd_cs4281_opl3_command(opl3_t * opl3, unsigned short cmd, unsigned char val) 1931 { 1932 unsigned long flags; 1933 cs4281_t *chip = opl3->private_data; 1934 void __iomem *port; 1935 1936 if (cmd & OPL3_RIGHT) 1937 port = (void *)chip->ba0 + BA0_B1AP; /* right port */ 1938 else 1939 port = (void *)chip->ba0 + BA0_B0AP; /* left port */ 1940 1941 spin_lock_irqsave(&opl3->reg_lock, flags); 1942 1943 writel((unsigned int)cmd, port); 1944 udelay(10); 1945 1946 writel((unsigned int)val, (unsigned long)port + 4); 1947 udelay(30); 1948 1949 spin_unlock_irqrestore(&opl3->reg_lock, flags); 1886 static void snd_cs4281_opl3_command(struct snd_opl3 *opl3, unsigned short cmd, 1887 unsigned char val) 1888 { 1889 unsigned long flags; 1890 struct cs4281 *chip = opl3->private_data; 1891 void __iomem *port; 1892 1893 if (cmd & OPL3_RIGHT) 1894 port = chip->ba0 + BA0_B1AP; /* right port */ 1895 else 1896 port = chip->ba0 + BA0_B0AP; /* left port */ 1897 1898 spin_lock_irqsave(&opl3->reg_lock, flags); 1899 1900 writel((unsigned int)cmd, port); 1901 udelay(10); 1902 1903 writel((unsigned int)val, port + 4); 1904 udelay(30); 1905 1906 spin_unlock_irqrestore(&opl3->reg_lock, flags); 1950 1907 } 1951 1908 1952 1909 static int __devinit snd_cs4281_probe(struct pci_dev *pci, 1953 const struct pci_device_id *pci_id) 1954 { 1955 static int dev; 1956 snd_card_t *card; 1957 cs4281_t *chip; 1958 opl3_t *opl3; 1959 int err; 1960 1961 if (dev >= SNDRV_CARDS) 1962 return -ENODEV; 1963 if (!enable[dev]) { 1964 dev++; 1965 return -ENOENT; 1966 } 1967 1968 card = snd_card_new(index[dev], id[dev], THIS_MODULE, 0); 1969 if (card == NULL) 1970 return -ENOMEM; 1971 1972 if ((err = snd_cs4281_create(card, pci, &chip, dual_codec[dev])) < 0) { 1973 snd_card_free(card); 1974 return err; 1975 } 1976 1977 if ((err = snd_cs4281_mixer(chip)) < 0) { 1978 snd_card_free(card); 1979 return err; 1980 } 1981 if ((err = snd_cs4281_pcm(chip, 0, NULL)) < 0) { 1982 snd_card_free(card); 1983 return err; 1984 } 1985 if ((err = snd_cs4281_midi(chip, 0, NULL)) < 0) { 1986 snd_card_free(card); 1987 return err; 1988 } 1989 if ((err = snd_opl3_new(card, OPL3_HW_OPL3_CS4281, &opl3)) < 0) { 1990 snd_card_free(card); 1991 return err; 1992 } 1993 opl3->private_data = chip; 1994 opl3->command = snd_cs4281_opl3_command; 1995 snd_opl3_init(opl3); 1996 1997 if ((err = snd_opl3_hwdep_new(opl3, 0, 1, NULL)) < 0) { 1998 snd_card_free(card); 1999 return err; 2000 } 2001 #ifndef LINUX_2_2 2002 snd_cs4281_gameport(chip); 2003 #endif 2004 strcpy(card->driver, "CS4281"); 2005 strcpy(card->shortname, "Cirrus Logic CS4281"); 2006 sprintf(card->longname, "%s at 0x%lx, irq %d", 2007 card->shortname, 2008 chip->ba0_addr, 2009 chip->irq); 2010 2011 if ((err = snd_card_register(card)) < 0) { 2012 snd_card_free(card); 2013 return err; 2014 } 2015 2016 pci_set_drvdata(pci, card); 2017 dev++; 2018 return 0; 1910 const struct pci_device_id *pci_id) 1911 { 1912 static int dev; 1913 struct snd_card *card; 1914 struct cs4281 *chip; 1915 struct snd_opl3 *opl3; 1916 int err; 1917 1918 if (dev >= SNDRV_CARDS) 1919 return -ENODEV; 1920 if (!enable[dev]) { 1921 dev++; 1922 return -ENOENT; 1923 } 1924 1925 card = snd_card_new(index[dev], id[dev], THIS_MODULE, 0); 1926 if (card == NULL) 1927 return -ENOMEM; 1928 1929 if ((err = snd_cs4281_create(card, pci, &chip, dual_codec[dev])) < 0) { 1930 snd_card_free(card); 1931 return err; 1932 } 1933 card->private_data = chip; 1934 1935 if ((err = snd_cs4281_mixer(chip)) < 0) { 1936 snd_card_free(card); 1937 return err; 1938 } 1939 if ((err = snd_cs4281_pcm(chip, 0, NULL)) < 0) { 1940 snd_card_free(card); 1941 return err; 1942 } 1943 if ((err = snd_cs4281_midi(chip, 0, NULL)) < 0) { 1944 snd_card_free(card); 1945 return err; 1946 } 1947 if ((err = snd_opl3_new(card, OPL3_HW_OPL3_CS4281, &opl3)) < 0) { 1948 snd_card_free(card); 1949 return err; 1950 } 1951 opl3->private_data = chip; 1952 opl3->command = snd_cs4281_opl3_command; 1953 snd_opl3_init(opl3); 1954 if ((err = snd_opl3_hwdep_new(opl3, 0, 1, NULL)) < 0) { 1955 snd_card_free(card); 1956 return err; 1957 } 1958 snd_cs4281_create_gameport(chip); 1959 strcpy(card->driver, "CS4281"); 1960 strcpy(card->shortname, "Cirrus Logic CS4281"); 1961 sprintf(card->longname, "%s at 0x%lx, irq %d", 1962 card->shortname, 1963 chip->ba0_addr, 1964 chip->irq); 1965 1966 if ((err = snd_card_register(card)) < 0) { 1967 snd_card_free(card); 1968 return err; 1969 } 1970 1971 pci_set_drvdata(pci, card); 1972 dev++; 1973 return 0; 2019 1974 } 2020 1975 2021 1976 static void __devexit snd_cs4281_remove(struct pci_dev *pci) 2022 1977 { 2023 2024 1978 snd_card_free(pci_get_drvdata(pci)); 1979 pci_set_drvdata(pci, NULL); 2025 1980 } 2026 1981 … … 2031 1986 2032 1987 static int saved_regs[SUSPEND_REGISTERS] = { 2033 2034 2035 2036 2037 2038 2039 2040 2041 2042 2043 2044 2045 1988 BA0_JSCTL, 1989 BA0_GPIOR, 1990 BA0_SSCR, 1991 BA0_MIDCR, 1992 BA0_SRCSA, 1993 BA0_PASR, 1994 BA0_CASR, 1995 BA0_DACSR, 1996 BA0_ADCSR, 1997 BA0_FMLVC, 1998 BA0_FMRVC, 1999 BA0_PPLVC, 2000 BA0_PPRVC, 2046 2001 }; 2047 2002 2048 #define number_of(array) (sizeof(array) / sizeof(array[0]))2049 2050 2003 #define CLKCR1_CKRA 0x00010000L 2051 2004 2052 static int cs4281_suspend(snd_card_t *card, unsigned int state) 2053 { 2054 cs4281_t *chip = card->pm_private_data; 2055 u32 ulCLK; 2056 unsigned int i; 2057 2058 snd_pcm_suspend_all(chip->pcm); 2059 2060 if (chip->ac97) 2061 snd_ac97_suspend(chip->ac97); 2062 if (chip->ac97_secondary) 2063 snd_ac97_suspend(chip->ac97_secondary); 2064 2065 ulCLK = snd_cs4281_peekBA0(chip, BA0_CLKCR1); 2066 ulCLK |= CLKCR1_CKRA; 2067 snd_cs4281_pokeBA0(chip, BA0_CLKCR1, ulCLK); 2068 2069 /* Disable interrupts. */ 2070 snd_cs4281_pokeBA0(chip, BA0_HICR, BA0_HICR_CHGM); 2071 2072 /* remember the status registers */ 2073 for (i = 0; i < number_of(saved_regs); i++) 2074 if (saved_regs[i]) 2075 chip->suspend_regs[i] = snd_cs4281_peekBA0(chip, saved_regs[i]); 2076 2077 /* Turn off the serial ports. */ 2078 snd_cs4281_pokeBA0(chip, BA0_SERMC, 0); 2079 2080 /* Power off FM, Joystick, AC link, */ 2081 snd_cs4281_pokeBA0(chip, BA0_SSPM, 0); 2082 2083 /* DLL off. */ 2084 snd_cs4281_pokeBA0(chip, BA0_CLKCR1, 0); 2085 2086 /* AC link off. */ 2087 snd_cs4281_pokeBA0(chip, BA0_SPMC, 0); 2088 2089 ulCLK = snd_cs4281_peekBA0(chip, BA0_CLKCR1); 2090 ulCLK &= ~CLKCR1_CKRA; 2091 snd_cs4281_pokeBA0(chip, BA0_CLKCR1, ulCLK); 2092 2093 return 0; 2094 } 2095 2096 static int cs4281_resume(snd_card_t *card, unsigned int state) 2097 { 2098 cs4281_t *chip = card->pm_private_data; 2099 unsigned int i; 2100 u32 ulCLK; 2101 2102 pci_enable_device(chip->pci); 2103 2104 ulCLK = snd_cs4281_peekBA0(chip, BA0_CLKCR1); 2105 ulCLK |= CLKCR1_CKRA; 2106 snd_cs4281_pokeBA0(chip, BA0_CLKCR1, ulCLK); 2107 2108 snd_cs4281_chip_init(chip); 2109 2110 /* restore the status registers */ 2111 for (i = 0; i < number_of(saved_regs); i++) 2112 if (saved_regs[i]) 2113 snd_cs4281_pokeBA0(chip, saved_regs[i], chip->suspend_regs[i]); 2114 2115 if (chip->ac97) 2116 snd_ac97_resume(chip->ac97); 2117 if (chip->ac97_secondary) 2118 snd_ac97_resume(chip->ac97_secondary); 2119 2120 ulCLK = snd_cs4281_peekBA0(chip, BA0_CLKCR1); 2121 ulCLK &= ~CLKCR1_CKRA; 2122 snd_cs4281_pokeBA0(chip, BA0_CLKCR1, ulCLK); 2123 2124 return 0; 2125 } 2126 2127 2005 static int cs4281_suspend(struct pci_dev *pci, pm_message_t state) 2006 { 2007 struct snd_card *card = pci_get_drvdata(pci); 2008 struct cs4281 *chip = card->private_data; 2009 u32 ulCLK; 2010 unsigned int i; 2011 2012 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot); 2013 snd_pcm_suspend_all(chip->pcm); 2014 2015 snd_ac97_suspend(chip->ac97); 2016 snd_ac97_suspend(chip->ac97_secondary); 2017 2018 ulCLK = snd_cs4281_peekBA0(chip, BA0_CLKCR1); 2019 ulCLK |= CLKCR1_CKRA; 2020 snd_cs4281_pokeBA0(chip, BA0_CLKCR1, ulCLK); 2021 2022 /* Disable interrupts. */ 2023 snd_cs4281_pokeBA0(chip, BA0_HICR, BA0_HICR_CHGM); 2024 2025 /* remember the status registers */ 2026 for (i = 0; i < ARRAY_SIZE(saved_regs); i++) 2027 if (saved_regs[i]) 2028 chip->suspend_regs[i] = snd_cs4281_peekBA0(chip, saved_regs[i]); 2029 2030 /* Turn off the serial ports. */ 2031 snd_cs4281_pokeBA0(chip, BA0_SERMC, 0); 2032 2033 /* Power off FM, Joystick, AC link, */ 2034 snd_cs4281_pokeBA0(chip, BA0_SSPM, 0); 2035 2036 /* DLL off. */ 2037 snd_cs4281_pokeBA0(chip, BA0_CLKCR1, 0); 2038 2039 /* AC link off. */ 2040 snd_cs4281_pokeBA0(chip, BA0_SPMC, 0); 2041 2042 ulCLK = snd_cs4281_peekBA0(chip, BA0_CLKCR1); 2043 ulCLK &= ~CLKCR1_CKRA; 2044 snd_cs4281_pokeBA0(chip, BA0_CLKCR1, ulCLK); 2045 2046 pci_disable_device(pci); 2047 pci_save_state(pci); 2048 pci_set_power_state(pci, pci_choose_state(pci, state)); 2049 return 0; 2050 } 2051 2052 static int cs4281_resume(struct pci_dev *pci) 2053 { 2054 struct snd_card *card = pci_get_drvdata(pci); 2055 struct cs4281 *chip = card->private_data; 2056 unsigned int i; 2057 u32 ulCLK; 2058 2059 pci_set_power_state(pci, PCI_D0); 2060 pci_restore_state(pci); 2061 if (pci_enable_device(pci) < 0) { 2062 printk(KERN_ERR "cs4281: pci_enable_device failed, " 2063 "disabling device\n"); 2064 snd_card_disconnect(card); 2065 return -EIO; 2066 } 2067 pci_set_master(pci); 2068 2069 ulCLK = snd_cs4281_peekBA0(chip, BA0_CLKCR1); 2070 ulCLK |= CLKCR1_CKRA; 2071 snd_cs4281_pokeBA0(chip, BA0_CLKCR1, ulCLK); 2072 2073 snd_cs4281_chip_init(chip); 2074 2075 /* restore the status registers */ 2076 for (i = 0; i < ARRAY_SIZE(saved_regs); i++) 2077 if (saved_regs[i]) 2078 snd_cs4281_pokeBA0(chip, saved_regs[i], chip->suspend_regs[i]); 2079 2080 snd_ac97_resume(chip->ac97); 2081 snd_ac97_resume(chip->ac97_secondary); 2082 2083 ulCLK = snd_cs4281_peekBA0(chip, BA0_CLKCR1); 2084 ulCLK &= ~CLKCR1_CKRA; 2085 snd_cs4281_pokeBA0(chip, BA0_CLKCR1, ulCLK); 2086 2087 snd_power_change_state(card, SNDRV_CTL_POWER_D0); 2088 return 0; 2089 } 2128 2090 #endif /* CONFIG_PM */ 2129 2091 2130 2092 static struct pci_driver driver = { 2131 0, 0,0, 2132 "CS4281", 2133 snd_cs4281_ids, 2134 snd_cs4281_probe, 2135 snd_cs4281_remove, 2136 SND_PCI_PM_CALLBACKS 2093 .name = "CS4281", 2094 .id_table = snd_cs4281_ids, 2095 .probe = snd_cs4281_probe, 2096 .remove = __devexit_p(snd_cs4281_remove), 2097 #ifdef CONFIG_PM 2098 .suspend = cs4281_suspend, 2099 .resume = cs4281_resume, 2100 #endif 2137 2101 }; 2138 2102 2139 2103 static int __init alsa_card_cs4281_init(void) 2140 2104 { 2141 int err; 2142 2143 if ((err = pci_module_init(&driver)) < 0) { 2144 #ifdef MODULE 2145 // printk(KERN_ERR "CS4281 soundcard not found or device busy\n"); 2146 #endif 2147 return err; 2148 } 2149 return 0; 2105 return pci_register_driver(&driver); 2150 2106 } 2151 2107 2152 2108 static void __exit alsa_card_cs4281_exit(void) 2153 2109 { 2154 2110 pci_unregister_driver(&driver); 2155 2111 } 2156 2112 2157 2113 module_init(alsa_card_cs4281_init) 2158 2114 module_exit(alsa_card_cs4281_exit) 2159 2160 #ifndef MODULE2161 2162 /* format is: snd-cs4281=snd_enable,snd_index,snd_id */2163 2164 static int __init alsa_card_cs4281_setup(char *str)2165 {2166 static unsigned __initdata nr_dev = 0;2167 2168 if (nr_dev >= SNDRV_CARDS)2169 return 0;2170 (void)(get_option(&str,&enable[nr_dev]) == 2 &&2171 get_option(&str,&index[nr_dev]) == 2 &&2172 get_id(&str,&id[nr_dev]) == 2);2173 nr_dev++;2174 return 1;2175 }2176 2177 __setup("snd-cs4281=", alsa_card_cs4281_setup);2178 2179 #endif /* ifndef MODULE */
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