source: GPL/trunk/alsa-kernel/pci/maestro3.c@ 680

Last change on this file since 680 was 679, checked in by David Azarewicz, 5 years ago

Merge changes from Paul's uniaud32next branch.
File size: 83.8 KB
Line 
1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Driver for ESS Maestro3/Allegro (ES1988) soundcards.
4 * Copyright (c) 2000 by Zach Brown <zab@zabbo.net>
5 * Takashi Iwai <tiwai@suse.de>
6 *
7 * Most of the hardware init stuffs are based on maestro3 driver for
8 * OSS/Free by Zach Brown. Many thanks to Zach!
9 *
10 * ChangeLog:
11 * Aug. 27, 2001
12 * - Fixed deadlock on capture
13 * - Added Canyon3D-2 support by Rob Riggs <rob@pangalactic.org>
14 */
15
16#define CARD_NAME "ESS Maestro3/Allegro/Canyon3D-2"
17#define DRIVER_NAME "Maestro3"
18#ifdef TARGET_OS2
19#define KBUILD_MODNAME "Maestro3"
20#endif
21
22#include <linux/io.h>
23#include <linux/delay.h>
24#include <linux/interrupt.h>
25#include <linux/init.h>
26#include <linux/pci.h>
27#include <linux/dma-mapping.h>
28#include <linux/slab.h>
29#include <linux/vmalloc.h>
30#include <linux/module.h>
31#include <linux/firmware.h>
32#include <linux/input.h>
33#include <sound/core.h>
34#include <sound/info.h>
35#include <sound/control.h>
36#include <sound/pcm.h>
37#include <sound/mpu401.h>
38#include <sound/ac97_codec.h>
39#include <sound/initval.h>
40#include <asm/byteorder.h>
41
42MODULE_AUTHOR("Zach Brown <zab@zabbo.net>, Takashi Iwai <tiwai@suse.de>");
43MODULE_DESCRIPTION("ESS Maestro3 PCI");
44MODULE_LICENSE("GPL");
45MODULE_SUPPORTED_DEVICE("{{ESS,Maestro3 PCI},"
46 "{ESS,ES1988},"
47 "{ESS,Allegro PCI},"
48 "{ESS,Allegro-1 PCI},"
49 "{ESS,Canyon3D-2/LE PCI}}");
50MODULE_FIRMWARE("ess/maestro3_assp_kernel.fw");
51MODULE_FIRMWARE("ess/maestro3_assp_minisrc.fw");
52
53static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
54static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
55static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* all enabled */
56#ifndef TARGET_OS2
57static bool external_amp[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = 1};
58static int amp_gpio[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = -1};
59#else
60static int external_amp[SNDRV_CARDS] = {REPEAT_SNDRV(1)};
61static int amp_gpio[SNDRV_CARDS] = {REPEAT_SNDRV(-1)};
62#endif
63module_param_array(index, int, NULL, 0444);
64MODULE_PARM_DESC(index, "Index value for " CARD_NAME " soundcard.");
65module_param_array(id, charp, NULL, 0444);
66MODULE_PARM_DESC(id, "ID string for " CARD_NAME " soundcard.");
67module_param_array(enable, bool, NULL, 0444);
68MODULE_PARM_DESC(enable, "Enable this soundcard.");
69module_param_array(external_amp, bool, NULL, 0444);
70MODULE_PARM_DESC(external_amp, "Enable external amp for " CARD_NAME " soundcard.");
71module_param_array(amp_gpio, int, NULL, 0444);
72MODULE_PARM_DESC(amp_gpio, "GPIO pin number for external amp. (default = -1)");
73
74#define MAX_PLAYBACKS 2
75#define MAX_CAPTURES 1
76#define NR_DSPS (MAX_PLAYBACKS + MAX_CAPTURES)
77
78
79/*
80 * maestro3 registers
81 */
82
83/* Allegro PCI configuration registers */
84#define PCI_LEGACY_AUDIO_CTRL 0x40
85#define SOUND_BLASTER_ENABLE 0x00000001
86#define FM_SYNTHESIS_ENABLE 0x00000002
87#define GAME_PORT_ENABLE 0x00000004
88#define MPU401_IO_ENABLE 0x00000008
89#define MPU401_IRQ_ENABLE 0x00000010
90#define ALIAS_10BIT_IO 0x00000020
91#define SB_DMA_MASK 0x000000C0
92#define SB_DMA_0 0x00000040
93#define SB_DMA_1 0x00000040
94#define SB_DMA_R 0x00000080
95#define SB_DMA_3 0x000000C0
96#define SB_IRQ_MASK 0x00000700
97#define SB_IRQ_5 0x00000000
98#define SB_IRQ_7 0x00000100
99#define SB_IRQ_9 0x00000200
100#define SB_IRQ_10 0x00000300
101#define MIDI_IRQ_MASK 0x00003800
102#define SERIAL_IRQ_ENABLE 0x00004000
103#define DISABLE_LEGACY 0x00008000
104
105#define PCI_ALLEGRO_CONFIG 0x50
106#define SB_ADDR_240 0x00000004
107#define MPU_ADDR_MASK 0x00000018
108#define MPU_ADDR_330 0x00000000
109#define MPU_ADDR_300 0x00000008
110#define MPU_ADDR_320 0x00000010
111#define MPU_ADDR_340 0x00000018
112#define USE_PCI_TIMING 0x00000040
113#define POSTED_WRITE_ENABLE 0x00000080
114#define DMA_POLICY_MASK 0x00000700
115#define DMA_DDMA 0x00000000
116#define DMA_TDMA 0x00000100
117#define DMA_PCPCI 0x00000200
118#define DMA_WBDMA16 0x00000400
119#define DMA_WBDMA4 0x00000500
120#define DMA_WBDMA2 0x00000600
121#define DMA_WBDMA1 0x00000700
122#define DMA_SAFE_GUARD 0x00000800
123#define HI_PERF_GP_ENABLE 0x00001000
124#define PIC_SNOOP_MODE_0 0x00002000
125#define PIC_SNOOP_MODE_1 0x00004000
126#define SOUNDBLASTER_IRQ_MASK 0x00008000
127#define RING_IN_ENABLE 0x00010000
128#define SPDIF_TEST_MODE 0x00020000
129#define CLK_MULT_MODE_SELECT_2 0x00040000
130#define EEPROM_WRITE_ENABLE 0x00080000
131#define CODEC_DIR_IN 0x00100000
132#define HV_BUTTON_FROM_GD 0x00200000
133#define REDUCED_DEBOUNCE 0x00400000
134#define HV_CTRL_ENABLE 0x00800000
135#define SPDIF_ENABLE 0x01000000
136#define CLK_DIV_SELECT 0x06000000
137#define CLK_DIV_BY_48 0x00000000
138#define CLK_DIV_BY_49 0x02000000
139#define CLK_DIV_BY_50 0x04000000
140#define CLK_DIV_RESERVED 0x06000000
141#define PM_CTRL_ENABLE 0x08000000
142#define CLK_MULT_MODE_SELECT 0x30000000
143#define CLK_MULT_MODE_SHIFT 28
144#define CLK_MULT_MODE_0 0x00000000
145#define CLK_MULT_MODE_1 0x10000000
146#define CLK_MULT_MODE_2 0x20000000
147#define CLK_MULT_MODE_3 0x30000000
148#define INT_CLK_SELECT 0x40000000
149#define INT_CLK_MULT_RESET 0x80000000
150
151/* M3 */
152#define INT_CLK_SRC_NOT_PCI 0x00100000
153#define INT_CLK_MULT_ENABLE 0x80000000
154
155#define PCI_ACPI_CONTROL 0x54
156#define PCI_ACPI_D0 0x00000000
157#define PCI_ACPI_D1 0xB4F70000
158#define PCI_ACPI_D2 0xB4F7B4F7
159
160#define PCI_USER_CONFIG 0x58
161#define EXT_PCI_MASTER_ENABLE 0x00000001
162#define SPDIF_OUT_SELECT 0x00000002
163#define TEST_PIN_DIR_CTRL 0x00000004
164#define AC97_CODEC_TEST 0x00000020
165#define TRI_STATE_BUFFER 0x00000080
166#define IN_CLK_12MHZ_SELECT 0x00000100
167#define MULTI_FUNC_DISABLE 0x00000200
168#define EXT_MASTER_PAIR_SEL 0x00000400
169#define PCI_MASTER_SUPPORT 0x00000800
170#define STOP_CLOCK_ENABLE 0x00001000
171#define EAPD_DRIVE_ENABLE 0x00002000
172#define REQ_TRI_STATE_ENABLE 0x00004000
173#define REQ_LOW_ENABLE 0x00008000
174#define MIDI_1_ENABLE 0x00010000
175#define MIDI_2_ENABLE 0x00020000
176#define SB_AUDIO_SYNC 0x00040000
177#define HV_CTRL_TEST 0x00100000
178#define SOUNDBLASTER_TEST 0x00400000
179
180#define PCI_USER_CONFIG_C 0x5C
181
182#define PCI_DDMA_CTRL 0x60
183#define DDMA_ENABLE 0x00000001
184
185
186/* Allegro registers */
187#define HOST_INT_CTRL 0x18
188#define SB_INT_ENABLE 0x0001
189#define MPU401_INT_ENABLE 0x0002
190#define ASSP_INT_ENABLE 0x0010
191#define RING_INT_ENABLE 0x0020
192#define HV_INT_ENABLE 0x0040
193#define CLKRUN_GEN_ENABLE 0x0100
194#define HV_CTRL_TO_PME 0x0400
195#define SOFTWARE_RESET_ENABLE 0x8000
196
197/*
198 * should be using the above defines, probably.
199 */
200#define REGB_ENABLE_RESET 0x01
201#define REGB_STOP_CLOCK 0x10
202
203#define HOST_INT_STATUS 0x1A
204#define SB_INT_PENDING 0x01
205#define MPU401_INT_PENDING 0x02
206#define ASSP_INT_PENDING 0x10
207#define RING_INT_PENDING 0x20
208#define HV_INT_PENDING 0x40
209
210#define HARDWARE_VOL_CTRL 0x1B
211#define SHADOW_MIX_REG_VOICE 0x1C
212#define HW_VOL_COUNTER_VOICE 0x1D
213#define SHADOW_MIX_REG_MASTER 0x1E
214#define HW_VOL_COUNTER_MASTER 0x1F
215
216#define CODEC_COMMAND 0x30
217#define CODEC_READ_B 0x80
218
219#define CODEC_STATUS 0x30
220#define CODEC_BUSY_B 0x01
221
222#define CODEC_DATA 0x32
223
224#define RING_BUS_CTRL_A 0x36
225#define RAC_PME_ENABLE 0x0100
226#define RAC_SDFS_ENABLE 0x0200
227#define LAC_PME_ENABLE 0x0400
228#define LAC_SDFS_ENABLE 0x0800
229#define SERIAL_AC_LINK_ENABLE 0x1000
230#define IO_SRAM_ENABLE 0x2000
231#define IIS_INPUT_ENABLE 0x8000
232
233#define RING_BUS_CTRL_B 0x38
234#define SECOND_CODEC_ID_MASK 0x0003
235#define SPDIF_FUNC_ENABLE 0x0010
236#define SECOND_AC_ENABLE 0x0020
237#define SB_MODULE_INTF_ENABLE 0x0040
238#define SSPE_ENABLE 0x0040
239#define M3I_DOCK_ENABLE 0x0080
240
241#define SDO_OUT_DEST_CTRL 0x3A
242#define COMMAND_ADDR_OUT 0x0003
243#define PCM_LR_OUT_LOCAL 0x0000
244#define PCM_LR_OUT_REMOTE 0x0004
245#define PCM_LR_OUT_MUTE 0x0008
246#define PCM_LR_OUT_BOTH 0x000C
247#define LINE1_DAC_OUT_LOCAL 0x0000
248#define LINE1_DAC_OUT_REMOTE 0x0010
249#define LINE1_DAC_OUT_MUTE 0x0020
250#define LINE1_DAC_OUT_BOTH 0x0030
251#define PCM_CLS_OUT_LOCAL 0x0000
252#define PCM_CLS_OUT_REMOTE 0x0040
253#define PCM_CLS_OUT_MUTE 0x0080
254#define PCM_CLS_OUT_BOTH 0x00C0
255#define PCM_RLF_OUT_LOCAL 0x0000
256#define PCM_RLF_OUT_REMOTE 0x0100
257#define PCM_RLF_OUT_MUTE 0x0200
258#define PCM_RLF_OUT_BOTH 0x0300
259#define LINE2_DAC_OUT_LOCAL 0x0000
260#define LINE2_DAC_OUT_REMOTE 0x0400
261#define LINE2_DAC_OUT_MUTE 0x0800
262#define LINE2_DAC_OUT_BOTH 0x0C00
263#define HANDSET_OUT_LOCAL 0x0000
264#define HANDSET_OUT_REMOTE 0x1000
265#define HANDSET_OUT_MUTE 0x2000
266#define HANDSET_OUT_BOTH 0x3000
267#define IO_CTRL_OUT_LOCAL 0x0000
268#define IO_CTRL_OUT_REMOTE 0x4000
269#define IO_CTRL_OUT_MUTE 0x8000
270#define IO_CTRL_OUT_BOTH 0xC000
271
272#define SDO_IN_DEST_CTRL 0x3C
273#define STATUS_ADDR_IN 0x0003
274#define PCM_LR_IN_LOCAL 0x0000
275#define PCM_LR_IN_REMOTE 0x0004
276#define PCM_LR_RESERVED 0x0008
277#define PCM_LR_IN_BOTH 0x000C
278#define LINE1_ADC_IN_LOCAL 0x0000
279#define LINE1_ADC_IN_REMOTE 0x0010
280#define LINE1_ADC_IN_MUTE 0x0020
281#define MIC_ADC_IN_LOCAL 0x0000
282#define MIC_ADC_IN_REMOTE 0x0040
283#define MIC_ADC_IN_MUTE 0x0080
284#define LINE2_DAC_IN_LOCAL 0x0000
285#define LINE2_DAC_IN_REMOTE 0x0400
286#define LINE2_DAC_IN_MUTE 0x0800
287#define HANDSET_IN_LOCAL 0x0000
288#define HANDSET_IN_REMOTE 0x1000
289#define HANDSET_IN_MUTE 0x2000
290#define IO_STATUS_IN_LOCAL 0x0000
291#define IO_STATUS_IN_REMOTE 0x4000
292
293#define SPDIF_IN_CTRL 0x3E
294#define SPDIF_IN_ENABLE 0x0001
295
296#define GPIO_DATA 0x60
297#define GPIO_DATA_MASK 0x0FFF
298#define GPIO_HV_STATUS 0x3000
299#define GPIO_PME_STATUS 0x4000
300
301#define GPIO_MASK 0x64
302#define GPIO_DIRECTION 0x68
303#define GPO_PRIMARY_AC97 0x0001
304#define GPI_LINEOUT_SENSE 0x0004
305#define GPO_SECONDARY_AC97 0x0008
306#define GPI_VOL_DOWN 0x0010
307#define GPI_VOL_UP 0x0020
308#define GPI_IIS_CLK 0x0040
309#define GPI_IIS_LRCLK 0x0080
310#define GPI_IIS_DATA 0x0100
311#define GPI_DOCKING_STATUS 0x0100
312#define GPI_HEADPHONE_SENSE 0x0200
313#define GPO_EXT_AMP_SHUTDOWN 0x1000
314
315#define GPO_EXT_AMP_M3 1 /* default m3 amp */
316#define GPO_EXT_AMP_ALLEGRO 8 /* default allegro amp */
317
318/* M3 */
319#define GPO_M3_EXT_AMP_SHUTDN 0x0002
320
321#define ASSP_INDEX_PORT 0x80
322#define ASSP_MEMORY_PORT 0x82
323#define ASSP_DATA_PORT 0x84
324
325#define MPU401_DATA_PORT 0x98
326#define MPU401_STATUS_PORT 0x99
327
328#define CLK_MULT_DATA_PORT 0x9C
329
330#define ASSP_CONTROL_A 0xA2
331#define ASSP_0_WS_ENABLE 0x01
332#define ASSP_CTRL_A_RESERVED1 0x02
333#define ASSP_CTRL_A_RESERVED2 0x04
334#define ASSP_CLK_49MHZ_SELECT 0x08
335#define FAST_PLU_ENABLE 0x10
336#define ASSP_CTRL_A_RESERVED3 0x20
337#define DSP_CLK_36MHZ_SELECT 0x40
338
339#define ASSP_CONTROL_B 0xA4
340#define RESET_ASSP 0x00
341#define RUN_ASSP 0x01
342#define ENABLE_ASSP_CLOCK 0x00
343#define STOP_ASSP_CLOCK 0x10
344#define RESET_TOGGLE 0x40
345
346#define ASSP_CONTROL_C 0xA6
347#define ASSP_HOST_INT_ENABLE 0x01
348#define FM_ADDR_REMAP_DISABLE 0x02
349#define HOST_WRITE_PORT_ENABLE 0x08
350
351#define ASSP_HOST_INT_STATUS 0xAC
352#define DSP2HOST_REQ_PIORECORD 0x01
353#define DSP2HOST_REQ_I2SRATE 0x02
354#define DSP2HOST_REQ_TIMER 0x04
355
356/*
357 * ASSP control regs
358 */
359#define DSP_PORT_TIMER_COUNT 0x06
360
361#define DSP_PORT_MEMORY_INDEX 0x80
362
363#define DSP_PORT_MEMORY_TYPE 0x82
364#define MEMTYPE_INTERNAL_CODE 0x0002
365#define MEMTYPE_INTERNAL_DATA 0x0003
366#define MEMTYPE_MASK 0x0003
367
368#define DSP_PORT_MEMORY_DATA 0x84
369
370#define DSP_PORT_CONTROL_REG_A 0xA2
371#define DSP_PORT_CONTROL_REG_B 0xA4
372#define DSP_PORT_CONTROL_REG_C 0xA6
373
374#define REV_A_CODE_MEMORY_BEGIN 0x0000
375#define REV_A_CODE_MEMORY_END 0x0FFF
376#define REV_A_CODE_MEMORY_UNIT_LENGTH 0x0040
377#define REV_A_CODE_MEMORY_LENGTH (REV_A_CODE_MEMORY_END - REV_A_CODE_MEMORY_BEGIN + 1)
378
379#define REV_B_CODE_MEMORY_BEGIN 0x0000
380#define REV_B_CODE_MEMORY_END 0x0BFF
381#define REV_B_CODE_MEMORY_UNIT_LENGTH 0x0040
382#define REV_B_CODE_MEMORY_LENGTH (REV_B_CODE_MEMORY_END - REV_B_CODE_MEMORY_BEGIN + 1)
383
384#define REV_A_DATA_MEMORY_BEGIN 0x1000
385#define REV_A_DATA_MEMORY_END 0x2FFF
386#define REV_A_DATA_MEMORY_UNIT_LENGTH 0x0080
387#define REV_A_DATA_MEMORY_LENGTH (REV_A_DATA_MEMORY_END - REV_A_DATA_MEMORY_BEGIN + 1)
388
389#define REV_B_DATA_MEMORY_BEGIN 0x1000
390#define REV_B_DATA_MEMORY_END 0x2BFF
391#define REV_B_DATA_MEMORY_UNIT_LENGTH 0x0080
392#define REV_B_DATA_MEMORY_LENGTH (REV_B_DATA_MEMORY_END - REV_B_DATA_MEMORY_BEGIN + 1)
393
394
395#define NUM_UNITS_KERNEL_CODE 16
396#define NUM_UNITS_KERNEL_DATA 2
397
398#define NUM_UNITS_KERNEL_CODE_WITH_HSP 16
399#define NUM_UNITS_KERNEL_DATA_WITH_HSP 5
400
401/*
402 * Kernel data layout
403 */
404
405#define DP_SHIFT_COUNT 7
406
407#define KDATA_BASE_ADDR 0x1000
408#define KDATA_BASE_ADDR2 0x1080
409
410#define KDATA_TASK0 (KDATA_BASE_ADDR + 0x0000)
411#define KDATA_TASK1 (KDATA_BASE_ADDR + 0x0001)
412#define KDATA_TASK2 (KDATA_BASE_ADDR + 0x0002)
413#define KDATA_TASK3 (KDATA_BASE_ADDR + 0x0003)
414#define KDATA_TASK4 (KDATA_BASE_ADDR + 0x0004)
415#define KDATA_TASK5 (KDATA_BASE_ADDR + 0x0005)
416#define KDATA_TASK6 (KDATA_BASE_ADDR + 0x0006)
417#define KDATA_TASK7 (KDATA_BASE_ADDR + 0x0007)
418#define KDATA_TASK_ENDMARK (KDATA_BASE_ADDR + 0x0008)
419
420#define KDATA_CURRENT_TASK (KDATA_BASE_ADDR + 0x0009)
421#define KDATA_TASK_SWITCH (KDATA_BASE_ADDR + 0x000A)
422
423#define KDATA_INSTANCE0_POS3D (KDATA_BASE_ADDR + 0x000B)
424#define KDATA_INSTANCE1_POS3D (KDATA_BASE_ADDR + 0x000C)
425#define KDATA_INSTANCE2_POS3D (KDATA_BASE_ADDR + 0x000D)
426#define KDATA_INSTANCE3_POS3D (KDATA_BASE_ADDR + 0x000E)
427#define KDATA_INSTANCE4_POS3D (KDATA_BASE_ADDR + 0x000F)
428#define KDATA_INSTANCE5_POS3D (KDATA_BASE_ADDR + 0x0010)
429#define KDATA_INSTANCE6_POS3D (KDATA_BASE_ADDR + 0x0011)
430#define KDATA_INSTANCE7_POS3D (KDATA_BASE_ADDR + 0x0012)
431#define KDATA_INSTANCE8_POS3D (KDATA_BASE_ADDR + 0x0013)
432#define KDATA_INSTANCE_POS3D_ENDMARK (KDATA_BASE_ADDR + 0x0014)
433
434#define KDATA_INSTANCE0_SPKVIRT (KDATA_BASE_ADDR + 0x0015)
435#define KDATA_INSTANCE_SPKVIRT_ENDMARK (KDATA_BASE_ADDR + 0x0016)
436
437#define KDATA_INSTANCE0_SPDIF (KDATA_BASE_ADDR + 0x0017)
438#define KDATA_INSTANCE_SPDIF_ENDMARK (KDATA_BASE_ADDR + 0x0018)
439
440#define KDATA_INSTANCE0_MODEM (KDATA_BASE_ADDR + 0x0019)
441#define KDATA_INSTANCE_MODEM_ENDMARK (KDATA_BASE_ADDR + 0x001A)
442
443#define KDATA_INSTANCE0_SRC (KDATA_BASE_ADDR + 0x001B)
444#define KDATA_INSTANCE1_SRC (KDATA_BASE_ADDR + 0x001C)
445#define KDATA_INSTANCE_SRC_ENDMARK (KDATA_BASE_ADDR + 0x001D)
446
447#define KDATA_INSTANCE0_MINISRC (KDATA_BASE_ADDR + 0x001E)
448#define KDATA_INSTANCE1_MINISRC (KDATA_BASE_ADDR + 0x001F)
449#define KDATA_INSTANCE2_MINISRC (KDATA_BASE_ADDR + 0x0020)
450#define KDATA_INSTANCE3_MINISRC (KDATA_BASE_ADDR + 0x0021)
451#define KDATA_INSTANCE_MINISRC_ENDMARK (KDATA_BASE_ADDR + 0x0022)
452
453#define KDATA_INSTANCE0_CPYTHRU (KDATA_BASE_ADDR + 0x0023)
454#define KDATA_INSTANCE1_CPYTHRU (KDATA_BASE_ADDR + 0x0024)
455#define KDATA_INSTANCE_CPYTHRU_ENDMARK (KDATA_BASE_ADDR + 0x0025)
456
457#define KDATA_CURRENT_DMA (KDATA_BASE_ADDR + 0x0026)
458#define KDATA_DMA_SWITCH (KDATA_BASE_ADDR + 0x0027)
459#define KDATA_DMA_ACTIVE (KDATA_BASE_ADDR + 0x0028)
460
461#define KDATA_DMA_XFER0 (KDATA_BASE_ADDR + 0x0029)
462#define KDATA_DMA_XFER1 (KDATA_BASE_ADDR + 0x002A)
463#define KDATA_DMA_XFER2 (KDATA_BASE_ADDR + 0x002B)
464#define KDATA_DMA_XFER3 (KDATA_BASE_ADDR + 0x002C)
465#define KDATA_DMA_XFER4 (KDATA_BASE_ADDR + 0x002D)
466#define KDATA_DMA_XFER5 (KDATA_BASE_ADDR + 0x002E)
467#define KDATA_DMA_XFER6 (KDATA_BASE_ADDR + 0x002F)
468#define KDATA_DMA_XFER7 (KDATA_BASE_ADDR + 0x0030)
469#define KDATA_DMA_XFER8 (KDATA_BASE_ADDR + 0x0031)
470#define KDATA_DMA_XFER_ENDMARK (KDATA_BASE_ADDR + 0x0032)
471
472#define KDATA_I2S_SAMPLE_COUNT (KDATA_BASE_ADDR + 0x0033)
473#define KDATA_I2S_INT_METER (KDATA_BASE_ADDR + 0x0034)
474#define KDATA_I2S_ACTIVE (KDATA_BASE_ADDR + 0x0035)
475
476#define KDATA_TIMER_COUNT_RELOAD (KDATA_BASE_ADDR + 0x0036)
477#define KDATA_TIMER_COUNT_CURRENT (KDATA_BASE_ADDR + 0x0037)
478
479#define KDATA_HALT_SYNCH_CLIENT (KDATA_BASE_ADDR + 0x0038)
480#define KDATA_HALT_SYNCH_DMA (KDATA_BASE_ADDR + 0x0039)
481#define KDATA_HALT_ACKNOWLEDGE (KDATA_BASE_ADDR + 0x003A)
482
483#define KDATA_ADC1_XFER0 (KDATA_BASE_ADDR + 0x003B)
484#define KDATA_ADC1_XFER_ENDMARK (KDATA_BASE_ADDR + 0x003C)
485#define KDATA_ADC1_LEFT_VOLUME (KDATA_BASE_ADDR + 0x003D)
486#define KDATA_ADC1_RIGHT_VOLUME (KDATA_BASE_ADDR + 0x003E)
487#define KDATA_ADC1_LEFT_SUR_VOL (KDATA_BASE_ADDR + 0x003F)
488#define KDATA_ADC1_RIGHT_SUR_VOL (KDATA_BASE_ADDR + 0x0040)
489
490#define KDATA_ADC2_XFER0 (KDATA_BASE_ADDR + 0x0041)
491#define KDATA_ADC2_XFER_ENDMARK (KDATA_BASE_ADDR + 0x0042)
492#define KDATA_ADC2_LEFT_VOLUME (KDATA_BASE_ADDR + 0x0043)
493#define KDATA_ADC2_RIGHT_VOLUME (KDATA_BASE_ADDR + 0x0044)
494#define KDATA_ADC2_LEFT_SUR_VOL (KDATA_BASE_ADDR + 0x0045)
495#define KDATA_ADC2_RIGHT_SUR_VOL (KDATA_BASE_ADDR + 0x0046)
496
497#define KDATA_CD_XFER0 (KDATA_BASE_ADDR + 0x0047)
498#define KDATA_CD_XFER_ENDMARK (KDATA_BASE_ADDR + 0x0048)
499#define KDATA_CD_LEFT_VOLUME (KDATA_BASE_ADDR + 0x0049)
500#define KDATA_CD_RIGHT_VOLUME (KDATA_BASE_ADDR + 0x004A)
501#define KDATA_CD_LEFT_SUR_VOL (KDATA_BASE_ADDR + 0x004B)
502#define KDATA_CD_RIGHT_SUR_VOL (KDATA_BASE_ADDR + 0x004C)
503
504#define KDATA_MIC_XFER0 (KDATA_BASE_ADDR + 0x004D)
505#define KDATA_MIC_XFER_ENDMARK (KDATA_BASE_ADDR + 0x004E)
506#define KDATA_MIC_VOLUME (KDATA_BASE_ADDR + 0x004F)
507#define KDATA_MIC_SUR_VOL (KDATA_BASE_ADDR + 0x0050)
508
509#define KDATA_I2S_XFER0 (KDATA_BASE_ADDR + 0x0051)
510#define KDATA_I2S_XFER_ENDMARK (KDATA_BASE_ADDR + 0x0052)
511
512#define KDATA_CHI_XFER0 (KDATA_BASE_ADDR + 0x0053)
513#define KDATA_CHI_XFER_ENDMARK (KDATA_BASE_ADDR + 0x0054)
514
515#define KDATA_SPDIF_XFER (KDATA_BASE_ADDR + 0x0055)
516#define KDATA_SPDIF_CURRENT_FRAME (KDATA_BASE_ADDR + 0x0056)
517#define KDATA_SPDIF_FRAME0 (KDATA_BASE_ADDR + 0x0057)
518#define KDATA_SPDIF_FRAME1 (KDATA_BASE_ADDR + 0x0058)
519#define KDATA_SPDIF_FRAME2 (KDATA_BASE_ADDR + 0x0059)
520
521#define KDATA_SPDIF_REQUEST (KDATA_BASE_ADDR + 0x005A)
522#define KDATA_SPDIF_TEMP (KDATA_BASE_ADDR + 0x005B)
523
524#define KDATA_SPDIFIN_XFER0 (KDATA_BASE_ADDR + 0x005C)
525#define KDATA_SPDIFIN_XFER_ENDMARK (KDATA_BASE_ADDR + 0x005D)
526#define KDATA_SPDIFIN_INT_METER (KDATA_BASE_ADDR + 0x005E)
527
528#define KDATA_DSP_RESET_COUNT (KDATA_BASE_ADDR + 0x005F)
529#define KDATA_DEBUG_OUTPUT (KDATA_BASE_ADDR + 0x0060)
530
531#define KDATA_KERNEL_ISR_LIST (KDATA_BASE_ADDR + 0x0061)
532
533#define KDATA_KERNEL_ISR_CBSR1 (KDATA_BASE_ADDR + 0x0062)
534#define KDATA_KERNEL_ISR_CBER1 (KDATA_BASE_ADDR + 0x0063)
535#define KDATA_KERNEL_ISR_CBCR (KDATA_BASE_ADDR + 0x0064)
536#define KDATA_KERNEL_ISR_AR0 (KDATA_BASE_ADDR + 0x0065)
537#define KDATA_KERNEL_ISR_AR1 (KDATA_BASE_ADDR + 0x0066)
538#define KDATA_KERNEL_ISR_AR2 (KDATA_BASE_ADDR + 0x0067)
539#define KDATA_KERNEL_ISR_AR3 (KDATA_BASE_ADDR + 0x0068)
540#define KDATA_KERNEL_ISR_AR4 (KDATA_BASE_ADDR + 0x0069)
541#define KDATA_KERNEL_ISR_AR5 (KDATA_BASE_ADDR + 0x006A)
542#define KDATA_KERNEL_ISR_BRCR (KDATA_BASE_ADDR + 0x006B)
543#define KDATA_KERNEL_ISR_PASR (KDATA_BASE_ADDR + 0x006C)
544#define KDATA_KERNEL_ISR_PAER (KDATA_BASE_ADDR + 0x006D)
545
546#define KDATA_CLIENT_SCRATCH0 (KDATA_BASE_ADDR + 0x006E)
547#define KDATA_CLIENT_SCRATCH1 (KDATA_BASE_ADDR + 0x006F)
548#define KDATA_KERNEL_SCRATCH (KDATA_BASE_ADDR + 0x0070)
549#define KDATA_KERNEL_ISR_SCRATCH (KDATA_BASE_ADDR + 0x0071)
550
551#define KDATA_OUEUE_LEFT (KDATA_BASE_ADDR + 0x0072)
552#define KDATA_QUEUE_RIGHT (KDATA_BASE_ADDR + 0x0073)
553
554#define KDATA_ADC1_REQUEST (KDATA_BASE_ADDR + 0x0074)
555#define KDATA_ADC2_REQUEST (KDATA_BASE_ADDR + 0x0075)
556#define KDATA_CD_REQUEST (KDATA_BASE_ADDR + 0x0076)
557#define KDATA_MIC_REQUEST (KDATA_BASE_ADDR + 0x0077)
558
559#define KDATA_ADC1_MIXER_REQUEST (KDATA_BASE_ADDR + 0x0078)
560#define KDATA_ADC2_MIXER_REQUEST (KDATA_BASE_ADDR + 0x0079)
561#define KDATA_CD_MIXER_REQUEST (KDATA_BASE_ADDR + 0x007A)
562#define KDATA_MIC_MIXER_REQUEST (KDATA_BASE_ADDR + 0x007B)
563#define KDATA_MIC_SYNC_COUNTER (KDATA_BASE_ADDR + 0x007C)
564
565/*
566 * second 'segment' (?) reserved for mixer
567 * buffers..
568 */
569
570#define KDATA_MIXER_WORD0 (KDATA_BASE_ADDR2 + 0x0000)
571#define KDATA_MIXER_WORD1 (KDATA_BASE_ADDR2 + 0x0001)
572#define KDATA_MIXER_WORD2 (KDATA_BASE_ADDR2 + 0x0002)
573#define KDATA_MIXER_WORD3 (KDATA_BASE_ADDR2 + 0x0003)
574#define KDATA_MIXER_WORD4 (KDATA_BASE_ADDR2 + 0x0004)
575#define KDATA_MIXER_WORD5 (KDATA_BASE_ADDR2 + 0x0005)
576#define KDATA_MIXER_WORD6 (KDATA_BASE_ADDR2 + 0x0006)
577#define KDATA_MIXER_WORD7 (KDATA_BASE_ADDR2 + 0x0007)
578#define KDATA_MIXER_WORD8 (KDATA_BASE_ADDR2 + 0x0008)
579#define KDATA_MIXER_WORD9 (KDATA_BASE_ADDR2 + 0x0009)
580#define KDATA_MIXER_WORDA (KDATA_BASE_ADDR2 + 0x000A)
581#define KDATA_MIXER_WORDB (KDATA_BASE_ADDR2 + 0x000B)
582#define KDATA_MIXER_WORDC (KDATA_BASE_ADDR2 + 0x000C)
583#define KDATA_MIXER_WORDD (KDATA_BASE_ADDR2 + 0x000D)
584#define KDATA_MIXER_WORDE (KDATA_BASE_ADDR2 + 0x000E)
585#define KDATA_MIXER_WORDF (KDATA_BASE_ADDR2 + 0x000F)
586
587#define KDATA_MIXER_XFER0 (KDATA_BASE_ADDR2 + 0x0010)
588#define KDATA_MIXER_XFER1 (KDATA_BASE_ADDR2 + 0x0011)
589#define KDATA_MIXER_XFER2 (KDATA_BASE_ADDR2 + 0x0012)
590#define KDATA_MIXER_XFER3 (KDATA_BASE_ADDR2 + 0x0013)
591#define KDATA_MIXER_XFER4 (KDATA_BASE_ADDR2 + 0x0014)
592#define KDATA_MIXER_XFER5 (KDATA_BASE_ADDR2 + 0x0015)
593#define KDATA_MIXER_XFER6 (KDATA_BASE_ADDR2 + 0x0016)
594#define KDATA_MIXER_XFER7 (KDATA_BASE_ADDR2 + 0x0017)
595#define KDATA_MIXER_XFER8 (KDATA_BASE_ADDR2 + 0x0018)
596#define KDATA_MIXER_XFER9 (KDATA_BASE_ADDR2 + 0x0019)
597#define KDATA_MIXER_XFER_ENDMARK (KDATA_BASE_ADDR2 + 0x001A)
598
599#define KDATA_MIXER_TASK_NUMBER (KDATA_BASE_ADDR2 + 0x001B)
600#define KDATA_CURRENT_MIXER (KDATA_BASE_ADDR2 + 0x001C)
601#define KDATA_MIXER_ACTIVE (KDATA_BASE_ADDR2 + 0x001D)
602#define KDATA_MIXER_BANK_STATUS (KDATA_BASE_ADDR2 + 0x001E)
603#define KDATA_DAC_LEFT_VOLUME (KDATA_BASE_ADDR2 + 0x001F)
604#define KDATA_DAC_RIGHT_VOLUME (KDATA_BASE_ADDR2 + 0x0020)
605
606#define MAX_INSTANCE_MINISRC (KDATA_INSTANCE_MINISRC_ENDMARK - KDATA_INSTANCE0_MINISRC)
607#define MAX_VIRTUAL_DMA_CHANNELS (KDATA_DMA_XFER_ENDMARK - KDATA_DMA_XFER0)
608#define MAX_VIRTUAL_MIXER_CHANNELS (KDATA_MIXER_XFER_ENDMARK - KDATA_MIXER_XFER0)
609#define MAX_VIRTUAL_ADC1_CHANNELS (KDATA_ADC1_XFER_ENDMARK - KDATA_ADC1_XFER0)
610
611/*
612 * client data area offsets
613 */
614#define CDATA_INSTANCE_READY 0x00
615
616#define CDATA_HOST_SRC_ADDRL 0x01
617#define CDATA_HOST_SRC_ADDRH 0x02
618#define CDATA_HOST_SRC_END_PLUS_1L 0x03
619#define CDATA_HOST_SRC_END_PLUS_1H 0x04
620#define CDATA_HOST_SRC_CURRENTL 0x05
621#define CDATA_HOST_SRC_CURRENTH 0x06
622
623#define CDATA_IN_BUF_CONNECT 0x07
624#define CDATA_OUT_BUF_CONNECT 0x08
625
626#define CDATA_IN_BUF_BEGIN 0x09
627#define CDATA_IN_BUF_END_PLUS_1 0x0A
628#define CDATA_IN_BUF_HEAD 0x0B
629#define CDATA_IN_BUF_TAIL 0x0C
630#define CDATA_OUT_BUF_BEGIN 0x0D
631#define CDATA_OUT_BUF_END_PLUS_1 0x0E
632#define CDATA_OUT_BUF_HEAD 0x0F
633#define CDATA_OUT_BUF_TAIL 0x10
634
635#define CDATA_DMA_CONTROL 0x11
636#define CDATA_RESERVED 0x12
637
638#define CDATA_FREQUENCY 0x13
639#define CDATA_LEFT_VOLUME 0x14
640#define CDATA_RIGHT_VOLUME 0x15
641#define CDATA_LEFT_SUR_VOL 0x16
642#define CDATA_RIGHT_SUR_VOL 0x17
643
644#define CDATA_HEADER_LEN 0x18
645
646#define SRC3_DIRECTION_OFFSET CDATA_HEADER_LEN
647#define SRC3_MODE_OFFSET (CDATA_HEADER_LEN + 1)
648#define SRC3_WORD_LENGTH_OFFSET (CDATA_HEADER_LEN + 2)
649#define SRC3_PARAMETER_OFFSET (CDATA_HEADER_LEN + 3)
650#define SRC3_COEFF_ADDR_OFFSET (CDATA_HEADER_LEN + 8)
651#define SRC3_FILTAP_ADDR_OFFSET (CDATA_HEADER_LEN + 10)
652#define SRC3_TEMP_INBUF_ADDR_OFFSET (CDATA_HEADER_LEN + 16)
653#define SRC3_TEMP_OUTBUF_ADDR_OFFSET (CDATA_HEADER_LEN + 17)
654
655#define MINISRC_IN_BUFFER_SIZE ( 0x50 * 2 )
656#define MINISRC_OUT_BUFFER_SIZE ( 0x50 * 2 * 2)
657#define MINISRC_TMP_BUFFER_SIZE ( 112 + ( MINISRC_BIQUAD_STAGE * 3 + 4 ) * 2 * 2 )
658#define MINISRC_BIQUAD_STAGE 2
659#define MINISRC_COEF_LOC 0x175
660
661#define DMACONTROL_BLOCK_MASK 0x000F
662#define DMAC_BLOCK0_SELECTOR 0x0000
663#define DMAC_BLOCK1_SELECTOR 0x0001
664#define DMAC_BLOCK2_SELECTOR 0x0002
665#define DMAC_BLOCK3_SELECTOR 0x0003
666#define DMAC_BLOCK4_SELECTOR 0x0004
667#define DMAC_BLOCK5_SELECTOR 0x0005
668#define DMAC_BLOCK6_SELECTOR 0x0006
669#define DMAC_BLOCK7_SELECTOR 0x0007
670#define DMAC_BLOCK8_SELECTOR 0x0008
671#define DMAC_BLOCK9_SELECTOR 0x0009
672#define DMAC_BLOCKA_SELECTOR 0x000A
673#define DMAC_BLOCKB_SELECTOR 0x000B
674#define DMAC_BLOCKC_SELECTOR 0x000C
675#define DMAC_BLOCKD_SELECTOR 0x000D
676#define DMAC_BLOCKE_SELECTOR 0x000E
677#define DMAC_BLOCKF_SELECTOR 0x000F
678#define DMACONTROL_PAGE_MASK 0x00F0
679#define DMAC_PAGE0_SELECTOR 0x0030
680#define DMAC_PAGE1_SELECTOR 0x0020
681#define DMAC_PAGE2_SELECTOR 0x0010
682#define DMAC_PAGE3_SELECTOR 0x0000
683#define DMACONTROL_AUTOREPEAT 0x1000
684#define DMACONTROL_STOPPED 0x2000
685#define DMACONTROL_DIRECTION 0x0100
686
687/*
688 * an arbitrary volume we set the internal
689 * volume settings to so that the ac97 volume
690 * range is a little less insane. 0x7fff is
691 * max.
692 */
693#define ARB_VOLUME ( 0x6800 )
694
695/*
696 */
697
698struct m3_list {
699 int curlen;
700 int mem_addr;
701 int max;
702};
703
704struct m3_dma {
705
706 int number;
707 struct snd_pcm_substream *substream;
708
709 struct assp_instance {
710 unsigned short code, data;
711 } inst;
712
713 int running;
714 int opened;
715
716 unsigned long buffer_addr;
717 int dma_size;
718 int period_size;
719 unsigned int hwptr;
720 int count;
721
722 int index[3];
723 struct m3_list *index_list[3];
724
725 int in_lists;
726
727 struct list_head list;
728
729};
730
731struct snd_m3 {
732
733 struct snd_card *card;
734
735 unsigned long iobase;
736
737 int irq;
738 unsigned int allegro_flag : 1;
739
740 struct snd_ac97 *ac97;
741
742 struct snd_pcm *pcm;
743
744 struct pci_dev *pci;
745
746 int dacs_active;
747 int timer_users;
748
749 struct m3_list msrc_list;
750 struct m3_list mixer_list;
751 struct m3_list adc1_list;
752 struct m3_list dma_list;
753
754 /* for storing reset state..*/
755 u8 reset_state;
756
757 int external_amp;
758 int amp_gpio; /* gpio pin # for external amp, -1 = default */
759 unsigned int hv_config; /* hardware-volume config bits */
760 unsigned irda_workaround :1; /* avoid to touch 0x10 on GPIO_DIRECTION
761 (e.g. for IrDA on Dell Inspirons) */
762 unsigned is_omnibook :1; /* Do HP OmniBook GPIO magic? */
763
764 /* midi */
765 struct snd_rawmidi *rmidi;
766
767 /* pcm streams */
768 int num_substreams;
769 struct m3_dma *substreams;
770
771 spinlock_t reg_lock;
772
773#ifdef CONFIG_SND_MAESTRO3_INPUT
774 struct input_dev *input_dev;
775 char phys[64]; /* physical device path */
776#else
777 struct snd_kcontrol *master_switch;
778 struct snd_kcontrol *master_volume;
779#endif
780 struct work_struct hwvol_work;
781
782 unsigned int in_suspend;
783
784#ifdef CONFIG_PM_SLEEP
785 u16 *suspend_mem;
786#endif
787
788 const struct firmware *assp_kernel_image;
789 const struct firmware *assp_minisrc_image;
790};
791
792/*
793 * pci ids
794 */
795static const struct pci_device_id snd_m3_ids[] = {
796 {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_ALLEGRO_1, PCI_ANY_ID, PCI_ANY_ID,
797 PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
798 {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_ALLEGRO, PCI_ANY_ID, PCI_ANY_ID,
799 PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
800 {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_CANYON3D_2LE, PCI_ANY_ID, PCI_ANY_ID,
801 PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
802 {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_CANYON3D_2, PCI_ANY_ID, PCI_ANY_ID,
803 PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
804 {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_MAESTRO3, PCI_ANY_ID, PCI_ANY_ID,
805 PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
806 {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_MAESTRO3_1, PCI_ANY_ID, PCI_ANY_ID,
807 PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
808 {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_MAESTRO3_HW, PCI_ANY_ID, PCI_ANY_ID,
809 PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
810 {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_MAESTRO3_2, PCI_ANY_ID, PCI_ANY_ID,
811 PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
812 {0,},
813};
814
815MODULE_DEVICE_TABLE(pci, snd_m3_ids);
816
817static const struct snd_pci_quirk m3_amp_quirk_list[] = {
818 SND_PCI_QUIRK(0x0E11, 0x0094, "Compaq Evo N600c", 0x0c),
819 SND_PCI_QUIRK(0x10f7, 0x833e, "Panasonic CF-28", 0x0d),
820 SND_PCI_QUIRK(0x10f7, 0x833d, "Panasonic CF-72", 0x0d),
821 SND_PCI_QUIRK(0x1033, 0x80f1, "NEC LM800J/7", 0x03),
822 SND_PCI_QUIRK(0x1509, 0x1740, "LEGEND ZhaoYang 3100CF", 0x03),
823 {0} /* END */
824};
825
826static const struct snd_pci_quirk m3_irda_quirk_list[] = {
827 SND_PCI_QUIRK(0x1028, 0x00b0, "Dell Inspiron 4000", 1),
828 SND_PCI_QUIRK(0x1028, 0x00a4, "Dell Inspiron 8000", 1),
829 SND_PCI_QUIRK(0x1028, 0x00e6, "Dell Inspiron 8100", 1),
830 {0} /* END */
831};
832
833/* hardware volume quirks */
834static const struct snd_pci_quirk m3_hv_quirk_list[] = {
835 /* Allegro chips */
836 SND_PCI_QUIRK(0x0E11, 0x002E, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
837 SND_PCI_QUIRK(0x0E11, 0x0094, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
838 SND_PCI_QUIRK(0x0E11, 0xB112, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
839 SND_PCI_QUIRK(0x0E11, 0xB114, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
840 SND_PCI_QUIRK(0x103C, 0x0012, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
841 SND_PCI_QUIRK(0x103C, 0x0018, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
842 SND_PCI_QUIRK(0x103C, 0x001C, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
843 SND_PCI_QUIRK(0x103C, 0x001D, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
844 SND_PCI_QUIRK(0x103C, 0x001E, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
845 SND_PCI_QUIRK(0x107B, 0x3350, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
846 SND_PCI_QUIRK(0x10F7, 0x8338, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
847 SND_PCI_QUIRK(0x10F7, 0x833C, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
848 SND_PCI_QUIRK(0x10F7, 0x833D, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
849 SND_PCI_QUIRK(0x10F7, 0x833E, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
850 SND_PCI_QUIRK(0x10F7, 0x833F, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
851 SND_PCI_QUIRK(0x13BD, 0x1018, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
852 SND_PCI_QUIRK(0x13BD, 0x1019, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
853 SND_PCI_QUIRK(0x13BD, 0x101A, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
854 SND_PCI_QUIRK(0x14FF, 0x0F03, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
855 SND_PCI_QUIRK(0x14FF, 0x0F04, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
856 SND_PCI_QUIRK(0x14FF, 0x0F05, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
857 SND_PCI_QUIRK(0x156D, 0xB400, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
858 SND_PCI_QUIRK(0x156D, 0xB795, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
859 SND_PCI_QUIRK(0x156D, 0xB797, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
860 SND_PCI_QUIRK(0x156D, 0xC700, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
861 SND_PCI_QUIRK(0x1033, 0x80F1, NULL,
862 HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE),
863 SND_PCI_QUIRK(0x103C, 0x001A, NULL, /* HP OmniBook 6100 */
864 HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE),
865 SND_PCI_QUIRK(0x107B, 0x340A, NULL,
866 HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE),
867 SND_PCI_QUIRK(0x107B, 0x3450, NULL,
868 HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE),
869 SND_PCI_QUIRK(0x109F, 0x3134, NULL,
870 HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE),
871 SND_PCI_QUIRK(0x109F, 0x3161, NULL,
872 HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE),
873 SND_PCI_QUIRK(0x144D, 0x3280, NULL,
874 HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE),
875 SND_PCI_QUIRK(0x144D, 0x3281, NULL,
876 HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE),
877 SND_PCI_QUIRK(0x144D, 0xC002, NULL,
878 HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE),
879 SND_PCI_QUIRK(0x144D, 0xC003, NULL,
880 HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE),
881 SND_PCI_QUIRK(0x1509, 0x1740, NULL,
882 HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE),
883 SND_PCI_QUIRK(0x1610, 0x0010, NULL,
884 HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE),
885 SND_PCI_QUIRK(0x1042, 0x1042, NULL, HV_CTRL_ENABLE),
886 SND_PCI_QUIRK(0x107B, 0x9500, NULL, HV_CTRL_ENABLE),
887 SND_PCI_QUIRK(0x14FF, 0x0F06, NULL, HV_CTRL_ENABLE),
888 SND_PCI_QUIRK(0x1558, 0x8586, NULL, HV_CTRL_ENABLE),
889 SND_PCI_QUIRK(0x161F, 0x2011, NULL, HV_CTRL_ENABLE),
890 /* Maestro3 chips */
891 SND_PCI_QUIRK(0x103C, 0x000E, NULL, HV_CTRL_ENABLE),
892 SND_PCI_QUIRK(0x103C, 0x0010, NULL, HV_CTRL_ENABLE),
893 SND_PCI_QUIRK(0x103C, 0x0011, NULL, HV_CTRL_ENABLE),
894 SND_PCI_QUIRK(0x103C, 0x001B, NULL, HV_CTRL_ENABLE),
895 SND_PCI_QUIRK(0x104D, 0x80A6, NULL, HV_CTRL_ENABLE),
896 SND_PCI_QUIRK(0x104D, 0x80AA, NULL, HV_CTRL_ENABLE),
897 SND_PCI_QUIRK(0x107B, 0x5300, NULL, HV_CTRL_ENABLE),
898 SND_PCI_QUIRK(0x110A, 0x1998, NULL, HV_CTRL_ENABLE),
899 SND_PCI_QUIRK(0x13BD, 0x1015, NULL, HV_CTRL_ENABLE),
900 SND_PCI_QUIRK(0x13BD, 0x101C, NULL, HV_CTRL_ENABLE),
901 SND_PCI_QUIRK(0x13BD, 0x1802, NULL, HV_CTRL_ENABLE),
902 SND_PCI_QUIRK(0x1599, 0x0715, NULL, HV_CTRL_ENABLE),
903 SND_PCI_QUIRK(0x5643, 0x5643, NULL, HV_CTRL_ENABLE),
904 SND_PCI_QUIRK(0x144D, 0x3260, NULL, HV_CTRL_ENABLE | REDUCED_DEBOUNCE),
905 SND_PCI_QUIRK(0x144D, 0x3261, NULL, HV_CTRL_ENABLE | REDUCED_DEBOUNCE),
906 SND_PCI_QUIRK(0x144D, 0xC000, NULL, HV_CTRL_ENABLE | REDUCED_DEBOUNCE),
907 SND_PCI_QUIRK(0x144D, 0xC001, NULL, HV_CTRL_ENABLE | REDUCED_DEBOUNCE),
908 {0} /* END */
909};
910
911/* HP Omnibook quirks */
912static const struct snd_pci_quirk m3_omnibook_quirk_list[] = {
913 SND_PCI_QUIRK_ID(0x103c, 0x0010), /* HP OmniBook 6000 */
914 SND_PCI_QUIRK_ID(0x103c, 0x0011), /* HP OmniBook 500 */
915 {0} /* END */
916};
917
918/*
919 * lowlevel functions
920 */
921
922static inline void snd_m3_outw(struct snd_m3 *chip, u16 value, unsigned long reg)
923{
924 outw(value, chip->iobase + reg);
925}
926
927static inline u16 snd_m3_inw(struct snd_m3 *chip, unsigned long reg)
928{
929 return inw(chip->iobase + reg);
930}
931
932static inline void snd_m3_outb(struct snd_m3 *chip, u8 value, unsigned long reg)
933{
934 outb(value, chip->iobase + reg);
935}
936
937static inline u8 snd_m3_inb(struct snd_m3 *chip, unsigned long reg)
938{
939 return inb(chip->iobase + reg);
940}
941
942/*
943 * access 16bit words to the code or data regions of the dsp's memory.
944 * index addresses 16bit words.
945 */
946static u16 snd_m3_assp_read(struct snd_m3 *chip, u16 region, u16 index)
947{
948 snd_m3_outw(chip, region & MEMTYPE_MASK, DSP_PORT_MEMORY_TYPE);
949 snd_m3_outw(chip, index, DSP_PORT_MEMORY_INDEX);
950 return snd_m3_inw(chip, DSP_PORT_MEMORY_DATA);
951}
952
953static void snd_m3_assp_write(struct snd_m3 *chip, u16 region, u16 index, u16 data)
954{
955 snd_m3_outw(chip, region & MEMTYPE_MASK, DSP_PORT_MEMORY_TYPE);
956 snd_m3_outw(chip, index, DSP_PORT_MEMORY_INDEX);
957 snd_m3_outw(chip, data, DSP_PORT_MEMORY_DATA);
958}
959
960static void snd_m3_assp_halt(struct snd_m3 *chip)
961{
962 chip->reset_state = snd_m3_inb(chip, DSP_PORT_CONTROL_REG_B) & ~REGB_STOP_CLOCK;
963 msleep(10);
964 snd_m3_outb(chip, chip->reset_state & ~REGB_ENABLE_RESET, DSP_PORT_CONTROL_REG_B);
965}
966
967static void snd_m3_assp_continue(struct snd_m3 *chip)
968{
969 snd_m3_outb(chip, chip->reset_state | REGB_ENABLE_RESET, DSP_PORT_CONTROL_REG_B);
970}
971
972
973/*
974 * This makes me sad. the maestro3 has lists
975 * internally that must be packed.. 0 terminates,
976 * apparently, or maybe all unused entries have
977 * to be 0, the lists have static lengths set
978 * by the binary code images.
979 */
980
981static int snd_m3_add_list(struct snd_m3 *chip, struct m3_list *list, u16 val)
982{
983 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
984 list->mem_addr + list->curlen,
985 val);
986 return list->curlen++;
987}
988
989static void snd_m3_remove_list(struct snd_m3 *chip, struct m3_list *list, int index)
990{
991 u16 val;
992 int lastindex = list->curlen - 1;
993
994 if (index != lastindex) {
995 val = snd_m3_assp_read(chip, MEMTYPE_INTERNAL_DATA,
996 list->mem_addr + lastindex);
997 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
998 list->mem_addr + index,
999 val);
1000 }
1001
1002 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1003 list->mem_addr + lastindex,
1004 0);
1005
1006 list->curlen--;
1007}
1008
1009static void snd_m3_inc_timer_users(struct snd_m3 *chip)
1010{
1011 chip->timer_users++;
1012 if (chip->timer_users != 1)
1013 return;
1014
1015 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1016 KDATA_TIMER_COUNT_RELOAD,
1017 240);
1018
1019 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1020 KDATA_TIMER_COUNT_CURRENT,
1021 240);
1022
1023 snd_m3_outw(chip,
1024 snd_m3_inw(chip, HOST_INT_CTRL) | CLKRUN_GEN_ENABLE,
1025 HOST_INT_CTRL);
1026}
1027
1028static void snd_m3_dec_timer_users(struct snd_m3 *chip)
1029{
1030 chip->timer_users--;
1031 if (chip->timer_users > 0)
1032 return;
1033
1034 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1035 KDATA_TIMER_COUNT_RELOAD,
1036 0);
1037
1038 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1039 KDATA_TIMER_COUNT_CURRENT,
1040 0);
1041
1042 snd_m3_outw(chip,
1043 snd_m3_inw(chip, HOST_INT_CTRL) & ~CLKRUN_GEN_ENABLE,
1044 HOST_INT_CTRL);
1045}
1046
1047/*
1048 * start/stop
1049 */
1050
1051/* spinlock held! */
1052static int snd_m3_pcm_start(struct snd_m3 *chip, struct m3_dma *s,
1053 struct snd_pcm_substream *subs)
1054{
1055 if (! s || ! subs)
1056 return -EINVAL;
1057
1058 snd_m3_inc_timer_users(chip);
1059 switch (subs->stream) {
1060 case SNDRV_PCM_STREAM_PLAYBACK:
1061 chip->dacs_active++;
1062 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1063 s->inst.data + CDATA_INSTANCE_READY, 1);
1064 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1065 KDATA_MIXER_TASK_NUMBER,
1066 chip->dacs_active);
1067 break;
1068 case SNDRV_PCM_STREAM_CAPTURE:
1069 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1070 KDATA_ADC1_REQUEST, 1);
1071 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1072 s->inst.data + CDATA_INSTANCE_READY, 1);
1073 break;
1074 }
1075 return 0;
1076}
1077
1078/* spinlock held! */
1079static int snd_m3_pcm_stop(struct snd_m3 *chip, struct m3_dma *s,
1080 struct snd_pcm_substream *subs)
1081{
1082 if (! s || ! subs)
1083 return -EINVAL;
1084
1085 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1086 s->inst.data + CDATA_INSTANCE_READY, 0);
1087 snd_m3_dec_timer_users(chip);
1088 switch (subs->stream) {
1089 case SNDRV_PCM_STREAM_PLAYBACK:
1090 chip->dacs_active--;
1091 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1092 KDATA_MIXER_TASK_NUMBER,
1093 chip->dacs_active);
1094 break;
1095 case SNDRV_PCM_STREAM_CAPTURE:
1096 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1097 KDATA_ADC1_REQUEST, 0);
1098 break;
1099 }
1100 return 0;
1101}
1102
1103static int
1104snd_m3_pcm_trigger(struct snd_pcm_substream *subs, int cmd)
1105{
1106 struct snd_m3 *chip = snd_pcm_substream_chip(subs);
1107 struct m3_dma *s = subs->runtime->private_data;
1108 int err = -EINVAL;
1109
1110 if (snd_BUG_ON(!s))
1111 return -ENXIO;
1112
1113 spin_lock(&chip->reg_lock);
1114 switch (cmd) {
1115 case SNDRV_PCM_TRIGGER_START:
1116 case SNDRV_PCM_TRIGGER_RESUME:
1117 if (s->running)
1118 err = -EBUSY;
1119 else {
1120 s->running = 1;
1121 err = snd_m3_pcm_start(chip, s, subs);
1122 }
1123 break;
1124 case SNDRV_PCM_TRIGGER_STOP:
1125 case SNDRV_PCM_TRIGGER_SUSPEND:
1126 if (! s->running)
1127 err = 0; /* should return error? */
1128 else {
1129 s->running = 0;
1130 err = snd_m3_pcm_stop(chip, s, subs);
1131 }
1132 break;
1133 }
1134 spin_unlock(&chip->reg_lock);
1135 return err;
1136}
1137
1138/*
1139 * setup
1140 */
1141static void
1142snd_m3_pcm_setup1(struct snd_m3 *chip, struct m3_dma *s, struct snd_pcm_substream *subs)
1143{
1144 int dsp_in_size, dsp_out_size, dsp_in_buffer, dsp_out_buffer;
1145 struct snd_pcm_runtime *runtime = subs->runtime;
1146
1147 if (subs->stream == SNDRV_PCM_STREAM_PLAYBACK) {
1148 dsp_in_size = MINISRC_IN_BUFFER_SIZE - (0x20 * 2);
1149 dsp_out_size = MINISRC_OUT_BUFFER_SIZE - (0x20 * 2);
1150 } else {
1151 dsp_in_size = MINISRC_IN_BUFFER_SIZE - (0x10 * 2);
1152 dsp_out_size = MINISRC_OUT_BUFFER_SIZE - (0x10 * 2);
1153 }
1154 dsp_in_buffer = s->inst.data + (MINISRC_TMP_BUFFER_SIZE / 2);
1155 dsp_out_buffer = dsp_in_buffer + (dsp_in_size / 2) + 1;
1156
1157 s->dma_size = frames_to_bytes(runtime, runtime->buffer_size);
1158 s->period_size = frames_to_bytes(runtime, runtime->period_size);
1159 s->hwptr = 0;
1160 s->count = 0;
1161
1162#define LO(x) ((x) & 0xffff)
1163#define HI(x) LO((x) >> 16)
1164
1165 /* host dma buffer pointers */
1166 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1167 s->inst.data + CDATA_HOST_SRC_ADDRL,
1168 LO(s->buffer_addr));
1169
1170 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1171 s->inst.data + CDATA_HOST_SRC_ADDRH,
1172 HI(s->buffer_addr));
1173
1174 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1175 s->inst.data + CDATA_HOST_SRC_END_PLUS_1L,
1176 LO(s->buffer_addr + s->dma_size));
1177
1178 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1179 s->inst.data + CDATA_HOST_SRC_END_PLUS_1H,
1180 HI(s->buffer_addr + s->dma_size));
1181
1182 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1183 s->inst.data + CDATA_HOST_SRC_CURRENTL,
1184 LO(s->buffer_addr));
1185
1186 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1187 s->inst.data + CDATA_HOST_SRC_CURRENTH,
1188 HI(s->buffer_addr));
1189#undef LO
1190#undef HI
1191
1192 /* dsp buffers */
1193
1194 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1195 s->inst.data + CDATA_IN_BUF_BEGIN,
1196 dsp_in_buffer);
1197
1198 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1199 s->inst.data + CDATA_IN_BUF_END_PLUS_1,
1200 dsp_in_buffer + (dsp_in_size / 2));
1201
1202 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1203 s->inst.data + CDATA_IN_BUF_HEAD,
1204 dsp_in_buffer);
1205
1206 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1207 s->inst.data + CDATA_IN_BUF_TAIL,
1208 dsp_in_buffer);
1209
1210 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1211 s->inst.data + CDATA_OUT_BUF_BEGIN,
1212 dsp_out_buffer);
1213
1214 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1215 s->inst.data + CDATA_OUT_BUF_END_PLUS_1,
1216 dsp_out_buffer + (dsp_out_size / 2));
1217
1218 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1219 s->inst.data + CDATA_OUT_BUF_HEAD,
1220 dsp_out_buffer);
1221
1222 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1223 s->inst.data + CDATA_OUT_BUF_TAIL,
1224 dsp_out_buffer);
1225}
1226
1227static void snd_m3_pcm_setup2(struct snd_m3 *chip, struct m3_dma *s,
1228 struct snd_pcm_runtime *runtime)
1229{
1230 u32 freq;
1231
1232 /*
1233 * put us in the lists if we're not already there
1234 */
1235 if (! s->in_lists) {
1236 s->index[0] = snd_m3_add_list(chip, s->index_list[0],
1237 s->inst.data >> DP_SHIFT_COUNT);
1238 s->index[1] = snd_m3_add_list(chip, s->index_list[1],
1239 s->inst.data >> DP_SHIFT_COUNT);
1240 s->index[2] = snd_m3_add_list(chip, s->index_list[2],
1241 s->inst.data >> DP_SHIFT_COUNT);
1242 s->in_lists = 1;
1243 }
1244
1245 /* write to 'mono' word */
1246 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1247 s->inst.data + SRC3_DIRECTION_OFFSET + 1,
1248 runtime->channels == 2 ? 0 : 1);
1249 /* write to '8bit' word */
1250 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1251 s->inst.data + SRC3_DIRECTION_OFFSET + 2,
1252 snd_pcm_format_width(runtime->format) == 16 ? 0 : 1);
1253
1254 /* set up dac/adc rate */
1255 freq = ((runtime->rate << 15) + 24000 ) / 48000;
1256 if (freq)
1257 freq--;
1258
1259 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1260 s->inst.data + CDATA_FREQUENCY,
1261 freq);
1262}
1263
1264
1265static const struct play_vals {
1266 u16 addr, val;
1267} pv[] = {
1268 {CDATA_LEFT_VOLUME, ARB_VOLUME},
1269 {CDATA_RIGHT_VOLUME, ARB_VOLUME},
1270 {SRC3_DIRECTION_OFFSET, 0} ,
1271 /* +1, +2 are stereo/16 bit */
1272 {SRC3_DIRECTION_OFFSET + 3, 0x0000}, /* fraction? */
1273 {SRC3_DIRECTION_OFFSET + 4, 0}, /* first l */
1274 {SRC3_DIRECTION_OFFSET + 5, 0}, /* first r */
1275 {SRC3_DIRECTION_OFFSET + 6, 0}, /* second l */
1276 {SRC3_DIRECTION_OFFSET + 7, 0}, /* second r */
1277 {SRC3_DIRECTION_OFFSET + 8, 0}, /* delta l */
1278 {SRC3_DIRECTION_OFFSET + 9, 0}, /* delta r */
1279 {SRC3_DIRECTION_OFFSET + 10, 0x8000}, /* round */
1280 {SRC3_DIRECTION_OFFSET + 11, 0xFF00}, /* higher bute mark */
1281 {SRC3_DIRECTION_OFFSET + 13, 0}, /* temp0 */
1282 {SRC3_DIRECTION_OFFSET + 14, 0}, /* c fraction */
1283 {SRC3_DIRECTION_OFFSET + 15, 0}, /* counter */
1284 {SRC3_DIRECTION_OFFSET + 16, 8}, /* numin */
1285 {SRC3_DIRECTION_OFFSET + 17, 50*2}, /* numout */
1286 {SRC3_DIRECTION_OFFSET + 18, MINISRC_BIQUAD_STAGE - 1}, /* numstage */
1287 {SRC3_DIRECTION_OFFSET + 20, 0}, /* filtertap */
1288 {SRC3_DIRECTION_OFFSET + 21, 0} /* booster */
1289};
1290
1291
1292/* the mode passed should be already shifted and masked */
1293static void
1294snd_m3_playback_setup(struct snd_m3 *chip, struct m3_dma *s,
1295 struct snd_pcm_substream *subs)
1296{
1297 unsigned int i;
1298
1299 /*
1300 * some per client initializers
1301 */
1302
1303 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1304 s->inst.data + SRC3_DIRECTION_OFFSET + 12,
1305 s->inst.data + 40 + 8);
1306
1307 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1308 s->inst.data + SRC3_DIRECTION_OFFSET + 19,
1309 s->inst.code + MINISRC_COEF_LOC);
1310
1311 /* enable or disable low pass filter? */
1312 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1313 s->inst.data + SRC3_DIRECTION_OFFSET + 22,
1314 subs->runtime->rate > 45000 ? 0xff : 0);
1315
1316 /* tell it which way dma is going? */
1317 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1318 s->inst.data + CDATA_DMA_CONTROL,
1319 DMACONTROL_AUTOREPEAT + DMAC_PAGE3_SELECTOR + DMAC_BLOCKF_SELECTOR);
1320
1321 /*
1322 * set an armload of static initializers
1323 */
1324 for (i = 0; i < ARRAY_SIZE(pv); i++)
1325 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1326 s->inst.data + pv[i].addr, pv[i].val);
1327}
1328
1329/*
1330 * Native record driver
1331 */
1332static const struct rec_vals {
1333 u16 addr, val;
1334} rv[] = {
1335 {CDATA_LEFT_VOLUME, ARB_VOLUME},
1336 {CDATA_RIGHT_VOLUME, ARB_VOLUME},
1337 {SRC3_DIRECTION_OFFSET, 1} ,
1338 /* +1, +2 are stereo/16 bit */
1339 {SRC3_DIRECTION_OFFSET + 3, 0x0000}, /* fraction? */
1340 {SRC3_DIRECTION_OFFSET + 4, 0}, /* first l */
1341 {SRC3_DIRECTION_OFFSET + 5, 0}, /* first r */
1342 {SRC3_DIRECTION_OFFSET + 6, 0}, /* second l */
1343 {SRC3_DIRECTION_OFFSET + 7, 0}, /* second r */
1344 {SRC3_DIRECTION_OFFSET + 8, 0}, /* delta l */
1345 {SRC3_DIRECTION_OFFSET + 9, 0}, /* delta r */
1346 {SRC3_DIRECTION_OFFSET + 10, 0x8000}, /* round */
1347 {SRC3_DIRECTION_OFFSET + 11, 0xFF00}, /* higher bute mark */
1348 {SRC3_DIRECTION_OFFSET + 13, 0}, /* temp0 */
1349 {SRC3_DIRECTION_OFFSET + 14, 0}, /* c fraction */
1350 {SRC3_DIRECTION_OFFSET + 15, 0}, /* counter */
1351 {SRC3_DIRECTION_OFFSET + 16, 50},/* numin */
1352 {SRC3_DIRECTION_OFFSET + 17, 8}, /* numout */
1353 {SRC3_DIRECTION_OFFSET + 18, 0}, /* numstage */
1354 {SRC3_DIRECTION_OFFSET + 19, 0}, /* coef */
1355 {SRC3_DIRECTION_OFFSET + 20, 0}, /* filtertap */
1356 {SRC3_DIRECTION_OFFSET + 21, 0}, /* booster */
1357 {SRC3_DIRECTION_OFFSET + 22, 0xff} /* skip lpf */
1358};
1359
1360static void
1361snd_m3_capture_setup(struct snd_m3 *chip, struct m3_dma *s, struct snd_pcm_substream *subs)
1362{
1363 unsigned int i;
1364
1365 /*
1366 * some per client initializers
1367 */
1368
1369 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1370 s->inst.data + SRC3_DIRECTION_OFFSET + 12,
1371 s->inst.data + 40 + 8);
1372
1373 /* tell it which way dma is going? */
1374 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1375 s->inst.data + CDATA_DMA_CONTROL,
1376 DMACONTROL_DIRECTION + DMACONTROL_AUTOREPEAT +
1377 DMAC_PAGE3_SELECTOR + DMAC_BLOCKF_SELECTOR);
1378
1379 /*
1380 * set an armload of static initializers
1381 */
1382 for (i = 0; i < ARRAY_SIZE(rv); i++)
1383 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1384 s->inst.data + rv[i].addr, rv[i].val);
1385}
1386
1387static int snd_m3_pcm_hw_params(struct snd_pcm_substream *substream,
1388 struct snd_pcm_hw_params *hw_params)
1389{
1390 struct m3_dma *s = substream->runtime->private_data;
1391
1392 /* set buffer address */
1393 s->buffer_addr = substream->runtime->dma_addr;
1394 if (s->buffer_addr & 0x3) {
1395 dev_err(substream->pcm->card->dev, "oh my, not aligned\n");
1396 s->buffer_addr = s->buffer_addr & ~0x3;
1397 }
1398 return 0;
1399}
1400
1401static int snd_m3_pcm_hw_free(struct snd_pcm_substream *substream)
1402{
1403 struct m3_dma *s;
1404
1405 if (substream->runtime->private_data == NULL)
1406 return 0;
1407 s = substream->runtime->private_data;
1408 s->buffer_addr = 0;
1409 return 0;
1410}
1411
1412static int
1413snd_m3_pcm_prepare(struct snd_pcm_substream *subs)
1414{
1415 struct snd_m3 *chip = snd_pcm_substream_chip(subs);
1416 struct snd_pcm_runtime *runtime = subs->runtime;
1417 struct m3_dma *s = runtime->private_data;
1418
1419 if (snd_BUG_ON(!s))
1420 return -ENXIO;
1421
1422 if (runtime->format != SNDRV_PCM_FORMAT_U8 &&
1423 runtime->format != SNDRV_PCM_FORMAT_S16_LE)
1424 return -EINVAL;
1425 if (runtime->rate > 48000 ||
1426 runtime->rate < 8000)
1427 return -EINVAL;
1428
1429 spin_lock_irq(&chip->reg_lock);
1430
1431 snd_m3_pcm_setup1(chip, s, subs);
1432
1433 if (subs->stream == SNDRV_PCM_STREAM_PLAYBACK)
1434 snd_m3_playback_setup(chip, s, subs);
1435 else
1436 snd_m3_capture_setup(chip, s, subs);
1437
1438 snd_m3_pcm_setup2(chip, s, runtime);
1439
1440 spin_unlock_irq(&chip->reg_lock);
1441
1442 return 0;
1443}
1444
1445/*
1446 * get current pointer
1447 */
1448static unsigned int
1449snd_m3_get_pointer(struct snd_m3 *chip, struct m3_dma *s, struct snd_pcm_substream *subs)
1450{
1451 u16 hi = 0, lo = 0;
1452 int retry = 10;
1453 u32 addr;
1454
1455 /*
1456 * try and get a valid answer
1457 */
1458 while (retry--) {
1459 hi = snd_m3_assp_read(chip, MEMTYPE_INTERNAL_DATA,
1460 s->inst.data + CDATA_HOST_SRC_CURRENTH);
1461
1462 lo = snd_m3_assp_read(chip, MEMTYPE_INTERNAL_DATA,
1463 s->inst.data + CDATA_HOST_SRC_CURRENTL);
1464
1465 if (hi == snd_m3_assp_read(chip, MEMTYPE_INTERNAL_DATA,
1466 s->inst.data + CDATA_HOST_SRC_CURRENTH))
1467 break;
1468 }
1469 addr = lo | ((u32)hi<<16);
1470 return (unsigned int)(addr - s->buffer_addr);
1471}
1472
1473static snd_pcm_uframes_t
1474snd_m3_pcm_pointer(struct snd_pcm_substream *subs)
1475{
1476 struct snd_m3 *chip = snd_pcm_substream_chip(subs);
1477 unsigned int ptr;
1478 struct m3_dma *s = subs->runtime->private_data;
1479
1480 if (snd_BUG_ON(!s))
1481 return 0;
1482
1483 spin_lock(&chip->reg_lock);
1484 ptr = snd_m3_get_pointer(chip, s, subs);
1485 spin_unlock(&chip->reg_lock);
1486 return bytes_to_frames(subs->runtime, ptr);
1487}
1488
1489
1490/* update pointer */
1491/* spinlock held! */
1492static void snd_m3_update_ptr(struct snd_m3 *chip, struct m3_dma *s)
1493{
1494 struct snd_pcm_substream *subs = s->substream;
1495 unsigned int hwptr;
1496 int diff;
1497
1498 if (! s->running)
1499 return;
1500
1501 hwptr = snd_m3_get_pointer(chip, s, subs);
1502
1503 /* try to avoid expensive modulo divisions */
1504 if (hwptr >= s->dma_size)
1505 hwptr %= s->dma_size;
1506
1507 diff = s->dma_size + hwptr - s->hwptr;
1508 if (diff >= s->dma_size)
1509 diff %= s->dma_size;
1510
1511 s->hwptr = hwptr;
1512 s->count += diff;
1513
1514 if (s->count >= (signed)s->period_size) {
1515
1516 if (s->count < 2 * (signed)s->period_size)
1517 s->count -= (signed)s->period_size;
1518 else
1519 s->count %= s->period_size;
1520
1521 spin_unlock(&chip->reg_lock);
1522 snd_pcm_period_elapsed(subs);
1523 spin_lock(&chip->reg_lock);
1524 }
1525}
1526
1527/* The m3's hardware volume works by incrementing / decrementing 2 counters
1528 (without wrap around) in response to volume button presses and then
1529 generating an interrupt. The pair of counters is stored in bits 1-3 and 5-7
1530 of a byte wide register. The meaning of bits 0 and 4 is unknown. */
1531static void snd_m3_update_hw_volume(struct work_struct *work)
1532{
1533 struct snd_m3 *chip = container_of(work, struct snd_m3, hwvol_work);
1534 int x, val;
1535
1536 /* Figure out which volume control button was pushed,
1537 based on differences from the default register
1538 values. */
1539 x = inb(chip->iobase + SHADOW_MIX_REG_VOICE) & 0xee;
1540
1541 /* Reset the volume counters to 4. Tests on the allegro integrated
1542 into a Compaq N600C laptop, have revealed that:
1543 1) Writing any value will result in the 2 counters being reset to
1544 4 so writing 0x88 is not strictly necessary
1545 2) Writing to any of the 4 involved registers will reset all 4
1546 of them (and reading them always returns the same value for all
1547 of them)
1548 It could be that a maestro deviates from this, so leave the code
1549 as is. */
1550 outb(0x88, chip->iobase + SHADOW_MIX_REG_VOICE);
1551 outb(0x88, chip->iobase + HW_VOL_COUNTER_VOICE);
1552 outb(0x88, chip->iobase + SHADOW_MIX_REG_MASTER);
1553 outb(0x88, chip->iobase + HW_VOL_COUNTER_MASTER);
1554
1555 /* Ignore spurious HV interrupts during suspend / resume, this avoids
1556 mistaking them for a mute button press. */
1557 if (chip->in_suspend)
1558 return;
1559
1560#ifndef CONFIG_SND_MAESTRO3_INPUT
1561 if (!chip->master_switch || !chip->master_volume)
1562 return;
1563
1564 val = snd_ac97_read(chip->ac97, AC97_MASTER);
1565 switch (x) {
1566 case 0x88:
1567 /* The counters have not changed, yet we've received a HV
1568 interrupt. According to tests run by various people this
1569 happens when pressing the mute button. */
1570 val ^= 0x8000;
1571 break;
1572 case 0xaa:
1573 /* counters increased by 1 -> volume up */
1574 if ((val & 0x7f) > 0)
1575 val--;
1576 if ((val & 0x7f00) > 0)
1577 val -= 0x0100;
1578 break;
1579 case 0x66:
1580 /* counters decreased by 1 -> volume down */
1581 if ((val & 0x7f) < 0x1f)
1582 val++;
1583 if ((val & 0x7f00) < 0x1f00)
1584 val += 0x0100;
1585 break;
1586 }
1587 if (snd_ac97_update(chip->ac97, AC97_MASTER, val))
1588 snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE,
1589 &chip->master_switch->id);
1590#else
1591 if (!chip->input_dev)
1592 return;
1593
1594 val = 0;
1595 switch (x) {
1596 case 0x88:
1597 /* The counters have not changed, yet we've received a HV
1598 interrupt. According to tests run by various people this
1599 happens when pressing the mute button. */
1600 val = KEY_MUTE;
1601 break;
1602 case 0xaa:
1603 /* counters increased by 1 -> volume up */
1604 val = KEY_VOLUMEUP;
1605 break;
1606 case 0x66:
1607 /* counters decreased by 1 -> volume down */
1608 val = KEY_VOLUMEDOWN;
1609 break;
1610 }
1611
1612 if (val) {
1613 input_report_key(chip->input_dev, val, 1);
1614 input_sync(chip->input_dev);
1615 input_report_key(chip->input_dev, val, 0);
1616 input_sync(chip->input_dev);
1617 }
1618#endif
1619}
1620
1621static irqreturn_t snd_m3_interrupt(int irq, void *dev_id)
1622{
1623 struct snd_m3 *chip = dev_id;
1624 u8 status;
1625 int i;
1626
1627 status = inb(chip->iobase + HOST_INT_STATUS);
1628
1629 if (status == 0xff)
1630 return IRQ_NONE;
1631
1632 if (status & HV_INT_PENDING)
1633 schedule_work(&chip->hwvol_work);
1634
1635 /*
1636 * ack an assp int if its running
1637 * and has an int pending
1638 */
1639 if (status & ASSP_INT_PENDING) {
1640 u8 ctl = inb(chip->iobase + ASSP_CONTROL_B);
1641 if (!(ctl & STOP_ASSP_CLOCK)) {
1642 ctl = inb(chip->iobase + ASSP_HOST_INT_STATUS);
1643 if (ctl & DSP2HOST_REQ_TIMER) {
1644 outb(DSP2HOST_REQ_TIMER, chip->iobase + ASSP_HOST_INT_STATUS);
1645 /* update adc/dac info if it was a timer int */
1646 spin_lock(&chip->reg_lock);
1647 for (i = 0; i < chip->num_substreams; i++) {
1648 struct m3_dma *s = &chip->substreams[i];
1649 if (s->running)
1650 snd_m3_update_ptr(chip, s);
1651 }
1652 spin_unlock(&chip->reg_lock);
1653 }
1654 }
1655 }
1656
1657#if 0 /* TODO: not supported yet */
1658 if ((status & MPU401_INT_PENDING) && chip->rmidi)
1659 snd_mpu401_uart_interrupt(irq, chip->rmidi->private_data, regs);
1660#endif
1661
1662 /* ack ints */
1663 outb(status, chip->iobase + HOST_INT_STATUS);
1664
1665 return IRQ_HANDLED;
1666}
1667
1668
1669/*
1670 */
1671
1672static const struct snd_pcm_hardware snd_m3_playback =
1673{
1674 .info = (SNDRV_PCM_INFO_MMAP |
1675 SNDRV_PCM_INFO_INTERLEAVED |
1676 SNDRV_PCM_INFO_MMAP_VALID |
1677 SNDRV_PCM_INFO_BLOCK_TRANSFER |
1678 /*SNDRV_PCM_INFO_PAUSE |*/
1679 SNDRV_PCM_INFO_RESUME),
1680 .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
1681 .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
1682 .rate_min = 8000,
1683 .rate_max = 48000,
1684 .channels_min = 1,
1685 .channels_max = 2,
1686 .buffer_bytes_max = (512*1024),
1687 .period_bytes_min = 64,
1688 .period_bytes_max = (512*1024),
1689 .periods_min = 1,
1690 .periods_max = 1024,
1691};
1692
1693static const struct snd_pcm_hardware snd_m3_capture =
1694{
1695 .info = (SNDRV_PCM_INFO_MMAP |
1696 SNDRV_PCM_INFO_INTERLEAVED |
1697 SNDRV_PCM_INFO_MMAP_VALID |
1698 SNDRV_PCM_INFO_BLOCK_TRANSFER |
1699 /*SNDRV_PCM_INFO_PAUSE |*/
1700 SNDRV_PCM_INFO_RESUME),
1701 .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
1702 .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
1703 .rate_min = 8000,
1704 .rate_max = 48000,
1705 .channels_min = 1,
1706 .channels_max = 2,
1707 .buffer_bytes_max = (512*1024),
1708 .period_bytes_min = 64,
1709 .period_bytes_max = (512*1024),
1710 .periods_min = 1,
1711 .periods_max = 1024,
1712};
1713
1714
1715/*
1716 */
1717
1718static int
1719snd_m3_substream_open(struct snd_m3 *chip, struct snd_pcm_substream *subs)
1720{
1721 int i;
1722 struct m3_dma *s;
1723
1724 spin_lock_irq(&chip->reg_lock);
1725 for (i = 0; i < chip->num_substreams; i++) {
1726 s = &chip->substreams[i];
1727 if (! s->opened)
1728 goto __found;
1729 }
1730 spin_unlock_irq(&chip->reg_lock);
1731 return -ENOMEM;
1732__found:
1733 s->opened = 1;
1734 s->running = 0;
1735 spin_unlock_irq(&chip->reg_lock);
1736
1737 subs->runtime->private_data = s;
1738 s->substream = subs;
1739
1740 /* set list owners */
1741 if (subs->stream == SNDRV_PCM_STREAM_PLAYBACK) {
1742 s->index_list[0] = &chip->mixer_list;
1743 } else
1744 s->index_list[0] = &chip->adc1_list;
1745 s->index_list[1] = &chip->msrc_list;
1746 s->index_list[2] = &chip->dma_list;
1747
1748 return 0;
1749}
1750
1751static void
1752snd_m3_substream_close(struct snd_m3 *chip, struct snd_pcm_substream *subs)
1753{
1754 struct m3_dma *s = subs->runtime->private_data;
1755
1756 if (s == NULL)
1757 return; /* not opened properly */
1758
1759 spin_lock_irq(&chip->reg_lock);
1760 if (s->substream && s->running)
1761 snd_m3_pcm_stop(chip, s, s->substream); /* does this happen? */
1762 if (s->in_lists) {
1763 snd_m3_remove_list(chip, s->index_list[0], s->index[0]);
1764 snd_m3_remove_list(chip, s->index_list[1], s->index[1]);
1765 snd_m3_remove_list(chip, s->index_list[2], s->index[2]);
1766 s->in_lists = 0;
1767 }
1768 s->running = 0;
1769 s->opened = 0;
1770 spin_unlock_irq(&chip->reg_lock);
1771}
1772
1773static int
1774snd_m3_playback_open(struct snd_pcm_substream *subs)
1775{
1776 struct snd_m3 *chip = snd_pcm_substream_chip(subs);
1777 struct snd_pcm_runtime *runtime = subs->runtime;
1778 int err;
1779
1780 if ((err = snd_m3_substream_open(chip, subs)) < 0)
1781 return err;
1782
1783 runtime->hw = snd_m3_playback;
1784
1785 return 0;
1786}
1787
1788static int
1789snd_m3_playback_close(struct snd_pcm_substream *subs)
1790{
1791 struct snd_m3 *chip = snd_pcm_substream_chip(subs);
1792
1793 snd_m3_substream_close(chip, subs);
1794 return 0;
1795}
1796
1797static int
1798snd_m3_capture_open(struct snd_pcm_substream *subs)
1799{
1800 struct snd_m3 *chip = snd_pcm_substream_chip(subs);
1801 struct snd_pcm_runtime *runtime = subs->runtime;
1802 int err;
1803
1804 if ((err = snd_m3_substream_open(chip, subs)) < 0)
1805 return err;
1806
1807 runtime->hw = snd_m3_capture;
1808
1809 return 0;
1810}
1811
1812static int
1813snd_m3_capture_close(struct snd_pcm_substream *subs)
1814{
1815 struct snd_m3 *chip = snd_pcm_substream_chip(subs);
1816
1817 snd_m3_substream_close(chip, subs);
1818 return 0;
1819}
1820
1821/*
1822 * create pcm instance
1823 */
1824
1825static const struct snd_pcm_ops snd_m3_playback_ops = {
1826 .open = snd_m3_playback_open,
1827 .close = snd_m3_playback_close,
1828 .hw_params = snd_m3_pcm_hw_params,
1829 .hw_free = snd_m3_pcm_hw_free,
1830 .prepare = snd_m3_pcm_prepare,
1831 .trigger = snd_m3_pcm_trigger,
1832 .pointer = snd_m3_pcm_pointer,
1833};
1834
1835static const struct snd_pcm_ops snd_m3_capture_ops = {
1836 .open = snd_m3_capture_open,
1837 .close = snd_m3_capture_close,
1838 .hw_params = snd_m3_pcm_hw_params,
1839 .hw_free = snd_m3_pcm_hw_free,
1840 .prepare = snd_m3_pcm_prepare,
1841 .trigger = snd_m3_pcm_trigger,
1842 .pointer = snd_m3_pcm_pointer,
1843};
1844
1845static int
1846snd_m3_pcm(struct snd_m3 * chip, int device)
1847{
1848 struct snd_pcm *pcm;
1849 int err;
1850
1851 err = snd_pcm_new(chip->card, chip->card->driver, device,
1852 MAX_PLAYBACKS, MAX_CAPTURES, &pcm);
1853 if (err < 0)
1854 return err;
1855
1856 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_m3_playback_ops);
1857 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_m3_capture_ops);
1858
1859 pcm->private_data = chip;
1860 pcm->info_flags = 0;
1861 strcpy(pcm->name, chip->card->driver);
1862 chip->pcm = pcm;
1863
1864 snd_pcm_set_managed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV,
1865 &chip->pci->dev, 64*1024, 64*1024);
1866
1867 return 0;
1868}
1869
1870
1871/*
1872 * ac97 interface
1873 */
1874
1875/*
1876 * Wait for the ac97 serial bus to be free.
1877 * return nonzero if the bus is still busy.
1878 */
1879static int snd_m3_ac97_wait(struct snd_m3 *chip)
1880{
1881 int i = 10000;
1882
1883 do {
1884 if (! (snd_m3_inb(chip, 0x30) & 1))
1885 return 0;
1886 cpu_relax();
1887 } while (i-- > 0);
1888
1889 dev_err(chip->card->dev, "ac97 serial bus busy\n");
1890 return 1;
1891}
1892
1893static unsigned short
1894snd_m3_ac97_read(struct snd_ac97 *ac97, unsigned short reg)
1895{
1896 struct snd_m3 *chip = ac97->private_data;
1897 unsigned short data = 0xffff;
1898
1899 if (snd_m3_ac97_wait(chip))
1900 goto fail;
1901 snd_m3_outb(chip, 0x80 | (reg & 0x7f), CODEC_COMMAND);
1902 if (snd_m3_ac97_wait(chip))
1903 goto fail;
1904 data = snd_m3_inw(chip, CODEC_DATA);
1905fail:
1906 return data;
1907}
1908
1909static void
1910snd_m3_ac97_write(struct snd_ac97 *ac97, unsigned short reg, unsigned short val)
1911{
1912 struct snd_m3 *chip = ac97->private_data;
1913
1914 if (snd_m3_ac97_wait(chip))
1915 return;
1916 snd_m3_outw(chip, val, CODEC_DATA);
1917 snd_m3_outb(chip, reg & 0x7f, CODEC_COMMAND);
1918 /*
1919 * Workaround for buggy ES1988 integrated AC'97 codec. It remains silent
1920 * until the MASTER volume or mute is touched (alsactl restore does not
1921 * work).
1922 */
1923 if (ac97->id == 0x45838308 && reg == AC97_MASTER) {
1924 snd_m3_ac97_wait(chip);
1925 snd_m3_outw(chip, val, CODEC_DATA);
1926 snd_m3_outb(chip, reg & 0x7f, CODEC_COMMAND);
1927 }
1928}
1929
1930
1931static void snd_m3_remote_codec_config(struct snd_m3 *chip, int isremote)
1932{
1933 int io = chip->iobase;
1934 u16 tmp;
1935
1936 isremote = isremote ? 1 : 0;
1937
1938 tmp = inw(io + RING_BUS_CTRL_B) & ~SECOND_CODEC_ID_MASK;
1939 /* enable dock on Dell Latitude C810 */
1940 if (chip->pci->subsystem_vendor == 0x1028 &&
1941 chip->pci->subsystem_device == 0x00e5)
1942 tmp |= M3I_DOCK_ENABLE;
1943 outw(tmp | isremote, io + RING_BUS_CTRL_B);
1944 outw((inw(io + SDO_OUT_DEST_CTRL) & ~COMMAND_ADDR_OUT) | isremote,
1945 io + SDO_OUT_DEST_CTRL);
1946 outw((inw(io + SDO_IN_DEST_CTRL) & ~STATUS_ADDR_IN) | isremote,
1947 io + SDO_IN_DEST_CTRL);
1948}
1949
1950/*
1951 * hack, returns non zero on err
1952 */
1953static int snd_m3_try_read_vendor(struct snd_m3 *chip)
1954{
1955 u16 ret;
1956
1957 if (snd_m3_ac97_wait(chip))
1958 return 1;
1959
1960 snd_m3_outb(chip, 0x80 | (AC97_VENDOR_ID1 & 0x7f), 0x30);
1961
1962 if (snd_m3_ac97_wait(chip))
1963 return 1;
1964
1965 ret = snd_m3_inw(chip, 0x32);
1966
1967 return (ret == 0) || (ret == 0xffff);
1968}
1969
1970static void snd_m3_ac97_reset(struct snd_m3 *chip)
1971{
1972 u16 dir;
1973 int delay1 = 0, delay2 = 0, i;
1974 int io = chip->iobase;
1975
1976 if (chip->allegro_flag) {
1977 /*
1978 * the onboard codec on the allegro seems
1979 * to want to wait a very long time before
1980 * coming back to life
1981 */
1982 delay1 = 50;
1983 delay2 = 800;
1984 } else {
1985 /* maestro3 */
1986 delay1 = 20;
1987 delay2 = 500;
1988 }
1989
1990 for (i = 0; i < 5; i++) {
1991 dir = inw(io + GPIO_DIRECTION);
1992 if (!chip->irda_workaround)
1993 dir |= 0x10; /* assuming pci bus master? */
1994
1995 snd_m3_remote_codec_config(chip, 0);
1996
1997 outw(IO_SRAM_ENABLE, io + RING_BUS_CTRL_A);
1998 udelay(20);
1999
2000 outw(dir & ~GPO_PRIMARY_AC97 , io + GPIO_DIRECTION);
2001 outw(~GPO_PRIMARY_AC97 , io + GPIO_MASK);
2002 outw(0, io + GPIO_DATA);
2003 outw(dir | GPO_PRIMARY_AC97, io + GPIO_DIRECTION);
2004
2005 schedule_timeout_uninterruptible(msecs_to_jiffies(delay1));
2006
2007 outw(GPO_PRIMARY_AC97, io + GPIO_DATA);
2008 udelay(5);
2009 /* ok, bring back the ac-link */
2010 outw(IO_SRAM_ENABLE | SERIAL_AC_LINK_ENABLE, io + RING_BUS_CTRL_A);
2011 outw(~0, io + GPIO_MASK);
2012
2013 schedule_timeout_uninterruptible(msecs_to_jiffies(delay2));
2014
2015 if (! snd_m3_try_read_vendor(chip))
2016 break;
2017
2018 delay1 += 10;
2019 delay2 += 100;
2020
2021 dev_dbg(chip->card->dev,
2022 "retrying codec reset with delays of %d and %d ms\n",
2023 delay1, delay2);
2024 }
2025
2026#if 0
2027 /* more gung-ho reset that doesn't
2028 * seem to work anywhere :)
2029 */
2030 tmp = inw(io + RING_BUS_CTRL_A);
2031 outw(RAC_SDFS_ENABLE|LAC_SDFS_ENABLE, io + RING_BUS_CTRL_A);
2032 msleep(20);
2033 outw(tmp, io + RING_BUS_CTRL_A);
2034 msleep(50);
2035#endif
2036}
2037
2038static int snd_m3_mixer(struct snd_m3 *chip)
2039{
2040 struct snd_ac97_bus *pbus;
2041 struct snd_ac97_template ac97;
2042#ifndef CONFIG_SND_MAESTRO3_INPUT
2043 struct snd_ctl_elem_id elem_id;
2044#endif
2045 int err;
2046 static const struct snd_ac97_bus_ops ops = {
2047 .write = snd_m3_ac97_write,
2048 .read = snd_m3_ac97_read,
2049 };
2050
2051 if ((err = snd_ac97_bus(chip->card, 0, &ops, NULL, &pbus)) < 0)
2052 return err;
2053
2054 memset(&ac97, 0, sizeof(ac97));
2055 ac97.private_data = chip;
2056 if ((err = snd_ac97_mixer(pbus, &ac97, &chip->ac97)) < 0)
2057 return err;
2058
2059 /* seems ac97 PCM needs initialization.. hack hack.. */
2060 snd_ac97_write(chip->ac97, AC97_PCM, 0x8000 | (15 << 8) | 15);
2061 schedule_timeout_uninterruptible(msecs_to_jiffies(100));
2062 snd_ac97_write(chip->ac97, AC97_PCM, 0);
2063
2064#ifndef CONFIG_SND_MAESTRO3_INPUT
2065 memset(&elem_id, 0, sizeof(elem_id));
2066 elem_id.iface = SNDRV_CTL_ELEM_IFACE_MIXER;
2067 strcpy(elem_id.name, "Master Playback Switch");
2068 chip->master_switch = snd_ctl_find_id(chip->card, &elem_id);
2069 memset(&elem_id, 0, sizeof(elem_id));
2070 elem_id.iface = SNDRV_CTL_ELEM_IFACE_MIXER;
2071 strcpy(elem_id.name, "Master Playback Volume");
2072 chip->master_volume = snd_ctl_find_id(chip->card, &elem_id);
2073#endif
2074
2075 return 0;
2076}
2077
2078
2079/*
2080 * initialize ASSP
2081 */
2082
2083#define MINISRC_LPF_LEN 10
2084static const u16 minisrc_lpf[MINISRC_LPF_LEN] = {
2085 0X0743, 0X1104, 0X0A4C, 0XF88D, 0X242C,
2086 0X1023, 0X1AA9, 0X0B60, 0XEFDD, 0X186F
2087};
2088
2089static void snd_m3_assp_init(struct snd_m3 *chip)
2090{
2091 unsigned int i;
2092 const __le16 *data;
2093
2094 /* zero kernel data */
2095 for (i = 0; i < (REV_B_DATA_MEMORY_UNIT_LENGTH * NUM_UNITS_KERNEL_DATA) / 2; i++)
2096 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2097 KDATA_BASE_ADDR + i, 0);
2098
2099 /* zero mixer data? */
2100 for (i = 0; i < (REV_B_DATA_MEMORY_UNIT_LENGTH * NUM_UNITS_KERNEL_DATA) / 2; i++)
2101 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2102 KDATA_BASE_ADDR2 + i, 0);
2103
2104 /* init dma pointer */
2105 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2106 KDATA_CURRENT_DMA,
2107 KDATA_DMA_XFER0);
2108
2109 /* write kernel into code memory.. */
2110 data = (const __le16 *)chip->assp_kernel_image->data;
2111 for (i = 0 ; i * 2 < chip->assp_kernel_image->size; i++) {
2112 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_CODE,
2113 REV_B_CODE_MEMORY_BEGIN + i,
2114 le16_to_cpu(data[i]));
2115 }
2116
2117 /*
2118 * We only have this one client and we know that 0x400
2119 * is free in our kernel's mem map, so lets just
2120 * drop it there. It seems that the minisrc doesn't
2121 * need vectors, so we won't bother with them..
2122 */
2123 data = (const __le16 *)chip->assp_minisrc_image->data;
2124 for (i = 0; i * 2 < chip->assp_minisrc_image->size; i++) {
2125 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_CODE,
2126 0x400 + i, le16_to_cpu(data[i]));
2127 }
2128
2129 /*
2130 * write the coefficients for the low pass filter?
2131 */
2132 for (i = 0; i < MINISRC_LPF_LEN ; i++) {
2133 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_CODE,
2134 0x400 + MINISRC_COEF_LOC + i,
2135 minisrc_lpf[i]);
2136 }
2137
2138 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_CODE,
2139 0x400 + MINISRC_COEF_LOC + MINISRC_LPF_LEN,
2140 0x8000);
2141
2142 /*
2143 * the minisrc is the only thing on
2144 * our task list..
2145 */
2146 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2147 KDATA_TASK0,
2148 0x400);
2149
2150 /*
2151 * init the mixer number..
2152 */
2153
2154 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2155 KDATA_MIXER_TASK_NUMBER,0);
2156
2157 /*
2158 * EXTREME KERNEL MASTER VOLUME
2159 */
2160 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2161 KDATA_DAC_LEFT_VOLUME, ARB_VOLUME);
2162 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2163 KDATA_DAC_RIGHT_VOLUME, ARB_VOLUME);
2164
2165 chip->mixer_list.curlen = 0;
2166 chip->mixer_list.mem_addr = KDATA_MIXER_XFER0;
2167 chip->mixer_list.max = MAX_VIRTUAL_MIXER_CHANNELS;
2168 chip->adc1_list.curlen = 0;
2169 chip->adc1_list.mem_addr = KDATA_ADC1_XFER0;
2170 chip->adc1_list.max = MAX_VIRTUAL_ADC1_CHANNELS;
2171 chip->dma_list.curlen = 0;
2172 chip->dma_list.mem_addr = KDATA_DMA_XFER0;
2173 chip->dma_list.max = MAX_VIRTUAL_DMA_CHANNELS;
2174 chip->msrc_list.curlen = 0;
2175 chip->msrc_list.mem_addr = KDATA_INSTANCE0_MINISRC;
2176 chip->msrc_list.max = MAX_INSTANCE_MINISRC;
2177}
2178
2179
2180static int snd_m3_assp_client_init(struct snd_m3 *chip, struct m3_dma *s, int index)
2181{
2182 int data_bytes = 2 * ( MINISRC_TMP_BUFFER_SIZE / 2 +
2183 MINISRC_IN_BUFFER_SIZE / 2 +
2184 1 + MINISRC_OUT_BUFFER_SIZE / 2 + 1 );
2185 int address, i;
2186
2187 /*
2188 * the revb memory map has 0x1100 through 0x1c00
2189 * free.
2190 */
2191
2192 /*
2193 * align instance address to 256 bytes so that its
2194 * shifted list address is aligned.
2195 * list address = (mem address >> 1) >> 7;
2196 */
2197 data_bytes = ALIGN(data_bytes, 256);
2198 address = 0x1100 + ((data_bytes/2) * index);
2199
2200 if ((address + (data_bytes/2)) >= 0x1c00) {
2201 dev_err(chip->card->dev,
2202 "no memory for %d bytes at ind %d (addr 0x%x)\n",
2203 data_bytes, index, address);
2204 return -ENOMEM;
2205 }
2206
2207 s->number = index;
2208 s->inst.code = 0x400;
2209 s->inst.data = address;
2210
2211 for (i = data_bytes / 2; i > 0; address++, i--) {
2212 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2213 address, 0);
2214 }
2215
2216 return 0;
2217}
2218
2219
2220/*
2221 * this works for the reference board, have to find
2222 * out about others
2223 *
2224 * this needs more magic for 4 speaker, but..
2225 */
2226static void
2227snd_m3_amp_enable(struct snd_m3 *chip, int enable)
2228{
2229 int io = chip->iobase;
2230 u16 gpo, polarity;
2231
2232 if (! chip->external_amp)
2233 return;
2234
2235 polarity = enable ? 0 : 1;
2236 polarity = polarity << chip->amp_gpio;
2237 gpo = 1 << chip->amp_gpio;
2238
2239 outw(~gpo, io + GPIO_MASK);
2240
2241 outw(inw(io + GPIO_DIRECTION) | gpo,
2242 io + GPIO_DIRECTION);
2243
2244 outw((GPO_SECONDARY_AC97 | GPO_PRIMARY_AC97 | polarity),
2245 io + GPIO_DATA);
2246
2247 outw(0xffff, io + GPIO_MASK);
2248}
2249
2250static void
2251snd_m3_hv_init(struct snd_m3 *chip)
2252{
2253 unsigned long io = chip->iobase;
2254 u16 val = GPI_VOL_DOWN | GPI_VOL_UP;
2255
2256 if (!chip->is_omnibook)
2257 return;
2258
2259 /*
2260 * Volume buttons on some HP OmniBook laptops
2261 * require some GPIO magic to work correctly.
2262 */
2263 outw(0xffff, io + GPIO_MASK);
2264 outw(0x0000, io + GPIO_DATA);
2265
2266 outw(~val, io + GPIO_MASK);
2267 outw(inw(io + GPIO_DIRECTION) & ~val, io + GPIO_DIRECTION);
2268 outw(val, io + GPIO_MASK);
2269
2270 outw(0xffff, io + GPIO_MASK);
2271}
2272
2273static int
2274snd_m3_chip_init(struct snd_m3 *chip)
2275{
2276 struct pci_dev *pcidev = chip->pci;
2277 unsigned long io = chip->iobase;
2278 u32 n;
2279 u16 w;
2280 u8 t; /* makes as much sense as 'n', no? */
2281
2282 pci_read_config_word(pcidev, PCI_LEGACY_AUDIO_CTRL, &w);
2283 w &= ~(SOUND_BLASTER_ENABLE|FM_SYNTHESIS_ENABLE|
2284 MPU401_IO_ENABLE|MPU401_IRQ_ENABLE|ALIAS_10BIT_IO|
2285 DISABLE_LEGACY);
2286 pci_write_config_word(pcidev, PCI_LEGACY_AUDIO_CTRL, w);
2287
2288 pci_read_config_dword(pcidev, PCI_ALLEGRO_CONFIG, &n);
2289 n &= ~(HV_CTRL_ENABLE | REDUCED_DEBOUNCE | HV_BUTTON_FROM_GD);
2290 n |= chip->hv_config;
2291 /* For some reason we must always use reduced debounce. */
2292 n |= REDUCED_DEBOUNCE;
2293 n |= PM_CTRL_ENABLE | CLK_DIV_BY_49 | USE_PCI_TIMING;
2294 pci_write_config_dword(pcidev, PCI_ALLEGRO_CONFIG, n);
2295
2296 outb(RESET_ASSP, chip->iobase + ASSP_CONTROL_B);
2297 pci_read_config_dword(pcidev, PCI_ALLEGRO_CONFIG, &n);
2298 n &= ~INT_CLK_SELECT;
2299 if (!chip->allegro_flag) {
2300 n &= ~INT_CLK_MULT_ENABLE;
2301 n |= INT_CLK_SRC_NOT_PCI;
2302 }
2303 n &= ~( CLK_MULT_MODE_SELECT | CLK_MULT_MODE_SELECT_2 );
2304 pci_write_config_dword(pcidev, PCI_ALLEGRO_CONFIG, n);
2305
2306 if (chip->allegro_flag) {
2307 pci_read_config_dword(pcidev, PCI_USER_CONFIG, &n);
2308 n |= IN_CLK_12MHZ_SELECT;
2309 pci_write_config_dword(pcidev, PCI_USER_CONFIG, n);
2310 }
2311
2312 t = inb(chip->iobase + ASSP_CONTROL_A);
2313 t &= ~( DSP_CLK_36MHZ_SELECT | ASSP_CLK_49MHZ_SELECT);
2314 t |= ASSP_CLK_49MHZ_SELECT;
2315 t |= ASSP_0_WS_ENABLE;
2316 outb(t, chip->iobase + ASSP_CONTROL_A);
2317
2318 snd_m3_assp_init(chip); /* download DSP code before starting ASSP below */
2319 outb(RUN_ASSP, chip->iobase + ASSP_CONTROL_B);
2320
2321 outb(0x00, io + HARDWARE_VOL_CTRL);
2322 outb(0x88, io + SHADOW_MIX_REG_VOICE);
2323 outb(0x88, io + HW_VOL_COUNTER_VOICE);
2324 outb(0x88, io + SHADOW_MIX_REG_MASTER);
2325 outb(0x88, io + HW_VOL_COUNTER_MASTER);
2326
2327 return 0;
2328}
2329
2330static void
2331snd_m3_enable_ints(struct snd_m3 *chip)
2332{
2333 unsigned long io = chip->iobase;
2334 unsigned short val;
2335
2336 /* TODO: MPU401 not supported yet */
2337 val = ASSP_INT_ENABLE /*| MPU401_INT_ENABLE*/;
2338 if (chip->hv_config & HV_CTRL_ENABLE)
2339 val |= HV_INT_ENABLE;
2340 outb(val, chip->iobase + HOST_INT_STATUS);
2341 outw(val, io + HOST_INT_CTRL);
2342 outb(inb(io + ASSP_CONTROL_C) | ASSP_HOST_INT_ENABLE,
2343 io + ASSP_CONTROL_C);
2344}
2345
2346
2347/*
2348 */
2349
2350static int snd_m3_free(struct snd_m3 *chip)
2351{
2352 struct m3_dma *s;
2353 int i;
2354
2355 cancel_work_sync(&chip->hwvol_work);
2356#ifdef CONFIG_SND_MAESTRO3_INPUT
2357 if (chip->input_dev)
2358 input_unregister_device(chip->input_dev);
2359#endif
2360
2361 if (chip->substreams) {
2362 spin_lock_irq(&chip->reg_lock);
2363 for (i = 0; i < chip->num_substreams; i++) {
2364 s = &chip->substreams[i];
2365 /* check surviving pcms; this should not happen though.. */
2366 if (s->substream && s->running)
2367 snd_m3_pcm_stop(chip, s, s->substream);
2368 }
2369 spin_unlock_irq(&chip->reg_lock);
2370 kfree(chip->substreams);
2371 }
2372 if (chip->iobase) {
2373 outw(0, chip->iobase + HOST_INT_CTRL); /* disable ints */
2374 }
2375
2376#ifdef CONFIG_PM_SLEEP
2377 vfree(chip->suspend_mem);
2378#endif
2379
2380 if (chip->irq >= 0)
2381 free_irq(chip->irq, chip);
2382
2383 if (chip->iobase)
2384 pci_release_regions(chip->pci);
2385
2386 release_firmware(chip->assp_kernel_image);
2387 release_firmware(chip->assp_minisrc_image);
2388
2389 pci_disable_device(chip->pci);
2390 kfree(chip);
2391 return 0;
2392}
2393
2394
2395/*
2396 * APM support
2397 */
2398#ifdef CONFIG_PM_SLEEP
2399static int m3_suspend(struct device *dev)
2400{
2401 struct snd_card *card = dev_get_drvdata(dev);
2402 struct snd_m3 *chip = card->private_data;
2403 int i, dsp_index;
2404
2405 if (chip->suspend_mem == NULL)
2406 return 0;
2407
2408 chip->in_suspend = 1;
2409 cancel_work_sync(&chip->hwvol_work);
2410 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
2411 snd_ac97_suspend(chip->ac97);
2412
2413 msleep(10); /* give the assp a chance to idle.. */
2414
2415 snd_m3_assp_halt(chip);
2416
2417 /* save dsp image */
2418 dsp_index = 0;
2419 for (i = REV_B_CODE_MEMORY_BEGIN; i <= REV_B_CODE_MEMORY_END; i++)
2420 chip->suspend_mem[dsp_index++] =
2421 snd_m3_assp_read(chip, MEMTYPE_INTERNAL_CODE, i);
2422 for (i = REV_B_DATA_MEMORY_BEGIN ; i <= REV_B_DATA_MEMORY_END; i++)
2423 chip->suspend_mem[dsp_index++] =
2424 snd_m3_assp_read(chip, MEMTYPE_INTERNAL_DATA, i);
2425 return 0;
2426}
2427
2428static int m3_resume(struct device *dev)
2429{
2430 struct snd_card *card = dev_get_drvdata(dev);
2431 struct snd_m3 *chip = card->private_data;
2432 int i, dsp_index;
2433
2434 if (chip->suspend_mem == NULL)
2435 return 0;
2436
2437 /* first lets just bring everything back. .*/
2438 snd_m3_outw(chip, 0, 0x54);
2439 snd_m3_outw(chip, 0, 0x56);
2440
2441 snd_m3_chip_init(chip);
2442 snd_m3_assp_halt(chip);
2443 snd_m3_ac97_reset(chip);
2444
2445 /* restore dsp image */
2446 dsp_index = 0;
2447 for (i = REV_B_CODE_MEMORY_BEGIN; i <= REV_B_CODE_MEMORY_END; i++)
2448 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_CODE, i,
2449 chip->suspend_mem[dsp_index++]);
2450 for (i = REV_B_DATA_MEMORY_BEGIN ; i <= REV_B_DATA_MEMORY_END; i++)
2451 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, i,
2452 chip->suspend_mem[dsp_index++]);
2453
2454 /* tell the dma engine to restart itself */
2455 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2456 KDATA_DMA_ACTIVE, 0);
2457
2458 /* restore ac97 registers */
2459 snd_ac97_resume(chip->ac97);
2460
2461 snd_m3_assp_continue(chip);
2462 snd_m3_enable_ints(chip);
2463 snd_m3_amp_enable(chip, 1);
2464
2465 snd_m3_hv_init(chip);
2466
2467 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
2468 chip->in_suspend = 0;
2469 return 0;
2470}
2471
2472static SIMPLE_DEV_PM_OPS(m3_pm, m3_suspend, m3_resume);
2473#define M3_PM_OPS &m3_pm
2474#else
2475#define M3_PM_OPS NULL
2476#endif /* CONFIG_PM_SLEEP */
2477
2478#ifdef CONFIG_SND_MAESTRO3_INPUT
2479static int snd_m3_input_register(struct snd_m3 *chip)
2480{
2481 struct input_dev *input_dev;
2482 int err;
2483
2484 input_dev = input_allocate_device();
2485 if (!input_dev)
2486 return -ENOMEM;
2487
2488 snprintf(chip->phys, sizeof(chip->phys), "pci-%s/input0",
2489 pci_name(chip->pci));
2490
2491 input_dev->name = chip->card->driver;
2492 input_dev->phys = chip->phys;
2493 input_dev->id.bustype = BUS_PCI;
2494 input_dev->id.vendor = chip->pci->vendor;
2495 input_dev->id.product = chip->pci->device;
2496 input_dev->dev.parent = &chip->pci->dev;
2497
2498 __set_bit(EV_KEY, input_dev->evbit);
2499 __set_bit(KEY_MUTE, input_dev->keybit);
2500 __set_bit(KEY_VOLUMEDOWN, input_dev->keybit);
2501 __set_bit(KEY_VOLUMEUP, input_dev->keybit);
2502
2503 err = input_register_device(input_dev);
2504 if (err) {
2505 input_free_device(input_dev);
2506 return err;
2507 }
2508
2509 chip->input_dev = input_dev;
2510 return 0;
2511}
2512#endif /* CONFIG_INPUT */
2513
2514/*
2515 */
2516
2517static int snd_m3_dev_free(struct snd_device *device)
2518{
2519 struct snd_m3 *chip = device->device_data;
2520 return snd_m3_free(chip);
2521}
2522
2523static int
2524snd_m3_create(struct snd_card *card, struct pci_dev *pci,
2525 int enable_amp,
2526 int amp_gpio,
2527 struct snd_m3 **chip_ret)
2528{
2529 struct snd_m3 *chip;
2530 int i, err;
2531 const struct snd_pci_quirk *quirk;
2532 static const struct snd_device_ops ops = {
2533 .dev_free = snd_m3_dev_free,
2534 };
2535
2536 *chip_ret = NULL;
2537
2538 if (pci_enable_device(pci))
2539 return -EIO;
2540
2541 /* check, if we can restrict PCI DMA transfers to 28 bits */
2542 if (dma_set_mask(&pci->dev, DMA_BIT_MASK(28)) < 0 ||
2543 dma_set_coherent_mask(&pci->dev, DMA_BIT_MASK(28)) < 0) {
2544 dev_err(card->dev,
2545 "architecture does not support 28bit PCI busmaster DMA\n");
2546 pci_disable_device(pci);
2547 return -ENXIO;
2548 }
2549
2550 chip = kzalloc(sizeof(*chip), GFP_KERNEL);
2551 if (chip == NULL) {
2552 pci_disable_device(pci);
2553 return -ENOMEM;
2554 }
2555
2556 spin_lock_init(&chip->reg_lock);
2557
2558 switch (pci->device) {
2559 case PCI_DEVICE_ID_ESS_ALLEGRO:
2560 case PCI_DEVICE_ID_ESS_ALLEGRO_1:
2561 case PCI_DEVICE_ID_ESS_CANYON3D_2LE:
2562 case PCI_DEVICE_ID_ESS_CANYON3D_2:
2563 chip->allegro_flag = 1;
2564 break;
2565 }
2566
2567 chip->card = card;
2568 chip->pci = pci;
2569 chip->irq = -1;
2570 INIT_WORK(&chip->hwvol_work, snd_m3_update_hw_volume);
2571
2572 chip->external_amp = enable_amp;
2573 if (amp_gpio >= 0 && amp_gpio <= 0x0f)
2574 chip->amp_gpio = amp_gpio;
2575 else {
2576 quirk = snd_pci_quirk_lookup(pci, m3_amp_quirk_list);
2577 if (quirk) {
2578 dev_info(card->dev, "set amp-gpio for '%s'\n",
2579 snd_pci_quirk_name(quirk));
2580 chip->amp_gpio = quirk->value;
2581 } else if (chip->allegro_flag)
2582 chip->amp_gpio = GPO_EXT_AMP_ALLEGRO;
2583 else /* presumably this is for all 'maestro3's.. */
2584 chip->amp_gpio = GPO_EXT_AMP_M3;
2585 }
2586
2587 quirk = snd_pci_quirk_lookup(pci, m3_irda_quirk_list);
2588 if (quirk) {
2589 dev_info(card->dev, "enabled irda workaround for '%s'\n",
2590 snd_pci_quirk_name(quirk));
2591 chip->irda_workaround = 1;
2592 }
2593 quirk = snd_pci_quirk_lookup(pci, m3_hv_quirk_list);
2594 if (quirk)
2595 chip->hv_config = quirk->value;
2596 if (snd_pci_quirk_lookup(pci, m3_omnibook_quirk_list))
2597 chip->is_omnibook = 1;
2598
2599 chip->num_substreams = NR_DSPS;
2600 chip->substreams = kcalloc(chip->num_substreams, sizeof(struct m3_dma),
2601 GFP_KERNEL);
2602 if (chip->substreams == NULL) {
2603 kfree(chip);
2604 pci_disable_device(pci);
2605 return -ENOMEM;
2606 }
2607
2608 err = request_firmware(&chip->assp_kernel_image,
2609 "ess/maestro3_assp_kernel.fw", &pci->dev);
2610 if (err < 0)
2611 goto free_chip;
2612
2613 err = request_firmware(&chip->assp_minisrc_image,
2614 "ess/maestro3_assp_minisrc.fw", &pci->dev);
2615 if (err < 0)
2616 goto free_chip;
2617
2618 err = pci_request_regions(pci, card->driver);
2619 if (err < 0)
2620 goto free_chip;
2621
2622 chip->iobase = pci_resource_start(pci, 0);
2623
2624 /* just to be sure */
2625 pci_set_master(pci);
2626
2627 snd_m3_chip_init(chip);
2628 snd_m3_assp_halt(chip);
2629
2630 snd_m3_ac97_reset(chip);
2631
2632 snd_m3_amp_enable(chip, 1);
2633
2634 snd_m3_hv_init(chip);
2635
2636 if (request_irq(pci->irq, snd_m3_interrupt, IRQF_SHARED,
2637 KBUILD_MODNAME, chip)) {
2638 dev_err(card->dev, "unable to grab IRQ %d\n", pci->irq);
2639 err = -ENOMEM;
2640 goto free_chip;
2641 }
2642 chip->irq = pci->irq;
2643 card->sync_irq = chip->irq;
2644
2645#ifdef CONFIG_PM_SLEEP
2646 chip->suspend_mem =
2647 vmalloc(array_size(sizeof(u16),
2648 REV_B_CODE_MEMORY_LENGTH +
2649 REV_B_DATA_MEMORY_LENGTH));
2650 if (chip->suspend_mem == NULL)
2651 dev_warn(card->dev, "can't allocate apm buffer\n");
2652#endif
2653
2654 err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
2655 if (err < 0)
2656 goto free_chip;
2657
2658 if ((err = snd_m3_mixer(chip)) < 0)
2659 return err;
2660
2661 for (i = 0; i < chip->num_substreams; i++) {
2662 struct m3_dma *s = &chip->substreams[i];
2663 if ((err = snd_m3_assp_client_init(chip, s, i)) < 0)
2664 return err;
2665 }
2666
2667 if ((err = snd_m3_pcm(chip, 0)) < 0)
2668 return err;
2669
2670#ifdef CONFIG_SND_MAESTRO3_INPUT
2671 if (chip->hv_config & HV_CTRL_ENABLE) {
2672 err = snd_m3_input_register(chip);
2673 if (err)
2674 dev_warn(card->dev,
2675 "Input device registration failed with error %i",
2676 err);
2677 }
2678#endif
2679
2680 snd_m3_enable_ints(chip);
2681 snd_m3_assp_continue(chip);
2682
2683 *chip_ret = chip;
2684
2685 return 0;
2686
2687free_chip:
2688 snd_m3_free(chip);
2689 return err;
2690}
2691
2692/*
2693 */
2694static int
2695snd_m3_probe(struct pci_dev *pci, const struct pci_device_id *pci_id)
2696{
2697 static int dev;
2698 struct snd_card *card;
2699 struct snd_m3 *chip;
2700 int err;
2701
2702 /* don't pick up modems */
2703 if (((pci->class >> 8) & 0xffff) != PCI_CLASS_MULTIMEDIA_AUDIO)
2704 return -ENODEV;
2705
2706 if (dev >= SNDRV_CARDS)
2707 return -ENODEV;
2708 if (!enable[dev]) {
2709 dev++;
2710 return -ENOENT;
2711 }
2712
2713 err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE,
2714 0, &card);
2715 if (err < 0)
2716 return err;
2717
2718 switch (pci->device) {
2719 case PCI_DEVICE_ID_ESS_ALLEGRO:
2720 case PCI_DEVICE_ID_ESS_ALLEGRO_1:
2721 strcpy(card->driver, "Allegro");
2722 break;
2723 case PCI_DEVICE_ID_ESS_CANYON3D_2LE:
2724 case PCI_DEVICE_ID_ESS_CANYON3D_2:
2725 strcpy(card->driver, "Canyon3D-2");
2726 break;
2727 default:
2728 strcpy(card->driver, "Maestro3");
2729 break;
2730 }
2731
2732 err = snd_m3_create(card, pci, external_amp[dev], amp_gpio[dev], &chip);
2733 if (err < 0)
2734 goto free_card;
2735
2736 card->private_data = chip;
2737
2738 sprintf(card->shortname, "ESS %s PCI", card->driver);
2739 sprintf(card->longname, "%s at 0x%lx, irq %d",
2740 card->shortname, chip->iobase, chip->irq);
2741
2742 err = snd_card_register(card);
2743 if (err < 0)
2744 goto free_card;
2745
2746#if 0 /* TODO: not supported yet */
2747 /* TODO enable MIDI IRQ and I/O */
2748 err = snd_mpu401_uart_new(chip->card, 0, MPU401_HW_MPU401,
2749 chip->iobase + MPU401_DATA_PORT,
2750 MPU401_INFO_INTEGRATED | MPU401_INFO_IRQ_HOOK,
2751 -1, &chip->rmidi);
2752 if (err < 0)
2753 dev_warn(card->dev, "no MIDI support.\n");
2754#endif
2755
2756 pci_set_drvdata(pci, card);
2757 dev++;
2758 return 0;
2759
2760free_card:
2761 snd_card_free(card);
2762 return err;
2763}
2764
2765static void snd_m3_remove(struct pci_dev *pci)
2766{
2767 snd_card_free(pci_get_drvdata(pci));
2768}
2769
2770static struct pci_driver m3_driver = {
2771 .name = KBUILD_MODNAME,
2772 .id_table = snd_m3_ids,
2773 .probe = snd_m3_probe,
2774 .remove = snd_m3_remove,
2775 .driver = {
2776 .pm = M3_PM_OPS,
2777 },
2778};
2779
2780module_pci_driver(m3_driver);
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