source: GPL/trunk/alsa-kernel/pci/maestro3.c@ 695

Last change on this file since 695 was 695, checked in by David Azarewicz, 4 years ago

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1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Driver for ESS Maestro3/Allegro (ES1988) soundcards.
4 * Copyright (c) 2000 by Zach Brown <zab@zabbo.net>
5 * Takashi Iwai <tiwai@suse.de>
6 *
7 * Most of the hardware init stuffs are based on maestro3 driver for
8 * OSS/Free by Zach Brown. Many thanks to Zach!
9 *
10 * ChangeLog:
11 * Aug. 27, 2001
12 * - Fixed deadlock on capture
13 * - Added Canyon3D-2 support by Rob Riggs <rob@pangalactic.org>
14 */
15
16#define CARD_NAME "ESS Maestro3/Allegro/Canyon3D-2"
17#define DRIVER_NAME "Maestro3"
18#ifdef TARGET_OS2
19#define KBUILD_MODNAME "Maestro3"
20#endif
21
22#include <linux/io.h>
23#include <linux/delay.h>
24#include <linux/interrupt.h>
25#include <linux/init.h>
26#include <linux/pci.h>
27#include <linux/dma-mapping.h>
28#include <linux/slab.h>
29#include <linux/vmalloc.h>
30#include <linux/module.h>
31#include <linux/firmware.h>
32#include <linux/input.h>
33#include <sound/core.h>
34#include <sound/info.h>
35#include <sound/control.h>
36#include <sound/pcm.h>
37#include <sound/mpu401.h>
38#include <sound/ac97_codec.h>
39#include <sound/initval.h>
40#include <asm/byteorder.h>
41
42MODULE_AUTHOR("Zach Brown <zab@zabbo.net>, Takashi Iwai <tiwai@suse.de>");
43MODULE_DESCRIPTION("ESS Maestro3 PCI");
44MODULE_LICENSE("GPL");
45MODULE_FIRMWARE("ess/maestro3_assp_kernel.fw");
46MODULE_FIRMWARE("ess/maestro3_assp_minisrc.fw");
47
48static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
49static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
50static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* all enabled */
51#ifndef TARGET_OS2
52static bool external_amp[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = 1};
53static int amp_gpio[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = -1};
54#else
55static int external_amp[SNDRV_CARDS] = {REPEAT_SNDRV(1)};
56static int amp_gpio[SNDRV_CARDS] = {REPEAT_SNDRV(-1)};
57#endif
58module_param_array(index, int, NULL, 0444);
59MODULE_PARM_DESC(index, "Index value for " CARD_NAME " soundcard.");
60module_param_array(id, charp, NULL, 0444);
61MODULE_PARM_DESC(id, "ID string for " CARD_NAME " soundcard.");
62module_param_array(enable, bool, NULL, 0444);
63MODULE_PARM_DESC(enable, "Enable this soundcard.");
64module_param_array(external_amp, bool, NULL, 0444);
65MODULE_PARM_DESC(external_amp, "Enable external amp for " CARD_NAME " soundcard.");
66module_param_array(amp_gpio, int, NULL, 0444);
67MODULE_PARM_DESC(amp_gpio, "GPIO pin number for external amp. (default = -1)");
68
69#define MAX_PLAYBACKS 2
70#define MAX_CAPTURES 1
71#define NR_DSPS (MAX_PLAYBACKS + MAX_CAPTURES)
72
73
74/*
75 * maestro3 registers
76 */
77
78/* Allegro PCI configuration registers */
79#define PCI_LEGACY_AUDIO_CTRL 0x40
80#define SOUND_BLASTER_ENABLE 0x00000001
81#define FM_SYNTHESIS_ENABLE 0x00000002
82#define GAME_PORT_ENABLE 0x00000004
83#define MPU401_IO_ENABLE 0x00000008
84#define MPU401_IRQ_ENABLE 0x00000010
85#define ALIAS_10BIT_IO 0x00000020
86#define SB_DMA_MASK 0x000000C0
87#define SB_DMA_0 0x00000040
88#define SB_DMA_1 0x00000040
89#define SB_DMA_R 0x00000080
90#define SB_DMA_3 0x000000C0
91#define SB_IRQ_MASK 0x00000700
92#define SB_IRQ_5 0x00000000
93#define SB_IRQ_7 0x00000100
94#define SB_IRQ_9 0x00000200
95#define SB_IRQ_10 0x00000300
96#define MIDI_IRQ_MASK 0x00003800
97#define SERIAL_IRQ_ENABLE 0x00004000
98#define DISABLE_LEGACY 0x00008000
99
100#define PCI_ALLEGRO_CONFIG 0x50
101#define SB_ADDR_240 0x00000004
102#define MPU_ADDR_MASK 0x00000018
103#define MPU_ADDR_330 0x00000000
104#define MPU_ADDR_300 0x00000008
105#define MPU_ADDR_320 0x00000010
106#define MPU_ADDR_340 0x00000018
107#define USE_PCI_TIMING 0x00000040
108#define POSTED_WRITE_ENABLE 0x00000080
109#define DMA_POLICY_MASK 0x00000700
110#define DMA_DDMA 0x00000000
111#define DMA_TDMA 0x00000100
112#define DMA_PCPCI 0x00000200
113#define DMA_WBDMA16 0x00000400
114#define DMA_WBDMA4 0x00000500
115#define DMA_WBDMA2 0x00000600
116#define DMA_WBDMA1 0x00000700
117#define DMA_SAFE_GUARD 0x00000800
118#define HI_PERF_GP_ENABLE 0x00001000
119#define PIC_SNOOP_MODE_0 0x00002000
120#define PIC_SNOOP_MODE_1 0x00004000
121#define SOUNDBLASTER_IRQ_MASK 0x00008000
122#define RING_IN_ENABLE 0x00010000
123#define SPDIF_TEST_MODE 0x00020000
124#define CLK_MULT_MODE_SELECT_2 0x00040000
125#define EEPROM_WRITE_ENABLE 0x00080000
126#define CODEC_DIR_IN 0x00100000
127#define HV_BUTTON_FROM_GD 0x00200000
128#define REDUCED_DEBOUNCE 0x00400000
129#define HV_CTRL_ENABLE 0x00800000
130#define SPDIF_ENABLE 0x01000000
131#define CLK_DIV_SELECT 0x06000000
132#define CLK_DIV_BY_48 0x00000000
133#define CLK_DIV_BY_49 0x02000000
134#define CLK_DIV_BY_50 0x04000000
135#define CLK_DIV_RESERVED 0x06000000
136#define PM_CTRL_ENABLE 0x08000000
137#define CLK_MULT_MODE_SELECT 0x30000000
138#define CLK_MULT_MODE_SHIFT 28
139#define CLK_MULT_MODE_0 0x00000000
140#define CLK_MULT_MODE_1 0x10000000
141#define CLK_MULT_MODE_2 0x20000000
142#define CLK_MULT_MODE_3 0x30000000
143#define INT_CLK_SELECT 0x40000000
144#define INT_CLK_MULT_RESET 0x80000000
145
146/* M3 */
147#define INT_CLK_SRC_NOT_PCI 0x00100000
148#define INT_CLK_MULT_ENABLE 0x80000000
149
150#define PCI_ACPI_CONTROL 0x54
151#define PCI_ACPI_D0 0x00000000
152#define PCI_ACPI_D1 0xB4F70000
153#define PCI_ACPI_D2 0xB4F7B4F7
154
155#define PCI_USER_CONFIG 0x58
156#define EXT_PCI_MASTER_ENABLE 0x00000001
157#define SPDIF_OUT_SELECT 0x00000002
158#define TEST_PIN_DIR_CTRL 0x00000004
159#define AC97_CODEC_TEST 0x00000020
160#define TRI_STATE_BUFFER 0x00000080
161#define IN_CLK_12MHZ_SELECT 0x00000100
162#define MULTI_FUNC_DISABLE 0x00000200
163#define EXT_MASTER_PAIR_SEL 0x00000400
164#define PCI_MASTER_SUPPORT 0x00000800
165#define STOP_CLOCK_ENABLE 0x00001000
166#define EAPD_DRIVE_ENABLE 0x00002000
167#define REQ_TRI_STATE_ENABLE 0x00004000
168#define REQ_LOW_ENABLE 0x00008000
169#define MIDI_1_ENABLE 0x00010000
170#define MIDI_2_ENABLE 0x00020000
171#define SB_AUDIO_SYNC 0x00040000
172#define HV_CTRL_TEST 0x00100000
173#define SOUNDBLASTER_TEST 0x00400000
174
175#define PCI_USER_CONFIG_C 0x5C
176
177#define PCI_DDMA_CTRL 0x60
178#define DDMA_ENABLE 0x00000001
179
180
181/* Allegro registers */
182#define HOST_INT_CTRL 0x18
183#define SB_INT_ENABLE 0x0001
184#define MPU401_INT_ENABLE 0x0002
185#define ASSP_INT_ENABLE 0x0010
186#define RING_INT_ENABLE 0x0020
187#define HV_INT_ENABLE 0x0040
188#define CLKRUN_GEN_ENABLE 0x0100
189#define HV_CTRL_TO_PME 0x0400
190#define SOFTWARE_RESET_ENABLE 0x8000
191
192/*
193 * should be using the above defines, probably.
194 */
195#define REGB_ENABLE_RESET 0x01
196#define REGB_STOP_CLOCK 0x10
197
198#define HOST_INT_STATUS 0x1A
199#define SB_INT_PENDING 0x01
200#define MPU401_INT_PENDING 0x02
201#define ASSP_INT_PENDING 0x10
202#define RING_INT_PENDING 0x20
203#define HV_INT_PENDING 0x40
204
205#define HARDWARE_VOL_CTRL 0x1B
206#define SHADOW_MIX_REG_VOICE 0x1C
207#define HW_VOL_COUNTER_VOICE 0x1D
208#define SHADOW_MIX_REG_MASTER 0x1E
209#define HW_VOL_COUNTER_MASTER 0x1F
210
211#define CODEC_COMMAND 0x30
212#define CODEC_READ_B 0x80
213
214#define CODEC_STATUS 0x30
215#define CODEC_BUSY_B 0x01
216
217#define CODEC_DATA 0x32
218
219#define RING_BUS_CTRL_A 0x36
220#define RAC_PME_ENABLE 0x0100
221#define RAC_SDFS_ENABLE 0x0200
222#define LAC_PME_ENABLE 0x0400
223#define LAC_SDFS_ENABLE 0x0800
224#define SERIAL_AC_LINK_ENABLE 0x1000
225#define IO_SRAM_ENABLE 0x2000
226#define IIS_INPUT_ENABLE 0x8000
227
228#define RING_BUS_CTRL_B 0x38
229#define SECOND_CODEC_ID_MASK 0x0003
230#define SPDIF_FUNC_ENABLE 0x0010
231#define SECOND_AC_ENABLE 0x0020
232#define SB_MODULE_INTF_ENABLE 0x0040
233#define SSPE_ENABLE 0x0040
234#define M3I_DOCK_ENABLE 0x0080
235
236#define SDO_OUT_DEST_CTRL 0x3A
237#define COMMAND_ADDR_OUT 0x0003
238#define PCM_LR_OUT_LOCAL 0x0000
239#define PCM_LR_OUT_REMOTE 0x0004
240#define PCM_LR_OUT_MUTE 0x0008
241#define PCM_LR_OUT_BOTH 0x000C
242#define LINE1_DAC_OUT_LOCAL 0x0000
243#define LINE1_DAC_OUT_REMOTE 0x0010
244#define LINE1_DAC_OUT_MUTE 0x0020
245#define LINE1_DAC_OUT_BOTH 0x0030
246#define PCM_CLS_OUT_LOCAL 0x0000
247#define PCM_CLS_OUT_REMOTE 0x0040
248#define PCM_CLS_OUT_MUTE 0x0080
249#define PCM_CLS_OUT_BOTH 0x00C0
250#define PCM_RLF_OUT_LOCAL 0x0000
251#define PCM_RLF_OUT_REMOTE 0x0100
252#define PCM_RLF_OUT_MUTE 0x0200
253#define PCM_RLF_OUT_BOTH 0x0300
254#define LINE2_DAC_OUT_LOCAL 0x0000
255#define LINE2_DAC_OUT_REMOTE 0x0400
256#define LINE2_DAC_OUT_MUTE 0x0800
257#define LINE2_DAC_OUT_BOTH 0x0C00
258#define HANDSET_OUT_LOCAL 0x0000
259#define HANDSET_OUT_REMOTE 0x1000
260#define HANDSET_OUT_MUTE 0x2000
261#define HANDSET_OUT_BOTH 0x3000
262#define IO_CTRL_OUT_LOCAL 0x0000
263#define IO_CTRL_OUT_REMOTE 0x4000
264#define IO_CTRL_OUT_MUTE 0x8000
265#define IO_CTRL_OUT_BOTH 0xC000
266
267#define SDO_IN_DEST_CTRL 0x3C
268#define STATUS_ADDR_IN 0x0003
269#define PCM_LR_IN_LOCAL 0x0000
270#define PCM_LR_IN_REMOTE 0x0004
271#define PCM_LR_RESERVED 0x0008
272#define PCM_LR_IN_BOTH 0x000C
273#define LINE1_ADC_IN_LOCAL 0x0000
274#define LINE1_ADC_IN_REMOTE 0x0010
275#define LINE1_ADC_IN_MUTE 0x0020
276#define MIC_ADC_IN_LOCAL 0x0000
277#define MIC_ADC_IN_REMOTE 0x0040
278#define MIC_ADC_IN_MUTE 0x0080
279#define LINE2_DAC_IN_LOCAL 0x0000
280#define LINE2_DAC_IN_REMOTE 0x0400
281#define LINE2_DAC_IN_MUTE 0x0800
282#define HANDSET_IN_LOCAL 0x0000
283#define HANDSET_IN_REMOTE 0x1000
284#define HANDSET_IN_MUTE 0x2000
285#define IO_STATUS_IN_LOCAL 0x0000
286#define IO_STATUS_IN_REMOTE 0x4000
287
288#define SPDIF_IN_CTRL 0x3E
289#define SPDIF_IN_ENABLE 0x0001
290
291#define GPIO_DATA 0x60
292#define GPIO_DATA_MASK 0x0FFF
293#define GPIO_HV_STATUS 0x3000
294#define GPIO_PME_STATUS 0x4000
295
296#define GPIO_MASK 0x64
297#define GPIO_DIRECTION 0x68
298#define GPO_PRIMARY_AC97 0x0001
299#define GPI_LINEOUT_SENSE 0x0004
300#define GPO_SECONDARY_AC97 0x0008
301#define GPI_VOL_DOWN 0x0010
302#define GPI_VOL_UP 0x0020
303#define GPI_IIS_CLK 0x0040
304#define GPI_IIS_LRCLK 0x0080
305#define GPI_IIS_DATA 0x0100
306#define GPI_DOCKING_STATUS 0x0100
307#define GPI_HEADPHONE_SENSE 0x0200
308#define GPO_EXT_AMP_SHUTDOWN 0x1000
309
310#define GPO_EXT_AMP_M3 1 /* default m3 amp */
311#define GPO_EXT_AMP_ALLEGRO 8 /* default allegro amp */
312
313/* M3 */
314#define GPO_M3_EXT_AMP_SHUTDN 0x0002
315
316#define ASSP_INDEX_PORT 0x80
317#define ASSP_MEMORY_PORT 0x82
318#define ASSP_DATA_PORT 0x84
319
320#define MPU401_DATA_PORT 0x98
321#define MPU401_STATUS_PORT 0x99
322
323#define CLK_MULT_DATA_PORT 0x9C
324
325#define ASSP_CONTROL_A 0xA2
326#define ASSP_0_WS_ENABLE 0x01
327#define ASSP_CTRL_A_RESERVED1 0x02
328#define ASSP_CTRL_A_RESERVED2 0x04
329#define ASSP_CLK_49MHZ_SELECT 0x08
330#define FAST_PLU_ENABLE 0x10
331#define ASSP_CTRL_A_RESERVED3 0x20
332#define DSP_CLK_36MHZ_SELECT 0x40
333
334#define ASSP_CONTROL_B 0xA4
335#define RESET_ASSP 0x00
336#define RUN_ASSP 0x01
337#define ENABLE_ASSP_CLOCK 0x00
338#define STOP_ASSP_CLOCK 0x10
339#define RESET_TOGGLE 0x40
340
341#define ASSP_CONTROL_C 0xA6
342#define ASSP_HOST_INT_ENABLE 0x01
343#define FM_ADDR_REMAP_DISABLE 0x02
344#define HOST_WRITE_PORT_ENABLE 0x08
345
346#define ASSP_HOST_INT_STATUS 0xAC
347#define DSP2HOST_REQ_PIORECORD 0x01
348#define DSP2HOST_REQ_I2SRATE 0x02
349#define DSP2HOST_REQ_TIMER 0x04
350
351/*
352 * ASSP control regs
353 */
354#define DSP_PORT_TIMER_COUNT 0x06
355
356#define DSP_PORT_MEMORY_INDEX 0x80
357
358#define DSP_PORT_MEMORY_TYPE 0x82
359#define MEMTYPE_INTERNAL_CODE 0x0002
360#define MEMTYPE_INTERNAL_DATA 0x0003
361#define MEMTYPE_MASK 0x0003
362
363#define DSP_PORT_MEMORY_DATA 0x84
364
365#define DSP_PORT_CONTROL_REG_A 0xA2
366#define DSP_PORT_CONTROL_REG_B 0xA4
367#define DSP_PORT_CONTROL_REG_C 0xA6
368
369#define REV_A_CODE_MEMORY_BEGIN 0x0000
370#define REV_A_CODE_MEMORY_END 0x0FFF
371#define REV_A_CODE_MEMORY_UNIT_LENGTH 0x0040
372#define REV_A_CODE_MEMORY_LENGTH (REV_A_CODE_MEMORY_END - REV_A_CODE_MEMORY_BEGIN + 1)
373
374#define REV_B_CODE_MEMORY_BEGIN 0x0000
375#define REV_B_CODE_MEMORY_END 0x0BFF
376#define REV_B_CODE_MEMORY_UNIT_LENGTH 0x0040
377#define REV_B_CODE_MEMORY_LENGTH (REV_B_CODE_MEMORY_END - REV_B_CODE_MEMORY_BEGIN + 1)
378
379#define REV_A_DATA_MEMORY_BEGIN 0x1000
380#define REV_A_DATA_MEMORY_END 0x2FFF
381#define REV_A_DATA_MEMORY_UNIT_LENGTH 0x0080
382#define REV_A_DATA_MEMORY_LENGTH (REV_A_DATA_MEMORY_END - REV_A_DATA_MEMORY_BEGIN + 1)
383
384#define REV_B_DATA_MEMORY_BEGIN 0x1000
385#define REV_B_DATA_MEMORY_END 0x2BFF
386#define REV_B_DATA_MEMORY_UNIT_LENGTH 0x0080
387#define REV_B_DATA_MEMORY_LENGTH (REV_B_DATA_MEMORY_END - REV_B_DATA_MEMORY_BEGIN + 1)
388
389
390#define NUM_UNITS_KERNEL_CODE 16
391#define NUM_UNITS_KERNEL_DATA 2
392
393#define NUM_UNITS_KERNEL_CODE_WITH_HSP 16
394#define NUM_UNITS_KERNEL_DATA_WITH_HSP 5
395
396/*
397 * Kernel data layout
398 */
399
400#define DP_SHIFT_COUNT 7
401
402#define KDATA_BASE_ADDR 0x1000
403#define KDATA_BASE_ADDR2 0x1080
404
405#define KDATA_TASK0 (KDATA_BASE_ADDR + 0x0000)
406#define KDATA_TASK1 (KDATA_BASE_ADDR + 0x0001)
407#define KDATA_TASK2 (KDATA_BASE_ADDR + 0x0002)
408#define KDATA_TASK3 (KDATA_BASE_ADDR + 0x0003)
409#define KDATA_TASK4 (KDATA_BASE_ADDR + 0x0004)
410#define KDATA_TASK5 (KDATA_BASE_ADDR + 0x0005)
411#define KDATA_TASK6 (KDATA_BASE_ADDR + 0x0006)
412#define KDATA_TASK7 (KDATA_BASE_ADDR + 0x0007)
413#define KDATA_TASK_ENDMARK (KDATA_BASE_ADDR + 0x0008)
414
415#define KDATA_CURRENT_TASK (KDATA_BASE_ADDR + 0x0009)
416#define KDATA_TASK_SWITCH (KDATA_BASE_ADDR + 0x000A)
417
418#define KDATA_INSTANCE0_POS3D (KDATA_BASE_ADDR + 0x000B)
419#define KDATA_INSTANCE1_POS3D (KDATA_BASE_ADDR + 0x000C)
420#define KDATA_INSTANCE2_POS3D (KDATA_BASE_ADDR + 0x000D)
421#define KDATA_INSTANCE3_POS3D (KDATA_BASE_ADDR + 0x000E)
422#define KDATA_INSTANCE4_POS3D (KDATA_BASE_ADDR + 0x000F)
423#define KDATA_INSTANCE5_POS3D (KDATA_BASE_ADDR + 0x0010)
424#define KDATA_INSTANCE6_POS3D (KDATA_BASE_ADDR + 0x0011)
425#define KDATA_INSTANCE7_POS3D (KDATA_BASE_ADDR + 0x0012)
426#define KDATA_INSTANCE8_POS3D (KDATA_BASE_ADDR + 0x0013)
427#define KDATA_INSTANCE_POS3D_ENDMARK (KDATA_BASE_ADDR + 0x0014)
428
429#define KDATA_INSTANCE0_SPKVIRT (KDATA_BASE_ADDR + 0x0015)
430#define KDATA_INSTANCE_SPKVIRT_ENDMARK (KDATA_BASE_ADDR + 0x0016)
431
432#define KDATA_INSTANCE0_SPDIF (KDATA_BASE_ADDR + 0x0017)
433#define KDATA_INSTANCE_SPDIF_ENDMARK (KDATA_BASE_ADDR + 0x0018)
434
435#define KDATA_INSTANCE0_MODEM (KDATA_BASE_ADDR + 0x0019)
436#define KDATA_INSTANCE_MODEM_ENDMARK (KDATA_BASE_ADDR + 0x001A)
437
438#define KDATA_INSTANCE0_SRC (KDATA_BASE_ADDR + 0x001B)
439#define KDATA_INSTANCE1_SRC (KDATA_BASE_ADDR + 0x001C)
440#define KDATA_INSTANCE_SRC_ENDMARK (KDATA_BASE_ADDR + 0x001D)
441
442#define KDATA_INSTANCE0_MINISRC (KDATA_BASE_ADDR + 0x001E)
443#define KDATA_INSTANCE1_MINISRC (KDATA_BASE_ADDR + 0x001F)
444#define KDATA_INSTANCE2_MINISRC (KDATA_BASE_ADDR + 0x0020)
445#define KDATA_INSTANCE3_MINISRC (KDATA_BASE_ADDR + 0x0021)
446#define KDATA_INSTANCE_MINISRC_ENDMARK (KDATA_BASE_ADDR + 0x0022)
447
448#define KDATA_INSTANCE0_CPYTHRU (KDATA_BASE_ADDR + 0x0023)
449#define KDATA_INSTANCE1_CPYTHRU (KDATA_BASE_ADDR + 0x0024)
450#define KDATA_INSTANCE_CPYTHRU_ENDMARK (KDATA_BASE_ADDR + 0x0025)
451
452#define KDATA_CURRENT_DMA (KDATA_BASE_ADDR + 0x0026)
453#define KDATA_DMA_SWITCH (KDATA_BASE_ADDR + 0x0027)
454#define KDATA_DMA_ACTIVE (KDATA_BASE_ADDR + 0x0028)
455
456#define KDATA_DMA_XFER0 (KDATA_BASE_ADDR + 0x0029)
457#define KDATA_DMA_XFER1 (KDATA_BASE_ADDR + 0x002A)
458#define KDATA_DMA_XFER2 (KDATA_BASE_ADDR + 0x002B)
459#define KDATA_DMA_XFER3 (KDATA_BASE_ADDR + 0x002C)
460#define KDATA_DMA_XFER4 (KDATA_BASE_ADDR + 0x002D)
461#define KDATA_DMA_XFER5 (KDATA_BASE_ADDR + 0x002E)
462#define KDATA_DMA_XFER6 (KDATA_BASE_ADDR + 0x002F)
463#define KDATA_DMA_XFER7 (KDATA_BASE_ADDR + 0x0030)
464#define KDATA_DMA_XFER8 (KDATA_BASE_ADDR + 0x0031)
465#define KDATA_DMA_XFER_ENDMARK (KDATA_BASE_ADDR + 0x0032)
466
467#define KDATA_I2S_SAMPLE_COUNT (KDATA_BASE_ADDR + 0x0033)
468#define KDATA_I2S_INT_METER (KDATA_BASE_ADDR + 0x0034)
469#define KDATA_I2S_ACTIVE (KDATA_BASE_ADDR + 0x0035)
470
471#define KDATA_TIMER_COUNT_RELOAD (KDATA_BASE_ADDR + 0x0036)
472#define KDATA_TIMER_COUNT_CURRENT (KDATA_BASE_ADDR + 0x0037)
473
474#define KDATA_HALT_SYNCH_CLIENT (KDATA_BASE_ADDR + 0x0038)
475#define KDATA_HALT_SYNCH_DMA (KDATA_BASE_ADDR + 0x0039)
476#define KDATA_HALT_ACKNOWLEDGE (KDATA_BASE_ADDR + 0x003A)
477
478#define KDATA_ADC1_XFER0 (KDATA_BASE_ADDR + 0x003B)
479#define KDATA_ADC1_XFER_ENDMARK (KDATA_BASE_ADDR + 0x003C)
480#define KDATA_ADC1_LEFT_VOLUME (KDATA_BASE_ADDR + 0x003D)
481#define KDATA_ADC1_RIGHT_VOLUME (KDATA_BASE_ADDR + 0x003E)
482#define KDATA_ADC1_LEFT_SUR_VOL (KDATA_BASE_ADDR + 0x003F)
483#define KDATA_ADC1_RIGHT_SUR_VOL (KDATA_BASE_ADDR + 0x0040)
484
485#define KDATA_ADC2_XFER0 (KDATA_BASE_ADDR + 0x0041)
486#define KDATA_ADC2_XFER_ENDMARK (KDATA_BASE_ADDR + 0x0042)
487#define KDATA_ADC2_LEFT_VOLUME (KDATA_BASE_ADDR + 0x0043)
488#define KDATA_ADC2_RIGHT_VOLUME (KDATA_BASE_ADDR + 0x0044)
489#define KDATA_ADC2_LEFT_SUR_VOL (KDATA_BASE_ADDR + 0x0045)
490#define KDATA_ADC2_RIGHT_SUR_VOL (KDATA_BASE_ADDR + 0x0046)
491
492#define KDATA_CD_XFER0 (KDATA_BASE_ADDR + 0x0047)
493#define KDATA_CD_XFER_ENDMARK (KDATA_BASE_ADDR + 0x0048)
494#define KDATA_CD_LEFT_VOLUME (KDATA_BASE_ADDR + 0x0049)
495#define KDATA_CD_RIGHT_VOLUME (KDATA_BASE_ADDR + 0x004A)
496#define KDATA_CD_LEFT_SUR_VOL (KDATA_BASE_ADDR + 0x004B)
497#define KDATA_CD_RIGHT_SUR_VOL (KDATA_BASE_ADDR + 0x004C)
498
499#define KDATA_MIC_XFER0 (KDATA_BASE_ADDR + 0x004D)
500#define KDATA_MIC_XFER_ENDMARK (KDATA_BASE_ADDR + 0x004E)
501#define KDATA_MIC_VOLUME (KDATA_BASE_ADDR + 0x004F)
502#define KDATA_MIC_SUR_VOL (KDATA_BASE_ADDR + 0x0050)
503
504#define KDATA_I2S_XFER0 (KDATA_BASE_ADDR + 0x0051)
505#define KDATA_I2S_XFER_ENDMARK (KDATA_BASE_ADDR + 0x0052)
506
507#define KDATA_CHI_XFER0 (KDATA_BASE_ADDR + 0x0053)
508#define KDATA_CHI_XFER_ENDMARK (KDATA_BASE_ADDR + 0x0054)
509
510#define KDATA_SPDIF_XFER (KDATA_BASE_ADDR + 0x0055)
511#define KDATA_SPDIF_CURRENT_FRAME (KDATA_BASE_ADDR + 0x0056)
512#define KDATA_SPDIF_FRAME0 (KDATA_BASE_ADDR + 0x0057)
513#define KDATA_SPDIF_FRAME1 (KDATA_BASE_ADDR + 0x0058)
514#define KDATA_SPDIF_FRAME2 (KDATA_BASE_ADDR + 0x0059)
515
516#define KDATA_SPDIF_REQUEST (KDATA_BASE_ADDR + 0x005A)
517#define KDATA_SPDIF_TEMP (KDATA_BASE_ADDR + 0x005B)
518
519#define KDATA_SPDIFIN_XFER0 (KDATA_BASE_ADDR + 0x005C)
520#define KDATA_SPDIFIN_XFER_ENDMARK (KDATA_BASE_ADDR + 0x005D)
521#define KDATA_SPDIFIN_INT_METER (KDATA_BASE_ADDR + 0x005E)
522
523#define KDATA_DSP_RESET_COUNT (KDATA_BASE_ADDR + 0x005F)
524#define KDATA_DEBUG_OUTPUT (KDATA_BASE_ADDR + 0x0060)
525
526#define KDATA_KERNEL_ISR_LIST (KDATA_BASE_ADDR + 0x0061)
527
528#define KDATA_KERNEL_ISR_CBSR1 (KDATA_BASE_ADDR + 0x0062)
529#define KDATA_KERNEL_ISR_CBER1 (KDATA_BASE_ADDR + 0x0063)
530#define KDATA_KERNEL_ISR_CBCR (KDATA_BASE_ADDR + 0x0064)
531#define KDATA_KERNEL_ISR_AR0 (KDATA_BASE_ADDR + 0x0065)
532#define KDATA_KERNEL_ISR_AR1 (KDATA_BASE_ADDR + 0x0066)
533#define KDATA_KERNEL_ISR_AR2 (KDATA_BASE_ADDR + 0x0067)
534#define KDATA_KERNEL_ISR_AR3 (KDATA_BASE_ADDR + 0x0068)
535#define KDATA_KERNEL_ISR_AR4 (KDATA_BASE_ADDR + 0x0069)
536#define KDATA_KERNEL_ISR_AR5 (KDATA_BASE_ADDR + 0x006A)
537#define KDATA_KERNEL_ISR_BRCR (KDATA_BASE_ADDR + 0x006B)
538#define KDATA_KERNEL_ISR_PASR (KDATA_BASE_ADDR + 0x006C)
539#define KDATA_KERNEL_ISR_PAER (KDATA_BASE_ADDR + 0x006D)
540
541#define KDATA_CLIENT_SCRATCH0 (KDATA_BASE_ADDR + 0x006E)
542#define KDATA_CLIENT_SCRATCH1 (KDATA_BASE_ADDR + 0x006F)
543#define KDATA_KERNEL_SCRATCH (KDATA_BASE_ADDR + 0x0070)
544#define KDATA_KERNEL_ISR_SCRATCH (KDATA_BASE_ADDR + 0x0071)
545
546#define KDATA_OUEUE_LEFT (KDATA_BASE_ADDR + 0x0072)
547#define KDATA_QUEUE_RIGHT (KDATA_BASE_ADDR + 0x0073)
548
549#define KDATA_ADC1_REQUEST (KDATA_BASE_ADDR + 0x0074)
550#define KDATA_ADC2_REQUEST (KDATA_BASE_ADDR + 0x0075)
551#define KDATA_CD_REQUEST (KDATA_BASE_ADDR + 0x0076)
552#define KDATA_MIC_REQUEST (KDATA_BASE_ADDR + 0x0077)
553
554#define KDATA_ADC1_MIXER_REQUEST (KDATA_BASE_ADDR + 0x0078)
555#define KDATA_ADC2_MIXER_REQUEST (KDATA_BASE_ADDR + 0x0079)
556#define KDATA_CD_MIXER_REQUEST (KDATA_BASE_ADDR + 0x007A)
557#define KDATA_MIC_MIXER_REQUEST (KDATA_BASE_ADDR + 0x007B)
558#define KDATA_MIC_SYNC_COUNTER (KDATA_BASE_ADDR + 0x007C)
559
560/*
561 * second 'segment' (?) reserved for mixer
562 * buffers..
563 */
564
565#define KDATA_MIXER_WORD0 (KDATA_BASE_ADDR2 + 0x0000)
566#define KDATA_MIXER_WORD1 (KDATA_BASE_ADDR2 + 0x0001)
567#define KDATA_MIXER_WORD2 (KDATA_BASE_ADDR2 + 0x0002)
568#define KDATA_MIXER_WORD3 (KDATA_BASE_ADDR2 + 0x0003)
569#define KDATA_MIXER_WORD4 (KDATA_BASE_ADDR2 + 0x0004)
570#define KDATA_MIXER_WORD5 (KDATA_BASE_ADDR2 + 0x0005)
571#define KDATA_MIXER_WORD6 (KDATA_BASE_ADDR2 + 0x0006)
572#define KDATA_MIXER_WORD7 (KDATA_BASE_ADDR2 + 0x0007)
573#define KDATA_MIXER_WORD8 (KDATA_BASE_ADDR2 + 0x0008)
574#define KDATA_MIXER_WORD9 (KDATA_BASE_ADDR2 + 0x0009)
575#define KDATA_MIXER_WORDA (KDATA_BASE_ADDR2 + 0x000A)
576#define KDATA_MIXER_WORDB (KDATA_BASE_ADDR2 + 0x000B)
577#define KDATA_MIXER_WORDC (KDATA_BASE_ADDR2 + 0x000C)
578#define KDATA_MIXER_WORDD (KDATA_BASE_ADDR2 + 0x000D)
579#define KDATA_MIXER_WORDE (KDATA_BASE_ADDR2 + 0x000E)
580#define KDATA_MIXER_WORDF (KDATA_BASE_ADDR2 + 0x000F)
581
582#define KDATA_MIXER_XFER0 (KDATA_BASE_ADDR2 + 0x0010)
583#define KDATA_MIXER_XFER1 (KDATA_BASE_ADDR2 + 0x0011)
584#define KDATA_MIXER_XFER2 (KDATA_BASE_ADDR2 + 0x0012)
585#define KDATA_MIXER_XFER3 (KDATA_BASE_ADDR2 + 0x0013)
586#define KDATA_MIXER_XFER4 (KDATA_BASE_ADDR2 + 0x0014)
587#define KDATA_MIXER_XFER5 (KDATA_BASE_ADDR2 + 0x0015)
588#define KDATA_MIXER_XFER6 (KDATA_BASE_ADDR2 + 0x0016)
589#define KDATA_MIXER_XFER7 (KDATA_BASE_ADDR2 + 0x0017)
590#define KDATA_MIXER_XFER8 (KDATA_BASE_ADDR2 + 0x0018)
591#define KDATA_MIXER_XFER9 (KDATA_BASE_ADDR2 + 0x0019)
592#define KDATA_MIXER_XFER_ENDMARK (KDATA_BASE_ADDR2 + 0x001A)
593
594#define KDATA_MIXER_TASK_NUMBER (KDATA_BASE_ADDR2 + 0x001B)
595#define KDATA_CURRENT_MIXER (KDATA_BASE_ADDR2 + 0x001C)
596#define KDATA_MIXER_ACTIVE (KDATA_BASE_ADDR2 + 0x001D)
597#define KDATA_MIXER_BANK_STATUS (KDATA_BASE_ADDR2 + 0x001E)
598#define KDATA_DAC_LEFT_VOLUME (KDATA_BASE_ADDR2 + 0x001F)
599#define KDATA_DAC_RIGHT_VOLUME (KDATA_BASE_ADDR2 + 0x0020)
600
601#define MAX_INSTANCE_MINISRC (KDATA_INSTANCE_MINISRC_ENDMARK - KDATA_INSTANCE0_MINISRC)
602#define MAX_VIRTUAL_DMA_CHANNELS (KDATA_DMA_XFER_ENDMARK - KDATA_DMA_XFER0)
603#define MAX_VIRTUAL_MIXER_CHANNELS (KDATA_MIXER_XFER_ENDMARK - KDATA_MIXER_XFER0)
604#define MAX_VIRTUAL_ADC1_CHANNELS (KDATA_ADC1_XFER_ENDMARK - KDATA_ADC1_XFER0)
605
606/*
607 * client data area offsets
608 */
609#define CDATA_INSTANCE_READY 0x00
610
611#define CDATA_HOST_SRC_ADDRL 0x01
612#define CDATA_HOST_SRC_ADDRH 0x02
613#define CDATA_HOST_SRC_END_PLUS_1L 0x03
614#define CDATA_HOST_SRC_END_PLUS_1H 0x04
615#define CDATA_HOST_SRC_CURRENTL 0x05
616#define CDATA_HOST_SRC_CURRENTH 0x06
617
618#define CDATA_IN_BUF_CONNECT 0x07
619#define CDATA_OUT_BUF_CONNECT 0x08
620
621#define CDATA_IN_BUF_BEGIN 0x09
622#define CDATA_IN_BUF_END_PLUS_1 0x0A
623#define CDATA_IN_BUF_HEAD 0x0B
624#define CDATA_IN_BUF_TAIL 0x0C
625#define CDATA_OUT_BUF_BEGIN 0x0D
626#define CDATA_OUT_BUF_END_PLUS_1 0x0E
627#define CDATA_OUT_BUF_HEAD 0x0F
628#define CDATA_OUT_BUF_TAIL 0x10
629
630#define CDATA_DMA_CONTROL 0x11
631#define CDATA_RESERVED 0x12
632
633#define CDATA_FREQUENCY 0x13
634#define CDATA_LEFT_VOLUME 0x14
635#define CDATA_RIGHT_VOLUME 0x15
636#define CDATA_LEFT_SUR_VOL 0x16
637#define CDATA_RIGHT_SUR_VOL 0x17
638
639#define CDATA_HEADER_LEN 0x18
640
641#define SRC3_DIRECTION_OFFSET CDATA_HEADER_LEN
642#define SRC3_MODE_OFFSET (CDATA_HEADER_LEN + 1)
643#define SRC3_WORD_LENGTH_OFFSET (CDATA_HEADER_LEN + 2)
644#define SRC3_PARAMETER_OFFSET (CDATA_HEADER_LEN + 3)
645#define SRC3_COEFF_ADDR_OFFSET (CDATA_HEADER_LEN + 8)
646#define SRC3_FILTAP_ADDR_OFFSET (CDATA_HEADER_LEN + 10)
647#define SRC3_TEMP_INBUF_ADDR_OFFSET (CDATA_HEADER_LEN + 16)
648#define SRC3_TEMP_OUTBUF_ADDR_OFFSET (CDATA_HEADER_LEN + 17)
649
650#define MINISRC_IN_BUFFER_SIZE ( 0x50 * 2 )
651#define MINISRC_OUT_BUFFER_SIZE ( 0x50 * 2 * 2)
652#define MINISRC_TMP_BUFFER_SIZE ( 112 + ( MINISRC_BIQUAD_STAGE * 3 + 4 ) * 2 * 2 )
653#define MINISRC_BIQUAD_STAGE 2
654#define MINISRC_COEF_LOC 0x175
655
656#define DMACONTROL_BLOCK_MASK 0x000F
657#define DMAC_BLOCK0_SELECTOR 0x0000
658#define DMAC_BLOCK1_SELECTOR 0x0001
659#define DMAC_BLOCK2_SELECTOR 0x0002
660#define DMAC_BLOCK3_SELECTOR 0x0003
661#define DMAC_BLOCK4_SELECTOR 0x0004
662#define DMAC_BLOCK5_SELECTOR 0x0005
663#define DMAC_BLOCK6_SELECTOR 0x0006
664#define DMAC_BLOCK7_SELECTOR 0x0007
665#define DMAC_BLOCK8_SELECTOR 0x0008
666#define DMAC_BLOCK9_SELECTOR 0x0009
667#define DMAC_BLOCKA_SELECTOR 0x000A
668#define DMAC_BLOCKB_SELECTOR 0x000B
669#define DMAC_BLOCKC_SELECTOR 0x000C
670#define DMAC_BLOCKD_SELECTOR 0x000D
671#define DMAC_BLOCKE_SELECTOR 0x000E
672#define DMAC_BLOCKF_SELECTOR 0x000F
673#define DMACONTROL_PAGE_MASK 0x00F0
674#define DMAC_PAGE0_SELECTOR 0x0030
675#define DMAC_PAGE1_SELECTOR 0x0020
676#define DMAC_PAGE2_SELECTOR 0x0010
677#define DMAC_PAGE3_SELECTOR 0x0000
678#define DMACONTROL_AUTOREPEAT 0x1000
679#define DMACONTROL_STOPPED 0x2000
680#define DMACONTROL_DIRECTION 0x0100
681
682/*
683 * an arbitrary volume we set the internal
684 * volume settings to so that the ac97 volume
685 * range is a little less insane. 0x7fff is
686 * max.
687 */
688#define ARB_VOLUME ( 0x6800 )
689
690/*
691 */
692
693struct m3_list {
694 int curlen;
695 int mem_addr;
696 int max;
697};
698
699struct m3_dma {
700
701 int number;
702 struct snd_pcm_substream *substream;
703
704 struct assp_instance {
705 unsigned short code, data;
706 } inst;
707
708 int running;
709 int opened;
710
711 unsigned long buffer_addr;
712 int dma_size;
713 int period_size;
714 unsigned int hwptr;
715 int count;
716
717 int index[3];
718 struct m3_list *index_list[3];
719
720 int in_lists;
721
722 struct list_head list;
723
724};
725
726struct snd_m3 {
727
728 struct snd_card *card;
729
730 unsigned long iobase;
731
732 int irq;
733 unsigned int allegro_flag : 1;
734
735 struct snd_ac97 *ac97;
736
737 struct snd_pcm *pcm;
738
739 struct pci_dev *pci;
740
741 int dacs_active;
742 int timer_users;
743
744 struct m3_list msrc_list;
745 struct m3_list mixer_list;
746 struct m3_list adc1_list;
747 struct m3_list dma_list;
748
749 /* for storing reset state..*/
750 u8 reset_state;
751
752 int external_amp;
753 int amp_gpio; /* gpio pin # for external amp, -1 = default */
754 unsigned int hv_config; /* hardware-volume config bits */
755 unsigned irda_workaround :1; /* avoid to touch 0x10 on GPIO_DIRECTION
756 (e.g. for IrDA on Dell Inspirons) */
757 unsigned is_omnibook :1; /* Do HP OmniBook GPIO magic? */
758
759 /* midi */
760 struct snd_rawmidi *rmidi;
761
762 /* pcm streams */
763 int num_substreams;
764 struct m3_dma *substreams;
765
766 spinlock_t reg_lock;
767
768#ifdef CONFIG_SND_MAESTRO3_INPUT
769 struct input_dev *input_dev;
770 char phys[64]; /* physical device path */
771#else
772 struct snd_kcontrol *master_switch;
773 struct snd_kcontrol *master_volume;
774#endif
775 struct work_struct hwvol_work;
776
777 unsigned int in_suspend;
778
779#ifdef CONFIG_PM_SLEEP
780 u16 *suspend_mem;
781#endif
782
783 const struct firmware *assp_kernel_image;
784 const struct firmware *assp_minisrc_image;
785};
786
787/*
788 * pci ids
789 */
790static const struct pci_device_id snd_m3_ids[] = {
791 {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_ALLEGRO_1, PCI_ANY_ID, PCI_ANY_ID,
792 PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
793 {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_ALLEGRO, PCI_ANY_ID, PCI_ANY_ID,
794 PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
795 {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_CANYON3D_2LE, PCI_ANY_ID, PCI_ANY_ID,
796 PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
797 {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_CANYON3D_2, PCI_ANY_ID, PCI_ANY_ID,
798 PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
799 {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_MAESTRO3, PCI_ANY_ID, PCI_ANY_ID,
800 PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
801 {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_MAESTRO3_1, PCI_ANY_ID, PCI_ANY_ID,
802 PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
803 {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_MAESTRO3_HW, PCI_ANY_ID, PCI_ANY_ID,
804 PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
805 {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_MAESTRO3_2, PCI_ANY_ID, PCI_ANY_ID,
806 PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
807 {0,},
808};
809
810MODULE_DEVICE_TABLE(pci, snd_m3_ids);
811
812static const struct snd_pci_quirk m3_amp_quirk_list[] = {
813 SND_PCI_QUIRK(0x0E11, 0x0094, "Compaq Evo N600c", 0x0c),
814 SND_PCI_QUIRK(0x10f7, 0x833e, "Panasonic CF-28", 0x0d),
815 SND_PCI_QUIRK(0x10f7, 0x833d, "Panasonic CF-72", 0x0d),
816 SND_PCI_QUIRK(0x1033, 0x80f1, "NEC LM800J/7", 0x03),
817 SND_PCI_QUIRK(0x1509, 0x1740, "LEGEND ZhaoYang 3100CF", 0x03),
818 {0} /* END */
819};
820
821static const struct snd_pci_quirk m3_irda_quirk_list[] = {
822 SND_PCI_QUIRK(0x1028, 0x00b0, "Dell Inspiron 4000", 1),
823 SND_PCI_QUIRK(0x1028, 0x00a4, "Dell Inspiron 8000", 1),
824 SND_PCI_QUIRK(0x1028, 0x00e6, "Dell Inspiron 8100", 1),
825 {0} /* END */
826};
827
828/* hardware volume quirks */
829static const struct snd_pci_quirk m3_hv_quirk_list[] = {
830 /* Allegro chips */
831 SND_PCI_QUIRK(0x0E11, 0x002E, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
832 SND_PCI_QUIRK(0x0E11, 0x0094, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
833 SND_PCI_QUIRK(0x0E11, 0xB112, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
834 SND_PCI_QUIRK(0x0E11, 0xB114, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
835 SND_PCI_QUIRK(0x103C, 0x0012, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
836 SND_PCI_QUIRK(0x103C, 0x0018, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
837 SND_PCI_QUIRK(0x103C, 0x001C, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
838 SND_PCI_QUIRK(0x103C, 0x001D, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
839 SND_PCI_QUIRK(0x103C, 0x001E, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
840 SND_PCI_QUIRK(0x107B, 0x3350, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
841 SND_PCI_QUIRK(0x10F7, 0x8338, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
842 SND_PCI_QUIRK(0x10F7, 0x833C, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
843 SND_PCI_QUIRK(0x10F7, 0x833D, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
844 SND_PCI_QUIRK(0x10F7, 0x833E, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
845 SND_PCI_QUIRK(0x10F7, 0x833F, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
846 SND_PCI_QUIRK(0x13BD, 0x1018, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
847 SND_PCI_QUIRK(0x13BD, 0x1019, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
848 SND_PCI_QUIRK(0x13BD, 0x101A, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
849 SND_PCI_QUIRK(0x14FF, 0x0F03, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
850 SND_PCI_QUIRK(0x14FF, 0x0F04, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
851 SND_PCI_QUIRK(0x14FF, 0x0F05, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
852 SND_PCI_QUIRK(0x156D, 0xB400, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
853 SND_PCI_QUIRK(0x156D, 0xB795, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
854 SND_PCI_QUIRK(0x156D, 0xB797, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
855 SND_PCI_QUIRK(0x156D, 0xC700, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
856 SND_PCI_QUIRK(0x1033, 0x80F1, NULL,
857 HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE),
858 SND_PCI_QUIRK(0x103C, 0x001A, NULL, /* HP OmniBook 6100 */
859 HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE),
860 SND_PCI_QUIRK(0x107B, 0x340A, NULL,
861 HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE),
862 SND_PCI_QUIRK(0x107B, 0x3450, NULL,
863 HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE),
864 SND_PCI_QUIRK(0x109F, 0x3134, NULL,
865 HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE),
866 SND_PCI_QUIRK(0x109F, 0x3161, NULL,
867 HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE),
868 SND_PCI_QUIRK(0x144D, 0x3280, NULL,
869 HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE),
870 SND_PCI_QUIRK(0x144D, 0x3281, NULL,
871 HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE),
872 SND_PCI_QUIRK(0x144D, 0xC002, NULL,
873 HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE),
874 SND_PCI_QUIRK(0x144D, 0xC003, NULL,
875 HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE),
876 SND_PCI_QUIRK(0x1509, 0x1740, NULL,
877 HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE),
878 SND_PCI_QUIRK(0x1610, 0x0010, NULL,
879 HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE),
880 SND_PCI_QUIRK(0x1042, 0x1042, NULL, HV_CTRL_ENABLE),
881 SND_PCI_QUIRK(0x107B, 0x9500, NULL, HV_CTRL_ENABLE),
882 SND_PCI_QUIRK(0x14FF, 0x0F06, NULL, HV_CTRL_ENABLE),
883 SND_PCI_QUIRK(0x1558, 0x8586, NULL, HV_CTRL_ENABLE),
884 SND_PCI_QUIRK(0x161F, 0x2011, NULL, HV_CTRL_ENABLE),
885 /* Maestro3 chips */
886 SND_PCI_QUIRK(0x103C, 0x000E, NULL, HV_CTRL_ENABLE),
887 SND_PCI_QUIRK(0x103C, 0x0010, NULL, HV_CTRL_ENABLE),
888 SND_PCI_QUIRK(0x103C, 0x0011, NULL, HV_CTRL_ENABLE),
889 SND_PCI_QUIRK(0x103C, 0x001B, NULL, HV_CTRL_ENABLE),
890 SND_PCI_QUIRK(0x104D, 0x80A6, NULL, HV_CTRL_ENABLE),
891 SND_PCI_QUIRK(0x104D, 0x80AA, NULL, HV_CTRL_ENABLE),
892 SND_PCI_QUIRK(0x107B, 0x5300, NULL, HV_CTRL_ENABLE),
893 SND_PCI_QUIRK(0x110A, 0x1998, NULL, HV_CTRL_ENABLE),
894 SND_PCI_QUIRK(0x13BD, 0x1015, NULL, HV_CTRL_ENABLE),
895 SND_PCI_QUIRK(0x13BD, 0x101C, NULL, HV_CTRL_ENABLE),
896 SND_PCI_QUIRK(0x13BD, 0x1802, NULL, HV_CTRL_ENABLE),
897 SND_PCI_QUIRK(0x1599, 0x0715, NULL, HV_CTRL_ENABLE),
898 SND_PCI_QUIRK(0x5643, 0x5643, NULL, HV_CTRL_ENABLE),
899 SND_PCI_QUIRK(0x144D, 0x3260, NULL, HV_CTRL_ENABLE | REDUCED_DEBOUNCE),
900 SND_PCI_QUIRK(0x144D, 0x3261, NULL, HV_CTRL_ENABLE | REDUCED_DEBOUNCE),
901 SND_PCI_QUIRK(0x144D, 0xC000, NULL, HV_CTRL_ENABLE | REDUCED_DEBOUNCE),
902 SND_PCI_QUIRK(0x144D, 0xC001, NULL, HV_CTRL_ENABLE | REDUCED_DEBOUNCE),
903 {0} /* END */
904};
905
906/* HP Omnibook quirks */
907static const struct snd_pci_quirk m3_omnibook_quirk_list[] = {
908 SND_PCI_QUIRK_ID(0x103c, 0x0010), /* HP OmniBook 6000 */
909 SND_PCI_QUIRK_ID(0x103c, 0x0011), /* HP OmniBook 500 */
910 {0} /* END */
911};
912
913/*
914 * lowlevel functions
915 */
916
917static inline void snd_m3_outw(struct snd_m3 *chip, u16 value, unsigned long reg)
918{
919 outw(value, chip->iobase + reg);
920}
921
922static inline u16 snd_m3_inw(struct snd_m3 *chip, unsigned long reg)
923{
924 return inw(chip->iobase + reg);
925}
926
927static inline void snd_m3_outb(struct snd_m3 *chip, u8 value, unsigned long reg)
928{
929 outb(value, chip->iobase + reg);
930}
931
932static inline u8 snd_m3_inb(struct snd_m3 *chip, unsigned long reg)
933{
934 return inb(chip->iobase + reg);
935}
936
937/*
938 * access 16bit words to the code or data regions of the dsp's memory.
939 * index addresses 16bit words.
940 */
941static u16 snd_m3_assp_read(struct snd_m3 *chip, u16 region, u16 index)
942{
943 snd_m3_outw(chip, region & MEMTYPE_MASK, DSP_PORT_MEMORY_TYPE);
944 snd_m3_outw(chip, index, DSP_PORT_MEMORY_INDEX);
945 return snd_m3_inw(chip, DSP_PORT_MEMORY_DATA);
946}
947
948static void snd_m3_assp_write(struct snd_m3 *chip, u16 region, u16 index, u16 data)
949{
950 snd_m3_outw(chip, region & MEMTYPE_MASK, DSP_PORT_MEMORY_TYPE);
951 snd_m3_outw(chip, index, DSP_PORT_MEMORY_INDEX);
952 snd_m3_outw(chip, data, DSP_PORT_MEMORY_DATA);
953}
954
955static void snd_m3_assp_halt(struct snd_m3 *chip)
956{
957 chip->reset_state = snd_m3_inb(chip, DSP_PORT_CONTROL_REG_B) & ~REGB_STOP_CLOCK;
958 msleep(10);
959 snd_m3_outb(chip, chip->reset_state & ~REGB_ENABLE_RESET, DSP_PORT_CONTROL_REG_B);
960}
961
962static void snd_m3_assp_continue(struct snd_m3 *chip)
963{
964 snd_m3_outb(chip, chip->reset_state | REGB_ENABLE_RESET, DSP_PORT_CONTROL_REG_B);
965}
966
967
968/*
969 * This makes me sad. the maestro3 has lists
970 * internally that must be packed.. 0 terminates,
971 * apparently, or maybe all unused entries have
972 * to be 0, the lists have static lengths set
973 * by the binary code images.
974 */
975
976static int snd_m3_add_list(struct snd_m3 *chip, struct m3_list *list, u16 val)
977{
978 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
979 list->mem_addr + list->curlen,
980 val);
981 return list->curlen++;
982}
983
984static void snd_m3_remove_list(struct snd_m3 *chip, struct m3_list *list, int index)
985{
986 u16 val;
987 int lastindex = list->curlen - 1;
988
989 if (index != lastindex) {
990 val = snd_m3_assp_read(chip, MEMTYPE_INTERNAL_DATA,
991 list->mem_addr + lastindex);
992 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
993 list->mem_addr + index,
994 val);
995 }
996
997 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
998 list->mem_addr + lastindex,
999 0);
1000
1001 list->curlen--;
1002}
1003
1004static void snd_m3_inc_timer_users(struct snd_m3 *chip)
1005{
1006 chip->timer_users++;
1007 if (chip->timer_users != 1)
1008 return;
1009
1010 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1011 KDATA_TIMER_COUNT_RELOAD,
1012 240);
1013
1014 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1015 KDATA_TIMER_COUNT_CURRENT,
1016 240);
1017
1018 snd_m3_outw(chip,
1019 snd_m3_inw(chip, HOST_INT_CTRL) | CLKRUN_GEN_ENABLE,
1020 HOST_INT_CTRL);
1021}
1022
1023static void snd_m3_dec_timer_users(struct snd_m3 *chip)
1024{
1025 chip->timer_users--;
1026 if (chip->timer_users > 0)
1027 return;
1028
1029 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1030 KDATA_TIMER_COUNT_RELOAD,
1031 0);
1032
1033 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1034 KDATA_TIMER_COUNT_CURRENT,
1035 0);
1036
1037 snd_m3_outw(chip,
1038 snd_m3_inw(chip, HOST_INT_CTRL) & ~CLKRUN_GEN_ENABLE,
1039 HOST_INT_CTRL);
1040}
1041
1042/*
1043 * start/stop
1044 */
1045
1046/* spinlock held! */
1047static int snd_m3_pcm_start(struct snd_m3 *chip, struct m3_dma *s,
1048 struct snd_pcm_substream *subs)
1049{
1050 if (! s || ! subs)
1051 return -EINVAL;
1052
1053 snd_m3_inc_timer_users(chip);
1054 switch (subs->stream) {
1055 case SNDRV_PCM_STREAM_PLAYBACK:
1056 chip->dacs_active++;
1057 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1058 s->inst.data + CDATA_INSTANCE_READY, 1);
1059 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1060 KDATA_MIXER_TASK_NUMBER,
1061 chip->dacs_active);
1062 break;
1063 case SNDRV_PCM_STREAM_CAPTURE:
1064 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1065 KDATA_ADC1_REQUEST, 1);
1066 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1067 s->inst.data + CDATA_INSTANCE_READY, 1);
1068 break;
1069 }
1070 return 0;
1071}
1072
1073/* spinlock held! */
1074static int snd_m3_pcm_stop(struct snd_m3 *chip, struct m3_dma *s,
1075 struct snd_pcm_substream *subs)
1076{
1077 if (! s || ! subs)
1078 return -EINVAL;
1079
1080 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1081 s->inst.data + CDATA_INSTANCE_READY, 0);
1082 snd_m3_dec_timer_users(chip);
1083 switch (subs->stream) {
1084 case SNDRV_PCM_STREAM_PLAYBACK:
1085 chip->dacs_active--;
1086 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1087 KDATA_MIXER_TASK_NUMBER,
1088 chip->dacs_active);
1089 break;
1090 case SNDRV_PCM_STREAM_CAPTURE:
1091 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1092 KDATA_ADC1_REQUEST, 0);
1093 break;
1094 }
1095 return 0;
1096}
1097
1098static int
1099snd_m3_pcm_trigger(struct snd_pcm_substream *subs, int cmd)
1100{
1101 struct snd_m3 *chip = snd_pcm_substream_chip(subs);
1102 struct m3_dma *s = subs->runtime->private_data;
1103 int err = -EINVAL;
1104
1105 if (snd_BUG_ON(!s))
1106 return -ENXIO;
1107
1108 spin_lock(&chip->reg_lock);
1109 switch (cmd) {
1110 case SNDRV_PCM_TRIGGER_START:
1111 case SNDRV_PCM_TRIGGER_RESUME:
1112 if (s->running)
1113 err = -EBUSY;
1114 else {
1115 s->running = 1;
1116 err = snd_m3_pcm_start(chip, s, subs);
1117 }
1118 break;
1119 case SNDRV_PCM_TRIGGER_STOP:
1120 case SNDRV_PCM_TRIGGER_SUSPEND:
1121 if (! s->running)
1122 err = 0; /* should return error? */
1123 else {
1124 s->running = 0;
1125 err = snd_m3_pcm_stop(chip, s, subs);
1126 }
1127 break;
1128 }
1129 spin_unlock(&chip->reg_lock);
1130 return err;
1131}
1132
1133/*
1134 * setup
1135 */
1136static void
1137snd_m3_pcm_setup1(struct snd_m3 *chip, struct m3_dma *s, struct snd_pcm_substream *subs)
1138{
1139 int dsp_in_size, dsp_out_size, dsp_in_buffer, dsp_out_buffer;
1140 struct snd_pcm_runtime *runtime = subs->runtime;
1141
1142 if (subs->stream == SNDRV_PCM_STREAM_PLAYBACK) {
1143 dsp_in_size = MINISRC_IN_BUFFER_SIZE - (0x20 * 2);
1144 dsp_out_size = MINISRC_OUT_BUFFER_SIZE - (0x20 * 2);
1145 } else {
1146 dsp_in_size = MINISRC_IN_BUFFER_SIZE - (0x10 * 2);
1147 dsp_out_size = MINISRC_OUT_BUFFER_SIZE - (0x10 * 2);
1148 }
1149 dsp_in_buffer = s->inst.data + (MINISRC_TMP_BUFFER_SIZE / 2);
1150 dsp_out_buffer = dsp_in_buffer + (dsp_in_size / 2) + 1;
1151
1152 s->dma_size = frames_to_bytes(runtime, runtime->buffer_size);
1153 s->period_size = frames_to_bytes(runtime, runtime->period_size);
1154 s->hwptr = 0;
1155 s->count = 0;
1156
1157#define LO(x) ((x) & 0xffff)
1158#define HI(x) LO((x) >> 16)
1159
1160 /* host dma buffer pointers */
1161 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1162 s->inst.data + CDATA_HOST_SRC_ADDRL,
1163 LO(s->buffer_addr));
1164
1165 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1166 s->inst.data + CDATA_HOST_SRC_ADDRH,
1167 HI(s->buffer_addr));
1168
1169 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1170 s->inst.data + CDATA_HOST_SRC_END_PLUS_1L,
1171 LO(s->buffer_addr + s->dma_size));
1172
1173 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1174 s->inst.data + CDATA_HOST_SRC_END_PLUS_1H,
1175 HI(s->buffer_addr + s->dma_size));
1176
1177 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1178 s->inst.data + CDATA_HOST_SRC_CURRENTL,
1179 LO(s->buffer_addr));
1180
1181 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1182 s->inst.data + CDATA_HOST_SRC_CURRENTH,
1183 HI(s->buffer_addr));
1184#undef LO
1185#undef HI
1186
1187 /* dsp buffers */
1188
1189 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1190 s->inst.data + CDATA_IN_BUF_BEGIN,
1191 dsp_in_buffer);
1192
1193 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1194 s->inst.data + CDATA_IN_BUF_END_PLUS_1,
1195 dsp_in_buffer + (dsp_in_size / 2));
1196
1197 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1198 s->inst.data + CDATA_IN_BUF_HEAD,
1199 dsp_in_buffer);
1200
1201 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1202 s->inst.data + CDATA_IN_BUF_TAIL,
1203 dsp_in_buffer);
1204
1205 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1206 s->inst.data + CDATA_OUT_BUF_BEGIN,
1207 dsp_out_buffer);
1208
1209 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1210 s->inst.data + CDATA_OUT_BUF_END_PLUS_1,
1211 dsp_out_buffer + (dsp_out_size / 2));
1212
1213 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1214 s->inst.data + CDATA_OUT_BUF_HEAD,
1215 dsp_out_buffer);
1216
1217 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1218 s->inst.data + CDATA_OUT_BUF_TAIL,
1219 dsp_out_buffer);
1220}
1221
1222static void snd_m3_pcm_setup2(struct snd_m3 *chip, struct m3_dma *s,
1223 struct snd_pcm_runtime *runtime)
1224{
1225 u32 freq;
1226
1227 /*
1228 * put us in the lists if we're not already there
1229 */
1230 if (! s->in_lists) {
1231 s->index[0] = snd_m3_add_list(chip, s->index_list[0],
1232 s->inst.data >> DP_SHIFT_COUNT);
1233 s->index[1] = snd_m3_add_list(chip, s->index_list[1],
1234 s->inst.data >> DP_SHIFT_COUNT);
1235 s->index[2] = snd_m3_add_list(chip, s->index_list[2],
1236 s->inst.data >> DP_SHIFT_COUNT);
1237 s->in_lists = 1;
1238 }
1239
1240 /* write to 'mono' word */
1241 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1242 s->inst.data + SRC3_DIRECTION_OFFSET + 1,
1243 runtime->channels == 2 ? 0 : 1);
1244 /* write to '8bit' word */
1245 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1246 s->inst.data + SRC3_DIRECTION_OFFSET + 2,
1247 snd_pcm_format_width(runtime->format) == 16 ? 0 : 1);
1248
1249 /* set up dac/adc rate */
1250#ifndef TARGET_OS2
1251 freq = DIV_ROUND_CLOSEST(runtime->rate << 15, 48000);
1252#else
1253 freq = ((runtime->rate << 15) + 24000 ) / 48000;
1254#endif
1255 if (freq)
1256 freq--;
1257
1258 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1259 s->inst.data + CDATA_FREQUENCY,
1260 freq);
1261}
1262
1263
1264static const struct play_vals {
1265 u16 addr, val;
1266} pv[] = {
1267 {CDATA_LEFT_VOLUME, ARB_VOLUME},
1268 {CDATA_RIGHT_VOLUME, ARB_VOLUME},
1269 {SRC3_DIRECTION_OFFSET, 0} ,
1270 /* +1, +2 are stereo/16 bit */
1271 {SRC3_DIRECTION_OFFSET + 3, 0x0000}, /* fraction? */
1272 {SRC3_DIRECTION_OFFSET + 4, 0}, /* first l */
1273 {SRC3_DIRECTION_OFFSET + 5, 0}, /* first r */
1274 {SRC3_DIRECTION_OFFSET + 6, 0}, /* second l */
1275 {SRC3_DIRECTION_OFFSET + 7, 0}, /* second r */
1276 {SRC3_DIRECTION_OFFSET + 8, 0}, /* delta l */
1277 {SRC3_DIRECTION_OFFSET + 9, 0}, /* delta r */
1278 {SRC3_DIRECTION_OFFSET + 10, 0x8000}, /* round */
1279 {SRC3_DIRECTION_OFFSET + 11, 0xFF00}, /* higher bute mark */
1280 {SRC3_DIRECTION_OFFSET + 13, 0}, /* temp0 */
1281 {SRC3_DIRECTION_OFFSET + 14, 0}, /* c fraction */
1282 {SRC3_DIRECTION_OFFSET + 15, 0}, /* counter */
1283 {SRC3_DIRECTION_OFFSET + 16, 8}, /* numin */
1284 {SRC3_DIRECTION_OFFSET + 17, 50*2}, /* numout */
1285 {SRC3_DIRECTION_OFFSET + 18, MINISRC_BIQUAD_STAGE - 1}, /* numstage */
1286 {SRC3_DIRECTION_OFFSET + 20, 0}, /* filtertap */
1287 {SRC3_DIRECTION_OFFSET + 21, 0} /* booster */
1288};
1289
1290
1291/* the mode passed should be already shifted and masked */
1292static void
1293snd_m3_playback_setup(struct snd_m3 *chip, struct m3_dma *s,
1294 struct snd_pcm_substream *subs)
1295{
1296 unsigned int i;
1297
1298 /*
1299 * some per client initializers
1300 */
1301
1302 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1303 s->inst.data + SRC3_DIRECTION_OFFSET + 12,
1304 s->inst.data + 40 + 8);
1305
1306 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1307 s->inst.data + SRC3_DIRECTION_OFFSET + 19,
1308 s->inst.code + MINISRC_COEF_LOC);
1309
1310 /* enable or disable low pass filter? */
1311 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1312 s->inst.data + SRC3_DIRECTION_OFFSET + 22,
1313 subs->runtime->rate > 45000 ? 0xff : 0);
1314
1315 /* tell it which way dma is going? */
1316 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1317 s->inst.data + CDATA_DMA_CONTROL,
1318 DMACONTROL_AUTOREPEAT + DMAC_PAGE3_SELECTOR + DMAC_BLOCKF_SELECTOR);
1319
1320 /*
1321 * set an armload of static initializers
1322 */
1323 for (i = 0; i < ARRAY_SIZE(pv); i++)
1324 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1325 s->inst.data + pv[i].addr, pv[i].val);
1326}
1327
1328/*
1329 * Native record driver
1330 */
1331static const struct rec_vals {
1332 u16 addr, val;
1333} rv[] = {
1334 {CDATA_LEFT_VOLUME, ARB_VOLUME},
1335 {CDATA_RIGHT_VOLUME, ARB_VOLUME},
1336 {SRC3_DIRECTION_OFFSET, 1} ,
1337 /* +1, +2 are stereo/16 bit */
1338 {SRC3_DIRECTION_OFFSET + 3, 0x0000}, /* fraction? */
1339 {SRC3_DIRECTION_OFFSET + 4, 0}, /* first l */
1340 {SRC3_DIRECTION_OFFSET + 5, 0}, /* first r */
1341 {SRC3_DIRECTION_OFFSET + 6, 0}, /* second l */
1342 {SRC3_DIRECTION_OFFSET + 7, 0}, /* second r */
1343 {SRC3_DIRECTION_OFFSET + 8, 0}, /* delta l */
1344 {SRC3_DIRECTION_OFFSET + 9, 0}, /* delta r */
1345 {SRC3_DIRECTION_OFFSET + 10, 0x8000}, /* round */
1346 {SRC3_DIRECTION_OFFSET + 11, 0xFF00}, /* higher bute mark */
1347 {SRC3_DIRECTION_OFFSET + 13, 0}, /* temp0 */
1348 {SRC3_DIRECTION_OFFSET + 14, 0}, /* c fraction */
1349 {SRC3_DIRECTION_OFFSET + 15, 0}, /* counter */
1350 {SRC3_DIRECTION_OFFSET + 16, 50},/* numin */
1351 {SRC3_DIRECTION_OFFSET + 17, 8}, /* numout */
1352 {SRC3_DIRECTION_OFFSET + 18, 0}, /* numstage */
1353 {SRC3_DIRECTION_OFFSET + 19, 0}, /* coef */
1354 {SRC3_DIRECTION_OFFSET + 20, 0}, /* filtertap */
1355 {SRC3_DIRECTION_OFFSET + 21, 0}, /* booster */
1356 {SRC3_DIRECTION_OFFSET + 22, 0xff} /* skip lpf */
1357};
1358
1359static void
1360snd_m3_capture_setup(struct snd_m3 *chip, struct m3_dma *s, struct snd_pcm_substream *subs)
1361{
1362 unsigned int i;
1363
1364 /*
1365 * some per client initializers
1366 */
1367
1368 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1369 s->inst.data + SRC3_DIRECTION_OFFSET + 12,
1370 s->inst.data + 40 + 8);
1371
1372 /* tell it which way dma is going? */
1373 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1374 s->inst.data + CDATA_DMA_CONTROL,
1375 DMACONTROL_DIRECTION + DMACONTROL_AUTOREPEAT +
1376 DMAC_PAGE3_SELECTOR + DMAC_BLOCKF_SELECTOR);
1377
1378 /*
1379 * set an armload of static initializers
1380 */
1381 for (i = 0; i < ARRAY_SIZE(rv); i++)
1382 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1383 s->inst.data + rv[i].addr, rv[i].val);
1384}
1385
1386static int snd_m3_pcm_hw_params(struct snd_pcm_substream *substream,
1387 struct snd_pcm_hw_params *hw_params)
1388{
1389 struct m3_dma *s = substream->runtime->private_data;
1390
1391 /* set buffer address */
1392 s->buffer_addr = substream->runtime->dma_addr;
1393 if (s->buffer_addr & 0x3) {
1394 dev_err(substream->pcm->card->dev, "oh my, not aligned\n");
1395 s->buffer_addr = s->buffer_addr & ~0x3;
1396 }
1397 return 0;
1398}
1399
1400static int snd_m3_pcm_hw_free(struct snd_pcm_substream *substream)
1401{
1402 struct m3_dma *s;
1403
1404 if (substream->runtime->private_data == NULL)
1405 return 0;
1406 s = substream->runtime->private_data;
1407 s->buffer_addr = 0;
1408 return 0;
1409}
1410
1411static int
1412snd_m3_pcm_prepare(struct snd_pcm_substream *subs)
1413{
1414 struct snd_m3 *chip = snd_pcm_substream_chip(subs);
1415 struct snd_pcm_runtime *runtime = subs->runtime;
1416 struct m3_dma *s = runtime->private_data;
1417
1418 if (snd_BUG_ON(!s))
1419 return -ENXIO;
1420
1421 if (runtime->format != SNDRV_PCM_FORMAT_U8 &&
1422 runtime->format != SNDRV_PCM_FORMAT_S16_LE)
1423 return -EINVAL;
1424 if (runtime->rate > 48000 ||
1425 runtime->rate < 8000)
1426 return -EINVAL;
1427
1428 spin_lock_irq(&chip->reg_lock);
1429
1430 snd_m3_pcm_setup1(chip, s, subs);
1431
1432 if (subs->stream == SNDRV_PCM_STREAM_PLAYBACK)
1433 snd_m3_playback_setup(chip, s, subs);
1434 else
1435 snd_m3_capture_setup(chip, s, subs);
1436
1437 snd_m3_pcm_setup2(chip, s, runtime);
1438
1439 spin_unlock_irq(&chip->reg_lock);
1440
1441 return 0;
1442}
1443
1444/*
1445 * get current pointer
1446 */
1447static unsigned int
1448snd_m3_get_pointer(struct snd_m3 *chip, struct m3_dma *s, struct snd_pcm_substream *subs)
1449{
1450 u16 hi = 0, lo = 0;
1451 int retry = 10;
1452 u32 addr;
1453
1454 /*
1455 * try and get a valid answer
1456 */
1457 while (retry--) {
1458 hi = snd_m3_assp_read(chip, MEMTYPE_INTERNAL_DATA,
1459 s->inst.data + CDATA_HOST_SRC_CURRENTH);
1460
1461 lo = snd_m3_assp_read(chip, MEMTYPE_INTERNAL_DATA,
1462 s->inst.data + CDATA_HOST_SRC_CURRENTL);
1463
1464 if (hi == snd_m3_assp_read(chip, MEMTYPE_INTERNAL_DATA,
1465 s->inst.data + CDATA_HOST_SRC_CURRENTH))
1466 break;
1467 }
1468 addr = lo | ((u32)hi<<16);
1469 return (unsigned int)(addr - s->buffer_addr);
1470}
1471
1472static snd_pcm_uframes_t
1473snd_m3_pcm_pointer(struct snd_pcm_substream *subs)
1474{
1475 struct snd_m3 *chip = snd_pcm_substream_chip(subs);
1476 unsigned int ptr;
1477 struct m3_dma *s = subs->runtime->private_data;
1478
1479 if (snd_BUG_ON(!s))
1480 return 0;
1481
1482 spin_lock(&chip->reg_lock);
1483 ptr = snd_m3_get_pointer(chip, s, subs);
1484 spin_unlock(&chip->reg_lock);
1485 return bytes_to_frames(subs->runtime, ptr);
1486}
1487
1488
1489/* update pointer */
1490/* spinlock held! */
1491static void snd_m3_update_ptr(struct snd_m3 *chip, struct m3_dma *s)
1492{
1493 struct snd_pcm_substream *subs = s->substream;
1494 unsigned int hwptr;
1495 int diff;
1496
1497 if (! s->running)
1498 return;
1499
1500 hwptr = snd_m3_get_pointer(chip, s, subs);
1501
1502 /* try to avoid expensive modulo divisions */
1503 if (hwptr >= s->dma_size)
1504 hwptr %= s->dma_size;
1505
1506 diff = s->dma_size + hwptr - s->hwptr;
1507 if (diff >= s->dma_size)
1508 diff %= s->dma_size;
1509
1510 s->hwptr = hwptr;
1511 s->count += diff;
1512
1513 if (s->count >= (signed)s->period_size) {
1514
1515 if (s->count < 2 * (signed)s->period_size)
1516 s->count -= (signed)s->period_size;
1517 else
1518 s->count %= s->period_size;
1519
1520 spin_unlock(&chip->reg_lock);
1521 snd_pcm_period_elapsed(subs);
1522 spin_lock(&chip->reg_lock);
1523 }
1524}
1525
1526/* The m3's hardware volume works by incrementing / decrementing 2 counters
1527 (without wrap around) in response to volume button presses and then
1528 generating an interrupt. The pair of counters is stored in bits 1-3 and 5-7
1529 of a byte wide register. The meaning of bits 0 and 4 is unknown. */
1530static void snd_m3_update_hw_volume(struct work_struct *work)
1531{
1532 struct snd_m3 *chip = container_of(work, struct snd_m3, hwvol_work);
1533 int x, val;
1534
1535 /* Figure out which volume control button was pushed,
1536 based on differences from the default register
1537 values. */
1538 x = inb(chip->iobase + SHADOW_MIX_REG_VOICE) & 0xee;
1539
1540 /* Reset the volume counters to 4. Tests on the allegro integrated
1541 into a Compaq N600C laptop, have revealed that:
1542 1) Writing any value will result in the 2 counters being reset to
1543 4 so writing 0x88 is not strictly necessary
1544 2) Writing to any of the 4 involved registers will reset all 4
1545 of them (and reading them always returns the same value for all
1546 of them)
1547 It could be that a maestro deviates from this, so leave the code
1548 as is. */
1549 outb(0x88, chip->iobase + SHADOW_MIX_REG_VOICE);
1550 outb(0x88, chip->iobase + HW_VOL_COUNTER_VOICE);
1551 outb(0x88, chip->iobase + SHADOW_MIX_REG_MASTER);
1552 outb(0x88, chip->iobase + HW_VOL_COUNTER_MASTER);
1553
1554 /* Ignore spurious HV interrupts during suspend / resume, this avoids
1555 mistaking them for a mute button press. */
1556 if (chip->in_suspend)
1557 return;
1558
1559#ifndef CONFIG_SND_MAESTRO3_INPUT
1560 if (!chip->master_switch || !chip->master_volume)
1561 return;
1562
1563 val = snd_ac97_read(chip->ac97, AC97_MASTER);
1564 switch (x) {
1565 case 0x88:
1566 /* The counters have not changed, yet we've received a HV
1567 interrupt. According to tests run by various people this
1568 happens when pressing the mute button. */
1569 val ^= 0x8000;
1570 break;
1571 case 0xaa:
1572 /* counters increased by 1 -> volume up */
1573 if ((val & 0x7f) > 0)
1574 val--;
1575 if ((val & 0x7f00) > 0)
1576 val -= 0x0100;
1577 break;
1578 case 0x66:
1579 /* counters decreased by 1 -> volume down */
1580 if ((val & 0x7f) < 0x1f)
1581 val++;
1582 if ((val & 0x7f00) < 0x1f00)
1583 val += 0x0100;
1584 break;
1585 }
1586 if (snd_ac97_update(chip->ac97, AC97_MASTER, val))
1587 snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE,
1588 &chip->master_switch->id);
1589#else
1590 if (!chip->input_dev)
1591 return;
1592
1593 val = 0;
1594 switch (x) {
1595 case 0x88:
1596 /* The counters have not changed, yet we've received a HV
1597 interrupt. According to tests run by various people this
1598 happens when pressing the mute button. */
1599 val = KEY_MUTE;
1600 break;
1601 case 0xaa:
1602 /* counters increased by 1 -> volume up */
1603 val = KEY_VOLUMEUP;
1604 break;
1605 case 0x66:
1606 /* counters decreased by 1 -> volume down */
1607 val = KEY_VOLUMEDOWN;
1608 break;
1609 }
1610
1611 if (val) {
1612 input_report_key(chip->input_dev, val, 1);
1613 input_sync(chip->input_dev);
1614 input_report_key(chip->input_dev, val, 0);
1615 input_sync(chip->input_dev);
1616 }
1617#endif
1618}
1619
1620static irqreturn_t snd_m3_interrupt(int irq, void *dev_id)
1621{
1622 struct snd_m3 *chip = dev_id;
1623 u8 status;
1624 int i;
1625
1626 status = inb(chip->iobase + HOST_INT_STATUS);
1627
1628 if (status == 0xff)
1629 return IRQ_NONE;
1630
1631 if (status & HV_INT_PENDING)
1632 schedule_work(&chip->hwvol_work);
1633
1634 /*
1635 * ack an assp int if its running
1636 * and has an int pending
1637 */
1638 if (status & ASSP_INT_PENDING) {
1639 u8 ctl = inb(chip->iobase + ASSP_CONTROL_B);
1640 if (!(ctl & STOP_ASSP_CLOCK)) {
1641 ctl = inb(chip->iobase + ASSP_HOST_INT_STATUS);
1642 if (ctl & DSP2HOST_REQ_TIMER) {
1643 outb(DSP2HOST_REQ_TIMER, chip->iobase + ASSP_HOST_INT_STATUS);
1644 /* update adc/dac info if it was a timer int */
1645 spin_lock(&chip->reg_lock);
1646 for (i = 0; i < chip->num_substreams; i++) {
1647 struct m3_dma *s = &chip->substreams[i];
1648 if (s->running)
1649 snd_m3_update_ptr(chip, s);
1650 }
1651 spin_unlock(&chip->reg_lock);
1652 }
1653 }
1654 }
1655
1656#if 0 /* TODO: not supported yet */
1657 if ((status & MPU401_INT_PENDING) && chip->rmidi)
1658 snd_mpu401_uart_interrupt(irq, chip->rmidi->private_data, regs);
1659#endif
1660
1661 /* ack ints */
1662 outb(status, chip->iobase + HOST_INT_STATUS);
1663
1664 return IRQ_HANDLED;
1665}
1666
1667
1668/*
1669 */
1670
1671static const struct snd_pcm_hardware snd_m3_playback =
1672{
1673 .info = (SNDRV_PCM_INFO_MMAP |
1674 SNDRV_PCM_INFO_INTERLEAVED |
1675 SNDRV_PCM_INFO_MMAP_VALID |
1676 SNDRV_PCM_INFO_BLOCK_TRANSFER |
1677 /*SNDRV_PCM_INFO_PAUSE |*/
1678 SNDRV_PCM_INFO_RESUME),
1679 .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
1680 .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
1681 .rate_min = 8000,
1682 .rate_max = 48000,
1683 .channels_min = 1,
1684 .channels_max = 2,
1685 .buffer_bytes_max = (512*1024),
1686 .period_bytes_min = 64,
1687 .period_bytes_max = (512*1024),
1688 .periods_min = 1,
1689 .periods_max = 1024,
1690};
1691
1692static const struct snd_pcm_hardware snd_m3_capture =
1693{
1694 .info = (SNDRV_PCM_INFO_MMAP |
1695 SNDRV_PCM_INFO_INTERLEAVED |
1696 SNDRV_PCM_INFO_MMAP_VALID |
1697 SNDRV_PCM_INFO_BLOCK_TRANSFER |
1698 /*SNDRV_PCM_INFO_PAUSE |*/
1699 SNDRV_PCM_INFO_RESUME),
1700 .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
1701 .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
1702 .rate_min = 8000,
1703 .rate_max = 48000,
1704 .channels_min = 1,
1705 .channels_max = 2,
1706 .buffer_bytes_max = (512*1024),
1707 .period_bytes_min = 64,
1708 .period_bytes_max = (512*1024),
1709 .periods_min = 1,
1710 .periods_max = 1024,
1711};
1712
1713
1714/*
1715 */
1716
1717static int
1718snd_m3_substream_open(struct snd_m3 *chip, struct snd_pcm_substream *subs)
1719{
1720 int i;
1721 struct m3_dma *s;
1722
1723 spin_lock_irq(&chip->reg_lock);
1724 for (i = 0; i < chip->num_substreams; i++) {
1725 s = &chip->substreams[i];
1726 if (! s->opened)
1727 goto __found;
1728 }
1729 spin_unlock_irq(&chip->reg_lock);
1730 return -ENOMEM;
1731__found:
1732 s->opened = 1;
1733 s->running = 0;
1734 spin_unlock_irq(&chip->reg_lock);
1735
1736 subs->runtime->private_data = s;
1737 s->substream = subs;
1738
1739 /* set list owners */
1740 if (subs->stream == SNDRV_PCM_STREAM_PLAYBACK) {
1741 s->index_list[0] = &chip->mixer_list;
1742 } else
1743 s->index_list[0] = &chip->adc1_list;
1744 s->index_list[1] = &chip->msrc_list;
1745 s->index_list[2] = &chip->dma_list;
1746
1747 return 0;
1748}
1749
1750static void
1751snd_m3_substream_close(struct snd_m3 *chip, struct snd_pcm_substream *subs)
1752{
1753 struct m3_dma *s = subs->runtime->private_data;
1754
1755 if (s == NULL)
1756 return; /* not opened properly */
1757
1758 spin_lock_irq(&chip->reg_lock);
1759 if (s->substream && s->running)
1760 snd_m3_pcm_stop(chip, s, s->substream); /* does this happen? */
1761 if (s->in_lists) {
1762 snd_m3_remove_list(chip, s->index_list[0], s->index[0]);
1763 snd_m3_remove_list(chip, s->index_list[1], s->index[1]);
1764 snd_m3_remove_list(chip, s->index_list[2], s->index[2]);
1765 s->in_lists = 0;
1766 }
1767 s->running = 0;
1768 s->opened = 0;
1769 spin_unlock_irq(&chip->reg_lock);
1770}
1771
1772static int
1773snd_m3_playback_open(struct snd_pcm_substream *subs)
1774{
1775 struct snd_m3 *chip = snd_pcm_substream_chip(subs);
1776 struct snd_pcm_runtime *runtime = subs->runtime;
1777 int err;
1778
1779 if ((err = snd_m3_substream_open(chip, subs)) < 0)
1780 return err;
1781
1782 runtime->hw = snd_m3_playback;
1783
1784 return 0;
1785}
1786
1787static int
1788snd_m3_playback_close(struct snd_pcm_substream *subs)
1789{
1790 struct snd_m3 *chip = snd_pcm_substream_chip(subs);
1791
1792 snd_m3_substream_close(chip, subs);
1793 return 0;
1794}
1795
1796static int
1797snd_m3_capture_open(struct snd_pcm_substream *subs)
1798{
1799 struct snd_m3 *chip = snd_pcm_substream_chip(subs);
1800 struct snd_pcm_runtime *runtime = subs->runtime;
1801 int err;
1802
1803 if ((err = snd_m3_substream_open(chip, subs)) < 0)
1804 return err;
1805
1806 runtime->hw = snd_m3_capture;
1807
1808 return 0;
1809}
1810
1811static int
1812snd_m3_capture_close(struct snd_pcm_substream *subs)
1813{
1814 struct snd_m3 *chip = snd_pcm_substream_chip(subs);
1815
1816 snd_m3_substream_close(chip, subs);
1817 return 0;
1818}
1819
1820/*
1821 * create pcm instance
1822 */
1823
1824static const struct snd_pcm_ops snd_m3_playback_ops = {
1825 .open = snd_m3_playback_open,
1826 .close = snd_m3_playback_close,
1827 .hw_params = snd_m3_pcm_hw_params,
1828 .hw_free = snd_m3_pcm_hw_free,
1829 .prepare = snd_m3_pcm_prepare,
1830 .trigger = snd_m3_pcm_trigger,
1831 .pointer = snd_m3_pcm_pointer,
1832};
1833
1834static const struct snd_pcm_ops snd_m3_capture_ops = {
1835 .open = snd_m3_capture_open,
1836 .close = snd_m3_capture_close,
1837 .hw_params = snd_m3_pcm_hw_params,
1838 .hw_free = snd_m3_pcm_hw_free,
1839 .prepare = snd_m3_pcm_prepare,
1840 .trigger = snd_m3_pcm_trigger,
1841 .pointer = snd_m3_pcm_pointer,
1842};
1843
1844static int
1845snd_m3_pcm(struct snd_m3 * chip, int device)
1846{
1847 struct snd_pcm *pcm;
1848 int err;
1849
1850 err = snd_pcm_new(chip->card, chip->card->driver, device,
1851 MAX_PLAYBACKS, MAX_CAPTURES, &pcm);
1852 if (err < 0)
1853 return err;
1854
1855 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_m3_playback_ops);
1856 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_m3_capture_ops);
1857
1858 pcm->private_data = chip;
1859 pcm->info_flags = 0;
1860 strcpy(pcm->name, chip->card->driver);
1861 chip->pcm = pcm;
1862
1863 snd_pcm_set_managed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV,
1864 &chip->pci->dev, 64*1024, 64*1024);
1865
1866 return 0;
1867}
1868
1869
1870/*
1871 * ac97 interface
1872 */
1873
1874/*
1875 * Wait for the ac97 serial bus to be free.
1876 * return nonzero if the bus is still busy.
1877 */
1878static int snd_m3_ac97_wait(struct snd_m3 *chip)
1879{
1880 int i = 10000;
1881
1882 do {
1883 if (! (snd_m3_inb(chip, 0x30) & 1))
1884 return 0;
1885 cpu_relax();
1886 } while (i-- > 0);
1887
1888 dev_err(chip->card->dev, "ac97 serial bus busy\n");
1889 return 1;
1890}
1891
1892static unsigned short
1893snd_m3_ac97_read(struct snd_ac97 *ac97, unsigned short reg)
1894{
1895 struct snd_m3 *chip = ac97->private_data;
1896 unsigned short data = 0xffff;
1897
1898 if (snd_m3_ac97_wait(chip))
1899 goto fail;
1900 snd_m3_outb(chip, 0x80 | (reg & 0x7f), CODEC_COMMAND);
1901 if (snd_m3_ac97_wait(chip))
1902 goto fail;
1903 data = snd_m3_inw(chip, CODEC_DATA);
1904fail:
1905 return data;
1906}
1907
1908static void
1909snd_m3_ac97_write(struct snd_ac97 *ac97, unsigned short reg, unsigned short val)
1910{
1911 struct snd_m3 *chip = ac97->private_data;
1912
1913 if (snd_m3_ac97_wait(chip))
1914 return;
1915 snd_m3_outw(chip, val, CODEC_DATA);
1916 snd_m3_outb(chip, reg & 0x7f, CODEC_COMMAND);
1917 /*
1918 * Workaround for buggy ES1988 integrated AC'97 codec. It remains silent
1919 * until the MASTER volume or mute is touched (alsactl restore does not
1920 * work).
1921 */
1922 if (ac97->id == 0x45838308 && reg == AC97_MASTER) {
1923 snd_m3_ac97_wait(chip);
1924 snd_m3_outw(chip, val, CODEC_DATA);
1925 snd_m3_outb(chip, reg & 0x7f, CODEC_COMMAND);
1926 }
1927}
1928
1929
1930static void snd_m3_remote_codec_config(struct snd_m3 *chip, int isremote)
1931{
1932 int io = chip->iobase;
1933 u16 tmp;
1934
1935 isremote = isremote ? 1 : 0;
1936
1937 tmp = inw(io + RING_BUS_CTRL_B) & ~SECOND_CODEC_ID_MASK;
1938 /* enable dock on Dell Latitude C810 */
1939 if (chip->pci->subsystem_vendor == 0x1028 &&
1940 chip->pci->subsystem_device == 0x00e5)
1941 tmp |= M3I_DOCK_ENABLE;
1942 outw(tmp | isremote, io + RING_BUS_CTRL_B);
1943 outw((inw(io + SDO_OUT_DEST_CTRL) & ~COMMAND_ADDR_OUT) | isremote,
1944 io + SDO_OUT_DEST_CTRL);
1945 outw((inw(io + SDO_IN_DEST_CTRL) & ~STATUS_ADDR_IN) | isremote,
1946 io + SDO_IN_DEST_CTRL);
1947}
1948
1949/*
1950 * hack, returns non zero on err
1951 */
1952static int snd_m3_try_read_vendor(struct snd_m3 *chip)
1953{
1954 u16 ret;
1955
1956 if (snd_m3_ac97_wait(chip))
1957 return 1;
1958
1959 snd_m3_outb(chip, 0x80 | (AC97_VENDOR_ID1 & 0x7f), 0x30);
1960
1961 if (snd_m3_ac97_wait(chip))
1962 return 1;
1963
1964 ret = snd_m3_inw(chip, 0x32);
1965
1966 return (ret == 0) || (ret == 0xffff);
1967}
1968
1969static void snd_m3_ac97_reset(struct snd_m3 *chip)
1970{
1971 u16 dir;
1972 int delay1 = 0, delay2 = 0, i;
1973 int io = chip->iobase;
1974
1975 if (chip->allegro_flag) {
1976 /*
1977 * the onboard codec on the allegro seems
1978 * to want to wait a very long time before
1979 * coming back to life
1980 */
1981 delay1 = 50;
1982 delay2 = 800;
1983 } else {
1984 /* maestro3 */
1985 delay1 = 20;
1986 delay2 = 500;
1987 }
1988
1989 for (i = 0; i < 5; i++) {
1990 dir = inw(io + GPIO_DIRECTION);
1991 if (!chip->irda_workaround)
1992 dir |= 0x10; /* assuming pci bus master? */
1993
1994 snd_m3_remote_codec_config(chip, 0);
1995
1996 outw(IO_SRAM_ENABLE, io + RING_BUS_CTRL_A);
1997 udelay(20);
1998
1999 outw(dir & ~GPO_PRIMARY_AC97 , io + GPIO_DIRECTION);
2000 outw(~GPO_PRIMARY_AC97 , io + GPIO_MASK);
2001 outw(0, io + GPIO_DATA);
2002 outw(dir | GPO_PRIMARY_AC97, io + GPIO_DIRECTION);
2003
2004 schedule_timeout_uninterruptible(msecs_to_jiffies(delay1));
2005
2006 outw(GPO_PRIMARY_AC97, io + GPIO_DATA);
2007 udelay(5);
2008 /* ok, bring back the ac-link */
2009 outw(IO_SRAM_ENABLE | SERIAL_AC_LINK_ENABLE, io + RING_BUS_CTRL_A);
2010 outw(~0, io + GPIO_MASK);
2011
2012 schedule_timeout_uninterruptible(msecs_to_jiffies(delay2));
2013
2014 if (! snd_m3_try_read_vendor(chip))
2015 break;
2016
2017 delay1 += 10;
2018 delay2 += 100;
2019
2020 dev_dbg(chip->card->dev,
2021 "retrying codec reset with delays of %d and %d ms\n",
2022 delay1, delay2);
2023 }
2024
2025#if 0
2026 /* more gung-ho reset that doesn't
2027 * seem to work anywhere :)
2028 */
2029 tmp = inw(io + RING_BUS_CTRL_A);
2030 outw(RAC_SDFS_ENABLE|LAC_SDFS_ENABLE, io + RING_BUS_CTRL_A);
2031 msleep(20);
2032 outw(tmp, io + RING_BUS_CTRL_A);
2033 msleep(50);
2034#endif
2035}
2036
2037static int snd_m3_mixer(struct snd_m3 *chip)
2038{
2039 struct snd_ac97_bus *pbus;
2040 struct snd_ac97_template ac97;
2041#ifndef CONFIG_SND_MAESTRO3_INPUT
2042 struct snd_ctl_elem_id elem_id;
2043#endif
2044 int err;
2045 static const struct snd_ac97_bus_ops ops = {
2046 .write = snd_m3_ac97_write,
2047 .read = snd_m3_ac97_read,
2048 };
2049
2050 if ((err = snd_ac97_bus(chip->card, 0, &ops, NULL, &pbus)) < 0)
2051 return err;
2052
2053 memset(&ac97, 0, sizeof(ac97));
2054 ac97.private_data = chip;
2055 if ((err = snd_ac97_mixer(pbus, &ac97, &chip->ac97)) < 0)
2056 return err;
2057
2058 /* seems ac97 PCM needs initialization.. hack hack.. */
2059 snd_ac97_write(chip->ac97, AC97_PCM, 0x8000 | (15 << 8) | 15);
2060 schedule_timeout_uninterruptible(msecs_to_jiffies(100));
2061 snd_ac97_write(chip->ac97, AC97_PCM, 0);
2062
2063#ifndef CONFIG_SND_MAESTRO3_INPUT
2064 memset(&elem_id, 0, sizeof(elem_id));
2065 elem_id.iface = SNDRV_CTL_ELEM_IFACE_MIXER;
2066 strcpy(elem_id.name, "Master Playback Switch");
2067 chip->master_switch = snd_ctl_find_id(chip->card, &elem_id);
2068 memset(&elem_id, 0, sizeof(elem_id));
2069 elem_id.iface = SNDRV_CTL_ELEM_IFACE_MIXER;
2070 strcpy(elem_id.name, "Master Playback Volume");
2071 chip->master_volume = snd_ctl_find_id(chip->card, &elem_id);
2072#endif
2073
2074 return 0;
2075}
2076
2077
2078/*
2079 * initialize ASSP
2080 */
2081
2082#define MINISRC_LPF_LEN 10
2083static const u16 minisrc_lpf[MINISRC_LPF_LEN] = {
2084 0X0743, 0X1104, 0X0A4C, 0XF88D, 0X242C,
2085 0X1023, 0X1AA9, 0X0B60, 0XEFDD, 0X186F
2086};
2087
2088static void snd_m3_assp_init(struct snd_m3 *chip)
2089{
2090 unsigned int i;
2091 const __le16 *data;
2092
2093 /* zero kernel data */
2094 for (i = 0; i < (REV_B_DATA_MEMORY_UNIT_LENGTH * NUM_UNITS_KERNEL_DATA) / 2; i++)
2095 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2096 KDATA_BASE_ADDR + i, 0);
2097
2098 /* zero mixer data? */
2099 for (i = 0; i < (REV_B_DATA_MEMORY_UNIT_LENGTH * NUM_UNITS_KERNEL_DATA) / 2; i++)
2100 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2101 KDATA_BASE_ADDR2 + i, 0);
2102
2103 /* init dma pointer */
2104 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2105 KDATA_CURRENT_DMA,
2106 KDATA_DMA_XFER0);
2107
2108 /* write kernel into code memory.. */
2109 data = (const __le16 *)chip->assp_kernel_image->data;
2110 for (i = 0 ; i * 2 < chip->assp_kernel_image->size; i++) {
2111 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_CODE,
2112 REV_B_CODE_MEMORY_BEGIN + i,
2113 le16_to_cpu(data[i]));
2114 }
2115
2116 /*
2117 * We only have this one client and we know that 0x400
2118 * is free in our kernel's mem map, so lets just
2119 * drop it there. It seems that the minisrc doesn't
2120 * need vectors, so we won't bother with them..
2121 */
2122 data = (const __le16 *)chip->assp_minisrc_image->data;
2123 for (i = 0; i * 2 < chip->assp_minisrc_image->size; i++) {
2124 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_CODE,
2125 0x400 + i, le16_to_cpu(data[i]));
2126 }
2127
2128 /*
2129 * write the coefficients for the low pass filter?
2130 */
2131 for (i = 0; i < MINISRC_LPF_LEN ; i++) {
2132 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_CODE,
2133 0x400 + MINISRC_COEF_LOC + i,
2134 minisrc_lpf[i]);
2135 }
2136
2137 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_CODE,
2138 0x400 + MINISRC_COEF_LOC + MINISRC_LPF_LEN,
2139 0x8000);
2140
2141 /*
2142 * the minisrc is the only thing on
2143 * our task list..
2144 */
2145 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2146 KDATA_TASK0,
2147 0x400);
2148
2149 /*
2150 * init the mixer number..
2151 */
2152
2153 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2154 KDATA_MIXER_TASK_NUMBER,0);
2155
2156 /*
2157 * EXTREME KERNEL MASTER VOLUME
2158 */
2159 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2160 KDATA_DAC_LEFT_VOLUME, ARB_VOLUME);
2161 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2162 KDATA_DAC_RIGHT_VOLUME, ARB_VOLUME);
2163
2164 chip->mixer_list.curlen = 0;
2165 chip->mixer_list.mem_addr = KDATA_MIXER_XFER0;
2166 chip->mixer_list.max = MAX_VIRTUAL_MIXER_CHANNELS;
2167 chip->adc1_list.curlen = 0;
2168 chip->adc1_list.mem_addr = KDATA_ADC1_XFER0;
2169 chip->adc1_list.max = MAX_VIRTUAL_ADC1_CHANNELS;
2170 chip->dma_list.curlen = 0;
2171 chip->dma_list.mem_addr = KDATA_DMA_XFER0;
2172 chip->dma_list.max = MAX_VIRTUAL_DMA_CHANNELS;
2173 chip->msrc_list.curlen = 0;
2174 chip->msrc_list.mem_addr = KDATA_INSTANCE0_MINISRC;
2175 chip->msrc_list.max = MAX_INSTANCE_MINISRC;
2176}
2177
2178
2179static int snd_m3_assp_client_init(struct snd_m3 *chip, struct m3_dma *s, int index)
2180{
2181 int data_bytes = 2 * ( MINISRC_TMP_BUFFER_SIZE / 2 +
2182 MINISRC_IN_BUFFER_SIZE / 2 +
2183 1 + MINISRC_OUT_BUFFER_SIZE / 2 + 1 );
2184 int address, i;
2185
2186 /*
2187 * the revb memory map has 0x1100 through 0x1c00
2188 * free.
2189 */
2190
2191 /*
2192 * align instance address to 256 bytes so that its
2193 * shifted list address is aligned.
2194 * list address = (mem address >> 1) >> 7;
2195 */
2196 data_bytes = ALIGN(data_bytes, 256);
2197 address = 0x1100 + ((data_bytes/2) * index);
2198
2199 if ((address + (data_bytes/2)) >= 0x1c00) {
2200 dev_err(chip->card->dev,
2201 "no memory for %d bytes at ind %d (addr 0x%x)\n",
2202 data_bytes, index, address);
2203 return -ENOMEM;
2204 }
2205
2206 s->number = index;
2207 s->inst.code = 0x400;
2208 s->inst.data = address;
2209
2210 for (i = data_bytes / 2; i > 0; address++, i--) {
2211 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2212 address, 0);
2213 }
2214
2215 return 0;
2216}
2217
2218
2219/*
2220 * this works for the reference board, have to find
2221 * out about others
2222 *
2223 * this needs more magic for 4 speaker, but..
2224 */
2225static void
2226snd_m3_amp_enable(struct snd_m3 *chip, int enable)
2227{
2228 int io = chip->iobase;
2229 u16 gpo, polarity;
2230
2231 if (! chip->external_amp)
2232 return;
2233
2234 polarity = enable ? 0 : 1;
2235 polarity = polarity << chip->amp_gpio;
2236 gpo = 1 << chip->amp_gpio;
2237
2238 outw(~gpo, io + GPIO_MASK);
2239
2240 outw(inw(io + GPIO_DIRECTION) | gpo,
2241 io + GPIO_DIRECTION);
2242
2243 outw((GPO_SECONDARY_AC97 | GPO_PRIMARY_AC97 | polarity),
2244 io + GPIO_DATA);
2245
2246 outw(0xffff, io + GPIO_MASK);
2247}
2248
2249static void
2250snd_m3_hv_init(struct snd_m3 *chip)
2251{
2252 unsigned long io = chip->iobase;
2253 u16 val = GPI_VOL_DOWN | GPI_VOL_UP;
2254
2255 if (!chip->is_omnibook)
2256 return;
2257
2258 /*
2259 * Volume buttons on some HP OmniBook laptops
2260 * require some GPIO magic to work correctly.
2261 */
2262 outw(0xffff, io + GPIO_MASK);
2263 outw(0x0000, io + GPIO_DATA);
2264
2265 outw(~val, io + GPIO_MASK);
2266 outw(inw(io + GPIO_DIRECTION) & ~val, io + GPIO_DIRECTION);
2267 outw(val, io + GPIO_MASK);
2268
2269 outw(0xffff, io + GPIO_MASK);
2270}
2271
2272static int
2273snd_m3_chip_init(struct snd_m3 *chip)
2274{
2275 struct pci_dev *pcidev = chip->pci;
2276 unsigned long io = chip->iobase;
2277 u32 n;
2278 u16 w;
2279 u8 t; /* makes as much sense as 'n', no? */
2280
2281 pci_read_config_word(pcidev, PCI_LEGACY_AUDIO_CTRL, &w);
2282 w &= ~(SOUND_BLASTER_ENABLE|FM_SYNTHESIS_ENABLE|
2283 MPU401_IO_ENABLE|MPU401_IRQ_ENABLE|ALIAS_10BIT_IO|
2284 DISABLE_LEGACY);
2285 pci_write_config_word(pcidev, PCI_LEGACY_AUDIO_CTRL, w);
2286
2287 pci_read_config_dword(pcidev, PCI_ALLEGRO_CONFIG, &n);
2288 n &= ~(HV_CTRL_ENABLE | REDUCED_DEBOUNCE | HV_BUTTON_FROM_GD);
2289 n |= chip->hv_config;
2290 /* For some reason we must always use reduced debounce. */
2291 n |= REDUCED_DEBOUNCE;
2292 n |= PM_CTRL_ENABLE | CLK_DIV_BY_49 | USE_PCI_TIMING;
2293 pci_write_config_dword(pcidev, PCI_ALLEGRO_CONFIG, n);
2294
2295 outb(RESET_ASSP, chip->iobase + ASSP_CONTROL_B);
2296 pci_read_config_dword(pcidev, PCI_ALLEGRO_CONFIG, &n);
2297 n &= ~INT_CLK_SELECT;
2298 if (!chip->allegro_flag) {
2299 n &= ~INT_CLK_MULT_ENABLE;
2300 n |= INT_CLK_SRC_NOT_PCI;
2301 }
2302 n &= ~( CLK_MULT_MODE_SELECT | CLK_MULT_MODE_SELECT_2 );
2303 pci_write_config_dword(pcidev, PCI_ALLEGRO_CONFIG, n);
2304
2305 if (chip->allegro_flag) {
2306 pci_read_config_dword(pcidev, PCI_USER_CONFIG, &n);
2307 n |= IN_CLK_12MHZ_SELECT;
2308 pci_write_config_dword(pcidev, PCI_USER_CONFIG, n);
2309 }
2310
2311 t = inb(chip->iobase + ASSP_CONTROL_A);
2312 t &= ~( DSP_CLK_36MHZ_SELECT | ASSP_CLK_49MHZ_SELECT);
2313 t |= ASSP_CLK_49MHZ_SELECT;
2314 t |= ASSP_0_WS_ENABLE;
2315 outb(t, chip->iobase + ASSP_CONTROL_A);
2316
2317 snd_m3_assp_init(chip); /* download DSP code before starting ASSP below */
2318 outb(RUN_ASSP, chip->iobase + ASSP_CONTROL_B);
2319
2320 outb(0x00, io + HARDWARE_VOL_CTRL);
2321 outb(0x88, io + SHADOW_MIX_REG_VOICE);
2322 outb(0x88, io + HW_VOL_COUNTER_VOICE);
2323 outb(0x88, io + SHADOW_MIX_REG_MASTER);
2324 outb(0x88, io + HW_VOL_COUNTER_MASTER);
2325
2326 return 0;
2327}
2328
2329static void
2330snd_m3_enable_ints(struct snd_m3 *chip)
2331{
2332 unsigned long io = chip->iobase;
2333 unsigned short val;
2334
2335 /* TODO: MPU401 not supported yet */
2336 val = ASSP_INT_ENABLE /*| MPU401_INT_ENABLE*/;
2337 if (chip->hv_config & HV_CTRL_ENABLE)
2338 val |= HV_INT_ENABLE;
2339 outb(val, chip->iobase + HOST_INT_STATUS);
2340 outw(val, io + HOST_INT_CTRL);
2341 outb(inb(io + ASSP_CONTROL_C) | ASSP_HOST_INT_ENABLE,
2342 io + ASSP_CONTROL_C);
2343}
2344
2345
2346/*
2347 */
2348
2349static int snd_m3_free(struct snd_m3 *chip)
2350{
2351 struct m3_dma *s;
2352 int i;
2353
2354 cancel_work_sync(&chip->hwvol_work);
2355#ifdef CONFIG_SND_MAESTRO3_INPUT
2356 if (chip->input_dev)
2357 input_unregister_device(chip->input_dev);
2358#endif
2359
2360 if (chip->substreams) {
2361 spin_lock_irq(&chip->reg_lock);
2362 for (i = 0; i < chip->num_substreams; i++) {
2363 s = &chip->substreams[i];
2364 /* check surviving pcms; this should not happen though.. */
2365 if (s->substream && s->running)
2366 snd_m3_pcm_stop(chip, s, s->substream);
2367 }
2368 spin_unlock_irq(&chip->reg_lock);
2369 kfree(chip->substreams);
2370 }
2371 if (chip->iobase) {
2372 outw(0, chip->iobase + HOST_INT_CTRL); /* disable ints */
2373 }
2374
2375#ifdef CONFIG_PM_SLEEP
2376 vfree(chip->suspend_mem);
2377#endif
2378
2379 if (chip->irq >= 0)
2380 free_irq(chip->irq, chip);
2381
2382 if (chip->iobase)
2383 pci_release_regions(chip->pci);
2384
2385 release_firmware(chip->assp_kernel_image);
2386 release_firmware(chip->assp_minisrc_image);
2387
2388 pci_disable_device(chip->pci);
2389 kfree(chip);
2390 return 0;
2391}
2392
2393
2394/*
2395 * APM support
2396 */
2397#ifdef CONFIG_PM_SLEEP
2398static int m3_suspend(struct device *dev)
2399{
2400 struct snd_card *card = dev_get_drvdata(dev);
2401 struct snd_m3 *chip = card->private_data;
2402 int i, dsp_index;
2403
2404 if (chip->suspend_mem == NULL)
2405 return 0;
2406
2407 chip->in_suspend = 1;
2408 cancel_work_sync(&chip->hwvol_work);
2409 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
2410 snd_ac97_suspend(chip->ac97);
2411
2412 msleep(10); /* give the assp a chance to idle.. */
2413
2414 snd_m3_assp_halt(chip);
2415
2416 /* save dsp image */
2417 dsp_index = 0;
2418 for (i = REV_B_CODE_MEMORY_BEGIN; i <= REV_B_CODE_MEMORY_END; i++)
2419 chip->suspend_mem[dsp_index++] =
2420 snd_m3_assp_read(chip, MEMTYPE_INTERNAL_CODE, i);
2421 for (i = REV_B_DATA_MEMORY_BEGIN ; i <= REV_B_DATA_MEMORY_END; i++)
2422 chip->suspend_mem[dsp_index++] =
2423 snd_m3_assp_read(chip, MEMTYPE_INTERNAL_DATA, i);
2424 return 0;
2425}
2426
2427static int m3_resume(struct device *dev)
2428{
2429 struct snd_card *card = dev_get_drvdata(dev);
2430 struct snd_m3 *chip = card->private_data;
2431 int i, dsp_index;
2432
2433 if (chip->suspend_mem == NULL)
2434 return 0;
2435
2436 /* first lets just bring everything back. .*/
2437 snd_m3_outw(chip, 0, 0x54);
2438 snd_m3_outw(chip, 0, 0x56);
2439
2440 snd_m3_chip_init(chip);
2441 snd_m3_assp_halt(chip);
2442 snd_m3_ac97_reset(chip);
2443
2444 /* restore dsp image */
2445 dsp_index = 0;
2446 for (i = REV_B_CODE_MEMORY_BEGIN; i <= REV_B_CODE_MEMORY_END; i++)
2447 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_CODE, i,
2448 chip->suspend_mem[dsp_index++]);
2449 for (i = REV_B_DATA_MEMORY_BEGIN ; i <= REV_B_DATA_MEMORY_END; i++)
2450 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, i,
2451 chip->suspend_mem[dsp_index++]);
2452
2453 /* tell the dma engine to restart itself */
2454 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2455 KDATA_DMA_ACTIVE, 0);
2456
2457 /* restore ac97 registers */
2458 snd_ac97_resume(chip->ac97);
2459
2460 snd_m3_assp_continue(chip);
2461 snd_m3_enable_ints(chip);
2462 snd_m3_amp_enable(chip, 1);
2463
2464 snd_m3_hv_init(chip);
2465
2466 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
2467 chip->in_suspend = 0;
2468 return 0;
2469}
2470
2471static SIMPLE_DEV_PM_OPS(m3_pm, m3_suspend, m3_resume);
2472#define M3_PM_OPS &m3_pm
2473#else
2474#define M3_PM_OPS NULL
2475#endif /* CONFIG_PM_SLEEP */
2476
2477#ifdef CONFIG_SND_MAESTRO3_INPUT
2478static int snd_m3_input_register(struct snd_m3 *chip)
2479{
2480 struct input_dev *input_dev;
2481 int err;
2482
2483 input_dev = input_allocate_device();
2484 if (!input_dev)
2485 return -ENOMEM;
2486
2487 snprintf(chip->phys, sizeof(chip->phys), "pci-%s/input0",
2488 pci_name(chip->pci));
2489
2490 input_dev->name = chip->card->driver;
2491 input_dev->phys = chip->phys;
2492 input_dev->id.bustype = BUS_PCI;
2493 input_dev->id.vendor = chip->pci->vendor;
2494 input_dev->id.product = chip->pci->device;
2495 input_dev->dev.parent = &chip->pci->dev;
2496
2497 __set_bit(EV_KEY, input_dev->evbit);
2498 __set_bit(KEY_MUTE, input_dev->keybit);
2499 __set_bit(KEY_VOLUMEDOWN, input_dev->keybit);
2500 __set_bit(KEY_VOLUMEUP, input_dev->keybit);
2501
2502 err = input_register_device(input_dev);
2503 if (err) {
2504 input_free_device(input_dev);
2505 return err;
2506 }
2507
2508 chip->input_dev = input_dev;
2509 return 0;
2510}
2511#endif /* CONFIG_INPUT */
2512
2513/*
2514 */
2515
2516static int snd_m3_dev_free(struct snd_device *device)
2517{
2518 struct snd_m3 *chip = device->device_data;
2519 return snd_m3_free(chip);
2520}
2521
2522static int
2523snd_m3_create(struct snd_card *card, struct pci_dev *pci,
2524 int enable_amp,
2525 int amp_gpio,
2526 struct snd_m3 **chip_ret)
2527{
2528 struct snd_m3 *chip;
2529 int i, err;
2530 const struct snd_pci_quirk *quirk;
2531 static const struct snd_device_ops ops = {
2532 .dev_free = snd_m3_dev_free,
2533 };
2534
2535 *chip_ret = NULL;
2536
2537 if (pci_enable_device(pci))
2538 return -EIO;
2539
2540 /* check, if we can restrict PCI DMA transfers to 28 bits */
2541 if (dma_set_mask_and_coherent(&pci->dev, DMA_BIT_MASK(28))) {
2542 dev_err(card->dev,
2543 "architecture does not support 28bit PCI busmaster DMA\n");
2544 pci_disable_device(pci);
2545 return -ENXIO;
2546 }
2547
2548 chip = kzalloc(sizeof(*chip), GFP_KERNEL);
2549 if (chip == NULL) {
2550 pci_disable_device(pci);
2551 return -ENOMEM;
2552 }
2553
2554 spin_lock_init(&chip->reg_lock);
2555
2556 switch (pci->device) {
2557 case PCI_DEVICE_ID_ESS_ALLEGRO:
2558 case PCI_DEVICE_ID_ESS_ALLEGRO_1:
2559 case PCI_DEVICE_ID_ESS_CANYON3D_2LE:
2560 case PCI_DEVICE_ID_ESS_CANYON3D_2:
2561 chip->allegro_flag = 1;
2562 break;
2563 }
2564
2565 chip->card = card;
2566 chip->pci = pci;
2567 chip->irq = -1;
2568 INIT_WORK(&chip->hwvol_work, snd_m3_update_hw_volume);
2569
2570 chip->external_amp = enable_amp;
2571 if (amp_gpio >= 0 && amp_gpio <= 0x0f)
2572 chip->amp_gpio = amp_gpio;
2573 else {
2574 quirk = snd_pci_quirk_lookup(pci, m3_amp_quirk_list);
2575 if (quirk) {
2576 dev_info(card->dev, "set amp-gpio for '%s'\n",
2577 snd_pci_quirk_name(quirk));
2578 chip->amp_gpio = quirk->value;
2579 } else if (chip->allegro_flag)
2580 chip->amp_gpio = GPO_EXT_AMP_ALLEGRO;
2581 else /* presumably this is for all 'maestro3's.. */
2582 chip->amp_gpio = GPO_EXT_AMP_M3;
2583 }
2584
2585 quirk = snd_pci_quirk_lookup(pci, m3_irda_quirk_list);
2586 if (quirk) {
2587 dev_info(card->dev, "enabled irda workaround for '%s'\n",
2588 snd_pci_quirk_name(quirk));
2589 chip->irda_workaround = 1;
2590 }
2591 quirk = snd_pci_quirk_lookup(pci, m3_hv_quirk_list);
2592 if (quirk)
2593 chip->hv_config = quirk->value;
2594 if (snd_pci_quirk_lookup(pci, m3_omnibook_quirk_list))
2595 chip->is_omnibook = 1;
2596
2597 chip->num_substreams = NR_DSPS;
2598 chip->substreams = kcalloc(chip->num_substreams, sizeof(struct m3_dma),
2599 GFP_KERNEL);
2600 if (chip->substreams == NULL) {
2601 kfree(chip);
2602 pci_disable_device(pci);
2603 return -ENOMEM;
2604 }
2605
2606 err = request_firmware(&chip->assp_kernel_image,
2607 "ess/maestro3_assp_kernel.fw", &pci->dev);
2608 if (err < 0)
2609 goto free_chip;
2610
2611 err = request_firmware(&chip->assp_minisrc_image,
2612 "ess/maestro3_assp_minisrc.fw", &pci->dev);
2613 if (err < 0)
2614 goto free_chip;
2615
2616 err = pci_request_regions(pci, card->driver);
2617 if (err < 0)
2618 goto free_chip;
2619
2620 chip->iobase = pci_resource_start(pci, 0);
2621
2622 /* just to be sure */
2623 pci_set_master(pci);
2624
2625 snd_m3_chip_init(chip);
2626 snd_m3_assp_halt(chip);
2627
2628 snd_m3_ac97_reset(chip);
2629
2630 snd_m3_amp_enable(chip, 1);
2631
2632 snd_m3_hv_init(chip);
2633
2634 if (request_irq(pci->irq, snd_m3_interrupt, IRQF_SHARED,
2635 KBUILD_MODNAME, chip)) {
2636 dev_err(card->dev, "unable to grab IRQ %d\n", pci->irq);
2637 err = -ENOMEM;
2638 goto free_chip;
2639 }
2640 chip->irq = pci->irq;
2641 card->sync_irq = chip->irq;
2642
2643#ifdef CONFIG_PM_SLEEP
2644 chip->suspend_mem =
2645 vmalloc(array_size(sizeof(u16),
2646 REV_B_CODE_MEMORY_LENGTH +
2647 REV_B_DATA_MEMORY_LENGTH));
2648 if (chip->suspend_mem == NULL)
2649 dev_warn(card->dev, "can't allocate apm buffer\n");
2650#endif
2651
2652 err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
2653 if (err < 0)
2654 goto free_chip;
2655
2656 if ((err = snd_m3_mixer(chip)) < 0)
2657 return err;
2658
2659 for (i = 0; i < chip->num_substreams; i++) {
2660 struct m3_dma *s = &chip->substreams[i];
2661 if ((err = snd_m3_assp_client_init(chip, s, i)) < 0)
2662 return err;
2663 }
2664
2665 if ((err = snd_m3_pcm(chip, 0)) < 0)
2666 return err;
2667
2668#ifdef CONFIG_SND_MAESTRO3_INPUT
2669 if (chip->hv_config & HV_CTRL_ENABLE) {
2670 err = snd_m3_input_register(chip);
2671 if (err)
2672 dev_warn(card->dev,
2673 "Input device registration failed with error %i",
2674 err);
2675 }
2676#endif
2677
2678 snd_m3_enable_ints(chip);
2679 snd_m3_assp_continue(chip);
2680
2681 *chip_ret = chip;
2682
2683 return 0;
2684
2685free_chip:
2686 snd_m3_free(chip);
2687 return err;
2688}
2689
2690/*
2691 */
2692static int
2693snd_m3_probe(struct pci_dev *pci, const struct pci_device_id *pci_id)
2694{
2695 static int dev;
2696 struct snd_card *card;
2697 struct snd_m3 *chip;
2698 int err;
2699
2700 /* don't pick up modems */
2701 if (((pci->class >> 8) & 0xffff) != PCI_CLASS_MULTIMEDIA_AUDIO)
2702 return -ENODEV;
2703
2704 if (dev >= SNDRV_CARDS)
2705 return -ENODEV;
2706 if (!enable[dev]) {
2707 dev++;
2708 return -ENOENT;
2709 }
2710
2711 err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE,
2712 0, &card);
2713 if (err < 0)
2714 return err;
2715
2716 switch (pci->device) {
2717 case PCI_DEVICE_ID_ESS_ALLEGRO:
2718 case PCI_DEVICE_ID_ESS_ALLEGRO_1:
2719 strcpy(card->driver, "Allegro");
2720 break;
2721 case PCI_DEVICE_ID_ESS_CANYON3D_2LE:
2722 case PCI_DEVICE_ID_ESS_CANYON3D_2:
2723 strcpy(card->driver, "Canyon3D-2");
2724 break;
2725 default:
2726 strcpy(card->driver, "Maestro3");
2727 break;
2728 }
2729
2730 err = snd_m3_create(card, pci, external_amp[dev], amp_gpio[dev], &chip);
2731 if (err < 0)
2732 goto free_card;
2733
2734 card->private_data = chip;
2735
2736 sprintf(card->shortname, "ESS %s PCI", card->driver);
2737 sprintf(card->longname, "%s at 0x%lx, irq %d",
2738 card->shortname, chip->iobase, chip->irq);
2739
2740 err = snd_card_register(card);
2741 if (err < 0)
2742 goto free_card;
2743
2744#if 0 /* TODO: not supported yet */
2745 /* TODO enable MIDI IRQ and I/O */
2746 err = snd_mpu401_uart_new(chip->card, 0, MPU401_HW_MPU401,
2747 chip->iobase + MPU401_DATA_PORT,
2748 MPU401_INFO_INTEGRATED | MPU401_INFO_IRQ_HOOK,
2749 -1, &chip->rmidi);
2750 if (err < 0)
2751 dev_warn(card->dev, "no MIDI support.\n");
2752#endif
2753
2754 pci_set_drvdata(pci, card);
2755 dev++;
2756 return 0;
2757
2758free_card:
2759 snd_card_free(card);
2760 return err;
2761}
2762
2763static void snd_m3_remove(struct pci_dev *pci)
2764{
2765 snd_card_free(pci_get_drvdata(pci));
2766}
2767
2768static struct pci_driver m3_driver = {
2769 .name = KBUILD_MODNAME,
2770 .id_table = snd_m3_ids,
2771 .probe = snd_m3_probe,
2772 .remove = snd_m3_remove,
2773 .driver = {
2774 .pm = M3_PM_OPS,
2775 },
2776};
2777
2778module_pci_driver(m3_driver);
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