source: GPL/trunk/alsa-kernel/pci/intel8x0.c@ 680

Last change on this file since 680 was 679, checked in by David Azarewicz, 5 years ago

Merge changes from Paul's uniaud32next branch.
File size: 92.6 KB
Line 
1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * ALSA driver for Intel ICH (i8x0) chipsets
4 *
5 * Copyright (c) 2000 Jaroslav Kysela <perex@perex.cz>
6 *
7 * This code also contains alpha support for SiS 735 chipsets provided
8 * by Mike Pieper <mptei@users.sourceforge.net>. We have no datasheet
9 * for SiS735, so the code is not fully functional.
10 *
11 */
12
13#ifdef TARGET_OS2
14#define KBUILD_MODNAME "intel8x0"
15#endif
16
17#include <linux/io.h>
18#include <linux/delay.h>
19#include <linux/interrupt.h>
20#include <linux/init.h>
21#include <linux/pci.h>
22#include <linux/slab.h>
23#include <linux/module.h>
24#include <sound/core.h>
25#include <sound/pcm.h>
26#include <sound/ac97_codec.h>
27#include <sound/info.h>
28#include <sound/initval.h>
29
30MODULE_AUTHOR("Jaroslav Kysela <perex@perex.cz>");
31MODULE_DESCRIPTION("Intel 82801AA,82901AB,i810,i820,i830,i840,i845,MX440; SiS 7012; Ali 5455");
32MODULE_LICENSE("GPL");
33MODULE_SUPPORTED_DEVICE("{{Intel,82801AA-ICH},"
34 "{Intel,82901AB-ICH0},"
35 "{Intel,82801BA-ICH2},"
36 "{Intel,82801CA-ICH3},"
37 "{Intel,82801DB-ICH4},"
38 "{Intel,ICH5},"
39 "{Intel,ICH6},"
40 "{Intel,ICH7},"
41 "{Intel,6300ESB},"
42 "{Intel,ESB2},"
43 "{Intel,MX440},"
44 "{SiS,SI7012},"
45 "{NVidia,nForce Audio},"
46 "{NVidia,nForce2 Audio},"
47 "{NVidia,nForce3 Audio},"
48 "{NVidia,MCP04},"
49 "{NVidia,MCP501},"
50 "{NVidia,CK804},"
51 "{NVidia,CK8},"
52 "{NVidia,CK8S},"
53 "{AMD,AMD768},"
54 "{AMD,AMD8111},"
55 "{ALI,M5455}}");
56
57static int index = SNDRV_DEFAULT_IDX1; /* Index 0-MAX */
58static char *id = SNDRV_DEFAULT_STR1; /* ID for this card */
59static int ac97_clock;
60static char *ac97_quirk;
61static bool buggy_semaphore;
62static int buggy_irq = -1; /* auto-check */
63static bool xbox;
64static int spdif_aclink = -1;
65static int inside_vm = -1;
66
67module_param(index, int, 0444);
68MODULE_PARM_DESC(index, "Index value for Intel i8x0 soundcard.");
69module_param(id, charp, 0444);
70MODULE_PARM_DESC(id, "ID string for Intel i8x0 soundcard.");
71module_param(ac97_clock, int, 0444);
72MODULE_PARM_DESC(ac97_clock, "AC'97 codec clock (0 = allowlist + auto-detect, 1 = force autodetect).");
73module_param(ac97_quirk, charp, 0444);
74MODULE_PARM_DESC(ac97_quirk, "AC'97 workaround for strange hardware.");
75module_param(buggy_semaphore, bool, 0444);
76MODULE_PARM_DESC(buggy_semaphore, "Enable workaround for hardwares with problematic codec semaphores.");
77module_param(buggy_irq, bint, 0444);
78MODULE_PARM_DESC(buggy_irq, "Enable workaround for buggy interrupts on some motherboards.");
79module_param(xbox, bool, 0444);
80MODULE_PARM_DESC(xbox, "Set to 1 for Xbox, if you have problems with the AC'97 codec detection.");
81module_param(spdif_aclink, int, 0444);
82MODULE_PARM_DESC(spdif_aclink, "S/PDIF over AC-link.");
83module_param(inside_vm, bint, 0444);
84MODULE_PARM_DESC(inside_vm, "KVM/Parallels optimization.");
85
86/* just for backward compatibility */
87//static bool enable;
88module_param(enable, bool, 0444);
89//static int joystick;
90module_param(joystick, int, 0444);
91
92/*
93 * Direct registers
94 */
95enum { DEVICE_INTEL, DEVICE_INTEL_ICH4, DEVICE_SIS, DEVICE_ALI, DEVICE_NFORCE };
96
97#define ICHREG(x) ICH_REG_##x
98
99#define DEFINE_REGSET(name,base) \
100enum { \
101 ICH_REG_##name##_BDBAR = base + 0x0, /* dword - buffer descriptor list base address */ \
102 ICH_REG_##name##_CIV = base + 0x04, /* byte - current index value */ \
103 ICH_REG_##name##_LVI = base + 0x05, /* byte - last valid index */ \
104 ICH_REG_##name##_SR = base + 0x06, /* byte - status register */ \
105 ICH_REG_##name##_PICB = base + 0x08, /* word - position in current buffer */ \
106 ICH_REG_##name##_PIV = base + 0x0a, /* byte - prefetched index value */ \
107 ICH_REG_##name##_CR = base + 0x0b, /* byte - control register */ \
108};
109
110/* busmaster blocks */
111DEFINE_REGSET(OFF, 0); /* offset */
112DEFINE_REGSET(PI, 0x00); /* PCM in */
113DEFINE_REGSET(PO, 0x10); /* PCM out */
114DEFINE_REGSET(MC, 0x20); /* Mic in */
115
116/* ICH4 busmaster blocks */
117DEFINE_REGSET(MC2, 0x40); /* Mic in 2 */
118DEFINE_REGSET(PI2, 0x50); /* PCM in 2 */
119DEFINE_REGSET(SP, 0x60); /* SPDIF out */
120
121/* values for each busmaster block */
122
123/* LVI */
124#define ICH_REG_LVI_MASK 0x1f
125
126/* SR */
127#define ICH_FIFOE 0x10 /* FIFO error */
128#define ICH_BCIS 0x08 /* buffer completion interrupt status */
129#define ICH_LVBCI 0x04 /* last valid buffer completion interrupt */
130#define ICH_CELV 0x02 /* current equals last valid */
131#define ICH_DCH 0x01 /* DMA controller halted */
132
133/* PIV */
134#define ICH_REG_PIV_MASK 0x1f /* mask */
135
136/* CR */
137#define ICH_IOCE 0x10 /* interrupt on completion enable */
138#define ICH_FEIE 0x08 /* fifo error interrupt enable */
139#define ICH_LVBIE 0x04 /* last valid buffer interrupt enable */
140#define ICH_RESETREGS 0x02 /* reset busmaster registers */
141#define ICH_STARTBM 0x01 /* start busmaster operation */
142
143
144/* global block */
145#define ICH_REG_GLOB_CNT 0x2c /* dword - global control */
146#define ICH_PCM_SPDIF_MASK 0xc0000000 /* s/pdif pcm slot mask (ICH4) */
147#define ICH_PCM_SPDIF_NONE 0x00000000 /* reserved - undefined */
148#define ICH_PCM_SPDIF_78 0x40000000 /* s/pdif pcm on slots 7&8 */
149#define ICH_PCM_SPDIF_69 0x80000000 /* s/pdif pcm on slots 6&9 */
150#define ICH_PCM_SPDIF_1011 0xc0000000 /* s/pdif pcm on slots 10&11 */
151#define ICH_PCM_20BIT 0x00400000 /* 20-bit samples (ICH4) */
152#define ICH_PCM_246_MASK 0x00300000 /* chan mask (not all chips) */
153#define ICH_PCM_8 0x00300000 /* 8 channels (not all chips) */
154#define ICH_PCM_6 0x00200000 /* 6 channels (not all chips) */
155#define ICH_PCM_4 0x00100000 /* 4 channels (not all chips) */
156#define ICH_PCM_2 0x00000000 /* 2 channels (stereo) */
157#define ICH_SIS_PCM_246_MASK 0x000000c0 /* 6 channels (SIS7012) */
158#define ICH_SIS_PCM_6 0x00000080 /* 6 channels (SIS7012) */
159#define ICH_SIS_PCM_4 0x00000040 /* 4 channels (SIS7012) */
160#define ICH_SIS_PCM_2 0x00000000 /* 2 channels (SIS7012) */
161#define ICH_TRIE 0x00000040 /* tertiary resume interrupt enable */
162#define ICH_SRIE 0x00000020 /* secondary resume interrupt enable */
163#define ICH_PRIE 0x00000010 /* primary resume interrupt enable */
164#define ICH_ACLINK 0x00000008 /* AClink shut off */
165#define ICH_AC97WARM 0x00000004 /* AC'97 warm reset */
166#define ICH_AC97COLD 0x00000002 /* AC'97 cold reset */
167#define ICH_GIE 0x00000001 /* GPI interrupt enable */
168#define ICH_REG_GLOB_STA 0x30 /* dword - global status */
169#define ICH_TRI 0x20000000 /* ICH4: tertiary (AC_SDIN2) resume interrupt */
170#define ICH_TCR 0x10000000 /* ICH4: tertiary (AC_SDIN2) codec ready */
171#define ICH_BCS 0x08000000 /* ICH4: bit clock stopped */
172#define ICH_SPINT 0x04000000 /* ICH4: S/PDIF interrupt */
173#define ICH_P2INT 0x02000000 /* ICH4: PCM2-In interrupt */
174#define ICH_M2INT 0x01000000 /* ICH4: Mic2-In interrupt */
175#define ICH_SAMPLE_CAP 0x00c00000 /* ICH4: sample capability bits (RO) */
176#define ICH_SAMPLE_16_20 0x00400000 /* ICH4: 16- and 20-bit samples */
177#define ICH_MULTICHAN_CAP 0x00300000 /* ICH4: multi-channel capability bits (RO) */
178#define ICH_SIS_TRI 0x00080000 /* SIS: tertiary resume irq */
179#define ICH_SIS_TCR 0x00040000 /* SIS: tertiary codec ready */
180#define ICH_MD3 0x00020000 /* modem power down semaphore */
181#define ICH_AD3 0x00010000 /* audio power down semaphore */
182#define ICH_RCS 0x00008000 /* read completion status */
183#define ICH_BIT3 0x00004000 /* bit 3 slot 12 */
184#define ICH_BIT2 0x00002000 /* bit 2 slot 12 */
185#define ICH_BIT1 0x00001000 /* bit 1 slot 12 */
186#define ICH_SRI 0x00000800 /* secondary (AC_SDIN1) resume interrupt */
187#define ICH_PRI 0x00000400 /* primary (AC_SDIN0) resume interrupt */
188#define ICH_SCR 0x00000200 /* secondary (AC_SDIN1) codec ready */
189#define ICH_PCR 0x00000100 /* primary (AC_SDIN0) codec ready */
190#define ICH_MCINT 0x00000080 /* MIC capture interrupt */
191#define ICH_POINT 0x00000040 /* playback interrupt */
192#define ICH_PIINT 0x00000020 /* capture interrupt */
193#define ICH_NVSPINT 0x00000010 /* nforce spdif interrupt */
194#define ICH_MOINT 0x00000004 /* modem playback interrupt */
195#define ICH_MIINT 0x00000002 /* modem capture interrupt */
196#define ICH_GSCI 0x00000001 /* GPI status change interrupt */
197#define ICH_REG_ACC_SEMA 0x34 /* byte - codec write semaphore */
198#define ICH_CAS 0x01 /* codec access semaphore */
199#define ICH_REG_SDM 0x80
200#define ICH_DI2L_MASK 0x000000c0 /* PCM In 2, Mic In 2 data in line */
201#define ICH_DI2L_SHIFT 6
202#define ICH_DI1L_MASK 0x00000030 /* PCM In 1, Mic In 1 data in line */
203#define ICH_DI1L_SHIFT 4
204#define ICH_SE 0x00000008 /* steer enable */
205#define ICH_LDI_MASK 0x00000003 /* last codec read data input */
206
207#define ICH_MAX_FRAGS 32 /* max hw frags */
208
209
210/*
211 * registers for Ali5455
212 */
213
214/* ALi 5455 busmaster blocks */
215DEFINE_REGSET(AL_PI, 0x40); /* ALi PCM in */
216DEFINE_REGSET(AL_PO, 0x50); /* Ali PCM out */
217DEFINE_REGSET(AL_MC, 0x60); /* Ali Mic in */
218DEFINE_REGSET(AL_CDC_SPO, 0x70); /* Ali Codec SPDIF out */
219DEFINE_REGSET(AL_CENTER, 0x80); /* Ali center out */
220DEFINE_REGSET(AL_LFE, 0x90); /* Ali center out */
221DEFINE_REGSET(AL_CLR_SPI, 0xa0); /* Ali Controller SPDIF in */
222DEFINE_REGSET(AL_CLR_SPO, 0xb0); /* Ali Controller SPDIF out */
223DEFINE_REGSET(AL_I2S, 0xc0); /* Ali I2S in */
224DEFINE_REGSET(AL_PI2, 0xd0); /* Ali PCM2 in */
225DEFINE_REGSET(AL_MC2, 0xe0); /* Ali Mic2 in */
226
227enum {
228 ICH_REG_ALI_SCR = 0x00, /* System Control Register */
229 ICH_REG_ALI_SSR = 0x04, /* System Status Register */
230 ICH_REG_ALI_DMACR = 0x08, /* DMA Control Register */
231 ICH_REG_ALI_FIFOCR1 = 0x0c, /* FIFO Control Register 1 */
232 ICH_REG_ALI_INTERFACECR = 0x10, /* Interface Control Register */
233 ICH_REG_ALI_INTERRUPTCR = 0x14, /* Interrupt control Register */
234 ICH_REG_ALI_INTERRUPTSR = 0x18, /* Interrupt Status Register */
235 ICH_REG_ALI_FIFOCR2 = 0x1c, /* FIFO Control Register 2 */
236 ICH_REG_ALI_CPR = 0x20, /* Command Port Register */
237 ICH_REG_ALI_CPR_ADDR = 0x22, /* ac97 addr write */
238 ICH_REG_ALI_SPR = 0x24, /* Status Port Register */
239 ICH_REG_ALI_SPR_ADDR = 0x26, /* ac97 addr read */
240 ICH_REG_ALI_FIFOCR3 = 0x2c, /* FIFO Control Register 3 */
241 ICH_REG_ALI_TTSR = 0x30, /* Transmit Tag Slot Register */
242 ICH_REG_ALI_RTSR = 0x34, /* Receive Tag Slot Register */
243 ICH_REG_ALI_CSPSR = 0x38, /* Command/Status Port Status Register */
244 ICH_REG_ALI_CAS = 0x3c, /* Codec Write Semaphore Register */
245 ICH_REG_ALI_HWVOL = 0xf0, /* hardware volume control/status */
246 ICH_REG_ALI_I2SCR = 0xf4, /* I2S control/status */
247 ICH_REG_ALI_SPDIFCSR = 0xf8, /* spdif channel status register */
248 ICH_REG_ALI_SPDIFICS = 0xfc, /* spdif interface control/status */
249};
250
251#define ALI_CAS_SEM_BUSY 0x80000000
252#define ALI_CPR_ADDR_SECONDARY 0x100
253#define ALI_CPR_ADDR_READ 0x80
254#define ALI_CSPSR_CODEC_READY 0x08
255#define ALI_CSPSR_READ_OK 0x02
256#define ALI_CSPSR_WRITE_OK 0x01
257
258/* interrupts for the whole chip by interrupt status register finish */
259
260#define ALI_INT_MICIN2 (1<<26)
261#define ALI_INT_PCMIN2 (1<<25)
262#define ALI_INT_I2SIN (1<<24)
263#define ALI_INT_SPDIFOUT (1<<23) /* controller spdif out INTERRUPT */
264#define ALI_INT_SPDIFIN (1<<22)
265#define ALI_INT_LFEOUT (1<<21)
266#define ALI_INT_CENTEROUT (1<<20)
267#define ALI_INT_CODECSPDIFOUT (1<<19)
268#define ALI_INT_MICIN (1<<18)
269#define ALI_INT_PCMOUT (1<<17)
270#define ALI_INT_PCMIN (1<<16)
271#define ALI_INT_CPRAIS (1<<7) /* command port available */
272#define ALI_INT_SPRAIS (1<<5) /* status port available */
273#define ALI_INT_GPIO (1<<1)
274#define ALI_INT_MASK (ALI_INT_SPDIFOUT|ALI_INT_CODECSPDIFOUT|\
275 ALI_INT_MICIN|ALI_INT_PCMOUT|ALI_INT_PCMIN)
276
277#define ICH_ALI_SC_RESET (1<<31) /* master reset */
278#define ICH_ALI_SC_AC97_DBL (1<<30)
279#define ICH_ALI_SC_CODEC_SPDF (3<<20) /* 1=7/8, 2=6/9, 3=10/11 */
280#define ICH_ALI_SC_IN_BITS (3<<18)
281#define ICH_ALI_SC_OUT_BITS (3<<16)
282#define ICH_ALI_SC_6CH_CFG (3<<14)
283#define ICH_ALI_SC_PCM_4 (1<<8)
284#define ICH_ALI_SC_PCM_6 (2<<8)
285#define ICH_ALI_SC_PCM_246_MASK (3<<8)
286
287#define ICH_ALI_SS_SEC_ID (3<<5)
288#define ICH_ALI_SS_PRI_ID (3<<3)
289
290#define ICH_ALI_IF_AC97SP (1<<21)
291#define ICH_ALI_IF_MC (1<<20)
292#define ICH_ALI_IF_PI (1<<19)
293#define ICH_ALI_IF_MC2 (1<<18)
294#define ICH_ALI_IF_PI2 (1<<17)
295#define ICH_ALI_IF_LINE_SRC (1<<15) /* 0/1 = slot 3/6 */
296#define ICH_ALI_IF_MIC_SRC (1<<14) /* 0/1 = slot 3/6 */
297#define ICH_ALI_IF_SPDF_SRC (3<<12) /* 00 = PCM, 01 = AC97-in, 10 = spdif-in, 11 = i2s */
298#define ICH_ALI_IF_AC97_OUT (3<<8) /* 00 = PCM, 10 = spdif-in, 11 = i2s */
299#define ICH_ALI_IF_PO_SPDF (1<<3)
300#define ICH_ALI_IF_PO (1<<1)
301
302/*
303 *
304 */
305
306enum {
307 ICHD_PCMIN,
308 ICHD_PCMOUT,
309 ICHD_MIC,
310 ICHD_MIC2,
311 ICHD_PCM2IN,
312 ICHD_SPBAR,
313 ICHD_LAST = ICHD_SPBAR
314};
315enum {
316 NVD_PCMIN,
317 NVD_PCMOUT,
318 NVD_MIC,
319 NVD_SPBAR,
320 NVD_LAST = NVD_SPBAR
321};
322enum {
323 ALID_PCMIN,
324 ALID_PCMOUT,
325 ALID_MIC,
326 ALID_AC97SPDIFOUT,
327 ALID_SPDIFIN,
328 ALID_SPDIFOUT,
329 ALID_LAST = ALID_SPDIFOUT
330};
331
332#define get_ichdev(substream) (substream->runtime->private_data)
333
334struct ichdev {
335 unsigned int ichd; /* ich device number */
336 unsigned long reg_offset; /* offset to bmaddr */
337 __le32 *bdbar; /* CPU address (32bit) */
338 unsigned int bdbar_addr; /* PCI bus address (32bit) */
339 struct snd_pcm_substream *substream;
340 unsigned int physbuf; /* physical address (32bit) */
341 unsigned int size;
342 unsigned int fragsize;
343 unsigned int fragsize1;
344 unsigned int position;
345 unsigned int pos_shift;
346 unsigned int last_pos;
347 int frags;
348 int lvi;
349 int lvi_frag;
350 int civ;
351 int ack;
352 int ack_reload;
353 unsigned int ack_bit;
354 unsigned int roff_sr;
355 unsigned int roff_picb;
356 unsigned int int_sta_mask; /* interrupt status mask */
357 unsigned int ali_slot; /* ALI DMA slot */
358 struct ac97_pcm *pcm;
359 int pcm_open_flag;
360 unsigned int suspended: 1;
361};
362
363struct intel8x0 {
364 unsigned int device_type;
365
366 int irq;
367
368 void __iomem *addr;
369 void __iomem *bmaddr;
370
371 struct pci_dev *pci;
372 struct snd_card *card;
373
374 int pcm_devs;
375 struct snd_pcm *pcm[6];
376 struct ichdev ichd[6];
377
378 unsigned multi4: 1,
379 multi6: 1,
380 multi8 :1,
381 dra: 1,
382 smp20bit: 1;
383 unsigned in_ac97_init: 1,
384 in_sdin_init: 1;
385 unsigned in_measurement: 1; /* during ac97 clock measurement */
386 unsigned fix_nocache: 1; /* workaround for 440MX */
387 unsigned buggy_irq: 1; /* workaround for buggy mobos */
388 unsigned xbox: 1; /* workaround for Xbox AC'97 detection */
389 unsigned buggy_semaphore: 1; /* workaround for buggy codec semaphore */
390 unsigned inside_vm: 1; /* enable VM optimization */
391
392 int spdif_idx; /* SPDIF BAR index; *_SPBAR or -1 if use PCMOUT */
393 unsigned int sdm_saved; /* SDM reg value */
394
395 struct snd_ac97_bus *ac97_bus;
396 struct snd_ac97 *ac97[3];
397 unsigned int ac97_sdin[3];
398 unsigned int max_codecs, ncodecs;
399 const unsigned int *codec_bit;
400 unsigned int codec_isr_bits;
401 unsigned int codec_ready_bits;
402
403 spinlock_t reg_lock;
404
405 u32 bdbars_count;
406 struct snd_dma_buffer bdbars;
407 u32 int_sta_reg; /* interrupt status register */
408 u32 int_sta_mask; /* interrupt status mask */
409};
410
411static const struct pci_device_id snd_intel8x0_ids[] = {
412 { PCI_VDEVICE(INTEL, 0x2415), DEVICE_INTEL }, /* 82801AA */
413 { PCI_VDEVICE(INTEL, 0x2425), DEVICE_INTEL }, /* 82901AB */
414 { PCI_VDEVICE(INTEL, 0x2445), DEVICE_INTEL }, /* 82801BA */
415 { PCI_VDEVICE(INTEL, 0x2485), DEVICE_INTEL }, /* ICH3 */
416 { PCI_VDEVICE(INTEL, 0x24c5), DEVICE_INTEL_ICH4 }, /* ICH4 */
417 { PCI_VDEVICE(INTEL, 0x24d5), DEVICE_INTEL_ICH4 }, /* ICH5 */
418 { PCI_VDEVICE(INTEL, 0x25a6), DEVICE_INTEL_ICH4 }, /* ESB */
419 { PCI_VDEVICE(INTEL, 0x266e), DEVICE_INTEL_ICH4 }, /* ICH6 */
420 { PCI_VDEVICE(INTEL, 0x27de), DEVICE_INTEL_ICH4 }, /* ICH7 */
421 { PCI_VDEVICE(INTEL, 0x2698), DEVICE_INTEL_ICH4 }, /* ESB2 */
422 { PCI_VDEVICE(INTEL, 0x7195), DEVICE_INTEL }, /* 440MX */
423 { PCI_VDEVICE(SI, 0x7012), DEVICE_SIS }, /* SI7012 */
424 { PCI_VDEVICE(NVIDIA, 0x01b1), DEVICE_NFORCE }, /* NFORCE */
425 { PCI_VDEVICE(NVIDIA, 0x003a), DEVICE_NFORCE }, /* MCP04 */
426 { PCI_VDEVICE(NVIDIA, 0x006a), DEVICE_NFORCE }, /* NFORCE2 */
427 { PCI_VDEVICE(NVIDIA, 0x0059), DEVICE_NFORCE }, /* CK804 */
428 { PCI_VDEVICE(NVIDIA, 0x008a), DEVICE_NFORCE }, /* CK8 */
429 { PCI_VDEVICE(NVIDIA, 0x00da), DEVICE_NFORCE }, /* NFORCE3 */
430 { PCI_VDEVICE(NVIDIA, 0x00ea), DEVICE_NFORCE }, /* CK8S */
431 { PCI_VDEVICE(NVIDIA, 0x026b), DEVICE_NFORCE }, /* MCP51 */
432 { PCI_VDEVICE(AMD, 0x746d), DEVICE_INTEL }, /* AMD8111 */
433 { PCI_VDEVICE(AMD, 0x7445), DEVICE_INTEL }, /* AMD768 */
434 { PCI_VDEVICE(AL, 0x5455), DEVICE_ALI }, /* Ali5455 */
435 { 0, }
436};
437
438MODULE_DEVICE_TABLE(pci, snd_intel8x0_ids);
439
440/*
441 * Lowlevel I/O - busmaster
442 */
443
444static inline u8 igetbyte(struct intel8x0 *chip, u32 offset)
445{
446 return ioread8(chip->bmaddr + offset);
447}
448
449static inline u16 igetword(struct intel8x0 *chip, u32 offset)
450{
451 return ioread16(chip->bmaddr + offset);
452}
453
454static inline u32 igetdword(struct intel8x0 *chip, u32 offset)
455{
456 return ioread32(chip->bmaddr + offset);
457}
458
459static inline void iputbyte(struct intel8x0 *chip, u32 offset, u8 val)
460{
461 iowrite8(val, chip->bmaddr + offset);
462}
463
464static inline void iputword(struct intel8x0 *chip, u32 offset, u16 val)
465{
466 iowrite16(val, chip->bmaddr + offset);
467}
468
469static inline void iputdword(struct intel8x0 *chip, u32 offset, u32 val)
470{
471 iowrite32(val, chip->bmaddr + offset);
472}
473
474/*
475 * Lowlevel I/O - AC'97 registers
476 */
477
478static inline u16 iagetword(struct intel8x0 *chip, u32 offset)
479{
480 return ioread16(chip->addr + offset);
481}
482
483static inline void iaputword(struct intel8x0 *chip, u32 offset, u16 val)
484{
485 iowrite16(val, chip->addr + offset);
486}
487
488/*
489 * Basic I/O
490 */
491
492/*
493 * access to AC97 codec via normal i/o (for ICH and SIS7012)
494 */
495
496static int snd_intel8x0_codec_semaphore(struct intel8x0 *chip, unsigned int codec)
497{
498 int time;
499
500 if (codec > 2)
501 return -EIO;
502 if (chip->in_sdin_init) {
503 /* we don't know the ready bit assignment at the moment */
504 /* so we check any */
505 codec = chip->codec_isr_bits;
506 } else {
507 codec = chip->codec_bit[chip->ac97_sdin[codec]];
508 }
509
510 /* codec ready ? */
511 if ((igetdword(chip, ICHREG(GLOB_STA)) & codec) == 0)
512 return -EIO;
513
514 if (chip->buggy_semaphore)
515 return 0; /* just ignore ... */
516
517 /* Anyone holding a semaphore for 1 msec should be shot... */
518 time = 100;
519 do {
520 if (!(igetbyte(chip, ICHREG(ACC_SEMA)) & ICH_CAS))
521 return 0;
522 udelay(10);
523 } while (time--);
524
525 /* access to some forbidden (non existent) ac97 registers will not
526 * reset the semaphore. So even if you don't get the semaphore, still
527 * continue the access. We don't need the semaphore anyway. */
528 dev_err(chip->card->dev,
529 "codec_semaphore: semaphore is not ready [0x%x][0x%x]\n",
530 igetbyte(chip, ICHREG(ACC_SEMA)), igetdword(chip, ICHREG(GLOB_STA)));
531 iagetword(chip, 0); /* clear semaphore flag */
532 /* I don't care about the semaphore */
533 return -EBUSY;
534}
535
536static void snd_intel8x0_codec_write(struct snd_ac97 *ac97,
537 unsigned short reg,
538 unsigned short val)
539{
540 struct intel8x0 *chip = ac97->private_data;
541
542 if (snd_intel8x0_codec_semaphore(chip, ac97->num) < 0) {
543 if (! chip->in_ac97_init)
544 dev_err(chip->card->dev,
545 "codec_write %d: semaphore is not ready for register 0x%x\n",
546 ac97->num, reg);
547 }
548 iaputword(chip, reg + ac97->num * 0x80, val);
549}
550
551static unsigned short snd_intel8x0_codec_read(struct snd_ac97 *ac97,
552 unsigned short reg)
553{
554 struct intel8x0 *chip = ac97->private_data;
555 unsigned short res;
556 unsigned int tmp;
557
558 if (snd_intel8x0_codec_semaphore(chip, ac97->num) < 0) {
559 if (! chip->in_ac97_init)
560 dev_err(chip->card->dev,
561 "codec_read %d: semaphore is not ready for register 0x%x\n",
562 ac97->num, reg);
563 res = 0xffff;
564 } else {
565 res = iagetword(chip, reg + ac97->num * 0x80);
566 if ((tmp = igetdword(chip, ICHREG(GLOB_STA))) & ICH_RCS) {
567 /* reset RCS and preserve other R/WC bits */
568 iputdword(chip, ICHREG(GLOB_STA), tmp &
569 ~(chip->codec_ready_bits | ICH_GSCI));
570 if (! chip->in_ac97_init)
571 dev_err(chip->card->dev,
572 "codec_read %d: read timeout for register 0x%x\n",
573 ac97->num, reg);
574 res = 0xffff;
575 }
576 }
577 return res;
578}
579
580static void snd_intel8x0_codec_read_test(struct intel8x0 *chip,
581 unsigned int codec)
582{
583 unsigned int tmp;
584
585 if (snd_intel8x0_codec_semaphore(chip, codec) >= 0) {
586 iagetword(chip, codec * 0x80);
587 if ((tmp = igetdword(chip, ICHREG(GLOB_STA))) & ICH_RCS) {
588 /* reset RCS and preserve other R/WC bits */
589 iputdword(chip, ICHREG(GLOB_STA), tmp &
590 ~(chip->codec_ready_bits | ICH_GSCI));
591 }
592 }
593}
594
595/*
596 * access to AC97 for Ali5455
597 */
598static int snd_intel8x0_ali_codec_ready(struct intel8x0 *chip, int mask)
599{
600 int count = 0;
601 for (count = 0; count < 0x7f; count++) {
602 int val = igetbyte(chip, ICHREG(ALI_CSPSR));
603 if (val & mask)
604 return 0;
605 }
606 if (! chip->in_ac97_init)
607 dev_warn(chip->card->dev, "AC97 codec ready timeout.\n");
608 return -EBUSY;
609}
610
611static int snd_intel8x0_ali_codec_semaphore(struct intel8x0 *chip)
612{
613 int time = 100;
614 if (chip->buggy_semaphore)
615 return 0; /* just ignore ... */
616 while (--time && (igetdword(chip, ICHREG(ALI_CAS)) & ALI_CAS_SEM_BUSY))
617 udelay(1);
618 if (! time && ! chip->in_ac97_init)
619 dev_warn(chip->card->dev, "ali_codec_semaphore timeout\n");
620 return snd_intel8x0_ali_codec_ready(chip, ALI_CSPSR_CODEC_READY);
621}
622
623static unsigned short snd_intel8x0_ali_codec_read(struct snd_ac97 *ac97, unsigned short reg)
624{
625 struct intel8x0 *chip = ac97->private_data;
626 unsigned short data = 0xffff;
627
628 if (snd_intel8x0_ali_codec_semaphore(chip))
629 goto __err;
630 reg |= ALI_CPR_ADDR_READ;
631 if (ac97->num)
632 reg |= ALI_CPR_ADDR_SECONDARY;
633 iputword(chip, ICHREG(ALI_CPR_ADDR), reg);
634 if (snd_intel8x0_ali_codec_ready(chip, ALI_CSPSR_READ_OK))
635 goto __err;
636 data = igetword(chip, ICHREG(ALI_SPR));
637 __err:
638 return data;
639}
640
641static void snd_intel8x0_ali_codec_write(struct snd_ac97 *ac97, unsigned short reg,
642 unsigned short val)
643{
644 struct intel8x0 *chip = ac97->private_data;
645
646 if (snd_intel8x0_ali_codec_semaphore(chip))
647 return;
648 iputword(chip, ICHREG(ALI_CPR), val);
649 if (ac97->num)
650 reg |= ALI_CPR_ADDR_SECONDARY;
651 iputword(chip, ICHREG(ALI_CPR_ADDR), reg);
652 snd_intel8x0_ali_codec_ready(chip, ALI_CSPSR_WRITE_OK);
653}
654
655
656/*
657 * DMA I/O
658 */
659static void snd_intel8x0_setup_periods(struct intel8x0 *chip, struct ichdev *ichdev)
660{
661 int idx;
662 __le32 *bdbar = ichdev->bdbar;
663 unsigned long port = ichdev->reg_offset;
664
665 iputdword(chip, port + ICH_REG_OFF_BDBAR, ichdev->bdbar_addr);
666 if (ichdev->size == ichdev->fragsize) {
667 ichdev->ack_reload = ichdev->ack = 2;
668 ichdev->fragsize1 = ichdev->fragsize >> 1;
669 for (idx = 0; idx < (ICH_REG_LVI_MASK + 1) * 2; idx += 4) {
670 bdbar[idx + 0] = cpu_to_le32(ichdev->physbuf);
671 bdbar[idx + 1] = cpu_to_le32(0x80000000 | /* interrupt on completion */
672 ichdev->fragsize1 >> ichdev->pos_shift);
673 bdbar[idx + 2] = cpu_to_le32(ichdev->physbuf + (ichdev->size >> 1));
674 bdbar[idx + 3] = cpu_to_le32(0x80000000 | /* interrupt on completion */
675 ichdev->fragsize1 >> ichdev->pos_shift);
676 }
677 ichdev->frags = 2;
678 } else {
679 ichdev->ack_reload = ichdev->ack = 1;
680 ichdev->fragsize1 = ichdev->fragsize;
681 for (idx = 0; idx < (ICH_REG_LVI_MASK + 1) * 2; idx += 2) {
682 bdbar[idx + 0] = cpu_to_le32(ichdev->physbuf +
683 (((idx >> 1) * ichdev->fragsize) %
684 ichdev->size));
685 bdbar[idx + 1] = cpu_to_le32(0x80000000 | /* interrupt on completion */
686 ichdev->fragsize >> ichdev->pos_shift);
687#if 0
688 dev_dbg(chip->card->dev, "bdbar[%i] = 0x%x [0x%x]\n",
689 idx + 0, bdbar[idx + 0], bdbar[idx + 1]);
690#endif
691 }
692 ichdev->frags = ichdev->size / ichdev->fragsize;
693 }
694 iputbyte(chip, port + ICH_REG_OFF_LVI, ichdev->lvi = ICH_REG_LVI_MASK);
695 ichdev->civ = 0;
696 iputbyte(chip, port + ICH_REG_OFF_CIV, 0);
697 ichdev->lvi_frag = ICH_REG_LVI_MASK % ichdev->frags;
698 ichdev->position = 0;
699#if 0
700 dev_dbg(chip->card->dev,
701 "lvi_frag = %i, frags = %i, period_size = 0x%x, period_size1 = 0x%x\n",
702 ichdev->lvi_frag, ichdev->frags, ichdev->fragsize,
703 ichdev->fragsize1);
704#endif
705 /* clear interrupts */
706 iputbyte(chip, port + ichdev->roff_sr, ICH_FIFOE | ICH_BCIS | ICH_LVBCI);
707}
708
709/*
710 * Interrupt handler
711 */
712
713static inline void snd_intel8x0_update(struct intel8x0 *chip, struct ichdev *ichdev)
714{
715 unsigned long port = ichdev->reg_offset;
716 unsigned long flags;
717 int status, civ, i, step;
718 int ack = 0;
719
720 spin_lock_irqsave(&chip->reg_lock, flags);
721 status = igetbyte(chip, port + ichdev->roff_sr);
722 civ = igetbyte(chip, port + ICH_REG_OFF_CIV);
723 if (!(status & ICH_BCIS)) {
724 step = 0;
725 } else if (civ == ichdev->civ) {
726 // snd_printd("civ same %d\n", civ);
727 step = 1;
728 ichdev->civ++;
729 ichdev->civ &= ICH_REG_LVI_MASK;
730 } else {
731 step = civ - ichdev->civ;
732 if (step < 0)
733 step += ICH_REG_LVI_MASK + 1;
734 // if (step != 1)
735 // snd_printd("step = %d, %d -> %d\n", step, ichdev->civ, civ);
736 ichdev->civ = civ;
737 }
738
739 ichdev->position += step * ichdev->fragsize1;
740 if (! chip->in_measurement)
741 ichdev->position %= ichdev->size;
742 ichdev->lvi += step;
743 ichdev->lvi &= ICH_REG_LVI_MASK;
744 iputbyte(chip, port + ICH_REG_OFF_LVI, ichdev->lvi);
745 for (i = 0; i < step; i++) {
746 ichdev->lvi_frag++;
747 ichdev->lvi_frag %= ichdev->frags;
748 ichdev->bdbar[ichdev->lvi * 2] = cpu_to_le32(ichdev->physbuf + ichdev->lvi_frag * ichdev->fragsize1);
749#if 0
750 dev_dbg(chip->card->dev,
751 "new: bdbar[%i] = 0x%x [0x%x], prefetch = %i, all = 0x%x, 0x%x\n",
752 ichdev->lvi * 2, ichdev->bdbar[ichdev->lvi * 2],
753 ichdev->bdbar[ichdev->lvi * 2 + 1], inb(ICH_REG_OFF_PIV + port),
754 inl(port + 4), inb(port + ICH_REG_OFF_CR));
755#endif
756 if (--ichdev->ack == 0) {
757 ichdev->ack = ichdev->ack_reload;
758 ack = 1;
759 }
760 }
761 spin_unlock_irqrestore(&chip->reg_lock, flags);
762 if (ack && ichdev->substream) {
763 snd_pcm_period_elapsed(ichdev->substream);
764 }
765 iputbyte(chip, port + ichdev->roff_sr,
766 status & (ICH_FIFOE | ICH_BCIS | ICH_LVBCI));
767}
768
769static irqreturn_t snd_intel8x0_interrupt(int irq, void *dev_id)
770{
771 struct intel8x0 *chip = dev_id;
772 struct ichdev *ichdev;
773 unsigned int status;
774 unsigned int i;
775
776 status = igetdword(chip, chip->int_sta_reg);
777 if (status == 0xffffffff) /* we are not yet resumed */
778 return IRQ_NONE;
779
780 if ((status & chip->int_sta_mask) == 0) {
781 if (status) {
782 /* ack */
783 iputdword(chip, chip->int_sta_reg, status);
784 if (! chip->buggy_irq)
785 status = 0;
786 }
787 return IRQ_RETVAL(status);
788 }
789
790 for (i = 0; i < chip->bdbars_count; i++) {
791 ichdev = &chip->ichd[i];
792 if (status & ichdev->int_sta_mask)
793 snd_intel8x0_update(chip, ichdev);
794 }
795
796 /* ack them */
797 iputdword(chip, chip->int_sta_reg, status & chip->int_sta_mask);
798
799 return IRQ_HANDLED;
800}
801
802/*
803 * PCM part
804 */
805
806static int snd_intel8x0_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
807{
808 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
809 struct ichdev *ichdev = get_ichdev(substream);
810 unsigned char val = 0;
811 unsigned long port = ichdev->reg_offset;
812
813 switch (cmd) {
814 case SNDRV_PCM_TRIGGER_RESUME:
815 ichdev->suspended = 0;
816 fallthrough;
817 case SNDRV_PCM_TRIGGER_START:
818 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
819 val = ICH_IOCE | ICH_STARTBM;
820 ichdev->last_pos = ichdev->position;
821 break;
822 case SNDRV_PCM_TRIGGER_SUSPEND:
823 ichdev->suspended = 1;
824 fallthrough;
825 case SNDRV_PCM_TRIGGER_STOP:
826 val = 0;
827 break;
828 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
829 val = ICH_IOCE;
830 break;
831 default:
832 return -EINVAL;
833 }
834 iputbyte(chip, port + ICH_REG_OFF_CR, val);
835 if (cmd == SNDRV_PCM_TRIGGER_STOP) {
836 /* wait until DMA stopped */
837 while (!(igetbyte(chip, port + ichdev->roff_sr) & ICH_DCH)) ;
838 /* reset whole DMA things */
839 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_RESETREGS);
840 }
841 return 0;
842}
843
844static int snd_intel8x0_ali_trigger(struct snd_pcm_substream *substream, int cmd)
845{
846 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
847 struct ichdev *ichdev = get_ichdev(substream);
848 unsigned long port = ichdev->reg_offset;
849 static const int fiforeg[] = {
850 ICHREG(ALI_FIFOCR1), ICHREG(ALI_FIFOCR2), ICHREG(ALI_FIFOCR3)
851 };
852 unsigned int val, fifo;
853
854 val = igetdword(chip, ICHREG(ALI_DMACR));
855 switch (cmd) {
856 case SNDRV_PCM_TRIGGER_RESUME:
857 ichdev->suspended = 0;
858 fallthrough;
859 case SNDRV_PCM_TRIGGER_START:
860 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
861 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
862 /* clear FIFO for synchronization of channels */
863 fifo = igetdword(chip, fiforeg[ichdev->ali_slot / 4]);
864 fifo &= ~(0xff << (ichdev->ali_slot % 4));
865 fifo |= 0x83 << (ichdev->ali_slot % 4);
866 iputdword(chip, fiforeg[ichdev->ali_slot / 4], fifo);
867 }
868 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_IOCE);
869 val &= ~(1 << (ichdev->ali_slot + 16)); /* clear PAUSE flag */
870 /* start DMA */
871 iputdword(chip, ICHREG(ALI_DMACR), val | (1 << ichdev->ali_slot));
872 break;
873 case SNDRV_PCM_TRIGGER_SUSPEND:
874 ichdev->suspended = 1;
875 fallthrough;
876 case SNDRV_PCM_TRIGGER_STOP:
877 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
878 /* pause */
879 iputdword(chip, ICHREG(ALI_DMACR), val | (1 << (ichdev->ali_slot + 16)));
880 iputbyte(chip, port + ICH_REG_OFF_CR, 0);
881 while (igetbyte(chip, port + ICH_REG_OFF_CR))
882 ;
883 if (cmd == SNDRV_PCM_TRIGGER_PAUSE_PUSH)
884 break;
885 /* reset whole DMA things */
886 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_RESETREGS);
887 /* clear interrupts */
888 iputbyte(chip, port + ICH_REG_OFF_SR,
889 igetbyte(chip, port + ICH_REG_OFF_SR) | 0x1e);
890 iputdword(chip, ICHREG(ALI_INTERRUPTSR),
891 igetdword(chip, ICHREG(ALI_INTERRUPTSR)) & ichdev->int_sta_mask);
892 break;
893 default:
894 return -EINVAL;
895 }
896 return 0;
897}
898
899static int snd_intel8x0_hw_params(struct snd_pcm_substream *substream,
900 struct snd_pcm_hw_params *hw_params)
901{
902 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
903 struct ichdev *ichdev = get_ichdev(substream);
904 int dbl = params_rate(hw_params) > 48000;
905 int err;
906
907 if (ichdev->pcm_open_flag) {
908 snd_ac97_pcm_close(ichdev->pcm);
909 ichdev->pcm_open_flag = 0;
910 }
911 err = snd_ac97_pcm_open(ichdev->pcm, params_rate(hw_params),
912 params_channels(hw_params),
913 ichdev->pcm->r[dbl].slots);
914 if (err >= 0) {
915 ichdev->pcm_open_flag = 1;
916 /* Force SPDIF setting */
917 if (ichdev->ichd == ICHD_PCMOUT && chip->spdif_idx < 0)
918 snd_ac97_set_rate(ichdev->pcm->r[0].codec[0], AC97_SPDIF,
919 params_rate(hw_params));
920 }
921 return err;
922}
923
924static int snd_intel8x0_hw_free(struct snd_pcm_substream *substream)
925{
926 struct ichdev *ichdev = get_ichdev(substream);
927
928 if (ichdev->pcm_open_flag) {
929 snd_ac97_pcm_close(ichdev->pcm);
930 ichdev->pcm_open_flag = 0;
931 }
932 return 0;
933}
934
935static void snd_intel8x0_setup_pcm_out(struct intel8x0 *chip,
936 struct snd_pcm_runtime *runtime)
937{
938 unsigned int cnt;
939 int dbl = runtime->rate > 48000;
940
941 spin_lock_irq(&chip->reg_lock);
942 switch (chip->device_type) {
943 case DEVICE_ALI:
944 cnt = igetdword(chip, ICHREG(ALI_SCR));
945 cnt &= ~ICH_ALI_SC_PCM_246_MASK;
946 if (runtime->channels == 4 || dbl)
947 cnt |= ICH_ALI_SC_PCM_4;
948 else if (runtime->channels == 6)
949 cnt |= ICH_ALI_SC_PCM_6;
950 iputdword(chip, ICHREG(ALI_SCR), cnt);
951 break;
952 case DEVICE_SIS:
953 cnt = igetdword(chip, ICHREG(GLOB_CNT));
954 cnt &= ~ICH_SIS_PCM_246_MASK;
955 if (runtime->channels == 4 || dbl)
956 cnt |= ICH_SIS_PCM_4;
957 else if (runtime->channels == 6)
958 cnt |= ICH_SIS_PCM_6;
959 iputdword(chip, ICHREG(GLOB_CNT), cnt);
960 break;
961 default:
962 cnt = igetdword(chip, ICHREG(GLOB_CNT));
963 cnt &= ~(ICH_PCM_246_MASK | ICH_PCM_20BIT);
964 if (runtime->channels == 4 || dbl)
965 cnt |= ICH_PCM_4;
966 else if (runtime->channels == 6)
967 cnt |= ICH_PCM_6;
968 else if (runtime->channels == 8)
969 cnt |= ICH_PCM_8;
970 if (chip->device_type == DEVICE_NFORCE) {
971 /* reset to 2ch once to keep the 6 channel data in alignment,
972 * to start from Front Left always
973 */
974 if (cnt & ICH_PCM_246_MASK) {
975 iputdword(chip, ICHREG(GLOB_CNT), cnt & ~ICH_PCM_246_MASK);
976 spin_unlock_irq(&chip->reg_lock);
977 msleep(50); /* grrr... */
978 spin_lock_irq(&chip->reg_lock);
979 }
980 } else if (chip->device_type == DEVICE_INTEL_ICH4) {
981 if (runtime->sample_bits > 16)
982 cnt |= ICH_PCM_20BIT;
983 }
984 iputdword(chip, ICHREG(GLOB_CNT), cnt);
985 break;
986 }
987 spin_unlock_irq(&chip->reg_lock);
988}
989
990static int snd_intel8x0_pcm_prepare(struct snd_pcm_substream *substream)
991{
992 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
993 struct snd_pcm_runtime *runtime = substream->runtime;
994 struct ichdev *ichdev = get_ichdev(substream);
995
996 ichdev->physbuf = runtime->dma_addr;
997 ichdev->size = snd_pcm_lib_buffer_bytes(substream);
998 ichdev->fragsize = snd_pcm_lib_period_bytes(substream);
999 if (ichdev->ichd == ICHD_PCMOUT) {
1000 snd_intel8x0_setup_pcm_out(chip, runtime);
1001 if (chip->device_type == DEVICE_INTEL_ICH4)
1002 ichdev->pos_shift = (runtime->sample_bits > 16) ? 2 : 1;
1003 }
1004 snd_intel8x0_setup_periods(chip, ichdev);
1005 return 0;
1006}
1007
1008static snd_pcm_uframes_t snd_intel8x0_pcm_pointer(struct snd_pcm_substream *substream)
1009{
1010 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1011 struct ichdev *ichdev = get_ichdev(substream);
1012 size_t ptr1, ptr;
1013 int civ, timeout = 10;
1014 unsigned int position;
1015
1016 spin_lock(&chip->reg_lock);
1017 do {
1018 civ = igetbyte(chip, ichdev->reg_offset + ICH_REG_OFF_CIV);
1019 ptr1 = igetword(chip, ichdev->reg_offset + ichdev->roff_picb);
1020 position = ichdev->position;
1021 if (ptr1 == 0) {
1022 udelay(10);
1023 continue;
1024 }
1025 if (civ != igetbyte(chip, ichdev->reg_offset + ICH_REG_OFF_CIV))
1026 continue;
1027
1028 /* IO read operation is very expensive inside virtual machine
1029 * as it is emulated. The probability that subsequent PICB read
1030 * will return different result is high enough to loop till
1031 * timeout here.
1032 * Same CIV is strict enough condition to be sure that PICB
1033 * is valid inside VM on emulated card. */
1034 if (chip->inside_vm)
1035 break;
1036 if (ptr1 == igetword(chip, ichdev->reg_offset + ichdev->roff_picb))
1037 break;
1038 } while (timeout--);
1039 ptr = ichdev->last_pos;
1040 if (ptr1 != 0) {
1041 ptr1 <<= ichdev->pos_shift;
1042 ptr = ichdev->fragsize1 - ptr1;
1043 ptr += position;
1044 if (ptr < ichdev->last_pos) {
1045 unsigned int pos_base, last_base;
1046 pos_base = position / ichdev->fragsize1;
1047 last_base = ichdev->last_pos / ichdev->fragsize1;
1048 /* another sanity check; ptr1 can go back to full
1049 * before the base position is updated
1050 */
1051 if (pos_base == last_base)
1052 ptr = ichdev->last_pos;
1053 }
1054 }
1055 ichdev->last_pos = ptr;
1056 spin_unlock(&chip->reg_lock);
1057 if (ptr >= ichdev->size)
1058 return 0;
1059 return bytes_to_frames(substream->runtime, ptr);
1060}
1061
1062static const struct snd_pcm_hardware snd_intel8x0_stream =
1063{
1064 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1065 SNDRV_PCM_INFO_BLOCK_TRANSFER |
1066 SNDRV_PCM_INFO_MMAP_VALID |
1067 SNDRV_PCM_INFO_PAUSE |
1068 SNDRV_PCM_INFO_RESUME),
1069 .formats = SNDRV_PCM_FMTBIT_S16_LE,
1070 .rates = SNDRV_PCM_RATE_48000,
1071 .rate_min = 48000,
1072 .rate_max = 48000,
1073 .channels_min = 2,
1074 .channels_max = 2,
1075 .buffer_bytes_max = 128 * 1024,
1076 .period_bytes_min = 32,
1077 .period_bytes_max = 128 * 1024,
1078 .periods_min = 1,
1079 .periods_max = 1024,
1080 .fifo_size = 0,
1081};
1082
1083static const unsigned int channels4[] = {
1084 2, 4,
1085};
1086
1087static const struct snd_pcm_hw_constraint_list hw_constraints_channels4 = {
1088 .count = ARRAY_SIZE(channels4),
1089 .list = channels4,
1090 .mask = 0,
1091};
1092
1093static const unsigned int channels6[] = {
1094 2, 4, 6,
1095};
1096
1097static const struct snd_pcm_hw_constraint_list hw_constraints_channels6 = {
1098 .count = ARRAY_SIZE(channels6),
1099 .list = channels6,
1100 .mask = 0,
1101};
1102
1103static const unsigned int channels8[] = {
1104 2, 4, 6, 8,
1105};
1106
1107static const struct snd_pcm_hw_constraint_list hw_constraints_channels8 = {
1108 .count = ARRAY_SIZE(channels8),
1109 .list = channels8,
1110 .mask = 0,
1111};
1112
1113static int snd_intel8x0_pcm_open(struct snd_pcm_substream *substream, struct ichdev *ichdev)
1114{
1115 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1116 struct snd_pcm_runtime *runtime = substream->runtime;
1117 int err;
1118
1119 ichdev->substream = substream;
1120 runtime->hw = snd_intel8x0_stream;
1121 runtime->hw.rates = ichdev->pcm->rates;
1122 snd_pcm_limit_hw_rates(runtime);
1123 if (chip->device_type == DEVICE_SIS) {
1124 runtime->hw.buffer_bytes_max = 64*1024;
1125 runtime->hw.period_bytes_max = 64*1024;
1126 }
1127 if ((err = snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS)) < 0)
1128 return err;
1129 runtime->private_data = ichdev;
1130 return 0;
1131}
1132
1133static int snd_intel8x0_playback_open(struct snd_pcm_substream *substream)
1134{
1135 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1136 struct snd_pcm_runtime *runtime = substream->runtime;
1137 int err;
1138
1139 err = snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_PCMOUT]);
1140 if (err < 0)
1141 return err;
1142
1143 if (chip->multi8) {
1144 runtime->hw.channels_max = 8;
1145 snd_pcm_hw_constraint_list(runtime, 0,
1146 SNDRV_PCM_HW_PARAM_CHANNELS,
1147 &hw_constraints_channels8);
1148 } else if (chip->multi6) {
1149 runtime->hw.channels_max = 6;
1150 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
1151 &hw_constraints_channels6);
1152 } else if (chip->multi4) {
1153 runtime->hw.channels_max = 4;
1154 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
1155 &hw_constraints_channels4);
1156 }
1157 if (chip->dra) {
1158 snd_ac97_pcm_double_rate_rules(runtime);
1159 }
1160 if (chip->smp20bit) {
1161 runtime->hw.formats |= SNDRV_PCM_FMTBIT_S32_LE;
1162 snd_pcm_hw_constraint_msbits(runtime, 0, 32, 20);
1163 }
1164 return 0;
1165}
1166
1167static int snd_intel8x0_playback_close(struct snd_pcm_substream *substream)
1168{
1169 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1170
1171 chip->ichd[ICHD_PCMOUT].substream = NULL;
1172 return 0;
1173}
1174
1175static int snd_intel8x0_capture_open(struct snd_pcm_substream *substream)
1176{
1177 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1178
1179 return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_PCMIN]);
1180}
1181
1182static int snd_intel8x0_capture_close(struct snd_pcm_substream *substream)
1183{
1184 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1185
1186 chip->ichd[ICHD_PCMIN].substream = NULL;
1187 return 0;
1188}
1189
1190static int snd_intel8x0_mic_open(struct snd_pcm_substream *substream)
1191{
1192 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1193
1194 return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_MIC]);
1195}
1196
1197static int snd_intel8x0_mic_close(struct snd_pcm_substream *substream)
1198{
1199 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1200
1201 chip->ichd[ICHD_MIC].substream = NULL;
1202 return 0;
1203}
1204
1205static int snd_intel8x0_mic2_open(struct snd_pcm_substream *substream)
1206{
1207 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1208
1209 return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_MIC2]);
1210}
1211
1212static int snd_intel8x0_mic2_close(struct snd_pcm_substream *substream)
1213{
1214 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1215
1216 chip->ichd[ICHD_MIC2].substream = NULL;
1217 return 0;
1218}
1219
1220static int snd_intel8x0_capture2_open(struct snd_pcm_substream *substream)
1221{
1222 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1223
1224 return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_PCM2IN]);
1225}
1226
1227static int snd_intel8x0_capture2_close(struct snd_pcm_substream *substream)
1228{
1229 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1230
1231 chip->ichd[ICHD_PCM2IN].substream = NULL;
1232 return 0;
1233}
1234
1235static int snd_intel8x0_spdif_open(struct snd_pcm_substream *substream)
1236{
1237 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1238 int idx = chip->device_type == DEVICE_NFORCE ? NVD_SPBAR : ICHD_SPBAR;
1239
1240 return snd_intel8x0_pcm_open(substream, &chip->ichd[idx]);
1241}
1242
1243static int snd_intel8x0_spdif_close(struct snd_pcm_substream *substream)
1244{
1245 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1246 int idx = chip->device_type == DEVICE_NFORCE ? NVD_SPBAR : ICHD_SPBAR;
1247
1248 chip->ichd[idx].substream = NULL;
1249 return 0;
1250}
1251
1252static int snd_intel8x0_ali_ac97spdifout_open(struct snd_pcm_substream *substream)
1253{
1254 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1255 unsigned int val;
1256
1257 spin_lock_irq(&chip->reg_lock);
1258 val = igetdword(chip, ICHREG(ALI_INTERFACECR));
1259 val |= ICH_ALI_IF_AC97SP;
1260 iputdword(chip, ICHREG(ALI_INTERFACECR), val);
1261 /* also needs to set ALI_SC_CODEC_SPDF correctly */
1262 spin_unlock_irq(&chip->reg_lock);
1263
1264 return snd_intel8x0_pcm_open(substream, &chip->ichd[ALID_AC97SPDIFOUT]);
1265}
1266
1267static int snd_intel8x0_ali_ac97spdifout_close(struct snd_pcm_substream *substream)
1268{
1269 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1270 unsigned int val;
1271
1272 chip->ichd[ALID_AC97SPDIFOUT].substream = NULL;
1273 spin_lock_irq(&chip->reg_lock);
1274 val = igetdword(chip, ICHREG(ALI_INTERFACECR));
1275 val &= ~ICH_ALI_IF_AC97SP;
1276 iputdword(chip, ICHREG(ALI_INTERFACECR), val);
1277 spin_unlock_irq(&chip->reg_lock);
1278
1279 return 0;
1280}
1281
1282#if 0 // NYI
1283static int snd_intel8x0_ali_spdifin_open(struct snd_pcm_substream *substream)
1284{
1285 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1286
1287 return snd_intel8x0_pcm_open(substream, &chip->ichd[ALID_SPDIFIN]);
1288}
1289
1290static int snd_intel8x0_ali_spdifin_close(struct snd_pcm_substream *substream)
1291{
1292 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1293
1294 chip->ichd[ALID_SPDIFIN].substream = NULL;
1295 return 0;
1296}
1297
1298static int snd_intel8x0_ali_spdifout_open(struct snd_pcm_substream *substream)
1299{
1300 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1301
1302 return snd_intel8x0_pcm_open(substream, &chip->ichd[ALID_SPDIFOUT]);
1303}
1304
1305static int snd_intel8x0_ali_spdifout_close(struct snd_pcm_substream *substream)
1306{
1307 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1308
1309 chip->ichd[ALID_SPDIFOUT].substream = NULL;
1310 return 0;
1311}
1312#endif
1313
1314static const struct snd_pcm_ops snd_intel8x0_playback_ops = {
1315 .open = snd_intel8x0_playback_open,
1316 .close = snd_intel8x0_playback_close,
1317 .hw_params = snd_intel8x0_hw_params,
1318 .hw_free = snd_intel8x0_hw_free,
1319 .prepare = snd_intel8x0_pcm_prepare,
1320 .trigger = snd_intel8x0_pcm_trigger,
1321 .pointer = snd_intel8x0_pcm_pointer,
1322};
1323
1324static const struct snd_pcm_ops snd_intel8x0_capture_ops = {
1325 .open = snd_intel8x0_capture_open,
1326 .close = snd_intel8x0_capture_close,
1327 .hw_params = snd_intel8x0_hw_params,
1328 .hw_free = snd_intel8x0_hw_free,
1329 .prepare = snd_intel8x0_pcm_prepare,
1330 .trigger = snd_intel8x0_pcm_trigger,
1331 .pointer = snd_intel8x0_pcm_pointer,
1332};
1333
1334static const struct snd_pcm_ops snd_intel8x0_capture_mic_ops = {
1335 .open = snd_intel8x0_mic_open,
1336 .close = snd_intel8x0_mic_close,
1337 .hw_params = snd_intel8x0_hw_params,
1338 .hw_free = snd_intel8x0_hw_free,
1339 .prepare = snd_intel8x0_pcm_prepare,
1340 .trigger = snd_intel8x0_pcm_trigger,
1341 .pointer = snd_intel8x0_pcm_pointer,
1342};
1343
1344static const struct snd_pcm_ops snd_intel8x0_capture_mic2_ops = {
1345 .open = snd_intel8x0_mic2_open,
1346 .close = snd_intel8x0_mic2_close,
1347 .hw_params = snd_intel8x0_hw_params,
1348 .hw_free = snd_intel8x0_hw_free,
1349 .prepare = snd_intel8x0_pcm_prepare,
1350 .trigger = snd_intel8x0_pcm_trigger,
1351 .pointer = snd_intel8x0_pcm_pointer,
1352};
1353
1354static const struct snd_pcm_ops snd_intel8x0_capture2_ops = {
1355 .open = snd_intel8x0_capture2_open,
1356 .close = snd_intel8x0_capture2_close,
1357 .hw_params = snd_intel8x0_hw_params,
1358 .hw_free = snd_intel8x0_hw_free,
1359 .prepare = snd_intel8x0_pcm_prepare,
1360 .trigger = snd_intel8x0_pcm_trigger,
1361 .pointer = snd_intel8x0_pcm_pointer,
1362};
1363
1364static const struct snd_pcm_ops snd_intel8x0_spdif_ops = {
1365 .open = snd_intel8x0_spdif_open,
1366 .close = snd_intel8x0_spdif_close,
1367 .hw_params = snd_intel8x0_hw_params,
1368 .hw_free = snd_intel8x0_hw_free,
1369 .prepare = snd_intel8x0_pcm_prepare,
1370 .trigger = snd_intel8x0_pcm_trigger,
1371 .pointer = snd_intel8x0_pcm_pointer,
1372};
1373
1374static const struct snd_pcm_ops snd_intel8x0_ali_playback_ops = {
1375 .open = snd_intel8x0_playback_open,
1376 .close = snd_intel8x0_playback_close,
1377 .hw_params = snd_intel8x0_hw_params,
1378 .hw_free = snd_intel8x0_hw_free,
1379 .prepare = snd_intel8x0_pcm_prepare,
1380 .trigger = snd_intel8x0_ali_trigger,
1381 .pointer = snd_intel8x0_pcm_pointer,
1382};
1383
1384static const struct snd_pcm_ops snd_intel8x0_ali_capture_ops = {
1385 .open = snd_intel8x0_capture_open,
1386 .close = snd_intel8x0_capture_close,
1387 .hw_params = snd_intel8x0_hw_params,
1388 .hw_free = snd_intel8x0_hw_free,
1389 .prepare = snd_intel8x0_pcm_prepare,
1390 .trigger = snd_intel8x0_ali_trigger,
1391 .pointer = snd_intel8x0_pcm_pointer,
1392};
1393
1394static const struct snd_pcm_ops snd_intel8x0_ali_capture_mic_ops = {
1395 .open = snd_intel8x0_mic_open,
1396 .close = snd_intel8x0_mic_close,
1397 .hw_params = snd_intel8x0_hw_params,
1398 .hw_free = snd_intel8x0_hw_free,
1399 .prepare = snd_intel8x0_pcm_prepare,
1400 .trigger = snd_intel8x0_ali_trigger,
1401 .pointer = snd_intel8x0_pcm_pointer,
1402};
1403
1404static const struct snd_pcm_ops snd_intel8x0_ali_ac97spdifout_ops = {
1405 .open = snd_intel8x0_ali_ac97spdifout_open,
1406 .close = snd_intel8x0_ali_ac97spdifout_close,
1407 .hw_params = snd_intel8x0_hw_params,
1408 .hw_free = snd_intel8x0_hw_free,
1409 .prepare = snd_intel8x0_pcm_prepare,
1410 .trigger = snd_intel8x0_ali_trigger,
1411 .pointer = snd_intel8x0_pcm_pointer,
1412};
1413
1414#if 0 // NYI
1415static struct snd_pcm_ops snd_intel8x0_ali_spdifin_ops = {
1416 .open = snd_intel8x0_ali_spdifin_open,
1417 .close = snd_intel8x0_ali_spdifin_close,
1418 .hw_params = snd_intel8x0_hw_params,
1419 .hw_free = snd_intel8x0_hw_free,
1420 .prepare = snd_intel8x0_pcm_prepare,
1421 .trigger = snd_intel8x0_pcm_trigger,
1422 .pointer = snd_intel8x0_pcm_pointer,
1423};
1424
1425static struct snd_pcm_ops snd_intel8x0_ali_spdifout_ops = {
1426 .open = snd_intel8x0_ali_spdifout_open,
1427 .close = snd_intel8x0_ali_spdifout_close,
1428 .hw_params = snd_intel8x0_hw_params,
1429 .hw_free = snd_intel8x0_hw_free,
1430 .prepare = snd_intel8x0_pcm_prepare,
1431 .trigger = snd_intel8x0_pcm_trigger,
1432 .pointer = snd_intel8x0_pcm_pointer,
1433};
1434#endif // NYI
1435
1436struct ich_pcm_table {
1437 char *suffix;
1438 const struct snd_pcm_ops *playback_ops;
1439 const struct snd_pcm_ops *capture_ops;
1440 size_t prealloc_size;
1441 size_t prealloc_max_size;
1442 int ac97_idx;
1443};
1444
1445#define intel8x0_dma_type(chip) \
1446 ((chip)->fix_nocache ? SNDRV_DMA_TYPE_DEV_UC : SNDRV_DMA_TYPE_DEV)
1447
1448static int snd_intel8x0_pcm1(struct intel8x0 *chip, int device,
1449 const struct ich_pcm_table *rec)
1450{
1451 struct snd_pcm *pcm;
1452 int err;
1453 char name[32];
1454
1455 if (rec->suffix)
1456 sprintf(name, "Intel ICH - %s", rec->suffix);
1457 else
1458 strcpy(name, "Intel ICH");
1459 err = snd_pcm_new(chip->card, name, device,
1460 rec->playback_ops ? 1 : 0,
1461 rec->capture_ops ? 1 : 0, &pcm);
1462 if (err < 0)
1463 return err;
1464
1465 if (rec->playback_ops)
1466 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, rec->playback_ops);
1467 if (rec->capture_ops)
1468 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, rec->capture_ops);
1469
1470 pcm->private_data = chip;
1471 pcm->info_flags = 0;
1472 if (rec->suffix)
1473 sprintf(pcm->name, "%s - %s", chip->card->shortname, rec->suffix);
1474 else
1475 strcpy(pcm->name, chip->card->shortname);
1476 chip->pcm[device] = pcm;
1477
1478 snd_pcm_set_managed_buffer_all(pcm, intel8x0_dma_type(chip),
1479 &chip->pci->dev,
1480 rec->prealloc_size, rec->prealloc_max_size);
1481
1482 if (rec->playback_ops &&
1483 rec->playback_ops->open == snd_intel8x0_playback_open) {
1484 struct snd_pcm_chmap *chmap;
1485 int chs = 2;
1486 if (chip->multi8)
1487 chs = 8;
1488 else if (chip->multi6)
1489 chs = 6;
1490 else if (chip->multi4)
1491 chs = 4;
1492 err = snd_pcm_add_chmap_ctls(pcm, SNDRV_PCM_STREAM_PLAYBACK,
1493 snd_pcm_alt_chmaps, chs, 0,
1494 &chmap);
1495 if (err < 0)
1496 return err;
1497 chmap->channel_mask = SND_PCM_CHMAP_MASK_2468;
1498 chip->ac97[0]->chmaps[SNDRV_PCM_STREAM_PLAYBACK] = chmap;
1499 }
1500
1501 return 0;
1502}
1503
1504static const struct ich_pcm_table intel_pcms[] = {
1505 {
1506 .playback_ops = &snd_intel8x0_playback_ops,
1507 .capture_ops = &snd_intel8x0_capture_ops,
1508 .prealloc_size = 64 * 1024,
1509 .prealloc_max_size = 128 * 1024,
1510 },
1511 {
1512 .suffix = "MIC ADC",
1513 .capture_ops = &snd_intel8x0_capture_mic_ops,
1514 .prealloc_size = 0,
1515 .prealloc_max_size = 128 * 1024,
1516 .ac97_idx = ICHD_MIC,
1517 },
1518 {
1519 .suffix = "MIC2 ADC",
1520 .capture_ops = &snd_intel8x0_capture_mic2_ops,
1521 .prealloc_size = 0,
1522 .prealloc_max_size = 128 * 1024,
1523 .ac97_idx = ICHD_MIC2,
1524 },
1525 {
1526 .suffix = "ADC2",
1527 .capture_ops = &snd_intel8x0_capture2_ops,
1528 .prealloc_size = 0,
1529 .prealloc_max_size = 128 * 1024,
1530 .ac97_idx = ICHD_PCM2IN,
1531 },
1532 {
1533 .suffix = "IEC958",
1534 .playback_ops = &snd_intel8x0_spdif_ops,
1535 .prealloc_size = 64 * 1024,
1536 .prealloc_max_size = 128 * 1024,
1537 .ac97_idx = ICHD_SPBAR,
1538 },
1539};
1540
1541static const struct ich_pcm_table nforce_pcms[] = {
1542 {
1543 .playback_ops = &snd_intel8x0_playback_ops,
1544 .capture_ops = &snd_intel8x0_capture_ops,
1545 .prealloc_size = 64 * 1024,
1546 .prealloc_max_size = 128 * 1024,
1547 },
1548 {
1549 .suffix = "MIC ADC",
1550 .capture_ops = &snd_intel8x0_capture_mic_ops,
1551 .prealloc_size = 0,
1552 .prealloc_max_size = 128 * 1024,
1553 .ac97_idx = NVD_MIC,
1554 },
1555 {
1556 .suffix = "IEC958",
1557 .playback_ops = &snd_intel8x0_spdif_ops,
1558 .prealloc_size = 64 * 1024,
1559 .prealloc_max_size = 128 * 1024,
1560 .ac97_idx = NVD_SPBAR,
1561 },
1562};
1563
1564static const struct ich_pcm_table ali_pcms[] = {
1565 {
1566 .playback_ops = &snd_intel8x0_ali_playback_ops,
1567 .capture_ops = &snd_intel8x0_ali_capture_ops,
1568 .prealloc_size = 64 * 1024,
1569 .prealloc_max_size = 128 * 1024,
1570 },
1571 {
1572 .suffix = "MIC ADC",
1573 .capture_ops = &snd_intel8x0_ali_capture_mic_ops,
1574 .prealloc_size = 0,
1575 .prealloc_max_size = 128 * 1024,
1576 .ac97_idx = ALID_MIC,
1577 },
1578 {
1579 .suffix = "IEC958",
1580 .playback_ops = &snd_intel8x0_ali_ac97spdifout_ops,
1581 /* .capture_ops = &snd_intel8x0_ali_spdifin_ops, */
1582 .prealloc_size = 64 * 1024,
1583 .prealloc_max_size = 128 * 1024,
1584 .ac97_idx = ALID_AC97SPDIFOUT,
1585 },
1586#if 0 // NYI
1587 {
1588 .suffix = "HW IEC958",
1589 .playback_ops = &snd_intel8x0_ali_spdifout_ops,
1590 .prealloc_size = 64 * 1024,
1591 .prealloc_max_size = 128 * 1024,
1592 },
1593#endif
1594};
1595
1596static int snd_intel8x0_pcm(struct intel8x0 *chip)
1597{
1598 int i, tblsize, device, err;
1599 const struct ich_pcm_table *tbl, *rec;
1600
1601 switch (chip->device_type) {
1602 case DEVICE_INTEL_ICH4:
1603 tbl = intel_pcms;
1604 tblsize = ARRAY_SIZE(intel_pcms);
1605 if (spdif_aclink)
1606 tblsize--;
1607 break;
1608 case DEVICE_NFORCE:
1609 tbl = nforce_pcms;
1610 tblsize = ARRAY_SIZE(nforce_pcms);
1611 if (spdif_aclink)
1612 tblsize--;
1613 break;
1614 case DEVICE_ALI:
1615 tbl = ali_pcms;
1616 tblsize = ARRAY_SIZE(ali_pcms);
1617 break;
1618 default:
1619 tbl = intel_pcms;
1620 tblsize = 2;
1621 break;
1622 }
1623
1624 device = 0;
1625 for (i = 0; i < tblsize; i++) {
1626 rec = tbl + i;
1627 if (i > 0 && rec->ac97_idx) {
1628 /* activate PCM only when associated AC'97 codec */
1629 if (! chip->ichd[rec->ac97_idx].pcm)
1630 continue;
1631 }
1632 err = snd_intel8x0_pcm1(chip, device, rec);
1633 if (err < 0)
1634 return err;
1635 device++;
1636 }
1637
1638 chip->pcm_devs = device;
1639 return 0;
1640}
1641
1642
1643/*
1644 * Mixer part
1645 */
1646
1647static void snd_intel8x0_mixer_free_ac97_bus(struct snd_ac97_bus *bus)
1648{
1649 struct intel8x0 *chip = bus->private_data;
1650 chip->ac97_bus = NULL;
1651}
1652
1653static void snd_intel8x0_mixer_free_ac97(struct snd_ac97 *ac97)
1654{
1655 struct intel8x0 *chip = ac97->private_data;
1656 chip->ac97[ac97->num] = NULL;
1657}
1658
1659static const struct ac97_pcm ac97_pcm_defs[] = {
1660 /* front PCM */
1661 {
1662 .exclusive = 1,
1663 .r = { {
1664 .slots = (1 << AC97_SLOT_PCM_LEFT) |
1665 (1 << AC97_SLOT_PCM_RIGHT) |
1666 (1 << AC97_SLOT_PCM_CENTER) |
1667 (1 << AC97_SLOT_PCM_SLEFT) |
1668 (1 << AC97_SLOT_PCM_SRIGHT) |
1669 (1 << AC97_SLOT_LFE)
1670 },
1671 {
1672 .slots = (1 << AC97_SLOT_PCM_LEFT) |
1673 (1 << AC97_SLOT_PCM_RIGHT) |
1674 (1 << AC97_SLOT_PCM_LEFT_0) |
1675 (1 << AC97_SLOT_PCM_RIGHT_0)
1676 }
1677 }
1678 },
1679 /* PCM IN #1 */
1680 {
1681 .stream = 1,
1682 .exclusive = 1,
1683 .r = { {
1684 .slots = (1 << AC97_SLOT_PCM_LEFT) |
1685 (1 << AC97_SLOT_PCM_RIGHT)
1686 }
1687 }
1688 },
1689 /* MIC IN #1 */
1690 {
1691 .stream = 1,
1692 .exclusive = 1,
1693 .r = { {
1694 .slots = (1 << AC97_SLOT_MIC)
1695 }
1696 }
1697 },
1698 /* S/PDIF PCM */
1699 {
1700 .exclusive = 1,
1701 .spdif = 1,
1702 .r = { {
1703 .slots = (1 << AC97_SLOT_SPDIF_LEFT2) |
1704 (1 << AC97_SLOT_SPDIF_RIGHT2)
1705 }
1706 }
1707 },
1708 /* PCM IN #2 */
1709 {
1710 .stream = 1,
1711 .exclusive = 1,
1712 .r = { {
1713 .slots = (1 << AC97_SLOT_PCM_LEFT) |
1714 (1 << AC97_SLOT_PCM_RIGHT)
1715 }
1716 }
1717 },
1718 /* MIC IN #2 */
1719 {
1720 .stream = 1,
1721 .exclusive = 1,
1722 .r = { {
1723 .slots = (1 << AC97_SLOT_MIC)
1724 }
1725 }
1726 },
1727};
1728
1729static const struct ac97_quirk ac97_quirks[] = {
1730 {
1731 .subvendor = 0x0e11,
1732 .subdevice = 0x000e,
1733 .name = "Compaq Deskpro EN", /* AD1885 */
1734 .type = AC97_TUNE_HP_ONLY
1735 },
1736 {
1737 .subvendor = 0x0e11,
1738 .subdevice = 0x008a,
1739 .name = "Compaq Evo W4000", /* AD1885 */
1740 .type = AC97_TUNE_HP_ONLY
1741 },
1742 {
1743 .subvendor = 0x0e11,
1744 .subdevice = 0x00b8,
1745 .name = "Compaq Evo D510C",
1746 .type = AC97_TUNE_HP_ONLY
1747 },
1748 {
1749 .subvendor = 0x0e11,
1750 .subdevice = 0x0860,
1751 .name = "HP/Compaq nx7010",
1752 .type = AC97_TUNE_MUTE_LED
1753 },
1754 {
1755 .subvendor = 0x1014,
1756 .subdevice = 0x0534,
1757 .name = "ThinkPad X31",
1758 .type = AC97_TUNE_INV_EAPD
1759 },
1760 {
1761 .subvendor = 0x1014,
1762 .subdevice = 0x1f00,
1763 .name = "MS-9128",
1764 .type = AC97_TUNE_ALC_JACK
1765 },
1766 {
1767 .subvendor = 0x1014,
1768 .subdevice = 0x0267,
1769 .name = "IBM NetVista A30p", /* AD1981B */
1770 .type = AC97_TUNE_HP_ONLY
1771 },
1772 {
1773 .subvendor = 0x1025,
1774 .subdevice = 0x0082,
1775 .name = "Acer Travelmate 2310",
1776 .type = AC97_TUNE_HP_ONLY
1777 },
1778 {
1779 .subvendor = 0x1025,
1780 .subdevice = 0x0083,
1781 .name = "Acer Aspire 3003LCi",
1782 .type = AC97_TUNE_HP_ONLY
1783 },
1784 {
1785 .subvendor = 0x1028,
1786 .subdevice = 0x00d8,
1787 .name = "Dell Precision 530", /* AD1885 */
1788 .type = AC97_TUNE_HP_ONLY
1789 },
1790 {
1791 .subvendor = 0x1028,
1792 .subdevice = 0x010d,
1793 .name = "Dell", /* which model? AD1885 */
1794 .type = AC97_TUNE_HP_ONLY
1795 },
1796 {
1797 .subvendor = 0x1028,
1798 .subdevice = 0x0126,
1799 .name = "Dell Optiplex GX260", /* AD1981A */
1800 .type = AC97_TUNE_HP_ONLY
1801 },
1802 {
1803 .subvendor = 0x1028,
1804 .subdevice = 0x012c,
1805 .name = "Dell Precision 650", /* AD1981A */
1806 .type = AC97_TUNE_HP_ONLY
1807 },
1808 {
1809 .subvendor = 0x1028,
1810 .subdevice = 0x012d,
1811 .name = "Dell Precision 450", /* AD1981B*/
1812 .type = AC97_TUNE_HP_ONLY
1813 },
1814 {
1815 .subvendor = 0x1028,
1816 .subdevice = 0x0147,
1817 .name = "Dell", /* which model? AD1981B*/
1818 .type = AC97_TUNE_HP_ONLY
1819 },
1820 {
1821 .subvendor = 0x1028,
1822 .subdevice = 0x0151,
1823 .name = "Dell Optiplex GX270", /* AD1981B */
1824 .type = AC97_TUNE_HP_ONLY
1825 },
1826 {
1827 .subvendor = 0x1028,
1828 .subdevice = 0x014e,
1829 .name = "Dell D800", /* STAC9750/51 */
1830 .type = AC97_TUNE_HP_ONLY
1831 },
1832 {
1833 .subvendor = 0x1028,
1834 .subdevice = 0x0163,
1835 .name = "Dell Unknown", /* STAC9750/51 */
1836 .type = AC97_TUNE_HP_ONLY
1837 },
1838 {
1839 .subvendor = 0x1028,
1840 .subdevice = 0x016a,
1841 .name = "Dell Inspiron 8600", /* STAC9750/51 */
1842 .type = AC97_TUNE_HP_ONLY
1843 },
1844 {
1845 .subvendor = 0x1028,
1846 .subdevice = 0x0182,
1847 .name = "Dell Latitude D610", /* STAC9750/51 */
1848 .type = AC97_TUNE_HP_ONLY
1849 },
1850 {
1851 .subvendor = 0x1028,
1852 .subdevice = 0x0186,
1853 .name = "Dell Latitude D810", /* cf. Malone #41015 */
1854 .type = AC97_TUNE_HP_MUTE_LED
1855 },
1856 {
1857 .subvendor = 0x1028,
1858 .subdevice = 0x0188,
1859 .name = "Dell Inspiron 6000",
1860 .type = AC97_TUNE_HP_MUTE_LED /* cf. Malone #41015 */
1861 },
1862 {
1863 .subvendor = 0x1028,
1864 .subdevice = 0x0189,
1865 .name = "Dell Inspiron 9300",
1866 .type = AC97_TUNE_HP_MUTE_LED
1867 },
1868 {
1869 .subvendor = 0x1028,
1870 .subdevice = 0x0191,
1871 .name = "Dell Inspiron 8600",
1872 .type = AC97_TUNE_HP_ONLY
1873 },
1874 {
1875 .subvendor = 0x103c,
1876 .subdevice = 0x006d,
1877 .name = "HP zv5000",
1878 .type = AC97_TUNE_MUTE_LED /*AD1981B*/
1879 },
1880 { /* FIXME: which codec? */
1881 .subvendor = 0x103c,
1882 .subdevice = 0x00c3,
1883 .name = "HP xw6000",
1884 .type = AC97_TUNE_HP_ONLY
1885 },
1886 {
1887 .subvendor = 0x103c,
1888 .subdevice = 0x088c,
1889 .name = "HP nc8000",
1890 .type = AC97_TUNE_HP_MUTE_LED
1891 },
1892 {
1893 .subvendor = 0x103c,
1894 .subdevice = 0x0890,
1895 .name = "HP nc6000",
1896 .type = AC97_TUNE_MUTE_LED
1897 },
1898 {
1899 .subvendor = 0x103c,
1900 .subdevice = 0x129d,
1901 .name = "HP xw8000",
1902 .type = AC97_TUNE_HP_ONLY
1903 },
1904 {
1905 .subvendor = 0x103c,
1906 .subdevice = 0x0938,
1907 .name = "HP nc4200",
1908 .type = AC97_TUNE_HP_MUTE_LED
1909 },
1910 {
1911 .subvendor = 0x103c,
1912 .subdevice = 0x099c,
1913 .name = "HP nx6110/nc6120",
1914 .type = AC97_TUNE_HP_MUTE_LED
1915 },
1916 {
1917 .subvendor = 0x103c,
1918 .subdevice = 0x0944,
1919 .name = "HP nc6220",
1920 .type = AC97_TUNE_HP_MUTE_LED
1921 },
1922 {
1923 .subvendor = 0x103c,
1924 .subdevice = 0x0934,
1925 .name = "HP nc8220",
1926 .type = AC97_TUNE_HP_MUTE_LED
1927 },
1928 {
1929 .subvendor = 0x103c,
1930 .subdevice = 0x12f1,
1931 .name = "HP xw8200", /* AD1981B*/
1932 .type = AC97_TUNE_HP_ONLY
1933 },
1934 {
1935 .subvendor = 0x103c,
1936 .subdevice = 0x12f2,
1937 .name = "HP xw6200",
1938 .type = AC97_TUNE_HP_ONLY
1939 },
1940 {
1941 .subvendor = 0x103c,
1942 .subdevice = 0x3008,
1943 .name = "HP xw4200", /* AD1981B*/
1944 .type = AC97_TUNE_HP_ONLY
1945 },
1946 {
1947 .subvendor = 0x104d,
1948 .subdevice = 0x8144,
1949 .name = "Sony",
1950 .type = AC97_TUNE_INV_EAPD
1951 },
1952 {
1953 .subvendor = 0x104d,
1954 .subdevice = 0x8197,
1955 .name = "Sony S1XP",
1956 .type = AC97_TUNE_INV_EAPD
1957 },
1958 {
1959 .subvendor = 0x104d,
1960 .subdevice = 0x81c0,
1961 .name = "Sony VAIO VGN-T350P", /*AD1981B*/
1962 .type = AC97_TUNE_INV_EAPD
1963 },
1964 {
1965 .subvendor = 0x104d,
1966 .subdevice = 0x81c5,
1967 .name = "Sony VAIO VGN-B1VP", /*AD1981B*/
1968 .type = AC97_TUNE_INV_EAPD
1969 },
1970 {
1971 .subvendor = 0x1043,
1972 .subdevice = 0x80f3,
1973 .name = "ASUS ICH5/AD1985",
1974 .type = AC97_TUNE_AD_SHARING
1975 },
1976 {
1977 .subvendor = 0x10cf,
1978 .subdevice = 0x11c3,
1979 .name = "Fujitsu-Siemens E4010",
1980 .type = AC97_TUNE_HP_ONLY
1981 },
1982 {
1983 .subvendor = 0x10cf,
1984 .subdevice = 0x1225,
1985 .name = "Fujitsu-Siemens T3010",
1986 .type = AC97_TUNE_HP_ONLY
1987 },
1988 {
1989 .subvendor = 0x10cf,
1990 .subdevice = 0x1253,
1991 .name = "Fujitsu S6210", /* STAC9750/51 */
1992 .type = AC97_TUNE_HP_ONLY
1993 },
1994 {
1995 .subvendor = 0x10cf,
1996 .subdevice = 0x127d,
1997 .name = "Fujitsu Lifebook P7010",
1998 .type = AC97_TUNE_HP_ONLY
1999 },
2000 {
2001 .subvendor = 0x10cf,
2002 .subdevice = 0x127e,
2003 .name = "Fujitsu Lifebook C1211D",
2004 .type = AC97_TUNE_HP_ONLY
2005 },
2006 {
2007 .subvendor = 0x10cf,
2008 .subdevice = 0x12ec,
2009 .name = "Fujitsu-Siemens 4010",
2010 .type = AC97_TUNE_HP_ONLY
2011 },
2012 {
2013 .subvendor = 0x10cf,
2014 .subdevice = 0x12f2,
2015 .name = "Fujitsu-Siemens Celsius H320",
2016 .type = AC97_TUNE_SWAP_HP
2017 },
2018 {
2019 .subvendor = 0x10f1,
2020 .subdevice = 0x2665,
2021 .name = "Fujitsu-Siemens Celsius", /* AD1981? */
2022 .type = AC97_TUNE_HP_ONLY
2023 },
2024 {
2025 .subvendor = 0x10f1,
2026 .subdevice = 0x2885,
2027 .name = "AMD64 Mobo", /* ALC650 */
2028 .type = AC97_TUNE_HP_ONLY
2029 },
2030 {
2031 .subvendor = 0x10f1,
2032 .subdevice = 0x2895,
2033 .name = "Tyan Thunder K8WE",
2034 .type = AC97_TUNE_HP_ONLY
2035 },
2036 {
2037 .subvendor = 0x10f7,
2038 .subdevice = 0x834c,
2039 .name = "Panasonic CF-R4",
2040 .type = AC97_TUNE_HP_ONLY,
2041 },
2042 {
2043 .subvendor = 0x110a,
2044 .subdevice = 0x0056,
2045 .name = "Fujitsu-Siemens Scenic", /* AD1981? */
2046 .type = AC97_TUNE_HP_ONLY
2047 },
2048 {
2049 .subvendor = 0x11d4,
2050 .subdevice = 0x5375,
2051 .name = "ADI AD1985 (discrete)",
2052 .type = AC97_TUNE_HP_ONLY
2053 },
2054 {
2055 .subvendor = 0x1462,
2056 .subdevice = 0x5470,
2057 .name = "MSI P4 ATX 645 Ultra",
2058 .type = AC97_TUNE_HP_ONLY
2059 },
2060 {
2061 .subvendor = 0x161f,
2062 .subdevice = 0x202f,
2063 .name = "Gateway M520",
2064 .type = AC97_TUNE_INV_EAPD
2065 },
2066 {
2067 .subvendor = 0x161f,
2068 .subdevice = 0x203a,
2069 .name = "Gateway 4525GZ", /* AD1981B */
2070 .type = AC97_TUNE_INV_EAPD
2071 },
2072 {
2073 .subvendor = 0x1734,
2074 .subdevice = 0x0088,
2075 .name = "Fujitsu-Siemens D1522", /* AD1981 */
2076 .type = AC97_TUNE_HP_ONLY
2077 },
2078 {
2079 .subvendor = 0x8086,
2080 .subdevice = 0x2000,
2081 .mask = 0xfff0,
2082 .name = "Intel ICH5/AD1985",
2083 .type = AC97_TUNE_AD_SHARING
2084 },
2085 {
2086 .subvendor = 0x8086,
2087 .subdevice = 0x4000,
2088 .mask = 0xfff0,
2089 .name = "Intel ICH5/AD1985",
2090 .type = AC97_TUNE_AD_SHARING
2091 },
2092 {
2093 .subvendor = 0x8086,
2094 .subdevice = 0x4856,
2095 .name = "Intel D845WN (82801BA)",
2096 .type = AC97_TUNE_SWAP_HP
2097 },
2098 {
2099 .subvendor = 0x8086,
2100 .subdevice = 0x4d44,
2101 .name = "Intel D850EMV2", /* AD1885 */
2102 .type = AC97_TUNE_HP_ONLY
2103 },
2104 {
2105 .subvendor = 0x8086,
2106 .subdevice = 0x4d56,
2107 .name = "Intel ICH/AD1885",
2108 .type = AC97_TUNE_HP_ONLY
2109 },
2110 {
2111 .subvendor = 0x8086,
2112 .subdevice = 0x6000,
2113 .mask = 0xfff0,
2114 .name = "Intel ICH5/AD1985",
2115 .type = AC97_TUNE_AD_SHARING
2116 },
2117 {
2118 .subvendor = 0x8086,
2119 .subdevice = 0xe000,
2120 .mask = 0xfff0,
2121 .name = "Intel ICH5/AD1985",
2122 .type = AC97_TUNE_AD_SHARING
2123 },
2124#if 0 /* FIXME: this seems wrong on most boards */
2125 {
2126 .subvendor = 0x8086,
2127 .subdevice = 0xa000,
2128 .mask = 0xfff0,
2129 .name = "Intel ICH5/AD1985",
2130 .type = AC97_TUNE_HP_ONLY
2131 },
2132#endif
2133 {0} /* terminator */
2134};
2135
2136static int snd_intel8x0_mixer(struct intel8x0 *chip, int ac97_clock,
2137 const char *quirk_override)
2138{
2139 struct snd_ac97_bus *pbus;
2140 struct snd_ac97_template ac97;
2141 int err;
2142 unsigned int i, codecs;
2143 unsigned int glob_sta = 0;
2144 const struct snd_ac97_bus_ops *ops;
2145 static const struct snd_ac97_bus_ops standard_bus_ops = {
2146 .write = snd_intel8x0_codec_write,
2147 .read = snd_intel8x0_codec_read,
2148 };
2149 static const struct snd_ac97_bus_ops ali_bus_ops = {
2150 .write = snd_intel8x0_ali_codec_write,
2151 .read = snd_intel8x0_ali_codec_read,
2152 };
2153
2154 chip->spdif_idx = -1; /* use PCMOUT (or disabled) */
2155 if (!spdif_aclink) {
2156 switch (chip->device_type) {
2157 case DEVICE_NFORCE:
2158 chip->spdif_idx = NVD_SPBAR;
2159 break;
2160 case DEVICE_ALI:
2161 chip->spdif_idx = ALID_AC97SPDIFOUT;
2162 break;
2163 case DEVICE_INTEL_ICH4:
2164 chip->spdif_idx = ICHD_SPBAR;
2165 break;
2166 }
2167 }
2168
2169 chip->in_ac97_init = 1;
2170
2171 memset(&ac97, 0, sizeof(ac97));
2172 ac97.private_data = chip;
2173 ac97.private_free = snd_intel8x0_mixer_free_ac97;
2174 ac97.scaps = AC97_SCAP_SKIP_MODEM | AC97_SCAP_POWER_SAVE;
2175 if (chip->xbox)
2176 ac97.scaps |= AC97_SCAP_DETECT_BY_VENDOR;
2177 if (chip->device_type != DEVICE_ALI) {
2178 glob_sta = igetdword(chip, ICHREG(GLOB_STA));
2179 ops = &standard_bus_ops;
2180 chip->in_sdin_init = 1;
2181 codecs = 0;
2182 for (i = 0; i < chip->max_codecs; i++) {
2183 if (! (glob_sta & chip->codec_bit[i]))
2184 continue;
2185 if (chip->device_type == DEVICE_INTEL_ICH4) {
2186 snd_intel8x0_codec_read_test(chip, codecs);
2187 chip->ac97_sdin[codecs] =
2188 igetbyte(chip, ICHREG(SDM)) & ICH_LDI_MASK;
2189 if (snd_BUG_ON(chip->ac97_sdin[codecs] >= 3))
2190 chip->ac97_sdin[codecs] = 0;
2191 } else
2192 chip->ac97_sdin[codecs] = i;
2193 codecs++;
2194 }
2195 chip->in_sdin_init = 0;
2196 if (! codecs)
2197 codecs = 1;
2198 } else {
2199 ops = &ali_bus_ops;
2200 codecs = 1;
2201 /* detect the secondary codec */
2202 for (i = 0; i < 100; i++) {
2203 unsigned int reg = igetdword(chip, ICHREG(ALI_RTSR));
2204 if (reg & 0x40) {
2205 codecs = 2;
2206 break;
2207 }
2208 iputdword(chip, ICHREG(ALI_RTSR), reg | 0x40);
2209 udelay(1);
2210 }
2211 }
2212 if ((err = snd_ac97_bus(chip->card, 0, ops, chip, &pbus)) < 0)
2213 goto __err;
2214 pbus->private_free = snd_intel8x0_mixer_free_ac97_bus;
2215 if (ac97_clock >= 8000 && ac97_clock <= 48000)
2216 pbus->clock = ac97_clock;
2217 /* FIXME: my test board doesn't work well with VRA... */
2218 if (chip->device_type == DEVICE_ALI)
2219 pbus->no_vra = 1;
2220 else
2221 pbus->dra = 1;
2222 chip->ac97_bus = pbus;
2223 chip->ncodecs = codecs;
2224
2225 ac97.pci = chip->pci;
2226 for (i = 0; i < codecs; i++) {
2227 ac97.num = i;
2228 if ((err = snd_ac97_mixer(pbus, &ac97, &chip->ac97[i])) < 0) {
2229 if (err != -EACCES)
2230 dev_err(chip->card->dev,
2231 "Unable to initialize codec #%d\n", i);
2232 if (i == 0)
2233 goto __err;
2234 }
2235 }
2236 /* tune up the primary codec */
2237 snd_ac97_tune_hardware(chip->ac97[0], ac97_quirks, quirk_override);
2238 /* enable separate SDINs for ICH4 */
2239 if (chip->device_type == DEVICE_INTEL_ICH4)
2240 pbus->isdin = 1;
2241 /* find the available PCM streams */
2242 i = ARRAY_SIZE(ac97_pcm_defs);
2243 if (chip->device_type != DEVICE_INTEL_ICH4)
2244 i -= 2; /* do not allocate PCM2IN and MIC2 */
2245 if (chip->spdif_idx < 0)
2246 i--; /* do not allocate S/PDIF */
2247 err = snd_ac97_pcm_assign(pbus, i, ac97_pcm_defs);
2248 if (err < 0)
2249 goto __err;
2250 chip->ichd[ICHD_PCMOUT].pcm = &pbus->pcms[0];
2251 chip->ichd[ICHD_PCMIN].pcm = &pbus->pcms[1];
2252 chip->ichd[ICHD_MIC].pcm = &pbus->pcms[2];
2253 if (chip->spdif_idx >= 0)
2254 chip->ichd[chip->spdif_idx].pcm = &pbus->pcms[3];
2255 if (chip->device_type == DEVICE_INTEL_ICH4) {
2256 chip->ichd[ICHD_PCM2IN].pcm = &pbus->pcms[4];
2257 chip->ichd[ICHD_MIC2].pcm = &pbus->pcms[5];
2258 }
2259 /* enable separate SDINs for ICH4 */
2260 if (chip->device_type == DEVICE_INTEL_ICH4) {
2261 struct ac97_pcm *pcm = chip->ichd[ICHD_PCM2IN].pcm;
2262 u8 tmp = igetbyte(chip, ICHREG(SDM));
2263 tmp &= ~(ICH_DI2L_MASK|ICH_DI1L_MASK);
2264 if (pcm) {
2265 tmp |= ICH_SE; /* steer enable for multiple SDINs */
2266 tmp |= chip->ac97_sdin[0] << ICH_DI1L_SHIFT;
2267 for (i = 1; i < 4; i++) {
2268 if (pcm->r[0].codec[i]) {
2269 tmp |= chip->ac97_sdin[pcm->r[0].codec[1]->num] << ICH_DI2L_SHIFT;
2270 break;
2271 }
2272 }
2273 } else {
2274 tmp &= ~ICH_SE; /* steer disable */
2275 }
2276 iputbyte(chip, ICHREG(SDM), tmp);
2277 }
2278 if (pbus->pcms[0].r[0].slots & (1 << AC97_SLOT_PCM_SLEFT)) {
2279 chip->multi4 = 1;
2280 if (pbus->pcms[0].r[0].slots & (1 << AC97_SLOT_LFE)) {
2281 chip->multi6 = 1;
2282 if (chip->ac97[0]->flags & AC97_HAS_8CH)
2283 chip->multi8 = 1;
2284 }
2285 }
2286 if (pbus->pcms[0].r[1].rslots[0]) {
2287 chip->dra = 1;
2288 }
2289 if (chip->device_type == DEVICE_INTEL_ICH4) {
2290 if ((igetdword(chip, ICHREG(GLOB_STA)) & ICH_SAMPLE_CAP) == ICH_SAMPLE_16_20)
2291 chip->smp20bit = 1;
2292 }
2293 if (chip->device_type == DEVICE_NFORCE && !spdif_aclink) {
2294 /* 48kHz only */
2295 chip->ichd[chip->spdif_idx].pcm->rates = SNDRV_PCM_RATE_48000;
2296 }
2297 if (chip->device_type == DEVICE_INTEL_ICH4 && !spdif_aclink) {
2298 /* use slot 10/11 for SPDIF */
2299 u32 val;
2300 val = igetdword(chip, ICHREG(GLOB_CNT)) & ~ICH_PCM_SPDIF_MASK;
2301 val |= ICH_PCM_SPDIF_1011;
2302 iputdword(chip, ICHREG(GLOB_CNT), val);
2303 snd_ac97_update_bits(chip->ac97[0], AC97_EXTENDED_STATUS, 0x03 << 4, 0x03 << 4);
2304 }
2305 chip->in_ac97_init = 0;
2306 return 0;
2307
2308 __err:
2309 /* clear the cold-reset bit for the next chance */
2310 if (chip->device_type != DEVICE_ALI)
2311 iputdword(chip, ICHREG(GLOB_CNT),
2312 igetdword(chip, ICHREG(GLOB_CNT)) & ~ICH_AC97COLD);
2313 return err;
2314}
2315
2316
2317/*
2318 *
2319 */
2320
2321static void do_ali_reset(struct intel8x0 *chip)
2322{
2323 iputdword(chip, ICHREG(ALI_SCR), ICH_ALI_SC_RESET);
2324 iputdword(chip, ICHREG(ALI_FIFOCR1), 0x83838383);
2325 iputdword(chip, ICHREG(ALI_FIFOCR2), 0x83838383);
2326 iputdword(chip, ICHREG(ALI_FIFOCR3), 0x83838383);
2327 iputdword(chip, ICHREG(ALI_INTERFACECR),
2328 ICH_ALI_IF_PI|ICH_ALI_IF_PO);
2329 iputdword(chip, ICHREG(ALI_INTERRUPTCR), 0x00000000);
2330 iputdword(chip, ICHREG(ALI_INTERRUPTSR), 0x00000000);
2331}
2332
2333#ifdef CONFIG_SND_AC97_POWER_SAVE
2334static const struct snd_pci_quirk ich_chip_reset_mode[] = {
2335 SND_PCI_QUIRK(0x1014, 0x051f, "Thinkpad R32", 1),
2336 {0} /* end */
2337};
2338
2339static int snd_intel8x0_ich_chip_cold_reset(struct intel8x0 *chip)
2340{
2341 unsigned int cnt;
2342 /* ACLink on, 2 channels */
2343
2344 if (snd_pci_quirk_lookup(chip->pci, ich_chip_reset_mode))
2345 return -EIO;
2346
2347 cnt = igetdword(chip, ICHREG(GLOB_CNT));
2348 cnt &= ~(ICH_ACLINK | ICH_PCM_246_MASK);
2349
2350 /* do cold reset - the full ac97 powerdown may leave the controller
2351 * in a warm state but actually it cannot communicate with the codec.
2352 */
2353 iputdword(chip, ICHREG(GLOB_CNT), cnt & ~ICH_AC97COLD);
2354 cnt = igetdword(chip, ICHREG(GLOB_CNT));
2355 udelay(10);
2356 iputdword(chip, ICHREG(GLOB_CNT), cnt | ICH_AC97COLD);
2357 msleep(1);
2358 return 0;
2359}
2360#define snd_intel8x0_ich_chip_can_cold_reset(chip) \
2361 (!snd_pci_quirk_lookup(chip->pci, ich_chip_reset_mode))
2362#else
2363#define snd_intel8x0_ich_chip_cold_reset(chip) 0
2364#define snd_intel8x0_ich_chip_can_cold_reset(chip) (0)
2365#endif
2366
2367static int snd_intel8x0_ich_chip_reset(struct intel8x0 *chip)
2368{
2369 unsigned long end_time;
2370 unsigned int cnt;
2371 /* ACLink on, 2 channels */
2372 cnt = igetdword(chip, ICHREG(GLOB_CNT));
2373 cnt &= ~(ICH_ACLINK | ICH_PCM_246_MASK);
2374 /* finish cold or do warm reset */
2375 cnt |= (cnt & ICH_AC97COLD) == 0 ? ICH_AC97COLD : ICH_AC97WARM;
2376 iputdword(chip, ICHREG(GLOB_CNT), cnt);
2377 end_time = (jiffies + (HZ / 4)) + 1;
2378 do {
2379 if ((igetdword(chip, ICHREG(GLOB_CNT)) & ICH_AC97WARM) == 0)
2380 return 0;
2381 schedule_timeout_uninterruptible(1);
2382 } while (time_after_eq(end_time, jiffies));
2383 dev_err(chip->card->dev, "AC'97 warm reset still in progress? [0x%x]\n",
2384 igetdword(chip, ICHREG(GLOB_CNT)));
2385 return -EIO;
2386}
2387
2388static int snd_intel8x0_ich_chip_init(struct intel8x0 *chip, int probing)
2389{
2390 unsigned long end_time;
2391 unsigned int status, nstatus;
2392 unsigned int cnt;
2393 int err;
2394
2395 /* put logic to right state */
2396 /* first clear status bits */
2397 status = ICH_RCS | ICH_MCINT | ICH_POINT | ICH_PIINT;
2398 if (chip->device_type == DEVICE_NFORCE)
2399 status |= ICH_NVSPINT;
2400 cnt = igetdword(chip, ICHREG(GLOB_STA));
2401 iputdword(chip, ICHREG(GLOB_STA), cnt & status);
2402
2403#ifdef CONFIG_SND_AC97_POWER_SAVE
2404 if (snd_intel8x0_ich_chip_can_cold_reset(chip))
2405 err = snd_intel8x0_ich_chip_cold_reset(chip);
2406 else
2407#endif
2408 err = snd_intel8x0_ich_chip_reset(chip);
2409 if (err < 0)
2410 return err;
2411
2412 if (probing) {
2413 /* wait for any codec ready status.
2414 * Once it becomes ready it should remain ready
2415 * as long as we do not disable the ac97 link.
2416 */
2417 end_time = jiffies + HZ;
2418 do {
2419 status = igetdword(chip, ICHREG(GLOB_STA)) &
2420 chip->codec_isr_bits;
2421 if (status)
2422 break;
2423 schedule_timeout_uninterruptible(1);
2424 } while (time_after_eq(end_time, jiffies));
2425 if (! status) {
2426 /* no codec is found */
2427 dev_err(chip->card->dev,
2428 "codec_ready: codec is not ready [0x%x]\n",
2429 igetdword(chip, ICHREG(GLOB_STA)));
2430 return -EIO;
2431 }
2432
2433 /* wait for other codecs ready status. */
2434 end_time = jiffies + HZ / 4;
2435 while (status != chip->codec_isr_bits &&
2436 time_after_eq(end_time, jiffies)) {
2437 schedule_timeout_uninterruptible(1);
2438 status |= igetdword(chip, ICHREG(GLOB_STA)) &
2439 chip->codec_isr_bits;
2440 }
2441
2442 } else {
2443 /* resume phase */
2444 int i;
2445 status = 0;
2446 for (i = 0; i < chip->ncodecs; i++)
2447 if (chip->ac97[i])
2448 status |= chip->codec_bit[chip->ac97_sdin[i]];
2449 /* wait until all the probed codecs are ready */
2450 end_time = jiffies + HZ;
2451 do {
2452 nstatus = igetdword(chip, ICHREG(GLOB_STA)) &
2453 chip->codec_isr_bits;
2454 if (status == nstatus)
2455 break;
2456 schedule_timeout_uninterruptible(1);
2457 } while (time_after_eq(end_time, jiffies));
2458 }
2459
2460 if (chip->device_type == DEVICE_SIS) {
2461 /* unmute the output on SIS7012 */
2462 iputword(chip, 0x4c, igetword(chip, 0x4c) | 1);
2463 }
2464 if (chip->device_type == DEVICE_NFORCE && !spdif_aclink) {
2465 /* enable SPDIF interrupt */
2466 unsigned int val;
2467 pci_read_config_dword(chip->pci, 0x4c, &val);
2468 val |= 0x1000000;
2469 pci_write_config_dword(chip->pci, 0x4c, val);
2470 }
2471 return 0;
2472}
2473
2474static int snd_intel8x0_ali_chip_init(struct intel8x0 *chip, int probing)
2475{
2476 u32 reg;
2477 int i = 0;
2478
2479 reg = igetdword(chip, ICHREG(ALI_SCR));
2480 if ((reg & 2) == 0) /* Cold required */
2481 reg |= 2;
2482 else
2483 reg |= 1; /* Warm */
2484 reg &= ~0x80000000; /* ACLink on */
2485 iputdword(chip, ICHREG(ALI_SCR), reg);
2486
2487 for (i = 0; i < HZ / 2; i++) {
2488 if (! (igetdword(chip, ICHREG(ALI_INTERRUPTSR)) & ALI_INT_GPIO))
2489 goto __ok;
2490 schedule_timeout_uninterruptible(1);
2491 }
2492 dev_err(chip->card->dev, "AC'97 reset failed.\n");
2493 if (probing)
2494 return -EIO;
2495
2496 __ok:
2497 for (i = 0; i < HZ / 2; i++) {
2498 reg = igetdword(chip, ICHREG(ALI_RTSR));
2499 if (reg & 0x80) /* primary codec */
2500 break;
2501 iputdword(chip, ICHREG(ALI_RTSR), reg | 0x80);
2502 schedule_timeout_uninterruptible(1);
2503 }
2504
2505 do_ali_reset(chip);
2506 return 0;
2507}
2508
2509static int snd_intel8x0_chip_init(struct intel8x0 *chip, int probing)
2510{
2511 unsigned int i, timeout;
2512 int err;
2513
2514 if (chip->device_type != DEVICE_ALI) {
2515 if ((err = snd_intel8x0_ich_chip_init(chip, probing)) < 0)
2516 return err;
2517 iagetword(chip, 0); /* clear semaphore flag */
2518 } else {
2519 if ((err = snd_intel8x0_ali_chip_init(chip, probing)) < 0)
2520 return err;
2521 }
2522
2523 /* disable interrupts */
2524 for (i = 0; i < chip->bdbars_count; i++)
2525 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, 0x00);
2526 /* reset channels */
2527 for (i = 0; i < chip->bdbars_count; i++)
2528 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, ICH_RESETREGS);
2529 for (i = 0; i < chip->bdbars_count; i++) {
2530 timeout = 100000;
2531 while (--timeout != 0) {
2532 if ((igetbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset) & ICH_RESETREGS) == 0)
2533 break;
2534 }
2535 if (timeout == 0)
2536 dev_err(chip->card->dev, "reset of registers failed?\n");
2537 }
2538 /* initialize Buffer Descriptor Lists */
2539 for (i = 0; i < chip->bdbars_count; i++)
2540 iputdword(chip, ICH_REG_OFF_BDBAR + chip->ichd[i].reg_offset,
2541 chip->ichd[i].bdbar_addr);
2542 return 0;
2543}
2544
2545static int snd_intel8x0_free(struct intel8x0 *chip)
2546{
2547 unsigned int i;
2548
2549 if (chip->irq < 0)
2550 goto __hw_end;
2551 /* disable interrupts */
2552 for (i = 0; i < chip->bdbars_count; i++)
2553 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, 0x00);
2554 /* reset channels */
2555 for (i = 0; i < chip->bdbars_count; i++)
2556 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, ICH_RESETREGS);
2557 if (chip->device_type == DEVICE_NFORCE && !spdif_aclink) {
2558 /* stop the spdif interrupt */
2559 unsigned int val;
2560 pci_read_config_dword(chip->pci, 0x4c, &val);
2561 val &= ~0x1000000;
2562 pci_write_config_dword(chip->pci, 0x4c, val);
2563 }
2564 /* --- */
2565
2566 __hw_end:
2567 if (chip->irq >= 0)
2568 free_irq(chip->irq, chip);
2569 if (chip->bdbars.area)
2570 snd_dma_free_pages(&chip->bdbars);
2571 if (chip->addr)
2572 pci_iounmap(chip->pci, chip->addr);
2573 if (chip->bmaddr)
2574 pci_iounmap(chip->pci, chip->bmaddr);
2575 pci_release_regions(chip->pci);
2576 pci_disable_device(chip->pci);
2577 kfree(chip);
2578 return 0;
2579}
2580
2581#ifdef CONFIG_PM_SLEEP
2582/*
2583 * power management
2584 */
2585static int intel8x0_suspend(struct device *dev)
2586{
2587 struct snd_card *card = dev_get_drvdata(dev);
2588 struct intel8x0 *chip = card->private_data;
2589 int i;
2590
2591 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
2592 for (i = 0; i < chip->ncodecs; i++)
2593 snd_ac97_suspend(chip->ac97[i]);
2594 if (chip->device_type == DEVICE_INTEL_ICH4)
2595 chip->sdm_saved = igetbyte(chip, ICHREG(SDM));
2596
2597 if (chip->irq >= 0) {
2598 free_irq(chip->irq, chip);
2599 chip->irq = -1;
2600 card->sync_irq = -1;
2601 }
2602 return 0;
2603}
2604
2605static int intel8x0_resume(struct device *dev)
2606{
2607 struct pci_dev *pci = to_pci_dev(dev);
2608 struct snd_card *card = dev_get_drvdata(dev);
2609 struct intel8x0 *chip = card->private_data;
2610 int i;
2611
2612 snd_intel8x0_chip_init(chip, 0);
2613 if (request_irq(pci->irq, snd_intel8x0_interrupt,
2614 IRQF_SHARED, KBUILD_MODNAME, chip)) {
2615 dev_err(dev, "unable to grab IRQ %d, disabling device\n",
2616 pci->irq);
2617 snd_card_disconnect(card);
2618 return -EIO;
2619 }
2620 chip->irq = pci->irq;
2621 card->sync_irq = chip->irq;
2622
2623 /* re-initialize mixer stuff */
2624 if (chip->device_type == DEVICE_INTEL_ICH4 && !spdif_aclink) {
2625 /* enable separate SDINs for ICH4 */
2626 iputbyte(chip, ICHREG(SDM), chip->sdm_saved);
2627 /* use slot 10/11 for SPDIF */
2628 iputdword(chip, ICHREG(GLOB_CNT),
2629 (igetdword(chip, ICHREG(GLOB_CNT)) & ~ICH_PCM_SPDIF_MASK) |
2630 ICH_PCM_SPDIF_1011);
2631 }
2632
2633 for (i = 0; i < chip->ncodecs; i++)
2634 snd_ac97_resume(chip->ac97[i]);
2635
2636 /* resume status */
2637 for (i = 0; i < chip->bdbars_count; i++) {
2638 struct ichdev *ichdev = &chip->ichd[i];
2639 unsigned long port = ichdev->reg_offset;
2640 if (! ichdev->substream || ! ichdev->suspended)
2641 continue;
2642 if (ichdev->ichd == ICHD_PCMOUT)
2643 snd_intel8x0_setup_pcm_out(chip, ichdev->substream->runtime);
2644 iputdword(chip, port + ICH_REG_OFF_BDBAR, ichdev->bdbar_addr);
2645 iputbyte(chip, port + ICH_REG_OFF_LVI, ichdev->lvi);
2646 iputbyte(chip, port + ICH_REG_OFF_CIV, ichdev->civ);
2647 iputbyte(chip, port + ichdev->roff_sr, ICH_FIFOE | ICH_BCIS | ICH_LVBCI);
2648 }
2649
2650 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
2651 return 0;
2652}
2653
2654static SIMPLE_DEV_PM_OPS(intel8x0_pm, intel8x0_suspend, intel8x0_resume);
2655#define INTEL8X0_PM_OPS &intel8x0_pm
2656#else
2657#define INTEL8X0_PM_OPS NULL
2658#endif /* CONFIG_PM_SLEEP */
2659
2660#define INTEL8X0_TESTBUF_SIZE 32768 /* enough large for one shot */
2661
2662static void intel8x0_measure_ac97_clock(struct intel8x0 *chip)
2663{
2664 struct snd_pcm_substream *subs;
2665 struct ichdev *ichdev;
2666 unsigned long port;
2667 unsigned long pos, pos1, t;
2668 int civ, timeout = 1000, attempt = 1;
2669#ifndef TARGET_OS2
2670 ktime_t start_time, stop_time;
2671#else
2672 struct timespec start_time, stop_time;
2673#endif
2674
2675 if (chip->ac97_bus->clock != 48000)
2676 return; /* specified in module option */
2677
2678 __again:
2679 subs = chip->pcm[0]->streams[0].substream;
2680 if (! subs || subs->dma_buffer.bytes < INTEL8X0_TESTBUF_SIZE) {
2681 dev_warn(chip->card->dev,
2682 "no playback buffer allocated - aborting measure ac97 clock\n");
2683 return;
2684 }
2685 ichdev = &chip->ichd[ICHD_PCMOUT];
2686 ichdev->physbuf = subs->dma_buffer.addr;
2687 ichdev->size = ichdev->fragsize = INTEL8X0_TESTBUF_SIZE;
2688 ichdev->substream = NULL; /* don't process interrupts */
2689
2690 /* set rate */
2691 if (snd_ac97_set_rate(chip->ac97[0], AC97_PCM_FRONT_DAC_RATE, 48000) < 0) {
2692 dev_err(chip->card->dev, "cannot set ac97 rate: clock = %d\n",
2693 chip->ac97_bus->clock);
2694 return;
2695 }
2696 snd_intel8x0_setup_periods(chip, ichdev);
2697 port = ichdev->reg_offset;
2698 spin_lock_irq(&chip->reg_lock);
2699 chip->in_measurement = 1;
2700 /* trigger */
2701 if (chip->device_type != DEVICE_ALI)
2702 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_IOCE | ICH_STARTBM);
2703 else {
2704 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_IOCE);
2705 iputdword(chip, ICHREG(ALI_DMACR), 1 << ichdev->ali_slot);
2706 }
2707#ifndef TARGET_OS2
2708 start_time = ktime_get();
2709#else
2710 do_posix_clock_monotonic_gettime(&start_time);
2711#endif
2712 spin_unlock_irq(&chip->reg_lock);
2713 msleep(50);
2714 spin_lock_irq(&chip->reg_lock);
2715 /* check the position */
2716 do {
2717 civ = igetbyte(chip, ichdev->reg_offset + ICH_REG_OFF_CIV);
2718 pos1 = igetword(chip, ichdev->reg_offset + ichdev->roff_picb);
2719 if (pos1 == 0) {
2720 udelay(10);
2721 continue;
2722 }
2723 if (civ == igetbyte(chip, ichdev->reg_offset + ICH_REG_OFF_CIV) &&
2724 pos1 == igetword(chip, ichdev->reg_offset + ichdev->roff_picb))
2725 break;
2726 } while (timeout--);
2727 if (pos1 == 0) { /* oops, this value is not reliable */
2728 pos = 0;
2729 } else {
2730 pos = ichdev->fragsize1;
2731 pos -= pos1 << ichdev->pos_shift;
2732 pos += ichdev->position;
2733 }
2734 chip->in_measurement = 0;
2735#ifndef TARGET_OS2
2736 stop_time = ktime_get();
2737#else
2738 do_posix_clock_monotonic_gettime(&stop_time);
2739#endif
2740 /* stop */
2741 if (chip->device_type == DEVICE_ALI) {
2742 iputdword(chip, ICHREG(ALI_DMACR), 1 << (ichdev->ali_slot + 16));
2743 iputbyte(chip, port + ICH_REG_OFF_CR, 0);
2744 while (igetbyte(chip, port + ICH_REG_OFF_CR))
2745 ;
2746 } else {
2747 iputbyte(chip, port + ICH_REG_OFF_CR, 0);
2748 while (!(igetbyte(chip, port + ichdev->roff_sr) & ICH_DCH))
2749 ;
2750 }
2751 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_RESETREGS);
2752 spin_unlock_irq(&chip->reg_lock);
2753
2754 if (pos == 0) {
2755 dev_err(chip->card->dev,
2756 "measure - unreliable DMA position..\n");
2757 __retry:
2758 if (attempt < 3) {
2759 msleep(300);
2760 attempt++;
2761 goto __again;
2762 }
2763 goto __end;
2764 }
2765
2766 pos /= 4;
2767#ifndef TARGET_OS2
2768 t = ktime_us_delta(stop_time, start_time);
2769#else
2770 t = stop_time.tv_sec - start_time.tv_sec;
2771 t *= 1000000;
2772 t += (stop_time.tv_nsec - start_time.tv_nsec) / 1000;
2773 dprintf(("%s: measured %lu usecs (%lu samples)\n", __func__, t, pos));
2774#endif
2775 dev_info(chip->card->dev,
2776 "%s: measured %lu usecs (%lu samples)\n", __func__, t, pos);
2777 if (t == 0) {
2778 dev_err(chip->card->dev, "?? calculation error..\n");
2779 goto __retry;
2780 }
2781 pos *= 1000;
2782 pos = (pos / t) * 1000 + ((pos % t) * 1000) / t;
2783 if (pos < 40000 || pos >= 60000) {
2784 /* abnormal value. hw problem? */
2785 dev_info(chip->card->dev, "measured clock %ld rejected\n", pos);
2786 goto __retry;
2787 } else if (pos > 40500 && pos < 41500)
2788 /* first exception - 41000Hz reference clock */
2789 chip->ac97_bus->clock = 41000;
2790 else if (pos > 43600 && pos < 44600)
2791 /* second exception - 44100HZ reference clock */
2792 chip->ac97_bus->clock = 44100;
2793 else if (pos < 47500 || pos > 48500)
2794 /* not 48000Hz, tuning the clock.. */
2795 chip->ac97_bus->clock = (chip->ac97_bus->clock * 48000) / pos;
2796 __end:
2797 dev_info(chip->card->dev, "clocking to %d\n", chip->ac97_bus->clock);
2798 snd_ac97_update_power(chip->ac97[0], AC97_PCM_FRONT_DAC_RATE, 0);
2799}
2800
2801static const struct snd_pci_quirk intel8x0_clock_list[] = {
2802 SND_PCI_QUIRK(0x0e11, 0x008a, "AD1885", 41000),
2803 SND_PCI_QUIRK(0x1014, 0x0581, "AD1981B", 48000),
2804 SND_PCI_QUIRK(0x1028, 0x00be, "AD1885", 44100),
2805 SND_PCI_QUIRK(0x1028, 0x0177, "AD1980", 48000),
2806 SND_PCI_QUIRK(0x1028, 0x01ad, "AD1981B", 48000),
2807 SND_PCI_QUIRK(0x1043, 0x80f3, "AD1985", 48000),
2808 {0} /* terminator */
2809};
2810
2811static int intel8x0_in_clock_list(struct intel8x0 *chip)
2812{
2813 struct pci_dev *pci = chip->pci;
2814 const struct snd_pci_quirk *wl;
2815
2816 wl = snd_pci_quirk_lookup(pci, intel8x0_clock_list);
2817 if (!wl)
2818 return 0;
2819 dev_info(chip->card->dev, "allow list rate for %04x:%04x is %i\n",
2820 pci->subsystem_vendor, pci->subsystem_device, wl->value);
2821 chip->ac97_bus->clock = wl->value;
2822 return 1;
2823}
2824
2825static void snd_intel8x0_proc_read(struct snd_info_entry * entry,
2826 struct snd_info_buffer *buffer)
2827{
2828 struct intel8x0 *chip = entry->private_data;
2829 unsigned int tmp;
2830
2831 snd_iprintf(buffer, "Intel8x0\n\n");
2832 if (chip->device_type == DEVICE_ALI)
2833 return;
2834 tmp = igetdword(chip, ICHREG(GLOB_STA));
2835 snd_iprintf(buffer, "Global control : 0x%08x\n", igetdword(chip, ICHREG(GLOB_CNT)));
2836 snd_iprintf(buffer, "Global status : 0x%08x\n", tmp);
2837 if (chip->device_type == DEVICE_INTEL_ICH4)
2838 snd_iprintf(buffer, "SDM : 0x%08x\n", igetdword(chip, ICHREG(SDM)));
2839 snd_iprintf(buffer, "AC'97 codecs ready :");
2840 if (tmp & chip->codec_isr_bits) {
2841 int i;
2842 static const char *codecs[3] = {
2843 "primary", "secondary", "tertiary"
2844 };
2845 for (i = 0; i < chip->max_codecs; i++)
2846 if (tmp & chip->codec_bit[i])
2847 snd_iprintf(buffer, " %s", codecs[i]);
2848 } else
2849 snd_iprintf(buffer, " none");
2850 snd_iprintf(buffer, "\n");
2851 if (chip->device_type == DEVICE_INTEL_ICH4 ||
2852 chip->device_type == DEVICE_SIS)
2853 snd_iprintf(buffer, "AC'97 codecs SDIN : %i %i %i\n",
2854 chip->ac97_sdin[0],
2855 chip->ac97_sdin[1],
2856 chip->ac97_sdin[2]);
2857}
2858
2859static void snd_intel8x0_proc_init(struct intel8x0 *chip)
2860{
2861 snd_card_ro_proc_new(chip->card, "intel8x0", chip,
2862 snd_intel8x0_proc_read);
2863}
2864
2865static int snd_intel8x0_dev_free(struct snd_device *device)
2866{
2867 struct intel8x0 *chip = device->device_data;
2868 return snd_intel8x0_free(chip);
2869}
2870
2871struct ich_reg_info {
2872 unsigned int int_sta_mask;
2873 unsigned int offset;
2874};
2875
2876static const unsigned int ich_codec_bits[3] = {
2877 ICH_PCR, ICH_SCR, ICH_TCR
2878};
2879static const unsigned int sis_codec_bits[3] = {
2880 ICH_PCR, ICH_SCR, ICH_SIS_TCR
2881};
2882
2883static int snd_intel8x0_inside_vm(struct pci_dev *pci)
2884{
2885 int result = inside_vm;
2886 char *msg = NULL;
2887
2888 /* check module parameter first (override detection) */
2889 if (result >= 0) {
2890 msg = result ? "enable (forced) VM" : "disable (forced) VM";
2891 goto fini;
2892 }
2893
2894 /* check for known (emulated) devices */
2895 result = 0;
2896 if (pci->subsystem_vendor == PCI_SUBVENDOR_ID_REDHAT_QUMRANET &&
2897 pci->subsystem_device == PCI_SUBDEVICE_ID_QEMU) {
2898 /* KVM emulated sound, PCI SSID: 1af4:1100 */
2899 msg = "enable KVM";
2900 result = 1;
2901 } else if (pci->subsystem_vendor == 0x1ab8) {
2902 /* Parallels VM emulated sound, PCI SSID: 1ab8:xxxx */
2903 msg = "enable Parallels VM";
2904 result = 1;
2905 }
2906
2907fini:
2908 if (msg != NULL)
2909 dev_info(&pci->dev, "%s optimization\n", msg);
2910
2911 return result;
2912}
2913
2914static int snd_intel8x0_create(struct snd_card *card,
2915 struct pci_dev *pci,
2916 unsigned long device_type,
2917 struct intel8x0 **r_intel8x0)
2918{
2919 struct intel8x0 *chip;
2920 int err;
2921 unsigned int i;
2922 unsigned int int_sta_masks;
2923 struct ichdev *ichdev;
2924 static const struct snd_device_ops ops = {
2925 .dev_free = snd_intel8x0_dev_free,
2926 };
2927
2928 static const unsigned int bdbars[] = {
2929 3, /* DEVICE_INTEL */
2930 6, /* DEVICE_INTEL_ICH4 */
2931 3, /* DEVICE_SIS */
2932 6, /* DEVICE_ALI */
2933 4, /* DEVICE_NFORCE */
2934 };
2935 static const struct ich_reg_info intel_regs[6] = {
2936 { ICH_PIINT, 0 },
2937 { ICH_POINT, 0x10 },
2938 { ICH_MCINT, 0x20 },
2939 { ICH_M2INT, 0x40 },
2940 { ICH_P2INT, 0x50 },
2941 { ICH_SPINT, 0x60 },
2942 };
2943 static const struct ich_reg_info nforce_regs[4] = {
2944 { ICH_PIINT, 0 },
2945 { ICH_POINT, 0x10 },
2946 { ICH_MCINT, 0x20 },
2947 { ICH_NVSPINT, 0x70 },
2948 };
2949 static const struct ich_reg_info ali_regs[6] = {
2950 { ALI_INT_PCMIN, 0x40 },
2951 { ALI_INT_PCMOUT, 0x50 },
2952 { ALI_INT_MICIN, 0x60 },
2953 { ALI_INT_CODECSPDIFOUT, 0x70 },
2954 { ALI_INT_SPDIFIN, 0xa0 },
2955 { ALI_INT_SPDIFOUT, 0xb0 },
2956 };
2957 const struct ich_reg_info *tbl;
2958
2959 *r_intel8x0 = NULL;
2960
2961 if ((err = pci_enable_device(pci)) < 0)
2962 return err;
2963
2964 chip = kzalloc(sizeof(*chip), GFP_KERNEL);
2965 if (chip == NULL) {
2966 pci_disable_device(pci);
2967 return -ENOMEM;
2968 }
2969 spin_lock_init(&chip->reg_lock);
2970 chip->device_type = device_type;
2971 chip->card = card;
2972 chip->pci = pci;
2973 chip->irq = -1;
2974
2975 /* module parameters */
2976 chip->buggy_irq = buggy_irq;
2977 chip->buggy_semaphore = buggy_semaphore;
2978 if (xbox)
2979 chip->xbox = 1;
2980
2981 chip->inside_vm = snd_intel8x0_inside_vm(pci);
2982
2983 /*
2984 * Intel 82443MX running a 100MHz processor system bus has a hardware
2985 * bug, which aborts PCI busmaster for audio transfer. A workaround
2986 * is to set the pages as non-cached. For details, see the errata in
2987 * http://download.intel.com/design/chipsets/specupdt/24505108.pdf
2988 */
2989 if (pci->vendor == PCI_VENDOR_ID_INTEL &&
2990 pci->device == PCI_DEVICE_ID_INTEL_440MX)
2991 chip->fix_nocache = 1; /* enable workaround */
2992
2993 if ((err = pci_request_regions(pci, card->shortname)) < 0) {
2994 kfree(chip);
2995 pci_disable_device(pci);
2996 return err;
2997 }
2998
2999 if (device_type == DEVICE_ALI) {
3000 /* ALI5455 has no ac97 region */
3001 chip->bmaddr = pci_iomap(pci, 0, 0);
3002 goto port_inited;
3003 }
3004
3005 if (pci_resource_flags(pci, 2) & IORESOURCE_MEM) /* ICH4 and Nforce */
3006 chip->addr = pci_iomap(pci, 2, 0);
3007 else
3008 chip->addr = pci_iomap(pci, 0, 0);
3009 if (!chip->addr) {
3010 dev_err(card->dev, "AC'97 space ioremap problem\n");
3011 snd_intel8x0_free(chip);
3012 return -EIO;
3013 }
3014 if (pci_resource_flags(pci, 3) & IORESOURCE_MEM) /* ICH4 */
3015 chip->bmaddr = pci_iomap(pci, 3, 0);
3016 else
3017 chip->bmaddr = pci_iomap(pci, 1, 0);
3018
3019 port_inited:
3020 if (!chip->bmaddr) {
3021 dev_err(card->dev, "Controller space ioremap problem\n");
3022 snd_intel8x0_free(chip);
3023 return -EIO;
3024 }
3025 chip->bdbars_count = bdbars[device_type];
3026
3027 /* initialize offsets */
3028 switch (device_type) {
3029 case DEVICE_NFORCE:
3030 tbl = nforce_regs;
3031 break;
3032 case DEVICE_ALI:
3033 tbl = ali_regs;
3034 break;
3035 default:
3036 tbl = intel_regs;
3037 break;
3038 }
3039 for (i = 0; i < chip->bdbars_count; i++) {
3040 ichdev = &chip->ichd[i];
3041 ichdev->ichd = i;
3042 ichdev->reg_offset = tbl[i].offset;
3043 ichdev->int_sta_mask = tbl[i].int_sta_mask;
3044 if (device_type == DEVICE_SIS) {
3045 /* SiS 7012 swaps the registers */
3046 ichdev->roff_sr = ICH_REG_OFF_PICB;
3047 ichdev->roff_picb = ICH_REG_OFF_SR;
3048 } else {
3049 ichdev->roff_sr = ICH_REG_OFF_SR;
3050 ichdev->roff_picb = ICH_REG_OFF_PICB;
3051 }
3052 if (device_type == DEVICE_ALI)
3053 ichdev->ali_slot = (ichdev->reg_offset - 0x40) / 0x10;
3054 /* SIS7012 handles the pcm data in bytes, others are in samples */
3055 ichdev->pos_shift = (device_type == DEVICE_SIS) ? 0 : 1;
3056 }
3057
3058 /* allocate buffer descriptor lists */
3059 /* the start of each lists must be aligned to 8 bytes */
3060 if (snd_dma_alloc_pages(intel8x0_dma_type(chip), &pci->dev,
3061 chip->bdbars_count * sizeof(u32) * ICH_MAX_FRAGS * 2,
3062 &chip->bdbars) < 0) {
3063 snd_intel8x0_free(chip);
3064 dev_err(card->dev, "cannot allocate buffer descriptors\n");
3065 return -ENOMEM;
3066 }
3067 /* tables must be aligned to 8 bytes here, but the kernel pages
3068 are much bigger, so we don't care (on i386) */
3069 int_sta_masks = 0;
3070 for (i = 0; i < chip->bdbars_count; i++) {
3071 ichdev = &chip->ichd[i];
3072 ichdev->bdbar = ((__le32 *)chip->bdbars.area) +
3073 (i * ICH_MAX_FRAGS * 2);
3074 ichdev->bdbar_addr = chip->bdbars.addr +
3075 (i * sizeof(u32) * ICH_MAX_FRAGS * 2);
3076 int_sta_masks |= ichdev->int_sta_mask;
3077 }
3078 chip->int_sta_reg = device_type == DEVICE_ALI ?
3079 ICH_REG_ALI_INTERRUPTSR : ICH_REG_GLOB_STA;
3080 chip->int_sta_mask = int_sta_masks;
3081
3082 pci_set_master(pci);
3083
3084 switch(chip->device_type) {
3085 case DEVICE_INTEL_ICH4:
3086 /* ICH4 can have three codecs */
3087 chip->max_codecs = 3;
3088 chip->codec_bit = ich_codec_bits;
3089 chip->codec_ready_bits = ICH_PRI | ICH_SRI | ICH_TRI;
3090 break;
3091 case DEVICE_SIS:
3092 /* recent SIS7012 can have three codecs */
3093 chip->max_codecs = 3;
3094 chip->codec_bit = sis_codec_bits;
3095 chip->codec_ready_bits = ICH_PRI | ICH_SRI | ICH_SIS_TRI;
3096 break;
3097 default:
3098 /* others up to two codecs */
3099 chip->max_codecs = 2;
3100 chip->codec_bit = ich_codec_bits;
3101 chip->codec_ready_bits = ICH_PRI | ICH_SRI;
3102 break;
3103 }
3104 for (i = 0; i < chip->max_codecs; i++)
3105 chip->codec_isr_bits |= chip->codec_bit[i];
3106
3107 if ((err = snd_intel8x0_chip_init(chip, 1)) < 0) {
3108 snd_intel8x0_free(chip);
3109 return err;
3110 }
3111
3112 /* request irq after initializaing int_sta_mask, etc */
3113 if (request_irq(pci->irq, snd_intel8x0_interrupt,
3114 IRQF_SHARED, KBUILD_MODNAME, chip)) {
3115 dev_err(card->dev, "unable to grab IRQ %d\n", pci->irq);
3116 snd_intel8x0_free(chip);
3117 return -EBUSY;
3118 }
3119 chip->irq = pci->irq;
3120 card->sync_irq = chip->irq;
3121
3122 if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) < 0) {
3123 snd_intel8x0_free(chip);
3124 return err;
3125 }
3126
3127 *r_intel8x0 = chip;
3128 return 0;
3129}
3130
3131static struct shortname_table {
3132 unsigned int id;
3133 const char *s;
3134} shortnames[] = {
3135 { PCI_DEVICE_ID_INTEL_82801AA_5, "Intel 82801AA-ICH" },
3136 { PCI_DEVICE_ID_INTEL_82801AB_5, "Intel 82901AB-ICH0" },
3137 { PCI_DEVICE_ID_INTEL_82801BA_4, "Intel 82801BA-ICH2" },
3138 { PCI_DEVICE_ID_INTEL_440MX, "Intel 440MX" },
3139 { PCI_DEVICE_ID_INTEL_82801CA_5, "Intel 82801CA-ICH3" },
3140 { PCI_DEVICE_ID_INTEL_82801DB_5, "Intel 82801DB-ICH4" },
3141 { PCI_DEVICE_ID_INTEL_82801EB_5, "Intel ICH5" },
3142 { PCI_DEVICE_ID_INTEL_ESB_5, "Intel 6300ESB" },
3143 { PCI_DEVICE_ID_INTEL_ICH6_18, "Intel ICH6" },
3144 { PCI_DEVICE_ID_INTEL_ICH7_20, "Intel ICH7" },
3145 { PCI_DEVICE_ID_INTEL_ESB2_14, "Intel ESB2" },
3146 { PCI_DEVICE_ID_SI_7012, "SiS SI7012" },
3147 { PCI_DEVICE_ID_NVIDIA_MCP1_AUDIO, "NVidia nForce" },
3148 { PCI_DEVICE_ID_NVIDIA_MCP2_AUDIO, "NVidia nForce2" },
3149 { PCI_DEVICE_ID_NVIDIA_MCP3_AUDIO, "NVidia nForce3" },
3150 { PCI_DEVICE_ID_NVIDIA_CK8S_AUDIO, "NVidia CK8S" },
3151 { PCI_DEVICE_ID_NVIDIA_CK804_AUDIO, "NVidia CK804" },
3152 { PCI_DEVICE_ID_NVIDIA_CK8_AUDIO, "NVidia CK8" },
3153 { 0x003a, "NVidia MCP04" },
3154 { 0x746d, "AMD AMD8111" },
3155 { 0x7445, "AMD AMD768" },
3156 { 0x5455, "ALi M5455" },
3157 { 0, NULL },
3158};
3159
3160static const struct snd_pci_quirk spdif_aclink_defaults[] = {
3161 SND_PCI_QUIRK(0x147b, 0x1c1a, "ASUS KN8", 1),
3162 {0} /* end */
3163};
3164
3165/* look up allow/deny list for SPDIF over ac-link */
3166static int check_default_spdif_aclink(struct pci_dev *pci)
3167{
3168 const struct snd_pci_quirk *w;
3169
3170 w = snd_pci_quirk_lookup(pci, spdif_aclink_defaults);
3171 if (w) {
3172 if (w->value)
3173 dev_dbg(&pci->dev,
3174 "Using SPDIF over AC-Link for %s\n",
3175 snd_pci_quirk_name(w));
3176 else
3177 dev_dbg(&pci->dev,
3178 "Using integrated SPDIF DMA for %s\n",
3179 snd_pci_quirk_name(w));
3180 return w->value;
3181 }
3182 return 0;
3183}
3184
3185static int snd_intel8x0_probe(struct pci_dev *pci,
3186 const struct pci_device_id *pci_id)
3187{
3188 struct snd_card *card;
3189 struct intel8x0 *chip;
3190 int err;
3191 struct shortname_table *name;
3192
3193 err = snd_card_new(&pci->dev, index, id, THIS_MODULE, 0, &card);
3194 if (err < 0)
3195 return err;
3196
3197 if (spdif_aclink < 0)
3198 spdif_aclink = check_default_spdif_aclink(pci);
3199
3200 strcpy(card->driver, "ICH");
3201 if (!spdif_aclink) {
3202 switch (pci_id->driver_data) {
3203 case DEVICE_NFORCE:
3204 strcpy(card->driver, "NFORCE");
3205 break;
3206 case DEVICE_INTEL_ICH4:
3207 strcpy(card->driver, "ICH4");
3208 }
3209 }
3210
3211 strcpy(card->shortname, "Intel ICH");
3212 for (name = shortnames; name->id; name++) {
3213 if (pci->device == name->id) {
3214 strcpy(card->shortname, name->s);
3215 break;
3216 }
3217 }
3218
3219 if (buggy_irq < 0) {
3220 /* some Nforce[2] and ICH boards have problems with IRQ handling.
3221 * Needs to return IRQ_HANDLED for unknown irqs.
3222 */
3223 if (pci_id->driver_data == DEVICE_NFORCE)
3224 buggy_irq = 1;
3225 else
3226 buggy_irq = 0;
3227 }
3228
3229 if ((err = snd_intel8x0_create(card, pci, pci_id->driver_data,
3230 &chip)) < 0) {
3231 snd_card_free(card);
3232 return err;
3233 }
3234 card->private_data = chip;
3235
3236 if ((err = snd_intel8x0_mixer(chip, ac97_clock, ac97_quirk)) < 0) {
3237 snd_card_free(card);
3238 return err;
3239 }
3240 if ((err = snd_intel8x0_pcm(chip)) < 0) {
3241 snd_card_free(card);
3242 return err;
3243 }
3244
3245 snd_intel8x0_proc_init(chip);
3246
3247 snprintf(card->longname, sizeof(card->longname),
3248 "%s with %s at irq %i", card->shortname,
3249 snd_ac97_get_short_name(chip->ac97[0]), chip->irq);
3250
3251 if (ac97_clock == 0 || ac97_clock == 1) {
3252 if (ac97_clock == 0) {
3253 if (intel8x0_in_clock_list(chip) == 0)
3254 intel8x0_measure_ac97_clock(chip);
3255 } else {
3256 intel8x0_measure_ac97_clock(chip);
3257 }
3258 }
3259
3260 if ((err = snd_card_register(card)) < 0) {
3261 snd_card_free(card);
3262 return err;
3263 }
3264 pci_set_drvdata(pci, card);
3265 return 0;
3266}
3267
3268static void snd_intel8x0_remove(struct pci_dev *pci)
3269{
3270 snd_card_free(pci_get_drvdata(pci));
3271}
3272
3273static struct pci_driver intel8x0_driver = {
3274 .name = KBUILD_MODNAME,
3275 .id_table = snd_intel8x0_ids,
3276 .probe = snd_intel8x0_probe,
3277 .remove = snd_intel8x0_remove,
3278 .driver = {
3279 .pm = INTEL8X0_PM_OPS,
3280 },
3281};
3282
3283module_pci_driver(intel8x0_driver);
Note: See TracBrowser for help on using the repository browser.