source: GPL/trunk/alsa-kernel/pci/ens1370.c@ 703

Last change on this file since 703 was 703, checked in by David Azarewicz, 4 years ago

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1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Driver for Ensoniq ES1370/ES1371 AudioPCI soundcard
4 * Copyright (c) by Jaroslav Kysela <perex@perex.cz>,
5 * Thomas Sailer <sailer@ife.ee.ethz.ch>
6 */
7
8/* Power-Management-Code ( CONFIG_PM )
9 * for ens1371 only ( FIXME )
10 * derived from cs4281.c, atiixp.c and via82xx.c
11 * using http://www.alsa-project.org/~tiwai/writing-an-alsa-driver/
12 * by Kurt J. Bosch
13 */
14
15#include <linux/io.h>
16#include <linux/delay.h>
17#include <linux/interrupt.h>
18#include <linux/init.h>
19#include <linux/pci.h>
20#include <linux/slab.h>
21#include <linux/gameport.h>
22#include <linux/module.h>
23#include <linux/mutex.h>
24
25#include <sound/core.h>
26#include <sound/control.h>
27#include <sound/pcm.h>
28#include <sound/rawmidi.h>
29#ifdef CHIP1371
30#include <sound/ac97_codec.h>
31#else
32#include <sound/ak4531_codec.h>
33#endif
34#include <sound/initval.h>
35#include <sound/asoundef.h>
36
37#ifndef CHIP1371
38#undef CHIP1370
39#define CHIP1370
40#endif
41
42#ifdef CHIP1370
43#define DRIVER_NAME "ENS1370"
44#define CHIP_NAME "ES1370" /* it can be ENS but just to keep compatibility... */
45#else
46#define DRIVER_NAME "ENS1371"
47#define CHIP_NAME "ES1371"
48#endif
49
50
51#ifdef TARGET_OS2
52#define KBUILD_MODNAME "ens137x"
53#endif
54MODULE_AUTHOR("Jaroslav Kysela <perex@perex.cz>, Thomas Sailer <sailer@ife.ee.ethz.ch>");
55MODULE_LICENSE("GPL");
56#ifdef CHIP1370
57MODULE_DESCRIPTION("Ensoniq AudioPCI ES1370");
58#endif
59#ifdef CHIP1371
60MODULE_DESCRIPTION("Ensoniq/Creative AudioPCI ES1371+");
61#endif
62
63#if IS_REACHABLE(CONFIG_GAMEPORT)
64#define SUPPORT_JOYSTICK
65#endif
66
67static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
68static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
69static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable switches */
70#ifdef SUPPORT_JOYSTICK
71#ifdef CHIP1371
72static int joystick_port[SNDRV_CARDS];
73#else
74static bool joystick[SNDRV_CARDS];
75#endif
76#endif
77#ifdef CHIP1371
78static int spdif[SNDRV_CARDS];
79static int lineio[SNDRV_CARDS];
80#endif
81
82module_param_array(index, int, NULL, 0444);
83MODULE_PARM_DESC(index, "Index value for Ensoniq AudioPCI soundcard.");
84module_param_array(id, charp, NULL, 0444);
85MODULE_PARM_DESC(id, "ID string for Ensoniq AudioPCI soundcard.");
86module_param_array(enable, bool, NULL, 0444);
87MODULE_PARM_DESC(enable, "Enable Ensoniq AudioPCI soundcard.");
88#ifdef SUPPORT_JOYSTICK
89#ifdef CHIP1371
90module_param_hw_array(joystick_port, int, ioport, NULL, 0444);
91MODULE_PARM_DESC(joystick_port, "Joystick port address.");
92#else
93module_param_array(joystick, bool, NULL, 0444);
94MODULE_PARM_DESC(joystick, "Enable joystick.");
95#endif
96#endif /* SUPPORT_JOYSTICK */
97#ifdef CHIP1371
98module_param_array(spdif, int, NULL, 0444);
99MODULE_PARM_DESC(spdif, "S/PDIF output (-1 = none, 0 = auto, 1 = force).");
100module_param_array(lineio, int, NULL, 0444);
101MODULE_PARM_DESC(lineio, "Line In to Rear Out (0 = auto, 1 = force).");
102#endif
103
104/* ES1371 chip ID */
105/* This is a little confusing because all ES1371 compatible chips have the
106 same DEVICE_ID, the only thing differentiating them is the REV_ID field.
107 This is only significant if you want to enable features on the later parts.
108 Yes, I know it's stupid and why didn't we use the sub IDs?
109*/
110#define ES1371REV_ES1373_A 0x04
111#define ES1371REV_ES1373_B 0x06
112#define ES1371REV_CT5880_A 0x07
113#define CT5880REV_CT5880_C 0x02
114#define CT5880REV_CT5880_D 0x03 /* ??? -jk */
115#define CT5880REV_CT5880_E 0x04 /* mw */
116#define ES1371REV_ES1371_B 0x09
117#define EV1938REV_EV1938_A 0x00
118#define ES1371REV_ES1373_8 0x08
119
120/*
121 * Direct registers
122 */
123
124#define ES_REG(ensoniq, x) ((ensoniq)->port + ES_REG_##x)
125
126#define ES_REG_CONTROL 0x00 /* R/W: Interrupt/Chip select control register */
127#define ES_1370_ADC_STOP (1<<31) /* disable capture buffer transfers */
128#define ES_1370_XCTL1 (1<<30) /* general purpose output bit */
129#define ES_1373_BYPASS_P1 (1<<31) /* bypass SRC for PB1 */
130#define ES_1373_BYPASS_P2 (1<<30) /* bypass SRC for PB2 */
131#define ES_1373_BYPASS_R (1<<29) /* bypass SRC for REC */
132#define ES_1373_TEST_BIT (1<<28) /* should be set to 0 for normal operation */
133#define ES_1373_RECEN_B (1<<27) /* mix record with playback for I2S/SPDIF out */
134#define ES_1373_SPDIF_THRU (1<<26) /* 0 = SPDIF thru mode, 1 = SPDIF == dig out */
135#define ES_1371_JOY_ASEL(o) (((o)&0x03)<<24)/* joystick port mapping */
136#define ES_1371_JOY_ASELM (0x03<<24) /* mask for above */
137#define ES_1371_JOY_ASELI(i) (((i)>>24)&0x03)
138#define ES_1371_GPIO_IN(i) (((i)>>20)&0x0f)/* GPIO in [3:0] pins - R/O */
139#define ES_1370_PCLKDIVO(o) (((o)&0x1fff)<<16)/* clock divide ratio for DAC2 */
140#define ES_1370_PCLKDIVM ((0x1fff)<<16) /* mask for above */
141#define ES_1370_PCLKDIVI(i) (((i)>>16)&0x1fff)/* clock divide ratio for DAC2 */
142#define ES_1371_GPIO_OUT(o) (((o)&0x0f)<<16)/* GPIO out [3:0] pins - W/R */
143#define ES_1371_GPIO_OUTM (0x0f<<16) /* mask for above */
144#define ES_MSFMTSEL (1<<15) /* MPEG serial data format; 0 = SONY, 1 = I2S */
145#define ES_1370_M_SBB (1<<14) /* clock source for DAC - 0 = clock generator; 1 = MPEG clocks */
146#define ES_1371_SYNC_RES (1<<14) /* Warm AC97 reset */
147#define ES_1370_WTSRSEL(o) (((o)&0x03)<<12)/* fixed frequency clock for DAC1 */
148#define ES_1370_WTSRSELM (0x03<<12) /* mask for above */
149#define ES_1371_ADC_STOP (1<<13) /* disable CCB transfer capture information */
150#define ES_1371_PWR_INTRM (1<<12) /* power level change interrupts enable */
151#define ES_1370_DAC_SYNC (1<<11) /* DAC's are synchronous */
152#define ES_1371_M_CB (1<<11) /* capture clock source; 0 = AC'97 ADC; 1 = I2S */
153#define ES_CCB_INTRM (1<<10) /* CCB voice interrupts enable */
154#define ES_1370_M_CB (1<<9) /* capture clock source; 0 = ADC; 1 = MPEG */
155#define ES_1370_XCTL0 (1<<8) /* generap purpose output bit */
156#define ES_1371_PDLEV(o) (((o)&0x03)<<8) /* current power down level */
157#define ES_1371_PDLEVM (0x03<<8) /* mask for above */
158#define ES_BREQ (1<<7) /* memory bus request enable */
159#define ES_DAC1_EN (1<<6) /* DAC1 playback channel enable */
160#define ES_DAC2_EN (1<<5) /* DAC2 playback channel enable */
161#define ES_ADC_EN (1<<4) /* ADC capture channel enable */
162#define ES_UART_EN (1<<3) /* UART enable */
163#define ES_JYSTK_EN (1<<2) /* Joystick module enable */
164#define ES_1370_CDC_EN (1<<1) /* Codec interface enable */
165#define ES_1371_XTALCKDIS (1<<1) /* Xtal clock disable */
166#define ES_1370_SERR_DISABLE (1<<0) /* PCI serr signal disable */
167#define ES_1371_PCICLKDIS (1<<0) /* PCI clock disable */
168#define ES_REG_STATUS 0x04 /* R/O: Interrupt/Chip select status register */
169#define ES_INTR (1<<31) /* Interrupt is pending */
170#define ES_1371_ST_AC97_RST (1<<29) /* CT5880 AC'97 Reset bit */
171#define ES_1373_REAR_BIT27 (1<<27) /* rear bits: 000 - front, 010 - mirror, 101 - separate */
172#define ES_1373_REAR_BIT26 (1<<26)
173#define ES_1373_REAR_BIT24 (1<<24)
174#define ES_1373_GPIO_INT_EN(o)(((o)&0x0f)<<20)/* GPIO [3:0] pins - interrupt enable */
175#define ES_1373_SPDIF_EN (1<<18) /* SPDIF enable */
176#define ES_1373_SPDIF_TEST (1<<17) /* SPDIF test */
177#define ES_1371_TEST (1<<16) /* test ASIC */
178#define ES_1373_GPIO_INT(i) (((i)&0x0f)>>12)/* GPIO [3:0] pins - interrupt pending */
179#define ES_1370_CSTAT (1<<10) /* CODEC is busy or register write in progress */
180#define ES_1370_CBUSY (1<<9) /* CODEC is busy */
181#define ES_1370_CWRIP (1<<8) /* CODEC register write in progress */
182#define ES_1371_SYNC_ERR (1<<8) /* CODEC synchronization error occurred */
183#define ES_1371_VC(i) (((i)>>6)&0x03) /* voice code from CCB module */
184#define ES_1370_VC(i) (((i)>>5)&0x03) /* voice code from CCB module */
185#define ES_1371_MPWR (1<<5) /* power level interrupt pending */
186#define ES_MCCB (1<<4) /* CCB interrupt pending */
187#define ES_UART (1<<3) /* UART interrupt pending */
188#define ES_DAC1 (1<<2) /* DAC1 channel interrupt pending */
189#define ES_DAC2 (1<<1) /* DAC2 channel interrupt pending */
190#define ES_ADC (1<<0) /* ADC channel interrupt pending */
191#define ES_REG_UART_DATA 0x08 /* R/W: UART data register */
192#define ES_REG_UART_STATUS 0x09 /* R/O: UART status register */
193#define ES_RXINT (1<<7) /* RX interrupt occurred */
194#define ES_TXINT (1<<2) /* TX interrupt occurred */
195#define ES_TXRDY (1<<1) /* transmitter ready */
196#define ES_RXRDY (1<<0) /* receiver ready */
197#define ES_REG_UART_CONTROL 0x09 /* W/O: UART control register */
198#define ES_RXINTEN (1<<7) /* RX interrupt enable */
199#define ES_TXINTENO(o) (((o)&0x03)<<5) /* TX interrupt enable */
200#define ES_TXINTENM (0x03<<5) /* mask for above */
201#define ES_TXINTENI(i) (((i)>>5)&0x03)
202#define ES_CNTRL(o) (((o)&0x03)<<0) /* control */
203#define ES_CNTRLM (0x03<<0) /* mask for above */
204#define ES_REG_UART_RES 0x0a /* R/W: UART reserver register */
205#define ES_TEST_MODE (1<<0) /* test mode enabled */
206#define ES_REG_MEM_PAGE 0x0c /* R/W: Memory page register */
207#define ES_MEM_PAGEO(o) (((o)&0x0f)<<0) /* memory page select - out */
208#define ES_MEM_PAGEM (0x0f<<0) /* mask for above */
209#define ES_MEM_PAGEI(i) (((i)>>0)&0x0f) /* memory page select - in */
210#define ES_REG_1370_CODEC 0x10 /* W/O: Codec write register address */
211#define ES_1370_CODEC_WRITE(a,d) ((((a)&0xff)<<8)|(((d)&0xff)<<0))
212#define ES_REG_1371_CODEC 0x14 /* W/R: Codec Read/Write register address */
213#define ES_1371_CODEC_RDY (1<<31) /* codec ready */
214#define ES_1371_CODEC_WIP (1<<30) /* codec register access in progress */
215#define EV_1938_CODEC_MAGIC (1<<26)
216#define ES_1371_CODEC_PIRD (1<<23) /* codec read/write select register */
217#define ES_1371_CODEC_WRITE(a,d) ((((a)&0x7f)<<16)|(((d)&0xffff)<<0))
218#define ES_1371_CODEC_READS(a) ((((a)&0x7f)<<16)|ES_1371_CODEC_PIRD)
219#define ES_1371_CODEC_READ(i) (((i)>>0)&0xffff)
220
221#define ES_REG_1371_SMPRATE 0x10 /* W/R: Codec rate converter interface register */
222#define ES_1371_SRC_RAM_ADDRO(o) (((o)&0x7f)<<25)/* address of the sample rate converter */
223#define ES_1371_SRC_RAM_ADDRM (0x7f<<25) /* mask for above */
224#define ES_1371_SRC_RAM_ADDRI(i) (((i)>>25)&0x7f)/* address of the sample rate converter */
225#define ES_1371_SRC_RAM_WE (1<<24) /* R/W: read/write control for sample rate converter */
226#define ES_1371_SRC_RAM_BUSY (1<<23) /* R/O: sample rate memory is busy */
227#define ES_1371_SRC_DISABLE (1<<22) /* sample rate converter disable */
228#define ES_1371_DIS_P1 (1<<21) /* playback channel 1 accumulator update disable */
229#define ES_1371_DIS_P2 (1<<20) /* playback channel 1 accumulator update disable */
230#define ES_1371_DIS_R1 (1<<19) /* capture channel accumulator update disable */
231#define ES_1371_SRC_RAM_DATAO(o) (((o)&0xffff)<<0)/* current value of the sample rate converter */
232#define ES_1371_SRC_RAM_DATAM (0xffff<<0) /* mask for above */
233#define ES_1371_SRC_RAM_DATAI(i) (((i)>>0)&0xffff)/* current value of the sample rate converter */
234
235#define ES_REG_1371_LEGACY 0x18 /* W/R: Legacy control/status register */
236#define ES_1371_JFAST (1<<31) /* fast joystick timing */
237#define ES_1371_HIB (1<<30) /* host interrupt blocking enable */
238#define ES_1371_VSB (1<<29) /* SB; 0 = addr 0x220xH, 1 = 0x22FxH */
239#define ES_1371_VMPUO(o) (((o)&0x03)<<27)/* base register address; 0 = 0x320xH; 1 = 0x330xH; 2 = 0x340xH; 3 = 0x350xH */
240#define ES_1371_VMPUM (0x03<<27) /* mask for above */
241#define ES_1371_VMPUI(i) (((i)>>27)&0x03)/* base register address */
242#define ES_1371_VCDCO(o) (((o)&0x03)<<25)/* CODEC; 0 = 0x530xH; 1 = undefined; 2 = 0xe80xH; 3 = 0xF40xH */
243#define ES_1371_VCDCM (0x03<<25) /* mask for above */
244#define ES_1371_VCDCI(i) (((i)>>25)&0x03)/* CODEC address */
245#define ES_1371_FIRQ (1<<24) /* force an interrupt */
246#define ES_1371_SDMACAP (1<<23) /* enable event capture for slave DMA controller */
247#define ES_1371_SPICAP (1<<22) /* enable event capture for slave IRQ controller */
248#define ES_1371_MDMACAP (1<<21) /* enable event capture for master DMA controller */
249#define ES_1371_MPICAP (1<<20) /* enable event capture for master IRQ controller */
250#define ES_1371_ADCAP (1<<19) /* enable event capture for ADLIB register; 0x388xH */
251#define ES_1371_SVCAP (1<<18) /* enable event capture for SB registers */
252#define ES_1371_CDCCAP (1<<17) /* enable event capture for CODEC registers */
253#define ES_1371_BACAP (1<<16) /* enable event capture for SoundScape base address */
254#define ES_1371_EXI(i) (((i)>>8)&0x07) /* event number */
255#define ES_1371_AI(i) (((i)>>3)&0x1f) /* event significant I/O address */
256#define ES_1371_WR (1<<2) /* event capture; 0 = read; 1 = write */
257#define ES_1371_LEGINT (1<<0) /* interrupt for legacy events; 0 = interrupt did occur */
258
259#define ES_REG_CHANNEL_STATUS 0x1c /* R/W: first 32-bits from S/PDIF channel status block, es1373 */
260
261#define ES_REG_SERIAL 0x20 /* R/W: Serial interface control register */
262#define ES_1371_DAC_TEST (1<<22) /* DAC test mode enable */
263#define ES_P2_END_INCO(o) (((o)&0x07)<<19)/* binary offset value to increment / loop end */
264#define ES_P2_END_INCM (0x07<<19) /* mask for above */
265#define ES_P2_END_INCI(i) (((i)>>16)&0x07)/* binary offset value to increment / loop end */
266#define ES_P2_ST_INCO(o) (((o)&0x07)<<16)/* binary offset value to increment / start */
267#define ES_P2_ST_INCM (0x07<<16) /* mask for above */
268#define ES_P2_ST_INCI(i) (((i)<<16)&0x07)/* binary offset value to increment / start */
269#define ES_R1_LOOP_SEL (1<<15) /* ADC; 0 - loop mode; 1 = stop mode */
270#define ES_P2_LOOP_SEL (1<<14) /* DAC2; 0 - loop mode; 1 = stop mode */
271#define ES_P1_LOOP_SEL (1<<13) /* DAC1; 0 - loop mode; 1 = stop mode */
272#define ES_P2_PAUSE (1<<12) /* DAC2; 0 - play mode; 1 = pause mode */
273#define ES_P1_PAUSE (1<<11) /* DAC1; 0 - play mode; 1 = pause mode */
274#define ES_R1_INT_EN (1<<10) /* ADC interrupt enable */
275#define ES_P2_INT_EN (1<<9) /* DAC2 interrupt enable */
276#define ES_P1_INT_EN (1<<8) /* DAC1 interrupt enable */
277#define ES_P1_SCT_RLD (1<<7) /* force sample counter reload for DAC1 */
278#define ES_P2_DAC_SEN (1<<6) /* when stop mode: 0 - DAC2 play back zeros; 1 = DAC2 play back last sample */
279#define ES_R1_MODEO(o) (((o)&0x03)<<4) /* ADC mode; 0 = 8-bit mono; 1 = 8-bit stereo; 2 = 16-bit mono; 3 = 16-bit stereo */
280#define ES_R1_MODEM (0x03<<4) /* mask for above */
281#define ES_R1_MODEI(i) (((i)>>4)&0x03)
282#define ES_P2_MODEO(o) (((o)&0x03)<<2) /* DAC2 mode; -- '' -- */
283#define ES_P2_MODEM (0x03<<2) /* mask for above */
284#define ES_P2_MODEI(i) (((i)>>2)&0x03)
285#define ES_P1_MODEO(o) (((o)&0x03)<<0) /* DAC1 mode; -- '' -- */
286#define ES_P1_MODEM (0x03<<0) /* mask for above */
287#define ES_P1_MODEI(i) (((i)>>0)&0x03)
288
289#define ES_REG_DAC1_COUNT 0x24 /* R/W: DAC1 sample count register */
290#define ES_REG_DAC2_COUNT 0x28 /* R/W: DAC2 sample count register */
291#define ES_REG_ADC_COUNT 0x2c /* R/W: ADC sample count register */
292#define ES_REG_CURR_COUNT(i) (((i)>>16)&0xffff)
293#define ES_REG_COUNTO(o) (((o)&0xffff)<<0)
294#define ES_REG_COUNTM (0xffff<<0)
295#define ES_REG_COUNTI(i) (((i)>>0)&0xffff)
296
297#define ES_REG_DAC1_FRAME 0x30 /* R/W: PAGE 0x0c; DAC1 frame address */
298#define ES_REG_DAC1_SIZE 0x34 /* R/W: PAGE 0x0c; DAC1 frame size */
299#define ES_REG_DAC2_FRAME 0x38 /* R/W: PAGE 0x0c; DAC2 frame address */
300#define ES_REG_DAC2_SIZE 0x3c /* R/W: PAGE 0x0c; DAC2 frame size */
301#define ES_REG_ADC_FRAME 0x30 /* R/W: PAGE 0x0d; ADC frame address */
302#define ES_REG_ADC_SIZE 0x34 /* R/W: PAGE 0x0d; ADC frame size */
303#define ES_REG_FCURR_COUNTO(o) (((o)&0xffff)<<16)
304#define ES_REG_FCURR_COUNTM (0xffff<<16)
305#define ES_REG_FCURR_COUNTI(i) (((i)>>14)&0x3fffc)
306#define ES_REG_FSIZEO(o) (((o)&0xffff)<<0)
307#define ES_REG_FSIZEM (0xffff<<0)
308#define ES_REG_FSIZEI(i) (((i)>>0)&0xffff)
309#define ES_REG_PHANTOM_FRAME 0x38 /* R/W: PAGE 0x0d: phantom frame address */
310#define ES_REG_PHANTOM_COUNT 0x3c /* R/W: PAGE 0x0d: phantom frame count */
311
312#define ES_REG_UART_FIFO 0x30 /* R/W: PAGE 0x0e; UART FIFO register */
313#define ES_REG_UF_VALID (1<<8)
314#define ES_REG_UF_BYTEO(o) (((o)&0xff)<<0)
315#define ES_REG_UF_BYTEM (0xff<<0)
316#define ES_REG_UF_BYTEI(i) (((i)>>0)&0xff)
317
318
319/*
320 * Pages
321 */
322
323#define ES_PAGE_DAC 0x0c
324#define ES_PAGE_ADC 0x0d
325#define ES_PAGE_UART 0x0e
326#define ES_PAGE_UART1 0x0f
327
328/*
329 * Sample rate converter addresses
330 */
331
332#define ES_SMPREG_DAC1 0x70
333#define ES_SMPREG_DAC2 0x74
334#define ES_SMPREG_ADC 0x78
335#define ES_SMPREG_VOL_ADC 0x6c
336#define ES_SMPREG_VOL_DAC1 0x7c
337#define ES_SMPREG_VOL_DAC2 0x7e
338#define ES_SMPREG_TRUNC_N 0x00
339#define ES_SMPREG_INT_REGS 0x01
340#define ES_SMPREG_ACCUM_FRAC 0x02
341#define ES_SMPREG_VFREQ_FRAC 0x03
342
343/*
344 * Some contants
345 */
346
347#define ES_1370_SRCLOCK 1411200
348#define ES_1370_SRTODIV(x) (ES_1370_SRCLOCK/(x)-2)
349
350/*
351 * Open modes
352 */
353
354#define ES_MODE_PLAY1 0x0001
355#define ES_MODE_PLAY2 0x0002
356#define ES_MODE_CAPTURE 0x0004
357
358#define ES_MODE_OUTPUT 0x0001 /* for MIDI */
359#define ES_MODE_INPUT 0x0002 /* for MIDI */
360
361/*
362
363 */
364
365struct ensoniq {
366 spinlock_t reg_lock;
367 struct mutex src_mutex;
368
369 int irq;
370
371 unsigned long playback1size;
372 unsigned long playback2size;
373 unsigned long capture3size;
374
375 unsigned long port;
376 unsigned int mode;
377 unsigned int uartm; /* UART mode */
378
379 unsigned int ctrl; /* control register */
380 unsigned int sctrl; /* serial control register */
381 unsigned int cssr; /* control status register */
382 unsigned int uartc; /* uart control register */
383 unsigned int rev; /* chip revision */
384
385 union {
386#ifdef CHIP1371
387 struct {
388 struct snd_ac97 *ac97;
389 } es1371;
390#else
391 struct {
392 int pclkdiv_lock;
393 struct snd_ak4531 *ak4531;
394 } es1370;
395#endif
396 } u;
397
398 struct pci_dev *pci;
399 struct snd_card *card;
400 struct snd_pcm *pcm1; /* DAC1/ADC PCM */
401 struct snd_pcm *pcm2; /* DAC2 PCM */
402 struct snd_pcm_substream *playback1_substream;
403 struct snd_pcm_substream *playback2_substream;
404 struct snd_pcm_substream *capture_substream;
405 unsigned int p1_dma_size;
406 unsigned int p2_dma_size;
407 unsigned int c_dma_size;
408 unsigned int p1_period_size;
409 unsigned int p2_period_size;
410 unsigned int c_period_size;
411 struct snd_rawmidi *rmidi;
412 struct snd_rawmidi_substream *midi_input;
413 struct snd_rawmidi_substream *midi_output;
414
415 unsigned int spdif;
416 unsigned int spdif_default;
417 unsigned int spdif_stream;
418
419#ifdef CHIP1370
420 struct snd_dma_buffer dma_bug;
421#endif
422
423#ifdef SUPPORT_JOYSTICK
424 struct gameport *gameport;
425#endif
426};
427
428static irqreturn_t snd_audiopci_interrupt(int irq, void *dev_id);
429
430static const struct pci_device_id snd_audiopci_ids[] = {
431#ifdef CHIP1370
432 { PCI_VDEVICE(ENSONIQ, 0x5000), 0, }, /* ES1370 */
433#endif
434#ifdef CHIP1371
435 { PCI_VDEVICE(ENSONIQ, 0x1371), 0, }, /* ES1371 */
436 { PCI_VDEVICE(ENSONIQ, 0x5880), 0, }, /* ES1373 - CT5880 */
437 { PCI_VDEVICE(ECTIVA, 0x8938), 0, }, /* Ectiva EV1938 */
438#endif
439 { 0, }
440};
441
442MODULE_DEVICE_TABLE(pci, snd_audiopci_ids);
443
444/*
445 * constants
446 */
447
448#define POLL_COUNT 0xa000
449
450#ifdef CHIP1370
451static const unsigned int snd_es1370_fixed_rates[] =
452 {5512, 11025, 22050, 44100};
453static const struct snd_pcm_hw_constraint_list snd_es1370_hw_constraints_rates = {
454 .count = 4,
455 .list = snd_es1370_fixed_rates,
456 .mask = 0,
457};
458static const struct snd_ratnum es1370_clock = {
459 .num = ES_1370_SRCLOCK,
460 .den_min = 29,
461 .den_max = 353,
462 .den_step = 1,
463};
464static const struct snd_pcm_hw_constraint_ratnums snd_es1370_hw_constraints_clock = {
465 .nrats = 1,
466 .rats = &es1370_clock,
467};
468#else
469static const struct snd_ratden es1371_dac_clock = {
470 .num_min = 3000 * (1 << 15),
471 .num_max = 48000 * (1 << 15),
472 .num_step = 3000,
473 .den = 1 << 15,
474};
475static const struct snd_pcm_hw_constraint_ratdens snd_es1371_hw_constraints_dac_clock = {
476 .nrats = 1,
477 .rats = &es1371_dac_clock,
478};
479static const struct snd_ratnum es1371_adc_clock = {
480 .num = 48000 << 15,
481 .den_min = 32768,
482 .den_max = 393216,
483 .den_step = 1,
484};
485static const struct snd_pcm_hw_constraint_ratnums snd_es1371_hw_constraints_adc_clock = {
486 .nrats = 1,
487 .rats = &es1371_adc_clock,
488};
489#endif
490static const unsigned int snd_ensoniq_sample_shift[] =
491 {0, 1, 1, 2};
492
493/*
494 * common I/O routines
495 */
496
497#ifdef CHIP1371
498
499static unsigned int snd_es1371_wait_src_ready(struct ensoniq * ensoniq)
500{
501 unsigned int t, r = 0;
502
503 for (t = 0; t < POLL_COUNT; t++) {
504 r = inl(ES_REG(ensoniq, 1371_SMPRATE));
505 if ((r & ES_1371_SRC_RAM_BUSY) == 0)
506 return r;
507 cond_resched();
508 }
509 dev_err(ensoniq->card->dev, "wait src ready timeout 0x%lx [0x%x]\n",
510 ES_REG(ensoniq, 1371_SMPRATE), r);
511 return 0;
512}
513
514static unsigned int snd_es1371_src_read(struct ensoniq * ensoniq, unsigned short reg)
515{
516 unsigned int temp, i, orig, r;
517
518 /* wait for ready */
519 temp = orig = snd_es1371_wait_src_ready(ensoniq);
520
521 /* expose the SRC state bits */
522 r = temp & (ES_1371_SRC_DISABLE | ES_1371_DIS_P1 |
523 ES_1371_DIS_P2 | ES_1371_DIS_R1);
524 r |= ES_1371_SRC_RAM_ADDRO(reg) | 0x10000;
525 outl(r, ES_REG(ensoniq, 1371_SMPRATE));
526
527 /* now, wait for busy and the correct time to read */
528 temp = snd_es1371_wait_src_ready(ensoniq);
529
530 if ((temp & 0x00870000) != 0x00010000) {
531 /* wait for the right state */
532 for (i = 0; i < POLL_COUNT; i++) {
533 temp = inl(ES_REG(ensoniq, 1371_SMPRATE));
534 if ((temp & 0x00870000) == 0x00010000)
535 break;
536 }
537 }
538
539 /* hide the state bits */
540 r = orig & (ES_1371_SRC_DISABLE | ES_1371_DIS_P1 |
541 ES_1371_DIS_P2 | ES_1371_DIS_R1);
542 r |= ES_1371_SRC_RAM_ADDRO(reg);
543 outl(r, ES_REG(ensoniq, 1371_SMPRATE));
544
545 return temp;
546}
547
548static void snd_es1371_src_write(struct ensoniq * ensoniq,
549 unsigned short reg, unsigned short data)
550{
551 unsigned int r;
552
553 r = snd_es1371_wait_src_ready(ensoniq) &
554 (ES_1371_SRC_DISABLE | ES_1371_DIS_P1 |
555 ES_1371_DIS_P2 | ES_1371_DIS_R1);
556 r |= ES_1371_SRC_RAM_ADDRO(reg) | ES_1371_SRC_RAM_DATAO(data);
557 outl(r | ES_1371_SRC_RAM_WE, ES_REG(ensoniq, 1371_SMPRATE));
558}
559
560#endif /* CHIP1371 */
561
562#ifdef CHIP1370
563
564static void snd_es1370_codec_write(struct snd_ak4531 *ak4531,
565 unsigned short reg, unsigned short val)
566{
567 struct ensoniq *ensoniq = ak4531->private_data;
568 unsigned long end_time = jiffies + HZ / 10;
569
570#if 0
571 dev_dbg(ensoniq->card->dev,
572 "CODEC WRITE: reg = 0x%x, val = 0x%x (0x%x), creg = 0x%x\n",
573 reg, val, ES_1370_CODEC_WRITE(reg, val), ES_REG(ensoniq, 1370_CODEC));
574#endif
575 do {
576 if (!(inl(ES_REG(ensoniq, STATUS)) & ES_1370_CSTAT)) {
577 outw(ES_1370_CODEC_WRITE(reg, val), ES_REG(ensoniq, 1370_CODEC));
578 return;
579 }
580 schedule_timeout_uninterruptible(1);
581 } while (time_after(end_time, jiffies));
582 dev_err(ensoniq->card->dev, "codec write timeout, status = 0x%x\n",
583 inl(ES_REG(ensoniq, STATUS)));
584}
585
586#endif /* CHIP1370 */
587
588#ifdef CHIP1371
589
590static inline bool is_ev1938(struct ensoniq *ensoniq)
591{
592 return ensoniq->pci->device == 0x8938;
593}
594
595static void snd_es1371_codec_write(struct snd_ac97 *ac97,
596 unsigned short reg, unsigned short val)
597{
598 struct ensoniq *ensoniq = ac97->private_data;
599 unsigned int t, x, flag;
600
601 flag = is_ev1938(ensoniq) ? EV_1938_CODEC_MAGIC : 0;
602 mutex_lock(&ensoniq->src_mutex);
603 for (t = 0; t < POLL_COUNT; t++) {
604 if (!(inl(ES_REG(ensoniq, 1371_CODEC)) & ES_1371_CODEC_WIP)) {
605 /* save the current state for latter */
606 x = snd_es1371_wait_src_ready(ensoniq);
607 outl((x & (ES_1371_SRC_DISABLE | ES_1371_DIS_P1 |
608 ES_1371_DIS_P2 | ES_1371_DIS_R1)) | 0x00010000,
609 ES_REG(ensoniq, 1371_SMPRATE));
610 /* wait for not busy (state 0) first to avoid
611 transition states */
612 for (t = 0; t < POLL_COUNT; t++) {
613 if ((inl(ES_REG(ensoniq, 1371_SMPRATE)) & 0x00870000) ==
614 0x00000000)
615 break;
616 }
617 /* wait for a SAFE time to write addr/data and then do it, dammit */
618 for (t = 0; t < POLL_COUNT; t++) {
619 if ((inl(ES_REG(ensoniq, 1371_SMPRATE)) & 0x00870000) ==
620 0x00010000)
621 break;
622 }
623 outl(ES_1371_CODEC_WRITE(reg, val) | flag,
624 ES_REG(ensoniq, 1371_CODEC));
625 /* restore SRC reg */
626 snd_es1371_wait_src_ready(ensoniq);
627 outl(x, ES_REG(ensoniq, 1371_SMPRATE));
628 mutex_unlock(&ensoniq->src_mutex);
629 return;
630 }
631 }
632 mutex_unlock(&ensoniq->src_mutex);
633 dev_err(ensoniq->card->dev, "codec write timeout at 0x%lx [0x%x]\n",
634 ES_REG(ensoniq, 1371_CODEC), inl(ES_REG(ensoniq, 1371_CODEC)));
635}
636
637static unsigned short snd_es1371_codec_read(struct snd_ac97 *ac97,
638 unsigned short reg)
639{
640 struct ensoniq *ensoniq = ac97->private_data;
641 unsigned int t, x, flag, fail = 0;
642
643 flag = is_ev1938(ensoniq) ? EV_1938_CODEC_MAGIC : 0;
644 __again:
645 mutex_lock(&ensoniq->src_mutex);
646 for (t = 0; t < POLL_COUNT; t++) {
647 if (!(inl(ES_REG(ensoniq, 1371_CODEC)) & ES_1371_CODEC_WIP)) {
648 /* save the current state for latter */
649 x = snd_es1371_wait_src_ready(ensoniq);
650 outl((x & (ES_1371_SRC_DISABLE | ES_1371_DIS_P1 |
651 ES_1371_DIS_P2 | ES_1371_DIS_R1)) | 0x00010000,
652 ES_REG(ensoniq, 1371_SMPRATE));
653 /* wait for not busy (state 0) first to avoid
654 transition states */
655 for (t = 0; t < POLL_COUNT; t++) {
656 if ((inl(ES_REG(ensoniq, 1371_SMPRATE)) & 0x00870000) ==
657 0x00000000)
658 break;
659 }
660 /* wait for a SAFE time to write addr/data and then do it, dammit */
661 for (t = 0; t < POLL_COUNT; t++) {
662 if ((inl(ES_REG(ensoniq, 1371_SMPRATE)) & 0x00870000) ==
663 0x00010000)
664 break;
665 }
666 outl(ES_1371_CODEC_READS(reg) | flag,
667 ES_REG(ensoniq, 1371_CODEC));
668 /* restore SRC reg */
669 snd_es1371_wait_src_ready(ensoniq);
670 outl(x, ES_REG(ensoniq, 1371_SMPRATE));
671 /* wait for WIP again */
672 for (t = 0; t < POLL_COUNT; t++) {
673 if (!(inl(ES_REG(ensoniq, 1371_CODEC)) & ES_1371_CODEC_WIP))
674 break;
675 }
676 /* now wait for the stinkin' data (RDY) */
677 for (t = 0; t < POLL_COUNT; t++) {
678 x = inl(ES_REG(ensoniq, 1371_CODEC));
679 if (x & ES_1371_CODEC_RDY) {
680 if (is_ev1938(ensoniq)) {
681 for (t = 0; t < 100; t++)
682 inl(ES_REG(ensoniq, CONTROL));
683 x = inl(ES_REG(ensoniq, 1371_CODEC));
684 }
685 mutex_unlock(&ensoniq->src_mutex);
686 return ES_1371_CODEC_READ(x);
687 }
688 }
689 mutex_unlock(&ensoniq->src_mutex);
690 if (++fail > 10) {
691 dev_err(ensoniq->card->dev,
692 "codec read timeout (final) at 0x%lx, reg = 0x%x [0x%x]\n",
693 ES_REG(ensoniq, 1371_CODEC), reg,
694 inl(ES_REG(ensoniq, 1371_CODEC)));
695 return 0;
696 }
697 goto __again;
698 }
699 }
700 mutex_unlock(&ensoniq->src_mutex);
701 dev_err(ensoniq->card->dev, "codec read timeout at 0x%lx [0x%x]\n",
702 ES_REG(ensoniq, 1371_CODEC), inl(ES_REG(ensoniq, 1371_CODEC)));
703 return 0;
704}
705
706static void snd_es1371_codec_wait(struct snd_ac97 *ac97)
707{
708 msleep(750);
709 snd_es1371_codec_read(ac97, AC97_RESET);
710 snd_es1371_codec_read(ac97, AC97_VENDOR_ID1);
711 snd_es1371_codec_read(ac97, AC97_VENDOR_ID2);
712 msleep(50);
713}
714
715static void snd_es1371_adc_rate(struct ensoniq * ensoniq, unsigned int rate)
716{
717 unsigned int n, truncm, freq;
718
719 mutex_lock(&ensoniq->src_mutex);
720 n = rate / 3000;
721 if ((1 << n) & ((1 << 15) | (1 << 13) | (1 << 11) | (1 << 9)))
722 n--;
723 truncm = (21 * n - 1) | 1;
724 freq = ((48000UL << 15) / rate) * n;
725 if (rate >= 24000) {
726 if (truncm > 239)
727 truncm = 239;
728 snd_es1371_src_write(ensoniq, ES_SMPREG_ADC + ES_SMPREG_TRUNC_N,
729 (((239 - truncm) >> 1) << 9) | (n << 4));
730 } else {
731 if (truncm > 119)
732 truncm = 119;
733 snd_es1371_src_write(ensoniq, ES_SMPREG_ADC + ES_SMPREG_TRUNC_N,
734 0x8000 | (((119 - truncm) >> 1) << 9) | (n << 4));
735 }
736 snd_es1371_src_write(ensoniq, ES_SMPREG_ADC + ES_SMPREG_INT_REGS,
737 (snd_es1371_src_read(ensoniq, ES_SMPREG_ADC +
738 ES_SMPREG_INT_REGS) & 0x00ff) |
739 ((freq >> 5) & 0xfc00));
740 snd_es1371_src_write(ensoniq, ES_SMPREG_ADC + ES_SMPREG_VFREQ_FRAC, freq & 0x7fff);
741 snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_ADC, n << 8);
742 snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_ADC + 1, n << 8);
743 mutex_unlock(&ensoniq->src_mutex);
744}
745
746static void snd_es1371_dac1_rate(struct ensoniq * ensoniq, unsigned int rate)
747{
748 unsigned int freq, r;
749
750 mutex_lock(&ensoniq->src_mutex);
751 freq = DIV_ROUND_CLOSEST(rate << 15, 3000);
752 r = (snd_es1371_wait_src_ready(ensoniq) & (ES_1371_SRC_DISABLE |
753 ES_1371_DIS_P2 | ES_1371_DIS_R1)) |
754 ES_1371_DIS_P1;
755 outl(r, ES_REG(ensoniq, 1371_SMPRATE));
756 snd_es1371_src_write(ensoniq, ES_SMPREG_DAC1 + ES_SMPREG_INT_REGS,
757 (snd_es1371_src_read(ensoniq, ES_SMPREG_DAC1 +
758 ES_SMPREG_INT_REGS) & 0x00ff) |
759 ((freq >> 5) & 0xfc00));
760 snd_es1371_src_write(ensoniq, ES_SMPREG_DAC1 + ES_SMPREG_VFREQ_FRAC, freq & 0x7fff);
761 r = (snd_es1371_wait_src_ready(ensoniq) & (ES_1371_SRC_DISABLE |
762 ES_1371_DIS_P2 | ES_1371_DIS_R1));
763 outl(r, ES_REG(ensoniq, 1371_SMPRATE));
764 mutex_unlock(&ensoniq->src_mutex);
765}
766
767static void snd_es1371_dac2_rate(struct ensoniq * ensoniq, unsigned int rate)
768{
769 unsigned int freq, r;
770
771 mutex_lock(&ensoniq->src_mutex);
772 freq = DIV_ROUND_CLOSEST(rate << 15, 3000);
773 r = (snd_es1371_wait_src_ready(ensoniq) & (ES_1371_SRC_DISABLE |
774 ES_1371_DIS_P1 | ES_1371_DIS_R1)) |
775 ES_1371_DIS_P2;
776 outl(r, ES_REG(ensoniq, 1371_SMPRATE));
777 snd_es1371_src_write(ensoniq, ES_SMPREG_DAC2 + ES_SMPREG_INT_REGS,
778 (snd_es1371_src_read(ensoniq, ES_SMPREG_DAC2 +
779 ES_SMPREG_INT_REGS) & 0x00ff) |
780 ((freq >> 5) & 0xfc00));
781 snd_es1371_src_write(ensoniq, ES_SMPREG_DAC2 + ES_SMPREG_VFREQ_FRAC,
782 freq & 0x7fff);
783 r = (snd_es1371_wait_src_ready(ensoniq) & (ES_1371_SRC_DISABLE |
784 ES_1371_DIS_P1 | ES_1371_DIS_R1));
785 outl(r, ES_REG(ensoniq, 1371_SMPRATE));
786 mutex_unlock(&ensoniq->src_mutex);
787}
788
789#endif /* CHIP1371 */
790
791static int snd_ensoniq_trigger(struct snd_pcm_substream *substream, int cmd)
792{
793 struct ensoniq *ensoniq = snd_pcm_substream_chip(substream);
794 switch (cmd) {
795 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
796 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
797 {
798 unsigned int what = 0;
799 struct snd_pcm_substream *s;
800 snd_pcm_group_for_each_entry(s, substream) {
801 if (s == ensoniq->playback1_substream) {
802 what |= ES_P1_PAUSE;
803 snd_pcm_trigger_done(s, substream);
804 } else if (s == ensoniq->playback2_substream) {
805 what |= ES_P2_PAUSE;
806 snd_pcm_trigger_done(s, substream);
807 } else if (s == ensoniq->capture_substream)
808 return -EINVAL;
809 }
810 spin_lock(&ensoniq->reg_lock);
811 if (cmd == SNDRV_PCM_TRIGGER_PAUSE_PUSH)
812 ensoniq->sctrl |= what;
813 else
814 ensoniq->sctrl &= ~what;
815 outl(ensoniq->sctrl, ES_REG(ensoniq, SERIAL));
816 spin_unlock(&ensoniq->reg_lock);
817 break;
818 }
819 case SNDRV_PCM_TRIGGER_START:
820 case SNDRV_PCM_TRIGGER_STOP:
821 {
822 unsigned int what = 0;
823 struct snd_pcm_substream *s;
824 snd_pcm_group_for_each_entry(s, substream) {
825 if (s == ensoniq->playback1_substream) {
826 what |= ES_DAC1_EN;
827 snd_pcm_trigger_done(s, substream);
828 } else if (s == ensoniq->playback2_substream) {
829 what |= ES_DAC2_EN;
830 snd_pcm_trigger_done(s, substream);
831 } else if (s == ensoniq->capture_substream) {
832 what |= ES_ADC_EN;
833 snd_pcm_trigger_done(s, substream);
834 }
835 }
836 spin_lock(&ensoniq->reg_lock);
837 if (cmd == SNDRV_PCM_TRIGGER_START)
838 ensoniq->ctrl |= what;
839 else
840 ensoniq->ctrl &= ~what;
841 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
842 spin_unlock(&ensoniq->reg_lock);
843 break;
844 }
845 default:
846 return -EINVAL;
847 }
848 return 0;
849}
850
851/*
852 * PCM part
853 */
854
855static int snd_ensoniq_playback1_prepare(struct snd_pcm_substream *substream)
856{
857 struct ensoniq *ensoniq = snd_pcm_substream_chip(substream);
858 struct snd_pcm_runtime *runtime = substream->runtime;
859 unsigned int mode = 0;
860
861 ensoniq->p1_dma_size = snd_pcm_lib_buffer_bytes(substream);
862 ensoniq->p1_period_size = snd_pcm_lib_period_bytes(substream);
863 if (snd_pcm_format_width(runtime->format) == 16)
864 mode |= 0x02;
865 if (runtime->channels > 1)
866 mode |= 0x01;
867 spin_lock_irq(&ensoniq->reg_lock);
868 ensoniq->ctrl &= ~ES_DAC1_EN;
869#ifdef CHIP1371
870 /* 48k doesn't need SRC (it breaks AC3-passthru) */
871 if (runtime->rate == 48000)
872 ensoniq->ctrl |= ES_1373_BYPASS_P1;
873 else
874 ensoniq->ctrl &= ~ES_1373_BYPASS_P1;
875#endif
876 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
877 outl(ES_MEM_PAGEO(ES_PAGE_DAC), ES_REG(ensoniq, MEM_PAGE));
878 outl(runtime->dma_addr, ES_REG(ensoniq, DAC1_FRAME));
879 outl((ensoniq->p1_dma_size >> 2) - 1, ES_REG(ensoniq, DAC1_SIZE));
880 ensoniq->sctrl &= ~(ES_P1_LOOP_SEL | ES_P1_PAUSE | ES_P1_SCT_RLD | ES_P1_MODEM);
881 ensoniq->sctrl |= ES_P1_INT_EN | ES_P1_MODEO(mode);
882 outl(ensoniq->sctrl, ES_REG(ensoniq, SERIAL));
883 outl((ensoniq->p1_period_size >> snd_ensoniq_sample_shift[mode]) - 1,
884 ES_REG(ensoniq, DAC1_COUNT));
885#ifdef CHIP1370
886 ensoniq->ctrl &= ~ES_1370_WTSRSELM;
887 switch (runtime->rate) {
888 case 5512: ensoniq->ctrl |= ES_1370_WTSRSEL(0); break;
889 case 11025: ensoniq->ctrl |= ES_1370_WTSRSEL(1); break;
890 case 22050: ensoniq->ctrl |= ES_1370_WTSRSEL(2); break;
891 case 44100: ensoniq->ctrl |= ES_1370_WTSRSEL(3); break;
892 default: snd_BUG();
893 }
894#endif
895 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
896 spin_unlock_irq(&ensoniq->reg_lock);
897#ifndef CHIP1370
898 snd_es1371_dac1_rate(ensoniq, runtime->rate);
899#endif
900 return 0;
901}
902
903static int snd_ensoniq_playback2_prepare(struct snd_pcm_substream *substream)
904{
905 struct ensoniq *ensoniq = snd_pcm_substream_chip(substream);
906 struct snd_pcm_runtime *runtime = substream->runtime;
907 unsigned int mode = 0;
908
909 ensoniq->p2_dma_size = snd_pcm_lib_buffer_bytes(substream);
910 ensoniq->p2_period_size = snd_pcm_lib_period_bytes(substream);
911 if (snd_pcm_format_width(runtime->format) == 16)
912 mode |= 0x02;
913 if (runtime->channels > 1)
914 mode |= 0x01;
915 spin_lock_irq(&ensoniq->reg_lock);
916 ensoniq->ctrl &= ~ES_DAC2_EN;
917 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
918 outl(ES_MEM_PAGEO(ES_PAGE_DAC), ES_REG(ensoniq, MEM_PAGE));
919 outl(runtime->dma_addr, ES_REG(ensoniq, DAC2_FRAME));
920 outl((ensoniq->p2_dma_size >> 2) - 1, ES_REG(ensoniq, DAC2_SIZE));
921 ensoniq->sctrl &= ~(ES_P2_LOOP_SEL | ES_P2_PAUSE | ES_P2_DAC_SEN |
922 ES_P2_END_INCM | ES_P2_ST_INCM | ES_P2_MODEM);
923 ensoniq->sctrl |= ES_P2_INT_EN | ES_P2_MODEO(mode) |
924 ES_P2_END_INCO(mode & 2 ? 2 : 1) | ES_P2_ST_INCO(0);
925 outl(ensoniq->sctrl, ES_REG(ensoniq, SERIAL));
926 outl((ensoniq->p2_period_size >> snd_ensoniq_sample_shift[mode]) - 1,
927 ES_REG(ensoniq, DAC2_COUNT));
928#ifdef CHIP1370
929 if (!(ensoniq->u.es1370.pclkdiv_lock & ES_MODE_CAPTURE)) {
930 ensoniq->ctrl &= ~ES_1370_PCLKDIVM;
931 ensoniq->ctrl |= ES_1370_PCLKDIVO(ES_1370_SRTODIV(runtime->rate));
932 ensoniq->u.es1370.pclkdiv_lock |= ES_MODE_PLAY2;
933 }
934#endif
935 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
936 spin_unlock_irq(&ensoniq->reg_lock);
937#ifndef CHIP1370
938 snd_es1371_dac2_rate(ensoniq, runtime->rate);
939#endif
940 return 0;
941}
942
943static int snd_ensoniq_capture_prepare(struct snd_pcm_substream *substream)
944{
945 struct ensoniq *ensoniq = snd_pcm_substream_chip(substream);
946 struct snd_pcm_runtime *runtime = substream->runtime;
947 unsigned int mode = 0;
948
949 ensoniq->c_dma_size = snd_pcm_lib_buffer_bytes(substream);
950 ensoniq->c_period_size = snd_pcm_lib_period_bytes(substream);
951 if (snd_pcm_format_width(runtime->format) == 16)
952 mode |= 0x02;
953 if (runtime->channels > 1)
954 mode |= 0x01;
955 spin_lock_irq(&ensoniq->reg_lock);
956 ensoniq->ctrl &= ~ES_ADC_EN;
957 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
958 outl(ES_MEM_PAGEO(ES_PAGE_ADC), ES_REG(ensoniq, MEM_PAGE));
959 outl(runtime->dma_addr, ES_REG(ensoniq, ADC_FRAME));
960 outl((ensoniq->c_dma_size >> 2) - 1, ES_REG(ensoniq, ADC_SIZE));
961 ensoniq->sctrl &= ~(ES_R1_LOOP_SEL | ES_R1_MODEM);
962 ensoniq->sctrl |= ES_R1_INT_EN | ES_R1_MODEO(mode);
963 outl(ensoniq->sctrl, ES_REG(ensoniq, SERIAL));
964 outl((ensoniq->c_period_size >> snd_ensoniq_sample_shift[mode]) - 1,
965 ES_REG(ensoniq, ADC_COUNT));
966#ifdef CHIP1370
967 if (!(ensoniq->u.es1370.pclkdiv_lock & ES_MODE_PLAY2)) {
968 ensoniq->ctrl &= ~ES_1370_PCLKDIVM;
969 ensoniq->ctrl |= ES_1370_PCLKDIVO(ES_1370_SRTODIV(runtime->rate));
970 ensoniq->u.es1370.pclkdiv_lock |= ES_MODE_CAPTURE;
971 }
972#endif
973 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
974 spin_unlock_irq(&ensoniq->reg_lock);
975#ifndef CHIP1370
976 snd_es1371_adc_rate(ensoniq, runtime->rate);
977#endif
978 return 0;
979}
980
981static snd_pcm_uframes_t snd_ensoniq_playback1_pointer(struct snd_pcm_substream *substream)
982{
983 struct ensoniq *ensoniq = snd_pcm_substream_chip(substream);
984 size_t ptr;
985
986 spin_lock(&ensoniq->reg_lock);
987 if (inl(ES_REG(ensoniq, CONTROL)) & ES_DAC1_EN) {
988 outl(ES_MEM_PAGEO(ES_PAGE_DAC), ES_REG(ensoniq, MEM_PAGE));
989 ptr = ES_REG_FCURR_COUNTI(inl(ES_REG(ensoniq, DAC1_SIZE)));
990 ptr = bytes_to_frames(substream->runtime, ptr);
991 } else {
992 ptr = 0;
993 }
994 spin_unlock(&ensoniq->reg_lock);
995 return ptr;
996}
997
998static snd_pcm_uframes_t snd_ensoniq_playback2_pointer(struct snd_pcm_substream *substream)
999{
1000 struct ensoniq *ensoniq = snd_pcm_substream_chip(substream);
1001 size_t ptr;
1002
1003 spin_lock(&ensoniq->reg_lock);
1004 if (inl(ES_REG(ensoniq, CONTROL)) & ES_DAC2_EN) {
1005 outl(ES_MEM_PAGEO(ES_PAGE_DAC), ES_REG(ensoniq, MEM_PAGE));
1006 ptr = ES_REG_FCURR_COUNTI(inl(ES_REG(ensoniq, DAC2_SIZE)));
1007 ptr = bytes_to_frames(substream->runtime, ptr);
1008 } else {
1009 ptr = 0;
1010 }
1011 spin_unlock(&ensoniq->reg_lock);
1012 return ptr;
1013}
1014
1015static snd_pcm_uframes_t snd_ensoniq_capture_pointer(struct snd_pcm_substream *substream)
1016{
1017 struct ensoniq *ensoniq = snd_pcm_substream_chip(substream);
1018 size_t ptr;
1019
1020 spin_lock(&ensoniq->reg_lock);
1021 if (inl(ES_REG(ensoniq, CONTROL)) & ES_ADC_EN) {
1022 outl(ES_MEM_PAGEO(ES_PAGE_ADC), ES_REG(ensoniq, MEM_PAGE));
1023 ptr = ES_REG_FCURR_COUNTI(inl(ES_REG(ensoniq, ADC_SIZE)));
1024 ptr = bytes_to_frames(substream->runtime, ptr);
1025 } else {
1026 ptr = 0;
1027 }
1028 spin_unlock(&ensoniq->reg_lock);
1029 return ptr;
1030}
1031
1032static const struct snd_pcm_hardware snd_ensoniq_playback1 =
1033{
1034 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1035 SNDRV_PCM_INFO_BLOCK_TRANSFER |
1036 SNDRV_PCM_INFO_MMAP_VALID |
1037 SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_SYNC_START),
1038 .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
1039 .rates =
1040#ifndef CHIP1370
1041 SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
1042#else
1043 (SNDRV_PCM_RATE_KNOT | /* 5512Hz rate */
1044 SNDRV_PCM_RATE_11025 | SNDRV_PCM_RATE_22050 |
1045 SNDRV_PCM_RATE_44100),
1046#endif
1047 .rate_min = 4000,
1048 .rate_max = 48000,
1049 .channels_min = 1,
1050 .channels_max = 2,
1051 .buffer_bytes_max = (128*1024),
1052 .period_bytes_min = 64,
1053 .period_bytes_max = (128*1024),
1054 .periods_min = 1,
1055 .periods_max = 1024,
1056 .fifo_size = 0,
1057};
1058
1059static const struct snd_pcm_hardware snd_ensoniq_playback2 =
1060{
1061 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1062 SNDRV_PCM_INFO_BLOCK_TRANSFER |
1063 SNDRV_PCM_INFO_MMAP_VALID | SNDRV_PCM_INFO_PAUSE |
1064 SNDRV_PCM_INFO_SYNC_START),
1065 .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
1066 .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
1067 .rate_min = 4000,
1068 .rate_max = 48000,
1069 .channels_min = 1,
1070 .channels_max = 2,
1071 .buffer_bytes_max = (128*1024),
1072 .period_bytes_min = 64,
1073 .period_bytes_max = (128*1024),
1074 .periods_min = 1,
1075 .periods_max = 1024,
1076 .fifo_size = 0,
1077};
1078
1079static const struct snd_pcm_hardware snd_ensoniq_capture =
1080{
1081 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1082 SNDRV_PCM_INFO_BLOCK_TRANSFER |
1083 SNDRV_PCM_INFO_MMAP_VALID | SNDRV_PCM_INFO_SYNC_START),
1084 .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
1085 .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
1086 .rate_min = 4000,
1087 .rate_max = 48000,
1088 .channels_min = 1,
1089 .channels_max = 2,
1090 .buffer_bytes_max = (128*1024),
1091 .period_bytes_min = 64,
1092 .period_bytes_max = (128*1024),
1093 .periods_min = 1,
1094 .periods_max = 1024,
1095 .fifo_size = 0,
1096};
1097
1098static int snd_ensoniq_playback1_open(struct snd_pcm_substream *substream)
1099{
1100 struct ensoniq *ensoniq = snd_pcm_substream_chip(substream);
1101 struct snd_pcm_runtime *runtime = substream->runtime;
1102
1103 ensoniq->mode |= ES_MODE_PLAY1;
1104 ensoniq->playback1_substream = substream;
1105 runtime->hw = snd_ensoniq_playback1;
1106 snd_pcm_set_sync(substream);
1107 spin_lock_irq(&ensoniq->reg_lock);
1108 if (ensoniq->spdif && ensoniq->playback2_substream == NULL)
1109 ensoniq->spdif_stream = ensoniq->spdif_default;
1110 spin_unlock_irq(&ensoniq->reg_lock);
1111#ifdef CHIP1370
1112 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
1113 &snd_es1370_hw_constraints_rates);
1114#else
1115 snd_pcm_hw_constraint_ratdens(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
1116 &snd_es1371_hw_constraints_dac_clock);
1117#endif
1118 return 0;
1119}
1120
1121static int snd_ensoniq_playback2_open(struct snd_pcm_substream *substream)
1122{
1123 struct ensoniq *ensoniq = snd_pcm_substream_chip(substream);
1124 struct snd_pcm_runtime *runtime = substream->runtime;
1125
1126 ensoniq->mode |= ES_MODE_PLAY2;
1127 ensoniq->playback2_substream = substream;
1128 runtime->hw = snd_ensoniq_playback2;
1129 snd_pcm_set_sync(substream);
1130 spin_lock_irq(&ensoniq->reg_lock);
1131 if (ensoniq->spdif && ensoniq->playback1_substream == NULL)
1132 ensoniq->spdif_stream = ensoniq->spdif_default;
1133 spin_unlock_irq(&ensoniq->reg_lock);
1134#ifdef CHIP1370
1135 snd_pcm_hw_constraint_ratnums(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
1136 &snd_es1370_hw_constraints_clock);
1137#else
1138 snd_pcm_hw_constraint_ratdens(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
1139 &snd_es1371_hw_constraints_dac_clock);
1140#endif
1141 return 0;
1142}
1143
1144static int snd_ensoniq_capture_open(struct snd_pcm_substream *substream)
1145{
1146 struct ensoniq *ensoniq = snd_pcm_substream_chip(substream);
1147 struct snd_pcm_runtime *runtime = substream->runtime;
1148
1149 ensoniq->mode |= ES_MODE_CAPTURE;
1150 ensoniq->capture_substream = substream;
1151 runtime->hw = snd_ensoniq_capture;
1152 snd_pcm_set_sync(substream);
1153#ifdef CHIP1370
1154 snd_pcm_hw_constraint_ratnums(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
1155 &snd_es1370_hw_constraints_clock);
1156#else
1157 snd_pcm_hw_constraint_ratnums(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
1158 &snd_es1371_hw_constraints_adc_clock);
1159#endif
1160 return 0;
1161}
1162
1163static int snd_ensoniq_playback1_close(struct snd_pcm_substream *substream)
1164{
1165 struct ensoniq *ensoniq = snd_pcm_substream_chip(substream);
1166
1167 ensoniq->playback1_substream = NULL;
1168 ensoniq->mode &= ~ES_MODE_PLAY1;
1169 return 0;
1170}
1171
1172static int snd_ensoniq_playback2_close(struct snd_pcm_substream *substream)
1173{
1174 struct ensoniq *ensoniq = snd_pcm_substream_chip(substream);
1175
1176 ensoniq->playback2_substream = NULL;
1177 spin_lock_irq(&ensoniq->reg_lock);
1178#ifdef CHIP1370
1179 ensoniq->u.es1370.pclkdiv_lock &= ~ES_MODE_PLAY2;
1180#endif
1181 ensoniq->mode &= ~ES_MODE_PLAY2;
1182 spin_unlock_irq(&ensoniq->reg_lock);
1183 return 0;
1184}
1185
1186static int snd_ensoniq_capture_close(struct snd_pcm_substream *substream)
1187{
1188 struct ensoniq *ensoniq = snd_pcm_substream_chip(substream);
1189
1190 ensoniq->capture_substream = NULL;
1191 spin_lock_irq(&ensoniq->reg_lock);
1192#ifdef CHIP1370
1193 ensoniq->u.es1370.pclkdiv_lock &= ~ES_MODE_CAPTURE;
1194#endif
1195 ensoniq->mode &= ~ES_MODE_CAPTURE;
1196 spin_unlock_irq(&ensoniq->reg_lock);
1197 return 0;
1198}
1199
1200static const struct snd_pcm_ops snd_ensoniq_playback1_ops = {
1201 .open = snd_ensoniq_playback1_open,
1202 .close = snd_ensoniq_playback1_close,
1203 .prepare = snd_ensoniq_playback1_prepare,
1204 .trigger = snd_ensoniq_trigger,
1205 .pointer = snd_ensoniq_playback1_pointer,
1206};
1207
1208static const struct snd_pcm_ops snd_ensoniq_playback2_ops = {
1209 .open = snd_ensoniq_playback2_open,
1210 .close = snd_ensoniq_playback2_close,
1211 .prepare = snd_ensoniq_playback2_prepare,
1212 .trigger = snd_ensoniq_trigger,
1213 .pointer = snd_ensoniq_playback2_pointer,
1214};
1215
1216static const struct snd_pcm_ops snd_ensoniq_capture_ops = {
1217 .open = snd_ensoniq_capture_open,
1218 .close = snd_ensoniq_capture_close,
1219 .prepare = snd_ensoniq_capture_prepare,
1220 .trigger = snd_ensoniq_trigger,
1221 .pointer = snd_ensoniq_capture_pointer,
1222};
1223
1224static const struct snd_pcm_chmap_elem surround_map[] = {
1225 { .channels = 1,
1226 .map = { SNDRV_CHMAP_MONO } },
1227 { .channels = 2,
1228 .map = { SNDRV_CHMAP_RL, SNDRV_CHMAP_RR } },
1229 {0}
1230};
1231
1232static int snd_ensoniq_pcm(struct ensoniq *ensoniq, int device)
1233{
1234 struct snd_pcm *pcm;
1235 int err;
1236
1237 err = snd_pcm_new(ensoniq->card, CHIP_NAME "/1", device, 1, 1, &pcm);
1238 if (err < 0)
1239 return err;
1240
1241#ifdef CHIP1370
1242 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_ensoniq_playback2_ops);
1243#else
1244 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_ensoniq_playback1_ops);
1245#endif
1246 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_ensoniq_capture_ops);
1247
1248 pcm->private_data = ensoniq;
1249 pcm->info_flags = 0;
1250 strcpy(pcm->name, CHIP_NAME " DAC2/ADC");
1251 ensoniq->pcm1 = pcm;
1252
1253 snd_pcm_set_managed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV,
1254 &ensoniq->pci->dev, 64*1024, 128*1024);
1255
1256#ifdef CHIP1370
1257 err = snd_pcm_add_chmap_ctls(pcm, SNDRV_PCM_STREAM_PLAYBACK,
1258 surround_map, 2, 0, NULL);
1259#else
1260 err = snd_pcm_add_chmap_ctls(pcm, SNDRV_PCM_STREAM_PLAYBACK,
1261 snd_pcm_std_chmaps, 2, 0, NULL);
1262#endif
1263 return err;
1264}
1265
1266static int snd_ensoniq_pcm2(struct ensoniq *ensoniq, int device)
1267{
1268 struct snd_pcm *pcm;
1269 int err;
1270
1271 err = snd_pcm_new(ensoniq->card, CHIP_NAME "/2", device, 1, 0, &pcm);
1272 if (err < 0)
1273 return err;
1274
1275#ifdef CHIP1370
1276 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_ensoniq_playback1_ops);
1277#else
1278 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_ensoniq_playback2_ops);
1279#endif
1280 pcm->private_data = ensoniq;
1281 pcm->info_flags = 0;
1282 strcpy(pcm->name, CHIP_NAME " DAC1");
1283 ensoniq->pcm2 = pcm;
1284
1285 snd_pcm_set_managed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV,
1286 &ensoniq->pci->dev, 64*1024, 128*1024);
1287
1288#ifdef CHIP1370
1289 err = snd_pcm_add_chmap_ctls(pcm, SNDRV_PCM_STREAM_PLAYBACK,
1290 snd_pcm_std_chmaps, 2, 0, NULL);
1291#else
1292 err = snd_pcm_add_chmap_ctls(pcm, SNDRV_PCM_STREAM_PLAYBACK,
1293 surround_map, 2, 0, NULL);
1294#endif
1295 return err;
1296}
1297
1298/*
1299 * Mixer section
1300 */
1301
1302/*
1303 * ENS1371 mixer (including SPDIF interface)
1304 */
1305#ifdef CHIP1371
1306static int snd_ens1373_spdif_info(struct snd_kcontrol *kcontrol,
1307 struct snd_ctl_elem_info *uinfo)
1308{
1309 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1310 uinfo->count = 1;
1311 return 0;
1312}
1313
1314static int snd_ens1373_spdif_default_get(struct snd_kcontrol *kcontrol,
1315 struct snd_ctl_elem_value *ucontrol)
1316{
1317 struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol);
1318 spin_lock_irq(&ensoniq->reg_lock);
1319 ucontrol->value.iec958.status[0] = (ensoniq->spdif_default >> 0) & 0xff;
1320 ucontrol->value.iec958.status[1] = (ensoniq->spdif_default >> 8) & 0xff;
1321 ucontrol->value.iec958.status[2] = (ensoniq->spdif_default >> 16) & 0xff;
1322 ucontrol->value.iec958.status[3] = (ensoniq->spdif_default >> 24) & 0xff;
1323 spin_unlock_irq(&ensoniq->reg_lock);
1324 return 0;
1325}
1326
1327static int snd_ens1373_spdif_default_put(struct snd_kcontrol *kcontrol,
1328 struct snd_ctl_elem_value *ucontrol)
1329{
1330 struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol);
1331 unsigned int val;
1332 int change;
1333
1334 val = ((u32)ucontrol->value.iec958.status[0] << 0) |
1335 ((u32)ucontrol->value.iec958.status[1] << 8) |
1336 ((u32)ucontrol->value.iec958.status[2] << 16) |
1337 ((u32)ucontrol->value.iec958.status[3] << 24);
1338 spin_lock_irq(&ensoniq->reg_lock);
1339 change = ensoniq->spdif_default != val;
1340 ensoniq->spdif_default = val;
1341 if (change && ensoniq->playback1_substream == NULL &&
1342 ensoniq->playback2_substream == NULL)
1343 outl(val, ES_REG(ensoniq, CHANNEL_STATUS));
1344 spin_unlock_irq(&ensoniq->reg_lock);
1345 return change;
1346}
1347
1348static int snd_ens1373_spdif_mask_get(struct snd_kcontrol *kcontrol,
1349 struct snd_ctl_elem_value *ucontrol)
1350{
1351 ucontrol->value.iec958.status[0] = 0xff;
1352 ucontrol->value.iec958.status[1] = 0xff;
1353 ucontrol->value.iec958.status[2] = 0xff;
1354 ucontrol->value.iec958.status[3] = 0xff;
1355 return 0;
1356}
1357
1358static int snd_ens1373_spdif_stream_get(struct snd_kcontrol *kcontrol,
1359 struct snd_ctl_elem_value *ucontrol)
1360{
1361 struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol);
1362 spin_lock_irq(&ensoniq->reg_lock);
1363 ucontrol->value.iec958.status[0] = (ensoniq->spdif_stream >> 0) & 0xff;
1364 ucontrol->value.iec958.status[1] = (ensoniq->spdif_stream >> 8) & 0xff;
1365 ucontrol->value.iec958.status[2] = (ensoniq->spdif_stream >> 16) & 0xff;
1366 ucontrol->value.iec958.status[3] = (ensoniq->spdif_stream >> 24) & 0xff;
1367 spin_unlock_irq(&ensoniq->reg_lock);
1368 return 0;
1369}
1370
1371static int snd_ens1373_spdif_stream_put(struct snd_kcontrol *kcontrol,
1372 struct snd_ctl_elem_value *ucontrol)
1373{
1374 struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol);
1375 unsigned int val;
1376 int change;
1377
1378 val = ((u32)ucontrol->value.iec958.status[0] << 0) |
1379 ((u32)ucontrol->value.iec958.status[1] << 8) |
1380 ((u32)ucontrol->value.iec958.status[2] << 16) |
1381 ((u32)ucontrol->value.iec958.status[3] << 24);
1382 spin_lock_irq(&ensoniq->reg_lock);
1383 change = ensoniq->spdif_stream != val;
1384 ensoniq->spdif_stream = val;
1385 if (change && (ensoniq->playback1_substream != NULL ||
1386 ensoniq->playback2_substream != NULL))
1387 outl(val, ES_REG(ensoniq, CHANNEL_STATUS));
1388 spin_unlock_irq(&ensoniq->reg_lock);
1389 return change;
1390}
1391
1392#define ES1371_SPDIF(xname) \
1393{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, .info = snd_es1371_spdif_info, \
1394 .get = snd_es1371_spdif_get, .put = snd_es1371_spdif_put }
1395
1396#define snd_es1371_spdif_info snd_ctl_boolean_mono_info
1397
1398static int snd_es1371_spdif_get(struct snd_kcontrol *kcontrol,
1399 struct snd_ctl_elem_value *ucontrol)
1400{
1401 struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol);
1402
1403 spin_lock_irq(&ensoniq->reg_lock);
1404 ucontrol->value.integer.value[0] = ensoniq->ctrl & ES_1373_SPDIF_THRU ? 1 : 0;
1405 spin_unlock_irq(&ensoniq->reg_lock);
1406 return 0;
1407}
1408
1409static int snd_es1371_spdif_put(struct snd_kcontrol *kcontrol,
1410 struct snd_ctl_elem_value *ucontrol)
1411{
1412 struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol);
1413 unsigned int nval1, nval2;
1414 int change;
1415
1416 nval1 = ucontrol->value.integer.value[0] ? ES_1373_SPDIF_THRU : 0;
1417 nval2 = ucontrol->value.integer.value[0] ? ES_1373_SPDIF_EN : 0;
1418 spin_lock_irq(&ensoniq->reg_lock);
1419 change = (ensoniq->ctrl & ES_1373_SPDIF_THRU) != nval1;
1420 ensoniq->ctrl &= ~ES_1373_SPDIF_THRU;
1421 ensoniq->ctrl |= nval1;
1422 ensoniq->cssr &= ~ES_1373_SPDIF_EN;
1423 ensoniq->cssr |= nval2;
1424 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
1425 outl(ensoniq->cssr, ES_REG(ensoniq, STATUS));
1426 spin_unlock_irq(&ensoniq->reg_lock);
1427 return change;
1428}
1429
1430
1431/* spdif controls */
1432static const struct snd_kcontrol_new snd_es1371_mixer_spdif[] = {
1433 ES1371_SPDIF(SNDRV_CTL_NAME_IEC958("",PLAYBACK,SWITCH)),
1434 {
1435 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1436 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,DEFAULT),
1437 .info = snd_ens1373_spdif_info,
1438 .get = snd_ens1373_spdif_default_get,
1439 .put = snd_ens1373_spdif_default_put,
1440 },
1441 {
1442 .access = SNDRV_CTL_ELEM_ACCESS_READ,
1443 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1444 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,MASK),
1445 .info = snd_ens1373_spdif_info,
1446 .get = snd_ens1373_spdif_mask_get
1447 },
1448 {
1449 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1450 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,PCM_STREAM),
1451 .info = snd_ens1373_spdif_info,
1452 .get = snd_ens1373_spdif_stream_get,
1453 .put = snd_ens1373_spdif_stream_put
1454 },
1455};
1456
1457
1458#define snd_es1373_rear_info snd_ctl_boolean_mono_info
1459
1460static int snd_es1373_rear_get(struct snd_kcontrol *kcontrol,
1461 struct snd_ctl_elem_value *ucontrol)
1462{
1463 struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol);
1464 int val = 0;
1465
1466 spin_lock_irq(&ensoniq->reg_lock);
1467 if ((ensoniq->cssr & (ES_1373_REAR_BIT27|ES_1373_REAR_BIT26|
1468 ES_1373_REAR_BIT24)) == ES_1373_REAR_BIT26)
1469 val = 1;
1470 ucontrol->value.integer.value[0] = val;
1471 spin_unlock_irq(&ensoniq->reg_lock);
1472 return 0;
1473}
1474
1475static int snd_es1373_rear_put(struct snd_kcontrol *kcontrol,
1476 struct snd_ctl_elem_value *ucontrol)
1477{
1478 struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol);
1479 unsigned int nval1;
1480 int change;
1481
1482 nval1 = ucontrol->value.integer.value[0] ?
1483 ES_1373_REAR_BIT26 : (ES_1373_REAR_BIT27|ES_1373_REAR_BIT24);
1484 spin_lock_irq(&ensoniq->reg_lock);
1485 change = (ensoniq->cssr & (ES_1373_REAR_BIT27|
1486 ES_1373_REAR_BIT26|ES_1373_REAR_BIT24)) != nval1;
1487 ensoniq->cssr &= ~(ES_1373_REAR_BIT27|ES_1373_REAR_BIT26|ES_1373_REAR_BIT24);
1488 ensoniq->cssr |= nval1;
1489 outl(ensoniq->cssr, ES_REG(ensoniq, STATUS));
1490 spin_unlock_irq(&ensoniq->reg_lock);
1491 return change;
1492}
1493
1494static const struct snd_kcontrol_new snd_ens1373_rear =
1495{
1496 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
1497 .name = "AC97 2ch->4ch Copy Switch",
1498 .info = snd_es1373_rear_info,
1499 .get = snd_es1373_rear_get,
1500 .put = snd_es1373_rear_put,
1501};
1502
1503#define snd_es1373_line_info snd_ctl_boolean_mono_info
1504
1505static int snd_es1373_line_get(struct snd_kcontrol *kcontrol,
1506 struct snd_ctl_elem_value *ucontrol)
1507{
1508 struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol);
1509 int val = 0;
1510
1511 spin_lock_irq(&ensoniq->reg_lock);
1512 if (ensoniq->ctrl & ES_1371_GPIO_OUT(4))
1513 val = 1;
1514 ucontrol->value.integer.value[0] = val;
1515 spin_unlock_irq(&ensoniq->reg_lock);
1516 return 0;
1517}
1518
1519static int snd_es1373_line_put(struct snd_kcontrol *kcontrol,
1520 struct snd_ctl_elem_value *ucontrol)
1521{
1522 struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol);
1523 int changed;
1524 unsigned int ctrl;
1525
1526 spin_lock_irq(&ensoniq->reg_lock);
1527 ctrl = ensoniq->ctrl;
1528 if (ucontrol->value.integer.value[0])
1529 ensoniq->ctrl |= ES_1371_GPIO_OUT(4); /* switch line-in -> rear out */
1530 else
1531 ensoniq->ctrl &= ~ES_1371_GPIO_OUT(4);
1532 changed = (ctrl != ensoniq->ctrl);
1533 if (changed)
1534 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
1535 spin_unlock_irq(&ensoniq->reg_lock);
1536 return changed;
1537}
1538
1539static const struct snd_kcontrol_new snd_ens1373_line =
1540{
1541 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
1542 .name = "Line In->Rear Out Switch",
1543 .info = snd_es1373_line_info,
1544 .get = snd_es1373_line_get,
1545 .put = snd_es1373_line_put,
1546};
1547
1548static void snd_ensoniq_mixer_free_ac97(struct snd_ac97 *ac97)
1549{
1550 struct ensoniq *ensoniq = ac97->private_data;
1551 ensoniq->u.es1371.ac97 = NULL;
1552}
1553
1554struct es1371_quirk {
1555 unsigned short vid; /* vendor ID */
1556 unsigned short did; /* device ID */
1557 unsigned char rev; /* revision */
1558};
1559
1560static int es1371_quirk_lookup(struct ensoniq *ensoniq,
1561 const struct es1371_quirk *list)
1562{
1563 while (list->vid != (unsigned short)PCI_ANY_ID) {
1564 if (ensoniq->pci->vendor == list->vid &&
1565 ensoniq->pci->device == list->did &&
1566 ensoniq->rev == list->rev)
1567 return 1;
1568 list++;
1569 }
1570 return 0;
1571}
1572
1573static const struct es1371_quirk es1371_spdif_present[] = {
1574 { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_CT5880, .rev = CT5880REV_CT5880_C },
1575 { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_CT5880, .rev = CT5880REV_CT5880_D },
1576 { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_CT5880, .rev = CT5880REV_CT5880_E },
1577 { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_ES1371, .rev = ES1371REV_CT5880_A },
1578 { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_ES1371, .rev = ES1371REV_ES1373_8 },
1579 { .vid = PCI_ANY_ID, .did = PCI_ANY_ID }
1580};
1581
1582static const struct snd_pci_quirk ens1373_line_quirk[] = {
1583 SND_PCI_QUIRK_ID(0x1274, 0x2000), /* GA-7DXR */
1584 SND_PCI_QUIRK_ID(0x1458, 0xa000), /* GA-8IEXP */
1585 {0} /* end */
1586};
1587
1588static int snd_ensoniq_1371_mixer(struct ensoniq *ensoniq,
1589 int has_spdif, int has_line)
1590{
1591 struct snd_card *card = ensoniq->card;
1592 struct snd_ac97_bus *pbus;
1593 struct snd_ac97_template ac97;
1594 int err;
1595 static const struct snd_ac97_bus_ops ops = {
1596 .write = snd_es1371_codec_write,
1597 .read = snd_es1371_codec_read,
1598 .wait = snd_es1371_codec_wait,
1599 };
1600
1601 err = snd_ac97_bus(card, 0, &ops, NULL, &pbus);
1602 if (err < 0)
1603 return err;
1604
1605 memset(&ac97, 0, sizeof(ac97));
1606 ac97.private_data = ensoniq;
1607 ac97.private_free = snd_ensoniq_mixer_free_ac97;
1608 ac97.pci = ensoniq->pci;
1609 ac97.scaps = AC97_SCAP_AUDIO;
1610 err = snd_ac97_mixer(pbus, &ac97, &ensoniq->u.es1371.ac97);
1611 if (err < 0)
1612 return err;
1613 if (has_spdif > 0 ||
1614 (!has_spdif && es1371_quirk_lookup(ensoniq, es1371_spdif_present))) {
1615 struct snd_kcontrol *kctl;
1616 int i, is_spdif = 0;
1617
1618 ensoniq->spdif_default = ensoniq->spdif_stream =
1619 SNDRV_PCM_DEFAULT_CON_SPDIF;
1620 outl(ensoniq->spdif_default, ES_REG(ensoniq, CHANNEL_STATUS));
1621
1622 if (ensoniq->u.es1371.ac97->ext_id & AC97_EI_SPDIF)
1623 is_spdif++;
1624
1625 for (i = 0; i < ARRAY_SIZE(snd_es1371_mixer_spdif); i++) {
1626 kctl = snd_ctl_new1(&snd_es1371_mixer_spdif[i], ensoniq);
1627 if (!kctl)
1628 return -ENOMEM;
1629 kctl->id.index = is_spdif;
1630 err = snd_ctl_add(card, kctl);
1631 if (err < 0)
1632 return err;
1633 }
1634 }
1635 if (ensoniq->u.es1371.ac97->ext_id & AC97_EI_SDAC) {
1636 /* mirror rear to front speakers */
1637 ensoniq->cssr &= ~(ES_1373_REAR_BIT27|ES_1373_REAR_BIT24);
1638 ensoniq->cssr |= ES_1373_REAR_BIT26;
1639 err = snd_ctl_add(card, snd_ctl_new1(&snd_ens1373_rear, ensoniq));
1640 if (err < 0)
1641 return err;
1642 }
1643 if (has_line > 0 ||
1644 snd_pci_quirk_lookup(ensoniq->pci, ens1373_line_quirk)) {
1645 err = snd_ctl_add(card, snd_ctl_new1(&snd_ens1373_line,
1646 ensoniq));
1647 if (err < 0)
1648 return err;
1649 }
1650
1651 return 0;
1652}
1653
1654#endif /* CHIP1371 */
1655
1656/* generic control callbacks for ens1370 */
1657#ifdef CHIP1370
1658#define ENSONIQ_CONTROL(xname, mask) \
1659{ .iface = SNDRV_CTL_ELEM_IFACE_CARD, .name = xname, .info = snd_ensoniq_control_info, \
1660 .get = snd_ensoniq_control_get, .put = snd_ensoniq_control_put, \
1661 .private_value = mask }
1662
1663#define snd_ensoniq_control_info snd_ctl_boolean_mono_info
1664
1665static int snd_ensoniq_control_get(struct snd_kcontrol *kcontrol,
1666 struct snd_ctl_elem_value *ucontrol)
1667{
1668 struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol);
1669 int mask = kcontrol->private_value;
1670
1671 spin_lock_irq(&ensoniq->reg_lock);
1672 ucontrol->value.integer.value[0] = ensoniq->ctrl & mask ? 1 : 0;
1673 spin_unlock_irq(&ensoniq->reg_lock);
1674 return 0;
1675}
1676
1677static int snd_ensoniq_control_put(struct snd_kcontrol *kcontrol,
1678 struct snd_ctl_elem_value *ucontrol)
1679{
1680 struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol);
1681 int mask = kcontrol->private_value;
1682 unsigned int nval;
1683 int change;
1684
1685 nval = ucontrol->value.integer.value[0] ? mask : 0;
1686 spin_lock_irq(&ensoniq->reg_lock);
1687 change = (ensoniq->ctrl & mask) != nval;
1688 ensoniq->ctrl &= ~mask;
1689 ensoniq->ctrl |= nval;
1690 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
1691 spin_unlock_irq(&ensoniq->reg_lock);
1692 return change;
1693}
1694
1695/*
1696 * ENS1370 mixer
1697 */
1698
1699static const struct snd_kcontrol_new snd_es1370_controls[2] = {
1700ENSONIQ_CONTROL("PCM 0 Output also on Line-In Jack", ES_1370_XCTL0),
1701ENSONIQ_CONTROL("Mic +5V bias", ES_1370_XCTL1)
1702};
1703
1704#define ES1370_CONTROLS ARRAY_SIZE(snd_es1370_controls)
1705
1706static void snd_ensoniq_mixer_free_ak4531(struct snd_ak4531 *ak4531)
1707{
1708 struct ensoniq *ensoniq = ak4531->private_data;
1709 ensoniq->u.es1370.ak4531 = NULL;
1710}
1711
1712static int snd_ensoniq_1370_mixer(struct ensoniq *ensoniq)
1713{
1714 struct snd_card *card = ensoniq->card;
1715 struct snd_ak4531 ak4531;
1716 unsigned int idx;
1717 int err;
1718
1719 /* try reset AK4531 */
1720 outw(ES_1370_CODEC_WRITE(AK4531_RESET, 0x02), ES_REG(ensoniq, 1370_CODEC));
1721 inw(ES_REG(ensoniq, 1370_CODEC));
1722 udelay(100);
1723 outw(ES_1370_CODEC_WRITE(AK4531_RESET, 0x03), ES_REG(ensoniq, 1370_CODEC));
1724 inw(ES_REG(ensoniq, 1370_CODEC));
1725 udelay(100);
1726
1727 memset(&ak4531, 0, sizeof(ak4531));
1728 ak4531.write = snd_es1370_codec_write;
1729 ak4531.private_data = ensoniq;
1730 ak4531.private_free = snd_ensoniq_mixer_free_ak4531;
1731 err = snd_ak4531_mixer(card, &ak4531, &ensoniq->u.es1370.ak4531);
1732 if (err < 0)
1733 return err;
1734 for (idx = 0; idx < ES1370_CONTROLS; idx++) {
1735 err = snd_ctl_add(card, snd_ctl_new1(&snd_es1370_controls[idx], ensoniq));
1736 if (err < 0)
1737 return err;
1738 }
1739 return 0;
1740}
1741
1742#endif /* CHIP1370 */
1743
1744#ifdef SUPPORT_JOYSTICK
1745
1746#ifdef CHIP1371
1747static int snd_ensoniq_get_joystick_port(struct ensoniq *ensoniq, int dev)
1748{
1749 switch (joystick_port[dev]) {
1750 case 0: /* disabled */
1751 case 1: /* auto-detect */
1752 case 0x200:
1753 case 0x208:
1754 case 0x210:
1755 case 0x218:
1756 return joystick_port[dev];
1757
1758 default:
1759 dev_err(ensoniq->card->dev,
1760 "invalid joystick port %#x", joystick_port[dev]);
1761 return 0;
1762 }
1763}
1764#else
1765static int snd_ensoniq_get_joystick_port(struct ensoniq *ensoniq, int dev)
1766{
1767 return joystick[dev] ? 0x200 : 0;
1768}
1769#endif
1770
1771static int snd_ensoniq_create_gameport(struct ensoniq *ensoniq, int dev)
1772{
1773 struct gameport *gp;
1774 int io_port;
1775
1776 io_port = snd_ensoniq_get_joystick_port(ensoniq, dev);
1777
1778 switch (io_port) {
1779 case 0:
1780 return -ENOSYS;
1781
1782 case 1: /* auto_detect */
1783 for (io_port = 0x200; io_port <= 0x218; io_port += 8)
1784 if (request_region(io_port, 8, "ens137x: gameport"))
1785 break;
1786 if (io_port > 0x218) {
1787 dev_warn(ensoniq->card->dev,
1788 "no gameport ports available\n");
1789 return -EBUSY;
1790 }
1791 break;
1792
1793 default:
1794 if (!request_region(io_port, 8, "ens137x: gameport")) {
1795 dev_warn(ensoniq->card->dev,
1796 "gameport io port %#x in use\n",
1797 io_port);
1798 return -EBUSY;
1799 }
1800 break;
1801 }
1802
1803 ensoniq->gameport = gp = gameport_allocate_port();
1804 if (!gp) {
1805 dev_err(ensoniq->card->dev,
1806 "cannot allocate memory for gameport\n");
1807 release_region(io_port, 8);
1808 return -ENOMEM;
1809 }
1810
1811 gameport_set_name(gp, "ES137x");
1812 gameport_set_phys(gp, "pci%s/gameport0", pci_name(ensoniq->pci));
1813 gameport_set_dev_parent(gp, &ensoniq->pci->dev);
1814 gp->io = io_port;
1815
1816 ensoniq->ctrl |= ES_JYSTK_EN;
1817#ifdef CHIP1371
1818 ensoniq->ctrl &= ~ES_1371_JOY_ASELM;
1819 ensoniq->ctrl |= ES_1371_JOY_ASEL((io_port - 0x200) / 8);
1820#endif
1821 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
1822
1823 gameport_register_port(ensoniq->gameport);
1824
1825 return 0;
1826}
1827
1828static void snd_ensoniq_free_gameport(struct ensoniq *ensoniq)
1829{
1830 if (ensoniq->gameport) {
1831 int port = ensoniq->gameport->io;
1832
1833 gameport_unregister_port(ensoniq->gameport);
1834 ensoniq->gameport = NULL;
1835 ensoniq->ctrl &= ~ES_JYSTK_EN;
1836 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
1837 release_region(port, 8);
1838 }
1839}
1840#else
1841static inline int snd_ensoniq_create_gameport(struct ensoniq *ensoniq, long port) { return -ENOSYS; }
1842static inline void snd_ensoniq_free_gameport(struct ensoniq *ensoniq) { }
1843#endif /* SUPPORT_JOYSTICK */
1844
1845/*
1846
1847 */
1848
1849static void snd_ensoniq_proc_read(struct snd_info_entry *entry,
1850 struct snd_info_buffer *buffer)
1851{
1852 struct ensoniq *ensoniq = entry->private_data;
1853
1854 snd_iprintf(buffer, "Ensoniq AudioPCI " CHIP_NAME "\n\n");
1855 snd_iprintf(buffer, "Joystick enable : %s\n",
1856 ensoniq->ctrl & ES_JYSTK_EN ? "on" : "off");
1857#ifdef CHIP1370
1858 snd_iprintf(buffer, "MIC +5V bias : %s\n",
1859 ensoniq->ctrl & ES_1370_XCTL1 ? "on" : "off");
1860 snd_iprintf(buffer, "Line In to AOUT : %s\n",
1861 ensoniq->ctrl & ES_1370_XCTL0 ? "on" : "off");
1862#else
1863 snd_iprintf(buffer, "Joystick port : 0x%x\n",
1864 (ES_1371_JOY_ASELI(ensoniq->ctrl) * 8) + 0x200);
1865#endif
1866}
1867
1868static void snd_ensoniq_proc_init(struct ensoniq *ensoniq)
1869{
1870 snd_card_ro_proc_new(ensoniq->card, "audiopci", ensoniq,
1871 snd_ensoniq_proc_read);
1872}
1873
1874/*
1875
1876 */
1877
1878static int snd_ensoniq_free(struct ensoniq *ensoniq)
1879{
1880 snd_ensoniq_free_gameport(ensoniq);
1881 if (ensoniq->irq < 0)
1882 goto __hw_end;
1883#ifdef CHIP1370
1884 outl(ES_1370_SERR_DISABLE, ES_REG(ensoniq, CONTROL)); /* switch everything off */
1885 outl(0, ES_REG(ensoniq, SERIAL)); /* clear serial interface */
1886#else
1887 outl(0, ES_REG(ensoniq, CONTROL)); /* switch everything off */
1888 outl(0, ES_REG(ensoniq, SERIAL)); /* clear serial interface */
1889#endif
1890 pci_set_power_state(ensoniq->pci, PCI_D3hot);
1891 __hw_end:
1892#ifdef CHIP1370
1893 if (ensoniq->dma_bug.area)
1894 snd_dma_free_pages(&ensoniq->dma_bug);
1895#endif
1896 if (ensoniq->irq >= 0)
1897 free_irq(ensoniq->irq, ensoniq);
1898 pci_release_regions(ensoniq->pci);
1899 pci_disable_device(ensoniq->pci);
1900 kfree(ensoniq);
1901 return 0;
1902}
1903
1904static int snd_ensoniq_dev_free(struct snd_device *device)
1905{
1906 struct ensoniq *ensoniq = device->device_data;
1907 return snd_ensoniq_free(ensoniq);
1908}
1909
1910#ifdef CHIP1371
1911static const struct snd_pci_quirk es1371_amplifier_hack[] = {
1912 SND_PCI_QUIRK_ID(0x107b, 0x2150), /* Gateway Solo 2150 */
1913 SND_PCI_QUIRK_ID(0x13bd, 0x100c), /* EV1938 on Mebius PC-MJ100V */
1914 SND_PCI_QUIRK_ID(0x1102, 0x5938), /* Targa Xtender300 */
1915 SND_PCI_QUIRK_ID(0x1102, 0x8938), /* IPC Topnote G notebook */
1916 {0} /* end */
1917};
1918
1919static const struct es1371_quirk es1371_ac97_reset_hack[] = {
1920 { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_CT5880, .rev = CT5880REV_CT5880_C },
1921 { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_CT5880, .rev = CT5880REV_CT5880_D },
1922 { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_CT5880, .rev = CT5880REV_CT5880_E },
1923 { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_ES1371, .rev = ES1371REV_CT5880_A },
1924 { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_ES1371, .rev = ES1371REV_ES1373_8 },
1925 { .vid = PCI_ANY_ID, .did = PCI_ANY_ID }
1926};
1927#endif
1928
1929static void snd_ensoniq_chip_init(struct ensoniq *ensoniq)
1930{
1931#ifdef CHIP1371
1932 int idx;
1933#endif
1934 /* this code was part of snd_ensoniq_create before intruduction
1935 * of suspend/resume
1936 */
1937#ifdef CHIP1370
1938 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
1939 outl(ensoniq->sctrl, ES_REG(ensoniq, SERIAL));
1940 outl(ES_MEM_PAGEO(ES_PAGE_ADC), ES_REG(ensoniq, MEM_PAGE));
1941 outl(ensoniq->dma_bug.addr, ES_REG(ensoniq, PHANTOM_FRAME));
1942 outl(0, ES_REG(ensoniq, PHANTOM_COUNT));
1943#else
1944 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
1945 outl(ensoniq->sctrl, ES_REG(ensoniq, SERIAL));
1946 outl(0, ES_REG(ensoniq, 1371_LEGACY));
1947 if (es1371_quirk_lookup(ensoniq, es1371_ac97_reset_hack)) {
1948 outl(ensoniq->cssr, ES_REG(ensoniq, STATUS));
1949 /* need to delay around 20ms(bleech) to give
1950 some CODECs enough time to wakeup */
1951 msleep(20);
1952 }
1953 /* AC'97 warm reset to start the bitclk */
1954 outl(ensoniq->ctrl | ES_1371_SYNC_RES, ES_REG(ensoniq, CONTROL));
1955 inl(ES_REG(ensoniq, CONTROL));
1956 udelay(20);
1957 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
1958 /* Init the sample rate converter */
1959 snd_es1371_wait_src_ready(ensoniq);
1960 outl(ES_1371_SRC_DISABLE, ES_REG(ensoniq, 1371_SMPRATE));
1961 for (idx = 0; idx < 0x80; idx++)
1962 snd_es1371_src_write(ensoniq, idx, 0);
1963 snd_es1371_src_write(ensoniq, ES_SMPREG_DAC1 + ES_SMPREG_TRUNC_N, 16 << 4);
1964 snd_es1371_src_write(ensoniq, ES_SMPREG_DAC1 + ES_SMPREG_INT_REGS, 16 << 10);
1965 snd_es1371_src_write(ensoniq, ES_SMPREG_DAC2 + ES_SMPREG_TRUNC_N, 16 << 4);
1966 snd_es1371_src_write(ensoniq, ES_SMPREG_DAC2 + ES_SMPREG_INT_REGS, 16 << 10);
1967 snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_ADC, 1 << 12);
1968 snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_ADC + 1, 1 << 12);
1969 snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_DAC1, 1 << 12);
1970 snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_DAC1 + 1, 1 << 12);
1971 snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_DAC2, 1 << 12);
1972 snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_DAC2 + 1, 1 << 12);
1973 snd_es1371_adc_rate(ensoniq, 22050);
1974 snd_es1371_dac1_rate(ensoniq, 22050);
1975 snd_es1371_dac2_rate(ensoniq, 22050);
1976 /* WARNING:
1977 * enabling the sample rate converter without properly programming
1978 * its parameters causes the chip to lock up (the SRC busy bit will
1979 * be stuck high, and I've found no way to rectify this other than
1980 * power cycle) - Thomas Sailer
1981 */
1982 snd_es1371_wait_src_ready(ensoniq);
1983 outl(0, ES_REG(ensoniq, 1371_SMPRATE));
1984 /* try reset codec directly */
1985 outl(ES_1371_CODEC_WRITE(0, 0), ES_REG(ensoniq, 1371_CODEC));
1986#endif
1987 outb(ensoniq->uartc = 0x00, ES_REG(ensoniq, UART_CONTROL));
1988 outb(0x00, ES_REG(ensoniq, UART_RES));
1989 outl(ensoniq->cssr, ES_REG(ensoniq, STATUS));
1990}
1991
1992#ifdef CONFIG_PM_SLEEP
1993static int snd_ensoniq_suspend(struct device *dev)
1994{
1995 struct snd_card *card = dev_get_drvdata(dev);
1996 struct ensoniq *ensoniq = card->private_data;
1997
1998 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
1999
2000#ifdef CHIP1371
2001 snd_ac97_suspend(ensoniq->u.es1371.ac97);
2002#else
2003 /* try to reset AK4531 */
2004 outw(ES_1370_CODEC_WRITE(AK4531_RESET, 0x02), ES_REG(ensoniq, 1370_CODEC));
2005 inw(ES_REG(ensoniq, 1370_CODEC));
2006 udelay(100);
2007 outw(ES_1370_CODEC_WRITE(AK4531_RESET, 0x03), ES_REG(ensoniq, 1370_CODEC));
2008 inw(ES_REG(ensoniq, 1370_CODEC));
2009 udelay(100);
2010 snd_ak4531_suspend(ensoniq->u.es1370.ak4531);
2011#endif
2012 return 0;
2013}
2014
2015static int snd_ensoniq_resume(struct device *dev)
2016{
2017 struct snd_card *card = dev_get_drvdata(dev);
2018 struct ensoniq *ensoniq = card->private_data;
2019
2020 snd_ensoniq_chip_init(ensoniq);
2021
2022#ifdef CHIP1371
2023 snd_ac97_resume(ensoniq->u.es1371.ac97);
2024#else
2025 snd_ak4531_resume(ensoniq->u.es1370.ak4531);
2026#endif
2027 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
2028 return 0;
2029}
2030
2031static SIMPLE_DEV_PM_OPS(snd_ensoniq_pm, snd_ensoniq_suspend, snd_ensoniq_resume);
2032#define SND_ENSONIQ_PM_OPS &snd_ensoniq_pm
2033#else
2034#define SND_ENSONIQ_PM_OPS NULL
2035#endif /* CONFIG_PM_SLEEP */
2036
2037static int snd_ensoniq_create(struct snd_card *card,
2038 struct pci_dev *pci,
2039 struct ensoniq **rensoniq)
2040{
2041 struct ensoniq *ensoniq;
2042 int err;
2043 static const struct snd_device_ops ops = {
2044 .dev_free = snd_ensoniq_dev_free,
2045 };
2046
2047 *rensoniq = NULL;
2048 err = pci_enable_device(pci);
2049 if (err < 0)
2050 return err;
2051 ensoniq = kzalloc(sizeof(*ensoniq), GFP_KERNEL);
2052 if (ensoniq == NULL) {
2053 pci_disable_device(pci);
2054 return -ENOMEM;
2055 }
2056 spin_lock_init(&ensoniq->reg_lock);
2057 mutex_init(&ensoniq->src_mutex);
2058 ensoniq->card = card;
2059 ensoniq->pci = pci;
2060 ensoniq->irq = -1;
2061 err = pci_request_regions(pci, "Ensoniq AudioPCI");
2062 if (err < 0) {
2063 kfree(ensoniq);
2064 pci_disable_device(pci);
2065 return err;
2066 }
2067 ensoniq->port = pci_resource_start(pci, 0);
2068 if (request_irq(pci->irq, snd_audiopci_interrupt, IRQF_SHARED,
2069 KBUILD_MODNAME, ensoniq)) {
2070 dev_err(card->dev, "unable to grab IRQ %d\n", pci->irq);
2071 snd_ensoniq_free(ensoniq);
2072 return -EBUSY;
2073 }
2074 ensoniq->irq = pci->irq;
2075 card->sync_irq = ensoniq->irq;
2076#ifdef CHIP1370
2077 if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, &pci->dev,
2078 16, &ensoniq->dma_bug) < 0) {
2079 dev_err(card->dev, "unable to allocate space for phantom area - dma_bug\n");
2080 snd_ensoniq_free(ensoniq);
2081 return -EBUSY;
2082 }
2083#endif
2084 pci_set_master(pci);
2085#ifndef TARGET_OS2
2086 ensoniq->rev = pci->revision;
2087#else
2088 ensoniq->rev = snd_pci_revision(pci);
2089#endif
2090#ifdef CHIP1370
2091#if 0
2092 ensoniq->ctrl = ES_1370_CDC_EN | ES_1370_SERR_DISABLE |
2093 ES_1370_PCLKDIVO(ES_1370_SRTODIV(8000));
2094#else /* get microphone working */
2095 ensoniq->ctrl = ES_1370_CDC_EN | ES_1370_PCLKDIVO(ES_1370_SRTODIV(8000));
2096#endif
2097 ensoniq->sctrl = 0;
2098#else
2099 ensoniq->ctrl = 0;
2100 ensoniq->sctrl = 0;
2101 ensoniq->cssr = 0;
2102 if (snd_pci_quirk_lookup(pci, es1371_amplifier_hack))
2103 ensoniq->ctrl |= ES_1371_GPIO_OUT(1); /* turn amplifier on */
2104
2105 if (es1371_quirk_lookup(ensoniq, es1371_ac97_reset_hack))
2106 ensoniq->cssr |= ES_1371_ST_AC97_RST;
2107#endif
2108
2109 snd_ensoniq_chip_init(ensoniq);
2110
2111 err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, ensoniq, &ops);
2112 if (err < 0) {
2113 snd_ensoniq_free(ensoniq);
2114 return err;
2115 }
2116
2117 snd_ensoniq_proc_init(ensoniq);
2118
2119 *rensoniq = ensoniq;
2120 return 0;
2121}
2122
2123/*
2124 * MIDI section
2125 */
2126
2127static void snd_ensoniq_midi_interrupt(struct ensoniq * ensoniq)
2128{
2129 struct snd_rawmidi *rmidi = ensoniq->rmidi;
2130 unsigned char status, mask, byte;
2131
2132 if (rmidi == NULL)
2133 return;
2134 /* do Rx at first */
2135 spin_lock(&ensoniq->reg_lock);
2136 mask = ensoniq->uartm & ES_MODE_INPUT ? ES_RXRDY : 0;
2137 while (mask) {
2138 status = inb(ES_REG(ensoniq, UART_STATUS));
2139 if ((status & mask) == 0)
2140 break;
2141 byte = inb(ES_REG(ensoniq, UART_DATA));
2142 snd_rawmidi_receive(ensoniq->midi_input, &byte, 1);
2143 }
2144 spin_unlock(&ensoniq->reg_lock);
2145
2146 /* do Tx at second */
2147 spin_lock(&ensoniq->reg_lock);
2148 mask = ensoniq->uartm & ES_MODE_OUTPUT ? ES_TXRDY : 0;
2149 while (mask) {
2150 status = inb(ES_REG(ensoniq, UART_STATUS));
2151 if ((status & mask) == 0)
2152 break;
2153 if (snd_rawmidi_transmit(ensoniq->midi_output, &byte, 1) != 1) {
2154 ensoniq->uartc &= ~ES_TXINTENM;
2155 outb(ensoniq->uartc, ES_REG(ensoniq, UART_CONTROL));
2156 mask &= ~ES_TXRDY;
2157 } else {
2158 outb(byte, ES_REG(ensoniq, UART_DATA));
2159 }
2160 }
2161 spin_unlock(&ensoniq->reg_lock);
2162}
2163
2164static int snd_ensoniq_midi_input_open(struct snd_rawmidi_substream *substream)
2165{
2166 struct ensoniq *ensoniq = substream->rmidi->private_data;
2167
2168 spin_lock_irq(&ensoniq->reg_lock);
2169 ensoniq->uartm |= ES_MODE_INPUT;
2170 ensoniq->midi_input = substream;
2171 if (!(ensoniq->uartm & ES_MODE_OUTPUT)) {
2172 outb(ES_CNTRL(3), ES_REG(ensoniq, UART_CONTROL));
2173 outb(ensoniq->uartc = 0, ES_REG(ensoniq, UART_CONTROL));
2174 outl(ensoniq->ctrl |= ES_UART_EN, ES_REG(ensoniq, CONTROL));
2175 }
2176 spin_unlock_irq(&ensoniq->reg_lock);
2177 return 0;
2178}
2179
2180static int snd_ensoniq_midi_input_close(struct snd_rawmidi_substream *substream)
2181{
2182 struct ensoniq *ensoniq = substream->rmidi->private_data;
2183
2184 spin_lock_irq(&ensoniq->reg_lock);
2185 if (!(ensoniq->uartm & ES_MODE_OUTPUT)) {
2186 outb(ensoniq->uartc = 0, ES_REG(ensoniq, UART_CONTROL));
2187 outl(ensoniq->ctrl &= ~ES_UART_EN, ES_REG(ensoniq, CONTROL));
2188 } else {
2189 outb(ensoniq->uartc &= ~ES_RXINTEN, ES_REG(ensoniq, UART_CONTROL));
2190 }
2191 ensoniq->midi_input = NULL;
2192 ensoniq->uartm &= ~ES_MODE_INPUT;
2193 spin_unlock_irq(&ensoniq->reg_lock);
2194 return 0;
2195}
2196
2197static int snd_ensoniq_midi_output_open(struct snd_rawmidi_substream *substream)
2198{
2199 struct ensoniq *ensoniq = substream->rmidi->private_data;
2200
2201 spin_lock_irq(&ensoniq->reg_lock);
2202 ensoniq->uartm |= ES_MODE_OUTPUT;
2203 ensoniq->midi_output = substream;
2204 if (!(ensoniq->uartm & ES_MODE_INPUT)) {
2205 outb(ES_CNTRL(3), ES_REG(ensoniq, UART_CONTROL));
2206 outb(ensoniq->uartc = 0, ES_REG(ensoniq, UART_CONTROL));
2207 outl(ensoniq->ctrl |= ES_UART_EN, ES_REG(ensoniq, CONTROL));
2208 }
2209 spin_unlock_irq(&ensoniq->reg_lock);
2210 return 0;
2211}
2212
2213static int snd_ensoniq_midi_output_close(struct snd_rawmidi_substream *substream)
2214{
2215 struct ensoniq *ensoniq = substream->rmidi->private_data;
2216
2217 spin_lock_irq(&ensoniq->reg_lock);
2218 if (!(ensoniq->uartm & ES_MODE_INPUT)) {
2219 outb(ensoniq->uartc = 0, ES_REG(ensoniq, UART_CONTROL));
2220 outl(ensoniq->ctrl &= ~ES_UART_EN, ES_REG(ensoniq, CONTROL));
2221 } else {
2222 outb(ensoniq->uartc &= ~ES_TXINTENM, ES_REG(ensoniq, UART_CONTROL));
2223 }
2224 ensoniq->midi_output = NULL;
2225 ensoniq->uartm &= ~ES_MODE_OUTPUT;
2226 spin_unlock_irq(&ensoniq->reg_lock);
2227 return 0;
2228}
2229
2230static void snd_ensoniq_midi_input_trigger(struct snd_rawmidi_substream *substream, int up)
2231{
2232 unsigned long flags;
2233 struct ensoniq *ensoniq = substream->rmidi->private_data;
2234 int idx;
2235
2236 spin_lock_irqsave(&ensoniq->reg_lock, flags);
2237 if (up) {
2238 if ((ensoniq->uartc & ES_RXINTEN) == 0) {
2239 /* empty input FIFO */
2240 for (idx = 0; idx < 32; idx++)
2241 inb(ES_REG(ensoniq, UART_DATA));
2242 ensoniq->uartc |= ES_RXINTEN;
2243 outb(ensoniq->uartc, ES_REG(ensoniq, UART_CONTROL));
2244 }
2245 } else {
2246 if (ensoniq->uartc & ES_RXINTEN) {
2247 ensoniq->uartc &= ~ES_RXINTEN;
2248 outb(ensoniq->uartc, ES_REG(ensoniq, UART_CONTROL));
2249 }
2250 }
2251 spin_unlock_irqrestore(&ensoniq->reg_lock, flags);
2252}
2253
2254static void snd_ensoniq_midi_output_trigger(struct snd_rawmidi_substream *substream, int up)
2255{
2256 unsigned long flags;
2257 struct ensoniq *ensoniq = substream->rmidi->private_data;
2258 unsigned char byte;
2259
2260 spin_lock_irqsave(&ensoniq->reg_lock, flags);
2261 if (up) {
2262 if (ES_TXINTENI(ensoniq->uartc) == 0) {
2263 ensoniq->uartc |= ES_TXINTENO(1);
2264 /* fill UART FIFO buffer at first, and turn Tx interrupts only if necessary */
2265 while (ES_TXINTENI(ensoniq->uartc) == 1 &&
2266 (inb(ES_REG(ensoniq, UART_STATUS)) & ES_TXRDY)) {
2267 if (snd_rawmidi_transmit(substream, &byte, 1) != 1) {
2268 ensoniq->uartc &= ~ES_TXINTENM;
2269 } else {
2270 outb(byte, ES_REG(ensoniq, UART_DATA));
2271 }
2272 }
2273 outb(ensoniq->uartc, ES_REG(ensoniq, UART_CONTROL));
2274 }
2275 } else {
2276 if (ES_TXINTENI(ensoniq->uartc) == 1) {
2277 ensoniq->uartc &= ~ES_TXINTENM;
2278 outb(ensoniq->uartc, ES_REG(ensoniq, UART_CONTROL));
2279 }
2280 }
2281 spin_unlock_irqrestore(&ensoniq->reg_lock, flags);
2282}
2283
2284static const struct snd_rawmidi_ops snd_ensoniq_midi_output =
2285{
2286 .open = snd_ensoniq_midi_output_open,
2287 .close = snd_ensoniq_midi_output_close,
2288 .trigger = snd_ensoniq_midi_output_trigger,
2289};
2290
2291static const struct snd_rawmidi_ops snd_ensoniq_midi_input =
2292{
2293 .open = snd_ensoniq_midi_input_open,
2294 .close = snd_ensoniq_midi_input_close,
2295 .trigger = snd_ensoniq_midi_input_trigger,
2296};
2297
2298static int snd_ensoniq_midi(struct ensoniq *ensoniq, int device)
2299{
2300 struct snd_rawmidi *rmidi;
2301 int err;
2302
2303 err = snd_rawmidi_new(ensoniq->card, "ES1370/1", device, 1, 1, &rmidi);
2304 if (err < 0)
2305 return err;
2306 strcpy(rmidi->name, CHIP_NAME);
2307 snd_rawmidi_set_ops(rmidi, SNDRV_RAWMIDI_STREAM_OUTPUT, &snd_ensoniq_midi_output);
2308 snd_rawmidi_set_ops(rmidi, SNDRV_RAWMIDI_STREAM_INPUT, &snd_ensoniq_midi_input);
2309 rmidi->info_flags |= SNDRV_RAWMIDI_INFO_OUTPUT | SNDRV_RAWMIDI_INFO_INPUT |
2310 SNDRV_RAWMIDI_INFO_DUPLEX;
2311 rmidi->private_data = ensoniq;
2312 ensoniq->rmidi = rmidi;
2313 return 0;
2314}
2315
2316/*
2317 * Interrupt handler
2318 */
2319
2320static irqreturn_t snd_audiopci_interrupt(int irq, void *dev_id)
2321{
2322 struct ensoniq *ensoniq = dev_id;
2323 unsigned int status, sctrl;
2324
2325 if (ensoniq == NULL)
2326 return IRQ_NONE;
2327
2328 status = inl(ES_REG(ensoniq, STATUS));
2329 if (!(status & ES_INTR))
2330 return IRQ_NONE;
2331
2332 spin_lock(&ensoniq->reg_lock);
2333 sctrl = ensoniq->sctrl;
2334 if (status & ES_DAC1)
2335 sctrl &= ~ES_P1_INT_EN;
2336 if (status & ES_DAC2)
2337 sctrl &= ~ES_P2_INT_EN;
2338 if (status & ES_ADC)
2339 sctrl &= ~ES_R1_INT_EN;
2340 outl(sctrl, ES_REG(ensoniq, SERIAL));
2341 outl(ensoniq->sctrl, ES_REG(ensoniq, SERIAL));
2342 spin_unlock(&ensoniq->reg_lock);
2343
2344 if (status & ES_UART)
2345 snd_ensoniq_midi_interrupt(ensoniq);
2346 if ((status & ES_DAC2) && ensoniq->playback2_substream)
2347 snd_pcm_period_elapsed(ensoniq->playback2_substream);
2348 if ((status & ES_ADC) && ensoniq->capture_substream)
2349 snd_pcm_period_elapsed(ensoniq->capture_substream);
2350 if ((status & ES_DAC1) && ensoniq->playback1_substream)
2351 snd_pcm_period_elapsed(ensoniq->playback1_substream);
2352 return IRQ_HANDLED;
2353}
2354
2355static int snd_audiopci_probe(struct pci_dev *pci,
2356 const struct pci_device_id *pci_id)
2357{
2358 static int dev;
2359 struct snd_card *card;
2360 struct ensoniq *ensoniq;
2361 int err;
2362
2363 if (dev >= SNDRV_CARDS)
2364 return -ENODEV;
2365 if (!enable[dev]) {
2366 dev++;
2367 return -ENOENT;
2368 }
2369
2370 err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE,
2371 0, &card);
2372 if (err < 0)
2373 return err;
2374
2375 err = snd_ensoniq_create(card, pci, &ensoniq);
2376 if (err < 0) {
2377 snd_card_free(card);
2378 return err;
2379 }
2380 card->private_data = ensoniq;
2381
2382#ifdef CHIP1370
2383 err = snd_ensoniq_1370_mixer(ensoniq);
2384 if (err < 0) {
2385 snd_card_free(card);
2386 return err;
2387 }
2388#endif
2389#ifdef CHIP1371
2390 err = snd_ensoniq_1371_mixer(ensoniq, spdif[dev], lineio[dev]);
2391 if (err < 0) {
2392 snd_card_free(card);
2393 return err;
2394 }
2395#endif
2396 err = snd_ensoniq_pcm(ensoniq, 0);
2397 if (err < 0) {
2398 snd_card_free(card);
2399 return err;
2400 }
2401 err = snd_ensoniq_pcm2(ensoniq, 1);
2402 if (err < 0) {
2403 snd_card_free(card);
2404 return err;
2405 }
2406 err = snd_ensoniq_midi(ensoniq, 0);
2407 if (err < 0) {
2408 snd_card_free(card);
2409 return err;
2410 }
2411
2412 snd_ensoniq_create_gameport(ensoniq, dev);
2413
2414 strcpy(card->driver, DRIVER_NAME);
2415
2416 strcpy(card->shortname, "Ensoniq AudioPCI");
2417 sprintf(card->longname, "%s %s at 0x%lx, irq %i",
2418 card->shortname,
2419 card->driver,
2420 ensoniq->port,
2421 ensoniq->irq);
2422
2423 err = snd_card_register(card);
2424 if (err < 0) {
2425 snd_card_free(card);
2426 return err;
2427 }
2428
2429 pci_set_drvdata(pci, card);
2430 dev++;
2431 return 0;
2432}
2433
2434static void snd_audiopci_remove(struct pci_dev *pci)
2435{
2436 snd_card_free(pci_get_drvdata(pci));
2437}
2438
2439static struct pci_driver ens137x_driver = {
2440 .name = KBUILD_MODNAME,
2441 .id_table = snd_audiopci_ids,
2442 .probe = snd_audiopci_probe,
2443 .remove = snd_audiopci_remove,
2444 .driver = {
2445 .pm = SND_ENSONIQ_PM_OPS,
2446 },
2447};
2448
2449module_pci_driver(ens137x_driver);
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