source: GPL/trunk/alsa-kernel/pci/ens1370.c@ 695

Last change on this file since 695 was 695, checked in by David Azarewicz, 4 years ago

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1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Driver for Ensoniq ES1370/ES1371 AudioPCI soundcard
4 * Copyright (c) by Jaroslav Kysela <perex@perex.cz>,
5 * Thomas Sailer <sailer@ife.ee.ethz.ch>
6 */
7
8/* Power-Management-Code ( CONFIG_PM )
9 * for ens1371 only ( FIXME )
10 * derived from cs4281.c, atiixp.c and via82xx.c
11 * using http://www.alsa-project.org/~tiwai/writing-an-alsa-driver/
12 * by Kurt J. Bosch
13 */
14
15#include <linux/io.h>
16#include <linux/delay.h>
17#include <linux/interrupt.h>
18#include <linux/init.h>
19#include <linux/pci.h>
20#include <linux/slab.h>
21#include <linux/gameport.h>
22#include <linux/module.h>
23#include <linux/mutex.h>
24
25#include <sound/core.h>
26#include <sound/control.h>
27#include <sound/pcm.h>
28#include <sound/rawmidi.h>
29#ifdef CHIP1371
30#include <sound/ac97_codec.h>
31#else
32#include <sound/ak4531_codec.h>
33#endif
34#include <sound/initval.h>
35#include <sound/asoundef.h>
36
37#ifndef CHIP1371
38#undef CHIP1370
39#define CHIP1370
40#endif
41
42#ifdef CHIP1370
43#define DRIVER_NAME "ENS1370"
44#define CHIP_NAME "ES1370" /* it can be ENS but just to keep compatibility... */
45#else
46#define DRIVER_NAME "ENS1371"
47#define CHIP_NAME "ES1371"
48#endif
49
50
51#ifdef TARGET_OS2
52#define KBUILD_MODNAME "ens137x"
53#endif
54MODULE_AUTHOR("Jaroslav Kysela <perex@perex.cz>, Thomas Sailer <sailer@ife.ee.ethz.ch>");
55MODULE_LICENSE("GPL");
56#ifdef CHIP1370
57MODULE_DESCRIPTION("Ensoniq AudioPCI ES1370");
58#endif
59#ifdef CHIP1371
60MODULE_DESCRIPTION("Ensoniq/Creative AudioPCI ES1371+");
61#endif
62
63#if IS_REACHABLE(CONFIG_GAMEPORT)
64#define SUPPORT_JOYSTICK
65#endif
66
67static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
68static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
69static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable switches */
70#ifdef SUPPORT_JOYSTICK
71#ifdef CHIP1371
72static int joystick_port[SNDRV_CARDS];
73#else
74static bool joystick[SNDRV_CARDS];
75#endif
76#endif
77#ifdef CHIP1371
78static int spdif[SNDRV_CARDS];
79static int lineio[SNDRV_CARDS];
80#endif
81
82module_param_array(index, int, NULL, 0444);
83MODULE_PARM_DESC(index, "Index value for Ensoniq AudioPCI soundcard.");
84module_param_array(id, charp, NULL, 0444);
85MODULE_PARM_DESC(id, "ID string for Ensoniq AudioPCI soundcard.");
86module_param_array(enable, bool, NULL, 0444);
87MODULE_PARM_DESC(enable, "Enable Ensoniq AudioPCI soundcard.");
88#ifdef SUPPORT_JOYSTICK
89#ifdef CHIP1371
90module_param_hw_array(joystick_port, int, ioport, NULL, 0444);
91MODULE_PARM_DESC(joystick_port, "Joystick port address.");
92#else
93module_param_array(joystick, bool, NULL, 0444);
94MODULE_PARM_DESC(joystick, "Enable joystick.");
95#endif
96#endif /* SUPPORT_JOYSTICK */
97#ifdef CHIP1371
98module_param_array(spdif, int, NULL, 0444);
99MODULE_PARM_DESC(spdif, "S/PDIF output (-1 = none, 0 = auto, 1 = force).");
100module_param_array(lineio, int, NULL, 0444);
101MODULE_PARM_DESC(lineio, "Line In to Rear Out (0 = auto, 1 = force).");
102#endif
103
104/* ES1371 chip ID */
105/* This is a little confusing because all ES1371 compatible chips have the
106 same DEVICE_ID, the only thing differentiating them is the REV_ID field.
107 This is only significant if you want to enable features on the later parts.
108 Yes, I know it's stupid and why didn't we use the sub IDs?
109*/
110#define ES1371REV_ES1373_A 0x04
111#define ES1371REV_ES1373_B 0x06
112#define ES1371REV_CT5880_A 0x07
113#define CT5880REV_CT5880_C 0x02
114#define CT5880REV_CT5880_D 0x03 /* ??? -jk */
115#define CT5880REV_CT5880_E 0x04 /* mw */
116#define ES1371REV_ES1371_B 0x09
117#define EV1938REV_EV1938_A 0x00
118#define ES1371REV_ES1373_8 0x08
119
120/*
121 * Direct registers
122 */
123
124#define ES_REG(ensoniq, x) ((ensoniq)->port + ES_REG_##x)
125
126#define ES_REG_CONTROL 0x00 /* R/W: Interrupt/Chip select control register */
127#define ES_1370_ADC_STOP (1<<31) /* disable capture buffer transfers */
128#define ES_1370_XCTL1 (1<<30) /* general purpose output bit */
129#define ES_1373_BYPASS_P1 (1<<31) /* bypass SRC for PB1 */
130#define ES_1373_BYPASS_P2 (1<<30) /* bypass SRC for PB2 */
131#define ES_1373_BYPASS_R (1<<29) /* bypass SRC for REC */
132#define ES_1373_TEST_BIT (1<<28) /* should be set to 0 for normal operation */
133#define ES_1373_RECEN_B (1<<27) /* mix record with playback for I2S/SPDIF out */
134#define ES_1373_SPDIF_THRU (1<<26) /* 0 = SPDIF thru mode, 1 = SPDIF == dig out */
135#define ES_1371_JOY_ASEL(o) (((o)&0x03)<<24)/* joystick port mapping */
136#define ES_1371_JOY_ASELM (0x03<<24) /* mask for above */
137#define ES_1371_JOY_ASELI(i) (((i)>>24)&0x03)
138#define ES_1371_GPIO_IN(i) (((i)>>20)&0x0f)/* GPIO in [3:0] pins - R/O */
139#define ES_1370_PCLKDIVO(o) (((o)&0x1fff)<<16)/* clock divide ratio for DAC2 */
140#define ES_1370_PCLKDIVM ((0x1fff)<<16) /* mask for above */
141#define ES_1370_PCLKDIVI(i) (((i)>>16)&0x1fff)/* clock divide ratio for DAC2 */
142#define ES_1371_GPIO_OUT(o) (((o)&0x0f)<<16)/* GPIO out [3:0] pins - W/R */
143#define ES_1371_GPIO_OUTM (0x0f<<16) /* mask for above */
144#define ES_MSFMTSEL (1<<15) /* MPEG serial data format; 0 = SONY, 1 = I2S */
145#define ES_1370_M_SBB (1<<14) /* clock source for DAC - 0 = clock generator; 1 = MPEG clocks */
146#define ES_1371_SYNC_RES (1<<14) /* Warm AC97 reset */
147#define ES_1370_WTSRSEL(o) (((o)&0x03)<<12)/* fixed frequency clock for DAC1 */
148#define ES_1370_WTSRSELM (0x03<<12) /* mask for above */
149#define ES_1371_ADC_STOP (1<<13) /* disable CCB transfer capture information */
150#define ES_1371_PWR_INTRM (1<<12) /* power level change interrupts enable */
151#define ES_1370_DAC_SYNC (1<<11) /* DAC's are synchronous */
152#define ES_1371_M_CB (1<<11) /* capture clock source; 0 = AC'97 ADC; 1 = I2S */
153#define ES_CCB_INTRM (1<<10) /* CCB voice interrupts enable */
154#define ES_1370_M_CB (1<<9) /* capture clock source; 0 = ADC; 1 = MPEG */
155#define ES_1370_XCTL0 (1<<8) /* generap purpose output bit */
156#define ES_1371_PDLEV(o) (((o)&0x03)<<8) /* current power down level */
157#define ES_1371_PDLEVM (0x03<<8) /* mask for above */
158#define ES_BREQ (1<<7) /* memory bus request enable */
159#define ES_DAC1_EN (1<<6) /* DAC1 playback channel enable */
160#define ES_DAC2_EN (1<<5) /* DAC2 playback channel enable */
161#define ES_ADC_EN (1<<4) /* ADC capture channel enable */
162#define ES_UART_EN (1<<3) /* UART enable */
163#define ES_JYSTK_EN (1<<2) /* Joystick module enable */
164#define ES_1370_CDC_EN (1<<1) /* Codec interface enable */
165#define ES_1371_XTALCKDIS (1<<1) /* Xtal clock disable */
166#define ES_1370_SERR_DISABLE (1<<0) /* PCI serr signal disable */
167#define ES_1371_PCICLKDIS (1<<0) /* PCI clock disable */
168#define ES_REG_STATUS 0x04 /* R/O: Interrupt/Chip select status register */
169#define ES_INTR (1<<31) /* Interrupt is pending */
170#define ES_1371_ST_AC97_RST (1<<29) /* CT5880 AC'97 Reset bit */
171#define ES_1373_REAR_BIT27 (1<<27) /* rear bits: 000 - front, 010 - mirror, 101 - separate */
172#define ES_1373_REAR_BIT26 (1<<26)
173#define ES_1373_REAR_BIT24 (1<<24)
174#define ES_1373_GPIO_INT_EN(o)(((o)&0x0f)<<20)/* GPIO [3:0] pins - interrupt enable */
175#define ES_1373_SPDIF_EN (1<<18) /* SPDIF enable */
176#define ES_1373_SPDIF_TEST (1<<17) /* SPDIF test */
177#define ES_1371_TEST (1<<16) /* test ASIC */
178#define ES_1373_GPIO_INT(i) (((i)&0x0f)>>12)/* GPIO [3:0] pins - interrupt pending */
179#define ES_1370_CSTAT (1<<10) /* CODEC is busy or register write in progress */
180#define ES_1370_CBUSY (1<<9) /* CODEC is busy */
181#define ES_1370_CWRIP (1<<8) /* CODEC register write in progress */
182#define ES_1371_SYNC_ERR (1<<8) /* CODEC synchronization error occurred */
183#define ES_1371_VC(i) (((i)>>6)&0x03) /* voice code from CCB module */
184#define ES_1370_VC(i) (((i)>>5)&0x03) /* voice code from CCB module */
185#define ES_1371_MPWR (1<<5) /* power level interrupt pending */
186#define ES_MCCB (1<<4) /* CCB interrupt pending */
187#define ES_UART (1<<3) /* UART interrupt pending */
188#define ES_DAC1 (1<<2) /* DAC1 channel interrupt pending */
189#define ES_DAC2 (1<<1) /* DAC2 channel interrupt pending */
190#define ES_ADC (1<<0) /* ADC channel interrupt pending */
191#define ES_REG_UART_DATA 0x08 /* R/W: UART data register */
192#define ES_REG_UART_STATUS 0x09 /* R/O: UART status register */
193#define ES_RXINT (1<<7) /* RX interrupt occurred */
194#define ES_TXINT (1<<2) /* TX interrupt occurred */
195#define ES_TXRDY (1<<1) /* transmitter ready */
196#define ES_RXRDY (1<<0) /* receiver ready */
197#define ES_REG_UART_CONTROL 0x09 /* W/O: UART control register */
198#define ES_RXINTEN (1<<7) /* RX interrupt enable */
199#define ES_TXINTENO(o) (((o)&0x03)<<5) /* TX interrupt enable */
200#define ES_TXINTENM (0x03<<5) /* mask for above */
201#define ES_TXINTENI(i) (((i)>>5)&0x03)
202#define ES_CNTRL(o) (((o)&0x03)<<0) /* control */
203#define ES_CNTRLM (0x03<<0) /* mask for above */
204#define ES_REG_UART_RES 0x0a /* R/W: UART reserver register */
205#define ES_TEST_MODE (1<<0) /* test mode enabled */
206#define ES_REG_MEM_PAGE 0x0c /* R/W: Memory page register */
207#define ES_MEM_PAGEO(o) (((o)&0x0f)<<0) /* memory page select - out */
208#define ES_MEM_PAGEM (0x0f<<0) /* mask for above */
209#define ES_MEM_PAGEI(i) (((i)>>0)&0x0f) /* memory page select - in */
210#define ES_REG_1370_CODEC 0x10 /* W/O: Codec write register address */
211#define ES_1370_CODEC_WRITE(a,d) ((((a)&0xff)<<8)|(((d)&0xff)<<0))
212#define ES_REG_1371_CODEC 0x14 /* W/R: Codec Read/Write register address */
213#define ES_1371_CODEC_RDY (1<<31) /* codec ready */
214#define ES_1371_CODEC_WIP (1<<30) /* codec register access in progress */
215#define EV_1938_CODEC_MAGIC (1<<26)
216#define ES_1371_CODEC_PIRD (1<<23) /* codec read/write select register */
217#define ES_1371_CODEC_WRITE(a,d) ((((a)&0x7f)<<16)|(((d)&0xffff)<<0))
218#define ES_1371_CODEC_READS(a) ((((a)&0x7f)<<16)|ES_1371_CODEC_PIRD)
219#define ES_1371_CODEC_READ(i) (((i)>>0)&0xffff)
220
221#define ES_REG_1371_SMPRATE 0x10 /* W/R: Codec rate converter interface register */
222#define ES_1371_SRC_RAM_ADDRO(o) (((o)&0x7f)<<25)/* address of the sample rate converter */
223#define ES_1371_SRC_RAM_ADDRM (0x7f<<25) /* mask for above */
224#define ES_1371_SRC_RAM_ADDRI(i) (((i)>>25)&0x7f)/* address of the sample rate converter */
225#define ES_1371_SRC_RAM_WE (1<<24) /* R/W: read/write control for sample rate converter */
226#define ES_1371_SRC_RAM_BUSY (1<<23) /* R/O: sample rate memory is busy */
227#define ES_1371_SRC_DISABLE (1<<22) /* sample rate converter disable */
228#define ES_1371_DIS_P1 (1<<21) /* playback channel 1 accumulator update disable */
229#define ES_1371_DIS_P2 (1<<20) /* playback channel 1 accumulator update disable */
230#define ES_1371_DIS_R1 (1<<19) /* capture channel accumulator update disable */
231#define ES_1371_SRC_RAM_DATAO(o) (((o)&0xffff)<<0)/* current value of the sample rate converter */
232#define ES_1371_SRC_RAM_DATAM (0xffff<<0) /* mask for above */
233#define ES_1371_SRC_RAM_DATAI(i) (((i)>>0)&0xffff)/* current value of the sample rate converter */
234
235#define ES_REG_1371_LEGACY 0x18 /* W/R: Legacy control/status register */
236#define ES_1371_JFAST (1<<31) /* fast joystick timing */
237#define ES_1371_HIB (1<<30) /* host interrupt blocking enable */
238#define ES_1371_VSB (1<<29) /* SB; 0 = addr 0x220xH, 1 = 0x22FxH */
239#define ES_1371_VMPUO(o) (((o)&0x03)<<27)/* base register address; 0 = 0x320xH; 1 = 0x330xH; 2 = 0x340xH; 3 = 0x350xH */
240#define ES_1371_VMPUM (0x03<<27) /* mask for above */
241#define ES_1371_VMPUI(i) (((i)>>27)&0x03)/* base register address */
242#define ES_1371_VCDCO(o) (((o)&0x03)<<25)/* CODEC; 0 = 0x530xH; 1 = undefined; 2 = 0xe80xH; 3 = 0xF40xH */
243#define ES_1371_VCDCM (0x03<<25) /* mask for above */
244#define ES_1371_VCDCI(i) (((i)>>25)&0x03)/* CODEC address */
245#define ES_1371_FIRQ (1<<24) /* force an interrupt */
246#define ES_1371_SDMACAP (1<<23) /* enable event capture for slave DMA controller */
247#define ES_1371_SPICAP (1<<22) /* enable event capture for slave IRQ controller */
248#define ES_1371_MDMACAP (1<<21) /* enable event capture for master DMA controller */
249#define ES_1371_MPICAP (1<<20) /* enable event capture for master IRQ controller */
250#define ES_1371_ADCAP (1<<19) /* enable event capture for ADLIB register; 0x388xH */
251#define ES_1371_SVCAP (1<<18) /* enable event capture for SB registers */
252#define ES_1371_CDCCAP (1<<17) /* enable event capture for CODEC registers */
253#define ES_1371_BACAP (1<<16) /* enable event capture for SoundScape base address */
254#define ES_1371_EXI(i) (((i)>>8)&0x07) /* event number */
255#define ES_1371_AI(i) (((i)>>3)&0x1f) /* event significant I/O address */
256#define ES_1371_WR (1<<2) /* event capture; 0 = read; 1 = write */
257#define ES_1371_LEGINT (1<<0) /* interrupt for legacy events; 0 = interrupt did occur */
258
259#define ES_REG_CHANNEL_STATUS 0x1c /* R/W: first 32-bits from S/PDIF channel status block, es1373 */
260
261#define ES_REG_SERIAL 0x20 /* R/W: Serial interface control register */
262#define ES_1371_DAC_TEST (1<<22) /* DAC test mode enable */
263#define ES_P2_END_INCO(o) (((o)&0x07)<<19)/* binary offset value to increment / loop end */
264#define ES_P2_END_INCM (0x07<<19) /* mask for above */
265#define ES_P2_END_INCI(i) (((i)>>16)&0x07)/* binary offset value to increment / loop end */
266#define ES_P2_ST_INCO(o) (((o)&0x07)<<16)/* binary offset value to increment / start */
267#define ES_P2_ST_INCM (0x07<<16) /* mask for above */
268#define ES_P2_ST_INCI(i) (((i)<<16)&0x07)/* binary offset value to increment / start */
269#define ES_R1_LOOP_SEL (1<<15) /* ADC; 0 - loop mode; 1 = stop mode */
270#define ES_P2_LOOP_SEL (1<<14) /* DAC2; 0 - loop mode; 1 = stop mode */
271#define ES_P1_LOOP_SEL (1<<13) /* DAC1; 0 - loop mode; 1 = stop mode */
272#define ES_P2_PAUSE (1<<12) /* DAC2; 0 - play mode; 1 = pause mode */
273#define ES_P1_PAUSE (1<<11) /* DAC1; 0 - play mode; 1 = pause mode */
274#define ES_R1_INT_EN (1<<10) /* ADC interrupt enable */
275#define ES_P2_INT_EN (1<<9) /* DAC2 interrupt enable */
276#define ES_P1_INT_EN (1<<8) /* DAC1 interrupt enable */
277#define ES_P1_SCT_RLD (1<<7) /* force sample counter reload for DAC1 */
278#define ES_P2_DAC_SEN (1<<6) /* when stop mode: 0 - DAC2 play back zeros; 1 = DAC2 play back last sample */
279#define ES_R1_MODEO(o) (((o)&0x03)<<4) /* ADC mode; 0 = 8-bit mono; 1 = 8-bit stereo; 2 = 16-bit mono; 3 = 16-bit stereo */
280#define ES_R1_MODEM (0x03<<4) /* mask for above */
281#define ES_R1_MODEI(i) (((i)>>4)&0x03)
282#define ES_P2_MODEO(o) (((o)&0x03)<<2) /* DAC2 mode; -- '' -- */
283#define ES_P2_MODEM (0x03<<2) /* mask for above */
284#define ES_P2_MODEI(i) (((i)>>2)&0x03)
285#define ES_P1_MODEO(o) (((o)&0x03)<<0) /* DAC1 mode; -- '' -- */
286#define ES_P1_MODEM (0x03<<0) /* mask for above */
287#define ES_P1_MODEI(i) (((i)>>0)&0x03)
288
289#define ES_REG_DAC1_COUNT 0x24 /* R/W: DAC1 sample count register */
290#define ES_REG_DAC2_COUNT 0x28 /* R/W: DAC2 sample count register */
291#define ES_REG_ADC_COUNT 0x2c /* R/W: ADC sample count register */
292#define ES_REG_CURR_COUNT(i) (((i)>>16)&0xffff)
293#define ES_REG_COUNTO(o) (((o)&0xffff)<<0)
294#define ES_REG_COUNTM (0xffff<<0)
295#define ES_REG_COUNTI(i) (((i)>>0)&0xffff)
296
297#define ES_REG_DAC1_FRAME 0x30 /* R/W: PAGE 0x0c; DAC1 frame address */
298#define ES_REG_DAC1_SIZE 0x34 /* R/W: PAGE 0x0c; DAC1 frame size */
299#define ES_REG_DAC2_FRAME 0x38 /* R/W: PAGE 0x0c; DAC2 frame address */
300#define ES_REG_DAC2_SIZE 0x3c /* R/W: PAGE 0x0c; DAC2 frame size */
301#define ES_REG_ADC_FRAME 0x30 /* R/W: PAGE 0x0d; ADC frame address */
302#define ES_REG_ADC_SIZE 0x34 /* R/W: PAGE 0x0d; ADC frame size */
303#define ES_REG_FCURR_COUNTO(o) (((o)&0xffff)<<16)
304#define ES_REG_FCURR_COUNTM (0xffff<<16)
305#define ES_REG_FCURR_COUNTI(i) (((i)>>14)&0x3fffc)
306#define ES_REG_FSIZEO(o) (((o)&0xffff)<<0)
307#define ES_REG_FSIZEM (0xffff<<0)
308#define ES_REG_FSIZEI(i) (((i)>>0)&0xffff)
309#define ES_REG_PHANTOM_FRAME 0x38 /* R/W: PAGE 0x0d: phantom frame address */
310#define ES_REG_PHANTOM_COUNT 0x3c /* R/W: PAGE 0x0d: phantom frame count */
311
312#define ES_REG_UART_FIFO 0x30 /* R/W: PAGE 0x0e; UART FIFO register */
313#define ES_REG_UF_VALID (1<<8)
314#define ES_REG_UF_BYTEO(o) (((o)&0xff)<<0)
315#define ES_REG_UF_BYTEM (0xff<<0)
316#define ES_REG_UF_BYTEI(i) (((i)>>0)&0xff)
317
318
319/*
320 * Pages
321 */
322
323#define ES_PAGE_DAC 0x0c
324#define ES_PAGE_ADC 0x0d
325#define ES_PAGE_UART 0x0e
326#define ES_PAGE_UART1 0x0f
327
328/*
329 * Sample rate converter addresses
330 */
331
332#define ES_SMPREG_DAC1 0x70
333#define ES_SMPREG_DAC2 0x74
334#define ES_SMPREG_ADC 0x78
335#define ES_SMPREG_VOL_ADC 0x6c
336#define ES_SMPREG_VOL_DAC1 0x7c
337#define ES_SMPREG_VOL_DAC2 0x7e
338#define ES_SMPREG_TRUNC_N 0x00
339#define ES_SMPREG_INT_REGS 0x01
340#define ES_SMPREG_ACCUM_FRAC 0x02
341#define ES_SMPREG_VFREQ_FRAC 0x03
342
343/*
344 * Some contants
345 */
346
347#define ES_1370_SRCLOCK 1411200
348#define ES_1370_SRTODIV(x) (ES_1370_SRCLOCK/(x)-2)
349
350/*
351 * Open modes
352 */
353
354#define ES_MODE_PLAY1 0x0001
355#define ES_MODE_PLAY2 0x0002
356#define ES_MODE_CAPTURE 0x0004
357
358#define ES_MODE_OUTPUT 0x0001 /* for MIDI */
359#define ES_MODE_INPUT 0x0002 /* for MIDI */
360
361/*
362
363 */
364
365struct ensoniq {
366 spinlock_t reg_lock;
367 struct mutex src_mutex;
368
369 int irq;
370
371 unsigned long playback1size;
372 unsigned long playback2size;
373 unsigned long capture3size;
374
375 unsigned long port;
376 unsigned int mode;
377 unsigned int uartm; /* UART mode */
378
379 unsigned int ctrl; /* control register */
380 unsigned int sctrl; /* serial control register */
381 unsigned int cssr; /* control status register */
382 unsigned int uartc; /* uart control register */
383 unsigned int rev; /* chip revision */
384
385 union {
386#ifdef CHIP1371
387 struct {
388 struct snd_ac97 *ac97;
389 } es1371;
390#else
391 struct {
392 int pclkdiv_lock;
393 struct snd_ak4531 *ak4531;
394 } es1370;
395#endif
396 } u;
397
398 struct pci_dev *pci;
399 struct snd_card *card;
400 struct snd_pcm *pcm1; /* DAC1/ADC PCM */
401 struct snd_pcm *pcm2; /* DAC2 PCM */
402 struct snd_pcm_substream *playback1_substream;
403 struct snd_pcm_substream *playback2_substream;
404 struct snd_pcm_substream *capture_substream;
405 unsigned int p1_dma_size;
406 unsigned int p2_dma_size;
407 unsigned int c_dma_size;
408 unsigned int p1_period_size;
409 unsigned int p2_period_size;
410 unsigned int c_period_size;
411 struct snd_rawmidi *rmidi;
412 struct snd_rawmidi_substream *midi_input;
413 struct snd_rawmidi_substream *midi_output;
414
415 unsigned int spdif;
416 unsigned int spdif_default;
417 unsigned int spdif_stream;
418
419#ifdef CHIP1370
420 struct snd_dma_buffer dma_bug;
421#endif
422
423#ifdef SUPPORT_JOYSTICK
424 struct gameport *gameport;
425#endif
426};
427
428static irqreturn_t snd_audiopci_interrupt(int irq, void *dev_id);
429
430static const struct pci_device_id snd_audiopci_ids[] = {
431#ifdef CHIP1370
432 { PCI_VDEVICE(ENSONIQ, 0x5000), 0, }, /* ES1370 */
433#endif
434#ifdef CHIP1371
435 { PCI_VDEVICE(ENSONIQ, 0x1371), 0, }, /* ES1371 */
436 { PCI_VDEVICE(ENSONIQ, 0x5880), 0, }, /* ES1373 - CT5880 */
437 { PCI_VDEVICE(ECTIVA, 0x8938), 0, }, /* Ectiva EV1938 */
438#endif
439 { 0, }
440};
441
442MODULE_DEVICE_TABLE(pci, snd_audiopci_ids);
443
444/*
445 * constants
446 */
447
448#define POLL_COUNT 0xa000
449
450#ifdef CHIP1370
451static const unsigned int snd_es1370_fixed_rates[] =
452 {5512, 11025, 22050, 44100};
453static const struct snd_pcm_hw_constraint_list snd_es1370_hw_constraints_rates = {
454 .count = 4,
455 .list = snd_es1370_fixed_rates,
456 .mask = 0,
457};
458static const struct snd_ratnum es1370_clock = {
459 .num = ES_1370_SRCLOCK,
460 .den_min = 29,
461 .den_max = 353,
462 .den_step = 1,
463};
464static const struct snd_pcm_hw_constraint_ratnums snd_es1370_hw_constraints_clock = {
465 .nrats = 1,
466 .rats = &es1370_clock,
467};
468#else
469static const struct snd_ratden es1371_dac_clock = {
470 .num_min = 3000 * (1 << 15),
471 .num_max = 48000 * (1 << 15),
472 .num_step = 3000,
473 .den = 1 << 15,
474};
475static const struct snd_pcm_hw_constraint_ratdens snd_es1371_hw_constraints_dac_clock = {
476 .nrats = 1,
477 .rats = &es1371_dac_clock,
478};
479static const struct snd_ratnum es1371_adc_clock = {
480 .num = 48000 << 15,
481 .den_min = 32768,
482 .den_max = 393216,
483 .den_step = 1,
484};
485static const struct snd_pcm_hw_constraint_ratnums snd_es1371_hw_constraints_adc_clock = {
486 .nrats = 1,
487 .rats = &es1371_adc_clock,
488};
489#endif
490static const unsigned int snd_ensoniq_sample_shift[] =
491 {0, 1, 1, 2};
492
493/*
494 * common I/O routines
495 */
496
497#ifdef CHIP1371
498
499static unsigned int snd_es1371_wait_src_ready(struct ensoniq * ensoniq)
500{
501 unsigned int t, r = 0;
502
503 for (t = 0; t < POLL_COUNT; t++) {
504 r = inl(ES_REG(ensoniq, 1371_SMPRATE));
505 if ((r & ES_1371_SRC_RAM_BUSY) == 0)
506 return r;
507 cond_resched();
508 }
509 dev_err(ensoniq->card->dev, "wait src ready timeout 0x%lx [0x%x]\n",
510 ES_REG(ensoniq, 1371_SMPRATE), r);
511 return 0;
512}
513
514static unsigned int snd_es1371_src_read(struct ensoniq * ensoniq, unsigned short reg)
515{
516 unsigned int temp, i, orig, r;
517
518 /* wait for ready */
519 temp = orig = snd_es1371_wait_src_ready(ensoniq);
520
521 /* expose the SRC state bits */
522 r = temp & (ES_1371_SRC_DISABLE | ES_1371_DIS_P1 |
523 ES_1371_DIS_P2 | ES_1371_DIS_R1);
524 r |= ES_1371_SRC_RAM_ADDRO(reg) | 0x10000;
525 outl(r, ES_REG(ensoniq, 1371_SMPRATE));
526
527 /* now, wait for busy and the correct time to read */
528 temp = snd_es1371_wait_src_ready(ensoniq);
529
530 if ((temp & 0x00870000) != 0x00010000) {
531 /* wait for the right state */
532 for (i = 0; i < POLL_COUNT; i++) {
533 temp = inl(ES_REG(ensoniq, 1371_SMPRATE));
534 if ((temp & 0x00870000) == 0x00010000)
535 break;
536 }
537 }
538
539 /* hide the state bits */
540 r = orig & (ES_1371_SRC_DISABLE | ES_1371_DIS_P1 |
541 ES_1371_DIS_P2 | ES_1371_DIS_R1);
542 r |= ES_1371_SRC_RAM_ADDRO(reg);
543 outl(r, ES_REG(ensoniq, 1371_SMPRATE));
544
545 return temp;
546}
547
548static void snd_es1371_src_write(struct ensoniq * ensoniq,
549 unsigned short reg, unsigned short data)
550{
551 unsigned int r;
552
553 r = snd_es1371_wait_src_ready(ensoniq) &
554 (ES_1371_SRC_DISABLE | ES_1371_DIS_P1 |
555 ES_1371_DIS_P2 | ES_1371_DIS_R1);
556 r |= ES_1371_SRC_RAM_ADDRO(reg) | ES_1371_SRC_RAM_DATAO(data);
557 outl(r | ES_1371_SRC_RAM_WE, ES_REG(ensoniq, 1371_SMPRATE));
558}
559
560#endif /* CHIP1371 */
561
562#ifdef CHIP1370
563
564static void snd_es1370_codec_write(struct snd_ak4531 *ak4531,
565 unsigned short reg, unsigned short val)
566{
567 struct ensoniq *ensoniq = ak4531->private_data;
568 unsigned long end_time = jiffies + HZ / 10;
569
570#if 0
571 dev_dbg(ensoniq->card->dev,
572 "CODEC WRITE: reg = 0x%x, val = 0x%x (0x%x), creg = 0x%x\n",
573 reg, val, ES_1370_CODEC_WRITE(reg, val), ES_REG(ensoniq, 1370_CODEC));
574#endif
575 do {
576 if (!(inl(ES_REG(ensoniq, STATUS)) & ES_1370_CSTAT)) {
577 outw(ES_1370_CODEC_WRITE(reg, val), ES_REG(ensoniq, 1370_CODEC));
578 return;
579 }
580 schedule_timeout_uninterruptible(1);
581 } while (time_after(end_time, jiffies));
582 dev_err(ensoniq->card->dev, "codec write timeout, status = 0x%x\n",
583 inl(ES_REG(ensoniq, STATUS)));
584}
585
586#endif /* CHIP1370 */
587
588#ifdef CHIP1371
589
590static inline bool is_ev1938(struct ensoniq *ensoniq)
591{
592 return ensoniq->pci->device == 0x8938;
593}
594
595static void snd_es1371_codec_write(struct snd_ac97 *ac97,
596 unsigned short reg, unsigned short val)
597{
598 struct ensoniq *ensoniq = ac97->private_data;
599 unsigned int t, x, flag;
600
601 flag = is_ev1938(ensoniq) ? EV_1938_CODEC_MAGIC : 0;
602 mutex_lock(&ensoniq->src_mutex);
603 for (t = 0; t < POLL_COUNT; t++) {
604 if (!(inl(ES_REG(ensoniq, 1371_CODEC)) & ES_1371_CODEC_WIP)) {
605 /* save the current state for latter */
606 x = snd_es1371_wait_src_ready(ensoniq);
607 outl((x & (ES_1371_SRC_DISABLE | ES_1371_DIS_P1 |
608 ES_1371_DIS_P2 | ES_1371_DIS_R1)) | 0x00010000,
609 ES_REG(ensoniq, 1371_SMPRATE));
610 /* wait for not busy (state 0) first to avoid
611 transition states */
612 for (t = 0; t < POLL_COUNT; t++) {
613 if ((inl(ES_REG(ensoniq, 1371_SMPRATE)) & 0x00870000) ==
614 0x00000000)
615 break;
616 }
617 /* wait for a SAFE time to write addr/data and then do it, dammit */
618 for (t = 0; t < POLL_COUNT; t++) {
619 if ((inl(ES_REG(ensoniq, 1371_SMPRATE)) & 0x00870000) ==
620 0x00010000)
621 break;
622 }
623 outl(ES_1371_CODEC_WRITE(reg, val) | flag,
624 ES_REG(ensoniq, 1371_CODEC));
625 /* restore SRC reg */
626 snd_es1371_wait_src_ready(ensoniq);
627 outl(x, ES_REG(ensoniq, 1371_SMPRATE));
628 mutex_unlock(&ensoniq->src_mutex);
629 return;
630 }
631 }
632 mutex_unlock(&ensoniq->src_mutex);
633 dev_err(ensoniq->card->dev, "codec write timeout at 0x%lx [0x%x]\n",
634 ES_REG(ensoniq, 1371_CODEC), inl(ES_REG(ensoniq, 1371_CODEC)));
635}
636
637static unsigned short snd_es1371_codec_read(struct snd_ac97 *ac97,
638 unsigned short reg)
639{
640 struct ensoniq *ensoniq = ac97->private_data;
641 unsigned int t, x, flag, fail = 0;
642
643 flag = is_ev1938(ensoniq) ? EV_1938_CODEC_MAGIC : 0;
644 __again:
645 mutex_lock(&ensoniq->src_mutex);
646 for (t = 0; t < POLL_COUNT; t++) {
647 if (!(inl(ES_REG(ensoniq, 1371_CODEC)) & ES_1371_CODEC_WIP)) {
648 /* save the current state for latter */
649 x = snd_es1371_wait_src_ready(ensoniq);
650 outl((x & (ES_1371_SRC_DISABLE | ES_1371_DIS_P1 |
651 ES_1371_DIS_P2 | ES_1371_DIS_R1)) | 0x00010000,
652 ES_REG(ensoniq, 1371_SMPRATE));
653 /* wait for not busy (state 0) first to avoid
654 transition states */
655 for (t = 0; t < POLL_COUNT; t++) {
656 if ((inl(ES_REG(ensoniq, 1371_SMPRATE)) & 0x00870000) ==
657 0x00000000)
658 break;
659 }
660 /* wait for a SAFE time to write addr/data and then do it, dammit */
661 for (t = 0; t < POLL_COUNT; t++) {
662 if ((inl(ES_REG(ensoniq, 1371_SMPRATE)) & 0x00870000) ==
663 0x00010000)
664 break;
665 }
666 outl(ES_1371_CODEC_READS(reg) | flag,
667 ES_REG(ensoniq, 1371_CODEC));
668 /* restore SRC reg */
669 snd_es1371_wait_src_ready(ensoniq);
670 outl(x, ES_REG(ensoniq, 1371_SMPRATE));
671 /* wait for WIP again */
672 for (t = 0; t < POLL_COUNT; t++) {
673 if (!(inl(ES_REG(ensoniq, 1371_CODEC)) & ES_1371_CODEC_WIP))
674 break;
675 }
676 /* now wait for the stinkin' data (RDY) */
677 for (t = 0; t < POLL_COUNT; t++) {
678 if ((x = inl(ES_REG(ensoniq, 1371_CODEC))) & ES_1371_CODEC_RDY) {
679 if (is_ev1938(ensoniq)) {
680 for (t = 0; t < 100; t++)
681 inl(ES_REG(ensoniq, CONTROL));
682 x = inl(ES_REG(ensoniq, 1371_CODEC));
683 }
684 mutex_unlock(&ensoniq->src_mutex);
685 return ES_1371_CODEC_READ(x);
686 }
687 }
688 mutex_unlock(&ensoniq->src_mutex);
689 if (++fail > 10) {
690 dev_err(ensoniq->card->dev,
691 "codec read timeout (final) at 0x%lx, reg = 0x%x [0x%x]\n",
692 ES_REG(ensoniq, 1371_CODEC), reg,
693 inl(ES_REG(ensoniq, 1371_CODEC)));
694 return 0;
695 }
696 goto __again;
697 }
698 }
699 mutex_unlock(&ensoniq->src_mutex);
700 dev_err(ensoniq->card->dev, "codec read timeout at 0x%lx [0x%x]\n",
701 ES_REG(ensoniq, 1371_CODEC), inl(ES_REG(ensoniq, 1371_CODEC)));
702 return 0;
703}
704
705static void snd_es1371_codec_wait(struct snd_ac97 *ac97)
706{
707 msleep(750);
708 snd_es1371_codec_read(ac97, AC97_RESET);
709 snd_es1371_codec_read(ac97, AC97_VENDOR_ID1);
710 snd_es1371_codec_read(ac97, AC97_VENDOR_ID2);
711 msleep(50);
712}
713
714static void snd_es1371_adc_rate(struct ensoniq * ensoniq, unsigned int rate)
715{
716 unsigned int n, truncm, freq;
717
718 mutex_lock(&ensoniq->src_mutex);
719 n = rate / 3000;
720 if ((1 << n) & ((1 << 15) | (1 << 13) | (1 << 11) | (1 << 9)))
721 n--;
722 truncm = (21 * n - 1) | 1;
723 freq = ((48000UL << 15) / rate) * n;
724 if (rate >= 24000) {
725 if (truncm > 239)
726 truncm = 239;
727 snd_es1371_src_write(ensoniq, ES_SMPREG_ADC + ES_SMPREG_TRUNC_N,
728 (((239 - truncm) >> 1) << 9) | (n << 4));
729 } else {
730 if (truncm > 119)
731 truncm = 119;
732 snd_es1371_src_write(ensoniq, ES_SMPREG_ADC + ES_SMPREG_TRUNC_N,
733 0x8000 | (((119 - truncm) >> 1) << 9) | (n << 4));
734 }
735 snd_es1371_src_write(ensoniq, ES_SMPREG_ADC + ES_SMPREG_INT_REGS,
736 (snd_es1371_src_read(ensoniq, ES_SMPREG_ADC +
737 ES_SMPREG_INT_REGS) & 0x00ff) |
738 ((freq >> 5) & 0xfc00));
739 snd_es1371_src_write(ensoniq, ES_SMPREG_ADC + ES_SMPREG_VFREQ_FRAC, freq & 0x7fff);
740 snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_ADC, n << 8);
741 snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_ADC + 1, n << 8);
742 mutex_unlock(&ensoniq->src_mutex);
743}
744
745static void snd_es1371_dac1_rate(struct ensoniq * ensoniq, unsigned int rate)
746{
747 unsigned int freq, r;
748
749 mutex_lock(&ensoniq->src_mutex);
750 freq = DIV_ROUND_CLOSEST(rate << 15, 3000);
751 r = (snd_es1371_wait_src_ready(ensoniq) & (ES_1371_SRC_DISABLE |
752 ES_1371_DIS_P2 | ES_1371_DIS_R1)) |
753 ES_1371_DIS_P1;
754 outl(r, ES_REG(ensoniq, 1371_SMPRATE));
755 snd_es1371_src_write(ensoniq, ES_SMPREG_DAC1 + ES_SMPREG_INT_REGS,
756 (snd_es1371_src_read(ensoniq, ES_SMPREG_DAC1 +
757 ES_SMPREG_INT_REGS) & 0x00ff) |
758 ((freq >> 5) & 0xfc00));
759 snd_es1371_src_write(ensoniq, ES_SMPREG_DAC1 + ES_SMPREG_VFREQ_FRAC, freq & 0x7fff);
760 r = (snd_es1371_wait_src_ready(ensoniq) & (ES_1371_SRC_DISABLE |
761 ES_1371_DIS_P2 | ES_1371_DIS_R1));
762 outl(r, ES_REG(ensoniq, 1371_SMPRATE));
763 mutex_unlock(&ensoniq->src_mutex);
764}
765
766static void snd_es1371_dac2_rate(struct ensoniq * ensoniq, unsigned int rate)
767{
768 unsigned int freq, r;
769
770 mutex_lock(&ensoniq->src_mutex);
771 freq = DIV_ROUND_CLOSEST(rate << 15, 3000);
772 r = (snd_es1371_wait_src_ready(ensoniq) & (ES_1371_SRC_DISABLE |
773 ES_1371_DIS_P1 | ES_1371_DIS_R1)) |
774 ES_1371_DIS_P2;
775 outl(r, ES_REG(ensoniq, 1371_SMPRATE));
776 snd_es1371_src_write(ensoniq, ES_SMPREG_DAC2 + ES_SMPREG_INT_REGS,
777 (snd_es1371_src_read(ensoniq, ES_SMPREG_DAC2 +
778 ES_SMPREG_INT_REGS) & 0x00ff) |
779 ((freq >> 5) & 0xfc00));
780 snd_es1371_src_write(ensoniq, ES_SMPREG_DAC2 + ES_SMPREG_VFREQ_FRAC,
781 freq & 0x7fff);
782 r = (snd_es1371_wait_src_ready(ensoniq) & (ES_1371_SRC_DISABLE |
783 ES_1371_DIS_P1 | ES_1371_DIS_R1));
784 outl(r, ES_REG(ensoniq, 1371_SMPRATE));
785 mutex_unlock(&ensoniq->src_mutex);
786}
787
788#endif /* CHIP1371 */
789
790static int snd_ensoniq_trigger(struct snd_pcm_substream *substream, int cmd)
791{
792 struct ensoniq *ensoniq = snd_pcm_substream_chip(substream);
793 switch (cmd) {
794 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
795 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
796 {
797 unsigned int what = 0;
798 struct snd_pcm_substream *s;
799 snd_pcm_group_for_each_entry(s, substream) {
800 if (s == ensoniq->playback1_substream) {
801 what |= ES_P1_PAUSE;
802 snd_pcm_trigger_done(s, substream);
803 } else if (s == ensoniq->playback2_substream) {
804 what |= ES_P2_PAUSE;
805 snd_pcm_trigger_done(s, substream);
806 } else if (s == ensoniq->capture_substream)
807 return -EINVAL;
808 }
809 spin_lock(&ensoniq->reg_lock);
810 if (cmd == SNDRV_PCM_TRIGGER_PAUSE_PUSH)
811 ensoniq->sctrl |= what;
812 else
813 ensoniq->sctrl &= ~what;
814 outl(ensoniq->sctrl, ES_REG(ensoniq, SERIAL));
815 spin_unlock(&ensoniq->reg_lock);
816 break;
817 }
818 case SNDRV_PCM_TRIGGER_START:
819 case SNDRV_PCM_TRIGGER_STOP:
820 {
821 unsigned int what = 0;
822 struct snd_pcm_substream *s;
823 snd_pcm_group_for_each_entry(s, substream) {
824 if (s == ensoniq->playback1_substream) {
825 what |= ES_DAC1_EN;
826 snd_pcm_trigger_done(s, substream);
827 } else if (s == ensoniq->playback2_substream) {
828 what |= ES_DAC2_EN;
829 snd_pcm_trigger_done(s, substream);
830 } else if (s == ensoniq->capture_substream) {
831 what |= ES_ADC_EN;
832 snd_pcm_trigger_done(s, substream);
833 }
834 }
835 spin_lock(&ensoniq->reg_lock);
836 if (cmd == SNDRV_PCM_TRIGGER_START)
837 ensoniq->ctrl |= what;
838 else
839 ensoniq->ctrl &= ~what;
840 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
841 spin_unlock(&ensoniq->reg_lock);
842 break;
843 }
844 default:
845 return -EINVAL;
846 }
847 return 0;
848}
849
850/*
851 * PCM part
852 */
853
854static int snd_ensoniq_playback1_prepare(struct snd_pcm_substream *substream)
855{
856 struct ensoniq *ensoniq = snd_pcm_substream_chip(substream);
857 struct snd_pcm_runtime *runtime = substream->runtime;
858 unsigned int mode = 0;
859
860 ensoniq->p1_dma_size = snd_pcm_lib_buffer_bytes(substream);
861 ensoniq->p1_period_size = snd_pcm_lib_period_bytes(substream);
862 if (snd_pcm_format_width(runtime->format) == 16)
863 mode |= 0x02;
864 if (runtime->channels > 1)
865 mode |= 0x01;
866 spin_lock_irq(&ensoniq->reg_lock);
867 ensoniq->ctrl &= ~ES_DAC1_EN;
868#ifdef CHIP1371
869 /* 48k doesn't need SRC (it breaks AC3-passthru) */
870 if (runtime->rate == 48000)
871 ensoniq->ctrl |= ES_1373_BYPASS_P1;
872 else
873 ensoniq->ctrl &= ~ES_1373_BYPASS_P1;
874#endif
875 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
876 outl(ES_MEM_PAGEO(ES_PAGE_DAC), ES_REG(ensoniq, MEM_PAGE));
877 outl(runtime->dma_addr, ES_REG(ensoniq, DAC1_FRAME));
878 outl((ensoniq->p1_dma_size >> 2) - 1, ES_REG(ensoniq, DAC1_SIZE));
879 ensoniq->sctrl &= ~(ES_P1_LOOP_SEL | ES_P1_PAUSE | ES_P1_SCT_RLD | ES_P1_MODEM);
880 ensoniq->sctrl |= ES_P1_INT_EN | ES_P1_MODEO(mode);
881 outl(ensoniq->sctrl, ES_REG(ensoniq, SERIAL));
882 outl((ensoniq->p1_period_size >> snd_ensoniq_sample_shift[mode]) - 1,
883 ES_REG(ensoniq, DAC1_COUNT));
884#ifdef CHIP1370
885 ensoniq->ctrl &= ~ES_1370_WTSRSELM;
886 switch (runtime->rate) {
887 case 5512: ensoniq->ctrl |= ES_1370_WTSRSEL(0); break;
888 case 11025: ensoniq->ctrl |= ES_1370_WTSRSEL(1); break;
889 case 22050: ensoniq->ctrl |= ES_1370_WTSRSEL(2); break;
890 case 44100: ensoniq->ctrl |= ES_1370_WTSRSEL(3); break;
891 default: snd_BUG();
892 }
893#endif
894 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
895 spin_unlock_irq(&ensoniq->reg_lock);
896#ifndef CHIP1370
897 snd_es1371_dac1_rate(ensoniq, runtime->rate);
898#endif
899 return 0;
900}
901
902static int snd_ensoniq_playback2_prepare(struct snd_pcm_substream *substream)
903{
904 struct ensoniq *ensoniq = snd_pcm_substream_chip(substream);
905 struct snd_pcm_runtime *runtime = substream->runtime;
906 unsigned int mode = 0;
907
908 ensoniq->p2_dma_size = snd_pcm_lib_buffer_bytes(substream);
909 ensoniq->p2_period_size = snd_pcm_lib_period_bytes(substream);
910 if (snd_pcm_format_width(runtime->format) == 16)
911 mode |= 0x02;
912 if (runtime->channels > 1)
913 mode |= 0x01;
914 spin_lock_irq(&ensoniq->reg_lock);
915 ensoniq->ctrl &= ~ES_DAC2_EN;
916 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
917 outl(ES_MEM_PAGEO(ES_PAGE_DAC), ES_REG(ensoniq, MEM_PAGE));
918 outl(runtime->dma_addr, ES_REG(ensoniq, DAC2_FRAME));
919 outl((ensoniq->p2_dma_size >> 2) - 1, ES_REG(ensoniq, DAC2_SIZE));
920 ensoniq->sctrl &= ~(ES_P2_LOOP_SEL | ES_P2_PAUSE | ES_P2_DAC_SEN |
921 ES_P2_END_INCM | ES_P2_ST_INCM | ES_P2_MODEM);
922 ensoniq->sctrl |= ES_P2_INT_EN | ES_P2_MODEO(mode) |
923 ES_P2_END_INCO(mode & 2 ? 2 : 1) | ES_P2_ST_INCO(0);
924 outl(ensoniq->sctrl, ES_REG(ensoniq, SERIAL));
925 outl((ensoniq->p2_period_size >> snd_ensoniq_sample_shift[mode]) - 1,
926 ES_REG(ensoniq, DAC2_COUNT));
927#ifdef CHIP1370
928 if (!(ensoniq->u.es1370.pclkdiv_lock & ES_MODE_CAPTURE)) {
929 ensoniq->ctrl &= ~ES_1370_PCLKDIVM;
930 ensoniq->ctrl |= ES_1370_PCLKDIVO(ES_1370_SRTODIV(runtime->rate));
931 ensoniq->u.es1370.pclkdiv_lock |= ES_MODE_PLAY2;
932 }
933#endif
934 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
935 spin_unlock_irq(&ensoniq->reg_lock);
936#ifndef CHIP1370
937 snd_es1371_dac2_rate(ensoniq, runtime->rate);
938#endif
939 return 0;
940}
941
942static int snd_ensoniq_capture_prepare(struct snd_pcm_substream *substream)
943{
944 struct ensoniq *ensoniq = snd_pcm_substream_chip(substream);
945 struct snd_pcm_runtime *runtime = substream->runtime;
946 unsigned int mode = 0;
947
948 ensoniq->c_dma_size = snd_pcm_lib_buffer_bytes(substream);
949 ensoniq->c_period_size = snd_pcm_lib_period_bytes(substream);
950 if (snd_pcm_format_width(runtime->format) == 16)
951 mode |= 0x02;
952 if (runtime->channels > 1)
953 mode |= 0x01;
954 spin_lock_irq(&ensoniq->reg_lock);
955 ensoniq->ctrl &= ~ES_ADC_EN;
956 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
957 outl(ES_MEM_PAGEO(ES_PAGE_ADC), ES_REG(ensoniq, MEM_PAGE));
958 outl(runtime->dma_addr, ES_REG(ensoniq, ADC_FRAME));
959 outl((ensoniq->c_dma_size >> 2) - 1, ES_REG(ensoniq, ADC_SIZE));
960 ensoniq->sctrl &= ~(ES_R1_LOOP_SEL | ES_R1_MODEM);
961 ensoniq->sctrl |= ES_R1_INT_EN | ES_R1_MODEO(mode);
962 outl(ensoniq->sctrl, ES_REG(ensoniq, SERIAL));
963 outl((ensoniq->c_period_size >> snd_ensoniq_sample_shift[mode]) - 1,
964 ES_REG(ensoniq, ADC_COUNT));
965#ifdef CHIP1370
966 if (!(ensoniq->u.es1370.pclkdiv_lock & ES_MODE_PLAY2)) {
967 ensoniq->ctrl &= ~ES_1370_PCLKDIVM;
968 ensoniq->ctrl |= ES_1370_PCLKDIVO(ES_1370_SRTODIV(runtime->rate));
969 ensoniq->u.es1370.pclkdiv_lock |= ES_MODE_CAPTURE;
970 }
971#endif
972 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
973 spin_unlock_irq(&ensoniq->reg_lock);
974#ifndef CHIP1370
975 snd_es1371_adc_rate(ensoniq, runtime->rate);
976#endif
977 return 0;
978}
979
980static snd_pcm_uframes_t snd_ensoniq_playback1_pointer(struct snd_pcm_substream *substream)
981{
982 struct ensoniq *ensoniq = snd_pcm_substream_chip(substream);
983 size_t ptr;
984
985 spin_lock(&ensoniq->reg_lock);
986 if (inl(ES_REG(ensoniq, CONTROL)) & ES_DAC1_EN) {
987 outl(ES_MEM_PAGEO(ES_PAGE_DAC), ES_REG(ensoniq, MEM_PAGE));
988 ptr = ES_REG_FCURR_COUNTI(inl(ES_REG(ensoniq, DAC1_SIZE)));
989 ptr = bytes_to_frames(substream->runtime, ptr);
990 } else {
991 ptr = 0;
992 }
993 spin_unlock(&ensoniq->reg_lock);
994 return ptr;
995}
996
997static snd_pcm_uframes_t snd_ensoniq_playback2_pointer(struct snd_pcm_substream *substream)
998{
999 struct ensoniq *ensoniq = snd_pcm_substream_chip(substream);
1000 size_t ptr;
1001
1002 spin_lock(&ensoniq->reg_lock);
1003 if (inl(ES_REG(ensoniq, CONTROL)) & ES_DAC2_EN) {
1004 outl(ES_MEM_PAGEO(ES_PAGE_DAC), ES_REG(ensoniq, MEM_PAGE));
1005 ptr = ES_REG_FCURR_COUNTI(inl(ES_REG(ensoniq, DAC2_SIZE)));
1006 ptr = bytes_to_frames(substream->runtime, ptr);
1007 } else {
1008 ptr = 0;
1009 }
1010 spin_unlock(&ensoniq->reg_lock);
1011 return ptr;
1012}
1013
1014static snd_pcm_uframes_t snd_ensoniq_capture_pointer(struct snd_pcm_substream *substream)
1015{
1016 struct ensoniq *ensoniq = snd_pcm_substream_chip(substream);
1017 size_t ptr;
1018
1019 spin_lock(&ensoniq->reg_lock);
1020 if (inl(ES_REG(ensoniq, CONTROL)) & ES_ADC_EN) {
1021 outl(ES_MEM_PAGEO(ES_PAGE_ADC), ES_REG(ensoniq, MEM_PAGE));
1022 ptr = ES_REG_FCURR_COUNTI(inl(ES_REG(ensoniq, ADC_SIZE)));
1023 ptr = bytes_to_frames(substream->runtime, ptr);
1024 } else {
1025 ptr = 0;
1026 }
1027 spin_unlock(&ensoniq->reg_lock);
1028 return ptr;
1029}
1030
1031static const struct snd_pcm_hardware snd_ensoniq_playback1 =
1032{
1033 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1034 SNDRV_PCM_INFO_BLOCK_TRANSFER |
1035 SNDRV_PCM_INFO_MMAP_VALID |
1036 SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_SYNC_START),
1037 .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
1038 .rates =
1039#ifndef CHIP1370
1040 SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
1041#else
1042 (SNDRV_PCM_RATE_KNOT | /* 5512Hz rate */
1043 SNDRV_PCM_RATE_11025 | SNDRV_PCM_RATE_22050 |
1044 SNDRV_PCM_RATE_44100),
1045#endif
1046 .rate_min = 4000,
1047 .rate_max = 48000,
1048 .channels_min = 1,
1049 .channels_max = 2,
1050 .buffer_bytes_max = (128*1024),
1051 .period_bytes_min = 64,
1052 .period_bytes_max = (128*1024),
1053 .periods_min = 1,
1054 .periods_max = 1024,
1055 .fifo_size = 0,
1056};
1057
1058static const struct snd_pcm_hardware snd_ensoniq_playback2 =
1059{
1060 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1061 SNDRV_PCM_INFO_BLOCK_TRANSFER |
1062 SNDRV_PCM_INFO_MMAP_VALID | SNDRV_PCM_INFO_PAUSE |
1063 SNDRV_PCM_INFO_SYNC_START),
1064 .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
1065 .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
1066 .rate_min = 4000,
1067 .rate_max = 48000,
1068 .channels_min = 1,
1069 .channels_max = 2,
1070 .buffer_bytes_max = (128*1024),
1071 .period_bytes_min = 64,
1072 .period_bytes_max = (128*1024),
1073 .periods_min = 1,
1074 .periods_max = 1024,
1075 .fifo_size = 0,
1076};
1077
1078static const struct snd_pcm_hardware snd_ensoniq_capture =
1079{
1080 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1081 SNDRV_PCM_INFO_BLOCK_TRANSFER |
1082 SNDRV_PCM_INFO_MMAP_VALID | SNDRV_PCM_INFO_SYNC_START),
1083 .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
1084 .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
1085 .rate_min = 4000,
1086 .rate_max = 48000,
1087 .channels_min = 1,
1088 .channels_max = 2,
1089 .buffer_bytes_max = (128*1024),
1090 .period_bytes_min = 64,
1091 .period_bytes_max = (128*1024),
1092 .periods_min = 1,
1093 .periods_max = 1024,
1094 .fifo_size = 0,
1095};
1096
1097static int snd_ensoniq_playback1_open(struct snd_pcm_substream *substream)
1098{
1099 struct ensoniq *ensoniq = snd_pcm_substream_chip(substream);
1100 struct snd_pcm_runtime *runtime = substream->runtime;
1101
1102 ensoniq->mode |= ES_MODE_PLAY1;
1103 ensoniq->playback1_substream = substream;
1104 runtime->hw = snd_ensoniq_playback1;
1105 snd_pcm_set_sync(substream);
1106 spin_lock_irq(&ensoniq->reg_lock);
1107 if (ensoniq->spdif && ensoniq->playback2_substream == NULL)
1108 ensoniq->spdif_stream = ensoniq->spdif_default;
1109 spin_unlock_irq(&ensoniq->reg_lock);
1110#ifdef CHIP1370
1111 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
1112 &snd_es1370_hw_constraints_rates);
1113#else
1114 snd_pcm_hw_constraint_ratdens(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
1115 &snd_es1371_hw_constraints_dac_clock);
1116#endif
1117 return 0;
1118}
1119
1120static int snd_ensoniq_playback2_open(struct snd_pcm_substream *substream)
1121{
1122 struct ensoniq *ensoniq = snd_pcm_substream_chip(substream);
1123 struct snd_pcm_runtime *runtime = substream->runtime;
1124
1125 ensoniq->mode |= ES_MODE_PLAY2;
1126 ensoniq->playback2_substream = substream;
1127 runtime->hw = snd_ensoniq_playback2;
1128 snd_pcm_set_sync(substream);
1129 spin_lock_irq(&ensoniq->reg_lock);
1130 if (ensoniq->spdif && ensoniq->playback1_substream == NULL)
1131 ensoniq->spdif_stream = ensoniq->spdif_default;
1132 spin_unlock_irq(&ensoniq->reg_lock);
1133#ifdef CHIP1370
1134 snd_pcm_hw_constraint_ratnums(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
1135 &snd_es1370_hw_constraints_clock);
1136#else
1137 snd_pcm_hw_constraint_ratdens(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
1138 &snd_es1371_hw_constraints_dac_clock);
1139#endif
1140 return 0;
1141}
1142
1143static int snd_ensoniq_capture_open(struct snd_pcm_substream *substream)
1144{
1145 struct ensoniq *ensoniq = snd_pcm_substream_chip(substream);
1146 struct snd_pcm_runtime *runtime = substream->runtime;
1147
1148 ensoniq->mode |= ES_MODE_CAPTURE;
1149 ensoniq->capture_substream = substream;
1150 runtime->hw = snd_ensoniq_capture;
1151 snd_pcm_set_sync(substream);
1152#ifdef CHIP1370
1153 snd_pcm_hw_constraint_ratnums(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
1154 &snd_es1370_hw_constraints_clock);
1155#else
1156 snd_pcm_hw_constraint_ratnums(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
1157 &snd_es1371_hw_constraints_adc_clock);
1158#endif
1159 return 0;
1160}
1161
1162static int snd_ensoniq_playback1_close(struct snd_pcm_substream *substream)
1163{
1164 struct ensoniq *ensoniq = snd_pcm_substream_chip(substream);
1165
1166 ensoniq->playback1_substream = NULL;
1167 ensoniq->mode &= ~ES_MODE_PLAY1;
1168 return 0;
1169}
1170
1171static int snd_ensoniq_playback2_close(struct snd_pcm_substream *substream)
1172{
1173 struct ensoniq *ensoniq = snd_pcm_substream_chip(substream);
1174
1175 ensoniq->playback2_substream = NULL;
1176 spin_lock_irq(&ensoniq->reg_lock);
1177#ifdef CHIP1370
1178 ensoniq->u.es1370.pclkdiv_lock &= ~ES_MODE_PLAY2;
1179#endif
1180 ensoniq->mode &= ~ES_MODE_PLAY2;
1181 spin_unlock_irq(&ensoniq->reg_lock);
1182 return 0;
1183}
1184
1185static int snd_ensoniq_capture_close(struct snd_pcm_substream *substream)
1186{
1187 struct ensoniq *ensoniq = snd_pcm_substream_chip(substream);
1188
1189 ensoniq->capture_substream = NULL;
1190 spin_lock_irq(&ensoniq->reg_lock);
1191#ifdef CHIP1370
1192 ensoniq->u.es1370.pclkdiv_lock &= ~ES_MODE_CAPTURE;
1193#endif
1194 ensoniq->mode &= ~ES_MODE_CAPTURE;
1195 spin_unlock_irq(&ensoniq->reg_lock);
1196 return 0;
1197}
1198
1199static const struct snd_pcm_ops snd_ensoniq_playback1_ops = {
1200 .open = snd_ensoniq_playback1_open,
1201 .close = snd_ensoniq_playback1_close,
1202 .prepare = snd_ensoniq_playback1_prepare,
1203 .trigger = snd_ensoniq_trigger,
1204 .pointer = snd_ensoniq_playback1_pointer,
1205};
1206
1207static const struct snd_pcm_ops snd_ensoniq_playback2_ops = {
1208 .open = snd_ensoniq_playback2_open,
1209 .close = snd_ensoniq_playback2_close,
1210 .prepare = snd_ensoniq_playback2_prepare,
1211 .trigger = snd_ensoniq_trigger,
1212 .pointer = snd_ensoniq_playback2_pointer,
1213};
1214
1215static const struct snd_pcm_ops snd_ensoniq_capture_ops = {
1216 .open = snd_ensoniq_capture_open,
1217 .close = snd_ensoniq_capture_close,
1218 .prepare = snd_ensoniq_capture_prepare,
1219 .trigger = snd_ensoniq_trigger,
1220 .pointer = snd_ensoniq_capture_pointer,
1221};
1222
1223static const struct snd_pcm_chmap_elem surround_map[] = {
1224 { .channels = 1,
1225 .map = { SNDRV_CHMAP_MONO } },
1226 { .channels = 2,
1227 .map = { SNDRV_CHMAP_RL, SNDRV_CHMAP_RR } },
1228 {0}
1229};
1230
1231static int snd_ensoniq_pcm(struct ensoniq *ensoniq, int device)
1232{
1233 struct snd_pcm *pcm;
1234 int err;
1235
1236 err = snd_pcm_new(ensoniq->card, CHIP_NAME "/1", device, 1, 1, &pcm);
1237 if (err < 0)
1238 return err;
1239
1240#ifdef CHIP1370
1241 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_ensoniq_playback2_ops);
1242#else
1243 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_ensoniq_playback1_ops);
1244#endif
1245 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_ensoniq_capture_ops);
1246
1247 pcm->private_data = ensoniq;
1248 pcm->info_flags = 0;
1249 strcpy(pcm->name, CHIP_NAME " DAC2/ADC");
1250 ensoniq->pcm1 = pcm;
1251
1252 snd_pcm_set_managed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV,
1253 &ensoniq->pci->dev, 64*1024, 128*1024);
1254
1255#ifdef CHIP1370
1256 err = snd_pcm_add_chmap_ctls(pcm, SNDRV_PCM_STREAM_PLAYBACK,
1257 surround_map, 2, 0, NULL);
1258#else
1259 err = snd_pcm_add_chmap_ctls(pcm, SNDRV_PCM_STREAM_PLAYBACK,
1260 snd_pcm_std_chmaps, 2, 0, NULL);
1261#endif
1262 return err;
1263}
1264
1265static int snd_ensoniq_pcm2(struct ensoniq *ensoniq, int device)
1266{
1267 struct snd_pcm *pcm;
1268 int err;
1269
1270 err = snd_pcm_new(ensoniq->card, CHIP_NAME "/2", device, 1, 0, &pcm);
1271 if (err < 0)
1272 return err;
1273
1274#ifdef CHIP1370
1275 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_ensoniq_playback1_ops);
1276#else
1277 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_ensoniq_playback2_ops);
1278#endif
1279 pcm->private_data = ensoniq;
1280 pcm->info_flags = 0;
1281 strcpy(pcm->name, CHIP_NAME " DAC1");
1282 ensoniq->pcm2 = pcm;
1283
1284 snd_pcm_set_managed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV,
1285 &ensoniq->pci->dev, 64*1024, 128*1024);
1286
1287#ifdef CHIP1370
1288 err = snd_pcm_add_chmap_ctls(pcm, SNDRV_PCM_STREAM_PLAYBACK,
1289 snd_pcm_std_chmaps, 2, 0, NULL);
1290#else
1291 err = snd_pcm_add_chmap_ctls(pcm, SNDRV_PCM_STREAM_PLAYBACK,
1292 surround_map, 2, 0, NULL);
1293#endif
1294 return err;
1295}
1296
1297/*
1298 * Mixer section
1299 */
1300
1301/*
1302 * ENS1371 mixer (including SPDIF interface)
1303 */
1304#ifdef CHIP1371
1305static int snd_ens1373_spdif_info(struct snd_kcontrol *kcontrol,
1306 struct snd_ctl_elem_info *uinfo)
1307{
1308 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1309 uinfo->count = 1;
1310 return 0;
1311}
1312
1313static int snd_ens1373_spdif_default_get(struct snd_kcontrol *kcontrol,
1314 struct snd_ctl_elem_value *ucontrol)
1315{
1316 struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol);
1317 spin_lock_irq(&ensoniq->reg_lock);
1318 ucontrol->value.iec958.status[0] = (ensoniq->spdif_default >> 0) & 0xff;
1319 ucontrol->value.iec958.status[1] = (ensoniq->spdif_default >> 8) & 0xff;
1320 ucontrol->value.iec958.status[2] = (ensoniq->spdif_default >> 16) & 0xff;
1321 ucontrol->value.iec958.status[3] = (ensoniq->spdif_default >> 24) & 0xff;
1322 spin_unlock_irq(&ensoniq->reg_lock);
1323 return 0;
1324}
1325
1326static int snd_ens1373_spdif_default_put(struct snd_kcontrol *kcontrol,
1327 struct snd_ctl_elem_value *ucontrol)
1328{
1329 struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol);
1330 unsigned int val;
1331 int change;
1332
1333 val = ((u32)ucontrol->value.iec958.status[0] << 0) |
1334 ((u32)ucontrol->value.iec958.status[1] << 8) |
1335 ((u32)ucontrol->value.iec958.status[2] << 16) |
1336 ((u32)ucontrol->value.iec958.status[3] << 24);
1337 spin_lock_irq(&ensoniq->reg_lock);
1338 change = ensoniq->spdif_default != val;
1339 ensoniq->spdif_default = val;
1340 if (change && ensoniq->playback1_substream == NULL &&
1341 ensoniq->playback2_substream == NULL)
1342 outl(val, ES_REG(ensoniq, CHANNEL_STATUS));
1343 spin_unlock_irq(&ensoniq->reg_lock);
1344 return change;
1345}
1346
1347static int snd_ens1373_spdif_mask_get(struct snd_kcontrol *kcontrol,
1348 struct snd_ctl_elem_value *ucontrol)
1349{
1350 ucontrol->value.iec958.status[0] = 0xff;
1351 ucontrol->value.iec958.status[1] = 0xff;
1352 ucontrol->value.iec958.status[2] = 0xff;
1353 ucontrol->value.iec958.status[3] = 0xff;
1354 return 0;
1355}
1356
1357static int snd_ens1373_spdif_stream_get(struct snd_kcontrol *kcontrol,
1358 struct snd_ctl_elem_value *ucontrol)
1359{
1360 struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol);
1361 spin_lock_irq(&ensoniq->reg_lock);
1362 ucontrol->value.iec958.status[0] = (ensoniq->spdif_stream >> 0) & 0xff;
1363 ucontrol->value.iec958.status[1] = (ensoniq->spdif_stream >> 8) & 0xff;
1364 ucontrol->value.iec958.status[2] = (ensoniq->spdif_stream >> 16) & 0xff;
1365 ucontrol->value.iec958.status[3] = (ensoniq->spdif_stream >> 24) & 0xff;
1366 spin_unlock_irq(&ensoniq->reg_lock);
1367 return 0;
1368}
1369
1370static int snd_ens1373_spdif_stream_put(struct snd_kcontrol *kcontrol,
1371 struct snd_ctl_elem_value *ucontrol)
1372{
1373 struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol);
1374 unsigned int val;
1375 int change;
1376
1377 val = ((u32)ucontrol->value.iec958.status[0] << 0) |
1378 ((u32)ucontrol->value.iec958.status[1] << 8) |
1379 ((u32)ucontrol->value.iec958.status[2] << 16) |
1380 ((u32)ucontrol->value.iec958.status[3] << 24);
1381 spin_lock_irq(&ensoniq->reg_lock);
1382 change = ensoniq->spdif_stream != val;
1383 ensoniq->spdif_stream = val;
1384 if (change && (ensoniq->playback1_substream != NULL ||
1385 ensoniq->playback2_substream != NULL))
1386 outl(val, ES_REG(ensoniq, CHANNEL_STATUS));
1387 spin_unlock_irq(&ensoniq->reg_lock);
1388 return change;
1389}
1390
1391#define ES1371_SPDIF(xname) \
1392{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, .info = snd_es1371_spdif_info, \
1393 .get = snd_es1371_spdif_get, .put = snd_es1371_spdif_put }
1394
1395#define snd_es1371_spdif_info snd_ctl_boolean_mono_info
1396
1397static int snd_es1371_spdif_get(struct snd_kcontrol *kcontrol,
1398 struct snd_ctl_elem_value *ucontrol)
1399{
1400 struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol);
1401
1402 spin_lock_irq(&ensoniq->reg_lock);
1403 ucontrol->value.integer.value[0] = ensoniq->ctrl & ES_1373_SPDIF_THRU ? 1 : 0;
1404 spin_unlock_irq(&ensoniq->reg_lock);
1405 return 0;
1406}
1407
1408static int snd_es1371_spdif_put(struct snd_kcontrol *kcontrol,
1409 struct snd_ctl_elem_value *ucontrol)
1410{
1411 struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol);
1412 unsigned int nval1, nval2;
1413 int change;
1414
1415 nval1 = ucontrol->value.integer.value[0] ? ES_1373_SPDIF_THRU : 0;
1416 nval2 = ucontrol->value.integer.value[0] ? ES_1373_SPDIF_EN : 0;
1417 spin_lock_irq(&ensoniq->reg_lock);
1418 change = (ensoniq->ctrl & ES_1373_SPDIF_THRU) != nval1;
1419 ensoniq->ctrl &= ~ES_1373_SPDIF_THRU;
1420 ensoniq->ctrl |= nval1;
1421 ensoniq->cssr &= ~ES_1373_SPDIF_EN;
1422 ensoniq->cssr |= nval2;
1423 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
1424 outl(ensoniq->cssr, ES_REG(ensoniq, STATUS));
1425 spin_unlock_irq(&ensoniq->reg_lock);
1426 return change;
1427}
1428
1429
1430/* spdif controls */
1431static const struct snd_kcontrol_new snd_es1371_mixer_spdif[] = {
1432 ES1371_SPDIF(SNDRV_CTL_NAME_IEC958("",PLAYBACK,SWITCH)),
1433 {
1434 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1435 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,DEFAULT),
1436 .info = snd_ens1373_spdif_info,
1437 .get = snd_ens1373_spdif_default_get,
1438 .put = snd_ens1373_spdif_default_put,
1439 },
1440 {
1441 .access = SNDRV_CTL_ELEM_ACCESS_READ,
1442 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1443 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,MASK),
1444 .info = snd_ens1373_spdif_info,
1445 .get = snd_ens1373_spdif_mask_get
1446 },
1447 {
1448 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1449 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,PCM_STREAM),
1450 .info = snd_ens1373_spdif_info,
1451 .get = snd_ens1373_spdif_stream_get,
1452 .put = snd_ens1373_spdif_stream_put
1453 },
1454};
1455
1456
1457#define snd_es1373_rear_info snd_ctl_boolean_mono_info
1458
1459static int snd_es1373_rear_get(struct snd_kcontrol *kcontrol,
1460 struct snd_ctl_elem_value *ucontrol)
1461{
1462 struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol);
1463 int val = 0;
1464
1465 spin_lock_irq(&ensoniq->reg_lock);
1466 if ((ensoniq->cssr & (ES_1373_REAR_BIT27|ES_1373_REAR_BIT26|
1467 ES_1373_REAR_BIT24)) == ES_1373_REAR_BIT26)
1468 val = 1;
1469 ucontrol->value.integer.value[0] = val;
1470 spin_unlock_irq(&ensoniq->reg_lock);
1471 return 0;
1472}
1473
1474static int snd_es1373_rear_put(struct snd_kcontrol *kcontrol,
1475 struct snd_ctl_elem_value *ucontrol)
1476{
1477 struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol);
1478 unsigned int nval1;
1479 int change;
1480
1481 nval1 = ucontrol->value.integer.value[0] ?
1482 ES_1373_REAR_BIT26 : (ES_1373_REAR_BIT27|ES_1373_REAR_BIT24);
1483 spin_lock_irq(&ensoniq->reg_lock);
1484 change = (ensoniq->cssr & (ES_1373_REAR_BIT27|
1485 ES_1373_REAR_BIT26|ES_1373_REAR_BIT24)) != nval1;
1486 ensoniq->cssr &= ~(ES_1373_REAR_BIT27|ES_1373_REAR_BIT26|ES_1373_REAR_BIT24);
1487 ensoniq->cssr |= nval1;
1488 outl(ensoniq->cssr, ES_REG(ensoniq, STATUS));
1489 spin_unlock_irq(&ensoniq->reg_lock);
1490 return change;
1491}
1492
1493static const struct snd_kcontrol_new snd_ens1373_rear =
1494{
1495 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
1496 .name = "AC97 2ch->4ch Copy Switch",
1497 .info = snd_es1373_rear_info,
1498 .get = snd_es1373_rear_get,
1499 .put = snd_es1373_rear_put,
1500};
1501
1502#define snd_es1373_line_info snd_ctl_boolean_mono_info
1503
1504static int snd_es1373_line_get(struct snd_kcontrol *kcontrol,
1505 struct snd_ctl_elem_value *ucontrol)
1506{
1507 struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol);
1508 int val = 0;
1509
1510 spin_lock_irq(&ensoniq->reg_lock);
1511 if (ensoniq->ctrl & ES_1371_GPIO_OUT(4))
1512 val = 1;
1513 ucontrol->value.integer.value[0] = val;
1514 spin_unlock_irq(&ensoniq->reg_lock);
1515 return 0;
1516}
1517
1518static int snd_es1373_line_put(struct snd_kcontrol *kcontrol,
1519 struct snd_ctl_elem_value *ucontrol)
1520{
1521 struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol);
1522 int changed;
1523 unsigned int ctrl;
1524
1525 spin_lock_irq(&ensoniq->reg_lock);
1526 ctrl = ensoniq->ctrl;
1527 if (ucontrol->value.integer.value[0])
1528 ensoniq->ctrl |= ES_1371_GPIO_OUT(4); /* switch line-in -> rear out */
1529 else
1530 ensoniq->ctrl &= ~ES_1371_GPIO_OUT(4);
1531 changed = (ctrl != ensoniq->ctrl);
1532 if (changed)
1533 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
1534 spin_unlock_irq(&ensoniq->reg_lock);
1535 return changed;
1536}
1537
1538static const struct snd_kcontrol_new snd_ens1373_line =
1539{
1540 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
1541 .name = "Line In->Rear Out Switch",
1542 .info = snd_es1373_line_info,
1543 .get = snd_es1373_line_get,
1544 .put = snd_es1373_line_put,
1545};
1546
1547static void snd_ensoniq_mixer_free_ac97(struct snd_ac97 *ac97)
1548{
1549 struct ensoniq *ensoniq = ac97->private_data;
1550 ensoniq->u.es1371.ac97 = NULL;
1551}
1552
1553struct es1371_quirk {
1554 unsigned short vid; /* vendor ID */
1555 unsigned short did; /* device ID */
1556 unsigned char rev; /* revision */
1557};
1558
1559static int es1371_quirk_lookup(struct ensoniq *ensoniq,
1560 const struct es1371_quirk *list)
1561{
1562 while (list->vid != (unsigned short)PCI_ANY_ID) {
1563 if (ensoniq->pci->vendor == list->vid &&
1564 ensoniq->pci->device == list->did &&
1565 ensoniq->rev == list->rev)
1566 return 1;
1567 list++;
1568 }
1569 return 0;
1570}
1571
1572static const struct es1371_quirk es1371_spdif_present[] = {
1573 { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_CT5880, .rev = CT5880REV_CT5880_C },
1574 { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_CT5880, .rev = CT5880REV_CT5880_D },
1575 { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_CT5880, .rev = CT5880REV_CT5880_E },
1576 { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_ES1371, .rev = ES1371REV_CT5880_A },
1577 { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_ES1371, .rev = ES1371REV_ES1373_8 },
1578 { .vid = PCI_ANY_ID, .did = PCI_ANY_ID }
1579};
1580
1581static const struct snd_pci_quirk ens1373_line_quirk[] = {
1582 SND_PCI_QUIRK_ID(0x1274, 0x2000), /* GA-7DXR */
1583 SND_PCI_QUIRK_ID(0x1458, 0xa000), /* GA-8IEXP */
1584 {0} /* end */
1585};
1586
1587static int snd_ensoniq_1371_mixer(struct ensoniq *ensoniq,
1588 int has_spdif, int has_line)
1589{
1590 struct snd_card *card = ensoniq->card;
1591 struct snd_ac97_bus *pbus;
1592 struct snd_ac97_template ac97;
1593 int err;
1594 static const struct snd_ac97_bus_ops ops = {
1595 .write = snd_es1371_codec_write,
1596 .read = snd_es1371_codec_read,
1597 .wait = snd_es1371_codec_wait,
1598 };
1599
1600 if ((err = snd_ac97_bus(card, 0, &ops, NULL, &pbus)) < 0)
1601 return err;
1602
1603 memset(&ac97, 0, sizeof(ac97));
1604 ac97.private_data = ensoniq;
1605 ac97.private_free = snd_ensoniq_mixer_free_ac97;
1606 ac97.pci = ensoniq->pci;
1607 ac97.scaps = AC97_SCAP_AUDIO;
1608 if ((err = snd_ac97_mixer(pbus, &ac97, &ensoniq->u.es1371.ac97)) < 0)
1609 return err;
1610 if (has_spdif > 0 ||
1611 (!has_spdif && es1371_quirk_lookup(ensoniq, es1371_spdif_present))) {
1612 struct snd_kcontrol *kctl;
1613 int i, is_spdif = 0;
1614
1615 ensoniq->spdif_default = ensoniq->spdif_stream =
1616 SNDRV_PCM_DEFAULT_CON_SPDIF;
1617 outl(ensoniq->spdif_default, ES_REG(ensoniq, CHANNEL_STATUS));
1618
1619 if (ensoniq->u.es1371.ac97->ext_id & AC97_EI_SPDIF)
1620 is_spdif++;
1621
1622 for (i = 0; i < ARRAY_SIZE(snd_es1371_mixer_spdif); i++) {
1623 kctl = snd_ctl_new1(&snd_es1371_mixer_spdif[i], ensoniq);
1624 if (!kctl)
1625 return -ENOMEM;
1626 kctl->id.index = is_spdif;
1627 err = snd_ctl_add(card, kctl);
1628 if (err < 0)
1629 return err;
1630 }
1631 }
1632 if (ensoniq->u.es1371.ac97->ext_id & AC97_EI_SDAC) {
1633 /* mirror rear to front speakers */
1634 ensoniq->cssr &= ~(ES_1373_REAR_BIT27|ES_1373_REAR_BIT24);
1635 ensoniq->cssr |= ES_1373_REAR_BIT26;
1636 err = snd_ctl_add(card, snd_ctl_new1(&snd_ens1373_rear, ensoniq));
1637 if (err < 0)
1638 return err;
1639 }
1640 if (has_line > 0 ||
1641 snd_pci_quirk_lookup(ensoniq->pci, ens1373_line_quirk)) {
1642 err = snd_ctl_add(card, snd_ctl_new1(&snd_ens1373_line,
1643 ensoniq));
1644 if (err < 0)
1645 return err;
1646 }
1647
1648 return 0;
1649}
1650
1651#endif /* CHIP1371 */
1652
1653/* generic control callbacks for ens1370 */
1654#ifdef CHIP1370
1655#define ENSONIQ_CONTROL(xname, mask) \
1656{ .iface = SNDRV_CTL_ELEM_IFACE_CARD, .name = xname, .info = snd_ensoniq_control_info, \
1657 .get = snd_ensoniq_control_get, .put = snd_ensoniq_control_put, \
1658 .private_value = mask }
1659
1660#define snd_ensoniq_control_info snd_ctl_boolean_mono_info
1661
1662static int snd_ensoniq_control_get(struct snd_kcontrol *kcontrol,
1663 struct snd_ctl_elem_value *ucontrol)
1664{
1665 struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol);
1666 int mask = kcontrol->private_value;
1667
1668 spin_lock_irq(&ensoniq->reg_lock);
1669 ucontrol->value.integer.value[0] = ensoniq->ctrl & mask ? 1 : 0;
1670 spin_unlock_irq(&ensoniq->reg_lock);
1671 return 0;
1672}
1673
1674static int snd_ensoniq_control_put(struct snd_kcontrol *kcontrol,
1675 struct snd_ctl_elem_value *ucontrol)
1676{
1677 struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol);
1678 int mask = kcontrol->private_value;
1679 unsigned int nval;
1680 int change;
1681
1682 nval = ucontrol->value.integer.value[0] ? mask : 0;
1683 spin_lock_irq(&ensoniq->reg_lock);
1684 change = (ensoniq->ctrl & mask) != nval;
1685 ensoniq->ctrl &= ~mask;
1686 ensoniq->ctrl |= nval;
1687 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
1688 spin_unlock_irq(&ensoniq->reg_lock);
1689 return change;
1690}
1691
1692/*
1693 * ENS1370 mixer
1694 */
1695
1696static const struct snd_kcontrol_new snd_es1370_controls[2] = {
1697ENSONIQ_CONTROL("PCM 0 Output also on Line-In Jack", ES_1370_XCTL0),
1698ENSONIQ_CONTROL("Mic +5V bias", ES_1370_XCTL1)
1699};
1700
1701#define ES1370_CONTROLS ARRAY_SIZE(snd_es1370_controls)
1702
1703static void snd_ensoniq_mixer_free_ak4531(struct snd_ak4531 *ak4531)
1704{
1705 struct ensoniq *ensoniq = ak4531->private_data;
1706 ensoniq->u.es1370.ak4531 = NULL;
1707}
1708
1709static int snd_ensoniq_1370_mixer(struct ensoniq *ensoniq)
1710{
1711 struct snd_card *card = ensoniq->card;
1712 struct snd_ak4531 ak4531;
1713 unsigned int idx;
1714 int err;
1715
1716 /* try reset AK4531 */
1717 outw(ES_1370_CODEC_WRITE(AK4531_RESET, 0x02), ES_REG(ensoniq, 1370_CODEC));
1718 inw(ES_REG(ensoniq, 1370_CODEC));
1719 udelay(100);
1720 outw(ES_1370_CODEC_WRITE(AK4531_RESET, 0x03), ES_REG(ensoniq, 1370_CODEC));
1721 inw(ES_REG(ensoniq, 1370_CODEC));
1722 udelay(100);
1723
1724 memset(&ak4531, 0, sizeof(ak4531));
1725 ak4531.write = snd_es1370_codec_write;
1726 ak4531.private_data = ensoniq;
1727 ak4531.private_free = snd_ensoniq_mixer_free_ak4531;
1728 if ((err = snd_ak4531_mixer(card, &ak4531, &ensoniq->u.es1370.ak4531)) < 0)
1729 return err;
1730 for (idx = 0; idx < ES1370_CONTROLS; idx++) {
1731 err = snd_ctl_add(card, snd_ctl_new1(&snd_es1370_controls[idx], ensoniq));
1732 if (err < 0)
1733 return err;
1734 }
1735 return 0;
1736}
1737
1738#endif /* CHIP1370 */
1739
1740#ifdef SUPPORT_JOYSTICK
1741
1742#ifdef CHIP1371
1743static int snd_ensoniq_get_joystick_port(struct ensoniq *ensoniq, int dev)
1744{
1745 switch (joystick_port[dev]) {
1746 case 0: /* disabled */
1747 case 1: /* auto-detect */
1748 case 0x200:
1749 case 0x208:
1750 case 0x210:
1751 case 0x218:
1752 return joystick_port[dev];
1753
1754 default:
1755 dev_err(ensoniq->card->dev,
1756 "invalid joystick port %#x", joystick_port[dev]);
1757 return 0;
1758 }
1759}
1760#else
1761static int snd_ensoniq_get_joystick_port(struct ensoniq *ensoniq, int dev)
1762{
1763 return joystick[dev] ? 0x200 : 0;
1764}
1765#endif
1766
1767static int snd_ensoniq_create_gameport(struct ensoniq *ensoniq, int dev)
1768{
1769 struct gameport *gp;
1770 int io_port;
1771
1772 io_port = snd_ensoniq_get_joystick_port(ensoniq, dev);
1773
1774 switch (io_port) {
1775 case 0:
1776 return -ENOSYS;
1777
1778 case 1: /* auto_detect */
1779 for (io_port = 0x200; io_port <= 0x218; io_port += 8)
1780 if (request_region(io_port, 8, "ens137x: gameport"))
1781 break;
1782 if (io_port > 0x218) {
1783 dev_warn(ensoniq->card->dev,
1784 "no gameport ports available\n");
1785 return -EBUSY;
1786 }
1787 break;
1788
1789 default:
1790 if (!request_region(io_port, 8, "ens137x: gameport")) {
1791 dev_warn(ensoniq->card->dev,
1792 "gameport io port %#x in use\n",
1793 io_port);
1794 return -EBUSY;
1795 }
1796 break;
1797 }
1798
1799 ensoniq->gameport = gp = gameport_allocate_port();
1800 if (!gp) {
1801 dev_err(ensoniq->card->dev,
1802 "cannot allocate memory for gameport\n");
1803 release_region(io_port, 8);
1804 return -ENOMEM;
1805 }
1806
1807 gameport_set_name(gp, "ES137x");
1808 gameport_set_phys(gp, "pci%s/gameport0", pci_name(ensoniq->pci));
1809 gameport_set_dev_parent(gp, &ensoniq->pci->dev);
1810 gp->io = io_port;
1811
1812 ensoniq->ctrl |= ES_JYSTK_EN;
1813#ifdef CHIP1371
1814 ensoniq->ctrl &= ~ES_1371_JOY_ASELM;
1815 ensoniq->ctrl |= ES_1371_JOY_ASEL((io_port - 0x200) / 8);
1816#endif
1817 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
1818
1819 gameport_register_port(ensoniq->gameport);
1820
1821 return 0;
1822}
1823
1824static void snd_ensoniq_free_gameport(struct ensoniq *ensoniq)
1825{
1826 if (ensoniq->gameport) {
1827 int port = ensoniq->gameport->io;
1828
1829 gameport_unregister_port(ensoniq->gameport);
1830 ensoniq->gameport = NULL;
1831 ensoniq->ctrl &= ~ES_JYSTK_EN;
1832 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
1833 release_region(port, 8);
1834 }
1835}
1836#else
1837static inline int snd_ensoniq_create_gameport(struct ensoniq *ensoniq, long port) { return -ENOSYS; }
1838static inline void snd_ensoniq_free_gameport(struct ensoniq *ensoniq) { }
1839#endif /* SUPPORT_JOYSTICK */
1840
1841/*
1842
1843 */
1844
1845static void snd_ensoniq_proc_read(struct snd_info_entry *entry,
1846 struct snd_info_buffer *buffer)
1847{
1848 struct ensoniq *ensoniq = entry->private_data;
1849
1850 snd_iprintf(buffer, "Ensoniq AudioPCI " CHIP_NAME "\n\n");
1851 snd_iprintf(buffer, "Joystick enable : %s\n",
1852 ensoniq->ctrl & ES_JYSTK_EN ? "on" : "off");
1853#ifdef CHIP1370
1854 snd_iprintf(buffer, "MIC +5V bias : %s\n",
1855 ensoniq->ctrl & ES_1370_XCTL1 ? "on" : "off");
1856 snd_iprintf(buffer, "Line In to AOUT : %s\n",
1857 ensoniq->ctrl & ES_1370_XCTL0 ? "on" : "off");
1858#else
1859 snd_iprintf(buffer, "Joystick port : 0x%x\n",
1860 (ES_1371_JOY_ASELI(ensoniq->ctrl) * 8) + 0x200);
1861#endif
1862}
1863
1864static void snd_ensoniq_proc_init(struct ensoniq *ensoniq)
1865{
1866 snd_card_ro_proc_new(ensoniq->card, "audiopci", ensoniq,
1867 snd_ensoniq_proc_read);
1868}
1869
1870/*
1871
1872 */
1873
1874static int snd_ensoniq_free(struct ensoniq *ensoniq)
1875{
1876 snd_ensoniq_free_gameport(ensoniq);
1877 if (ensoniq->irq < 0)
1878 goto __hw_end;
1879#ifdef CHIP1370
1880 outl(ES_1370_SERR_DISABLE, ES_REG(ensoniq, CONTROL)); /* switch everything off */
1881 outl(0, ES_REG(ensoniq, SERIAL)); /* clear serial interface */
1882#else
1883 outl(0, ES_REG(ensoniq, CONTROL)); /* switch everything off */
1884 outl(0, ES_REG(ensoniq, SERIAL)); /* clear serial interface */
1885#endif
1886 pci_set_power_state(ensoniq->pci, PCI_D3hot);
1887 __hw_end:
1888#ifdef CHIP1370
1889 if (ensoniq->dma_bug.area)
1890 snd_dma_free_pages(&ensoniq->dma_bug);
1891#endif
1892 if (ensoniq->irq >= 0)
1893 free_irq(ensoniq->irq, ensoniq);
1894 pci_release_regions(ensoniq->pci);
1895 pci_disable_device(ensoniq->pci);
1896 kfree(ensoniq);
1897 return 0;
1898}
1899
1900static int snd_ensoniq_dev_free(struct snd_device *device)
1901{
1902 struct ensoniq *ensoniq = device->device_data;
1903 return snd_ensoniq_free(ensoniq);
1904}
1905
1906#ifdef CHIP1371
1907static const struct snd_pci_quirk es1371_amplifier_hack[] = {
1908 SND_PCI_QUIRK_ID(0x107b, 0x2150), /* Gateway Solo 2150 */
1909 SND_PCI_QUIRK_ID(0x13bd, 0x100c), /* EV1938 on Mebius PC-MJ100V */
1910 SND_PCI_QUIRK_ID(0x1102, 0x5938), /* Targa Xtender300 */
1911 SND_PCI_QUIRK_ID(0x1102, 0x8938), /* IPC Topnote G notebook */
1912 {0} /* end */
1913};
1914
1915static const struct es1371_quirk es1371_ac97_reset_hack[] = {
1916 { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_CT5880, .rev = CT5880REV_CT5880_C },
1917 { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_CT5880, .rev = CT5880REV_CT5880_D },
1918 { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_CT5880, .rev = CT5880REV_CT5880_E },
1919 { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_ES1371, .rev = ES1371REV_CT5880_A },
1920 { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_ES1371, .rev = ES1371REV_ES1373_8 },
1921 { .vid = PCI_ANY_ID, .did = PCI_ANY_ID }
1922};
1923#endif
1924
1925static void snd_ensoniq_chip_init(struct ensoniq *ensoniq)
1926{
1927#ifdef CHIP1371
1928 int idx;
1929#endif
1930 /* this code was part of snd_ensoniq_create before intruduction
1931 * of suspend/resume
1932 */
1933#ifdef CHIP1370
1934 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
1935 outl(ensoniq->sctrl, ES_REG(ensoniq, SERIAL));
1936 outl(ES_MEM_PAGEO(ES_PAGE_ADC), ES_REG(ensoniq, MEM_PAGE));
1937 outl(ensoniq->dma_bug.addr, ES_REG(ensoniq, PHANTOM_FRAME));
1938 outl(0, ES_REG(ensoniq, PHANTOM_COUNT));
1939#else
1940 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
1941 outl(ensoniq->sctrl, ES_REG(ensoniq, SERIAL));
1942 outl(0, ES_REG(ensoniq, 1371_LEGACY));
1943 if (es1371_quirk_lookup(ensoniq, es1371_ac97_reset_hack)) {
1944 outl(ensoniq->cssr, ES_REG(ensoniq, STATUS));
1945 /* need to delay around 20ms(bleech) to give
1946 some CODECs enough time to wakeup */
1947 msleep(20);
1948 }
1949 /* AC'97 warm reset to start the bitclk */
1950 outl(ensoniq->ctrl | ES_1371_SYNC_RES, ES_REG(ensoniq, CONTROL));
1951 inl(ES_REG(ensoniq, CONTROL));
1952 udelay(20);
1953 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
1954 /* Init the sample rate converter */
1955 snd_es1371_wait_src_ready(ensoniq);
1956 outl(ES_1371_SRC_DISABLE, ES_REG(ensoniq, 1371_SMPRATE));
1957 for (idx = 0; idx < 0x80; idx++)
1958 snd_es1371_src_write(ensoniq, idx, 0);
1959 snd_es1371_src_write(ensoniq, ES_SMPREG_DAC1 + ES_SMPREG_TRUNC_N, 16 << 4);
1960 snd_es1371_src_write(ensoniq, ES_SMPREG_DAC1 + ES_SMPREG_INT_REGS, 16 << 10);
1961 snd_es1371_src_write(ensoniq, ES_SMPREG_DAC2 + ES_SMPREG_TRUNC_N, 16 << 4);
1962 snd_es1371_src_write(ensoniq, ES_SMPREG_DAC2 + ES_SMPREG_INT_REGS, 16 << 10);
1963 snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_ADC, 1 << 12);
1964 snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_ADC + 1, 1 << 12);
1965 snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_DAC1, 1 << 12);
1966 snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_DAC1 + 1, 1 << 12);
1967 snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_DAC2, 1 << 12);
1968 snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_DAC2 + 1, 1 << 12);
1969 snd_es1371_adc_rate(ensoniq, 22050);
1970 snd_es1371_dac1_rate(ensoniq, 22050);
1971 snd_es1371_dac2_rate(ensoniq, 22050);
1972 /* WARNING:
1973 * enabling the sample rate converter without properly programming
1974 * its parameters causes the chip to lock up (the SRC busy bit will
1975 * be stuck high, and I've found no way to rectify this other than
1976 * power cycle) - Thomas Sailer
1977 */
1978 snd_es1371_wait_src_ready(ensoniq);
1979 outl(0, ES_REG(ensoniq, 1371_SMPRATE));
1980 /* try reset codec directly */
1981 outl(ES_1371_CODEC_WRITE(0, 0), ES_REG(ensoniq, 1371_CODEC));
1982#endif
1983 outb(ensoniq->uartc = 0x00, ES_REG(ensoniq, UART_CONTROL));
1984 outb(0x00, ES_REG(ensoniq, UART_RES));
1985 outl(ensoniq->cssr, ES_REG(ensoniq, STATUS));
1986}
1987
1988#ifdef CONFIG_PM_SLEEP
1989static int snd_ensoniq_suspend(struct device *dev)
1990{
1991 struct snd_card *card = dev_get_drvdata(dev);
1992 struct ensoniq *ensoniq = card->private_data;
1993
1994 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
1995
1996#ifdef CHIP1371
1997 snd_ac97_suspend(ensoniq->u.es1371.ac97);
1998#else
1999 /* try to reset AK4531 */
2000 outw(ES_1370_CODEC_WRITE(AK4531_RESET, 0x02), ES_REG(ensoniq, 1370_CODEC));
2001 inw(ES_REG(ensoniq, 1370_CODEC));
2002 udelay(100);
2003 outw(ES_1370_CODEC_WRITE(AK4531_RESET, 0x03), ES_REG(ensoniq, 1370_CODEC));
2004 inw(ES_REG(ensoniq, 1370_CODEC));
2005 udelay(100);
2006 snd_ak4531_suspend(ensoniq->u.es1370.ak4531);
2007#endif
2008 return 0;
2009}
2010
2011static int snd_ensoniq_resume(struct device *dev)
2012{
2013 struct snd_card *card = dev_get_drvdata(dev);
2014 struct ensoniq *ensoniq = card->private_data;
2015
2016 snd_ensoniq_chip_init(ensoniq);
2017
2018#ifdef CHIP1371
2019 snd_ac97_resume(ensoniq->u.es1371.ac97);
2020#else
2021 snd_ak4531_resume(ensoniq->u.es1370.ak4531);
2022#endif
2023 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
2024 return 0;
2025}
2026
2027static SIMPLE_DEV_PM_OPS(snd_ensoniq_pm, snd_ensoniq_suspend, snd_ensoniq_resume);
2028#define SND_ENSONIQ_PM_OPS &snd_ensoniq_pm
2029#else
2030#define SND_ENSONIQ_PM_OPS NULL
2031#endif /* CONFIG_PM_SLEEP */
2032
2033static int snd_ensoniq_create(struct snd_card *card,
2034 struct pci_dev *pci,
2035 struct ensoniq **rensoniq)
2036{
2037 struct ensoniq *ensoniq;
2038 int err;
2039 static const struct snd_device_ops ops = {
2040 .dev_free = snd_ensoniq_dev_free,
2041 };
2042
2043 *rensoniq = NULL;
2044 if ((err = pci_enable_device(pci)) < 0)
2045 return err;
2046 ensoniq = kzalloc(sizeof(*ensoniq), GFP_KERNEL);
2047 if (ensoniq == NULL) {
2048 pci_disable_device(pci);
2049 return -ENOMEM;
2050 }
2051 spin_lock_init(&ensoniq->reg_lock);
2052 mutex_init(&ensoniq->src_mutex);
2053 ensoniq->card = card;
2054 ensoniq->pci = pci;
2055 ensoniq->irq = -1;
2056 if ((err = pci_request_regions(pci, "Ensoniq AudioPCI")) < 0) {
2057 kfree(ensoniq);
2058 pci_disable_device(pci);
2059 return err;
2060 }
2061 ensoniq->port = pci_resource_start(pci, 0);
2062 if (request_irq(pci->irq, snd_audiopci_interrupt, IRQF_SHARED,
2063 KBUILD_MODNAME, ensoniq)) {
2064 dev_err(card->dev, "unable to grab IRQ %d\n", pci->irq);
2065 snd_ensoniq_free(ensoniq);
2066 return -EBUSY;
2067 }
2068 ensoniq->irq = pci->irq;
2069 card->sync_irq = ensoniq->irq;
2070#ifdef CHIP1370
2071 if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, &pci->dev,
2072 16, &ensoniq->dma_bug) < 0) {
2073 dev_err(card->dev, "unable to allocate space for phantom area - dma_bug\n");
2074 snd_ensoniq_free(ensoniq);
2075 return -EBUSY;
2076 }
2077#endif
2078 pci_set_master(pci);
2079#ifndef TARGET_OS2
2080 ensoniq->rev = pci->revision;
2081#else
2082 ensoniq->rev = snd_pci_revision(pci);
2083#endif
2084#ifdef CHIP1370
2085#if 0
2086 ensoniq->ctrl = ES_1370_CDC_EN | ES_1370_SERR_DISABLE |
2087 ES_1370_PCLKDIVO(ES_1370_SRTODIV(8000));
2088#else /* get microphone working */
2089 ensoniq->ctrl = ES_1370_CDC_EN | ES_1370_PCLKDIVO(ES_1370_SRTODIV(8000));
2090#endif
2091 ensoniq->sctrl = 0;
2092#else
2093 ensoniq->ctrl = 0;
2094 ensoniq->sctrl = 0;
2095 ensoniq->cssr = 0;
2096 if (snd_pci_quirk_lookup(pci, es1371_amplifier_hack))
2097 ensoniq->ctrl |= ES_1371_GPIO_OUT(1); /* turn amplifier on */
2098
2099 if (es1371_quirk_lookup(ensoniq, es1371_ac97_reset_hack))
2100 ensoniq->cssr |= ES_1371_ST_AC97_RST;
2101#endif
2102
2103 snd_ensoniq_chip_init(ensoniq);
2104
2105 if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, ensoniq, &ops)) < 0) {
2106 snd_ensoniq_free(ensoniq);
2107 return err;
2108 }
2109
2110 snd_ensoniq_proc_init(ensoniq);
2111
2112 *rensoniq = ensoniq;
2113 return 0;
2114}
2115
2116/*
2117 * MIDI section
2118 */
2119
2120static void snd_ensoniq_midi_interrupt(struct ensoniq * ensoniq)
2121{
2122 struct snd_rawmidi *rmidi = ensoniq->rmidi;
2123 unsigned char status, mask, byte;
2124
2125 if (rmidi == NULL)
2126 return;
2127 /* do Rx at first */
2128 spin_lock(&ensoniq->reg_lock);
2129 mask = ensoniq->uartm & ES_MODE_INPUT ? ES_RXRDY : 0;
2130 while (mask) {
2131 status = inb(ES_REG(ensoniq, UART_STATUS));
2132 if ((status & mask) == 0)
2133 break;
2134 byte = inb(ES_REG(ensoniq, UART_DATA));
2135 snd_rawmidi_receive(ensoniq->midi_input, &byte, 1);
2136 }
2137 spin_unlock(&ensoniq->reg_lock);
2138
2139 /* do Tx at second */
2140 spin_lock(&ensoniq->reg_lock);
2141 mask = ensoniq->uartm & ES_MODE_OUTPUT ? ES_TXRDY : 0;
2142 while (mask) {
2143 status = inb(ES_REG(ensoniq, UART_STATUS));
2144 if ((status & mask) == 0)
2145 break;
2146 if (snd_rawmidi_transmit(ensoniq->midi_output, &byte, 1) != 1) {
2147 ensoniq->uartc &= ~ES_TXINTENM;
2148 outb(ensoniq->uartc, ES_REG(ensoniq, UART_CONTROL));
2149 mask &= ~ES_TXRDY;
2150 } else {
2151 outb(byte, ES_REG(ensoniq, UART_DATA));
2152 }
2153 }
2154 spin_unlock(&ensoniq->reg_lock);
2155}
2156
2157static int snd_ensoniq_midi_input_open(struct snd_rawmidi_substream *substream)
2158{
2159 struct ensoniq *ensoniq = substream->rmidi->private_data;
2160
2161 spin_lock_irq(&ensoniq->reg_lock);
2162 ensoniq->uartm |= ES_MODE_INPUT;
2163 ensoniq->midi_input = substream;
2164 if (!(ensoniq->uartm & ES_MODE_OUTPUT)) {
2165 outb(ES_CNTRL(3), ES_REG(ensoniq, UART_CONTROL));
2166 outb(ensoniq->uartc = 0, ES_REG(ensoniq, UART_CONTROL));
2167 outl(ensoniq->ctrl |= ES_UART_EN, ES_REG(ensoniq, CONTROL));
2168 }
2169 spin_unlock_irq(&ensoniq->reg_lock);
2170 return 0;
2171}
2172
2173static int snd_ensoniq_midi_input_close(struct snd_rawmidi_substream *substream)
2174{
2175 struct ensoniq *ensoniq = substream->rmidi->private_data;
2176
2177 spin_lock_irq(&ensoniq->reg_lock);
2178 if (!(ensoniq->uartm & ES_MODE_OUTPUT)) {
2179 outb(ensoniq->uartc = 0, ES_REG(ensoniq, UART_CONTROL));
2180 outl(ensoniq->ctrl &= ~ES_UART_EN, ES_REG(ensoniq, CONTROL));
2181 } else {
2182 outb(ensoniq->uartc &= ~ES_RXINTEN, ES_REG(ensoniq, UART_CONTROL));
2183 }
2184 ensoniq->midi_input = NULL;
2185 ensoniq->uartm &= ~ES_MODE_INPUT;
2186 spin_unlock_irq(&ensoniq->reg_lock);
2187 return 0;
2188}
2189
2190static int snd_ensoniq_midi_output_open(struct snd_rawmidi_substream *substream)
2191{
2192 struct ensoniq *ensoniq = substream->rmidi->private_data;
2193
2194 spin_lock_irq(&ensoniq->reg_lock);
2195 ensoniq->uartm |= ES_MODE_OUTPUT;
2196 ensoniq->midi_output = substream;
2197 if (!(ensoniq->uartm & ES_MODE_INPUT)) {
2198 outb(ES_CNTRL(3), ES_REG(ensoniq, UART_CONTROL));
2199 outb(ensoniq->uartc = 0, ES_REG(ensoniq, UART_CONTROL));
2200 outl(ensoniq->ctrl |= ES_UART_EN, ES_REG(ensoniq, CONTROL));
2201 }
2202 spin_unlock_irq(&ensoniq->reg_lock);
2203 return 0;
2204}
2205
2206static int snd_ensoniq_midi_output_close(struct snd_rawmidi_substream *substream)
2207{
2208 struct ensoniq *ensoniq = substream->rmidi->private_data;
2209
2210 spin_lock_irq(&ensoniq->reg_lock);
2211 if (!(ensoniq->uartm & ES_MODE_INPUT)) {
2212 outb(ensoniq->uartc = 0, ES_REG(ensoniq, UART_CONTROL));
2213 outl(ensoniq->ctrl &= ~ES_UART_EN, ES_REG(ensoniq, CONTROL));
2214 } else {
2215 outb(ensoniq->uartc &= ~ES_TXINTENM, ES_REG(ensoniq, UART_CONTROL));
2216 }
2217 ensoniq->midi_output = NULL;
2218 ensoniq->uartm &= ~ES_MODE_OUTPUT;
2219 spin_unlock_irq(&ensoniq->reg_lock);
2220 return 0;
2221}
2222
2223static void snd_ensoniq_midi_input_trigger(struct snd_rawmidi_substream *substream, int up)
2224{
2225 unsigned long flags;
2226 struct ensoniq *ensoniq = substream->rmidi->private_data;
2227 int idx;
2228
2229 spin_lock_irqsave(&ensoniq->reg_lock, flags);
2230 if (up) {
2231 if ((ensoniq->uartc & ES_RXINTEN) == 0) {
2232 /* empty input FIFO */
2233 for (idx = 0; idx < 32; idx++)
2234 inb(ES_REG(ensoniq, UART_DATA));
2235 ensoniq->uartc |= ES_RXINTEN;
2236 outb(ensoniq->uartc, ES_REG(ensoniq, UART_CONTROL));
2237 }
2238 } else {
2239 if (ensoniq->uartc & ES_RXINTEN) {
2240 ensoniq->uartc &= ~ES_RXINTEN;
2241 outb(ensoniq->uartc, ES_REG(ensoniq, UART_CONTROL));
2242 }
2243 }
2244 spin_unlock_irqrestore(&ensoniq->reg_lock, flags);
2245}
2246
2247static void snd_ensoniq_midi_output_trigger(struct snd_rawmidi_substream *substream, int up)
2248{
2249 unsigned long flags;
2250 struct ensoniq *ensoniq = substream->rmidi->private_data;
2251 unsigned char byte;
2252
2253 spin_lock_irqsave(&ensoniq->reg_lock, flags);
2254 if (up) {
2255 if (ES_TXINTENI(ensoniq->uartc) == 0) {
2256 ensoniq->uartc |= ES_TXINTENO(1);
2257 /* fill UART FIFO buffer at first, and turn Tx interrupts only if necessary */
2258 while (ES_TXINTENI(ensoniq->uartc) == 1 &&
2259 (inb(ES_REG(ensoniq, UART_STATUS)) & ES_TXRDY)) {
2260 if (snd_rawmidi_transmit(substream, &byte, 1) != 1) {
2261 ensoniq->uartc &= ~ES_TXINTENM;
2262 } else {
2263 outb(byte, ES_REG(ensoniq, UART_DATA));
2264 }
2265 }
2266 outb(ensoniq->uartc, ES_REG(ensoniq, UART_CONTROL));
2267 }
2268 } else {
2269 if (ES_TXINTENI(ensoniq->uartc) == 1) {
2270 ensoniq->uartc &= ~ES_TXINTENM;
2271 outb(ensoniq->uartc, ES_REG(ensoniq, UART_CONTROL));
2272 }
2273 }
2274 spin_unlock_irqrestore(&ensoniq->reg_lock, flags);
2275}
2276
2277static const struct snd_rawmidi_ops snd_ensoniq_midi_output =
2278{
2279 .open = snd_ensoniq_midi_output_open,
2280 .close = snd_ensoniq_midi_output_close,
2281 .trigger = snd_ensoniq_midi_output_trigger,
2282};
2283
2284static const struct snd_rawmidi_ops snd_ensoniq_midi_input =
2285{
2286 .open = snd_ensoniq_midi_input_open,
2287 .close = snd_ensoniq_midi_input_close,
2288 .trigger = snd_ensoniq_midi_input_trigger,
2289};
2290
2291static int snd_ensoniq_midi(struct ensoniq *ensoniq, int device)
2292{
2293 struct snd_rawmidi *rmidi;
2294 int err;
2295
2296 if ((err = snd_rawmidi_new(ensoniq->card, "ES1370/1", device, 1, 1, &rmidi)) < 0)
2297 return err;
2298 strcpy(rmidi->name, CHIP_NAME);
2299 snd_rawmidi_set_ops(rmidi, SNDRV_RAWMIDI_STREAM_OUTPUT, &snd_ensoniq_midi_output);
2300 snd_rawmidi_set_ops(rmidi, SNDRV_RAWMIDI_STREAM_INPUT, &snd_ensoniq_midi_input);
2301 rmidi->info_flags |= SNDRV_RAWMIDI_INFO_OUTPUT | SNDRV_RAWMIDI_INFO_INPUT |
2302 SNDRV_RAWMIDI_INFO_DUPLEX;
2303 rmidi->private_data = ensoniq;
2304 ensoniq->rmidi = rmidi;
2305 return 0;
2306}
2307
2308/*
2309 * Interrupt handler
2310 */
2311
2312static irqreturn_t snd_audiopci_interrupt(int irq, void *dev_id)
2313{
2314 struct ensoniq *ensoniq = dev_id;
2315 unsigned int status, sctrl;
2316
2317 if (ensoniq == NULL)
2318 return IRQ_NONE;
2319
2320 status = inl(ES_REG(ensoniq, STATUS));
2321 if (!(status & ES_INTR))
2322 return IRQ_NONE;
2323
2324 spin_lock(&ensoniq->reg_lock);
2325 sctrl = ensoniq->sctrl;
2326 if (status & ES_DAC1)
2327 sctrl &= ~ES_P1_INT_EN;
2328 if (status & ES_DAC2)
2329 sctrl &= ~ES_P2_INT_EN;
2330 if (status & ES_ADC)
2331 sctrl &= ~ES_R1_INT_EN;
2332 outl(sctrl, ES_REG(ensoniq, SERIAL));
2333 outl(ensoniq->sctrl, ES_REG(ensoniq, SERIAL));
2334 spin_unlock(&ensoniq->reg_lock);
2335
2336 if (status & ES_UART)
2337 snd_ensoniq_midi_interrupt(ensoniq);
2338 if ((status & ES_DAC2) && ensoniq->playback2_substream)
2339 snd_pcm_period_elapsed(ensoniq->playback2_substream);
2340 if ((status & ES_ADC) && ensoniq->capture_substream)
2341 snd_pcm_period_elapsed(ensoniq->capture_substream);
2342 if ((status & ES_DAC1) && ensoniq->playback1_substream)
2343 snd_pcm_period_elapsed(ensoniq->playback1_substream);
2344 return IRQ_HANDLED;
2345}
2346
2347static int snd_audiopci_probe(struct pci_dev *pci,
2348 const struct pci_device_id *pci_id)
2349{
2350 static int dev;
2351 struct snd_card *card;
2352 struct ensoniq *ensoniq;
2353 int err;
2354
2355 if (dev >= SNDRV_CARDS)
2356 return -ENODEV;
2357 if (!enable[dev]) {
2358 dev++;
2359 return -ENOENT;
2360 }
2361
2362 err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE,
2363 0, &card);
2364 if (err < 0)
2365 return err;
2366
2367 if ((err = snd_ensoniq_create(card, pci, &ensoniq)) < 0) {
2368 snd_card_free(card);
2369 return err;
2370 }
2371 card->private_data = ensoniq;
2372
2373#ifdef CHIP1370
2374 if ((err = snd_ensoniq_1370_mixer(ensoniq)) < 0) {
2375 snd_card_free(card);
2376 return err;
2377 }
2378#endif
2379#ifdef CHIP1371
2380 if ((err = snd_ensoniq_1371_mixer(ensoniq, spdif[dev], lineio[dev])) < 0) {
2381 snd_card_free(card);
2382 return err;
2383 }
2384#endif
2385 if ((err = snd_ensoniq_pcm(ensoniq, 0)) < 0) {
2386 snd_card_free(card);
2387 return err;
2388 }
2389 if ((err = snd_ensoniq_pcm2(ensoniq, 1)) < 0) {
2390 snd_card_free(card);
2391 return err;
2392 }
2393 if ((err = snd_ensoniq_midi(ensoniq, 0)) < 0) {
2394 snd_card_free(card);
2395 return err;
2396 }
2397
2398 snd_ensoniq_create_gameport(ensoniq, dev);
2399
2400 strcpy(card->driver, DRIVER_NAME);
2401
2402 strcpy(card->shortname, "Ensoniq AudioPCI");
2403 sprintf(card->longname, "%s %s at 0x%lx, irq %i",
2404 card->shortname,
2405 card->driver,
2406 ensoniq->port,
2407 ensoniq->irq);
2408
2409 if ((err = snd_card_register(card)) < 0) {
2410 snd_card_free(card);
2411 return err;
2412 }
2413
2414 pci_set_drvdata(pci, card);
2415 dev++;
2416 return 0;
2417}
2418
2419static void snd_audiopci_remove(struct pci_dev *pci)
2420{
2421 snd_card_free(pci_get_drvdata(pci));
2422}
2423
2424static struct pci_driver ens137x_driver = {
2425 .name = KBUILD_MODNAME,
2426 .id_table = snd_audiopci_ids,
2427 .probe = snd_audiopci_probe,
2428 .remove = snd_audiopci_remove,
2429 .driver = {
2430 .pm = SND_ENSONIQ_PM_OPS,
2431 },
2432};
2433
2434module_pci_driver(ens137x_driver);
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