source: GPL/trunk/alsa-kernel/pci/ens1370.c@ 680

Last change on this file since 680 was 679, checked in by David Azarewicz, 5 years ago

Merge changes from Paul's uniaud32next branch.
File size: 79.4 KB
Line 
1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Driver for Ensoniq ES1370/ES1371 AudioPCI soundcard
4 * Copyright (c) by Jaroslav Kysela <perex@perex.cz>,
5 * Thomas Sailer <sailer@ife.ee.ethz.ch>
6 */
7
8/* Power-Management-Code ( CONFIG_PM )
9 * for ens1371 only ( FIXME )
10 * derived from cs4281.c, atiixp.c and via82xx.c
11 * using http://www.alsa-project.org/~tiwai/writing-an-alsa-driver/
12 * by Kurt J. Bosch
13 */
14
15#include <linux/io.h>
16#include <linux/delay.h>
17#include <linux/interrupt.h>
18#include <linux/init.h>
19#include <linux/pci.h>
20#include <linux/slab.h>
21#include <linux/gameport.h>
22#include <linux/module.h>
23#include <linux/mutex.h>
24
25#include <sound/core.h>
26#include <sound/control.h>
27#include <sound/pcm.h>
28#include <sound/rawmidi.h>
29#ifdef CHIP1371
30#include <sound/ac97_codec.h>
31#else
32#include <sound/ak4531_codec.h>
33#endif
34#include <sound/initval.h>
35#include <sound/asoundef.h>
36
37#ifndef CHIP1371
38#undef CHIP1370
39#define CHIP1370
40#endif
41
42#ifdef CHIP1370
43#define DRIVER_NAME "ENS1370"
44#define CHIP_NAME "ES1370" /* it can be ENS but just to keep compatibility... */
45#else
46#define DRIVER_NAME "ENS1371"
47#define CHIP_NAME "ES1371"
48#endif
49
50
51#ifdef TARGET_OS2
52#define KBUILD_MODNAME "ens137x"
53#endif
54MODULE_AUTHOR("Jaroslav Kysela <perex@perex.cz>, Thomas Sailer <sailer@ife.ee.ethz.ch>");
55MODULE_LICENSE("GPL");
56#ifdef CHIP1370
57MODULE_DESCRIPTION("Ensoniq AudioPCI ES1370");
58MODULE_SUPPORTED_DEVICE("{{Ensoniq,AudioPCI-97 ES1370},"
59 "{Creative Labs,SB PCI64/128 (ES1370)}}");
60#endif
61#ifdef CHIP1371
62MODULE_DESCRIPTION("Ensoniq/Creative AudioPCI ES1371+");
63MODULE_SUPPORTED_DEVICE("{{Ensoniq,AudioPCI ES1371/73},"
64 "{Ensoniq,AudioPCI ES1373},"
65 "{Creative Labs,Ectiva EV1938},"
66 "{Creative Labs,SB PCI64/128 (ES1371/73)},"
67 "{Creative Labs,Vibra PCI128},"
68 "{Ectiva,EV1938}}");
69#endif
70
71#if IS_REACHABLE(CONFIG_GAMEPORT)
72#define SUPPORT_JOYSTICK
73#endif
74
75static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
76static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
77static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable switches */
78#ifdef SUPPORT_JOYSTICK
79#ifdef CHIP1371
80static int joystick_port[SNDRV_CARDS];
81#else
82static bool joystick[SNDRV_CARDS];
83#endif
84#endif
85#ifdef CHIP1371
86static int spdif[SNDRV_CARDS];
87static int lineio[SNDRV_CARDS];
88#endif
89
90module_param_array(index, int, NULL, 0444);
91MODULE_PARM_DESC(index, "Index value for Ensoniq AudioPCI soundcard.");
92module_param_array(id, charp, NULL, 0444);
93MODULE_PARM_DESC(id, "ID string for Ensoniq AudioPCI soundcard.");
94module_param_array(enable, bool, NULL, 0444);
95MODULE_PARM_DESC(enable, "Enable Ensoniq AudioPCI soundcard.");
96#ifdef SUPPORT_JOYSTICK
97#ifdef CHIP1371
98module_param_hw_array(joystick_port, int, ioport, NULL, 0444);
99MODULE_PARM_DESC(joystick_port, "Joystick port address.");
100#else
101module_param_array(joystick, bool, NULL, 0444);
102MODULE_PARM_DESC(joystick, "Enable joystick.");
103#endif
104#endif /* SUPPORT_JOYSTICK */
105#ifdef CHIP1371
106module_param_array(spdif, int, NULL, 0444);
107MODULE_PARM_DESC(spdif, "S/PDIF output (-1 = none, 0 = auto, 1 = force).");
108module_param_array(lineio, int, NULL, 0444);
109MODULE_PARM_DESC(lineio, "Line In to Rear Out (0 = auto, 1 = force).");
110#endif
111
112/* ES1371 chip ID */
113/* This is a little confusing because all ES1371 compatible chips have the
114 same DEVICE_ID, the only thing differentiating them is the REV_ID field.
115 This is only significant if you want to enable features on the later parts.
116 Yes, I know it's stupid and why didn't we use the sub IDs?
117*/
118#define ES1371REV_ES1373_A 0x04
119#define ES1371REV_ES1373_B 0x06
120#define ES1371REV_CT5880_A 0x07
121#define CT5880REV_CT5880_C 0x02
122#define CT5880REV_CT5880_D 0x03 /* ??? -jk */
123#define CT5880REV_CT5880_E 0x04 /* mw */
124#define ES1371REV_ES1371_B 0x09
125#define EV1938REV_EV1938_A 0x00
126#define ES1371REV_ES1373_8 0x08
127
128/*
129 * Direct registers
130 */
131
132#define ES_REG(ensoniq, x) ((ensoniq)->port + ES_REG_##x)
133
134#define ES_REG_CONTROL 0x00 /* R/W: Interrupt/Chip select control register */
135#define ES_1370_ADC_STOP (1<<31) /* disable capture buffer transfers */
136#define ES_1370_XCTL1 (1<<30) /* general purpose output bit */
137#define ES_1373_BYPASS_P1 (1<<31) /* bypass SRC for PB1 */
138#define ES_1373_BYPASS_P2 (1<<30) /* bypass SRC for PB2 */
139#define ES_1373_BYPASS_R (1<<29) /* bypass SRC for REC */
140#define ES_1373_TEST_BIT (1<<28) /* should be set to 0 for normal operation */
141#define ES_1373_RECEN_B (1<<27) /* mix record with playback for I2S/SPDIF out */
142#define ES_1373_SPDIF_THRU (1<<26) /* 0 = SPDIF thru mode, 1 = SPDIF == dig out */
143#define ES_1371_JOY_ASEL(o) (((o)&0x03)<<24)/* joystick port mapping */
144#define ES_1371_JOY_ASELM (0x03<<24) /* mask for above */
145#define ES_1371_JOY_ASELI(i) (((i)>>24)&0x03)
146#define ES_1371_GPIO_IN(i) (((i)>>20)&0x0f)/* GPIO in [3:0] pins - R/O */
147#define ES_1370_PCLKDIVO(o) (((o)&0x1fff)<<16)/* clock divide ratio for DAC2 */
148#define ES_1370_PCLKDIVM ((0x1fff)<<16) /* mask for above */
149#define ES_1370_PCLKDIVI(i) (((i)>>16)&0x1fff)/* clock divide ratio for DAC2 */
150#define ES_1371_GPIO_OUT(o) (((o)&0x0f)<<16)/* GPIO out [3:0] pins - W/R */
151#define ES_1371_GPIO_OUTM (0x0f<<16) /* mask for above */
152#define ES_MSFMTSEL (1<<15) /* MPEG serial data format; 0 = SONY, 1 = I2S */
153#define ES_1370_M_SBB (1<<14) /* clock source for DAC - 0 = clock generator; 1 = MPEG clocks */
154#define ES_1371_SYNC_RES (1<<14) /* Warm AC97 reset */
155#define ES_1370_WTSRSEL(o) (((o)&0x03)<<12)/* fixed frequency clock for DAC1 */
156#define ES_1370_WTSRSELM (0x03<<12) /* mask for above */
157#define ES_1371_ADC_STOP (1<<13) /* disable CCB transfer capture information */
158#define ES_1371_PWR_INTRM (1<<12) /* power level change interrupts enable */
159#define ES_1370_DAC_SYNC (1<<11) /* DAC's are synchronous */
160#define ES_1371_M_CB (1<<11) /* capture clock source; 0 = AC'97 ADC; 1 = I2S */
161#define ES_CCB_INTRM (1<<10) /* CCB voice interrupts enable */
162#define ES_1370_M_CB (1<<9) /* capture clock source; 0 = ADC; 1 = MPEG */
163#define ES_1370_XCTL0 (1<<8) /* generap purpose output bit */
164#define ES_1371_PDLEV(o) (((o)&0x03)<<8) /* current power down level */
165#define ES_1371_PDLEVM (0x03<<8) /* mask for above */
166#define ES_BREQ (1<<7) /* memory bus request enable */
167#define ES_DAC1_EN (1<<6) /* DAC1 playback channel enable */
168#define ES_DAC2_EN (1<<5) /* DAC2 playback channel enable */
169#define ES_ADC_EN (1<<4) /* ADC capture channel enable */
170#define ES_UART_EN (1<<3) /* UART enable */
171#define ES_JYSTK_EN (1<<2) /* Joystick module enable */
172#define ES_1370_CDC_EN (1<<1) /* Codec interface enable */
173#define ES_1371_XTALCKDIS (1<<1) /* Xtal clock disable */
174#define ES_1370_SERR_DISABLE (1<<0) /* PCI serr signal disable */
175#define ES_1371_PCICLKDIS (1<<0) /* PCI clock disable */
176#define ES_REG_STATUS 0x04 /* R/O: Interrupt/Chip select status register */
177#define ES_INTR (1<<31) /* Interrupt is pending */
178#define ES_1371_ST_AC97_RST (1<<29) /* CT5880 AC'97 Reset bit */
179#define ES_1373_REAR_BIT27 (1<<27) /* rear bits: 000 - front, 010 - mirror, 101 - separate */
180#define ES_1373_REAR_BIT26 (1<<26)
181#define ES_1373_REAR_BIT24 (1<<24)
182#define ES_1373_GPIO_INT_EN(o)(((o)&0x0f)<<20)/* GPIO [3:0] pins - interrupt enable */
183#define ES_1373_SPDIF_EN (1<<18) /* SPDIF enable */
184#define ES_1373_SPDIF_TEST (1<<17) /* SPDIF test */
185#define ES_1371_TEST (1<<16) /* test ASIC */
186#define ES_1373_GPIO_INT(i) (((i)&0x0f)>>12)/* GPIO [3:0] pins - interrupt pending */
187#define ES_1370_CSTAT (1<<10) /* CODEC is busy or register write in progress */
188#define ES_1370_CBUSY (1<<9) /* CODEC is busy */
189#define ES_1370_CWRIP (1<<8) /* CODEC register write in progress */
190#define ES_1371_SYNC_ERR (1<<8) /* CODEC synchronization error occurred */
191#define ES_1371_VC(i) (((i)>>6)&0x03) /* voice code from CCB module */
192#define ES_1370_VC(i) (((i)>>5)&0x03) /* voice code from CCB module */
193#define ES_1371_MPWR (1<<5) /* power level interrupt pending */
194#define ES_MCCB (1<<4) /* CCB interrupt pending */
195#define ES_UART (1<<3) /* UART interrupt pending */
196#define ES_DAC1 (1<<2) /* DAC1 channel interrupt pending */
197#define ES_DAC2 (1<<1) /* DAC2 channel interrupt pending */
198#define ES_ADC (1<<0) /* ADC channel interrupt pending */
199#define ES_REG_UART_DATA 0x08 /* R/W: UART data register */
200#define ES_REG_UART_STATUS 0x09 /* R/O: UART status register */
201#define ES_RXINT (1<<7) /* RX interrupt occurred */
202#define ES_TXINT (1<<2) /* TX interrupt occurred */
203#define ES_TXRDY (1<<1) /* transmitter ready */
204#define ES_RXRDY (1<<0) /* receiver ready */
205#define ES_REG_UART_CONTROL 0x09 /* W/O: UART control register */
206#define ES_RXINTEN (1<<7) /* RX interrupt enable */
207#define ES_TXINTENO(o) (((o)&0x03)<<5) /* TX interrupt enable */
208#define ES_TXINTENM (0x03<<5) /* mask for above */
209#define ES_TXINTENI(i) (((i)>>5)&0x03)
210#define ES_CNTRL(o) (((o)&0x03)<<0) /* control */
211#define ES_CNTRLM (0x03<<0) /* mask for above */
212#define ES_REG_UART_RES 0x0a /* R/W: UART reserver register */
213#define ES_TEST_MODE (1<<0) /* test mode enabled */
214#define ES_REG_MEM_PAGE 0x0c /* R/W: Memory page register */
215#define ES_MEM_PAGEO(o) (((o)&0x0f)<<0) /* memory page select - out */
216#define ES_MEM_PAGEM (0x0f<<0) /* mask for above */
217#define ES_MEM_PAGEI(i) (((i)>>0)&0x0f) /* memory page select - in */
218#define ES_REG_1370_CODEC 0x10 /* W/O: Codec write register address */
219#define ES_1370_CODEC_WRITE(a,d) ((((a)&0xff)<<8)|(((d)&0xff)<<0))
220#define ES_REG_1371_CODEC 0x14 /* W/R: Codec Read/Write register address */
221#define ES_1371_CODEC_RDY (1<<31) /* codec ready */
222#define ES_1371_CODEC_WIP (1<<30) /* codec register access in progress */
223#define EV_1938_CODEC_MAGIC (1<<26)
224#define ES_1371_CODEC_PIRD (1<<23) /* codec read/write select register */
225#define ES_1371_CODEC_WRITE(a,d) ((((a)&0x7f)<<16)|(((d)&0xffff)<<0))
226#define ES_1371_CODEC_READS(a) ((((a)&0x7f)<<16)|ES_1371_CODEC_PIRD)
227#define ES_1371_CODEC_READ(i) (((i)>>0)&0xffff)
228
229#define ES_REG_1371_SMPRATE 0x10 /* W/R: Codec rate converter interface register */
230#define ES_1371_SRC_RAM_ADDRO(o) (((o)&0x7f)<<25)/* address of the sample rate converter */
231#define ES_1371_SRC_RAM_ADDRM (0x7f<<25) /* mask for above */
232#define ES_1371_SRC_RAM_ADDRI(i) (((i)>>25)&0x7f)/* address of the sample rate converter */
233#define ES_1371_SRC_RAM_WE (1<<24) /* R/W: read/write control for sample rate converter */
234#define ES_1371_SRC_RAM_BUSY (1<<23) /* R/O: sample rate memory is busy */
235#define ES_1371_SRC_DISABLE (1<<22) /* sample rate converter disable */
236#define ES_1371_DIS_P1 (1<<21) /* playback channel 1 accumulator update disable */
237#define ES_1371_DIS_P2 (1<<20) /* playback channel 1 accumulator update disable */
238#define ES_1371_DIS_R1 (1<<19) /* capture channel accumulator update disable */
239#define ES_1371_SRC_RAM_DATAO(o) (((o)&0xffff)<<0)/* current value of the sample rate converter */
240#define ES_1371_SRC_RAM_DATAM (0xffff<<0) /* mask for above */
241#define ES_1371_SRC_RAM_DATAI(i) (((i)>>0)&0xffff)/* current value of the sample rate converter */
242
243#define ES_REG_1371_LEGACY 0x18 /* W/R: Legacy control/status register */
244#define ES_1371_JFAST (1<<31) /* fast joystick timing */
245#define ES_1371_HIB (1<<30) /* host interrupt blocking enable */
246#define ES_1371_VSB (1<<29) /* SB; 0 = addr 0x220xH, 1 = 0x22FxH */
247#define ES_1371_VMPUO(o) (((o)&0x03)<<27)/* base register address; 0 = 0x320xH; 1 = 0x330xH; 2 = 0x340xH; 3 = 0x350xH */
248#define ES_1371_VMPUM (0x03<<27) /* mask for above */
249#define ES_1371_VMPUI(i) (((i)>>27)&0x03)/* base register address */
250#define ES_1371_VCDCO(o) (((o)&0x03)<<25)/* CODEC; 0 = 0x530xH; 1 = undefined; 2 = 0xe80xH; 3 = 0xF40xH */
251#define ES_1371_VCDCM (0x03<<25) /* mask for above */
252#define ES_1371_VCDCI(i) (((i)>>25)&0x03)/* CODEC address */
253#define ES_1371_FIRQ (1<<24) /* force an interrupt */
254#define ES_1371_SDMACAP (1<<23) /* enable event capture for slave DMA controller */
255#define ES_1371_SPICAP (1<<22) /* enable event capture for slave IRQ controller */
256#define ES_1371_MDMACAP (1<<21) /* enable event capture for master DMA controller */
257#define ES_1371_MPICAP (1<<20) /* enable event capture for master IRQ controller */
258#define ES_1371_ADCAP (1<<19) /* enable event capture for ADLIB register; 0x388xH */
259#define ES_1371_SVCAP (1<<18) /* enable event capture for SB registers */
260#define ES_1371_CDCCAP (1<<17) /* enable event capture for CODEC registers */
261#define ES_1371_BACAP (1<<16) /* enable event capture for SoundScape base address */
262#define ES_1371_EXI(i) (((i)>>8)&0x07) /* event number */
263#define ES_1371_AI(i) (((i)>>3)&0x1f) /* event significant I/O address */
264#define ES_1371_WR (1<<2) /* event capture; 0 = read; 1 = write */
265#define ES_1371_LEGINT (1<<0) /* interrupt for legacy events; 0 = interrupt did occur */
266
267#define ES_REG_CHANNEL_STATUS 0x1c /* R/W: first 32-bits from S/PDIF channel status block, es1373 */
268
269#define ES_REG_SERIAL 0x20 /* R/W: Serial interface control register */
270#define ES_1371_DAC_TEST (1<<22) /* DAC test mode enable */
271#define ES_P2_END_INCO(o) (((o)&0x07)<<19)/* binary offset value to increment / loop end */
272#define ES_P2_END_INCM (0x07<<19) /* mask for above */
273#define ES_P2_END_INCI(i) (((i)>>16)&0x07)/* binary offset value to increment / loop end */
274#define ES_P2_ST_INCO(o) (((o)&0x07)<<16)/* binary offset value to increment / start */
275#define ES_P2_ST_INCM (0x07<<16) /* mask for above */
276#define ES_P2_ST_INCI(i) (((i)<<16)&0x07)/* binary offset value to increment / start */
277#define ES_R1_LOOP_SEL (1<<15) /* ADC; 0 - loop mode; 1 = stop mode */
278#define ES_P2_LOOP_SEL (1<<14) /* DAC2; 0 - loop mode; 1 = stop mode */
279#define ES_P1_LOOP_SEL (1<<13) /* DAC1; 0 - loop mode; 1 = stop mode */
280#define ES_P2_PAUSE (1<<12) /* DAC2; 0 - play mode; 1 = pause mode */
281#define ES_P1_PAUSE (1<<11) /* DAC1; 0 - play mode; 1 = pause mode */
282#define ES_R1_INT_EN (1<<10) /* ADC interrupt enable */
283#define ES_P2_INT_EN (1<<9) /* DAC2 interrupt enable */
284#define ES_P1_INT_EN (1<<8) /* DAC1 interrupt enable */
285#define ES_P1_SCT_RLD (1<<7) /* force sample counter reload for DAC1 */
286#define ES_P2_DAC_SEN (1<<6) /* when stop mode: 0 - DAC2 play back zeros; 1 = DAC2 play back last sample */
287#define ES_R1_MODEO(o) (((o)&0x03)<<4) /* ADC mode; 0 = 8-bit mono; 1 = 8-bit stereo; 2 = 16-bit mono; 3 = 16-bit stereo */
288#define ES_R1_MODEM (0x03<<4) /* mask for above */
289#define ES_R1_MODEI(i) (((i)>>4)&0x03)
290#define ES_P2_MODEO(o) (((o)&0x03)<<2) /* DAC2 mode; -- '' -- */
291#define ES_P2_MODEM (0x03<<2) /* mask for above */
292#define ES_P2_MODEI(i) (((i)>>2)&0x03)
293#define ES_P1_MODEO(o) (((o)&0x03)<<0) /* DAC1 mode; -- '' -- */
294#define ES_P1_MODEM (0x03<<0) /* mask for above */
295#define ES_P1_MODEI(i) (((i)>>0)&0x03)
296
297#define ES_REG_DAC1_COUNT 0x24 /* R/W: DAC1 sample count register */
298#define ES_REG_DAC2_COUNT 0x28 /* R/W: DAC2 sample count register */
299#define ES_REG_ADC_COUNT 0x2c /* R/W: ADC sample count register */
300#define ES_REG_CURR_COUNT(i) (((i)>>16)&0xffff)
301#define ES_REG_COUNTO(o) (((o)&0xffff)<<0)
302#define ES_REG_COUNTM (0xffff<<0)
303#define ES_REG_COUNTI(i) (((i)>>0)&0xffff)
304
305#define ES_REG_DAC1_FRAME 0x30 /* R/W: PAGE 0x0c; DAC1 frame address */
306#define ES_REG_DAC1_SIZE 0x34 /* R/W: PAGE 0x0c; DAC1 frame size */
307#define ES_REG_DAC2_FRAME 0x38 /* R/W: PAGE 0x0c; DAC2 frame address */
308#define ES_REG_DAC2_SIZE 0x3c /* R/W: PAGE 0x0c; DAC2 frame size */
309#define ES_REG_ADC_FRAME 0x30 /* R/W: PAGE 0x0d; ADC frame address */
310#define ES_REG_ADC_SIZE 0x34 /* R/W: PAGE 0x0d; ADC frame size */
311#define ES_REG_FCURR_COUNTO(o) (((o)&0xffff)<<16)
312#define ES_REG_FCURR_COUNTM (0xffff<<16)
313#define ES_REG_FCURR_COUNTI(i) (((i)>>14)&0x3fffc)
314#define ES_REG_FSIZEO(o) (((o)&0xffff)<<0)
315#define ES_REG_FSIZEM (0xffff<<0)
316#define ES_REG_FSIZEI(i) (((i)>>0)&0xffff)
317#define ES_REG_PHANTOM_FRAME 0x38 /* R/W: PAGE 0x0d: phantom frame address */
318#define ES_REG_PHANTOM_COUNT 0x3c /* R/W: PAGE 0x0d: phantom frame count */
319
320#define ES_REG_UART_FIFO 0x30 /* R/W: PAGE 0x0e; UART FIFO register */
321#define ES_REG_UF_VALID (1<<8)
322#define ES_REG_UF_BYTEO(o) (((o)&0xff)<<0)
323#define ES_REG_UF_BYTEM (0xff<<0)
324#define ES_REG_UF_BYTEI(i) (((i)>>0)&0xff)
325
326
327/*
328 * Pages
329 */
330
331#define ES_PAGE_DAC 0x0c
332#define ES_PAGE_ADC 0x0d
333#define ES_PAGE_UART 0x0e
334#define ES_PAGE_UART1 0x0f
335
336/*
337 * Sample rate converter addresses
338 */
339
340#define ES_SMPREG_DAC1 0x70
341#define ES_SMPREG_DAC2 0x74
342#define ES_SMPREG_ADC 0x78
343#define ES_SMPREG_VOL_ADC 0x6c
344#define ES_SMPREG_VOL_DAC1 0x7c
345#define ES_SMPREG_VOL_DAC2 0x7e
346#define ES_SMPREG_TRUNC_N 0x00
347#define ES_SMPREG_INT_REGS 0x01
348#define ES_SMPREG_ACCUM_FRAC 0x02
349#define ES_SMPREG_VFREQ_FRAC 0x03
350
351/*
352 * Some contants
353 */
354
355#define ES_1370_SRCLOCK 1411200
356#define ES_1370_SRTODIV(x) (ES_1370_SRCLOCK/(x)-2)
357
358/*
359 * Open modes
360 */
361
362#define ES_MODE_PLAY1 0x0001
363#define ES_MODE_PLAY2 0x0002
364#define ES_MODE_CAPTURE 0x0004
365
366#define ES_MODE_OUTPUT 0x0001 /* for MIDI */
367#define ES_MODE_INPUT 0x0002 /* for MIDI */
368
369/*
370
371 */
372
373struct ensoniq {
374 spinlock_t reg_lock;
375 struct mutex src_mutex;
376
377 int irq;
378
379 unsigned long playback1size;
380 unsigned long playback2size;
381 unsigned long capture3size;
382
383 unsigned long port;
384 unsigned int mode;
385 unsigned int uartm; /* UART mode */
386
387 unsigned int ctrl; /* control register */
388 unsigned int sctrl; /* serial control register */
389 unsigned int cssr; /* control status register */
390 unsigned int uartc; /* uart control register */
391 unsigned int rev; /* chip revision */
392
393 union {
394#ifdef CHIP1371
395 struct {
396 struct snd_ac97 *ac97;
397 } es1371;
398#else
399 struct {
400 int pclkdiv_lock;
401 struct snd_ak4531 *ak4531;
402 } es1370;
403#endif
404 } u;
405
406 struct pci_dev *pci;
407 struct snd_card *card;
408 struct snd_pcm *pcm1; /* DAC1/ADC PCM */
409 struct snd_pcm *pcm2; /* DAC2 PCM */
410 struct snd_pcm_substream *playback1_substream;
411 struct snd_pcm_substream *playback2_substream;
412 struct snd_pcm_substream *capture_substream;
413 unsigned int p1_dma_size;
414 unsigned int p2_dma_size;
415 unsigned int c_dma_size;
416 unsigned int p1_period_size;
417 unsigned int p2_period_size;
418 unsigned int c_period_size;
419 struct snd_rawmidi *rmidi;
420 struct snd_rawmidi_substream *midi_input;
421 struct snd_rawmidi_substream *midi_output;
422
423 unsigned int spdif;
424 unsigned int spdif_default;
425 unsigned int spdif_stream;
426
427#ifdef CHIP1370
428 struct snd_dma_buffer dma_bug;
429#endif
430
431#ifdef SUPPORT_JOYSTICK
432 struct gameport *gameport;
433#endif
434};
435
436static irqreturn_t snd_audiopci_interrupt(int irq, void *dev_id);
437
438static const struct pci_device_id snd_audiopci_ids[] = {
439#ifdef CHIP1370
440 { PCI_VDEVICE(ENSONIQ, 0x5000), 0, }, /* ES1370 */
441#endif
442#ifdef CHIP1371
443 { PCI_VDEVICE(ENSONIQ, 0x1371), 0, }, /* ES1371 */
444 { PCI_VDEVICE(ENSONIQ, 0x5880), 0, }, /* ES1373 - CT5880 */
445 { PCI_VDEVICE(ECTIVA, 0x8938), 0, }, /* Ectiva EV1938 */
446#endif
447 { 0, }
448};
449
450MODULE_DEVICE_TABLE(pci, snd_audiopci_ids);
451
452/*
453 * constants
454 */
455
456#define POLL_COUNT 0xa000
457
458#ifdef CHIP1370
459static const unsigned int snd_es1370_fixed_rates[] =
460 {5512, 11025, 22050, 44100};
461static const struct snd_pcm_hw_constraint_list snd_es1370_hw_constraints_rates = {
462 .count = 4,
463 .list = snd_es1370_fixed_rates,
464 .mask = 0,
465};
466static const struct snd_ratnum es1370_clock = {
467 .num = ES_1370_SRCLOCK,
468 .den_min = 29,
469 .den_max = 353,
470 .den_step = 1,
471};
472static const struct snd_pcm_hw_constraint_ratnums snd_es1370_hw_constraints_clock = {
473 .nrats = 1,
474 .rats = &es1370_clock,
475};
476#else
477static const struct snd_ratden es1371_dac_clock = {
478 .num_min = 3000 * (1 << 15),
479 .num_max = 48000 * (1 << 15),
480 .num_step = 3000,
481 .den = 1 << 15,
482};
483static const struct snd_pcm_hw_constraint_ratdens snd_es1371_hw_constraints_dac_clock = {
484 .nrats = 1,
485 .rats = &es1371_dac_clock,
486};
487static const struct snd_ratnum es1371_adc_clock = {
488 .num = 48000 << 15,
489 .den_min = 32768,
490 .den_max = 393216,
491 .den_step = 1,
492};
493static const struct snd_pcm_hw_constraint_ratnums snd_es1371_hw_constraints_adc_clock = {
494 .nrats = 1,
495 .rats = &es1371_adc_clock,
496};
497#endif
498static const unsigned int snd_ensoniq_sample_shift[] =
499 {0, 1, 1, 2};
500
501/*
502 * common I/O routines
503 */
504
505#ifdef CHIP1371
506
507static unsigned int snd_es1371_wait_src_ready(struct ensoniq * ensoniq)
508{
509 unsigned int t, r = 0;
510
511 for (t = 0; t < POLL_COUNT; t++) {
512 r = inl(ES_REG(ensoniq, 1371_SMPRATE));
513 if ((r & ES_1371_SRC_RAM_BUSY) == 0)
514 return r;
515 cond_resched();
516 }
517 dev_err(ensoniq->card->dev, "wait src ready timeout 0x%lx [0x%x]\n",
518 ES_REG(ensoniq, 1371_SMPRATE), r);
519 return 0;
520}
521
522static unsigned int snd_es1371_src_read(struct ensoniq * ensoniq, unsigned short reg)
523{
524 unsigned int temp, i, orig, r;
525
526 /* wait for ready */
527 temp = orig = snd_es1371_wait_src_ready(ensoniq);
528
529 /* expose the SRC state bits */
530 r = temp & (ES_1371_SRC_DISABLE | ES_1371_DIS_P1 |
531 ES_1371_DIS_P2 | ES_1371_DIS_R1);
532 r |= ES_1371_SRC_RAM_ADDRO(reg) | 0x10000;
533 outl(r, ES_REG(ensoniq, 1371_SMPRATE));
534
535 /* now, wait for busy and the correct time to read */
536 temp = snd_es1371_wait_src_ready(ensoniq);
537
538 if ((temp & 0x00870000) != 0x00010000) {
539 /* wait for the right state */
540 for (i = 0; i < POLL_COUNT; i++) {
541 temp = inl(ES_REG(ensoniq, 1371_SMPRATE));
542 if ((temp & 0x00870000) == 0x00010000)
543 break;
544 }
545 }
546
547 /* hide the state bits */
548 r = orig & (ES_1371_SRC_DISABLE | ES_1371_DIS_P1 |
549 ES_1371_DIS_P2 | ES_1371_DIS_R1);
550 r |= ES_1371_SRC_RAM_ADDRO(reg);
551 outl(r, ES_REG(ensoniq, 1371_SMPRATE));
552
553 return temp;
554}
555
556static void snd_es1371_src_write(struct ensoniq * ensoniq,
557 unsigned short reg, unsigned short data)
558{
559 unsigned int r;
560
561 r = snd_es1371_wait_src_ready(ensoniq) &
562 (ES_1371_SRC_DISABLE | ES_1371_DIS_P1 |
563 ES_1371_DIS_P2 | ES_1371_DIS_R1);
564 r |= ES_1371_SRC_RAM_ADDRO(reg) | ES_1371_SRC_RAM_DATAO(data);
565 outl(r | ES_1371_SRC_RAM_WE, ES_REG(ensoniq, 1371_SMPRATE));
566}
567
568#endif /* CHIP1371 */
569
570#ifdef CHIP1370
571
572static void snd_es1370_codec_write(struct snd_ak4531 *ak4531,
573 unsigned short reg, unsigned short val)
574{
575 struct ensoniq *ensoniq = ak4531->private_data;
576 unsigned long end_time = jiffies + HZ / 10;
577
578#if 0
579 dev_dbg(ensoniq->card->dev,
580 "CODEC WRITE: reg = 0x%x, val = 0x%x (0x%x), creg = 0x%x\n",
581 reg, val, ES_1370_CODEC_WRITE(reg, val), ES_REG(ensoniq, 1370_CODEC));
582#endif
583 do {
584 if (!(inl(ES_REG(ensoniq, STATUS)) & ES_1370_CSTAT)) {
585 outw(ES_1370_CODEC_WRITE(reg, val), ES_REG(ensoniq, 1370_CODEC));
586 return;
587 }
588 schedule_timeout_uninterruptible(1);
589 } while (time_after(end_time, jiffies));
590 dev_err(ensoniq->card->dev, "codec write timeout, status = 0x%x\n",
591 inl(ES_REG(ensoniq, STATUS)));
592}
593
594#endif /* CHIP1370 */
595
596#ifdef CHIP1371
597
598static inline bool is_ev1938(struct ensoniq *ensoniq)
599{
600 return ensoniq->pci->device == 0x8938;
601}
602
603static void snd_es1371_codec_write(struct snd_ac97 *ac97,
604 unsigned short reg, unsigned short val)
605{
606 struct ensoniq *ensoniq = ac97->private_data;
607 unsigned int t, x, flag;
608
609 flag = is_ev1938(ensoniq) ? EV_1938_CODEC_MAGIC : 0;
610 mutex_lock(&ensoniq->src_mutex);
611 for (t = 0; t < POLL_COUNT; t++) {
612 if (!(inl(ES_REG(ensoniq, 1371_CODEC)) & ES_1371_CODEC_WIP)) {
613 /* save the current state for latter */
614 x = snd_es1371_wait_src_ready(ensoniq);
615 outl((x & (ES_1371_SRC_DISABLE | ES_1371_DIS_P1 |
616 ES_1371_DIS_P2 | ES_1371_DIS_R1)) | 0x00010000,
617 ES_REG(ensoniq, 1371_SMPRATE));
618 /* wait for not busy (state 0) first to avoid
619 transition states */
620 for (t = 0; t < POLL_COUNT; t++) {
621 if ((inl(ES_REG(ensoniq, 1371_SMPRATE)) & 0x00870000) ==
622 0x00000000)
623 break;
624 }
625 /* wait for a SAFE time to write addr/data and then do it, dammit */
626 for (t = 0; t < POLL_COUNT; t++) {
627 if ((inl(ES_REG(ensoniq, 1371_SMPRATE)) & 0x00870000) ==
628 0x00010000)
629 break;
630 }
631 outl(ES_1371_CODEC_WRITE(reg, val) | flag,
632 ES_REG(ensoniq, 1371_CODEC));
633 /* restore SRC reg */
634 snd_es1371_wait_src_ready(ensoniq);
635 outl(x, ES_REG(ensoniq, 1371_SMPRATE));
636 mutex_unlock(&ensoniq->src_mutex);
637 return;
638 }
639 }
640 mutex_unlock(&ensoniq->src_mutex);
641 dev_err(ensoniq->card->dev, "codec write timeout at 0x%lx [0x%x]\n",
642 ES_REG(ensoniq, 1371_CODEC), inl(ES_REG(ensoniq, 1371_CODEC)));
643}
644
645static unsigned short snd_es1371_codec_read(struct snd_ac97 *ac97,
646 unsigned short reg)
647{
648 struct ensoniq *ensoniq = ac97->private_data;
649 unsigned int t, x, flag, fail = 0;
650
651 flag = is_ev1938(ensoniq) ? EV_1938_CODEC_MAGIC : 0;
652 __again:
653 mutex_lock(&ensoniq->src_mutex);
654 for (t = 0; t < POLL_COUNT; t++) {
655 if (!(inl(ES_REG(ensoniq, 1371_CODEC)) & ES_1371_CODEC_WIP)) {
656 /* save the current state for latter */
657 x = snd_es1371_wait_src_ready(ensoniq);
658 outl((x & (ES_1371_SRC_DISABLE | ES_1371_DIS_P1 |
659 ES_1371_DIS_P2 | ES_1371_DIS_R1)) | 0x00010000,
660 ES_REG(ensoniq, 1371_SMPRATE));
661 /* wait for not busy (state 0) first to avoid
662 transition states */
663 for (t = 0; t < POLL_COUNT; t++) {
664 if ((inl(ES_REG(ensoniq, 1371_SMPRATE)) & 0x00870000) ==
665 0x00000000)
666 break;
667 }
668 /* wait for a SAFE time to write addr/data and then do it, dammit */
669 for (t = 0; t < POLL_COUNT; t++) {
670 if ((inl(ES_REG(ensoniq, 1371_SMPRATE)) & 0x00870000) ==
671 0x00010000)
672 break;
673 }
674 outl(ES_1371_CODEC_READS(reg) | flag,
675 ES_REG(ensoniq, 1371_CODEC));
676 /* restore SRC reg */
677 snd_es1371_wait_src_ready(ensoniq);
678 outl(x, ES_REG(ensoniq, 1371_SMPRATE));
679 /* wait for WIP again */
680 for (t = 0; t < POLL_COUNT; t++) {
681 if (!(inl(ES_REG(ensoniq, 1371_CODEC)) & ES_1371_CODEC_WIP))
682 break;
683 }
684 /* now wait for the stinkin' data (RDY) */
685 for (t = 0; t < POLL_COUNT; t++) {
686 if ((x = inl(ES_REG(ensoniq, 1371_CODEC))) & ES_1371_CODEC_RDY) {
687 if (is_ev1938(ensoniq)) {
688 for (t = 0; t < 100; t++)
689 inl(ES_REG(ensoniq, CONTROL));
690 x = inl(ES_REG(ensoniq, 1371_CODEC));
691 }
692 mutex_unlock(&ensoniq->src_mutex);
693 return ES_1371_CODEC_READ(x);
694 }
695 }
696 mutex_unlock(&ensoniq->src_mutex);
697 if (++fail > 10) {
698 dev_err(ensoniq->card->dev,
699 "codec read timeout (final) at 0x%lx, reg = 0x%x [0x%x]\n",
700 ES_REG(ensoniq, 1371_CODEC), reg,
701 inl(ES_REG(ensoniq, 1371_CODEC)));
702 return 0;
703 }
704 goto __again;
705 }
706 }
707 mutex_unlock(&ensoniq->src_mutex);
708 dev_err(ensoniq->card->dev, "codec read timeout at 0x%lx [0x%x]\n",
709 ES_REG(ensoniq, 1371_CODEC), inl(ES_REG(ensoniq, 1371_CODEC)));
710 return 0;
711}
712
713static void snd_es1371_codec_wait(struct snd_ac97 *ac97)
714{
715 msleep(750);
716 snd_es1371_codec_read(ac97, AC97_RESET);
717 snd_es1371_codec_read(ac97, AC97_VENDOR_ID1);
718 snd_es1371_codec_read(ac97, AC97_VENDOR_ID2);
719 msleep(50);
720}
721
722static void snd_es1371_adc_rate(struct ensoniq * ensoniq, unsigned int rate)
723{
724 unsigned int n, truncm, freq;
725
726 mutex_lock(&ensoniq->src_mutex);
727 n = rate / 3000;
728 if ((1 << n) & ((1 << 15) | (1 << 13) | (1 << 11) | (1 << 9)))
729 n--;
730 truncm = (21 * n - 1) | 1;
731 freq = ((48000UL << 15) / rate) * n;
732 if (rate >= 24000) {
733 if (truncm > 239)
734 truncm = 239;
735 snd_es1371_src_write(ensoniq, ES_SMPREG_ADC + ES_SMPREG_TRUNC_N,
736 (((239 - truncm) >> 1) << 9) | (n << 4));
737 } else {
738 if (truncm > 119)
739 truncm = 119;
740 snd_es1371_src_write(ensoniq, ES_SMPREG_ADC + ES_SMPREG_TRUNC_N,
741 0x8000 | (((119 - truncm) >> 1) << 9) | (n << 4));
742 }
743 snd_es1371_src_write(ensoniq, ES_SMPREG_ADC + ES_SMPREG_INT_REGS,
744 (snd_es1371_src_read(ensoniq, ES_SMPREG_ADC +
745 ES_SMPREG_INT_REGS) & 0x00ff) |
746 ((freq >> 5) & 0xfc00));
747 snd_es1371_src_write(ensoniq, ES_SMPREG_ADC + ES_SMPREG_VFREQ_FRAC, freq & 0x7fff);
748 snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_ADC, n << 8);
749 snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_ADC + 1, n << 8);
750 mutex_unlock(&ensoniq->src_mutex);
751}
752
753static void snd_es1371_dac1_rate(struct ensoniq * ensoniq, unsigned int rate)
754{
755 unsigned int freq, r;
756
757 mutex_lock(&ensoniq->src_mutex);
758 freq = ((rate << 15) + 1500) / 3000;
759 r = (snd_es1371_wait_src_ready(ensoniq) & (ES_1371_SRC_DISABLE |
760 ES_1371_DIS_P2 | ES_1371_DIS_R1)) |
761 ES_1371_DIS_P1;
762 outl(r, ES_REG(ensoniq, 1371_SMPRATE));
763 snd_es1371_src_write(ensoniq, ES_SMPREG_DAC1 + ES_SMPREG_INT_REGS,
764 (snd_es1371_src_read(ensoniq, ES_SMPREG_DAC1 +
765 ES_SMPREG_INT_REGS) & 0x00ff) |
766 ((freq >> 5) & 0xfc00));
767 snd_es1371_src_write(ensoniq, ES_SMPREG_DAC1 + ES_SMPREG_VFREQ_FRAC, freq & 0x7fff);
768 r = (snd_es1371_wait_src_ready(ensoniq) & (ES_1371_SRC_DISABLE |
769 ES_1371_DIS_P2 | ES_1371_DIS_R1));
770 outl(r, ES_REG(ensoniq, 1371_SMPRATE));
771 mutex_unlock(&ensoniq->src_mutex);
772}
773
774static void snd_es1371_dac2_rate(struct ensoniq * ensoniq, unsigned int rate)
775{
776 unsigned int freq, r;
777
778 mutex_lock(&ensoniq->src_mutex);
779 freq = ((rate << 15) + 1500) / 3000;
780 r = (snd_es1371_wait_src_ready(ensoniq) & (ES_1371_SRC_DISABLE |
781 ES_1371_DIS_P1 | ES_1371_DIS_R1)) |
782 ES_1371_DIS_P2;
783 outl(r, ES_REG(ensoniq, 1371_SMPRATE));
784 snd_es1371_src_write(ensoniq, ES_SMPREG_DAC2 + ES_SMPREG_INT_REGS,
785 (snd_es1371_src_read(ensoniq, ES_SMPREG_DAC2 +
786 ES_SMPREG_INT_REGS) & 0x00ff) |
787 ((freq >> 5) & 0xfc00));
788 snd_es1371_src_write(ensoniq, ES_SMPREG_DAC2 + ES_SMPREG_VFREQ_FRAC,
789 freq & 0x7fff);
790 r = (snd_es1371_wait_src_ready(ensoniq) & (ES_1371_SRC_DISABLE |
791 ES_1371_DIS_P1 | ES_1371_DIS_R1));
792 outl(r, ES_REG(ensoniq, 1371_SMPRATE));
793 mutex_unlock(&ensoniq->src_mutex);
794}
795
796#endif /* CHIP1371 */
797
798static int snd_ensoniq_trigger(struct snd_pcm_substream *substream, int cmd)
799{
800 struct ensoniq *ensoniq = snd_pcm_substream_chip(substream);
801 switch (cmd) {
802 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
803 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
804 {
805 unsigned int what = 0;
806 struct snd_pcm_substream *s;
807 snd_pcm_group_for_each_entry(s, substream) {
808 if (s == ensoniq->playback1_substream) {
809 what |= ES_P1_PAUSE;
810 snd_pcm_trigger_done(s, substream);
811 } else if (s == ensoniq->playback2_substream) {
812 what |= ES_P2_PAUSE;
813 snd_pcm_trigger_done(s, substream);
814 } else if (s == ensoniq->capture_substream)
815 return -EINVAL;
816 }
817 spin_lock(&ensoniq->reg_lock);
818 if (cmd == SNDRV_PCM_TRIGGER_PAUSE_PUSH)
819 ensoniq->sctrl |= what;
820 else
821 ensoniq->sctrl &= ~what;
822 outl(ensoniq->sctrl, ES_REG(ensoniq, SERIAL));
823 spin_unlock(&ensoniq->reg_lock);
824 break;
825 }
826 case SNDRV_PCM_TRIGGER_START:
827 case SNDRV_PCM_TRIGGER_STOP:
828 {
829 unsigned int what = 0;
830 struct snd_pcm_substream *s;
831 snd_pcm_group_for_each_entry(s, substream) {
832 if (s == ensoniq->playback1_substream) {
833 what |= ES_DAC1_EN;
834 snd_pcm_trigger_done(s, substream);
835 } else if (s == ensoniq->playback2_substream) {
836 what |= ES_DAC2_EN;
837 snd_pcm_trigger_done(s, substream);
838 } else if (s == ensoniq->capture_substream) {
839 what |= ES_ADC_EN;
840 snd_pcm_trigger_done(s, substream);
841 }
842 }
843 spin_lock(&ensoniq->reg_lock);
844 if (cmd == SNDRV_PCM_TRIGGER_START)
845 ensoniq->ctrl |= what;
846 else
847 ensoniq->ctrl &= ~what;
848 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
849 spin_unlock(&ensoniq->reg_lock);
850 break;
851 }
852 default:
853 return -EINVAL;
854 }
855 return 0;
856}
857
858/*
859 * PCM part
860 */
861
862static int snd_ensoniq_playback1_prepare(struct snd_pcm_substream *substream)
863{
864 struct ensoniq *ensoniq = snd_pcm_substream_chip(substream);
865 struct snd_pcm_runtime *runtime = substream->runtime;
866 unsigned int mode = 0;
867
868 ensoniq->p1_dma_size = snd_pcm_lib_buffer_bytes(substream);
869 ensoniq->p1_period_size = snd_pcm_lib_period_bytes(substream);
870 if (snd_pcm_format_width(runtime->format) == 16)
871 mode |= 0x02;
872 if (runtime->channels > 1)
873 mode |= 0x01;
874 spin_lock_irq(&ensoniq->reg_lock);
875 ensoniq->ctrl &= ~ES_DAC1_EN;
876#ifdef CHIP1371
877 /* 48k doesn't need SRC (it breaks AC3-passthru) */
878 if (runtime->rate == 48000)
879 ensoniq->ctrl |= ES_1373_BYPASS_P1;
880 else
881 ensoniq->ctrl &= ~ES_1373_BYPASS_P1;
882#endif
883 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
884 outl(ES_MEM_PAGEO(ES_PAGE_DAC), ES_REG(ensoniq, MEM_PAGE));
885 outl(runtime->dma_addr, ES_REG(ensoniq, DAC1_FRAME));
886 outl((ensoniq->p1_dma_size >> 2) - 1, ES_REG(ensoniq, DAC1_SIZE));
887 ensoniq->sctrl &= ~(ES_P1_LOOP_SEL | ES_P1_PAUSE | ES_P1_SCT_RLD | ES_P1_MODEM);
888 ensoniq->sctrl |= ES_P1_INT_EN | ES_P1_MODEO(mode);
889 outl(ensoniq->sctrl, ES_REG(ensoniq, SERIAL));
890 outl((ensoniq->p1_period_size >> snd_ensoniq_sample_shift[mode]) - 1,
891 ES_REG(ensoniq, DAC1_COUNT));
892#ifdef CHIP1370
893 ensoniq->ctrl &= ~ES_1370_WTSRSELM;
894 switch (runtime->rate) {
895 case 5512: ensoniq->ctrl |= ES_1370_WTSRSEL(0); break;
896 case 11025: ensoniq->ctrl |= ES_1370_WTSRSEL(1); break;
897 case 22050: ensoniq->ctrl |= ES_1370_WTSRSEL(2); break;
898 case 44100: ensoniq->ctrl |= ES_1370_WTSRSEL(3); break;
899 default: snd_BUG();
900 }
901#endif
902 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
903 spin_unlock_irq(&ensoniq->reg_lock);
904#ifndef CHIP1370
905 snd_es1371_dac1_rate(ensoniq, runtime->rate);
906#endif
907 return 0;
908}
909
910static int snd_ensoniq_playback2_prepare(struct snd_pcm_substream *substream)
911{
912 struct ensoniq *ensoniq = snd_pcm_substream_chip(substream);
913 struct snd_pcm_runtime *runtime = substream->runtime;
914 unsigned int mode = 0;
915
916 ensoniq->p2_dma_size = snd_pcm_lib_buffer_bytes(substream);
917 ensoniq->p2_period_size = snd_pcm_lib_period_bytes(substream);
918 if (snd_pcm_format_width(runtime->format) == 16)
919 mode |= 0x02;
920 if (runtime->channels > 1)
921 mode |= 0x01;
922 spin_lock_irq(&ensoniq->reg_lock);
923 ensoniq->ctrl &= ~ES_DAC2_EN;
924 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
925 outl(ES_MEM_PAGEO(ES_PAGE_DAC), ES_REG(ensoniq, MEM_PAGE));
926 outl(runtime->dma_addr, ES_REG(ensoniq, DAC2_FRAME));
927 outl((ensoniq->p2_dma_size >> 2) - 1, ES_REG(ensoniq, DAC2_SIZE));
928 ensoniq->sctrl &= ~(ES_P2_LOOP_SEL | ES_P2_PAUSE | ES_P2_DAC_SEN |
929 ES_P2_END_INCM | ES_P2_ST_INCM | ES_P2_MODEM);
930 ensoniq->sctrl |= ES_P2_INT_EN | ES_P2_MODEO(mode) |
931 ES_P2_END_INCO(mode & 2 ? 2 : 1) | ES_P2_ST_INCO(0);
932 outl(ensoniq->sctrl, ES_REG(ensoniq, SERIAL));
933 outl((ensoniq->p2_period_size >> snd_ensoniq_sample_shift[mode]) - 1,
934 ES_REG(ensoniq, DAC2_COUNT));
935#ifdef CHIP1370
936 if (!(ensoniq->u.es1370.pclkdiv_lock & ES_MODE_CAPTURE)) {
937 ensoniq->ctrl &= ~ES_1370_PCLKDIVM;
938 ensoniq->ctrl |= ES_1370_PCLKDIVO(ES_1370_SRTODIV(runtime->rate));
939 ensoniq->u.es1370.pclkdiv_lock |= ES_MODE_PLAY2;
940 }
941#endif
942 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
943 spin_unlock_irq(&ensoniq->reg_lock);
944#ifndef CHIP1370
945 snd_es1371_dac2_rate(ensoniq, runtime->rate);
946#endif
947 return 0;
948}
949
950static int snd_ensoniq_capture_prepare(struct snd_pcm_substream *substream)
951{
952 struct ensoniq *ensoniq = snd_pcm_substream_chip(substream);
953 struct snd_pcm_runtime *runtime = substream->runtime;
954 unsigned int mode = 0;
955
956 ensoniq->c_dma_size = snd_pcm_lib_buffer_bytes(substream);
957 ensoniq->c_period_size = snd_pcm_lib_period_bytes(substream);
958 if (snd_pcm_format_width(runtime->format) == 16)
959 mode |= 0x02;
960 if (runtime->channels > 1)
961 mode |= 0x01;
962 spin_lock_irq(&ensoniq->reg_lock);
963 ensoniq->ctrl &= ~ES_ADC_EN;
964 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
965 outl(ES_MEM_PAGEO(ES_PAGE_ADC), ES_REG(ensoniq, MEM_PAGE));
966 outl(runtime->dma_addr, ES_REG(ensoniq, ADC_FRAME));
967 outl((ensoniq->c_dma_size >> 2) - 1, ES_REG(ensoniq, ADC_SIZE));
968 ensoniq->sctrl &= ~(ES_R1_LOOP_SEL | ES_R1_MODEM);
969 ensoniq->sctrl |= ES_R1_INT_EN | ES_R1_MODEO(mode);
970 outl(ensoniq->sctrl, ES_REG(ensoniq, SERIAL));
971 outl((ensoniq->c_period_size >> snd_ensoniq_sample_shift[mode]) - 1,
972 ES_REG(ensoniq, ADC_COUNT));
973#ifdef CHIP1370
974 if (!(ensoniq->u.es1370.pclkdiv_lock & ES_MODE_PLAY2)) {
975 ensoniq->ctrl &= ~ES_1370_PCLKDIVM;
976 ensoniq->ctrl |= ES_1370_PCLKDIVO(ES_1370_SRTODIV(runtime->rate));
977 ensoniq->u.es1370.pclkdiv_lock |= ES_MODE_CAPTURE;
978 }
979#endif
980 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
981 spin_unlock_irq(&ensoniq->reg_lock);
982#ifndef CHIP1370
983 snd_es1371_adc_rate(ensoniq, runtime->rate);
984#endif
985 return 0;
986}
987
988static snd_pcm_uframes_t snd_ensoniq_playback1_pointer(struct snd_pcm_substream *substream)
989{
990 struct ensoniq *ensoniq = snd_pcm_substream_chip(substream);
991 size_t ptr;
992
993 spin_lock(&ensoniq->reg_lock);
994 if (inl(ES_REG(ensoniq, CONTROL)) & ES_DAC1_EN) {
995 outl(ES_MEM_PAGEO(ES_PAGE_DAC), ES_REG(ensoniq, MEM_PAGE));
996 ptr = ES_REG_FCURR_COUNTI(inl(ES_REG(ensoniq, DAC1_SIZE)));
997 ptr = bytes_to_frames(substream->runtime, ptr);
998 } else {
999 ptr = 0;
1000 }
1001 spin_unlock(&ensoniq->reg_lock);
1002 return ptr;
1003}
1004
1005static snd_pcm_uframes_t snd_ensoniq_playback2_pointer(struct snd_pcm_substream *substream)
1006{
1007 struct ensoniq *ensoniq = snd_pcm_substream_chip(substream);
1008 size_t ptr;
1009
1010 spin_lock(&ensoniq->reg_lock);
1011 if (inl(ES_REG(ensoniq, CONTROL)) & ES_DAC2_EN) {
1012 outl(ES_MEM_PAGEO(ES_PAGE_DAC), ES_REG(ensoniq, MEM_PAGE));
1013 ptr = ES_REG_FCURR_COUNTI(inl(ES_REG(ensoniq, DAC2_SIZE)));
1014 ptr = bytes_to_frames(substream->runtime, ptr);
1015 } else {
1016 ptr = 0;
1017 }
1018 spin_unlock(&ensoniq->reg_lock);
1019 return ptr;
1020}
1021
1022static snd_pcm_uframes_t snd_ensoniq_capture_pointer(struct snd_pcm_substream *substream)
1023{
1024 struct ensoniq *ensoniq = snd_pcm_substream_chip(substream);
1025 size_t ptr;
1026
1027 spin_lock(&ensoniq->reg_lock);
1028 if (inl(ES_REG(ensoniq, CONTROL)) & ES_ADC_EN) {
1029 outl(ES_MEM_PAGEO(ES_PAGE_ADC), ES_REG(ensoniq, MEM_PAGE));
1030 ptr = ES_REG_FCURR_COUNTI(inl(ES_REG(ensoniq, ADC_SIZE)));
1031 ptr = bytes_to_frames(substream->runtime, ptr);
1032 } else {
1033 ptr = 0;
1034 }
1035 spin_unlock(&ensoniq->reg_lock);
1036 return ptr;
1037}
1038
1039static const struct snd_pcm_hardware snd_ensoniq_playback1 =
1040{
1041 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1042 SNDRV_PCM_INFO_BLOCK_TRANSFER |
1043 SNDRV_PCM_INFO_MMAP_VALID |
1044 SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_SYNC_START),
1045 .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
1046 .rates =
1047#ifndef CHIP1370
1048 SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
1049#else
1050 (SNDRV_PCM_RATE_KNOT | /* 5512Hz rate */
1051 SNDRV_PCM_RATE_11025 | SNDRV_PCM_RATE_22050 |
1052 SNDRV_PCM_RATE_44100),
1053#endif
1054 .rate_min = 4000,
1055 .rate_max = 48000,
1056 .channels_min = 1,
1057 .channels_max = 2,
1058 .buffer_bytes_max = (128*1024),
1059 .period_bytes_min = 64,
1060 .period_bytes_max = (128*1024),
1061 .periods_min = 1,
1062 .periods_max = 1024,
1063 .fifo_size = 0,
1064};
1065
1066static const struct snd_pcm_hardware snd_ensoniq_playback2 =
1067{
1068 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1069 SNDRV_PCM_INFO_BLOCK_TRANSFER |
1070 SNDRV_PCM_INFO_MMAP_VALID | SNDRV_PCM_INFO_PAUSE |
1071 SNDRV_PCM_INFO_SYNC_START),
1072 .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
1073 .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
1074 .rate_min = 4000,
1075 .rate_max = 48000,
1076 .channels_min = 1,
1077 .channels_max = 2,
1078 .buffer_bytes_max = (128*1024),
1079 .period_bytes_min = 64,
1080 .period_bytes_max = (128*1024),
1081 .periods_min = 1,
1082 .periods_max = 1024,
1083 .fifo_size = 0,
1084};
1085
1086static const struct snd_pcm_hardware snd_ensoniq_capture =
1087{
1088 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1089 SNDRV_PCM_INFO_BLOCK_TRANSFER |
1090 SNDRV_PCM_INFO_MMAP_VALID | SNDRV_PCM_INFO_SYNC_START),
1091 .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
1092 .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
1093 .rate_min = 4000,
1094 .rate_max = 48000,
1095 .channels_min = 1,
1096 .channels_max = 2,
1097 .buffer_bytes_max = (128*1024),
1098 .period_bytes_min = 64,
1099 .period_bytes_max = (128*1024),
1100 .periods_min = 1,
1101 .periods_max = 1024,
1102 .fifo_size = 0,
1103};
1104
1105static int snd_ensoniq_playback1_open(struct snd_pcm_substream *substream)
1106{
1107 struct ensoniq *ensoniq = snd_pcm_substream_chip(substream);
1108 struct snd_pcm_runtime *runtime = substream->runtime;
1109
1110 ensoniq->mode |= ES_MODE_PLAY1;
1111 ensoniq->playback1_substream = substream;
1112 runtime->hw = snd_ensoniq_playback1;
1113 snd_pcm_set_sync(substream);
1114 spin_lock_irq(&ensoniq->reg_lock);
1115 if (ensoniq->spdif && ensoniq->playback2_substream == NULL)
1116 ensoniq->spdif_stream = ensoniq->spdif_default;
1117 spin_unlock_irq(&ensoniq->reg_lock);
1118#ifdef CHIP1370
1119 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
1120 &snd_es1370_hw_constraints_rates);
1121#else
1122 snd_pcm_hw_constraint_ratdens(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
1123 &snd_es1371_hw_constraints_dac_clock);
1124#endif
1125 return 0;
1126}
1127
1128static int snd_ensoniq_playback2_open(struct snd_pcm_substream *substream)
1129{
1130 struct ensoniq *ensoniq = snd_pcm_substream_chip(substream);
1131 struct snd_pcm_runtime *runtime = substream->runtime;
1132
1133 ensoniq->mode |= ES_MODE_PLAY2;
1134 ensoniq->playback2_substream = substream;
1135 runtime->hw = snd_ensoniq_playback2;
1136 snd_pcm_set_sync(substream);
1137 spin_lock_irq(&ensoniq->reg_lock);
1138 if (ensoniq->spdif && ensoniq->playback1_substream == NULL)
1139 ensoniq->spdif_stream = ensoniq->spdif_default;
1140 spin_unlock_irq(&ensoniq->reg_lock);
1141#ifdef CHIP1370
1142 snd_pcm_hw_constraint_ratnums(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
1143 &snd_es1370_hw_constraints_clock);
1144#else
1145 snd_pcm_hw_constraint_ratdens(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
1146 &snd_es1371_hw_constraints_dac_clock);
1147#endif
1148 return 0;
1149}
1150
1151static int snd_ensoniq_capture_open(struct snd_pcm_substream *substream)
1152{
1153 struct ensoniq *ensoniq = snd_pcm_substream_chip(substream);
1154 struct snd_pcm_runtime *runtime = substream->runtime;
1155
1156 ensoniq->mode |= ES_MODE_CAPTURE;
1157 ensoniq->capture_substream = substream;
1158 runtime->hw = snd_ensoniq_capture;
1159 snd_pcm_set_sync(substream);
1160#ifdef CHIP1370
1161 snd_pcm_hw_constraint_ratnums(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
1162 &snd_es1370_hw_constraints_clock);
1163#else
1164 snd_pcm_hw_constraint_ratnums(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
1165 &snd_es1371_hw_constraints_adc_clock);
1166#endif
1167 return 0;
1168}
1169
1170static int snd_ensoniq_playback1_close(struct snd_pcm_substream *substream)
1171{
1172 struct ensoniq *ensoniq = snd_pcm_substream_chip(substream);
1173
1174 ensoniq->playback1_substream = NULL;
1175 ensoniq->mode &= ~ES_MODE_PLAY1;
1176 return 0;
1177}
1178
1179static int snd_ensoniq_playback2_close(struct snd_pcm_substream *substream)
1180{
1181 struct ensoniq *ensoniq = snd_pcm_substream_chip(substream);
1182
1183 ensoniq->playback2_substream = NULL;
1184 spin_lock_irq(&ensoniq->reg_lock);
1185#ifdef CHIP1370
1186 ensoniq->u.es1370.pclkdiv_lock &= ~ES_MODE_PLAY2;
1187#endif
1188 ensoniq->mode &= ~ES_MODE_PLAY2;
1189 spin_unlock_irq(&ensoniq->reg_lock);
1190 return 0;
1191}
1192
1193static int snd_ensoniq_capture_close(struct snd_pcm_substream *substream)
1194{
1195 struct ensoniq *ensoniq = snd_pcm_substream_chip(substream);
1196
1197 ensoniq->capture_substream = NULL;
1198 spin_lock_irq(&ensoniq->reg_lock);
1199#ifdef CHIP1370
1200 ensoniq->u.es1370.pclkdiv_lock &= ~ES_MODE_CAPTURE;
1201#endif
1202 ensoniq->mode &= ~ES_MODE_CAPTURE;
1203 spin_unlock_irq(&ensoniq->reg_lock);
1204 return 0;
1205}
1206
1207static const struct snd_pcm_ops snd_ensoniq_playback1_ops = {
1208 .open = snd_ensoniq_playback1_open,
1209 .close = snd_ensoniq_playback1_close,
1210 .prepare = snd_ensoniq_playback1_prepare,
1211 .trigger = snd_ensoniq_trigger,
1212 .pointer = snd_ensoniq_playback1_pointer,
1213};
1214
1215static const struct snd_pcm_ops snd_ensoniq_playback2_ops = {
1216 .open = snd_ensoniq_playback2_open,
1217 .close = snd_ensoniq_playback2_close,
1218 .prepare = snd_ensoniq_playback2_prepare,
1219 .trigger = snd_ensoniq_trigger,
1220 .pointer = snd_ensoniq_playback2_pointer,
1221};
1222
1223static const struct snd_pcm_ops snd_ensoniq_capture_ops = {
1224 .open = snd_ensoniq_capture_open,
1225 .close = snd_ensoniq_capture_close,
1226 .prepare = snd_ensoniq_capture_prepare,
1227 .trigger = snd_ensoniq_trigger,
1228 .pointer = snd_ensoniq_capture_pointer,
1229};
1230
1231static const struct snd_pcm_chmap_elem surround_map[] = {
1232 { .channels = 1,
1233 .map = { SNDRV_CHMAP_MONO } },
1234 { .channels = 2,
1235 .map = { SNDRV_CHMAP_RL, SNDRV_CHMAP_RR } },
1236 {0}
1237};
1238
1239static int snd_ensoniq_pcm(struct ensoniq *ensoniq, int device)
1240{
1241 struct snd_pcm *pcm;
1242 int err;
1243
1244 err = snd_pcm_new(ensoniq->card, CHIP_NAME "/1", device, 1, 1, &pcm);
1245 if (err < 0)
1246 return err;
1247
1248#ifdef CHIP1370
1249 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_ensoniq_playback2_ops);
1250#else
1251 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_ensoniq_playback1_ops);
1252#endif
1253 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_ensoniq_capture_ops);
1254
1255 pcm->private_data = ensoniq;
1256 pcm->info_flags = 0;
1257 strcpy(pcm->name, CHIP_NAME " DAC2/ADC");
1258 ensoniq->pcm1 = pcm;
1259
1260 snd_pcm_set_managed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV,
1261 &ensoniq->pci->dev, 64*1024, 128*1024);
1262
1263#ifdef CHIP1370
1264 err = snd_pcm_add_chmap_ctls(pcm, SNDRV_PCM_STREAM_PLAYBACK,
1265 surround_map, 2, 0, NULL);
1266#else
1267 err = snd_pcm_add_chmap_ctls(pcm, SNDRV_PCM_STREAM_PLAYBACK,
1268 snd_pcm_std_chmaps, 2, 0, NULL);
1269#endif
1270 return err;
1271}
1272
1273static int snd_ensoniq_pcm2(struct ensoniq *ensoniq, int device)
1274{
1275 struct snd_pcm *pcm;
1276 int err;
1277
1278 err = snd_pcm_new(ensoniq->card, CHIP_NAME "/2", device, 1, 0, &pcm);
1279 if (err < 0)
1280 return err;
1281
1282#ifdef CHIP1370
1283 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_ensoniq_playback1_ops);
1284#else
1285 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_ensoniq_playback2_ops);
1286#endif
1287 pcm->private_data = ensoniq;
1288 pcm->info_flags = 0;
1289 strcpy(pcm->name, CHIP_NAME " DAC1");
1290 ensoniq->pcm2 = pcm;
1291
1292 snd_pcm_set_managed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV,
1293 &ensoniq->pci->dev, 64*1024, 128*1024);
1294
1295#ifdef CHIP1370
1296 err = snd_pcm_add_chmap_ctls(pcm, SNDRV_PCM_STREAM_PLAYBACK,
1297 snd_pcm_std_chmaps, 2, 0, NULL);
1298#else
1299 err = snd_pcm_add_chmap_ctls(pcm, SNDRV_PCM_STREAM_PLAYBACK,
1300 surround_map, 2, 0, NULL);
1301#endif
1302 return err;
1303}
1304
1305/*
1306 * Mixer section
1307 */
1308
1309/*
1310 * ENS1371 mixer (including SPDIF interface)
1311 */
1312#ifdef CHIP1371
1313static int snd_ens1373_spdif_info(struct snd_kcontrol *kcontrol,
1314 struct snd_ctl_elem_info *uinfo)
1315{
1316 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1317 uinfo->count = 1;
1318 return 0;
1319}
1320
1321static int snd_ens1373_spdif_default_get(struct snd_kcontrol *kcontrol,
1322 struct snd_ctl_elem_value *ucontrol)
1323{
1324 struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol);
1325 spin_lock_irq(&ensoniq->reg_lock);
1326 ucontrol->value.iec958.status[0] = (ensoniq->spdif_default >> 0) & 0xff;
1327 ucontrol->value.iec958.status[1] = (ensoniq->spdif_default >> 8) & 0xff;
1328 ucontrol->value.iec958.status[2] = (ensoniq->spdif_default >> 16) & 0xff;
1329 ucontrol->value.iec958.status[3] = (ensoniq->spdif_default >> 24) & 0xff;
1330 spin_unlock_irq(&ensoniq->reg_lock);
1331 return 0;
1332}
1333
1334static int snd_ens1373_spdif_default_put(struct snd_kcontrol *kcontrol,
1335 struct snd_ctl_elem_value *ucontrol)
1336{
1337 struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol);
1338 unsigned int val;
1339 int change;
1340
1341 val = ((u32)ucontrol->value.iec958.status[0] << 0) |
1342 ((u32)ucontrol->value.iec958.status[1] << 8) |
1343 ((u32)ucontrol->value.iec958.status[2] << 16) |
1344 ((u32)ucontrol->value.iec958.status[3] << 24);
1345 spin_lock_irq(&ensoniq->reg_lock);
1346 change = ensoniq->spdif_default != val;
1347 ensoniq->spdif_default = val;
1348 if (change && ensoniq->playback1_substream == NULL &&
1349 ensoniq->playback2_substream == NULL)
1350 outl(val, ES_REG(ensoniq, CHANNEL_STATUS));
1351 spin_unlock_irq(&ensoniq->reg_lock);
1352 return change;
1353}
1354
1355static int snd_ens1373_spdif_mask_get(struct snd_kcontrol *kcontrol,
1356 struct snd_ctl_elem_value *ucontrol)
1357{
1358 ucontrol->value.iec958.status[0] = 0xff;
1359 ucontrol->value.iec958.status[1] = 0xff;
1360 ucontrol->value.iec958.status[2] = 0xff;
1361 ucontrol->value.iec958.status[3] = 0xff;
1362 return 0;
1363}
1364
1365static int snd_ens1373_spdif_stream_get(struct snd_kcontrol *kcontrol,
1366 struct snd_ctl_elem_value *ucontrol)
1367{
1368 struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol);
1369 spin_lock_irq(&ensoniq->reg_lock);
1370 ucontrol->value.iec958.status[0] = (ensoniq->spdif_stream >> 0) & 0xff;
1371 ucontrol->value.iec958.status[1] = (ensoniq->spdif_stream >> 8) & 0xff;
1372 ucontrol->value.iec958.status[2] = (ensoniq->spdif_stream >> 16) & 0xff;
1373 ucontrol->value.iec958.status[3] = (ensoniq->spdif_stream >> 24) & 0xff;
1374 spin_unlock_irq(&ensoniq->reg_lock);
1375 return 0;
1376}
1377
1378static int snd_ens1373_spdif_stream_put(struct snd_kcontrol *kcontrol,
1379 struct snd_ctl_elem_value *ucontrol)
1380{
1381 struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol);
1382 unsigned int val;
1383 int change;
1384
1385 val = ((u32)ucontrol->value.iec958.status[0] << 0) |
1386 ((u32)ucontrol->value.iec958.status[1] << 8) |
1387 ((u32)ucontrol->value.iec958.status[2] << 16) |
1388 ((u32)ucontrol->value.iec958.status[3] << 24);
1389 spin_lock_irq(&ensoniq->reg_lock);
1390 change = ensoniq->spdif_stream != val;
1391 ensoniq->spdif_stream = val;
1392 if (change && (ensoniq->playback1_substream != NULL ||
1393 ensoniq->playback2_substream != NULL))
1394 outl(val, ES_REG(ensoniq, CHANNEL_STATUS));
1395 spin_unlock_irq(&ensoniq->reg_lock);
1396 return change;
1397}
1398
1399#define ES1371_SPDIF(xname) \
1400{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, .info = snd_es1371_spdif_info, \
1401 .get = snd_es1371_spdif_get, .put = snd_es1371_spdif_put }
1402
1403#define snd_es1371_spdif_info snd_ctl_boolean_mono_info
1404
1405static int snd_es1371_spdif_get(struct snd_kcontrol *kcontrol,
1406 struct snd_ctl_elem_value *ucontrol)
1407{
1408 struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol);
1409
1410 spin_lock_irq(&ensoniq->reg_lock);
1411 ucontrol->value.integer.value[0] = ensoniq->ctrl & ES_1373_SPDIF_THRU ? 1 : 0;
1412 spin_unlock_irq(&ensoniq->reg_lock);
1413 return 0;
1414}
1415
1416static int snd_es1371_spdif_put(struct snd_kcontrol *kcontrol,
1417 struct snd_ctl_elem_value *ucontrol)
1418{
1419 struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol);
1420 unsigned int nval1, nval2;
1421 int change;
1422
1423 nval1 = ucontrol->value.integer.value[0] ? ES_1373_SPDIF_THRU : 0;
1424 nval2 = ucontrol->value.integer.value[0] ? ES_1373_SPDIF_EN : 0;
1425 spin_lock_irq(&ensoniq->reg_lock);
1426 change = (ensoniq->ctrl & ES_1373_SPDIF_THRU) != nval1;
1427 ensoniq->ctrl &= ~ES_1373_SPDIF_THRU;
1428 ensoniq->ctrl |= nval1;
1429 ensoniq->cssr &= ~ES_1373_SPDIF_EN;
1430 ensoniq->cssr |= nval2;
1431 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
1432 outl(ensoniq->cssr, ES_REG(ensoniq, STATUS));
1433 spin_unlock_irq(&ensoniq->reg_lock);
1434 return change;
1435}
1436
1437
1438/* spdif controls */
1439static const struct snd_kcontrol_new snd_es1371_mixer_spdif[] = {
1440 ES1371_SPDIF(SNDRV_CTL_NAME_IEC958("",PLAYBACK,SWITCH)),
1441 {
1442 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1443 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,DEFAULT),
1444 .info = snd_ens1373_spdif_info,
1445 .get = snd_ens1373_spdif_default_get,
1446 .put = snd_ens1373_spdif_default_put,
1447 },
1448 {
1449 .access = SNDRV_CTL_ELEM_ACCESS_READ,
1450 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1451 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,MASK),
1452 .info = snd_ens1373_spdif_info,
1453 .get = snd_ens1373_spdif_mask_get
1454 },
1455 {
1456 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1457 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,PCM_STREAM),
1458 .info = snd_ens1373_spdif_info,
1459 .get = snd_ens1373_spdif_stream_get,
1460 .put = snd_ens1373_spdif_stream_put
1461 },
1462};
1463
1464
1465#define snd_es1373_rear_info snd_ctl_boolean_mono_info
1466
1467static int snd_es1373_rear_get(struct snd_kcontrol *kcontrol,
1468 struct snd_ctl_elem_value *ucontrol)
1469{
1470 struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol);
1471 int val = 0;
1472
1473 spin_lock_irq(&ensoniq->reg_lock);
1474 if ((ensoniq->cssr & (ES_1373_REAR_BIT27|ES_1373_REAR_BIT26|
1475 ES_1373_REAR_BIT24)) == ES_1373_REAR_BIT26)
1476 val = 1;
1477 ucontrol->value.integer.value[0] = val;
1478 spin_unlock_irq(&ensoniq->reg_lock);
1479 return 0;
1480}
1481
1482static int snd_es1373_rear_put(struct snd_kcontrol *kcontrol,
1483 struct snd_ctl_elem_value *ucontrol)
1484{
1485 struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol);
1486 unsigned int nval1;
1487 int change;
1488
1489 nval1 = ucontrol->value.integer.value[0] ?
1490 ES_1373_REAR_BIT26 : (ES_1373_REAR_BIT27|ES_1373_REAR_BIT24);
1491 spin_lock_irq(&ensoniq->reg_lock);
1492 change = (ensoniq->cssr & (ES_1373_REAR_BIT27|
1493 ES_1373_REAR_BIT26|ES_1373_REAR_BIT24)) != nval1;
1494 ensoniq->cssr &= ~(ES_1373_REAR_BIT27|ES_1373_REAR_BIT26|ES_1373_REAR_BIT24);
1495 ensoniq->cssr |= nval1;
1496 outl(ensoniq->cssr, ES_REG(ensoniq, STATUS));
1497 spin_unlock_irq(&ensoniq->reg_lock);
1498 return change;
1499}
1500
1501static const struct snd_kcontrol_new snd_ens1373_rear =
1502{
1503 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
1504 .name = "AC97 2ch->4ch Copy Switch",
1505 .info = snd_es1373_rear_info,
1506 .get = snd_es1373_rear_get,
1507 .put = snd_es1373_rear_put,
1508};
1509
1510#define snd_es1373_line_info snd_ctl_boolean_mono_info
1511
1512static int snd_es1373_line_get(struct snd_kcontrol *kcontrol,
1513 struct snd_ctl_elem_value *ucontrol)
1514{
1515 struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol);
1516 int val = 0;
1517
1518 spin_lock_irq(&ensoniq->reg_lock);
1519 if (ensoniq->ctrl & ES_1371_GPIO_OUT(4))
1520 val = 1;
1521 ucontrol->value.integer.value[0] = val;
1522 spin_unlock_irq(&ensoniq->reg_lock);
1523 return 0;
1524}
1525
1526static int snd_es1373_line_put(struct snd_kcontrol *kcontrol,
1527 struct snd_ctl_elem_value *ucontrol)
1528{
1529 struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol);
1530 int changed;
1531 unsigned int ctrl;
1532
1533 spin_lock_irq(&ensoniq->reg_lock);
1534 ctrl = ensoniq->ctrl;
1535 if (ucontrol->value.integer.value[0])
1536 ensoniq->ctrl |= ES_1371_GPIO_OUT(4); /* switch line-in -> rear out */
1537 else
1538 ensoniq->ctrl &= ~ES_1371_GPIO_OUT(4);
1539 changed = (ctrl != ensoniq->ctrl);
1540 if (changed)
1541 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
1542 spin_unlock_irq(&ensoniq->reg_lock);
1543 return changed;
1544}
1545
1546static const struct snd_kcontrol_new snd_ens1373_line =
1547{
1548 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
1549 .name = "Line In->Rear Out Switch",
1550 .info = snd_es1373_line_info,
1551 .get = snd_es1373_line_get,
1552 .put = snd_es1373_line_put,
1553};
1554
1555static void snd_ensoniq_mixer_free_ac97(struct snd_ac97 *ac97)
1556{
1557 struct ensoniq *ensoniq = ac97->private_data;
1558 ensoniq->u.es1371.ac97 = NULL;
1559}
1560
1561struct es1371_quirk {
1562 unsigned short vid; /* vendor ID */
1563 unsigned short did; /* device ID */
1564 unsigned char rev; /* revision */
1565};
1566
1567static int es1371_quirk_lookup(struct ensoniq *ensoniq,
1568 const struct es1371_quirk *list)
1569{
1570 while (list->vid != (unsigned short)PCI_ANY_ID) {
1571 if (ensoniq->pci->vendor == list->vid &&
1572 ensoniq->pci->device == list->did &&
1573 ensoniq->rev == list->rev)
1574 return 1;
1575 list++;
1576 }
1577 return 0;
1578}
1579
1580static const struct es1371_quirk es1371_spdif_present[] = {
1581 { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_CT5880, .rev = CT5880REV_CT5880_C },
1582 { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_CT5880, .rev = CT5880REV_CT5880_D },
1583 { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_CT5880, .rev = CT5880REV_CT5880_E },
1584 { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_ES1371, .rev = ES1371REV_CT5880_A },
1585 { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_ES1371, .rev = ES1371REV_ES1373_8 },
1586 { .vid = PCI_ANY_ID, .did = PCI_ANY_ID }
1587};
1588
1589static const struct snd_pci_quirk ens1373_line_quirk[] = {
1590 SND_PCI_QUIRK_ID(0x1274, 0x2000), /* GA-7DXR */
1591 SND_PCI_QUIRK_ID(0x1458, 0xa000), /* GA-8IEXP */
1592 {0} /* end */
1593};
1594
1595static int snd_ensoniq_1371_mixer(struct ensoniq *ensoniq,
1596 int has_spdif, int has_line)
1597{
1598 struct snd_card *card = ensoniq->card;
1599 struct snd_ac97_bus *pbus;
1600 struct snd_ac97_template ac97;
1601 int err;
1602 static const struct snd_ac97_bus_ops ops = {
1603 .write = snd_es1371_codec_write,
1604 .read = snd_es1371_codec_read,
1605 .wait = snd_es1371_codec_wait,
1606 };
1607
1608 if ((err = snd_ac97_bus(card, 0, &ops, NULL, &pbus)) < 0)
1609 return err;
1610
1611 memset(&ac97, 0, sizeof(ac97));
1612 ac97.private_data = ensoniq;
1613 ac97.private_free = snd_ensoniq_mixer_free_ac97;
1614 ac97.pci = ensoniq->pci;
1615 ac97.scaps = AC97_SCAP_AUDIO;
1616 if ((err = snd_ac97_mixer(pbus, &ac97, &ensoniq->u.es1371.ac97)) < 0)
1617 return err;
1618 if (has_spdif > 0 ||
1619 (!has_spdif && es1371_quirk_lookup(ensoniq, es1371_spdif_present))) {
1620 struct snd_kcontrol *kctl;
1621 int i, is_spdif = 0;
1622
1623 ensoniq->spdif_default = ensoniq->spdif_stream =
1624 SNDRV_PCM_DEFAULT_CON_SPDIF;
1625 outl(ensoniq->spdif_default, ES_REG(ensoniq, CHANNEL_STATUS));
1626
1627 if (ensoniq->u.es1371.ac97->ext_id & AC97_EI_SPDIF)
1628 is_spdif++;
1629
1630 for (i = 0; i < ARRAY_SIZE(snd_es1371_mixer_spdif); i++) {
1631 kctl = snd_ctl_new1(&snd_es1371_mixer_spdif[i], ensoniq);
1632 if (!kctl)
1633 return -ENOMEM;
1634 kctl->id.index = is_spdif;
1635 err = snd_ctl_add(card, kctl);
1636 if (err < 0)
1637 return err;
1638 }
1639 }
1640 if (ensoniq->u.es1371.ac97->ext_id & AC97_EI_SDAC) {
1641 /* mirror rear to front speakers */
1642 ensoniq->cssr &= ~(ES_1373_REAR_BIT27|ES_1373_REAR_BIT24);
1643 ensoniq->cssr |= ES_1373_REAR_BIT26;
1644 err = snd_ctl_add(card, snd_ctl_new1(&snd_ens1373_rear, ensoniq));
1645 if (err < 0)
1646 return err;
1647 }
1648 if (has_line > 0 ||
1649 snd_pci_quirk_lookup(ensoniq->pci, ens1373_line_quirk)) {
1650 err = snd_ctl_add(card, snd_ctl_new1(&snd_ens1373_line,
1651 ensoniq));
1652 if (err < 0)
1653 return err;
1654 }
1655
1656 return 0;
1657}
1658
1659#endif /* CHIP1371 */
1660
1661/* generic control callbacks for ens1370 */
1662#ifdef CHIP1370
1663#define ENSONIQ_CONTROL(xname, mask) \
1664{ .iface = SNDRV_CTL_ELEM_IFACE_CARD, .name = xname, .info = snd_ensoniq_control_info, \
1665 .get = snd_ensoniq_control_get, .put = snd_ensoniq_control_put, \
1666 .private_value = mask }
1667
1668#define snd_ensoniq_control_info snd_ctl_boolean_mono_info
1669
1670static int snd_ensoniq_control_get(struct snd_kcontrol *kcontrol,
1671 struct snd_ctl_elem_value *ucontrol)
1672{
1673 struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol);
1674 int mask = kcontrol->private_value;
1675
1676 spin_lock_irq(&ensoniq->reg_lock);
1677 ucontrol->value.integer.value[0] = ensoniq->ctrl & mask ? 1 : 0;
1678 spin_unlock_irq(&ensoniq->reg_lock);
1679 return 0;
1680}
1681
1682static int snd_ensoniq_control_put(struct snd_kcontrol *kcontrol,
1683 struct snd_ctl_elem_value *ucontrol)
1684{
1685 struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol);
1686 int mask = kcontrol->private_value;
1687 unsigned int nval;
1688 int change;
1689
1690 nval = ucontrol->value.integer.value[0] ? mask : 0;
1691 spin_lock_irq(&ensoniq->reg_lock);
1692 change = (ensoniq->ctrl & mask) != nval;
1693 ensoniq->ctrl &= ~mask;
1694 ensoniq->ctrl |= nval;
1695 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
1696 spin_unlock_irq(&ensoniq->reg_lock);
1697 return change;
1698}
1699
1700/*
1701 * ENS1370 mixer
1702 */
1703
1704static const struct snd_kcontrol_new snd_es1370_controls[2] = {
1705ENSONIQ_CONTROL("PCM 0 Output also on Line-In Jack", ES_1370_XCTL0),
1706ENSONIQ_CONTROL("Mic +5V bias", ES_1370_XCTL1)
1707};
1708
1709#define ES1370_CONTROLS ARRAY_SIZE(snd_es1370_controls)
1710
1711static void snd_ensoniq_mixer_free_ak4531(struct snd_ak4531 *ak4531)
1712{
1713 struct ensoniq *ensoniq = ak4531->private_data;
1714 ensoniq->u.es1370.ak4531 = NULL;
1715}
1716
1717static int snd_ensoniq_1370_mixer(struct ensoniq *ensoniq)
1718{
1719 struct snd_card *card = ensoniq->card;
1720 struct snd_ak4531 ak4531;
1721 unsigned int idx;
1722 int err;
1723
1724 /* try reset AK4531 */
1725 outw(ES_1370_CODEC_WRITE(AK4531_RESET, 0x02), ES_REG(ensoniq, 1370_CODEC));
1726 inw(ES_REG(ensoniq, 1370_CODEC));
1727 udelay(100);
1728 outw(ES_1370_CODEC_WRITE(AK4531_RESET, 0x03), ES_REG(ensoniq, 1370_CODEC));
1729 inw(ES_REG(ensoniq, 1370_CODEC));
1730 udelay(100);
1731
1732 memset(&ak4531, 0, sizeof(ak4531));
1733 ak4531.write = snd_es1370_codec_write;
1734 ak4531.private_data = ensoniq;
1735 ak4531.private_free = snd_ensoniq_mixer_free_ak4531;
1736 if ((err = snd_ak4531_mixer(card, &ak4531, &ensoniq->u.es1370.ak4531)) < 0)
1737 return err;
1738 for (idx = 0; idx < ES1370_CONTROLS; idx++) {
1739 err = snd_ctl_add(card, snd_ctl_new1(&snd_es1370_controls[idx], ensoniq));
1740 if (err < 0)
1741 return err;
1742 }
1743 return 0;
1744}
1745
1746#endif /* CHIP1370 */
1747
1748#ifdef SUPPORT_JOYSTICK
1749
1750#ifdef CHIP1371
1751static int snd_ensoniq_get_joystick_port(struct ensoniq *ensoniq, int dev)
1752{
1753 switch (joystick_port[dev]) {
1754 case 0: /* disabled */
1755 case 1: /* auto-detect */
1756 case 0x200:
1757 case 0x208:
1758 case 0x210:
1759 case 0x218:
1760 return joystick_port[dev];
1761
1762 default:
1763 dev_err(ensoniq->card->dev,
1764 "invalid joystick port %#x", joystick_port[dev]);
1765 return 0;
1766 }
1767}
1768#else
1769static int snd_ensoniq_get_joystick_port(struct ensoniq *ensoniq, int dev)
1770{
1771 return joystick[dev] ? 0x200 : 0;
1772}
1773#endif
1774
1775static int snd_ensoniq_create_gameport(struct ensoniq *ensoniq, int dev)
1776{
1777 struct gameport *gp;
1778 int io_port;
1779
1780 io_port = snd_ensoniq_get_joystick_port(ensoniq, dev);
1781
1782 switch (io_port) {
1783 case 0:
1784 return -ENOSYS;
1785
1786 case 1: /* auto_detect */
1787 for (io_port = 0x200; io_port <= 0x218; io_port += 8)
1788 if (request_region(io_port, 8, "ens137x: gameport"))
1789 break;
1790 if (io_port > 0x218) {
1791 dev_warn(ensoniq->card->dev,
1792 "no gameport ports available\n");
1793 return -EBUSY;
1794 }
1795 break;
1796
1797 default:
1798 if (!request_region(io_port, 8, "ens137x: gameport")) {
1799 dev_warn(ensoniq->card->dev,
1800 "gameport io port %#x in use\n",
1801 io_port);
1802 return -EBUSY;
1803 }
1804 break;
1805 }
1806
1807 ensoniq->gameport = gp = gameport_allocate_port();
1808 if (!gp) {
1809 dev_err(ensoniq->card->dev,
1810 "cannot allocate memory for gameport\n");
1811 release_region(io_port, 8);
1812 return -ENOMEM;
1813 }
1814
1815 gameport_set_name(gp, "ES137x");
1816 gameport_set_phys(gp, "pci%s/gameport0", pci_name(ensoniq->pci));
1817 gameport_set_dev_parent(gp, &ensoniq->pci->dev);
1818 gp->io = io_port;
1819
1820 ensoniq->ctrl |= ES_JYSTK_EN;
1821#ifdef CHIP1371
1822 ensoniq->ctrl &= ~ES_1371_JOY_ASELM;
1823 ensoniq->ctrl |= ES_1371_JOY_ASEL((io_port - 0x200) / 8);
1824#endif
1825 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
1826
1827 gameport_register_port(ensoniq->gameport);
1828
1829 return 0;
1830}
1831
1832static void snd_ensoniq_free_gameport(struct ensoniq *ensoniq)
1833{
1834 if (ensoniq->gameport) {
1835 int port = ensoniq->gameport->io;
1836
1837 gameport_unregister_port(ensoniq->gameport);
1838 ensoniq->gameport = NULL;
1839 ensoniq->ctrl &= ~ES_JYSTK_EN;
1840 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
1841 release_region(port, 8);
1842 }
1843}
1844#else
1845static inline int snd_ensoniq_create_gameport(struct ensoniq *ensoniq, long port) { return -ENOSYS; }
1846static inline void snd_ensoniq_free_gameport(struct ensoniq *ensoniq) { }
1847#endif /* SUPPORT_JOYSTICK */
1848
1849/*
1850
1851 */
1852
1853static void snd_ensoniq_proc_read(struct snd_info_entry *entry,
1854 struct snd_info_buffer *buffer)
1855{
1856 struct ensoniq *ensoniq = entry->private_data;
1857
1858 snd_iprintf(buffer, "Ensoniq AudioPCI " CHIP_NAME "\n\n");
1859 snd_iprintf(buffer, "Joystick enable : %s\n",
1860 ensoniq->ctrl & ES_JYSTK_EN ? "on" : "off");
1861#ifdef CHIP1370
1862 snd_iprintf(buffer, "MIC +5V bias : %s\n",
1863 ensoniq->ctrl & ES_1370_XCTL1 ? "on" : "off");
1864 snd_iprintf(buffer, "Line In to AOUT : %s\n",
1865 ensoniq->ctrl & ES_1370_XCTL0 ? "on" : "off");
1866#else
1867 snd_iprintf(buffer, "Joystick port : 0x%x\n",
1868 (ES_1371_JOY_ASELI(ensoniq->ctrl) * 8) + 0x200);
1869#endif
1870}
1871
1872static void snd_ensoniq_proc_init(struct ensoniq *ensoniq)
1873{
1874 snd_card_ro_proc_new(ensoniq->card, "audiopci", ensoniq,
1875 snd_ensoniq_proc_read);
1876}
1877
1878/*
1879
1880 */
1881
1882static int snd_ensoniq_free(struct ensoniq *ensoniq)
1883{
1884 snd_ensoniq_free_gameport(ensoniq);
1885 if (ensoniq->irq < 0)
1886 goto __hw_end;
1887#ifdef CHIP1370
1888 outl(ES_1370_SERR_DISABLE, ES_REG(ensoniq, CONTROL)); /* switch everything off */
1889 outl(0, ES_REG(ensoniq, SERIAL)); /* clear serial interface */
1890#else
1891 outl(0, ES_REG(ensoniq, CONTROL)); /* switch everything off */
1892 outl(0, ES_REG(ensoniq, SERIAL)); /* clear serial interface */
1893#endif
1894 pci_set_power_state(ensoniq->pci, PCI_D3hot);
1895 __hw_end:
1896#ifdef CHIP1370
1897 if (ensoniq->dma_bug.area)
1898 snd_dma_free_pages(&ensoniq->dma_bug);
1899#endif
1900 if (ensoniq->irq >= 0)
1901 free_irq(ensoniq->irq, ensoniq);
1902 pci_release_regions(ensoniq->pci);
1903 pci_disable_device(ensoniq->pci);
1904 kfree(ensoniq);
1905 return 0;
1906}
1907
1908static int snd_ensoniq_dev_free(struct snd_device *device)
1909{
1910 struct ensoniq *ensoniq = device->device_data;
1911 return snd_ensoniq_free(ensoniq);
1912}
1913
1914#ifdef CHIP1371
1915static const struct snd_pci_quirk es1371_amplifier_hack[] = {
1916 SND_PCI_QUIRK_ID(0x107b, 0x2150), /* Gateway Solo 2150 */
1917 SND_PCI_QUIRK_ID(0x13bd, 0x100c), /* EV1938 on Mebius PC-MJ100V */
1918 SND_PCI_QUIRK_ID(0x1102, 0x5938), /* Targa Xtender300 */
1919 SND_PCI_QUIRK_ID(0x1102, 0x8938), /* IPC Topnote G notebook */
1920 {0} /* end */
1921};
1922
1923static const struct es1371_quirk es1371_ac97_reset_hack[] = {
1924 { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_CT5880, .rev = CT5880REV_CT5880_C },
1925 { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_CT5880, .rev = CT5880REV_CT5880_D },
1926 { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_CT5880, .rev = CT5880REV_CT5880_E },
1927 { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_ES1371, .rev = ES1371REV_CT5880_A },
1928 { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_ES1371, .rev = ES1371REV_ES1373_8 },
1929 { .vid = PCI_ANY_ID, .did = PCI_ANY_ID }
1930};
1931#endif
1932
1933static void snd_ensoniq_chip_init(struct ensoniq *ensoniq)
1934{
1935#ifdef CHIP1371
1936 int idx;
1937#endif
1938 /* this code was part of snd_ensoniq_create before intruduction
1939 * of suspend/resume
1940 */
1941#ifdef CHIP1370
1942 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
1943 outl(ensoniq->sctrl, ES_REG(ensoniq, SERIAL));
1944 outl(ES_MEM_PAGEO(ES_PAGE_ADC), ES_REG(ensoniq, MEM_PAGE));
1945 outl(ensoniq->dma_bug.addr, ES_REG(ensoniq, PHANTOM_FRAME));
1946 outl(0, ES_REG(ensoniq, PHANTOM_COUNT));
1947#else
1948 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
1949 outl(ensoniq->sctrl, ES_REG(ensoniq, SERIAL));
1950 outl(0, ES_REG(ensoniq, 1371_LEGACY));
1951 if (es1371_quirk_lookup(ensoniq, es1371_ac97_reset_hack)) {
1952 outl(ensoniq->cssr, ES_REG(ensoniq, STATUS));
1953 /* need to delay around 20ms(bleech) to give
1954 some CODECs enough time to wakeup */
1955 msleep(20);
1956 }
1957 /* AC'97 warm reset to start the bitclk */
1958 outl(ensoniq->ctrl | ES_1371_SYNC_RES, ES_REG(ensoniq, CONTROL));
1959 inl(ES_REG(ensoniq, CONTROL));
1960 udelay(20);
1961 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
1962 /* Init the sample rate converter */
1963 snd_es1371_wait_src_ready(ensoniq);
1964 outl(ES_1371_SRC_DISABLE, ES_REG(ensoniq, 1371_SMPRATE));
1965 for (idx = 0; idx < 0x80; idx++)
1966 snd_es1371_src_write(ensoniq, idx, 0);
1967 snd_es1371_src_write(ensoniq, ES_SMPREG_DAC1 + ES_SMPREG_TRUNC_N, 16 << 4);
1968 snd_es1371_src_write(ensoniq, ES_SMPREG_DAC1 + ES_SMPREG_INT_REGS, 16 << 10);
1969 snd_es1371_src_write(ensoniq, ES_SMPREG_DAC2 + ES_SMPREG_TRUNC_N, 16 << 4);
1970 snd_es1371_src_write(ensoniq, ES_SMPREG_DAC2 + ES_SMPREG_INT_REGS, 16 << 10);
1971 snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_ADC, 1 << 12);
1972 snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_ADC + 1, 1 << 12);
1973 snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_DAC1, 1 << 12);
1974 snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_DAC1 + 1, 1 << 12);
1975 snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_DAC2, 1 << 12);
1976 snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_DAC2 + 1, 1 << 12);
1977 snd_es1371_adc_rate(ensoniq, 22050);
1978 snd_es1371_dac1_rate(ensoniq, 22050);
1979 snd_es1371_dac2_rate(ensoniq, 22050);
1980 /* WARNING:
1981 * enabling the sample rate converter without properly programming
1982 * its parameters causes the chip to lock up (the SRC busy bit will
1983 * be stuck high, and I've found no way to rectify this other than
1984 * power cycle) - Thomas Sailer
1985 */
1986 snd_es1371_wait_src_ready(ensoniq);
1987 outl(0, ES_REG(ensoniq, 1371_SMPRATE));
1988 /* try reset codec directly */
1989 outl(ES_1371_CODEC_WRITE(0, 0), ES_REG(ensoniq, 1371_CODEC));
1990#endif
1991 outb(ensoniq->uartc = 0x00, ES_REG(ensoniq, UART_CONTROL));
1992 outb(0x00, ES_REG(ensoniq, UART_RES));
1993 outl(ensoniq->cssr, ES_REG(ensoniq, STATUS));
1994}
1995
1996#ifdef CONFIG_PM_SLEEP
1997static int snd_ensoniq_suspend(struct device *dev)
1998{
1999 struct snd_card *card = dev_get_drvdata(dev);
2000 struct ensoniq *ensoniq = card->private_data;
2001
2002 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
2003
2004#ifdef CHIP1371
2005 snd_ac97_suspend(ensoniq->u.es1371.ac97);
2006#else
2007 /* try to reset AK4531 */
2008 outw(ES_1370_CODEC_WRITE(AK4531_RESET, 0x02), ES_REG(ensoniq, 1370_CODEC));
2009 inw(ES_REG(ensoniq, 1370_CODEC));
2010 udelay(100);
2011 outw(ES_1370_CODEC_WRITE(AK4531_RESET, 0x03), ES_REG(ensoniq, 1370_CODEC));
2012 inw(ES_REG(ensoniq, 1370_CODEC));
2013 udelay(100);
2014 snd_ak4531_suspend(ensoniq->u.es1370.ak4531);
2015#endif
2016 return 0;
2017}
2018
2019static int snd_ensoniq_resume(struct device *dev)
2020{
2021 struct snd_card *card = dev_get_drvdata(dev);
2022 struct ensoniq *ensoniq = card->private_data;
2023
2024 snd_ensoniq_chip_init(ensoniq);
2025
2026#ifdef CHIP1371
2027 snd_ac97_resume(ensoniq->u.es1371.ac97);
2028#else
2029 snd_ak4531_resume(ensoniq->u.es1370.ak4531);
2030#endif
2031 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
2032 return 0;
2033}
2034
2035static SIMPLE_DEV_PM_OPS(snd_ensoniq_pm, snd_ensoniq_suspend, snd_ensoniq_resume);
2036#define SND_ENSONIQ_PM_OPS &snd_ensoniq_pm
2037#else
2038#define SND_ENSONIQ_PM_OPS NULL
2039#endif /* CONFIG_PM_SLEEP */
2040
2041static int snd_ensoniq_create(struct snd_card *card,
2042 struct pci_dev *pci,
2043 struct ensoniq **rensoniq)
2044{
2045 struct ensoniq *ensoniq;
2046 int err;
2047 static const struct snd_device_ops ops = {
2048 .dev_free = snd_ensoniq_dev_free,
2049 };
2050
2051 *rensoniq = NULL;
2052 if ((err = pci_enable_device(pci)) < 0)
2053 return err;
2054 ensoniq = kzalloc(sizeof(*ensoniq), GFP_KERNEL);
2055 if (ensoniq == NULL) {
2056 pci_disable_device(pci);
2057 return -ENOMEM;
2058 }
2059 spin_lock_init(&ensoniq->reg_lock);
2060 mutex_init(&ensoniq->src_mutex);
2061 ensoniq->card = card;
2062 ensoniq->pci = pci;
2063 ensoniq->irq = -1;
2064 if ((err = pci_request_regions(pci, "Ensoniq AudioPCI")) < 0) {
2065 kfree(ensoniq);
2066 pci_disable_device(pci);
2067 return err;
2068 }
2069 ensoniq->port = pci_resource_start(pci, 0);
2070 if (request_irq(pci->irq, snd_audiopci_interrupt, IRQF_SHARED,
2071 KBUILD_MODNAME, ensoniq)) {
2072 dev_err(card->dev, "unable to grab IRQ %d\n", pci->irq);
2073 snd_ensoniq_free(ensoniq);
2074 return -EBUSY;
2075 }
2076 ensoniq->irq = pci->irq;
2077 card->sync_irq = ensoniq->irq;
2078#ifdef CHIP1370
2079 if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, &pci->dev,
2080 16, &ensoniq->dma_bug) < 0) {
2081 dev_err(card->dev, "unable to allocate space for phantom area - dma_bug\n");
2082 snd_ensoniq_free(ensoniq);
2083 return -EBUSY;
2084 }
2085#endif
2086 pci_set_master(pci);
2087#ifndef TARGET_OS2
2088 ensoniq->rev = pci->revision;
2089#else
2090 ensoniq->rev = snd_pci_revision(pci);
2091#endif
2092#ifdef CHIP1370
2093#if 0
2094 ensoniq->ctrl = ES_1370_CDC_EN | ES_1370_SERR_DISABLE |
2095 ES_1370_PCLKDIVO(ES_1370_SRTODIV(8000));
2096#else /* get microphone working */
2097 ensoniq->ctrl = ES_1370_CDC_EN | ES_1370_PCLKDIVO(ES_1370_SRTODIV(8000));
2098#endif
2099 ensoniq->sctrl = 0;
2100#else
2101 ensoniq->ctrl = 0;
2102 ensoniq->sctrl = 0;
2103 ensoniq->cssr = 0;
2104 if (snd_pci_quirk_lookup(pci, es1371_amplifier_hack))
2105 ensoniq->ctrl |= ES_1371_GPIO_OUT(1); /* turn amplifier on */
2106
2107 if (es1371_quirk_lookup(ensoniq, es1371_ac97_reset_hack))
2108 ensoniq->cssr |= ES_1371_ST_AC97_RST;
2109#endif
2110
2111 snd_ensoniq_chip_init(ensoniq);
2112
2113 if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, ensoniq, &ops)) < 0) {
2114 snd_ensoniq_free(ensoniq);
2115 return err;
2116 }
2117
2118 snd_ensoniq_proc_init(ensoniq);
2119
2120 *rensoniq = ensoniq;
2121 return 0;
2122}
2123
2124/*
2125 * MIDI section
2126 */
2127
2128static void snd_ensoniq_midi_interrupt(struct ensoniq * ensoniq)
2129{
2130 struct snd_rawmidi *rmidi = ensoniq->rmidi;
2131 unsigned char status, mask, byte;
2132
2133 if (rmidi == NULL)
2134 return;
2135 /* do Rx at first */
2136 spin_lock(&ensoniq->reg_lock);
2137 mask = ensoniq->uartm & ES_MODE_INPUT ? ES_RXRDY : 0;
2138 while (mask) {
2139 status = inb(ES_REG(ensoniq, UART_STATUS));
2140 if ((status & mask) == 0)
2141 break;
2142 byte = inb(ES_REG(ensoniq, UART_DATA));
2143 snd_rawmidi_receive(ensoniq->midi_input, &byte, 1);
2144 }
2145 spin_unlock(&ensoniq->reg_lock);
2146
2147 /* do Tx at second */
2148 spin_lock(&ensoniq->reg_lock);
2149 mask = ensoniq->uartm & ES_MODE_OUTPUT ? ES_TXRDY : 0;
2150 while (mask) {
2151 status = inb(ES_REG(ensoniq, UART_STATUS));
2152 if ((status & mask) == 0)
2153 break;
2154 if (snd_rawmidi_transmit(ensoniq->midi_output, &byte, 1) != 1) {
2155 ensoniq->uartc &= ~ES_TXINTENM;
2156 outb(ensoniq->uartc, ES_REG(ensoniq, UART_CONTROL));
2157 mask &= ~ES_TXRDY;
2158 } else {
2159 outb(byte, ES_REG(ensoniq, UART_DATA));
2160 }
2161 }
2162 spin_unlock(&ensoniq->reg_lock);
2163}
2164
2165static int snd_ensoniq_midi_input_open(struct snd_rawmidi_substream *substream)
2166{
2167 struct ensoniq *ensoniq = substream->rmidi->private_data;
2168
2169 spin_lock_irq(&ensoniq->reg_lock);
2170 ensoniq->uartm |= ES_MODE_INPUT;
2171 ensoniq->midi_input = substream;
2172 if (!(ensoniq->uartm & ES_MODE_OUTPUT)) {
2173 outb(ES_CNTRL(3), ES_REG(ensoniq, UART_CONTROL));
2174 outb(ensoniq->uartc = 0, ES_REG(ensoniq, UART_CONTROL));
2175 outl(ensoniq->ctrl |= ES_UART_EN, ES_REG(ensoniq, CONTROL));
2176 }
2177 spin_unlock_irq(&ensoniq->reg_lock);
2178 return 0;
2179}
2180
2181static int snd_ensoniq_midi_input_close(struct snd_rawmidi_substream *substream)
2182{
2183 struct ensoniq *ensoniq = substream->rmidi->private_data;
2184
2185 spin_lock_irq(&ensoniq->reg_lock);
2186 if (!(ensoniq->uartm & ES_MODE_OUTPUT)) {
2187 outb(ensoniq->uartc = 0, ES_REG(ensoniq, UART_CONTROL));
2188 outl(ensoniq->ctrl &= ~ES_UART_EN, ES_REG(ensoniq, CONTROL));
2189 } else {
2190 outb(ensoniq->uartc &= ~ES_RXINTEN, ES_REG(ensoniq, UART_CONTROL));
2191 }
2192 ensoniq->midi_input = NULL;
2193 ensoniq->uartm &= ~ES_MODE_INPUT;
2194 spin_unlock_irq(&ensoniq->reg_lock);
2195 return 0;
2196}
2197
2198static int snd_ensoniq_midi_output_open(struct snd_rawmidi_substream *substream)
2199{
2200 struct ensoniq *ensoniq = substream->rmidi->private_data;
2201
2202 spin_lock_irq(&ensoniq->reg_lock);
2203 ensoniq->uartm |= ES_MODE_OUTPUT;
2204 ensoniq->midi_output = substream;
2205 if (!(ensoniq->uartm & ES_MODE_INPUT)) {
2206 outb(ES_CNTRL(3), ES_REG(ensoniq, UART_CONTROL));
2207 outb(ensoniq->uartc = 0, ES_REG(ensoniq, UART_CONTROL));
2208 outl(ensoniq->ctrl |= ES_UART_EN, ES_REG(ensoniq, CONTROL));
2209 }
2210 spin_unlock_irq(&ensoniq->reg_lock);
2211 return 0;
2212}
2213
2214static int snd_ensoniq_midi_output_close(struct snd_rawmidi_substream *substream)
2215{
2216 struct ensoniq *ensoniq = substream->rmidi->private_data;
2217
2218 spin_lock_irq(&ensoniq->reg_lock);
2219 if (!(ensoniq->uartm & ES_MODE_INPUT)) {
2220 outb(ensoniq->uartc = 0, ES_REG(ensoniq, UART_CONTROL));
2221 outl(ensoniq->ctrl &= ~ES_UART_EN, ES_REG(ensoniq, CONTROL));
2222 } else {
2223 outb(ensoniq->uartc &= ~ES_TXINTENM, ES_REG(ensoniq, UART_CONTROL));
2224 }
2225 ensoniq->midi_output = NULL;
2226 ensoniq->uartm &= ~ES_MODE_OUTPUT;
2227 spin_unlock_irq(&ensoniq->reg_lock);
2228 return 0;
2229}
2230
2231static void snd_ensoniq_midi_input_trigger(struct snd_rawmidi_substream *substream, int up)
2232{
2233 unsigned long flags;
2234 struct ensoniq *ensoniq = substream->rmidi->private_data;
2235 int idx;
2236
2237 spin_lock_irqsave(&ensoniq->reg_lock, flags);
2238 if (up) {
2239 if ((ensoniq->uartc & ES_RXINTEN) == 0) {
2240 /* empty input FIFO */
2241 for (idx = 0; idx < 32; idx++)
2242 inb(ES_REG(ensoniq, UART_DATA));
2243 ensoniq->uartc |= ES_RXINTEN;
2244 outb(ensoniq->uartc, ES_REG(ensoniq, UART_CONTROL));
2245 }
2246 } else {
2247 if (ensoniq->uartc & ES_RXINTEN) {
2248 ensoniq->uartc &= ~ES_RXINTEN;
2249 outb(ensoniq->uartc, ES_REG(ensoniq, UART_CONTROL));
2250 }
2251 }
2252 spin_unlock_irqrestore(&ensoniq->reg_lock, flags);
2253}
2254
2255static void snd_ensoniq_midi_output_trigger(struct snd_rawmidi_substream *substream, int up)
2256{
2257 unsigned long flags;
2258 struct ensoniq *ensoniq = substream->rmidi->private_data;
2259 unsigned char byte;
2260
2261 spin_lock_irqsave(&ensoniq->reg_lock, flags);
2262 if (up) {
2263 if (ES_TXINTENI(ensoniq->uartc) == 0) {
2264 ensoniq->uartc |= ES_TXINTENO(1);
2265 /* fill UART FIFO buffer at first, and turn Tx interrupts only if necessary */
2266 while (ES_TXINTENI(ensoniq->uartc) == 1 &&
2267 (inb(ES_REG(ensoniq, UART_STATUS)) & ES_TXRDY)) {
2268 if (snd_rawmidi_transmit(substream, &byte, 1) != 1) {
2269 ensoniq->uartc &= ~ES_TXINTENM;
2270 } else {
2271 outb(byte, ES_REG(ensoniq, UART_DATA));
2272 }
2273 }
2274 outb(ensoniq->uartc, ES_REG(ensoniq, UART_CONTROL));
2275 }
2276 } else {
2277 if (ES_TXINTENI(ensoniq->uartc) == 1) {
2278 ensoniq->uartc &= ~ES_TXINTENM;
2279 outb(ensoniq->uartc, ES_REG(ensoniq, UART_CONTROL));
2280 }
2281 }
2282 spin_unlock_irqrestore(&ensoniq->reg_lock, flags);
2283}
2284
2285static const struct snd_rawmidi_ops snd_ensoniq_midi_output =
2286{
2287 .open = snd_ensoniq_midi_output_open,
2288 .close = snd_ensoniq_midi_output_close,
2289 .trigger = snd_ensoniq_midi_output_trigger,
2290};
2291
2292static const struct snd_rawmidi_ops snd_ensoniq_midi_input =
2293{
2294 .open = snd_ensoniq_midi_input_open,
2295 .close = snd_ensoniq_midi_input_close,
2296 .trigger = snd_ensoniq_midi_input_trigger,
2297};
2298
2299static int snd_ensoniq_midi(struct ensoniq *ensoniq, int device)
2300{
2301 struct snd_rawmidi *rmidi;
2302 int err;
2303
2304 if ((err = snd_rawmidi_new(ensoniq->card, "ES1370/1", device, 1, 1, &rmidi)) < 0)
2305 return err;
2306 strcpy(rmidi->name, CHIP_NAME);
2307 snd_rawmidi_set_ops(rmidi, SNDRV_RAWMIDI_STREAM_OUTPUT, &snd_ensoniq_midi_output);
2308 snd_rawmidi_set_ops(rmidi, SNDRV_RAWMIDI_STREAM_INPUT, &snd_ensoniq_midi_input);
2309 rmidi->info_flags |= SNDRV_RAWMIDI_INFO_OUTPUT | SNDRV_RAWMIDI_INFO_INPUT |
2310 SNDRV_RAWMIDI_INFO_DUPLEX;
2311 rmidi->private_data = ensoniq;
2312 ensoniq->rmidi = rmidi;
2313 return 0;
2314}
2315
2316/*
2317 * Interrupt handler
2318 */
2319
2320static irqreturn_t snd_audiopci_interrupt(int irq, void *dev_id)
2321{
2322 struct ensoniq *ensoniq = dev_id;
2323 unsigned int status, sctrl;
2324
2325 if (ensoniq == NULL)
2326 return IRQ_NONE;
2327
2328 status = inl(ES_REG(ensoniq, STATUS));
2329 if (!(status & ES_INTR))
2330 return IRQ_NONE;
2331
2332 spin_lock(&ensoniq->reg_lock);
2333 sctrl = ensoniq->sctrl;
2334 if (status & ES_DAC1)
2335 sctrl &= ~ES_P1_INT_EN;
2336 if (status & ES_DAC2)
2337 sctrl &= ~ES_P2_INT_EN;
2338 if (status & ES_ADC)
2339 sctrl &= ~ES_R1_INT_EN;
2340 outl(sctrl, ES_REG(ensoniq, SERIAL));
2341 outl(ensoniq->sctrl, ES_REG(ensoniq, SERIAL));
2342 spin_unlock(&ensoniq->reg_lock);
2343
2344 if (status & ES_UART)
2345 snd_ensoniq_midi_interrupt(ensoniq);
2346 if ((status & ES_DAC2) && ensoniq->playback2_substream)
2347 snd_pcm_period_elapsed(ensoniq->playback2_substream);
2348 if ((status & ES_ADC) && ensoniq->capture_substream)
2349 snd_pcm_period_elapsed(ensoniq->capture_substream);
2350 if ((status & ES_DAC1) && ensoniq->playback1_substream)
2351 snd_pcm_period_elapsed(ensoniq->playback1_substream);
2352 return IRQ_HANDLED;
2353}
2354
2355static int snd_audiopci_probe(struct pci_dev *pci,
2356 const struct pci_device_id *pci_id)
2357{
2358 static int dev;
2359 struct snd_card *card;
2360 struct ensoniq *ensoniq;
2361 int err;
2362
2363 if (dev >= SNDRV_CARDS)
2364 return -ENODEV;
2365 if (!enable[dev]) {
2366 dev++;
2367 return -ENOENT;
2368 }
2369
2370 err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE,
2371 0, &card);
2372 if (err < 0)
2373 return err;
2374
2375 if ((err = snd_ensoniq_create(card, pci, &ensoniq)) < 0) {
2376 snd_card_free(card);
2377 return err;
2378 }
2379 card->private_data = ensoniq;
2380
2381#ifdef CHIP1370
2382 if ((err = snd_ensoniq_1370_mixer(ensoniq)) < 0) {
2383 snd_card_free(card);
2384 return err;
2385 }
2386#endif
2387#ifdef CHIP1371
2388 if ((err = snd_ensoniq_1371_mixer(ensoniq, spdif[dev], lineio[dev])) < 0) {
2389 snd_card_free(card);
2390 return err;
2391 }
2392#endif
2393 if ((err = snd_ensoniq_pcm(ensoniq, 0)) < 0) {
2394 snd_card_free(card);
2395 return err;
2396 }
2397 if ((err = snd_ensoniq_pcm2(ensoniq, 1)) < 0) {
2398 snd_card_free(card);
2399 return err;
2400 }
2401 if ((err = snd_ensoniq_midi(ensoniq, 0)) < 0) {
2402 snd_card_free(card);
2403 return err;
2404 }
2405
2406 snd_ensoniq_create_gameport(ensoniq, dev);
2407
2408 strcpy(card->driver, DRIVER_NAME);
2409
2410 strcpy(card->shortname, "Ensoniq AudioPCI");
2411 sprintf(card->longname, "%s %s at 0x%lx, irq %i",
2412 card->shortname,
2413 card->driver,
2414 ensoniq->port,
2415 ensoniq->irq);
2416
2417 if ((err = snd_card_register(card)) < 0) {
2418 snd_card_free(card);
2419 return err;
2420 }
2421
2422 pci_set_drvdata(pci, card);
2423 dev++;
2424 return 0;
2425}
2426
2427static void snd_audiopci_remove(struct pci_dev *pci)
2428{
2429 snd_card_free(pci_get_drvdata(pci));
2430}
2431
2432static struct pci_driver ens137x_driver = {
2433 .name = KBUILD_MODNAME,
2434 .id_table = snd_audiopci_ids,
2435 .probe = snd_audiopci_probe,
2436 .remove = snd_audiopci_remove,
2437 .driver = {
2438 .pm = SND_ENSONIQ_PM_OPS,
2439 },
2440};
2441
2442module_pci_driver(ens137x_driver);
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